Semiconductor devices and methods

Abstract

The present disclosure relates to semiconductor devices and methods. Methods for improving the profile of a channel region in a semiconductor device and semiconductor devices formed by these methods are disclosed. In one embodiment, a method includes forming a semiconductor fin over a semiconductor substrate, the semiconductor fin including germanium, a first portion of the semiconductor fin having a greater germanium concentration than a second portion of the semiconductor fin, a first distance between the first portion and a major surface of the semiconductor substrate being less than a second distance between the second portion and the major surface of the semiconductor substrate; and trimming the semiconductor fin, the first portion of the semiconductor fin being trimmed at a greater rate than the second portion of the semiconductor fin.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to semiconductor devices and methods. BACKGROUND

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductive layers of materials on a semiconductor substrate and patterning the various material layers using photolithography to form circuit components and elements thereon.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continually reducing the size of the minimum feature size. This improvement in integration density has increased the performance and lower cost of electronic devices. SUMMARY

[0004] According to one embodiment of the present disclosure, a method of forming a semiconductor device is provided, including forming a semiconductor fin over a semiconductor substrate, the semiconductor fin including germanium, wherein a germanium concentration of a first portion of the semiconductor fin is greater than a germanium concentration of a second portion of the semiconductor fin, a first distance between the first portion and a major surface of the semiconductor substrate is less than a second distance between the second portion and the major surface of the semiconductor substrate; and trimming the semiconductor fin, wherein the first portion of the semiconductor fin is trimmed at a greater rate than the second portion of the semiconductor fin.

[0005] According to another embodiment of the present disclosure, a semiconductor device is provided, including a semiconductor substrate; a first semiconductor fin over the semiconductor substrate, the first semiconductor fin including silicon germanium, a germanium concentration of the first semiconductor fin decreasing as a distance from the semiconductor substrate increases; a second semiconductor fin over the semiconductor substrate, the second semiconductor fin including silicon, wherein a first angle between a sidewall of the first semiconductor fin and a major surface of the semiconductor substrate is closer to perpendicular than a second angle between a sidewall of the second semiconductor fin and the major surface of the semiconductor substrate; a gate stack over the first semiconductor fin; and a source / drain region at least partially in the first semiconductor fin adjacent to the gate stack.

[0006] According to yet another embodiment of the present disclosure, a semiconductor device is provided, comprising: a first channel region over a semiconductor substrate, the first channel region comprising silicon germanium, the first channel region having a first width; a second channel region over the first channel region, the second channel region comprising silicon germanium, the second channel region having a lower germanium concentration than the first channel region, the second channel region having a second width; a third channel region over the semiconductor substrate, the third channel region comprising silicon, the third channel region having a third width; a fourth channel region over the third channel region, the fourth channel region comprising silicon, the fourth channel region having a fourth width, wherein a difference between the first width and the second width is less than a difference between the third width and the fourth width; and a gate stack surrounding the first channel region and the second channel region. BRIEF DESCRIPTION OF DRAWINGS

[0007] Various aspects of the present disclosure can be best understood with reference to the following specific examples when considered in connection with the accompanying drawings. It should be noted that various features are not drawn to scale. In fact, the dimensions of the various features can be arbitrarily increased or decreased for the sake of discussion.

[0008] FIG. 1 An example of a semiconductor device including a fin field effect transistor (FinFET) in a three-dimensional view is shown in accordance with some embodiments.

[0009] FIG. 2 , FIG. 3A , FIG. 3B , FIG. 3C , FIG. 4A , FIG. 4B , FIG. 5 , FIG. 6A , FIG. 6B , FIG. 7A , FIG. 7B , FIG. 8A , FIG. 8B , FIG. 9A , FIG. 9B , FIG. 10A , FIG. 10B , FIG. 10C , FIG. 11A , FIG. 11B , FIG. 12A , FIG. 12B , FIG. 13A , FIG. 13B , FIG. 13C , FIG. 13D , FIG. 13E , FIG. 14A , FIG. 14B , FIG. 14C , FIG. 15A ,FIG. 15B 、 FIG. 16A 、 FIG. 16B 、 FIG. 16C 、 FIG. 16D and FIG. 16E are cross-sectional views of intermediate stages of fabricating a semiconductor device according to some embodiments.

[0010] FIG. 17 An example of a semiconductor device including a nanostructure field effect transistor (NSFET) is shown in a three-dimensional view according to some embodiments.

[0011] FIG. 18 、 FIG. 19A 、 FIG. 19B 、 FIG. 20A 、 FIG. 20B 、 FIG. 21 、 FIG. 22A 、 FIG. 22B 、 FIG. 23A 、 FIG. 23B 、 FIG. 24A 、 FIG. 24B 、 FIG. 25A 、 FIG. 25B 、 FIG. 26A 、 FIG. 26B 、 FIG. 26C 、 FIG. 27A 、 FIG. 27B 、 FIG. 27C 、 FIG. 28A 、 FIG. 28B 、 FIG. 28C 、 FIG. 28D 、 FIG. 29A 、 FIG. 29B 、 FIG. 29C 、 FIG. 30A 、 FIG. 30B 、 FIG. 30C 、 FIG. 31A 、 FIG. 31B 、 FIG. 31C 、 FIG. 31D 、 FIG. 31E 、 FIG. 32A 、 FIG. 32B 、 FIG. 32C 、 FIG. 32D 、 FIG. 33A 、 FIG. 33B 、 FIG. 33C 、 FIG. 33D 、 FIG. 33E 、 FIG. 33F 、 FIG. 34A 、 FIG. 34B 、 FIG. 35A 、Figure FIG. 35B 、 FIG. 35C and FIG. 35D are cross-sectional views of intermediate stages of fabricating a semiconductor device according to some embodiments. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments, or examples, for implementing different characteristics of the application. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on a second feature can include embodiments in which the first feature is formed in direct contact with the second feature, and can also include embodiments in which additional features can be formed between the first feature and the second feature such that the first feature can not be in direct contact with the second feature. Furthermore, the present disclosure can repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0013] In addition, spatially relative terms (e.g., "beneath," "below," "lower," "above," "upper," and the like) can be used herein for ease of describing one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Such spatially relative terms can be intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0014] Various embodiments provide methods of forming a channel region with an improved profile in a semiconductor device, and semiconductor devices formed by the methods. The methods can include forming a channel region of a semiconductor material having a gradient concentration, and thinning the channel region. In some embodiments, the channel region can be formed of silicon germanium having a higher germanium concentration at a bottom of the channel region and a lower germanium concentration at a top of the channel region. The channel region can be thinned by exposing the channel region to an alkaline or acidic solution, which can be combined with or circulated with an oxidizing agent solution. Portions of the channel region having the higher germanium concentration can be thinned at a higher rate than portions of the channel region having the lower germanium concentration, which can be used to provide a channel region having a rectangular profile. Providing a channel region with a more rectangular profile reduces drain induced barrier lowering (DIBL), improves performance, and reduces device defects of the resulting semiconductor device.

[0015] FIG. 1An example of a FinFET is shown in accordance with some embodiments. The FinFET includes a fin 55 on a substrate 50 (e.g., a semiconductor substrate). Shallow trench isolation (STI) regions 58 are disposed in the substrate 50, and the fin 55 protrudes above and between adjacent STI regions 58. Although the STI regions 58 are depicted / illustrated as being separate from the substrate 50, as used herein, the term "substrate" can be used to refer to a semiconductor substrate alone or a semiconductor substrate including STI regions. Additionally, although the fin 55 is shown as a single continuous material with the substrate 50, the fin 55 and / or the substrate 50 can include a single material or multiple materials. In this context, the fin 55 refers to the portion that extends between adjacent STI regions 58.

[0016] A gate dielectric layer 100 is along the sidewalls and over the top surface of the fin 55, and a gate electrode 102 is over the gate dielectric layer 100. Epitaxial source / drain regions 92 are disposed opposite the fin 55, the gate dielectric layer 100, and the gate electrode 102. FIG. 1 Further shown are reference cross-sections used in later figures. Cross-section A-A' is along the longitudinal axis of the gate electrode 102, and in a direction perpendicular to, for example, the direction of current flow between the epitaxial source / drain regions 92 of the FinFET. Cross-section B-B' is perpendicular to cross-section A-A', and along the longitudinal axis of the fin 55 and in the direction of current flow between, for example, the epitaxial source / drain regions 92 of the FinFET. Cross-section C-C' is parallel to cross-section A-A', and extends through the epitaxial source / drain regions 92 of the FinFET. For clarity, the subsequent figures refer to these reference cross-sections.

[0017] Some embodiments discussed herein are discussed in the context of fin field effect transistors (FinFETs) and nanostructure (e.g., nanosheet, nanowire, wraparound gate, etc.) field effect transistors (NSFETs) formed using a gate-last process. In some embodiments, a gate-first process can be used. Additionally, some embodiments consider aspects used in planar devices, etc.

[0018] FIG. 2 to FIG. 16B is a cross-sectional view of an intermediate stage of manufacturing a FinFET in accordance with some embodiments. FIG. 2 、 FIG. 3A 、 FIG. 3B 、 FIG. 3C 、 FIG. 4A 、 FIG. 4B 、 FIG. 5 、 FIG. 13C 、 FIG. 16C 、 FIG. 16D and FIG. 16E shows FIG. 1 the reference cross-section A-A' shown in FIG. 1, including region 50N and region 50P. FIG. 6A、 FIG. 11A 、 FIG. 12A 、 FIG. 13A 、 FIG. 14A 、 FIG. 15A and FIG. 16A are shown along a reference cross-section A-A' in region 50N or region 50P, as indicated. FIG. 1 、 FIG. 6B 、 FIG. 7B 、 FIG. 8B 、 FIG. 9B 、 FIG. 10B 、 FIG. 11B 、 FIG. 12B 、 FIG. 13B 、 FIG. 13D 、 FIG. 13E 、 FIG. 14B 、 FIG. 14C 、 FIG. 15B and FIG. 16B are shown along a similar cross-section B-B', as indicated. FIG. 1 、 FIG. 7A 、 FIG. 8A 、 FIG. 9A and FIG. 10A are shown along a reference cross-section C-C', as indicated. FIG. 10C 、 FIG. 1 In

[0019] In FIG. 2 , a substrate 50 is provided. Substrate 50 can be a semiconductor substrate, e.g., a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which can be doped (e.g., with p-type or n-type dopants) or undoped. Substrate 50 can be a wafer, e.g., a silicon wafer. In general, an SOI substrate is a layer of semiconductor material formed on an insulator layer. The insulator layer can be, e.g., a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is disposed on a substrate, which is typically a silicon or glass substrate. Other substrates can also be used, e.g., a multilayer substrate or a graded substrate. In some embodiments, the semiconductor material of substrate 50 can include silicon; germanium; a compound semiconductor, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium antimonide; or a combination thereof.

[0020] Substrate 50 has a region 50N and a region 50P. Region 50N can be used to form n-type devices, e.g., NMOS transistors, such as n-type FinFETs. Region 50P can be used to form p-type devices, e.g., PMOS transistors, such as p-type FinFETs. Region 50N can be physically separated from region 50P (as shown by partition 51), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be disposed between region 50N and region 50P.

[0021] Further in FIG. 2 region 50P. A patterned mask (not shown separately), e.g., a patterned photoresist, can be formed over region 50N. The patterned photoresist can be formed by depositing a photoresist layer over substrate 50 using spin coating or the like, and then patterning the photoresist layer by exposing the photoresist layer to a patterning energy source, e.g., a patterning light source, and developing the photoresist layer to remove either the exposed or unexposed portions of the photoresist layer, thereby forming the patterned photoresist. Substrate 50 in region 50P is then etched using a suitable etching process, such as an anisotropic etching process, e.g., a dry etching process, to form the first opening. The patterned photoresist can then be removed.

[0022] The first epitaxial semiconductor material 52 is then formed to fill the first opening. The first epitaxial semiconductor material 52 can be deposited by an epitaxial growth process, e.g., chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or the like. The first epitaxial semiconductor material 52 can include a semiconductor material such as silicon germanium or the like.

[0023] The first epitaxial semiconductor material 52 can be formed with a graded germanium concentration. For example, in some embodiments, the germanium concentration of the first epitaxial semiconductor material 52 can gradually and continuously increase from a top surface of the first epitaxial semiconductor material 52 to a bottom surface of the first epitaxial semiconductor material 52. In some embodiments, the percentage of germanium atoms in the first epitaxial semiconductor material 52 can range from about 0% at the top surface of the first epitaxial semiconductor material 52 to about 90% at the bottom surface of the first epitaxial semiconductor material 52. In some embodiments, the percentage of germanium atoms in the first epitaxial semiconductor material 52 can range from about 8% at the top surface of the first epitaxial semiconductor material 52 to about 32% at the bottom surface of the first epitaxial semiconductor material 52. In some embodiments, the ratio of the percentage of germanium atoms at the top surface of the first epitaxial semiconductor material 52 to the percentage of germanium atoms at the bottom surface of the first epitaxial semiconductor material 52 can range from about 1 :2 to about 1 :8, or from about 1 :3 to about 1 :5. As will be discussed in more detail below, the first epitaxial semiconductor material 52 including the germanium atom percentages in the prescribed ratio enables the fins (e.g., fins 55 discussed below with reference to FIG. 5) to have an improved rectangular profile, which enables better gate control, reduces fin width variation, and reduces drain induced barrier lowering. FIG. 3A to FIG. 4B

[0024] ​In embodiments in which the first epitaxial semiconductor material 52 is deposited by CVD, a graded germanium concentration in the first epitaxial semiconductor material 52 can be achieved by gradually reducing the flow rate of a germanium-containing precursor (e.g., germane (GeH4)) relative to the flow rate of a silicon-containing precursor (e.g., dichlorosilane (H2Cl2Si), silane (SiH4), etc.) during deposition of the first epitaxial semiconductor material 52. For example, at the beginning of the deposition process for depositing the first epitaxial semiconductor material 52, the ratio of the flow rate of the germanium precursor to the flow rate of the silicon precursor can be about 1 to about 9, or about 1 to about 3, and at the end of the deposition process for depositing the first epitaxial semiconductor material 52, the ratio of the flow rate of the germanium precursor to the flow rate of the silicon precursor can be about 0 to about 1, or about 0 to about 0.5. After depositing the first epitaxial semiconductor material 52, the top surface of the substrate 50 in the region 50N and the top surface of the first epitaxial semiconductor material 52 in the region 50P can be planarized by a process such as chemical mechanical polishing (CMP). The thickness T1 of the first epitaxial semiconductor material 52 can be about 10 nm to about 200 nm, or about 40 nm to about 60 nm.

[0025] In FIG. 3A the substrate 50 and the first epitaxial semiconductor material 52. The fins 55 are semiconductor strips. In some embodiments, the fins 55 can be formed in the substrate 50 and the first epitaxial semiconductor material 52 by etching trenches in the substrate 50 and the first epitaxial semiconductor material 52. The etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. The etching can be anisotropic.

[0026] The fins 55 can be patterned by any suitable method. For example, one or more photolithography processes can be used to pattern the fins 55, including a double patterning process or a multiple patterning process. In some embodiments, the double patterning process or the multiple patterning process combines photolithography and a self-alignment process, allowing a pattern to be created with, for example, smaller pitch than is obtainable using a single direct photolithography process. For example, in some embodiments, a sacrificial layer is formed over the substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins 55. In some embodiments, a mask (or other layer) can remain on the fins 55. As FIG. 3A shown, the fins 55 in both the region 50N and the region 50P can have a tapered profile, in which the width of the bottom of the fins 55 is greater than the width of the top of the fins 55.

[0027] In region 50N, the fins 55 (including the fin-shaped portions of the substrate 50 extending from the planar top surface of the substrate 50) can have a bottom width Wl from about 2.2 nm to about 100 nm, from about 25 nm to about 35 nm, or from about 28 nm to about 32 nm; a top width W2 from about 2 nm to about 50 nm, about 20 nm to 30 nm, or about 23 nm to about 27 nm; a ratio of the top width W2 to the bottom width Wl from about 0.5 to about 2, or about 0.7 to about 0.9; and a height Hl from about 10 nm to about 200 nm, or about 70 nm to about 90 nm. The fins 55 in region 50N can be spaced apart by a pitch Pl from about 2 nm to about 100 nm, or about 25 nm to about 35 nm. The angle Θl between the sidewalls of the fins 55 and the top surface of the substrate 50 in region 50N can be from about 70° to about 85°, about 78° to about 82°, about 95° to about 120°, or about 98° to about 102°. In region 50P, the fins 55 (including the first epitaxial semiconductor material 52 and the fin-shaped portions of the substrate 50 extending from the planar top surface of the substrate 50) can have a bottom width W3 from about 2.2 nm to about 100 nm, about 25 nm to about 35 nm, or about 28 nm to about 32 nm; an intermediate width W4 at the interface between the substrate 50 and the first epitaxial semiconductor material 52 from about 2.2 nm to about 80 nm, about 23 nm to about 33 nm, or about 26 nm to about 30 nm; a top width W5 from about 2 nm to about 50 nm, about 20 nm to about 30 nm, or about 23 nm to about 27 nm; and a height H2 from about 10 nm to about 200 nm, or about 70 nm to about 90 nm. The ratio of the top width W5 to the intermediate width W4 can be from about 2 to about 0.5, or about 0.8 to about 1.0, and the ratio of the intermediate width W4 to the bottom width W3 can be from about 2 to about 0.5, or from about 0.8 to about 1.0. The fins 55 in region 50P can be spaced apart by a pitch P2 from about 2 nm to about 100 nm, or about 25 nm to about 35 nm. The angle Θ2 between the sidewalls of the fins 55 and the top surface of the substrate 50 in region 50P can be from about 70° to about 85°, about 78° to about 82°, about 95° to about 120°, or about 98° to about 102°.

[0028] FIG. 3B One embodiment is shown in which a thinning process is performed after forming the fins 55 and before the STI region (e.g., the STI region 58 discussed below) to thin the fins 55. In the embodiment shown, the fins 55 in region 50N can be exposed to an etchant used to thin the fins 55 in region 50P, and the fins 55 in region 50P can be exposed to an etchant used to thin the fins in region 50N. FIG. 4A FIG. 3B In the embodiment shown, the fins 55 in region 50N can be exposed to an etchant used to thin the fins 55 in region 50P, and the fins 55 in region 50P can be exposed to an etchant used to thin the fins in region 50N. ​

[0029] exist FIG. 3B In the first etching process, a first etching chemistry can be used to etch the exposed portions of the fins 55 in the region 50N and the exposed portions of the fins 55 in the region 50P formed in the substrate 50. During the first etching process, the fins 55 in both the region 50N and the region 50P can be exposed to the first etching chemistry. It can be desirable to have a high first etching selectivity in order to minimize etching of the portion of the fin 55 in the region 50P formed from the first epitaxial semiconductor material 52. The first etching selectivity is the ratio of the etching rate (sometimes referred to as the trim rate) of the portions of the fins 55 in the region 50N and the region 50P formed in the substrate 50 (e.g., the portion of the fin 55 formed from silicon) to the etching rate of the portion of the fin 55 in the region 50P formed from the first epitaxial semiconductor material 52 (e.g., the portion of the fin 55 formed from silicon germanium). For example, the first etching selectivity can be greater than about 5 and can be in the range of about 5 to about 20, or more. The first etching process may be performed at a temperature in a range of about 5° C. to about 100° C., for example, about room temperature (eg, about 23° C.). The fin 55 may be exposed to the first etching chemistry for a duration of about 10 seconds to about 5 minutes, or about 45 seconds to about 75 seconds.

[0030] In some embodiments, the first etching chemistry may include a first etchant dissolved in a first solvent. The first etching chemistry may not contain an oxidizing agent. The first etchant may include a base or an acid. In embodiments where the first etchant includes a base, the first etchant may include a metal hydroxide (M n+ (OH - ) n ), amine derivatives, ammonium derivatives, combinations thereof, and the like. The metal hydroxide may include sodium hydroxide (NaOH), potassium hydroxide (KOH), lithium hydroxide (LiOH), rubidium hydroxide (RbOH), cesium hydroxide (CsOH), combinations thereof, and the like. The amine derivative may include ammonia (NH3), ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH, (CH3)4N(OH)), tetraethylammonium hydroxide (TEAH, (C2H5)4N(OH)), trimethyltetradecylammonium hydroxide (TTAH, (CH3)3(C 14 H 29 )N(OH)), tetrabutylammonium hydroxide (TBAH, (C4H9)4N(OH)), combinations thereof, and the like. In embodiments where the first etchant is a base, the pH of the first etch chemistry can be from about 7 to about 13, or from about 8 to about 10. The concentration of the first etchant in the first etch chemistry can range from about 0.01 M to about 20 M, or from about 0.5 M to about 1.5 M.

[0031] In embodiments where the first etchant includes an acid, the first etchant can include hydrochloric acid (HC1), hydrofluoric acid (HF), sulfuric acid (H2SO4), phosphoric acid (H3PO4), nitric acid (HNO3), carboxylic acid derivatives (C n H 2n+1 COOH), combinations thereof, or the like. In embodiments where the first etchant is an acid, the pH of the first etching chemistry can be from about 0 to about 7, or from about 1 to about 3. The concentration of the first etchant in the first etching chemistry can range from about 0.01 M to about 20 M, or from about 0.5 M to about 1.5 M.

[0032] A first solvent can be utilized to assist in mixing and delivering the first etchant. The first solvent can not participate in the etching reaction itself. In particular embodiments, the first etching solvent can be a solvent such as deionized water or the like. However, any suitable solvent can be used.

[0033] The first etching chemistry can further include an ionic surfactant or a non-ionic surfactant, for example, a quaternary ammonium (NR4 + ), a sulfate (SO4 2- ), a sulfonate (R-SO3 - ), a phosphate (-PO4 3- ), a carboxylate (R-COO - ), an alcohol ethoxylate, an alkyl phenol ethoxylate, a fatty acid ethoxylate, a fatty amine ethoxylate, a glycol ester, a glycerol ester, combinations thereof, or the like, which can be added to reduce the surface tension of the first etching chemistry. The concentration of the surfactant in the first etching chemistry can range from about 0.0001 M to about 1 M, or from about 0.005 M to about 0.02 M.

[0034] Prior to etching the fins 55 with the first etching process, the fins 55 have a tapered profile, where the width of the bottom of the fins 55 is greater than the width of the top of the fins 55 (as previously discussed with respect to FIG. 1A). FIG. 3A The first etching process can have the same etch rate at the top of the fins 55 and the bottom of the fins 55, such that the fins 55 in the region 50N, as well as the portion of the fins 55 in the region 50P that are formed in the substrate 50, still have a tapered profile after etching the fins 55 with the first etching process.

[0035] After etching the fins 55 in the region 50N and the region 50P with the first etching process, the height H5 of the fins 55 in the region 50N can be from about 10 nm to about 200 nm, or from about 60 nm to about 80 nm; the bottom width W 10 may be from about 2.2 nm to about 100 nm, from about 15 nm to about 25 nm, or from about 18 nm to about 22 nm; and the top width W 11The top width W may be from about 2 nm to about 50 nm, from about 10 nm to about 20 nm, or from about 13 nm to about 17 nm; and 11 With bottom width W 10 The ratio of θ5 may be from about 0.5 to about 2, or from about 0.65 to about 0.85. The angle θ5 between the sidewall of the fin 55 in the region 50N and the top surface of the substrate 50 may be from about 70° to about 85°, from about 78° to about 82°, from about 95° to about 120°, or from about 98° to about 102°. The bottom width W of the portion of the fin 55 in the region 50P formed in the substrate 50 may be from about 10° to about 10°. 12 The top width W may be from about 2.2 nm to about 100 nm, from about 15 nm to about 25 nm, or from about 18 nm to about 22 nm; 13 The top width W may be from about 2 nm to about 80 nm, from about 13 nm to about 23 nm, or from about 16 nm to about 20 nm; and 13 With bottom width W 12 The ratio of θ may be from about 0.5 to about 2, or from about 0.8 to about 1.0. Angle θ6 between the sidewall of the portion of fin 55 in region 50P formed in substrate 50 and the top surface of substrate 50 may be from about 70° to about 85°, from about 78° to about 82°, from about 95° to about 120°, or from about 98° to about 102°.

[0036] Further in FIG. 3B In the embodiment of the present invention, a second etching chemistry may be used in a second etching process different from the first etching process to etch the exposed portions of the fins 55 formed of the first epitaxial semiconductor material 52 in the region 50P. During the second etching process, the fins 55 in both the region 50P and the region 50N may be exposed to the second etching chemistry. It is desirable that the second etching selectivity is high so as to minimize etching of the fins 55 in the region 50N and the portions of the fins 55 in the region 50P formed in the substrate 50. The second etching selectivity is the ratio of the etching rate of the portions of the fins 55 in the region 50P formed of the first epitaxial semiconductor material 52 to the etching rate of the portions of the fins 55 in the region 50N and the portions of the fins 55 in the region 50P formed in the substrate 50. For example, the second etching selectivity may be higher than about 5 and may be in the range of about 5 to about 20, or higher. The second etching process may be performed at a temperature in the range of about 5°C to about 100°C, for example, about room temperature (e.g., about 23°C).

[0037] In some embodiments, the second etch chemistry can include an oxidizing agent and a second etchant dissolved in a second solvent. The fins 55 can be simultaneously exposed to the oxidizing agent and the second etchant. In embodiments in which the fins 55 are simultaneously exposed to the oxidizing agent and the second etchant, the fins 55 can be exposed to the second etch chemistry for a duration of about 30 seconds to about 2 minutes, or about 45 seconds to about 75 seconds. In some embodiments, the second etchant can be the same as the first etchant. For example, in some embodiments, the second etchant can be a base or an acid.

[0038] In embodiments in which the second etchant includes a base, the second etchant can include a metal hydroxide (M n+ (OH - ) n ), amine derivatives, ammonium derivatives, combinations thereof, and the like. The metal hydroxide can include sodium hydroxide (NaOH), potassium hydroxide (KOH), lithium hydroxide (LiOH), rubidium hydroxide (RbOH), cesium hydroxide (CsOH), combinations thereof, and the like. The amine derivatives can include ammonia (NH3), ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH, (CH3)4N(OH)), tetraethylammonium hydroxide (TEAH, (C2H5)4N(OH)), trimethyltetradecylammonium hydroxide (TTAH, (CH3)3(C 14 H 29 )N(OH)), tetrabutylammonium hydroxide (TBAH, (C4H9)4N(OH)), combinations thereof, and the like. In embodiments in which the second etchant is basic, the pH of the second etch chemistry can be from about 7 to about 13, or about 8 to about 10. The concentration of the second etchant in the second etch chemistry can range from about 0.01 M to about 20 M, or about 0.5 M to about 1.5 M.

[0039] In embodiments in which the second etchant includes an acid, the second etchant can include hydrochloric acid (HC1), hydrofluoric acid (HF), sulfuric acid (H2SO4), phosphoric acid (H3PO4), nitric acid (HNO3), carboxylic acid derivatives (C n H 2n+1 COOH), combinations thereof, and the like. In embodiments in which the second etchant is acidic, the pH of the second etch chemistry can be about 0 to about 7, or about 1 to about 3. The concentration of the second etchant in the second etch chemistry can range from about 0.01 M to about 20 M, or about 0.5 M to about 1.5 M.

[0040] The oxidizing agent can include ozonated deionized water (DIO3), hydrogen peroxide (H2O2), other non-metallic oxidizing agents, combinations thereof, and the like. The concentration of the oxidizing agent in the second etching chemistry can range from about 0.0001 M to about 1 M, or about 0.0005 M to about 0.002 M. The inclusion of the oxidizing agent in addition to the second etchant can cause the first epitaxial semiconductor material 52 to be selectively etched relative to the fins 55 in the region 50N and the portion of the fins 55 in the region 50P formed in the substrate 50. The oxidizing agent can be used to oxidize the fins 55 in the region 50P, forming silicon germanium oxide in the fins 55, and then the second etchant can be used to etch the silicon germanium oxide material, thinning the fins 55 in the region 50P. On the other hand, in the region 50N, the oxidizing agent can be used to oxidize the fins 55, forming silicon oxide in the fins 55 that is etched at a slower rate by the second etchant. Silicon can also be oxidized at a slower rate compared to silicon germanium, such that any silicon oxide layer formed in the fins 55 in the region 50N and in the portion of the fins 55 in the region 50P formed in the substrate 50 is thinner than the oxide layer formed in the fins 55 in the region 50P. Thus, the fins 55 in the region 50N and the portion of the fins 55 in the region 50P formed in the substrate 50 are not substantially thinned, while the fins 55 in the region 50P are thinned.

[0041] A second solvent can be utilized to assist in mixing and delivering the oxidizing agent and the second etchant. The second solvent can not participate in the etching reaction itself. In particular embodiments, the second etching solvent can be a solvent such as deionized water, acetic acid (CH3COOH), and the like. In embodiments in which the oxidizing agent includes ozonated deionized water, the deionized water can also serve as the solvent. Any suitable solvent can be used.

[0042] The second etching chemistry can further include an ionic surfactant or a non-ionic surfactant, for example, a quaternary ammonium (NR4 + ), a sulfate (SO4 2- ), a sulfonate (R-SO3 - ), a phosphate (-PO4 3- ), a carboxylate (R-COO - ), an alcohol ethoxylate, an alkyl phenol ethoxylate, a fatty acid ethoxylate, a fatty amine ethoxylate, a glycol ester, a glycerol ester, combinations thereof, and the like, which can be added to reduce the surface tension of the second etching chemistry. The concentration of the surfactant in the second etching chemistry can range from about 0.0001 M to about 1 M, or about 0.005 M to about 0.02 M.

[0043] In a specific embodiment, the second etching chemical can include hydrofluoric acid (HF), hydrogen peroxide (H2O2), and acetic acid (CH3COOH). The acetic acid can be a solvent in which the hydrofluoric acid and hydrogen peroxide are dissolved. The hydrogen peroxide can be an oxidizing agent used to oxidize the fins 55 in the region 50P. The hydrofluoric acid can be a second etchant used to thin the fins 55 in the region 50P. The volume ratio of the hydrofluoric acid: hydrogen peroxide: acetic acid can be about 1 : 2 : 3.

[0044] In a further embodiment, in a cyclic process, the fins 55 can be exposed to an oxidizing agent, then the oxidizing agent can be removed, and the fins 55 can be exposed to a second etchant to thin the fins 55. Exposing the fins 55 to the oxidizing agent can oxidize the fins 55 in the region 50N and the region 50P. Exposing the fins 55 to the etchant can selectively etch the oxide formed in the first epitaxial semiconductor material 52 relative to the oxide in the fins 55 formed in the region 50N and in the portion of the fins 55 formed in the substrate 50 in the region 50P.

[0045] The oxidizing agent used in the cyclic process can be the same as the oxidizing agent used in the process where the fins 55 are simultaneously exposed to the oxidizing agent and the second etchant described above. For example, the oxidizing agent can include ozonated deionized water (DIO3), hydrogen peroxide (H2O2), other non-metallic oxidizing agents, combinations thereof, and the like. The concentration of the oxidizing agent in the oxidizing agent can range from 0.0001 M to about 1 M, or about 0.0005 M to about 0.002 M. As described previously, exposing the fins 55 can oxidize the fins 55 in the region 50P. The fins 55 in the region 50N can also be oxidized, but can be oxidized at a slower rate than the fins 55 in the region 50P.

[0046] The second etchant used in the cyclic process can be the same or similar to the first etchant. The concentration of the second etchant can range from about 0.01 M to about 20 M, or about 0.5 M to about 1.5 M. Exposing the fins 55 to the second etchant thins the fins 55. As described previously, the fins 55 in the region 50N can be thinned at a slower rate than the fins 55 in the region 50P.

[0047] For each cycle, the fins 55 can be exposed to the oxidizing agent for a duration of from about 10 seconds to about 2 minutes, or about 45 seconds to about 75 seconds, and the fins 55 can be exposed to the second etchant for a duration of from about 10 seconds to about 5 minutes, or about 45 seconds to about 75 seconds. The cyclic etching process can be repeated for up to 20 cycles, up to 10 cycles, 4 to 6 cycles, and the like. Exposing the fins 55 to the oxidizing agent and then to the second etchant in the cyclic process can provide better control of the etching of the first epitaxial semiconductor material 52. This results in improved gate control of the resulting FinFET, reduces fin width variation, and results in reduced DIBL.

[0048] The second etch process can have an etch rate that depends on the germanium concentration in the first epitaxial semiconductor material 52. For example, the second etch process can have a higher etch rate as the germanium concentration in the first epitaxial semiconductor material 52 increases. As discussed previously in the discussion related to FIGS. 3A-3C, the first epitaxial semiconductor material 52 can have a gradient germanium concentration, where the germanium concentration is higher at a bottom surface of the first epitaxial semiconductor material 52 and gradually and continuously decreases toward a top surface of the first epitaxial semiconductor material 52. Thus, a bottom portion of the first epitaxial semiconductor material 52 can be etched by the second etch process at a higher etch rate compared to a top portion of the first epitaxial semiconductor material 52. A ratio of the etch rate at the bottom surface of the first epitaxial semiconductor material 52 (e.g., the maximum etch rate) to the etch rate at the top surface of the first epitaxial semiconductor material 52 (e.g., the minimum etch rate) can be from about 1 to about 3, or about 1.25 to about 1.75. FIG. 2 As discussed previously in the discussion related to FIGS. 3A-3C, the first epitaxial semiconductor material 52 can have a gradient germanium concentration, where the germanium concentration is higher at a bottom surface of the first epitaxial semiconductor material 52 and gradually and continuously decreases toward a top surface of the first epitaxial semiconductor material 52. Thus, a bottom portion of the first epitaxial semiconductor material 52 can be etched by the second etch process at a higher etch rate compared to a top portion of the first epitaxial semiconductor material 52. A ratio of the etch rate at the bottom surface of the first epitaxial semiconductor material 52 (e.g., the maximum etch rate) to the etch rate at the top surface of the first epitaxial semiconductor material 52 (e.g., the minimum etch rate) can be from about 1 to about 3, or about 1.25 to about 1.75.

[0049] Prior to etching the fin 55 in the region 50P with the second etch process, the fin 55 has a tapered profile, where a width of a bottom of the fin 55 is greater than a width of a top of the fin 55 (as discussed previously in the discussion related to FIGS. 3A-3C). Etching the first epitaxial semiconductor material 52 with the second etch process, which has a higher etch rate at the bottom of the first epitaxial semiconductor material 52 than at the top of the first epitaxial semiconductor material 52, causes the first epitaxial semiconductor material 52 to have a more rectangular profile after etching the first epitaxial semiconductor material 52 with the second etch process. FIG. 3A After etching the first epitaxial semiconductor material 52 with the second etch process, a height H6 of the portion of the fin 55 in the region 50P formed of the first epitaxial semiconductor material 52 can be from about 5 nm to about 100 nm, or about 60 nm to about 80 nm; a bottom width W 14 may be from about 2.2 nm to about 100 nm, about 10 nm to about 20 nm, or about 13 nm to about 17 nm; a top width W 15 may be from about 2 nm to about 50 nm, about 10 nm to about 20 nm, or about 13 nm to about 17 nm; and a top width W 15 may be from about 2 nm to about 50 nm, about 10 nm to about 20 nm, or about 13 nm to about 17 nm; and a top width W 14 may be from about 2 nm to about 50 nm, about 10 nm to about 20 nm, or about 13 nm to about 17 nm; and a top width W 16 may be from about 2 nm to about 50 nm, about 10 nm to about 20 nm, or about 13 nm to about 17 nm; and a top width W

[0050]

[0051] The fins 55 in the region 50P are formed with a graded germanium concentration, and the fins 55 in the region 50P are thinned using an etch process that has a higher etch rate as the germanium concentration increases, so that the fins 55 in the region 50P have a more rectangular profile and control of the process used to etch the fins 55 in the region 50P is improved. Inclusion of the fins 55 in the FinFET enables better gate control, reduces fin width variation, and reduces DIBL.

[0052] FIG. 3C Another embodiment is shown in which a thinning process is performed to thin the fins 55 after the fins 55 are formed and before the STI region (e.g., the STI region 58 discussed below with reference to FIG. 4A In the embodiment shown, the fins 55 in the region 50N can be masked while the fins 55 in the region 50P are thinned, and the fins 55 in the region 50P can be masked while the fins 55 in the region 50N are thinned. FIG. 3C In the embodiment shown, the fins 55 in the region 50N can be masked while the fins 55 in the region 50P are thinned, and the fins 55 in the region 50P can be masked while the fins 55 in the region 50N are thinned.

[0053] In the embodiment shown, the fins 55 in the region 50N can be masked while the fins 55 in the region 50P are thinned, and the fins 55 in the region 50P can be masked while the fins 55 in the region 50N are thinned. FIG. 3C In the embodiment shown, the fins 55 in the region 50N can be masked while the fins 55 in the region 50P are thinned, and the fins 55 in the region 50P can be masked while the fins 55 in the region 50N are thinned. FIG. 3B In the embodiment shown, the fins 55 in the region 50N can be masked while the fins 55 in the region 50P are thinned, and the fins 55 in the region 50P can be masked while the fins 55 in the region 50N are thinned.

[0054] After the fins 55 in the region 50N and the region 50P are etched, the fins 55 in the region 50N can have the same dimensions as the fins 55 in the region 50N discussed above with reference to FIG. 3B The formation of the fins 55 in the region 50P can have the same dimensions as the fins 55 in the region 50P discussed above with reference to FIG. 3AThe fins 55 in the region 50P discussed may be of the same or similar size as the portion formed in the substrate 50. For example, the width of the fins 55 in the region 50P formed in the substrate 50P may be the same as above with respect to FIG. 3A The height H8 of the portion of the fin 55 formed by the first epitaxial semiconductor material 52 in the region 50P can be about 5 nm to about 100 nm, or about 60 nm to about 80 nm; the bottom width W 16 The top width W may be from about 2.2 nm to about 100 nm, from about 10 nm to about 20 nm, or from about 13 nm to about 17 nm; 17 The top width W may be from about 2 nm to about 50 nm, from about 10 nm to about 20 nm, or from about 13 nm to about 17 nm; and 17 With bottom width W 16 The ratio of θ to θ can be from about 0.8 to about 1.2, or from about 0.9 to about 1.1. An angle θ8 between the sidewalls of the portion of the fin 55 formed of the first epitaxial semiconductor material 52 in the region 50P and the top surface of the substrate 50 can be from about 80° to about 100°, from about 85° to about 95°, or from about 88° to about 92°. A height H9 of the fin 55 in the region 50P can be from about 10 nm to about 200 nm, or from about 70 nm to about 90 nm.

[0055] Fins 55 having a gradient germanium concentration are formed in region 50P, and fins 55 in region 50P are thinned using an etch process with a higher etch rate as the germanium concentration increases. This results in fins 55 in region 50P having a more rectangular profile and improved control over the process used to etch fins 55 in region 50P. Including fins 55 in the FinFET enables better gate control, reduces fin width variation, and reduces DIBL. Using various masks to protect fins 55 in region 50N and etch fins 55 in region 50P, and to protect fins in region 50P and etch fins in region 50N, provides additional control over the fin profiles in both regions 50N and 50P.

[0056] FIG. 4A An embodiment is shown in which the fin 55 is not thinned until after the shallow trench isolation (STI) region 58 is formed. For example, as will be described below with respect to FIG. 4B After forming the STI regions 58 as discussed below, or as will be discussed below with respect to FIG. 13C to FIG. 13E The removal of the dummy gate stack discussed below (e.g., FIG. 6A and FIG. 6B The thinning process is performed after the dummy gate stack including the dummy gate 72 and the dummy dielectric layer 60 discussed above. However, it should be understood that the thinning process can be performed after the dummy gate stack including the dummy gate 72 and the dummy dielectric layer 60 discussed above. FIG. 3B and FIG. 3CThe thinned fin 55 is then formed on FIG. 4A and subsequently performed steps in the figures.

[0057] In FIG. 4A adjacent to the fins 55. The STI regions 58 can be formed by forming an insulating material (not separately shown) over the substrate 50 and between adjacent fins 55. The insulating material can be an oxide (e.g., silicon oxide), nitride, etc., or combinations thereof, and can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition in a remote plasma system and post-curing to convert the deposited material to another material, such as an oxide), etc., or combinations thereof. Other insulating materials formed by any acceptable process can be used. In the illustrated embodiment, the insulating material is silicon oxide formed by a FCVD process. Once the insulating material is formed, an annealing process can be performed. In some embodiments, the insulating material is formed such that excess insulating material covers the fins 55. The insulating material can include a single layer or can employ multiple layers. For example, in some embodiments, a liner (not separately shown) can first be formed along the surfaces of the substrate 50 and fins 55. Thereafter, a fill material such as described above can be formed over the liner.

[0058] A removal process is then applied to the insulating material to remove the excess insulating material over the fins 55. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), an etch-back process, combinations thereof, etc., can be employed. The planarization process can planarize the insulating material and the fins 55. The planarization process exposes the fins 55 such that the top surfaces of the fins 55 and the insulating material are flush after the planarization process is completed.

[0059] The insulating material is then recessed to form the STI regions 58 as FIG. 4A shown. The insulating material is recessed such that the fins 55 and the upper portions of the substrate 50 protrude from between adjacent STI regions 58. In addition, the top surfaces of the STI regions 58 can have a planar surface (as shown), a convex surface, a concave surface (e.g., dished), or combinations thereof. The top surfaces of the STI regions 58 can be formed to be planar, convex, and / or concave by appropriate etching. The STI regions 58 can be recessed using an acceptable etching process, such as an etching process selective to the material of the insulating material (e.g., etching the material of the insulating material at a faster rate than the materials of the fins 55 and the substrate 50). For example, oxide removal using, for example, dilute hydrofluoric acid (dHF) acid can be employed. The height H 11 may be from about 30 nm to about 100 nm, or about 55 nm to about 75 nm.

[0060] Further in FIG. 4A the appropriate wells (not shown separately) can be formed in the fins 55 and / or the substrate 50. In some embodiments, a P-well can be formed in the region 50N, and an N-well can be formed in the region 50P. In some embodiments, a P-well or an N-well is formed in both the region 50N and the region 50P.

[0061] In embodiments with different well types, a photoresist or other mask (not shown separately) can be used to implement different implant steps for the region 50N and the region 50P. For example, a photoresist can be formed over the fins 55 and the STI region 58 in the region 50N. The photoresist is patterned to expose the region 50P of the substrate 50, e.g., the PMOS region. The photoresist can be formed by using a spin-on technique, and can be patterned using an acceptable photolithography technique. Once the photoresist is patterned, an n-type impurity implant is performed in the region 50P, and the photoresist can be used as a mask to substantially prevent the n-type impurity from being implanted into the region 50N, e.g., the NMOS region. The n-type impurity can be phosphorous, arsenic, antimony, etc., implanted into the region at a concentration equal to or less than 1 x 1019atoms / cm2, e.g., between about 1 x 1018atoms / cm2and about 1 x 1019atoms / cm2. After implantation, the photoresist is removed, e.g., by an acceptable ashing process. 18 3 16 3 18 3 After implantation, the photoresist can be removed, e.g., by an acceptable ashing process.

[0062] After implantation in the region 50P, a photoresist is formed over the fins 55 and the STI region 58 in the region 50P. The photoresist is patterned to expose the region 50N of the substrate 50, e.g., the NMOS region. The photoresist can be formed by using a spin-on technique, and can be patterned using an acceptable photolithography technique. Once the photoresist is patterned, a p-type impurity implant can be performed in the region 50N, and the photoresist can be used as a mask to substantially prevent the p-type impurity from being implanted into the region 50P, e.g., the PMOS region. The p-type impurity can be boron, boron fluoride, indium, etc., implanted into the region at a concentration equal to or less than 1 x 1019atoms / cm2, e.g., between about 1 x 1018atoms / cm2and about 1 x 1019atoms / cm2. After implantation, the photoresist can be removed, e.g., by an acceptable ashing process. 18 3 16 3 18 3 After implantation, the photoresist can be removed, e.g., by an acceptable ashing process.

[0063] ​​​​​​​​​​After implantation in region 50N and region 50P, annealing can be performed to repair implant damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the epitaxial fin growth material can be doped in-situ during growth, which can eliminate implantation, but in-situ doping and implantation doping can be used together.

[0064] FIG. 4B One embodiment is shown in which a thinning process is performed after forming STI region 58 to thin the fins 55, rather than as discussed above with reference to FIG. 3B and FIG. 3C performing a thinning process after forming fins 55 and before forming STI region 58. In FIG. 4B the embodiment shown, fins 55 in region 50N can be exposed to an etchant used to thin fins 55 in region 50P, and fins 55 in region 50P can be exposed to an etchant used to thin fins 55 in region 50N.

[0065] In FIG. 4B the embodiment shown, fins 55 in both region 50N and region 50P are thinned in the same direction, which can be the vertical direction, as shown in FIG. 5B. In other embodiments, fins 55 in region 50N and region 50P can be thinned in different directions. FIG. 3BThe fin 55 in region 50N (including the fin-shaped portion of substrate 50 extending from the flat top surface of substrate 50) may be exposed to the first etch chemistry and the second etch chemistry in the same or similar process as described above. After the first etch process, the height H3 of the fin 55 in region 50N (including the fin-shaped portion of substrate 50 extending from the flat top surface of substrate 50) may be from about 5 nm to about 100 nm, or from about 60 nm to about 80 nm; the bottom width W6 may be from about 2.2 nm to about 80 nm, from about 17 nm to about 27 nm, or from about 20 nm to about 24 nm; the top width W7 may be from about 2 nm to about 50 nm, from about 10 nm to about 20 nm, or from about 13 nm to about 17 nm; and the ratio of the top width W7 to the bottom width W6 may be from about 0.5 to about 2, or from about 0.6 to about 0.8. The angle θ3 between the sidewalls of the fin 55 in region 50N and the top surface of substrate 50 may be from about 70° to about 85°, from about 78° to about 82°, from about 95° to about 120°, or from about 98° to about 102°. After the second etching process, the height H4 of the fin 55 (including the first epitaxial semiconductor material 52 and the fin-shaped portion of the substrate 50 extending from the flat top surface of the substrate 50) in the region 50P can be from about 5 nm to about 100 nm, or from about 60 nm to about 80 nm; the bottom width W8 can be from about 2.2 nm to about 80 nm, from about 10 nm to about 20 nm, or from about 13 nm to about 17 nm; the top width W9 can be from about 2 nm to about 50 nm, from about 10 nm to about 20 nm, or from about 13 nm to about 17 nm; and the ratio of the top width W9 to the bottom width W8 can be from about 0.8 to about 1.2, or from about 0.9 to about 1.1. In some embodiments, the bottom width W8 of the fin 55 in the region 50P can be within 10 nm, within 5 nm, or within 1 nm of the top width W9 of the fin 55 in the region 50P. An angle θ4 between the sidewalls of the fin 55 in the region 50P and the top surface of the substrate 50 may be from about 80° to about 100°, about 85° to about 95°, or about 88° to about 92°.

[0066] The portion of the fin 55 in the region 50N and the region 50P that is surrounded by the STI region 58 may remain unchanged after the thinning process is performed. For example, the portion of the fin 55 disposed below the top surface of the STI region 58 may have the same thickness as described above. FIG. 3A The width in question is similar or identical to the width. FIG. 4B As shown, the width of fin 55 flush with the top surface of STI region 58 may have a step change due to the thinning process.

[0067] The fins 55 in the region 50P are formed with a graded germanium concentration, and the fins 55 in the region 50P are thinned using an etch process that has a higher etch rate as the germanium concentration increases, such that the fins 55 in the region 50P have a more rectangular profile and improved control of the process used to etch the fins 55 in the region 50P. The inclusion of the fins 55 in the FinFET enables better gate control, reduces fin width variation, and reduces DIBL.

[0068] FIG. 5 Embodiments are shown in which the fins 55 are not thinned until after the dummy gate stack (e.g., the dummy gate 72 and the dummy dielectric layer 60 discussed below with reference to FIG. 6A and FIG. 6B are discussed. For example, the thinning process can be performed after the dummy gate stack is removed, as will be discussed below with reference to FIG. 13C to FIG. 13E However, it should be understood that the steps performed in FIG. 3B , FIG. 3C and FIG. 4B may be performed on fins 55 that have already been thinned as described above with reference to FIG. 5 and subsequent figures.

[0069] In FIG. 5 , a dummy dielectric layer 60 is formed on the fins 55 and the substrate 50. The dummy dielectric layer 60 can be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and can be deposited or thermally grown according to acceptable techniques. A dummy gate layer 62 is formed over the dummy dielectric layer 60, and a mask layer 64 is formed over the dummy gate layer 62. The dummy gate layer 62 can be deposited over the dummy dielectric layer 60 and then planarized by a process such as CMP. The mask layer 64 can be deposited over the dummy gate layer 62. The dummy gate layer 62 can be a conductive material or a non-conductive material, and can be selected from the group including amorphous silicon, polysilicon, poly-SiGe, metal nitride, metal silicide, metal oxide, and metal. The dummy gate layer 62 can be deposited by physical vapor deposition (PVD), CVD, sputter deposition, or other techniques known in the art and used to deposit the selected material. The dummy gate layer 62 can be made of other materials that have a high etch selectivity with respect to the material of the STI region 58. The mask layer 64 can include, for example, silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer 62 and a single mask layer 64 are formed across the region 50N and the region 50P. It should be noted that the dummy dielectric layer 60 is shown as covering only the fins 55 and the substrate 50 for illustrative purposes. In some embodiments, the dummy dielectric layer 60 can be deposited such that the dummy dielectric layer 60 covers the STI region 58, extending between the dummy gate layer 62 and the STI region 58.

[0070] FIG. 6A to FIG. 16E Various additional steps in the fabrication of an embodiment device are shown. FIG. 6A to FIG. 13B and FIG. 14A to FIG. 16B Features in region 50N or region 50P are shown. For example, FIG. 6A to FIG. 13B and FIG. 14A to FIG. 16B The structures shown can apply to both region 50N and region 50P. Differences in the structures of region 50N and region 50P, if any, are described in the text accompanying each figure. For example, FIG. 13C to FIG. 13E and FIG. 16C to FIG. 16E The structures shown describe differences between region 50N and region 50P.

[0071] In FIG. 6A and FIG. 6B Mask layer 64 (see FIG. 5 ) can be patterned using acceptable photolithography and etching techniques to form mask 74. The pattern of mask 74 can be transferred to dummy gate layer 62 using acceptable etching techniques to form dummy gates 72. In some embodiments, the pattern of mask 74 can also be transferred to dummy dielectric layer 60. Dummy gates 72 cover respective channel regions 68 of fins 55. The pattern of mask 74 can be used to separate each dummy gate 72 from adjacent dummy gates. Dummy gates 72 can also have a length direction that is substantially perpendicular to the length direction of the respective fin 55. Dummy dielectric layer 60, dummy gates 72, and mask 74 can be collectively referred to as a “dummy gate stack.”

[0072] In FIG. 7A and FIG. 7B First spacer layer 80 and second spacer layer 82 are formed over the structures shown in FIG. 6A and FIG. 6B In FIG. 7A and FIG. 7B First spacer layer 80 is formed on the top surfaces of STI regions 58, fins 55, and the top surfaces and sidewalls of mask 74, and the sidewalls of dummy gates 72 and dummy dielectric layer 60. Second spacer layer 82 is deposited over first spacer layer 80. First spacer layer 80 can be formed by thermal oxidation, or deposited by CVD, ALD, etc. First spacer layer 80 can be formed of silicon oxide, silicon nitride, silicon oxynitride, etc. Second spacer layer 82 can be deposited by CVD, ALD, etc. Second spacer layer 82 can be formed of silicon oxide, silicon nitride, silicon oxynitride, etc.

[0073] In FIG. 8A and FIG. 8BIn some embodiments, the first spacer 81 and the second spacer 83 can partially extend upward to the sidewalls of the fin 55 and the dummy gate stack. In some embodiments, the first spacer 81 and the second spacer 83 can extend to the top surface of the dummy gate stack. FIG. 8A and FIG. 8B As shown in FIG. 4, the first spacer 81 and the second spacer 83 can be formed on the sidewalls of the fin 55, the dummy dielectric layer 60, the dummy gate 72, and the mask 74. The first spacer 81 and the second spacer 83 can have different heights due to the etching process used to etch the first spacer layer 80 and the second spacer layer 82, as well as different heights between the fin 55 and the dummy gate stack. Specifically, as shown in FIG. 4, the first spacer 81 and the second spacer 83 can partially extend upward to the sidewalls of the fin 55 and the dummy gate stack. In some embodiments, the first spacer 81 and the second spacer 83 can extend to the top surface of the dummy gate stack.

[0074] After the first spacer 81 and the second spacer 83 are formed, an implant for a lightly doped source / drain (LDD) region (not shown separately) can be performed. In embodiments having different device types, similar to the implant discussed above in FIG. 4, a mask (e.g., photoresist) can be formed over the region 50N, exposing the region 50P, and impurities of an appropriate type (e.g., p-type) can be implanted into the exposed fin 55 and substrate 50 in the region 50P. The mask can then be removed. Subsequently, a mask (e.g., photoresist) can be formed over the region 50P, exposing the region 50N, and impurities of an appropriate type (e.g., n-type) can be implanted into the exposed fin 55 and substrate 50 in the region 50N. The mask can then be removed. The n-type impurities can be any of the n-type impurities discussed previously, and the p-type impurities can be any of the p-type impurities discussed previously. The lightly doped source / drain region can have an impurity concentration of about 1 x 1010atoms / cm3to about 1 x 1012atoms / cm3. Annealing can be used to repair implant damage and activate the implanted impurities. 15 3 19 3

[0075] Note that the above disclosure generally describes processes for forming spacers and LDD regions. Other processes and sequences can be used. For example, fewer or additional spacers can be employed, different step sequences can be employed (e.g., the first spacer 81 can be formed before the second spacer 83 is formed, additional spacers can be formed and removed, etc.). Furthermore, different structures and steps can be used to form n-type devices and p-type devices.

[0076] In some embodiments, the first spacer 81 and the second spacer 83 can partially extend upward to the sidewalls of the fin 55 and the dummy gate stack. In some embodiments, the first spacer 81 and the second spacer 83 can extend to the top surface of the dummy gate stack. FIG. 9A and​​​​FIG. 9B In the embodiment, a first recess 86 is formed in the fin 55 and the substrate 50. FIG. 9A As shown, the top surface of the STI region 58 can be flush with the top surface of the substrate 50. The substrate 50 can be etched so that the bottom surface of the first recess 86 is disposed above or below the top surface of the STI region 58. The first recess 86 can be formed by etching the fin 55 and the substrate 50 using an anisotropic etching process such as RIE, NBE, etc. During the etching process for forming the first recess 86, the first spacer 81, the second spacer 83, and the mask 74 mask portions of the fin 55 and the substrate 50. The first recess 86 can be formed using a single etching process or multiple etching processes. A timed etching process can be used to stop etching the first recess 86 after the first recess 86 reaches a desired depth.

[0077] exist FIG. 10A-10C In the embodiment, epitaxial source / drain regions 92 are formed in the first recess 86 to apply stress on the channel region 68 of the fin 55, thereby improving performance. FIG. 10B As shown, epitaxial source / drain regions 92 are formed in first recesses 86 such that each dummy gate 72 is disposed between a corresponding adjacent pair of epitaxial source / drain regions 92. In some embodiments, first spacers 81 are used to separate the epitaxial source / drain regions 92 from the dummy gates 72 by an appropriate lateral distance so that the epitaxial source / drain regions 92 do not short-circuit the gate of a subsequently formed resulting FinFET.

[0078] Epitaxial source / drain regions 92 in region 50N (e.g., NMOS region) can be formed by masking region 50P (e.g., PMOS region). Epitaxial source / drain regions 92 are then epitaxially grown in first recess 86. Epitaxial source / drain regions 92 can include any acceptable material, such as a material suitable for n-type FinFETs. For example, if fin 55 is silicon, epitaxial source / drain regions 92 can include a material that imposes tensile strain on fin 55, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphorus, etc. Epitaxial source / drain regions 92 can have surfaces that are raised from corresponding surfaces of fin 55 and can have small facets.

[0079] Epitaxial source / drain regions 92 in region 50P (e.g., PMOS region) can be formed by masking region 50N (e.g., NMOS region). Epitaxial source / drain regions 92 are then epitaxially grown in first recesses 86. Epitaxial source / drain regions 92 can comprise any acceptable material, such as a material suitable for a p-type NSFET. For example, if fins 55 are silicon, epitaxial source / drain regions 92 can comprise a material that exerts a compressive strain on fins 55, such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin, etc. Epitaxial source / drain regions 92 can also have surfaces that protrude from the respective surfaces of fins 55, and can have facets.

[0080] Epitaxial source / drain regions 92, fins 55, and / or substrate 50 can be implanted with dopants to form source / drain regions, similar to the previously discussed process for forming lightly doped source / drain regions, followed by annealing. The impurity concentration of the source / drain regions can be between about 1 x 1018atoms / cm3 19 and about 1 x 1019atoms / cm3 3 and about 1 x 1019atoms / cm3 21 and about 1 x 1019atoms / cm3 3 The n-type and / or p-type impurities for the source / drain regions can be any of the previously discussed impurities. In some embodiments, epitaxial source / drain regions 92 can be doped in situ during growth.

[0081] As a result of the epitaxial process for forming epitaxial source / drain regions 92 in region 50N and region 50P, the upper surfaces of epitaxial source / drain regions 92 have facets that extend laterally outward beyond the sidewalls of fins 55. In some embodiments, these facets cause adjacent epitaxial source / drain regions 92 of the same FinFET to merge, as shown in FIG. 10A In some embodiments, adjacent epitaxial source / drain regions 92 remain separate after the epitaxial process is complete, as shown in FIG. 10C In embodiments shown in FIG. 10A and FIG. 10C , first spacers 81 can be formed to cover the portions of the sidewalls of fins 55 that extend above STI regions 58, thereby preventing epitaxial growth. In some embodiments, the spacer etch used to form first spacers 81 can be adjusted to remove spacer material to allow the region of epitaxial growth to extend to the surface of STI regions 58.

[0082] In FIG. 11A and FIG. 11B , first interlayer dielectric (ILD) 96 is deposited over the structures shown in FIG. 6A and FIG. 10B , respectively FIG. 7A-FIG. 10C The process of FIG. 6AThe cross-section shown illustrates dummy gate 72 and the multi-layer stack 56 protected by dummy gate 72. First ILD 96 can be formed of a dielectric material and can be deposited by any suitable method such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material can include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process can be used. In some embodiments, a contact etch stop layer (CESL) 94 is disposed between first ILD 96 and epitaxial source / drain regions 92, mask 74, and first spacers 81. CESL 94 can include a dielectric material having a different etch rate than the material of overlying first ILD 96, for example, silicon nitride, silicon oxide, silicon oxynitride, etc.

[0083] In FIG. 12A and FIG. 12B a planarization process such as CMP can be performed to level the top surface of first ILD 96 with the top surface of dummy gate 72 or mask 74. The planarization process can also remove mask 74 over dummy gate 72, and portions of first spacers 81 along the sidewalls of mask 74. After the planarization process, the top surfaces of dummy gate 72, first spacers 81, and first ILD 96 are level. Thus, the top surface of dummy gate 72 is exposed through first ILD 96. In some embodiments, mask 74 can remain, in which case the planarization process levels the top surface of first ILD 96 with the top surfaces of mask 74 and first spacers 81.

[0084] In FIG. 13A and FIG. 13BIn some embodiments, dummy gate 72 and mask 74 (if present) are removed in the etching step(s), forming second recesses 98. Portions of dummy dielectric layer 60 in second recesses 98 can also be removed. In some embodiments, only dummy gate 72 is removed, and dummy dielectric layer 60 remains and is exposed by second recesses 98. In some embodiments, dummy dielectric layer 60 is removed from second recesses 98 in a first region of the die (e.g., a core logic region), and remains in second recesses 98 in a second region of the die (e.g., an input / output region). In some embodiments, dummy gate 72 is removed by an anisotropic dry etch process. For example, the etch process can include a dry etch process using reactive gas(es) that selectively etch dummy gate 72 at a faster rate than first ILD 96 or first spacers 81. Each second recess 98 exposes a channel region 68 of a respective fin 55 and / or overlying the channel region 68 of the respective fin 55. Each channel region 68 is disposed between an adjacent pair of epitaxial source / drain regions 92. During removal, dummy dielectric layer 60 can act as an etch stop layer when etching dummy gate 72. Dummy dielectric layer 60 can then be optionally removed after removing dummy gate 72.

[0085] FIG. 13C to FIG. 13E One embodiment is shown in which a thinning process is performed after removing the dummy gate stack to thin the fins 55, rather than as discussed above with reference to FIG. 3B and FIG. 3C performing the thinning process after forming the fins 55 and before forming the STI regions 58, or as discussed above with reference to FIG. 4B performing the thinning process after forming the STI regions 58. In FIG. 13C to FIG. 13E the embodiment shown, fins 55 in region 50N can be exposed to an etchant used to thin fins 55 in region 50P, and fins 55 in region 50P can be exposed to an etchant used to thin fins 55 in region 50N.

[0086] In FIG. 13C to FIG. 13E the embodiment shown, fins 55 in both region 50N and region 50P are exposed to a first etch chemistry and a second etch chemistry in the same or similar processes as discussed above with reference to FIG. 3B After the first etch process, fins 55 in region 50N can have the same dimensions as fins 55 in region 50N discussed above with reference to FIG. 4B After the second etch process, portions of fins 55 in region 50P formed of first epitaxial semiconductor material 52 can have the same dimensions as portions of fins 55 in region 50P discussed above with reference to FIG. 4B region 50P.

[0087] like FIG. 13D and FIG. 13E As shown, the thinning of the fin 55 may recess the exposed portion of the top surface of the fin 55 between the second spacers 83. FIG. 13D In the embodiment, a groove is formed in the top portion of the fin 55 in the region 50N formed by the substrate 50. FIG. 13E In the embodiment of the present invention, a recess is formed in the top portion of the fin 55 in the region 50P formed from the first epitaxial semiconductor material. The depth of the recess can be greatest at a point between the second spacers 83. The depth of the recess can become shallower as it approaches the second spacers 83. The fin 55 in the region 50N can be recessed to a depth D2 of about 2 nm to about 50 nm, about 5 nm to about 15 nm, or about 8 nm to about 12 nm below the topmost surface of the fin 55 in the region 50N. The fin 55 in the region 50P can be recessed to a depth D3 of about 2 nm to about 50 nm, about 5 nm to about 15 nm, or about 8 nm to about 12 nm below the topmost surface of the fin 55 in the region 50P.

[0088] Fins 55 having a gradient germanium concentration are formed in region 50P, and fins 55 in region 50P are thinned using an etch process having a higher etch rate as the germanium concentration increases, resulting in fins 55 in region 50P having a more rectangular profile and improved control over the process used to etch fins 55 in region 50P. Including fins 55 in FinFETs enables better gate control, reduces fin width variation, and reduces DIBL.

[0089] FIG. 14A to FIG. 14C An embodiment is shown in which the fin 55 is not thinned after the dummy gate stack is removed. FIG. 14A and FIG. 14B In the embodiment, a gate dielectric layer 100 and a gate electrode 102 are formed for replacing a gate. FIG. 14C Shown FIG. 14BA detailed view of region 101. Gate dielectric layer 100 is conformally deposited in second recess 98, e.g., on the top surfaces and sidewalls of fins 55 and first spacers 81, and on the top surfaces of STI region 58, first ILD 96, second spacers 83, and CESL 94. According to some embodiments, gate dielectric layer 100 includes silicon oxide, silicon nitride, or multiple layers thereof. In some embodiments, gate dielectric layer 100 includes a high-k dielectric material, and in these embodiments, gate dielectric layer 100 can have a k value greater than about 7.0, and can include a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. Methods of forming gate dielectric layer 100 can include molecular beam deposition (MBD), ALD, PECVD, etc. In embodiments in which portions of dummy dielectric layer 60 remain in second recess 98, gate dielectric layer 100 includes the material of dummy dielectric layer 60 (e.g., Si02).

[0090] Gate electrode 102 is deposited over gate dielectric layer 100 and fills the remaining portions of second recess 98, respectively. Gate electrode 102 can include a metal-containing material, e.g., titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers thereof. For example, although a single layer of gate electrode 102 is shown in FIG. 1C, gate electrode 102 can include any number of liner layers 102A, any number of work function adjustment layers 102B, and a fill material 102C, as shown in FIG. 2C. FIG. 14B FIG. 14C After filling second recess 98, a planarization process such as CMP can be performed to remove excess portions of material of gate electrode 102 and gate dielectric layer 100 that are above the top surface of first ILD 96. The remaining portions of material of gate electrode 102 and gate dielectric layer 100 thereby form a replacement gate for the resulting FinFET. Gate electrode 102 and gate dielectric layer 100 can be collectively referred to as a "gate stack." The gate and gate stack can extend along the sidewalls of channel region 68 of fin 55.

[0091] Formation of gate dielectric layer 100 in regions 50N and 50P can occur simultaneously, such that gate dielectric layer 100 in each region is formed of the same material, and formation of gate electrode 102 can occur simultaneously, such that gate electrode 102 in each region is formed of the same material. In some embodiments, gate dielectric layer 100 in each region can be formed by different processes, such that gate dielectric layer 100 can be a different material, and / or gate electrode 102 in each region can be formed by different processes, such that gate electrode 102 can be a different material. When different processes are used, various masking steps can be used to mask and expose the appropriate regions.​

[0092] In FIG. 15A and FIG. 15B , a second ILD 106 is deposited over the first ILD 96. In some embodiments, the second ILD 106 is a flowable film formed by FCVD. In some embodiments, the second ILD 106 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any appropriate method such as CVD, PECVD, etc. In some embodiments, prior to forming the second ILD 106, the gate stack (including the gate dielectric layer 100 and the corresponding overlying gate electrode 102) is recessed, forming a recess between the gate stack directly above and opposite portions of the first spacers 81. The gate mask 104, which includes one or more layers of dielectric material (e.g., silicon nitride, silicon oxynitride, etc.), is filled in the recess, and then a planarization process is performed to remove excess portions of the dielectric material extending above the first ILD 96. Subsequently formed gate contacts (e.g., the gate contacts 112 discussed below in relation to FIG. 16A and FIG. 16B , pass through the gate mask 104 to contact the top surface of the recessed gate electrode 102.

[0093] In FIG. 16A and FIG. 16BIn the embodiment of the present invention, a gate contact 112 and a source / drain contact 114 are formed through the second ILD 106 and the first ILD 96. An opening for the source / drain contact 114 is formed through the first ILD 96 and the second ILD 106, and an opening for the gate contact 112 is formed through the second ILD 106 and the gate mask 104. The openings can be formed using acceptable photolithography and etching techniques. A liner, such as a diffusion barrier layer, an adhesion layer, etc., and a conductive material are formed in the openings. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process, such as CMP, may be performed to remove excess material from the surface of the second ILD 106. The remaining liner and conductive material form the source / drain contacts 114 and the gate contact 112 in the openings. An annealing process may be performed to form silicide at the interface between the epitaxial source / drain regions 92 and the source / drain contacts 114. The source / drain contacts 114 are physically and electrically coupled to the epitaxial source / drain regions 92, and the gate contact 112 is physically and electrically coupled to the gate electrode 102. The source / drain contacts 114 and the gate contact 112 may be formed in different processes or may be formed in the same process. Although shown as being formed in the same cross-section, it should be understood that each of the source / drain contacts 114 and the gate contact 112 may be formed in different cross-sections, which may avoid shorting the contacts.

[0094] FIG. 16C to FIG. 16E The embodiment of thinning the fin 55 at various stages is shown. FIG. 16A and FIG. 16B structure. FIG. 16C Shown FIG. 3B In an embodiment, fins 55 are thinned simultaneously before forming STI regions 58. Portions of fins 55 in region 50N formed above and below the top surface of STI regions 58 may have continuous sidewalls at the same angle relative to the main surface of substrate 50. Portions of fins 55 in region 50P formed above and below the top surface of STI regions 58 may have sidewalls at different angles relative to the main surface of substrate 50. For example, FIG. 16C As shown, the sidewalls of the portion of the fin 55 in region 50P that is above the top surface of the STI region 58 and formed by the first epitaxial semiconductor material 52 can be more vertical than the sidewalls of the portion of the fin 55 in region 50P that is below the top surface of the STI region 58 and formed in the substrate 50.

[0095] FIG. 16D Shown FIG. 3Cembodiments, portions of the fins 55 in the region 50N that are formed above and below the top surface of the STI region 58 can have continuous sidewalls that are at the same angle relative to the major surface of the substrate 50. Portions of the fins 55 in the region 50P that are formed in the first epitaxial semiconductor material 52 and that are formed in the substrate 50 can have sidewalls that are at different angles relative to the major surface of the substrate 50 and that have a step difference in width. For example, as shown in FIG. 5A, the sidewalls of the portions of the fins 55 in the region 50P that are formed in the first epitaxial semiconductor material 52 can be more vertical than the sidewalls of the portions of the fins 55 in the region 50P that are formed in the substrate 50. Also, there can be a step difference between the widths of the portions of the fins 55 that are formed in the first epitaxial semiconductor material 52 and the portions of the fins 55 that are formed in the substrate 50, and the width of the portions of the fins 55 that are formed in the first epitaxial semiconductor material 52 is less than the width of the portions of the fins 55 that are formed in the substrate 50. FIG. 16D

[0096] FIG. 16E embodiments, portions of the fins 55 in the region 50N that are formed above and below the top surface of the STI region 58 can have continuous sidewalls that are at the same angle relative to the major surface of the substrate 50. Portions of the fins 55 in the region 50P that are formed in the first epitaxial semiconductor material 52 and that are formed in the substrate 50 can have sidewalls that are at different angles relative to the major surface of the substrate 50 and that have a step difference in width. For example, as shown in FIG. 5A, the sidewalls of the portions of the fins 55 in the region 50P that are formed in the first epitaxial semiconductor material 52 can be more vertical than the sidewalls of the portions of the fins 55 in the region 50P that are formed in the substrate 50. Also, there can be a step difference between the widths of the portions of the fins 55 that are formed in the first epitaxial semiconductor material 52 and the portions of the fins 55 that are formed in the substrate 50, and the width of the portions of the fins 55 that are formed in the first epitaxial semiconductor material 52 is less than the width of the portions of the fins 55 that are formed in the substrate 50. FIG. 4B FIG. 13C to FIG. 13E embodiments, portions of the fins 55 in the region 50N that are formed above and below the top surface of the STI region 58 can have continuous sidewalls that are at the same angle relative to the major surface of the substrate 50. Portions of the fins 55 in the region 50P that are formed in the first epitaxial semiconductor material 52 and that are formed in the substrate 50 can have sidewalls that are at different angles relative to the major surface of the substrate 50 and that have a step difference in width. For example, as shown in FIG. 5A, the sidewalls of the portions of the fins 55 in the region 50P that are formed in the first epitaxial semiconductor material 52 can be more vertical than the sidewalls of the portions of the fins 55 in the region 50P that are formed in the substrate 50. Also, there can be a step difference between the widths of the portions of the fins 55 that are formed in the first epitaxial semiconductor material 52 and the portions of the fins 55 that are formed in the substrate 50, and the width of the portions of the fins 55 that are formed in the first epitaxial semiconductor material 52 is less than the width of the portions of the fins 55 that are formed in the substrate 50. FIG. 16E

[0097] embodiments, portions of the fins 55 in the region 50N that are formed above and below the top surface of the STI region 58 can have continuous sidewalls that are at the same angle relative to the major surface of the substrate 50. Portions of the fins 55 in the region 50P that are formed in the first epitaxial semiconductor material 52 and that are formed in the substrate 50 can have sidewalls that are at different angles relative to the major surface of the substrate 50 and that have a step difference in width. For example, as shown in FIG. 5A, the sidewalls of the portions of the fins 55 in the region 50P that are formed in the first epitaxial semiconductor material 52 can be more vertical than the sidewalls of the portions of the fins 55 in the region 50P that are formed in the substrate 50. Also, there can be a step difference between the widths of the portions of the fins 55 that are formed in the first epitaxial semiconductor material 52 and the portions of the fins 55 that are formed in the substrate 50, and the width of the portions of the fins 55 that are formed in the first epitaxial semiconductor material 52 is less than the width of the portions of the fins 55 that are formed in the substrate 50. Figure 16E ​​​As shown, the sidewalls of the portions of the fin 55 in the region 50P that are formed above the top surface of the STI region 58 (e.g., the portions of the fin 55 that are formed in the first epitaxial semiconductor material 52) can be more vertical than the sidewalls of the portions of the fin 55 in the region 50P that are formed below the top surface of the STI region 58 (e.g., the portions of the fin 55 that are formed in the substrate 50). Further, there can be a step difference between the widths of the portions of the fin 55 that are formed below the top surface of the STI region 58 and the portions of the fin 55 that are formed above the top surface of the STI region 58, and the width of the portions of the fin 55 that are formed below the top surface of the STI region 58 is greater than the width of the portions of the fin 55 that are formed above the top surface of the STI region 58.

[0098] As described above, the fin 55 in the region 50P is formed with a graded germanium concentration, and the fin 55 in the region 50P is thinned using an etch process that has a higher etch rate as the germanium concentration increases, such that the fin 55 in the region 50P has a more rectangular profile and control of the process used to etch the fin 55 in the region 50P is improved. Inclusion of the fin 55 in the FinFET enables better gate control, reduces fin width variation, and reduces DIBL.

[0099] Figure 17 An example of a nanostructure (e.g., nanosheet, nanowire, wrap-around gate, etc.) field effect transistor (NSFET) is shown in accordance with some embodiments. The NSFET includes a nanostructure 255 over a substrate 250 (e.g., a semiconductor substrate). The nanostructure 255 includes second semiconductor layers 254A-254C that function as channel regions of the nanostructure 255. Shallow trench isolation (STI) regions 258 are disposed in the substrate 250, and the nanostructure 255 is disposed over and between adjacent STI regions 258. Although the STI regions 258 are depicted / illustrated as being separate from the substrate 250, as used herein, the term "substrate" can refer to a semiconductor substrate alone, or a combination of a semiconductor substrate and STI regions.

[0100] A gate dielectric layer 300 is along the top surfaces, sidewalls, and bottom surfaces of the nanostructure 255, e.g., on the top surfaces, sidewalls, and bottom surfaces of each of the second semiconductor layers 254A-254C, and along the top surfaces and sidewalls of portions of the substrate 250. A gate electrode 302 is over the gate dielectric layer 300. Epitaxial source / drain regions 292 are disposed on opposite sides of the nanostructure 255, the gate dielectric layer 300, and the gate electrode 302. Figure 17Further shown are reference cross-sections used in the subsequent figures. Cross-section A-A' is along the longitudinal axis of the gate electrode 302, and in a direction, for example, perpendicular to the direction of current flow between the epitaxial source / drain regions 292 of the NSFET. Cross-section B-B' is perpendicular to cross-section A-A', and along the longitudinal axis of the nanostructure 255 and in a direction, for example, of current flow between the epitaxial source / drain regions 292 of the NSFET. Cross-section C-C' is parallel to cross-section A-A', and extends through the epitaxial source / drain regions 292 of the NSFET. For clarity, the subsequent figures refer to these reference cross-sections.

[0101] Figures 18 to 35D is a cross-sectional view of an intermediate stage of manufacturing a NSFET, in accordance with some embodiments. Figure 18 Figure 19A Figure 19B Figure 20A Figure 20B Figure 21 Figure 31D Figure 35C and Figure 35D illustrates Figure 17 the reference cross-section A-A' shown in FIG. 1, including region 250N and region 250P. Figure 22A Figure 29A Figure 30A Figure 31A Figure 32A Figure 32C Figure 33A Figure 33C Figure 33E Figure 34A and Figure 35A are shown in region 250N or region 250P, along the reference cross-section A-A' shown in FIG. 1. Figure 17 Figure 22B Figure 23B Figure 24B Figure 25B Figure 26B Figure 26C Figure 27B Figure 27C Figure 28B Figure 28C Figure 29B Figure 29C Figure 30B Figure 30C Figure 31B Figure 31C Figure 31E Figure 32B Figure 32D Figure 33B Figure 33D Figure 33F Figure 34B and Figure 35B are shown in region 250N or region 250P, along the reference cross-section A-A' shown in FIG. 1. Figure 17 ​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​The illustrated similar cross-section B-B’ is shown. Figure 23A , Figure 24A , Figure 25A , Figure 26A , Figure 27A , Figure 28A and Figure 28D along Figure 17 the illustrated reference cross-section C-C’.

[0102] In Figure 18 , a substrate 250 is provided for forming an NSFET. The substrate 250 can be a semiconductor substrate, e.g., a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which can be doped (e.g., with p-type or n-type dopants) or undoped. The substrate 250 can be a wafer, e.g., a silicon wafer. In general, an SOI substrate is a layer of semiconductor material formed on an insulator layer. The insulator layer can be, e.g., a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is disposed on a substrate, which is typically a silicon or glass substrate. Other substrates can also be used, e.g., a multilayer substrate or a graded substrate. In some embodiments, the semiconductor material of the substrate 250 can include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide; or combinations thereof.

[0103] The substrate 250 has a region 250N and a region 250P. The region 250N can be used to form n-type devices, e.g., NMOS transistors, such as n-type NSFETs. The region 250P can be used to form p-type devices, e.g., PMOS transistors, such as p-type NSFETs. The region 250N can be physically separated from the region 250P (as shown by the partition 251), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be disposed between the region 250N and the region 250P.

[0104] The substrate 250 can be lightly doped with p-type or n-type impurities. An anti-punchthrough (APT) implant can be performed on an upper portion of the substrate 50 to form an APT region 253. During the APT implant, dopants can be implanted in the region 250N and the region 250P. The dopants can have a polarity opposite to that of the source / drain regions to be formed in each of the region 250N and the region 250P (e.g., described below with respect to Figures 28A-28DThe APT region 253 may be of a conductivity type opposite to that of the epitaxial source / drain region 292 discussed above. The APT region 253 may extend below the subsequently formed source / drain regions in the resulting NSFET, which will be formed in subsequent processing. The APT region 253 may be used to reduce leakage from the source / drain regions to the substrate 250. In some embodiments, the doping concentration in the APT region 253 may be from about 1×10 18 atoms / cm 3 to about 1×10 19 atoms / cm 3 For simplicity and clarity, the APT region 253 is not shown in subsequent figures.

[0105] Further in Figure 18 , a multilayer stack 256 is formed on a substrate 250. The multilayer stack 256 includes alternating first semiconductor layers 252 and second semiconductor layers 254 of different semiconductor materials. The first semiconductor layer 252 can be formed of a first semiconductor material, which can include, for example, silicon germanium (SiGe). The second semiconductor layer 254 can be formed of a second semiconductor material, which can include, for example, silicon (Si), silicon carbon (SiC), etc. In some embodiments, the first semiconductor layer 252 can be formed of a second semiconductor material, and the second semiconductor layer 254 can be formed of a first semiconductor material. For illustrative purposes, the multilayer stack 256 includes three first semiconductor layers 252 (e.g., first semiconductor layers 252A-252C) and three second semiconductor layers 254 (e.g., second semiconductor layers 254A-254C). In some embodiments, the multilayer stack 256 can include any number of first semiconductor layers 252 and second semiconductor layers 254. Each layer of the multilayer stack 256 can be epitaxially grown using a process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), etc. The thickness of each of the first semiconductor layers 252A-252C can be from about 2 nm to about 50 nm, from about 15 nm to about 25 nm, or from about 18 nm to about 22 nm. The thickness of each of the second semiconductor layers 254A-254C can be from about 2 nm to about 50 nm, from about 15 nm to about 25 nm, or from about 18 nm to about 22 nm.

[0106] The first semiconductor layers 252A-252C can be formed with a graded germanium concentration. For example, in some embodiments, the germanium concentration of each of the first semiconductor layers 252A-252C can gradually and continuously decrease from a bottom surface of the layer to a top surface of the layer. The percentage of germanium atoms in the first semiconductor layer 252A can range from about 90% at a bottom surface of the first semiconductor layer 252A to about 40% at a top surface of the first semiconductor layer 252A, from about 32% at a bottom surface of the first semiconductor layer 252A to about 15% at a top surface of the first semiconductor layer 252A, and the like. The percentage of germanium atoms in the first semiconductor layer 252B can range from about 60% at a bottom surface of the first semiconductor layer 252B to about 20% at a top surface of the first semiconductor layer 252B, from about 25% at a bottom surface of the first semiconductor layer 252B to about 8% at a top surface of the first semiconductor layer 252B, and the like. The percentage of germanium atoms in the first semiconductor layer 252C can range from about 50% at a bottom surface of the first semiconductor layer 252C to about 0% at a top surface of the first semiconductor layer 252C, from about 20% at a bottom surface of the first semiconductor layer 252C to about 8% at a top surface of the first semiconductor layer 252C, and the like.

[0107] In some embodiments, a ratio of the percentage of germanium atoms at a top surface of each of the first semiconductor layers 252A-252C to the percentage of germanium atoms at a bottom surface of each of the first semiconductor layers 252A-252C can range from about 1 : 1 to about 1 :4, or from about 1 :2 to about 1 :3. A ratio of the percentage of germanium atoms at a top surface of the first semiconductor layer 252C to the percentage of germanium atoms at a bottom surface of the first semiconductor layer 252A can range from about 1 :2 to about 1 :8, or from about 1 :3 to about 1 :5. As will be discussed in more detail below, the first semiconductor layers 252A-252C including the percentage of germanium atoms at the prescribed ratio results in nanostructures (e.g., the nanostructures 255 discussed below with reference to FIG. 3) that result in improved rectangular profiles, which enables better gate control, reduces nanostructure width variation, and reduces drain induced barrier lowering. Figures 19A to 20B

[0108] ​In embodiments in which the first semiconductor layers 252A-252C are deposited by CVD, the graded germanium concentration in the first semiconductor layers 252A-252C can be achieved by gradually reducing the flow rate of a germanium-containing precursor (e.g., germane (GeH4)) relative to the flow rate of a silicon-containing precursor (e.g., dichlorosilane (H2Cl2Si), silane (SiH4), etc.) during deposition of each of the first semiconductor layers 252A-252C. For example, at the beginning of the deposition process for depositing the first semiconductor layer 252A, the ratio of the flow rate of the germanium precursor to the flow rate of the silicon precursor can be about 1 to about 9, or about 1 to about 3, and at the end of the deposition process for depositing the first semiconductor layer 252C, the ratio of the flow rate of the germanium precursor to the flow rate of the silicon precursor can be about 0 to about 1, or about 0 to about 0.5.

[0109] For purposes of illustration, in a completed NSFET device, the second semiconductor layer 254 will be described as forming a channel region in the region 250N, and the first semiconductor layer 252 will be described as forming a channel region in the region 250P. The first semiconductor layer 252 can be a sacrificial layer in the region 250N, and the second semiconductor layer 254 can be a sacrificial layer in the region 250P, which can be subsequently removed. In some embodiments, the first semiconductor layer 252 can form a channel region in the region 250N and the region 250P, and the second semiconductor layer 254 can be a sacrificial layer. In some embodiments, the second semiconductor layer 254 can form a channel region in the region 250N and the region 250P, and the first semiconductor layer 252 can be a sacrificial layer.

[0110] In Figure 19A In some embodiments, the nanostmctures 255 can be formed by etching trenches in the multilayer stack 256 and the substrate 250. The etching can be any acceptable etching process, such as, for example, reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. The etching can be anisotropic.

[0111] The nanostructures 255 and substrate 250 can be patterned by any suitable method. For example, the nanostructures 255 and substrate 250 can be patterned using one or more photolithography processes, including a double patterning process or a multi-patterning process. Typically, the double patterning process or the multi-patterning process combines photolithography and a self-aligned process, allowing the creation of patterns with, for example, a smaller pitch than that obtainable using a single direct photolithography process. For example, in some embodiments, a sacrificial layer is formed over the substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the nanostructures 255 and substrate 250. In some embodiments, the mask (or other layer) can remain on the nanostructures 255 after the nanostructures 255 and substrate 250 are patterned. Figure 19A As shown, the nanostructures 255 in both the region 250N and the region 250P may have a tapered profile, wherein the width of the bottom of the nanostructure 255 is greater than the width of the top of the nanostructure 255 .

[0112] In the region 250N, the bottom width W of the nanostructure 255 is 18 The top width W may be from about 2.2 nm to about 100 nm, from about 25 nm to about 35 nm, or from about 28 nm to about 32 nm; 19 can be from about 2 nm to about 50 nm, from about 20 nm to about 30 nm, or from about 23 nm to about 27 nm; and the top width W 19 With bottom width W 18 The ratio of θ to θ may be from about 0.5 to about 2, or from about 0.7 to about 0.9. The nanostructures 255 in region 250N may be spaced apart by a pitch P3 of from about 2 nm to about 50 nm, or from about 15 nm to about 25 nm. The angle θ9 between the sidewalls of the nanostructures 255 in region 250N and the top surface of the substrate 250 may be from about 70° to about 85°, from about 78° to about 82°, from about 95° to about 120°, or from about 98° to about 102°. In region 250P, the bottom width W of the nanostructures 255 may be from about 1 nm to about 2 nm. 20 The top width W may be from about 2.2 nm to about 100 nm, from about 25 nm to about 35 nm, or from about 28 nm to about 32 nm; 21 can be from about 2 nm to about 50 nm, from about 20 nm to about 30 nm, or from about 23 nm to about 27 nm; and the top width W 21 With bottom width W 20The ratio of θ to θ can be from about 0.5 to about 2, or from about 0.7 to about 0.9. The nanostructures 255 in the region 250P can be spaced apart by a pitch P4 of from about 2 nm to about 50 nm, or from about 15 nm to about 25 nm. The angle θ between the sidewalls of the nanostructures 255 in the region 250P and the top surface of the substrate 250 is 10 The height H of the nanostructures 255 in the regions 250N and 250P may be about 70° to about 85°, about 78° to about 82°, about 95° to about 120°, or about 98° to about 102°. 10 The depth D1 may be about 10 nm to about 200 nm, or about 70 nm to about 90 nm. The substrate 250 may be etched to a depth D1 of about 30 nm to about 100 nm, or about 60 nm to about 70 nm below the top surface of the substrate 250 .

[0113] Figure 19B An embodiment is shown in which, after forming the nanostructures 255 and in the STI region (eg, as described below with respect to Figure 20A A thinning process is performed before the STI region 258 discussed above to thin the nanostructure 255. Figure 19B In the embodiment shown, the nanostructures 255 in the region 250N may be exposed to an etchant for thinning the nanostructures 255 in the region 250P, and the nanostructures 255 in the region 250P may be exposed to an etchant for thinning the fin in the region 250N.

[0114] exist Figure 19B In the first etching process, a first etching chemistry can be used to etch the exposed portions of the second semiconductor layers 254A-254C in the regions 250N and 250P. During the first etching process, the first semiconductor layers 252A-252C and the second semiconductor layers 254A-254C in both the regions 250N and 250P can be exposed to the first etching chemistry. It is desirable that the first etching selectivity is high in order to minimize etching of the first semiconductor layers 252A-252C. The first etching selectivity is the ratio of the etching rate (sometimes referred to as the trim rate) of the second semiconductor layers 254A-254C (formed of, for example, silicon) to the etching rate of the first semiconductor layers 252A-252C (formed of, for example, silicon germanium). For example, the first etching selectivity can be greater than about 5 and can be in the range of about 5 to about 20, or higher. The first etching process can be performed at a temperature in the range of about 5°C to about 100°C, for example, about room temperature (e.g., about 23°C). The nanostructures 255 may be exposed to the first etch chemistry for a duration of about 10 seconds to about 5 minutes, or about 45 seconds to about 75 seconds.

[0115] In some embodiments, the first etching chemistry may include a first etchant dissolved in a first solvent. The first etching chemistry may not contain an oxidizing agent. The first etchant may include a base or an acid. In embodiments where the first etchant includes a base, the first etchant may include a metal hydroxide (M n+ (OH - ) n ), amine derivatives, ammonium derivatives, combinations thereof, and the like. The metal hydroxide may include sodium hydroxide (NaOH), potassium hydroxide (KOH), lithium hydroxide (LiOH), rubidium hydroxide (RbOH), cesium hydroxide (CsOH), combinations thereof, and the like. The amine derivative may include ammonia (NH3), ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH, (CH3)4N(OH)), tetraethylammonium hydroxide (TEAH, (C2H5)4N(OH)), trimethyltetradecylammonium hydroxide (TTAH, (CH3)3(C 14 H 29 )N(OH)), tetrabutylammonium hydroxide (TBAH, (C4H9)4N(OH)), combinations thereof, and the like. In embodiments where the first etchant is a base, the pH of the first etch chemistry can be from about 7 to about 13, or from about 8 to about 10. The concentration of the first etchant in the first etch chemistry can range from about 0.01 M to about 20 M, or from about 0.5 M to about 1.5 M.

[0116] In embodiments where the first etchant comprises an acid, the first etchant may comprise hydrochloric acid (HCl), hydrofluoric acid (HF), sulfuric acid (H2SO4), phosphoric acid (H3PO4), nitric acid (HNO3), carboxylic acid derivatives (C n H 2n+1 COOH), combinations thereof, and the like. In embodiments where the first etchant is an acid, the pH of the first etch chemistry can be from about 0 to about 7, or from about 1 to about 3. The concentration of the first etchant in the first etch chemistry can range from about 0.01 M to about 20 M, or from about 0.5 M to about 1.5 M.

[0117] The first solvent may be used to assist in mixing and transporting the first etchant. The first solvent may not participate in the etching reaction itself. In certain embodiments, the first etching solvent may be a solvent such as deionized water. However, any suitable solvent may be used.

[0118] The first etching chemistry may further include an ionic surfactant or a nonionic surfactant, for example, a quaternary ammonium (NR4 + ), sulfate (SO4 2- ), sulfonate (R-SO3 - ), phosphate (-PO4 3- ), carboxylates (R-COO -), alcohol ethoxylates, alkylphenol ethoxylates, fatty acid ethoxylates, fatty amine ethoxylates, glycol esters, glycerol esters, combinations thereof, etc., which may be added to reduce the surface tension of the first etch chemistry. The concentration of the surfactant in the first etch chemistry may range from about 0.0001M to about 1M, or from about 0.0005M to about 0.002M.

[0119] Before etching the second semiconductor layers 254A-254C using the first etching process, each of the second semiconductor layers 254A-254C has a tapered profile, wherein the width of the bottom of the second semiconductor layers 254A-254C is greater than the width of the top of the second semiconductor layers 254A-254C (as previously described with respect to FIG. Figure 19A The first etching process may have the same etching rate at the top of the second semiconductor layers 254A-254C and at the bottom of the second semiconductor layers 254A-254C, so that the second semiconductor layers 254A-254C still have a tapered profile after etching the nanostructures 255 using the first etching process. The first etching process may etch the top surface and sidewalls of the second semiconductor layer 254C, so that the height of the second semiconductor layer 254C is less than the height of the second semiconductor layers 254A-254B.

[0120] After etching the nanostructures 255 in the regions 250N and 250P using the first etching process, the height H of the second semiconductor layers 254A- 254B is 13 The height H of the second semiconductor layer 254C may be from about 2 nm to about 50 nm, from about 15 nm to about 25 nm, or from about 18 nm to about 22 nm. 14 The width of the nanostructure 255 may be from about 2 nm to about 30 nm, from about 10 nm to about 20 nm, or from about 13 nm to about 17 nm. In some embodiments, the width of the nanostructure 255 may be different in the region 250N and the region 250P. For example, in the region 250N, the average width W of the second semiconductor layer 254A may be about 1 / 4 of the second semiconductor layer 254A. 22 The average width W of the second semiconductor layer 254B may be from about 2.2 nm to about 80 nm, from about 12 nm to about 22 nm, or from about 15 nm to about 19 nm. 23 The average width W of the second semiconductor layer 254C may be from about 2.2 nm to about 80 nm, from about 11 nm to about 21 nm, or from about 14 nm to about 18 nm; and 24 The width W may be from about 2.2 nm to about 50 nm, from about 10 nm to about 20 nm, or from about 13 nm to about 17 nm. 24 With width W 23 The ratio can be from about 0.5 to about 2, or from about 0.8 to about 1.0, and the width W 23 With width W 22The ratio of can be from about 0.5 to about 2, or from about 0.8 to about 1.0, and the width W 24 With width W 22 The ratio of can be from about 0.25 to about 4, or from about 0.64 to about 1.0. In the region 250P, the average width W of the second semiconductor layer 254A is 25 The average width W of the second semiconductor layer 254B may be from about 2.2 nm to about 80 nm, from about 12 nm to about 22 nm, or from about 15 nm to about 19 nm. 26 The average width W of the second semiconductor layer 254C may be from about 2.2 nm to about 80 nm, from about 11 nm to about 21 nm, or from about 14 nm to about 18 nm; and 27 The width W may be from about 2.2 nm to about 80 nm, from about 10 nm to about 20 nm, or from about 13 nm to about 17 nm. 27 With width W 26 The ratio of can be from about 0.5 to about 2, or from about 0.8 to about 1.0, and the width W 26 With width W 25 The ratio can be from about 0.5 to about 2, or from about 0.8 to about 1.0.

[0121] The bottom width W of the portion of the nanostructure 255 in the region 250N formed in the substrate 250 is 30 The width W may be from about 2.2 nm to about 100 nm, from about 15 nm to about 25 nm, or from about 18 nm to about 22 nm. 31 The top width W may be from about 2.2 nm to about 80 nm, from about 13 nm to about 23 nm, or from about 16 nm to about 20 nm. 31 With bottom width W 30 The ratio of θ can be from about 0.5 to about 2, or from about 0.8 to about 1.0. The angle θ between the sidewall of the portion of the nanostructure 255 in the region 250N formed in the substrate 250 and the top surface of the substrate 250 is 11 The angle of the nanostructure 255 in the region 250P may be from about 70° to about 85°, from about 78° to about 82°, from about 95° to about 120°, or from about 98° to about 102°. The bottom width W32 of the portion of the nanostructure 255 formed in the substrate 250 in the region 250P may be from about 2.2 nm to about 100 nm, from about 15 nm to about 25 nm, or from about 18 nm to about 22 nm, and the top width W 33 The angle θ between the sidewall of the portion of the nanostructure 255 in the region 250P formed in the substrate 250 and the top surface of the substrate 250 may be from about 2.2 nm to about 80 nm, about 13 nm to about 23 nm, or about 15 nm to about 20 nm. 12The ratio of the top width W 33 to the bottom width W 32 may be from about 0.5 to about 2, or about 0.8 to about 1.0.

[0122] Further in Figure 19B , the exposed portions of the first semiconductor layers 252A-252C in the regions 250N and 250P can be etched in a second etch process using a second etch chemical. During the second etch process, the first semiconductor layers 252A-252C and the second semiconductor layers 254A-254C in both the regions 250P and 250N can be exposed to the second etch chemical. A higher second etch selectivity, which is the ratio of the etch rate of the first semiconductor layers 252A-252C (formed of, e.g., silicon germanium) to the etch rate of the second semiconductor layers 254A-254C (formed of, e.g., silicon), is desired in order to minimize etching of the second semiconductor layers 254A-254C. For example, the second etch selectivity can be higher than about 5, and can be in a range of about 5 to about 20, or higher. The second etch process can be performed at a temperature in a range of about 5 °C to about 100 °C, e.g., about room temperature (e.g., about 23 °C).

[0123] In some embodiments, the second etch chemical can include an oxidizing agent and a second etchant dissolved in a second solvent. The nanostructures 255 can be simultaneously exposed to the oxidizing agent and the second etchant. In embodiments in which the nanostructures 255 are simultaneously exposed to the oxidizing agent and the second etchant, the nanostructures 255 can be exposed to the second etch chemical for a duration of about 30 seconds to about 2 minutes, or about 45 seconds to about 75 seconds. In some embodiments, the second etchant can be the same as the first etchant. The second etchant can be a base or an acid.

[0124] In embodiments in which the second etchant includes a base, the second etchant can include a metal hydroxide (M n+ (OH - ) n ), an amine derivative, an ammonium derivative, combinations thereof, or the like. The metal hydroxide can include sodium hydroxide (NaOH), potassium hydroxide (KOH), lithium hydroxide (LiOH), rubidium hydroxide (RbOH), cesium hydroxide (CsOH), combinations thereof, or the like. The amine derivative can include ammonia (NH3), ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH, (CH3)4N(OH)), tetraethylammonium hydroxide (TEAH, (C2H5)4N(OH)), trimethyltetradecylammonium hydroxide (TTAH, (CH3)3(C 14 H 29)N(OH)), tetrabutylammonium hydroxide (TBAH, (C4H9)4N(OH)), combinations thereof, and the like. In embodiments where the second etchant is basic, the pH of the second etch chemistry can be from about 7 to about 13, or about 8 to about 10. The concentration of the second etchant in the second etch chemistry can range from about 0.01 M to about 20 M, or about 0.5 M to about 1.5 M.

[0125] In embodiments where the second etchant includes an acid, the second etchant can include hydrochloric acid (HC1), hydrofluoric acid (HF), sulfuric acid (H2SO4), phosphoric acid (H3PO4), nitric acid (HNO3), carboxylic acid derivatives (COOH), combinations thereof, and the like. In embodiments where the second etchant is an acid, the pH of the second etch chemistry can be about 0 to about 7, or about 1 to about 3. The concentration of the second etchant in the second etch chemistry can range from about 0.01 M to about 20 M, or about 0.5 M to about 1.5 M. n H 2n+1 COOH), combinations thereof, and the like. In embodiments where the second etchant is an acid, the pH of the second etch chemistry can be about 0 to about 7, or about 1 to about 3. The concentration of the second etchant in the second etch chemistry can range from about 0.01 M to about 20 M, or about 0.5 M to about 1.5 M.

[0126] The oxidizing agent can include ozonated deionized water (DIO3), hydrogen peroxide (H2O2), other non-metallic oxidizing agents, combinations thereof, and the like. The concentration of the oxidizing agent in the second etch chemistry can range from about 0.0001 M to about 1 M, or about 0.0005 M to about 0.002 M. The inclusion of the oxidizing agent in addition to the second etchant can cause the first semiconductor layers 252A-252C to be selectively etched relative to the second semiconductor layers 254A-254C. The oxidizing agent can be used to oxidize the first semiconductor layers 252A-252C, forming a silicon germanium oxide in the first semiconductor layers 252A-252C, and then the second etchant can be used to etch the silicon germanium oxide material, thinning the first semiconductor layers 252A-252C. On the other hand, in the regions 250N, the oxidizing agent can be used to oxidize the second semiconductor layers 254A-254C, forming a silicon oxide in the second semiconductor layers 254A-254C, which is etched at a slower rate by the second etchant. Silicon can also be oxidized at a slower rate than silicon germanium, such that any silicon oxide layer formed in the second semiconductor layers 254A-254C is thinner than the oxide formed in the first semiconductor layers 252A-252C. Thus, the second semiconductor layers 254A-254C are substantially unthinned, while the first semiconductor layers 252A-252C are thinned.

[0127] A second solvent can be utilized to assist in mixing and delivering the oxidizing agent and the second etchant. The second solvent can not participate in the etching reaction itself. In particular embodiments, the second etch solvent can be a solvent such as deionized water, acetic acid (CH3COOH), and the like. In embodiments where the oxidizing agent includes ozonated deionized water, the deionized water can also serve as the solvent. Any suitable solvent can be used.

[0128] The second etching chemical can further include an ionic surfactant or a non-ionic surfactant, for example, a quaternary ammonium (NR4 + ), a sulfate (SO4 2- ), a sulfonate (R-SO3 - ), a phosphate (-PO4 3- ), a carboxylate (R-COO - ), an alcohol ethoxylate, an alkyl phenol ethoxylate, a fatty acid ethoxylate, a fatty amine ethoxylate, a glycol ester, a glycerol ester, combinations thereof, and the like, which can be added to reduce the surface tension of the second etching chemical. The concentration of the surfactant in the second etching chemical can range from about 0.01 M to about 20 M, or from about 0.5 M to about 1.5 M.

[0129] In particular embodiments, the second etching chemical can include hydrofluoric acid (HF), hydrogen peroxide (H2O2), and acetic acid (CH3COOH). The acetic acid can be a solvent in which the hydrofluoric acid and the hydrogen peroxide are dissolved. The hydrogen peroxide can be an oxidizing agent used to oxidize the first semiconductor layers 252A-252C. The hydrofluoric acid can be a second etchant used to thin the first semiconductor layers 252A-252C. The volume ratio of the hydrofluoric acid:hydrogen peroxide:acetic acid can be about 1 :2:3.

[0130] In further embodiments, in a cyclic process, the nanostructures 255 can be exposed to an oxidizing agent, then the oxidizing agent can be removed, and the nanostructures 255 can be exposed to a second etchant to thin the second semiconductor layers 254A-254C of the nanostructures 255. Exposing the nanostructures 255 to the oxidizing agent can oxidize the nanostructures 255 in the regions 250N and the regions 250P. Exposing the nanostructures 255 to the second etchant can selectively etch the oxide formed in the first semiconductor layers 252A-252C relative to the oxide formed in the second semiconductor layers 254A-254C.

[0131] The oxidizing agent used in the cyclic process can be the same as the oxidizing agent used in the process of simultaneously exposing the nanostructures 255 to the oxidizing agent and the second etchant described above. For example, the oxidizing agent can include ozonated deionized water (DIO3), hydrogen peroxide (H2O2), other non-metallic oxidizing agents, combinations thereof, and the like. The concentration of the oxidizing agent in the oxidizing agent can range from 0.0001 M to about 1 M, or from about 0.0005 M to about 0.002 M. As described previously, exposing the nanostructures 255 can oxidize the first semiconductor layers 252A-252C. The second semiconductor layers 254A-254C can also be oxidized, but can be oxidized at a slower rate than the first semiconductor layers 252A-252C.

[0132] The second etchant used in the cyclic process can be the same as or similar to the first etchant. The concentration of the second etchant can range from about 0.01 M to about 20 M, or about 0.5 M to about 1.5 M. Exposure of the nanostructure 255 to the second etchant thins the second semiconductor layers 254A-C. As previously discussed, the first semiconductor layers 252A-C can thin at a slower rate than the second semiconductor layers 254A-C.

[0133] For each cycle, the nanostructure 255 can be exposed to the oxidizing agent for a duration of from about 10 seconds to about 5 minutes, or about 45 seconds to about 75 seconds, and the nanostructure 255 can be exposed to the second etchant for a duration of from about 10 seconds to about 5 minutes, or about 45 seconds to about 75 seconds. The cyclic etching process can be repeated for up to 20 cycles, up to 10 cycles, 4 to 6 cycles, etc. Exposure of the nanostructure 255 to the oxidizing agent and then to the second etchant in the cyclic process can provide better control of the etching of the first semiconductor layers 252A-C. This results in improved gate control of the resulting NSFET, reduces nanostructure width variation, and results in reduced DIBL.

[0134] The second etching process can have an etch rate that depends on the germanium concentration in the first semiconductor layers 252A-C. For example, the second etching process can have a higher etch rate as the germanium concentration in the first semiconductor layers 252A-C increases. As previously discussed in the discussion related to Figure 18 As previously discussed in the discussion related to

[0135] Prior to etching the first semiconductor layers 252A-C with the second etching process, the first semiconductor layers 252A-C have a tapered profile, where the width of the bottom of each of the first semiconductor layers 252A-C is greater than the width of the top of each of the first semiconductor layers 252A-C (as previously discussed in the discussion related to Figure 19AThe first semiconductor layers 252A-252C are etched using a second etch process that has a higher etch rate at the bottom of each of the first semiconductor layers 252A-252C than at the top of each of the first semiconductor layers 252A-252C such that the first semiconductor layers 252A-252C have a more rectangular profile after the first semiconductor layers 252A-252C are etched using the second etch process.

[0136] After the first semiconductor layers 252A-252C are etched using the second etch process, the average width W of each of the first semiconductor layers 252A-252C in the region 250N 28 may be from about 2.2 nm to about 80 nm, about 23 nm to about 33 nm, or about 26 nm to about 30 nm. The ratio of the width W of the top first semiconductor layer 252C to the bottom semiconductor layer 252A 28 may be from about 0.8 to about 1.2, or about 0.9 to about 1.1. The average width W of each of the first semiconductor layers 252A-252C in the region 250P 29 may be from about 2.2 nm to about 80 nm, about 23 nm to about 33 nm, or about 26 nm to about 30 nm. The ratio of the width W of the top first semiconductor layer 252C to the bottom semiconductor layer 252A 29 may be from about 0.8 to about 1.2, or about 0.9 to about 1.1. The height H of each of the first semiconductor layers 252A-252C in the region 250N and the region 250P 15 may be from about 2 nm to about 50 nm, about 15 nm to about 25 nm, or about 18 nm to about 22 nm.

[0137] The first semiconductor layers 252A-252C are formed with a gradient germanium concentration and are thinned using an etch process that has a higher etch rate as the germanium concentration increases such that the first semiconductor layers 252A-252C have a more rectangular profile and improved control over the process used to etch the first semiconductor layers 252A-252C. The inclusion of the first semiconductor layers 252A-252C in the NSFET enables better gate control, reduces nanowire width variation, and reduces DIBL.

[0138] Figure 20A Embodiments are shown in which the nanowires 255 are not thinned until after the shallow trench isolation (STI) regions 258 are formed. For example, the nanowires 255 can be thinned after the STI regions 258 are formed as will be discussed below with respect to Figure 20B or removed after the dummy gate stacks are removed as will be discussed below with respect to Figure 31D and Figure 31E Figure 22A ​and Figure 22B A thinning process is performed after the dummy gate stack, including the dummy gate 272 and the dummy dielectric layer 260, is discussed. However, it should be appreciated that the steps performed in Figure 19B on the nanostructures 255 that have been thinned as described above with reference to Figure 20A and subsequent figures.

[0139] In Figure 20A A shallow trench isolation (STI) region 258 is formed adjacent to the nanostructures 255 and the patterned portions of the substrate 250. The STI region 258 can be formed by forming an insulating material (not shown separately) over the substrate 250 and between adjacent patterned portions of the substrate 250 / nanostructures 255. The insulating material can be an oxide (e.g., silicon oxide), a nitride, etc., or a combination thereof, and can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition in a remote plasma system and post-curing to convert the deposited material to another material, such as an oxide), etc., or a combination thereof. Other insulating materials formed by any acceptable process can be used. In some embodiments, the insulating material is silicon oxide formed by a FCVD process. Once the insulating material is formed, an annealing process can be performed. In some embodiments, the insulating material is formed such that excess insulating material covers the nanostructures 255. The insulating material can include a single layer or can take multiple layers. For example, in some embodiments, a liner (not shown separately) can first be formed along the surfaces of the substrate 250 and the nanostructures 255. Thereafter, a fill material such as described above can be formed over the liner.

[0140] A removal process is then applied to the insulating material to remove the excess insulating material over the nanostructures 255. In some embodiments, a planarization process, such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, etc., can be employed. The planarization process can planarize the insulating material and the nanostructures 255. The planarization process exposes the nanostructures 255 such that the top surfaces of the nanostructures 255 and the insulating material are flush after the planarization process is completed.

[0141] The insulating material is then recessed to form the STI region 258 as Figure 20AThe STI regions 258 shown. The insulating material is recessed so that the upper portions of the nanostructures 255 and the substrate 250 protrude from between adjacent STI regions 258. In addition, the top surface of the STI regions 258 can have a flat surface (as shown), a convex surface, a concave surface (e.g., a dished shape), or a combination thereof. The top surface of the STI regions 258 can be formed to be flat, convex, and / or concave by appropriate etching. The STI regions 258 can be recessed using an acceptable etching process, for example, an etching process that is selective to the material of the insulating material (e.g., an etching process that etches the material of the insulating material at a faster rate than the material of the nanostructures 255 and the substrate 250). For example, oxide removal using an acid such as dilute hydrofluoric acid (dHF) can be employed. The height H of the STI regions 258 is preferably 0.01-0.02. 12 It may be from about 30 nm to about 100 nm, or from about 55 nm to about 75 nm.

[0142] Figure 20B An embodiment is shown in which a thinning process is performed after forming the STI region 258 to thin the nanostructure 255, rather than as described above with reference to FIG. Figure 19B The thinning process discussed is performed after forming the nanostructures 255 and before forming the STI regions 258. Figure 20B In the embodiment shown, the nanostructures 255 in the region 250N may be exposed to an etchant for thinning the nanostructures 255 in the region 250P, and the nanostructures 255 in the region 250P may be exposed to an etchant for thinning the nanostructures 255 in the region 250N.

[0143] exist Figure 20B In the embodiment shown, the nanostructures 255 in both the region 250N and the region 250P are similar to those described above. Figure 19B After the first etching process, the second semiconductor layers 254A-254C in the regions 250N and 250P may have the same or similar properties as described above. Figure 19B After the second etching process, the first semiconductor layers 252A-252C in the regions 250N and 250P may have the same or similar dimensions as those discussed above with respect to the second semiconductor layers 254A-254C. Figure 19B The first semiconductor layers 252A-252C are the same or similar in size as discussed above. For example, the sizes of the first semiconductor layers 252A-252C and the sizes of the second semiconductor layers 254A-254C may be the same as discussed above. Figure 19B The dimensions in question are within about 10 nm.

[0144] The first semiconductor layers 252A-252C are formed with a graded germanium concentration, and are thinned using an etch process that has a higher etch rate as the germanium concentration increases, such that the first semiconductor layers 252A-252C have a more rectangular profile, and control of the process used to etch the first semiconductor layers 252A-252C is improved. Inclusion of the first semiconductor layers 252A-252C in the NSFETs enables better gate control, reduces nanostucture width variation, and reduces DIBL.

[0145] The portions of the nanostuctures 255 in the regions 250N and 250P that are surrounded by the STI regions 258 can remain unchanged after the thinning process is performed. For example, the portions of the nanostuctures 255 disposed below the top surfaces of the STI regions 258 can have a similar or identical width as discussed above with respect to Figure 19A Figure 20B As shown, the width of the nanostuctures 255 that are flush with the top surfaces of the STI regions 258 can have a step change due to the thinning process.

[0146] Figure 21 Embodiments are shown in which the nanostuctures 255 are not thinned until after a dummy gate stack (e.g., the dummy gate stack including the dummy gate 272 and the dummy dielectric layer 260 discussed below with respect to Figure 22A and Figure 22B is formed). For example, the thinning process can be performed after the dummy gate stack is removed, as will be discussed below with respect to Figures 31D to 31E However, it should be understood that the steps performed in Figure 19B and subsequent figures can be performed on nanostuctures 255 that have already been thinned as described above with respect to Figure 20B Figure 21

[0147] In Figure 21 ​​​In this example, dummy dielectric layer 260 is formed on nanostmcture 255 and substrate 250. Dummy dielectric layer 260 can be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and can be deposited or thermally grown according to acceptable techniques. Dummy gate layer 262 is formed over dummy dielectric layer 260, and mask layer 264 is formed over dummy gate layer 262. Dummy gate layer 262 can be deposited over dummy dielectric layer 260 and then planarized, for example, by an implantation-CMP process or the like. Mask layer 264 can be deposited over dummy gate layer 262. Dummy gate layer 262 can be a conductive material or a non-conductive material, and can be selected from a group including amorphous silicon, polysilicon, poly-SiGe, metal nitride, metal silicide, metal oxide, and metal. Dummy gate layer 262 can be deposited by physical vapor deposition (PVD), CVD, sputter deposition, or other known techniques used in the art to deposit selected materials. Dummy gate layer 262 can be made of other materials that have a high etch selectivity with respect to the material of STI region 258. Mask layer 264 can include, for example, silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer 262 and a single mask layer 264 are formed across region 250N and region 250P. Note that dummy dielectric layer 260 is shown as covering only nanostmcture 255 and substrate 250 for illustrative purposes only. In some embodiments, dummy dielectric layer 260 can be deposited such that dummy dielectric layer 260 covers STI region 258 and extends between dummy gate layer 262 and STI region 258.

[0148] 22A to 35D Various additional steps in the fabrication of an embodiment device are shown. Figures 22A to 25B Figure 26A Figure 27A Figure 28A Figure 28D Figure 29A Figure 30A Figure 31A Figure 31E Figure 34A and Figure 35A Features in region 250N or region 250P are shown. For example, Figures 22A to 25B Figure 26A Figure 27A Figure 28A Figure 28D Figure 29A Figure 30A Figure 31A Figure 31E Figure 34A and Figure 35A ​​​​​​​​​​​​​​​​​​The structures shown in the middle can apply to both region 250N and region 250P. Differences in the structures of region 250N and region 250P, if any, are described in the text accompanying each figure. For example, Figure 26B , Figure 27B , Figure 28B , Figure 29B , Figure 30B , Figure 31B , Figure 32A , Figure 32B , Figure 33A , Figure 33B , Figure 33E , Figure 33F , Figure 34B and Figure 35B show structures in region 250N, Figure 26C , Figure 27C , Figure 28C , Figure 29C , Figure 30C , Figure 31C , Figure 32C , Figure 32D , Figure 33C and Figure 33D show structures in region 250P, and Figure 31D , Figure 35C and Figure 35D show structures in region 250N and region 250P.

[0149] In Figure 22A and Figure 22B , the mask layer 264 (see Figure 21 ) can be patterned using acceptable lithography and etching techniques to form a mask 274. The pattern of the mask 274 can be transferred to the dummy gate layer 262 using acceptable etching techniques to form a dummy gate 272. In some embodiments, the pattern of the mask 274 can also be transferred to the dummy dielectric layer 260. The dummy gate 272 covers a corresponding channel region of the nanostructure 255. In some embodiments, in region 250N, the channel region can be formed in the second semiconductor layer 254A-254C that includes the second semiconductor material, and in region 250P, the channel region can be formed in the first semiconductor layer 252A-252C that includes the first semiconductor material. The pattern of the mask 274 can be used to physically separate each dummy gate 272 from an adjacent dummy gate 272. The dummy gate 272 can have a length direction that is substantially perpendicular to a length direction of the corresponding nanostructure 255. The dummy dielectric layer 260, the dummy gate 272, and the mask 274 can be collectively referred to as a “dummy gate stack.”

[0150] In Figure 23A and Figure 23B , in Figure 22A and Figure 22B A first spacer layer 280 and a second spacer layer 282 are formed over the structures shown. In Figure 23A and Figure 23B , the first spacer layer 280 is formed on the top surface of the STI region 258, the nanostmcture 255, and the top surface and sidewalls of the mask 274, and the sidewalls of the substrate 250, dummy gate 272, and dummy dielectric layer 260. The second spacer layer 282 is deposited over the first spacer layer 280. The first spacer layer 280 can be formed by thermal oxidation, or deposited by CVD, ALD, etc. The first spacer layer 280 can be formed of silicon oxide, silicon nitride, silicon oxynitride, etc. The second spacer layer 282 can be deposited by CVD, ALD, etc. The second spacer layer 282 can be formed of silicon oxide, silicon nitride, silicon oxynitride, etc.

[0151] In Figure 24A and Figure 24B , the first spacer layer 280 and the second spacer layer 282 are etched to form first spacers 281 and second spacers 283. The first spacer layer 280 and the second spacer layer 282 can be etched using an appropriate etching process, such as an anisotropic etching process (e.g., a dry etching process), etc. The first spacers 281 and the second spacers 283 can be disposed on the sidewalls of the nanostmcture 255, the dummy dielectric layer 260, the dummy gate 272, and the mask 274. The first spacers 281 and the second spacers 283 can have different heights proximate the nanostmcture 255 and the dummy gate stack due to the etching process used to etch the first spacer layer 280 and the second spacer layer 282, as well as different heights between the nanostmcture 255 and the dummy gate stack. Specifically, as shown in Figure 24A and Figure 24B , in some embodiments, the first spacers 281 and the second spacers 283 can extend partially up the nanostmcture 255 sidewalls, and can extend to the top surface of the dummy gate stack. In some embodiments, the first spacers 281 and the second spacers 283 can extend partially up the sidewalls of the dummy gate stack. For example, the top surfaces of the first spacers 281 and the second spacers 283 can be disposed above the top surface of the dummy gate 272 and below the top surface of the mask 274.

[0152] In Figure 25A and Figure 25B , a first recess 286 is formed in the nanostmcture 255 and the substrate 250. The first recess 286 can extend through the first semiconductor layers 252A-252C and the second semiconductor layers 254A-254C. In some embodiments, the first recess 286 can also extend into the substrate 250. As shown in Figure 25AAs shown, the top surface of the STI region 258 can be flush with the top surface of the substrate 250. In some embodiments, the substrate 250 can be etched such that the bottom surface of the first recess 286 is disposed below the top surface of the STI region 258, etc. The first recess 286 can be formed by etching the nanostructure 255 and / or the substrate 250 using one or more anisotropic etching processes (e.g., RIE, NBE, etc.). During the etching process used to form the first recess 286, the first spacers 281, the second spacers 283, and the mask 274 mask portions of the nanostructure 255 and the substrate 250. A single etching process can be used to etch each layer in the multi-layer stack 256. In some embodiments, multiple etching processes can be used to etch the layers of the multi-layer stack 256. A timed etching process can be used to stop etching of the first recess 286 after the first recess 286 reaches a desired depth.

[0153] In Figures 26A to 26C some embodiments, portions of the sidewalls of the first semiconductor layers 252A-252C and the second semiconductor layers 254A-254C of the multi-layer stack 256 are etched to form sidewall recesses 288. For example, as shown in Figure 26B and Figure 26C the sidewalls of the first semiconductor layers 252A-252C formed of the first semiconductor material in the region 250N and the sidewalls of the second semiconductor layers 254A-254C formed of the second semiconductor material in the region 250P are etched to form the sidewall recesses 288. A mask, such as a photoresist, can be formed over the region 250P while the sidewall recesses 288 are formed in the first semiconductor layers 252A-252C in the region 250N. The mask can then be removed. Subsequently, a mask, such as a photoresist, can be formed over the region 250N while the sidewall recesses 288 are formed in the second semiconductor layers 254A-254C in the region 250P. The mask can then be removed.

[0154] Although the sidewalls of the first semiconductor layers 252A-252C and the second semiconductor layers 254A-254C adjacent to the sidewall recesses 288 are Figure 26B and Figure 26C252C, the sidewalls may be concave or convex. The sidewalls may be etched using an isotropic etching process, such as a wet etch, a dry etch, or the like. The etchant used to etch the first semiconductor layers 252A-252C may be selective to the first semiconductor material, such that the second semiconductor layers 254A-254C and the substrate 250 remain relatively unetched compared to the first semiconductor layers 252A-252C. Similarly, the etchant used to etch the second semiconductor layers 254A-254C may be selective to the second semiconductor material, such that the first semiconductor layers 252A-252C and the substrate 250 remain relatively unetched compared to the second semiconductor layers 254A-254C.

[0155] exist Figures 27A to 27C In the embodiment, a first inner spacer 290 is formed in the sidewall groove 288. Figures 26A to 26C An inner spacer layer (not separately shown) is deposited over the structure shown to form a first inner spacer 290. The inner spacer layer can be deposited by a conformal deposition process such as CVD, ALD, or the like. The inner spacer layer can include a material such as silicon nitride or silicon oxynitride, but any suitable material can be utilized, for example, a low dielectric constant (low-k) material having a k value of less than about 3.5. The inner spacer layer can then be etched to form the first inner spacer 290. Although the outer sidewalls of the first inner spacer 290 are shown as being aligned with the second semiconductor layers 254A-254C ( Figure 27B ) and the first semiconductor layers 252A-252 ( Figure 27C Although the outer sidewalls of the first inner spacer 290 are flush with the sidewalls of the second semiconductor layers 254A-254C and the first semiconductor layers 252A-252C, the outer sidewalls of the first inner spacer 290 may extend beyond the sidewalls of the second semiconductor layers 254A-254C and the first semiconductor layers 252A-252C or be recessed from the sidewalls of the second semiconductor layers 254A-254C and the first semiconductor layers 252A-252C. Figure 27B and Figure 27C Although shown as straight in FIG, the outer sidewalls of the first inner spacer 290 may be concave or convex. The inner spacer layer may be etched by an anisotropic etching process such as RIE, NBE, or the like.

[0156] The first inner spacer 290 may be used to prevent the subsequent etching of source / drain regions (eg, as described below) that are subsequently formed by a subsequent etching process. 28A to 28D The first inner spacer 290 can also prevent the subsequently formed gate electrode (e.g., as discussed below) from being damaged by the epitaxial source / drain region 292. Figures 33A to 33F The gate electrode 302 discussed is insulated from the subsequently formed epitaxial source / drain regions 292, which prevents short circuits in the resulting NSFET.

[0157] In 28A to 28D some embodiments, epitaxial source / drain regions 292 are formed in first recesses 286 to apply stress on second semiconductor layers 254A-254C and first semiconductor layers 252A-252C of nanostmctures 255 to improve performance. As shown in Figure 28B and Figure 28C embodiments, first spacers 281 are used to separate epitaxial source / drain regions 292 from dummy gates 272 by an appropriate lateral distance so that epitaxial source / drain regions 292 do not short the gates of the resulting NSFETs that are subsequently formed.

[0158] Epitaxial source / drain regions 292 in region 250N (e.g., NMOS region) can be formed by masking region 250P (e.g., PMOS region). Epitaxial source / drain regions 292 are then epitaxially grown in first recesses 286. Epitaxial source / drain regions 292 can include any acceptable material, such as a material suitable for n-type NSFETs. For example, if second semiconductor layers 254A-254C are silicon, epitaxial source / drain regions 292 can include a material that applies tensile strain on second semiconductor layers 254A-254C, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. Epitaxial source / drain regions 292 can have a surface that protrudes from the respective surface of multilayer stack 256 and can have facets.

[0159] Epitaxial source / drain regions 292 in region 250P (e.g., PMOS region) can be formed by masking region 250N (e.g., NMOS region). Epitaxial source / drain regions 292 are then epitaxially grown in first recesses 286. Epitaxial source / drain regions 292 can include any acceptable material, such as a material suitable for p-type NSFETs. For example, if second semiconductor layers 254A-254C are silicon germanium, epitaxial source / drain regions 292 can include a material that applies compressive strain on second semiconductor layers 254A-254C, such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin, etc. Epitaxial source / drain regions 292 can also have a surface that protrudes from the respective surface of multilayer stack 256 and can have facets.

[0160] Epitaxial source / drain regions 292 can be implanted with dopants to form source / drain regions, similar to the process previously discussed for forming lightly doped source / drain regions, followed by annealing. The impurity concentration of the source / drain regions can be about 1 x 1018atoms / cm3to about 1 x 1021atoms / cm3. 19 atoms / cm 3and about 1×10 21 atoms / cm 3 The n-type and / or p-type impurities used for the source / drain regions can be any of the impurities previously discussed. In some embodiments, the epitaxial source / drain regions 292 can be doped in situ during growth.

[0161] As a result of the epitaxial process used to form epitaxial source / drain regions 292 in regions 250N and 250P, the upper surfaces of epitaxial source / drain regions 292 have facets that extend laterally outward beyond the sidewalls of nanostructures 255. In some embodiments, these facets allow adjacent epitaxial source / drain regions 292 of the same NSFET to merge, e.g., Figure 28A In some embodiments, adjacent epitaxial source / drain regions 292 remain separated after the epitaxial process is completed, as shown in FIG. Figure 28D As shown. Figure 28A and Figure 28D In the embodiment shown, first spacers 281 can be formed to cover the sidewalls of nanostructures 255 and portions of substrate 250 extending over STI regions 258, thereby preventing epitaxial growth. In some embodiments, the spacer etch used to form first spacers 281 can be adjusted to remove spacer material to allow the region of epitaxial growth to extend to the surface of STI regions 258.

[0162] exist Figures 29A to 29C In the embodiment, the first interlayer dielectric (ILD) 296 is deposited on Figure 22A 、 Figure 28B and Figure 28C Above the structure shown ( 23A to 28D The process will not change Figure 22A , which shows a cross-section of the dummy gate 272 and the multilayer stack 256 protected by the dummy gate 272). The first ILD 296 can be formed of a dielectric material and can be deposited by any suitable method such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL) 294 is disposed between the first ILD 296 and the epitaxial source / drain regions 292, the mask 274, and the first spacer 281. The CESL 294 may include a dielectric material having a different etch rate than the material of the overlying first ILD 296, such as silicon nitride, silicon oxide, silicon oxynitride, etc.

[0163] exist Figures 30A to 30CDuring the planarization process, a planarization process such as CMP may be performed to make the top surface of the first ILD 296 flush with the top surface of the dummy gate 272 or the mask 274. The planarization process may also remove the mask 274 on the dummy gate 272 and the portion of the first spacer 281 along the sidewall of the mask 274. After the planarization process, the top surfaces of the dummy gate 272, the first spacer 281, and the first ILD 296 are flush. Therefore, the top surface of the dummy gate 272 is exposed through the first ILD 296. In some embodiments, the mask 274 may remain, in which case the planarization process makes the top surface of the first ILD 296 flush with the top surfaces of the mask 274 and the first spacer 281.

[0164] exist Figures 31A to 31C In the embodiment of the present invention, dummy gates 272 and mask 274 (if present) are removed in one or more etching steps, thereby forming second recesses 298. Portions of dummy dielectric layer 260 in second recesses 298 may also be removed. In some embodiments, dummy gates 272 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using one or more reactive gases that selectively etches dummy gates 272 at a faster rate than first ILD 296 or first spacers 281. Each second recess 298 exposes and / or overlies portions of multilayer stack 256 that serve as channel regions in the subsequently completed NSFET. The portions of multilayer stack 256 that serve as channel regions are disposed between adjacent pairs of epitaxial source / drain regions 292. During removal, dummy dielectric layer 260 may serve as an etch stop when etching dummy gates 272. Dummy dielectric layer 260 may then be removed after removal of dummy gates 272.

[0165] Figure 31D and Figure 31E An embodiment is shown in which a thinning process is performed after removing the dummy gate stack to thin the nanostructure 255, rather than as described above with reference to FIG. Figure 19B After forming the nanostructures 255 and before forming the STI regions 258, as discussed above, or as discussed above with reference to Figure 20B The thinning process discussed is performed after forming the STI regions 258. Figure 31D and Figure 31E In the embodiment shown, the nanostructures 255 in the region 250N may be exposed to an etchant for thinning the nanostructures 255 in the region 250P, and the nanostructures 255 in the region 250P may be exposed to an etchant for thinning the nanostructures 255 in the region 250N.

[0166] exist Figure 31D and Figure 31EIn the embodiment shown, the nanostructures 255 in both the region 250N and the region 250P are similar to those described above. Figure 19B After the first etching process, the second semiconductor layers 254A-254C in the region 250N and the region 250P may have the same or similar properties as described above. Figure 19B After the second etching process, the first semiconductor layers 252A-252C in the regions 250N and 250P may have the same dimensions as discussed above. Figure 19B The first semiconductor layers 252A-252C discussed are of the same size.

[0167] like Figure 31E As shown, the thinning of the nanostructure 255 may recess the exposed portion of the top surface of the second semiconductor layer 254C between the second spacers 283. Figure 31E In the embodiment of the present invention, a groove is formed in the top portion of the second semiconductor layer 254C. The depth of the groove can be greatest at a point between the second spacers 283. The depth of the groove can become shallower as it gets closer to the second spacers 283. The second semiconductor layer 254C can be recessed below the topmost surface of the second semiconductor layer 254C in both the region 250N and the region 250P to a depth D4 of from about 5 nm to about 40 nm, from about 5 nm to about 15 nm, or from about 8 nm to about 12 nm.

[0168] First semiconductor layers 252A-252C are formed with a gradient germanium concentration and thinned using an etching process having a higher etch rate as the germanium concentration increases, resulting in a more rectangular profile for first semiconductor layers 252A-252C and improved control over the process for etching first semiconductor layers 252A-252C. Including first semiconductor layers 252A-252C in NSFETs enables better gate control, reduces nanostructure width variation, and reduces DIBL.

[0169] Figures 32A to 32D An embodiment is shown in which the nanostructure 255 is not thinned after the dummy gate stack is removed. Figures 32A to 32D, the first semiconductor layers 252A-252C are removed from the region 250N, and the second semiconductor layers 254A-254C are removed from the region 250P, thereby extending the second recess 298. A mask such as a photoresist may be formed over the region 250P, while the first semiconductor layers 252A-252C are removed from the region 250N. The mask may then be removed. Subsequently, a mask such as a photoresist may be formed over the region 250N, while the second semiconductor layers 254A-254C are removed from the region 250P. The mask may then be removed.

[0170] The layers of the multilayer stack 256 may be removed by an isotropic etching process (e.g., wet etching, etc.). The etchant used to remove the first semiconductor layers 252A-252C may be selective to the material of the second semiconductor layers 254A-254C, while the etchant used to etch the second semiconductor layers 254A-254C may be selective to the material of the first semiconductor layers 252A-252C. In embodiments where the first semiconductor layers 252A-252C include a first semiconductor material (e.g., SiGe, etc.) and the second semiconductor layers 254A-254C include a second semiconductor material (e.g., Si, SiC, etc.), the layers of the multilayer stack 256 in the region 250N may be removed using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc., and the layers of the multilayer stack 256 in the region 250P may be removed using a diluted ammonium hydroxide-hydrogen peroxide mixture (APM), a sulfuric acid-hydrogen peroxide mixture (SPM), etc. The first semiconductor layers 252A-252C may be removed using plasma (e.g., plasma formed from hydrogen (H2) or the like). The second semiconductor layers 254A-254C may be removed using a solution including hydrofluoric acid (HF) and hydrogen peroxide (H2O2), a solution including hydrofluoric acid and nitric acid (HNO3) and water (H2O), or the like.

[0171] exist Figures 33A to 33D In the embodiment, a gate dielectric layer 300 and a gate electrode 302 are formed for replacing the gate. Figure 33E Shown Figure 33A A detailed view of area 301, and Figure 33F Shown Figure 33B A detailed view of area 303. Figure 33A and Figure 33B In the illustrated region 250N, the gate dielectric layer 300 is conformally deposited in the second recess 298, for example, on the top surface of the STI region 258, on the top surface of the substrate 250, and on the top surface, sidewalls, and bottom surface of the second semiconductor layers 254A-254C. Figure 33C and Figure 33DIn the depicted region 250P, a gate dielectric layer 300 is conformally deposited in the second recess 298, e.g., on the top surface of the STI region 258, and on the top surfaces, sidewalls, and bottom surfaces of the first semiconductor layers 252A-252C.

[0172] According to some embodiments, the gate dielectric layer 300 includes silicon oxide, silicon nitride, or multiple layers thereof. In some embodiments, the gate dielectric layer 300 includes a high-k dielectric material, and in these embodiments, the gate dielectric layer 300 can have a k value greater than about 7.0, and can include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. Methods of forming the gate dielectric layer 300 can include molecular beam deposition (MBD), ALD, PECVD, etc. In embodiments in which portions of the dummy dielectric layer 260 remain in the second recess 298, the gate dielectric layer 300 includes the material of the dummy dielectric layer 260 (e.g., Si02).

[0173] A gate electrode 302 is deposited over the gate dielectric layer 300, and fills the remaining portions of the second recess 298. The gate electrode 302 can include a metal-containing material, e.g., titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers thereof. For example, although a single layer of the gate electrode 302 is shown in Figures 33A to 33D , the gate electrode 302 can include any number of liner layers 302A, any number of work function adjustment layers 302B, and a fill material 302C, as shown in Figure 33E , and Figure 33F After filling the second recess 298, a planarization process such as CMP can be performed to remove excess portions of the material of the gate electrode 302 and the gate dielectric layer 300, which are above the top surface of the first ILD 296. The material of the gate electrode 302 and the remaining portions of the gate dielectric layer 300 thereby form a replacement gate for the resulting NSFET. The gate electrode 302 and the gate dielectric layer 300 can be collectively referred to as a "gate stack." The gate and the gate stack can extend along the sidewalls of the channel region 268 of the nanostmcture 255.

[0174] Formation of the gate dielectric layers 300 in the regions 250N and 250P can occur simultaneously, such that the gate dielectric layers 300 in each region are formed of the same material, and formation of the gate electrodes 302 can occur simultaneously, such that the gate electrodes 302 in each region are formed of the same material. In some embodiments, the gate dielectric layers 300 in each region can be formed by different processes, such that the gate dielectric layers 300 can be different materials, and / or the gate electrodes 302 in each region can be formed by different processes, such that the gate electrodes 302 can be different materials. When different processes are used, various masking steps can be used to mask and expose the appropriate regions.

[0175] In Figure 34A and Figure 34B , a second ILD 306 is deposited over the first ILD 296. In some embodiments, the second ILD 306 is a flowable film formed by FCVD. In some embodiments, the second ILD 306 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any appropriate method such as CVD, PECVD, etc. In some embodiments, prior to forming the second ILD 306, the gate stacks (including the gate dielectric layers 300 and the respective overlying gate electrodes 302) are recessed, forming a recess between the gate stacks directly above and opposing portions of the first spacers 281. The gate mask 304, which includes one or more layers of dielectric material (e.g., silicon nitride, silicon oxynitride, etc.), is filled in the recess, and then a planarization process is performed to remove excess portions of the dielectric material extending over the first ILD 296. Subsequently formed gate contacts (e.g., the gate contacts 312 discussed below in relation to Figure 35A and Figure 35B The gate contacts pass through the gate mask 304 to contact the top surfaces of the recessed gate electrodes 302.

[0176] In Figure 35A and Figure 35BIn the embodiment, gate contact 312 and source / drain contacts 314 are formed through second ILD 306 and first ILD 296. Openings for source / drain contacts 314 are formed through first ILD 296 and second ILD 306, and openings for gate contact 312 are formed through second ILD 306 and gate mask 304. Acceptable photolithography and etching techniques can be used to form the openings. A liner, such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material are formed in the openings. The liner can include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material can be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as CMP, can be performed to remove excess material from the surface of second ILD 306. The remaining liner and conductive material form source / drain contacts 314 and gate contact 312 in the openings. An annealing process may be performed to form silicide at the interface between the epitaxial source / drain regions 292 and the source / drain contacts 314. The source / drain contacts 314 are physically and electrically coupled to the epitaxial source / drain regions 292, and the gate contact 312 is physically and electrically coupled to the gate electrode 302. The source / drain contacts 314 and the gate contact 312 may be formed in different processes or may be formed in the same process. Although shown as being formed in the same cross-section, it should be understood that each of the source / drain contacts 314 and the gate contact 312 may be formed in different cross-sections, which may avoid shorting the contacts.

[0177] FIG. 35C and FIG. 35D The embodiment of thinning the nanostructure 255 at various stages is shown. FIG. 35A and FIG. 35B structure. FIG. 35C Shown FIG. 19B Embodiments in which the nanostructures 255 are thinned before forming the STI regions 258. Portions of the nanostructures 255 in the regions 250N that are formed above the top surface of the STI regions 258 (e.g., portions of the nanostructures 255 formed by the second semiconductor layers 254A-254C) and portions of the nanostructures 255 that are formed below the top surface of the STI regions 258 (e.g., portions of the nanostructures 255 that are formed in the substrate 250) can have sidewalls that are at the same angle relative to the major surface of the substrate 250. Portions of the nanostructures 255 in the regions 250P that are formed above and below the top surface of the STI regions 258 can have sidewalls that are at different angles relative to the major surface of the substrate 250. For example, as FIG. 35CAs shown, the sidewalls of the portions of the nanostructures 255 in the region 250P that are above the top surface of the STI region 258 and formed from the first semiconductor layers 252A-252C can be more vertical than the sidewalls of the portions of the nanostructures 255 in the region 250P that are below the top surface of the STI region 258 and formed in the substrate 250.

[0178] FIG. 35D Embodiments are shown FIG. 20B , or FIG. 31D and FIG. 31E where the nanostructures 255 are thinned after the STI region 258 is formed or after the dummy gate stacks are removed. The portions of the nanostructures 255 in the region 250N that are formed above and below the top surface of the STI region 258 can have sidewalls that are angled differently relative to the major surface of the substrate 250. For example, the sidewalls of the portions of the nanostructures 255 in the region 250N that are below the top surface of the STI region 258 and formed in the substrate 250 can be more vertical than the sidewalls of the portions of the nanostructures 255 in the region 250N that are above the top surface of the STI region 258 and formed from the second semiconductor layers 254A-254C.

[0179] The portions of the nanostructures 255 in the region 250P that are above and below the top surface of the STI region 258 can have sidewalls that are angled differently relative to the major surface of the substrate 250 and have a step difference in width. For example, as shown FIG. 35D , the sidewalls of the portions of the nanostructures 255 in the region 250P that are above the top surface of the STI region 258 (e.g., the portions of the nanostructures 255 formed in the first semiconductor layers 252A-252C) can be more vertical than the sidewalls of the portions of the nanostructures 255 in the region 250P that are below the top surface of the STI region 258 (e.g., the portions of the nanostructures 255 formed in the substrate 250). In addition, there can be a step difference between the width of the portions of the nanostructures 255 that are below the top surface of the STI region 258 and the width of the portions of the nanostructures 255 that are above the top surface of the STI region 258, and the width of the portions of the nanostructures 255 that are below the top surface of the STI region 258 is greater than the width of the portions of the nanostructures 255 that are above the top surface of the STI region 258.

[0180] As described above, the first semiconductor layers 252A-252C are formed with a graded germanium concentration, and the first semiconductor layers 252A-252C are thinned using an etch process that has a higher etch rate as the germanium concentration increases, such that the first semiconductor layers 252A-252C have a more rectangular profile, and control of the process for etching the nanostructures 255 in regions 250N and regions 250P is improved. The first semiconductor layers 252A-252C are then used as channel regions in regions 250P. Inclusion of the channel regions formed from the first semiconductor layers 252A-252C in the NSFETs enables better gate control, reduces nanostructure width variation, and reduces DIBL.

[0181] According to one embodiment, a method includes forming a semiconductor fin over a semiconductor substrate, the semiconductor fin including germanium, a first portion of the semiconductor fin having a greater germanium concentration than a second portion of the semiconductor fin, a first distance between the first portion and a major surface of the semiconductor substrate being less than a second distance between the second portion and the major surface of the semiconductor substrate; and trimming the semiconductor fin, the first portion of the semiconductor fin being trimmed at a greater rate than the second portion of the semiconductor fin. In one embodiment, a first angle between a sidewall of the semiconductor fin and the major surface of the semiconductor substrate prior to trimming the semiconductor fin is different than a second angle between the sidewall of the semiconductor fin and the major surface of the semiconductor substrate after trimming the semiconductor fin. In one embodiment, a ratio of the trimming rate of the first portion of the semiconductor fin to the trimming rate of the second portion of the semiconductor fin is 1 to 3. In one embodiment, trimming the semiconductor fin includes exposing the semiconductor fin to an oxidizing agent. In one embodiment, trimming the semiconductor fin includes, in a cyclic process, exposing the semiconductor fin to an oxidizing agent, and then exposing the semiconductor fin to a base or an acid. In one embodiment, the method further includes forming a shallow trench isolation region around at least a portion of the semiconductor fin, the semiconductor fin being trimmed after the shallow trench isolation region is formed. In one embodiment, the method further includes forming a shallow trench isolation region around at least a portion of the semiconductor fin, the semiconductor fin being trimmed prior to the shallow trench isolation region is formed. In one embodiment, the method further includes forming a dummy gate over the semiconductor fin; and removing the dummy gate to expose the semiconductor fin, the semiconductor fin being trimmed after the dummy gate is removed.

[0182] According to another embodiment, a semiconductor device includes: a semiconductor substrate; a first semiconductor fin over the semiconductor substrate, the first semiconductor fin including silicon germanium, a germanium concentration of the first semiconductor fin decreasing as a distance from the semiconductor substrate increases; a second semiconductor fin over the semiconductor substrate, the second semiconductor fin including silicon, wherein a first angle between a sidewall of the first semiconductor fin and a major surface of the semiconductor substrate is more perpendicular than a second angle between a sidewall of the second semiconductor fin and the major surface of the semiconductor substrate; a gate stack over the first semiconductor fin; and a source / drain region at least partially in the first semiconductor fin adjacent to the gate stack. In one embodiment, the first angle is 85° to 95°. In one embodiment, the second angle is 70° to 85°, or 95° to 120°. In one embodiment, a ratio of a percentage of germanium atoms in a first portion of the first semiconductor fin to a percentage of germanium atoms in a second portion of the first semiconductor fin is 1 :2 to 1 :8. In one embodiment, the first portion has a first width, the second portion has a second width, and the second width is greater than the first width by less than 1 nm. In one embodiment, the semiconductor device further includes: a shallow trench isolation region around a portion of the first semiconductor fin, a ratio of a topmost width of a portion of the first semiconductor fin extending above the shallow trench isolation region to a bottommost width of the portion of the first semiconductor fin extending above the shallow trench isolation region is 0.8 to 1.2. In one embodiment, the semiconductor device further includes: a shallow trench isolation region around a portion of the first semiconductor fin, the first semiconductor fin has a step change in width at a top surface of the shallow trench isolation region. In one embodiment, the first semiconductor fin includes a first straight sidewall above the top surface of the shallow trench isolation region and a second straight sidewall below the top surface of the shallow trench isolation region, a third angle between the first straight sidewall and the major surface of the semiconductor substrate is more perpendicular than a fourth angle between the second straight sidewall and the major surface of the semiconductor substrate.

[0183] According to yet another embodiment, a semiconductor device includes: a first channel region over a semiconductor substrate, the first channel region including silicon germanium, the first channel region having a first width; a second channel region over the first channel region, the second channel region including silicon germanium, the second channel region having a lower germanium concentration than the first channel region, the second channel region having a second width; a third channel region over the semiconductor substrate, the third channel region including silicon, the third channel region having a third width; a fourth channel region over the third channel region, the fourth channel region including silicon, the fourth channel region having a fourth width, a difference between the first width and the second width being less than a difference between the third width and the fourth width; and a gate stack surrounding the first channel region and the second channel region. In one embodiment, the first channel region has a gradient germanium concentration that decreases as a distance from the semiconductor substrate increases, and the second channel region has a gradient germanium concentration that decreases as a distance from the semiconductor substrate increases. In one embodiment, a ratio of the second width to the first width is 0.9 to 1.1. In one embodiment, a ratio of the fourth width to the third width is 0.64 to 1.0.

[0184] The foregoing has outlined rather generally the features of several embodiments in order that the detailed description that follows can be better understood. Those skilled in the art will appreciate that they can readily use the disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or for implementing the same advantages of the embodiments introduced herein. Those skilled in the art will realize that such equivalent constructions do not depart from the spirit and scope of the disclosure and that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the disclosure.

[0185] Example 1 is a method of forming a semiconductor device, comprising: forming a semiconductor fin over a semiconductor substrate, the semiconductor fin including germanium, wherein a germanium concentration of a first portion of the semiconductor fin is greater than a germanium concentration of a second portion of the semiconductor fin, a first distance between the first portion and a major surface of the semiconductor substrate is less than a second distance between the second portion and the major surface of the semiconductor substrate; and trimming the semiconductor fin, wherein the first portion of the semiconductor fin is trimmed at a greater rate than the second portion of the semiconductor fin.

[0186] Example 2 is the method of Example 1, wherein a first angle between a sidewall of the semiconductor fin and the major surface of the semiconductor substrate prior to trimming the semiconductor fin is different than a second angle between the sidewall of the semiconductor fin and the major surface of the semiconductor substrate after trimming the semiconductor fin.

[0187] Example 3 is the method of example 1, wherein a ratio of a trim rate of the first portion of the semiconductor fin to a trim rate of the second portion of the semiconductor fin is 1 to 3.

[0188] Example 4 is the method of example 1, wherein trimming the semiconductor fin comprises exposing the semiconductor fin to an oxidizing agent.

[0189] Example 5 is the method of example 1, wherein trimming the semiconductor fin comprises, in a cyclic process, exposing the semiconductor fin to an oxidizing agent, and then exposing the semiconductor fin to a base or an acid.

[0190] Example 6 is the method of example 1, further comprising forming a shallow trench isolation region around at least a portion of the semiconductor fin, wherein the semiconductor fin is trimmed after the shallow trench isolation region is formed.

[0191] Example 7 is the method of example 1, further comprising forming a shallow trench isolation region around at least a portion of the semiconductor fin, wherein the semiconductor fin is trimmed before the shallow trench isolation region is formed.

[0192] Example 8 is the method of example 1, further comprising forming a dummy gate over the semiconductor fin; and removing the dummy gate to expose the semiconductor fin, wherein the semiconductor fin is trimmed after the dummy gate is removed.

[0193] Example 9 is a semiconductor device comprising: a semiconductor substrate; a first semiconductor fin over the semiconductor substrate, the first semiconductor fin comprising silicon germanium, a germanium concentration of the first semiconductor fin decreasing with increasing distance from the semiconductor substrate; a second semiconductor fin over the semiconductor substrate, the second semiconductor fin comprising silicon, wherein a first angle between a sidewall of the first semiconductor fin and a major surface of the semiconductor substrate is more perpendicular than a second angle between a sidewall of the second semiconductor fin and the major surface of the semiconductor substrate; a gate stack over the first semiconductor fin; and a source / drain region at least partially in the first semiconductor fin adjacent to the gate stack.

[0194] Example 10 is the semiconductor device of example 9, wherein the first angle is 85° to 95°.

[0195] Example 11 is the semiconductor device of example 10, wherein the second angle is 70° to 85°, or 95° to 120°.

[0196] Example 12 is the semiconductor device of Example 9, wherein a ratio of a percentage of germanium atoms in the first portion of the first semiconductor fin to a percentage of germanium atoms in the second portion of the first semiconductor fin is 1 :2 to 1 :8.

[0197] Example 13 is the semiconductor device of Example 12, wherein the first portion has a first width, wherein the second portion has a second width, and wherein the second width is greater than the first width by less than 1 nm.

[0198] Example 14 is the semiconductor device of Example 9, further comprising a shallow trench isolation region surrounding a portion of the first semiconductor fin, wherein a ratio of a topmost width of a portion of the first semiconductor fin extending above the shallow trench isolation region to a bottommost width of the portion of the first semiconductor fin extending above the shallow trench isolation region is 0.8 to 1.2.

[0199] Example 15 is the semiconductor device of Example 9, further comprising a shallow trench isolation region surrounding a portion of the first semiconductor fin, wherein the first semiconductor fin has a step change in width at a top surface of the shallow trench isolation region.

[0200] Example 16 is the semiconductor device of Example 15, wherein the first semiconductor fin includes a first straight sidewall above the top surface of the shallow trench isolation region and a second straight sidewall below the top surface of the shallow trench isolation region, wherein a third angle between the first straight sidewall and the major surface of the semiconductor substrate is closer to perpendicular than a fourth angle between the second straight sidewall and the major surface of the semiconductor substrate.

[0201] Example 17 is a semiconductor device comprising: a first channel region over a semiconductor substrate, the first channel region comprising silicon germanium, the first channel region having a first width; a second channel region over the first channel region, the second channel region comprising silicon germanium, the second channel region having a lower germanium concentration than the first channel region, the second channel region having a second width; a third channel region over the semiconductor substrate, the third channel region comprising silicon, the third channel region having a third width; a fourth channel region over the third channel region, the fourth channel region comprising silicon, the fourth channel region having a fourth width, wherein a difference between the first width and the second width is less than a difference between the third width and the fourth width; and a gate stack surrounding the first channel region and the second channel region.

[0202] Example 18 is the semiconductor device of Example 17, wherein the first channel region has a gradient germanium concentration that decreases with increasing distance from the semiconductor substrate, and wherein the second channel region has a gradient germanium concentration that decreases with increasing distance from the semiconductor substrate.

[0203] Example 19 is the semiconductor device of Example 17, wherein a ratio of the second width to the first width is 0.9 to 1.1.

[0204] Example 20 is the semiconductor device of Example 19, wherein a ratio of the fourth width to the third width is 0.64 to 1.0.

Claims

1. A method for forming a semiconductor device, comprising: forming a semiconductor fin and a second semiconductor fin over a semiconductor substrate, the semiconductor fin comprising silicon germanium and the second semiconductor fin comprising silicon, wherein a germanium concentration of a first portion of the semiconductor fin is greater than a germanium concentration of a second portion of the semiconductor fin, a first distance between the first portion and a major surface of the semiconductor substrate is less than a second distance between the second portion and the major surface of the semiconductor substrate, and wherein a third angle between a sidewall of the semiconductor fin and the major surface of the semiconductor substrate is closer to perpendicular than a fourth angle between a sidewall of the second semiconductor fin and the major surface of the semiconductor substrate; and trimming the semiconductor fin, wherein the first portion of the semiconductor fin is trimmed at a greater rate than the second portion of the semiconductor fin, The method further comprises: forming a shallow trench isolation region surrounding at least a portion of the semiconductor fin; wherein the semiconductor fin includes a first straight sidewall above a top surface of the shallow trench isolation region and a second straight sidewall below the top surface of the shallow trench isolation region, wherein a first angle between the first straight sidewall and the main surface of the semiconductor substrate is closer to vertical than a second angle between the second straight sidewall and the main surface of the semiconductor substrate, There is a step difference between the width of a portion of the semiconductor fin above the top surface of the shallow trench isolation region and the width of a portion of the semiconductor fin below the top surface of the shallow trench isolation region.

2. The method according to claim 1, wherein A first angle between a sidewall of the semiconductor fin and the main surface of the semiconductor substrate before trimming the semiconductor fin is different from a second angle between the sidewall of the semiconductor fin and the main surface of the semiconductor substrate after trimming the semiconductor fin.

3. The method according to claim 1, wherein A ratio of a trimming rate of the first portion of the semiconductor fin to a trimming rate of the second portion of the semiconductor fin is 1 to 3.

4. The method according to claim 1, wherein Trimming the semiconductor fin includes exposing the semiconductor fin to an oxidant.

5. The method according to claim 1, wherein Trimming the semiconductor fin includes exposing the semiconductor fin to an oxidant and then exposing the semiconductor fin to a base or an acid in a cyclic process.

6. The method according to claim 1, wherein The semiconductor fins are trimmed after forming the shallow trench isolation regions.

7. The method according to claim 1, wherein The semiconductor fins are trimmed before forming the shallow trench isolation regions.

8. The method according to claim 1, further comprising: forming a dummy gate on the semiconductor fin; as well as The dummy gate is removed to expose the semiconductor fin, wherein the semiconductor fin is trimmed after removing the dummy gate.

9. A semiconductor device comprising: semiconductor substrates; a first semiconductor fin on the semiconductor substrate, the first semiconductor fin comprising silicon germanium, and a germanium concentration of the first semiconductor fin decreasing as the distance from the semiconductor substrate increases; a second semiconductor fin over the semiconductor substrate, the second semiconductor fin comprising silicon, wherein a first angle between a sidewall of the first semiconductor fin and a major surface of the semiconductor substrate is closer to vertical than a second angle between a sidewall of the second semiconductor fin and the major surface of the semiconductor substrate; a gate stack on the first semiconductor fin; a source / drain region at least partially within the first semiconductor fin adjacent to the gate stack; and a shallow trench isolation region surrounding a portion of the first semiconductor fin, wherein the first semiconductor fin includes a first straight sidewall above a top surface of the shallow trench isolation region and a second straight sidewall below the top surface of the shallow trench isolation region, wherein a third angle between the first straight sidewall and the main surface of the semiconductor substrate is closer to vertical than a fourth angle between the second straight sidewall and the main surface of the semiconductor substrate.

10. The semiconductor device according to claim 9, wherein The first angle is 85° to 95°.

11. The semiconductor device according to claim 10, wherein The second angle is 70° to 85°, or 95° to 120°.

12. The semiconductor device according to claim 9, wherein A ratio of a germanium atomic percentage in the first portion of the first semiconductor fin to a germanium atomic percentage in the second portion of the first semiconductor fin is 1:2 to 1:

8.

13. The semiconductor device according to claim 12, wherein The first portion has a first width, wherein the second portion has a second width, and wherein the second width is less than 1 nm greater than the first width.

14. The semiconductor device according to claim 9, further comprising: a shallow trench isolation region surrounding a portion of the first semiconductor fin, wherein a ratio of a topmost width of the portion of the first semiconductor fin extending above the shallow trench isolation region to a bottommost width of the portion of the first semiconductor fin extending above the shallow trench isolation region is 0.8 to 1.

2.

15. The semiconductor device according to claim 9, wherein The first semiconductor fin has a step change in width at a top surface of the shallow trench isolation region.

16. A semiconductor device comprising: A nanostructure comprising: a first channel region on the semiconductor substrate, the first channel region comprising silicon germanium, and having a first width; and a second channel region above the first channel region, the second channel region comprising silicon germanium, the second channel region having a lower germanium concentration than the first channel region, and the second channel region having a second width; A second nanostructure, the second nanostructure comprising: a third channel region on the semiconductor substrate, the third channel region comprising silicon and having a third width; a fourth channel region above the third channel region, the fourth channel region comprising silicon, the fourth channel region having a fourth width, wherein a difference between the first width and the second width is less than a difference between the third width and the fourth width, and wherein a third angle between a sidewall of the nanostructure and a major surface of the semiconductor substrate is closer to perpendicular than a fourth angle between a sidewall of the second nanostructure and the major surface of the semiconductor substrate; a gate stack surrounding the first channel region and the second channel region; and a shallow trench isolation region surrounding a portion of the nanostructure, wherein the nanostructure includes a first straight sidewall above a top surface of the shallow trench isolation region and a second straight sidewall below the top surface of the shallow trench isolation region, wherein a first angle between the first straight sidewall and a main surface of the semiconductor substrate is closer to vertical than a second angle between the second straight sidewall and the main surface of the semiconductor substrate, There is a step difference between the width of a portion of the nanostructure above the top surface of the shallow trench isolation region and the width of a portion of the nanostructure below the top surface of the shallow trench isolation region.

17. The semiconductor device according to claim 16, wherein The first channel region has a gradient germanium concentration that decreases with increasing distance from the semiconductor substrate, and wherein the second channel region has a gradient germanium concentration that decreases with increasing distance from the semiconductor substrate.

18. The semiconductor device according to claim 16, wherein A ratio of the second width to the first width is 0.9 to 1.

1.

19. The semiconductor device according to claim 18, wherein A ratio of the fourth width to the third width is 0.64 to 1.0.

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