Image sensor, forming method thereof and integrated chip

Abstract

Various embodiments of the present disclosure relate to an image sensor having a photodetector disposed in a substrate. The substrate has a front surface and a rear surface. An absorption enhancement structure is disposed along the rear surface of the substrate and overlies the photodetector. The absorption enhancement structure includes a plurality of protrusions extending outwardly from the rear surface of the substrate. Each of the plurality of protrusions includes opposing curved sidewalls.

Description

Technical Field

[0001] The embodiments of the present invention relate to an image sensor, a method for forming the same, and an integrated chip. Background Art

[0002] Many modern electronic devices (such as digital cameras, optical imaging devices, etc.) include image sensors. Image sensors convert optical images into digital data that can be represented in the form of digital images. Image sensors include an array of pixel sensors, which are unit devices used to convert optical images into digital data. Some types of pixel sensors include charge-coupled device (CCD) image sensors and complementary metal-oxide-semiconductor (CMOS) image sensors (CIS). Compared with CCD pixel sensors, CIS is favored due to its low power consumption, small size, fast data processing, direct data output and low manufacturing cost. Summary of the invention

[0003] An embodiment of the present invention provides an image sensor, comprising: a substrate, comprising a front surface and a rear surface; a photodetector, arranged in the substrate; and an absorption enhancement structure, arranged along the rear surface of the substrate and overlying the photodetector, wherein the absorption enhancement structure comprises a plurality of protrusions extending outward from the rear surface of the substrate, and wherein each of the plurality of protrusions comprises relative curved side walls.

[0004] An embodiment of the present invention provides an integrated chip, comprising: a substrate, comprising a front surface and a back surface; an internal connection structure, arranged along the front surface of the substrate; a photodetector, arranged in the substrate; an absorption enhancement structure, arranged along the back surface of the substrate, wherein the absorption enhancement structure comprises a plurality of first protrusions and a corresponding plurality of grooves located in the back surface, the corresponding plurality of grooves intersecting with the plurality of first protrusions in a meshing manner, wherein each of the plurality of first protrusions comprises relative curved side walls; and an upper dielectric structure, overlying the back surface of the substrate, wherein the upper dielectric structure comprises a plurality of second protrusions arranged along the lower surface of the upper dielectric structure, wherein each of the plurality of second protrusions comprises a convex lower surface and fills a corresponding groove in the plurality of grooves, wherein the refractive index of the upper dielectric structure is less than the refractive index of the substrate.

[0005] An embodiment of the present invention provides a method for forming an image sensor, comprising: performing an ion implantation process to form a photodetector in a substrate; depositing a dielectric layer on the back side surface of the substrate; forming a masking layer on the dielectric layer, wherein the masking layer includes a plurality of side walls defining a first plurality of openings, wherein the first plurality of openings expose the upper surface of the dielectric layer; performing a first patterning process on the dielectric layer and the substrate to form a plurality of grooves in the substrate; and performing a second patterning process on the substrate to enlarge the plurality of grooves and form an absorption enhancement structure along the back side surface of the substrate, wherein the absorption enhancement structure includes a plurality of protrusions each including relative curved side walls. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure can be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 Cross-sectional views of some embodiments of image sensors including an absorption enhancement structure comprising a plurality of protrusions disposed along a surface of a substrate, wherein the protrusions include curved sidewalls are illustrated.

[0008] Figure 2 illustrate Figure 1 Cross-sectional views of some alternative embodiments of image sensors are shown in which each protrusion includes a substantially flat upper surface.

[0009] Figures 3A to 3D illustrate Figure 1 Cross-sectional views of some alternative embodiments of image sensors are shown in which color filters and microlenses overly the absorption enhancement structure.

[0010] FIG. 4A to FIG. 4C Some embodiments are illustrated of a cross-sectional view of an integrated chip including an absorption enhancement structure including a plurality of protrusions disposed along a surface of a substrate, wherein the protrusions include curved sidewalls.

[0011] Figures 5 to 12 Cross-sectional views illustrating some embodiments of a method of forming an image sensor including an absorption enhancement structure comprising a plurality of protrusions disposed along a surface of a substrate, wherein the protrusions include curved sidewalls.

[0012] Fig.13 A method is described in a flow chart format that illustrates some embodiments of forming an image sensor including an absorption enhancement structure comprising a plurality of protrusions disposed along a surface of a substrate, wherein the protrusions include curved sidewalls. DETAILED DESCRIPTION

[0013] The present disclosure provides many different embodiments or examples to implement different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, a first feature formed on or formed on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not indicate the relationship between the various embodiments and / or configurations discussed by itself.

[0014] In addition, for ease of description, spatially relative terms, such as "beneath," "below," "lower," "above," "upper," etc., may be used herein to describe the relationship between one element or feature illustrated in the figures and another (other) element or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0015] A CMOS image sensor (CIS) generally includes an array of pixel regions, each of which has a photodetector arranged in a semiconductor substrate. A color filter is arranged above the photodetector and is configured to filter incident light provided to different photodetectors in the CIS. After receiving the light, the photodetector is configured to generate an electrical signal corresponding to the received light. A signal processing unit may process the electrical signal from the photodetector to determine an image captured by the CIS. Quantum efficiency (QE) is the ratio of the number of photons that contribute to the electrical signal generated by the photodetector in the pixel region to the number of photons incident on the pixel region. It is understood that the QE of a CIS can be improved using an on-chip absorption enhancement structure.

[0016] In some embodiments, an absorption enhancement structure is disposed along the backside surface of the semiconductor substrate such that the absorption enhancement structure overlies the photodetector. The absorption enhancement structure may include a plurality of protrusions having a triangular shape such that the protrusions are configured to increase a light receiving surface area for incident electromagnetic radiation disposed on the backside of the semiconductor substrate. Typically, the triangular protrusions have substantially straight sidewalls. This may partially increase the amount of incident electromagnetic radiation disposed on the photodetector relative to a backside having a substantially flat surface, thereby improving the QE of the CIS. However, since the sidewalls of each protrusion are substantially straight, the light receiving surface area for incident electromagnetic radiation may be reduced, thereby reducing the QE of the CIS.

[0017] Therefore, some embodiments of the present disclosure relate to an image sensor including an absorption enhancement structure disposed along a backside surface of a semiconductor substrate. In addition, a photodetector is disposed within the semiconductor substrate and directly below the absorption enhancement structure. The absorption enhancement structure includes a plurality of protrusions disposed along the backside surface of the semiconductor substrate. Each protrusion in the absorption enhancement structure includes a curved sidewall. By means of the curved sidewall, a light receiving surface area for incident electromagnetic radiation disposed on the backside surface of the semiconductor substrate can be increased. For example, an arc length of a curved sidewall of a protrusion is greater than a corresponding length of a substantially straight sidewall of another protrusion, wherein the protrusion has the same height as the other protrusion. This increases the light receiving surface area, thereby improving the QE of the image sensor.

[0018] Figure 1 A cross-sectional view of some embodiments of an image sensor 100 including an absorption enhancement structure 110 comprising a plurality of protrusions 112 disposed along a surface of a substrate 104 is illustrated.

[0019] The image sensor 100 includes an interconnect structure 102 disposed along a front side 104f of a substrate 104. In some embodiments, the substrate 104 may include any semiconductor body (e.g., bulk silicon, epitaxial silicon, another suitable semiconductor material, or any combination of the foregoing materials) and / or have a first doping type (e.g., p-type doping). The substrate 104 has a first refractive index (e.g., in a range of about 3.40 to 3.99 or another suitable value). The photodetector 108 is disposed within the substrate 104 and is configured to convert incident electromagnetic radiation 116 (e.g., photons) into electrical signals (i.e., to generate electron-hole pairs from the incident electromagnetic radiation 116). The photodetector 108 includes a second doping type (e.g., n-type doping) that is opposite to the first doping type. In some embodiments, the first doping type is n-type and the second doping type is p-type, or vice versa. In other embodiments, the photodetector 108 may be configured as and / or include a photodiode or another suitable image sensor device. The first isolation structure 106 is disposed within the substrate 104 and extends from the front side 104f of the substrate 104 to a point above the front side 104f. In some embodiments, the first isolation structure 106 may include a dielectric material (e.g., silicon dioxide, silicon nitride, silicon carbide, etc.) and / or may be configured as a shallow trench isolation (STI) structure or another suitable isolation structure.

[0020] The absorption enhancement structure 110 is arranged along the back side 104b of the substrate 104, wherein the back side 104b is opposite to the front side 104f of the substrate 104. In addition, an upper dielectric structure 114 overlies the absorption enhancement structure 110. The upper dielectric structure 114 has a second refractive index (e.g., in the range of about 1.40 to 1.55 or another suitable value). In some embodiments, the first refractive index is greater than the second refractive index. The absorption enhancement structure 110 is configured to improve the quantum efficiency (QE) of the underlying photodetector 108 by improving the absorption of photons by the photodetector 108. In some embodiments, the absorption enhancement structure 110 can be configured to improve the QE by modifying the properties of the incident electromagnetic radiation 116 transmitted to the photodetector 108. For example, in some embodiments, the substrate 104 is a single crystal silicon substrate, and the absorption enhancement structure 110 corresponds to one or more recesses 113 and corresponding protrusions 112 intersecting the recesses 113 in the back side 104b of the substrate 104, so that the back side 104b of the substrate 104 is non-planar. The recesses 113 are filled with an upper dielectric structure 114, wherein the upper dielectric structure 114 includes a dielectric material (e.g., silicon dioxide) intersecting the protrusions 112 in an intersecting manner. The protrusions 112 are part of the substrate 104 (e.g., made of single crystal silicon), or alternatively are made of a layer of amorphous silicon or polycrystalline silicon on the back side 104b of the substrate 104 (e.g., formed by chemical vapor deposition (CVD), plasma vapor deposition (PVD) or another suitable deposition process). In some embodiments, the protrusions 112 are arranged at regularly spaced intervals and / or are arranged in a periodic pattern. The interface 110f where the grooves 113 meet the protrusions 112 helps redirect the incident electromagnetic radiation 116 through the substrate 104 and toward the photodetector 108. Therefore, the grooves 113 and the protrusions 112 establish a morphology that increases the absorption of the incident electromagnetic radiation 116 by the substrate 104 (for example, by reducing the reflection of light from non-planar surfaces). In other embodiments, the grooves 113 each have a concave shape so that the protrusions 112 can each have curved relative sidewalls. By having curved relative sidewalls of the protrusions 112, the light receiving surface area for the incident electromagnetic radiation 116 disposed on the back side 104b of the substrate 104 can be increased, thereby improving the QE of the image sensor 100. In addition, as Figure 1 As illustrated in , each protrusion 112 includes opposing curved sidewalls 112 cs that meet at a protrusion point 112 p , wherein the protrusion point 112 p defines the apex of the protrusion 112 .

[0021] Figure 2 Description and Figure 1Some alternative embodiments of image sensor 100 are shown corresponding to some embodiments of cross-sectional views of image sensor 200 .

[0022] like Figure 2 As illustrated in , each protrusion 112 includes opposite curved sidewalls 112cs extending from an upper surface 112us, respectively. In these embodiments, the upper surface 112us of each protrusion 112 may be substantially flat (e.g., a flat upper surface within the tolerance of a chemical mechanical polishing (CMP) process). For example, in some embodiments, at any point, the height of the upper surface 112us of the protrusion 112 varies within a range of -25 angstroms and +25 angstroms from the straight horizontal line 202. In yet other embodiments, at any point, the height of the upper surface 112us of the protrusion 112 varies within a range of approximately +5% and -5% of the thickness of the substrate 104 from the straight horizontal line 202.

[0023] Additionally, the opposing curved sidewalls 112cs of each protrusion 112 are due to each groove 113 including an arcuate recess having a substantially arcuate cross-section along the back side 104b of the substrate 104. The arcuate recess has a surface area that is proportional to the length of the arcuate recess (e.g., such that the surface area of ​​the protrusion 112 may correspond to the length of the arcuate recess), such that an arcuate recess whose arc length of the inner surface spans an angle Φ will have a length L approximately equal to (Φ / 360°)*d*π. For example, a semicircular arcuate recess having a distance d (e.g., the lateral distance between point A and point B) and an arc length spanning 180° (i.e., a semicircle, where Φ=180°) will have a length L (extending between point A and point B along a portion of the back side 104b of the substrate 104) approximately equal to (180° / 360°)*d*π=(π / 2)*d.

[0024] In some embodiments, the respective curved grooves 113 cause each protrusion 112 to include opposite curved sidewalls 112cs, thereby increasing the length of the cross section along the back side 104b of the substrate 104 relative to the straight sidewalls. For example, in some embodiments, if each groove 113 includes opposite straight inclined sidewalls ss1, ss2 (as illustrated by the dashed lines extending from point C to point A and from point C to point B), the length between point A and point B extending along the opposite inclined sidewalls ss1, ss2 is less than the length L extending along the arc-shaped recess. The increased length L between point A and point B increases the light receiving area for incident electromagnetic radiation disposed on the back side 104b of the substrate 104, thereby improving the QE of the image sensor 200.

[0025] In some embodiments, the curved sidewall 112cs of the protrusion 112 is defined from point C to point B. In other embodiments, when moving from point C to point B along the incremental section of the curved sidewall 112cs of the protrusion 112, the slope of the curved sidewall 112cs increases continuously. The angle α defined between the curved sidewall 112cs and the lower horizontal line 204 may be, for example, in the range of about 30 degrees to 120 degrees or may be another suitable value. The lower horizontal line 204 may be parallel to the straight horizontal line 202. In yet other embodiments, when moving from the bottom point of the corresponding curved sidewall 112cs to the upper surface 112us of the plurality of protrusions 112 along the incremental section of the curved sidewall 112cs of each protrusion 112, the slope of the curved sidewall 112cs increases continuously. Therefore, in some embodiments, each curved sidewall 112cs may have an angle α in the range of about 30 degrees to 120 degrees or another suitable value.

[0026] Figure 3A A cross-sectional view of some embodiments of an image sensor 300 a including an absorption enhancement structure 110 comprising a plurality of protrusions 112 disposed along a back side 104 b of a substrate 104 is illustrated.

[0027] In some embodiments, the image sensor 300a includes a substrate 104 overlying the interconnect structure 102. The image sensor 300a can be configured as a back-side illuminated CMOS image sensor (BSI-CIS) or another suitable image sensor device. In some embodiments, the substrate 104 can be or include any type of semiconductor body (e.g., single crystal silicon, CMOS bulk, silicon germanium (SeGe), silicon-on-insulator (SOI)), or another suitable semiconductor body or material, and / or has a first doping type (e.g., p-type doping). The photodetector 108 is disposed in the substrate 104 and can include, for example, a second doping type (e.g., n-type doping) opposite to the first doping type. It should be understood that the photodetector 108 and / or the substrate 104 including another doping type, respectively, are also within the scope of the present disclosure. In some embodiments, the photodetector 108 can be configured to generate an electrical signal from visible light radiation including electromagnetic radiation within a certain wavelength range. For example, the wavelength range can be in the range of about 400 nanometers to 700 nanometers. It should be understood that other values ​​of wavelength ranges are also within the scope of the present disclosure.

[0028] The first isolation structure 106 is disposed along the front side 104f of the substrate 104 and encloses the photodetector 108 in the lateral direction. In some embodiments, the first isolation structure 106 is configured as an STI structure or another suitable isolation structure. In other embodiments, the first isolation structure 106 may be, for example, or include silicon nitride, silicon carbide, silicon dioxide, silicon oxynitride, silicon oxycarbide, another suitable dielectric material, or any combination of the foregoing materials. In addition, the second isolation structure 302 is disposed within the substrate 104 and extends from the back side 104b of the substrate 104 to a point below the back side 104b. In some embodiments, the second isolation structure 302 may be configured as a deep trench isolation (DTI) structure or another suitable isolation structure. In addition, the second isolation structure 302 encloses the photodetector 108 in the lateral direction. In some embodiments, the second isolation structure 302 may be, for example, or include silicon nitride, silicon dioxide, silicon carbide, another suitable material, or any combination of the foregoing materials. In yet other embodiments, the second isolation structure 302 may extend continuously from the back side 104 b of the substrate 104 to an upper surface (not shown) of the first isolation structure 106. The first isolation structure 106 and the second isolation structure 302 are configured to electrically isolate the photodetector 108 from other semiconductor devices (not shown) disposed along and / or within the substrate 104, other photodetectors (not shown) disposed within the substrate 104, and / or other doped regions (not shown) disposed within the substrate 104.

[0029] The absorption enhancement structure 110 is arranged along the back side 104b of the substrate 104 and includes a plurality of protrusions 112 that intersect with the plurality of grooves 113 in a meshing manner. In addition, an upper dielectric structure 114 overlies the absorption enhancement structure 110 so that the grooves 113 are filled with dielectric material from the upper dielectric structure 114. Since the plurality of protrusions 112 each include a curved sidewall, the light receiving surface area for incident electromagnetic radiation disposed on the back side 104b of the substrate 104 is increased, thereby improving the QE of the image sensor 300a. In some embodiments, the upper dielectric structure 114 can be or include an oxide such as silicon dioxide, another oxide, another suitable dielectric material, or any combination of the foregoing materials.

[0030] The grid structure 303 overlies the back side 104b of the substrate 104. In some embodiments, the grid structure 303 can be or include, for example, a dielectric grid structure, a metal grid structure, another suitable grid structure, or any combination of the foregoing structures. For example, the grid structure 303 can be or include a dielectric grid structure configured to achieve total internal reflection (TIR) ​​using the adjacent upper dielectric structure 114, thereby directing incident electromagnetic radiation toward the underlying photodetector 108. This in turn further improves the QE of the image sensor 300a. In these embodiments, the grid structure 303 can be or include, for example, an oxide such as silicon oxynitride, another suitable dielectric material, or any combination of the foregoing materials. In yet another embodiment, the grid structure 303 can be or include a metal grid structure configured to reflect incident electromagnetic radiation from its sidewalls toward the underlying photodetector 108. In these embodiments, the grid structure 303 can be or include, for example, tungsten, another suitable metal material, or any combination of the foregoing materials. In some other embodiments, the grid structure 303 may be or include tungsten and silicon oxynitride, for example, so that the grid structure 303 includes a dielectric grid structure and a metal grid structure.

[0031] In addition, a color filter 304 is disposed over the absorption enhancement structure 110 and is configured to transmit incident electromagnetic radiation of a particular wavelength within a first wavelength range, while blocking incident electromagnetic radiation within a second wavelength range different from the first wavelength range. For example, the color filter 304 may be configured to transmit a first color (e.g., green light) toward the photodetector 108, while blocking other colors. It should be appreciated that color filters 304 that transmit other colors and / or incident electromagnetic radiation are within the scope of the present disclosure. A microlens 306 overlies the color filter 304 and includes a convex upper surface configured to direct incident electromagnetic radiation toward the photodetector 108, thereby improving the QE of the image sensor 300a.

[0032] Figure 3B Description Figure 3A A cross-sectional view of some embodiments of image sensor 300b that is an alternative embodiment of image sensor 300a is shown, wherein each protrusion 112 includes opposing curved sidewalls 112cs extending from an upper surface 112us. In some embodiments, upper surface 112us of each protrusion 112 is substantially flat.

[0033] Figure 3C Description Figure 3AA cross-sectional view of some embodiments of an image sensor 300c that is an alternative embodiment of the image sensor 300a shown, wherein each protrusion 112 includes an upper portion 112up overlying a lower portion 112lp. In some embodiments, the upper portion 112up of each protrusion 112 has a rectangular shape or another suitable shape. Thus, each protrusion 112 may have opposing sloping sidewalls 112ss overlying opposing curved sidewalls 112cs. Due to the opposing sloping sidewalls 112ss of the upper portion 112up, the light receiving surface area for incident electromagnetic radiation disposed on the substrate 104 is increased, thereby improving the QE of the image sensor 300c.

[0034] Figure 3D Description Figure 3A A cross-sectional view of some embodiments of an image sensor 300d that is an alternative embodiment of the image sensor 300a is shown, wherein each protrusion 112 includes an upper portion 112up overlying a lower portion 112lp. In some embodiments, the upper portion of each protrusion 112 has a semicircular shape or another suitable shape. Thus, the upper surface 112us of each protrusion 112 may be curved, convex, or another suitable shape, thereby increasing the light receiving surface area for incident electromagnetic radiation disposed on the substrate 104 and improving the QE of the image sensor 300d.

[0035] Figure 4A A cross-sectional view illustrating some embodiments of an integrated chip 400 a includes a substrate 104 overlying an interconnect structure 102 .

[0036] A plurality of semiconductor devices 410 are arranged to be located within the interconnect structure 102 and along the front side 104f of the substrate 104. In some embodiments, the semiconductor device 410 may be configured as a pixel device that can output and / or process electrical signals generated by the photodetectors 108a to 108c. The semiconductor device 410 may be configured, for example, as a transfer transistor, a source follower transistor, a row select transistor, and / or a reset transistor. It should be understood that semiconductor devices 410 configured as other semiconductor devices are also within the scope of the present disclosure. In further embodiments, the semiconductor devices 410 may each include a gate structure 412 disposed along the front side 104f of the substrate 104 and a sidewall spacer structure 414 disposed along the sidewalls of the gate structure 412. In yet other embodiments, the gate structure 412 includes a gate dielectric layer and a gate electrode, wherein the gate dielectric layer is disposed between the substrate 104 and the gate electrode.

[0037] The interconnect structure 102 may include, for example, a plurality of dielectric layers 402, a plurality of inter-level dielectric (ILD) layers 404, a plurality of conductive wires 406, and a plurality of conductive vias 408. In some embodiments, the dielectric layer 402 may be configured as an etch stop layer, and / or may be or include, for example, silicon nitride, silicon carbide, silicon oxynitride, silicon oxycarbide, another suitable dielectric material, or any combination of the foregoing materials. In other embodiments, the ILD layer 404 may be or include, for example, an oxide (e.g., silicon dioxide), fluorosilicate glass, phosphate glass (e.g., borophosphate silicate glass), another suitable dielectric material, or any combination of the foregoing materials. The conductive wires 406 and the conductive vias 408 are disposed in the ILD layer 404 and the dielectric layer 402, and are configured to electrically couple the devices disposed in the integrated chip 400a to each other and / or to another integrated chip (not shown). In some embodiments, the conductive wire 406 and / or the conductive via 408 may be or include copper, aluminum, titanium nitride, tantalum nitride, tungsten, another suitable conductive material, or any combination of the foregoing materials, for example. It should be understood that the conductive wire 406 and / or the conductive via 408 including other suitable materials are also within the scope of the present disclosure.

[0038] In some embodiments, the substrate 104 can be any semiconductor body (e.g., bulk silicon, another suitable semiconductor material, etc.) and / or has a first doping type (e.g., p-type doping). The photodetectors 108a to 108c are disposed within the substrate 104 and each has a second doping type (e.g., n-type doping) opposite to the first doping type. It should be understood that photodetectors 108a to 108c and / or substrate 104 including another doping type are also within the scope of the present disclosure. The absorption enhancement structure 110 is arranged along the back side 104b of the substrate 104 and includes a plurality of protrusions 112 each having opposing curved sidewalls. Therefore, the absorption enhancement structure 110 is configured to increase the light receiving surface area for incident electromagnetic radiation disposed on the back side 104b of the substrate 104, thereby improving the QE of the integrated chip 400a.

[0039] In some embodiments, the second isolation structure 302 may laterally enclose the photodetectors 108a to 108c and extend from the back side 104b of the substrate 104 to a point below the back side 104b. The second isolation structure 302 may be configured as a DTI structure, a back-side deep trench isolation (BDTI) structure, or another suitable isolation structure. In some embodiments, the second isolation structure 302 may be or include, for example, a dielectric material (e.g., silicon nitride, silicon carbide, silicon dioxide, silicon oxycarbide, silicon oxynitride), another suitable dielectric material, a metal material (e.g., copper, aluminum, tungsten), another suitable metal material, or any combination of the foregoing materials. In further embodiments, a passivation layer 416 is disposed along the back side 104b of the substrate 104 and between the second isolation structure 302 and the substrate 104. Thus, the passivation layer 416 may extend laterally continuously along the protrusion 112 of the absorption enhancement structure 110. In some embodiments, the passivation layer 416 may be or include, for example, a high-k dielectric material (eg, a dielectric material having a dielectric constant greater than 3.9), hafnium oxide (eg, HfO 2 ), aluminum oxide (e.g., Al 2 O 3 ), tantalum oxide (e.g., Ta 2 O 5 ), another suitable dielectric material or any combination of the above materials. In addition, the upper dielectric structure 114 overlies the passivation layer 416 and the second isolation structure 302. The grid structure 303 overlies the upper dielectric structure 114 and the second isolation structure 302.

[0040] A plurality of color filters 304a to 304c overlie the upper dielectric structure 114. The color filters 304a to 304c (e.g., a red filter, a blue filter, a green filter, etc.) are respectively configured to pass electromagnetic radiation within a first frequency range and block electromagnetic radiation within a second frequency range different from the first frequency range. For example, in some embodiments, the first color filter 304a may be configured as a green filter, while the adjacent second color filter 304b may be configured as a red filter. In addition, a microlens 306 overlies the color filters 304a to 304c and is configured to direct incident electromagnetic radiation toward the photodetectors 108a to 108c, thereby further improving the QE of the integrated chip 400a.

[0041] Figure 4B Description and Figure 4ASome alternative embodiments of the integrated chip 400a are shown in cross-sectional views of some embodiments of the integrated chip 400b, where the second isolation structure 302 comprises the same material as the upper dielectric structure 114. In some embodiments, the passivation layer 416 extends continuously from above the back side 104b of the substrate 104 to a point aligned with the front side 104f of the substrate 104.

[0042] Figure 4C Description and Figure 4B Some alternative embodiments of integrated chip 400b are shown as cross-sectional views of some embodiments of integrated chip 400c, where color filters 304a-304c are laterally spaced apart between sidewalls of grid structure 303. In some embodiments, microlens 306 directly overlies each photodetector 108a-108c.

[0043] In some embodiments, it should be understood that although FIG. 4A to FIG. 4C The protrusions 112 of the integrated chips 400a to 400c are illustrated and / or described as Figure 3B The protrusion 112, but FIG. 4A to FIG. 4C The protrusion 112 may be configured as Figure 3A , Figure 3C or Figure 3D protrusion 112.

[0044] Figures 5 to 12 Cross-sectional views 500 through 1200 illustrate some embodiments of a method of forming an image sensor including an absorption enhancement structure including a plurality of protrusions disposed along a surface of a substrate according to the present disclosure. Figures 5 to 12 The cross-sectional views 500 to 1200 shown in the drawings are described with reference to the method, but it should be understood that Figures 5 to 12 The structure shown in is not limited to the method, but can exist independently of the method. Figures 5 to 12 It is described as a series of actions, but it should be understood that these actions are not restrictive, but the order of actions can be changed in other embodiments, and the disclosed method is also applicable to other structures. In other embodiments, some actions described and / or described can be omitted completely or partially.

[0045] like Figure 5As illustrated in the cross-sectional view 500 of , a substrate 104 is provided, and a first isolation structure 106 is formed on the front side 104f of the substrate 104. In some embodiments, the substrate 104 may be, for example, a bulk substrate (e.g., a bulk silicon substrate), a silicon-on-insulator (SOI) substrate, or another suitable substrate. It should be understood that other materials of the substrate 104 are also within the scope of the present disclosure. In some embodiments, before forming the first isolation structure 106, a first implantation process is performed to dope the substrate 104 with a first doping type (e.g., p-type). In other embodiments, the process of forming the first isolation structure 106 may include: selectively etching the substrate 104 to form a trench in the substrate 104 extending from the front side 104 f of the substrate 104 into the substrate 104; and filling (e.g., by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), thermal oxidation, etc.) the trench with a dielectric material (e.g., silicon nitride, silicon carbide, silicon dioxide, another suitable dielectric material, or any combination of the foregoing materials). In other embodiments, the substrate 104 is selectively etched by forming a masking layer (not shown) on the front side 104 f of the substrate 104, and then exposing the substrate 104 to one or more etchants configured to selectively remove unmasked portions of the substrate 104.

[0046] In addition, if Figure 5 As shown in , a photodetector 108 is formed within the substrate 104. In some embodiments, the photodetector 108 includes a region of the substrate 104 including a second doping type (e.g., n-type) opposite to the first doping type. In some embodiments, the photodetector 108 may be formed by a selective ion implantation process that selectively implants ions into the substrate using a masking layer (not shown) on the front side 104f of the substrate 104. In other embodiments, the first doping type includes a p-type dopant and the second doping type includes an n-type dopant, or vice versa. Subsequently, an interconnect structure 102 is formed along the front side 104f of the substrate 104. In some embodiments, forming the interconnect structure 102 may include performing one or more deposition processes, a single damascene process, a dual damascene process, other suitable formation processes, or any combination of the foregoing processes.

[0047] In addition, if Figure 5As described in , after forming the photodetector 108, a thinning process is performed on the back side 104b of the substrate 104 to reduce the initial thickness Ti of the substrate 104 to a thickness Ts. In some embodiments, the thinning process may include performing a mechanical grinding process, a chemical mechanical polishing (CMP) process, another suitable thinning process, or any combination of the foregoing processes.

[0048] like Figure 6 As shown in the cross-sectional view 600, Figure 5 The structure of the substrate 104 is inverted and then an upper dielectric layer 602 is formed along the back side 104b of the substrate 104. The upper dielectric layer 602 can be deposited, for example, by CVD, PVD, ALD, or another suitable growth process or deposition process. In some embodiments, the upper dielectric layer 602 can be, for example, or include an oxide such as silicon dioxide, another suitable dielectric material front surface 104f. In some other embodiments, a reflectivity test process can be performed on the plurality of protrusions 112 to confirm or any combination of the foregoing materials, and / or a thickness of about 170 angstroms or in the range of about 150 angstroms to 190 angstroms is formed. It should be understood that other values ​​of the thickness of the upper dielectric layer 602 are also within the scope of the present disclosure. In addition, a masking layer 604 is formed on the upper dielectric layer 602 so that the masking layer 604 includes a plurality of sidewalls defining a plurality of openings 606. In some embodiments, the masking layer 604 is deposited by CVD, PVD, ALD, or another suitable growth process or deposition process. In yet other embodiments, the masking layer 604 may be or include, for example, a hard mask layer, a photoresist, another suitable material, or any combination thereof.

[0049] like Figure 7 As shown in the cross-sectional view 700 of FIG. Figure 6 The first patterning process is performed on the substrate 104 and the upper dielectric layer 602 to form a plurality of grooves 113. The grooves 113 extend into the upper dielectric layer 602 and the back side 104b of the substrate 104. In some embodiments, the first patterning process may include performing a dry etching process or another suitable etching process. Subsequently, a removal process is performed to remove the masking layer ( Figure 6 604). In some embodiments, the removal process includes performing a wet etching process or another suitable removal process. In some other embodiments, the first patterning process may include performing a chemical dry etch (CDE) driven at a bias voltage greater than zero.

[0050] like Figure 8As illustrated in the cross-sectional view 800 of , a second patterning process is performed on the substrate 104, thereby enlarging the plurality of grooves 113 and forming a plurality of protrusions 112 along the back side 104b of the substrate 104. This partially forms the absorption enhancement structure 110 along the back side 104b of the substrate 104. In some embodiments, the second patterning process may include performing an isotropic etching process (e.g., a CDE driven at a zero bias voltage), a dry etching process, a plasma etching process, another suitable etching process, or any combination of the foregoing processes. The second patterning process is performed so that the protrusions 112 each have opposing curved sidewalls, thereby increasing a light receiving surface area for incident electromagnetic radiation disposed on the back side 104b of the substrate 104. In addition, in some embodiments, the second patterning process includes exposing the substrate 104 to one or more etchants, which may, for example, include sulfur hexafluoride (e.g., SF 6 ), carbon tetrafluoride (such as CF 4 ), oxygen (such as O 2 ), another suitable etchant or any combination of the foregoing etchants wherein the bias power is zero.

[0051] In some embodiments, the curved sidewall 112cs of the protrusion 112 is defined from the first point 802 to the second point 804 by the first patterning process and the second patterning process. In other embodiments, the slope of the curved sidewall 112cs increases continuously when moving along the incremental section of the curved sidewall 112cs of the protrusion 112 from the first point 802 to the second point 804. The angle α defined between the curved sidewall 112cs and the straight horizontal line 806 may be, for example, in the range of about 30 degrees to 120 degrees or another suitable value. The straight horizontal line 806 may be parallel to the substrate 104 to ensure that the curved sidewall 112cs of each protrusion 112 is substantially curved (i.e., the slope of each curved sidewall 112cs increases continuously when moving along the incremental section of the curved sidewall 112cs of the protrusion 112, and / or the angle α is in the range of about 30 degrees to 120 degrees or another suitable value). In other embodiments, the reflectivity testing process includes placing incident electromagnetic radiation on the plurality of protrusions 112 and determining the percentage of the incident electromagnetic radiation that is reflected from the protrusions 112. In still other embodiments, if the reflectivity is substantially high, the second patterning process may be repeated or the time of the second patterning process may be extended to ensure that the curved sidewall 112cs of each protrusion 112 is substantially curved.

[0052] like Fig. 9 As shown in the cross-sectional view 900 of FIG. 1 , a removal process is performed to remove the upper dielectric layer ( Figure 8602). In some embodiments, the removal process may include performing a wet etching process, a dry etching process, another suitable etching process, or any combination of the foregoing processes. In other embodiments, the removal process includes removing the upper dielectric layer ( Figure 8 602) and the substrate 104 are exposed to one or more etchants, such as (for example) hydrofluoric acid, dilute hydrofluoric acid, another suitable etchant, or any combination of the foregoing etchants.

[0053] like Fig.10 1000, a third patterning process is performed on the substrate 104 to further expand the groove 113. In addition, after performing the third patterning process, each protrusion 112 includes an upper portion 112up overlying the lower portion 112lp. In some embodiments, the upper portion 112up of each protrusion 112 has a rectangular shape or another suitable shape. Therefore, each protrusion 112 may have relative inclined sidewalls 112ss overlying the relative curved sidewalls 112cs. By the inclined sidewalls 112ss of the upper portion 112up, the light receiving surface area for incident electromagnetic radiation disposed on the substrate 104 can be increased, thereby improving the QE of the photodetector 108. In some embodiments, the third patterning process includes performing a wet etching process or another suitable etching process. In further embodiments, the third patterning process includes exposing the substrate 104 to one or more etchants, such as, for example, tetramethylammonium hydroxide (TMAH) or another suitable etchant.

[0054] In yet other embodiments, the timing and / or etchant used in the third patterning process is adjusted so that the upper portion of each protrusion 112 has a semicircular shape (not shown) (see, for example, Figure 3D ) or another suitable shape. Thus, the upper surface of each protrusion 112 may be curved, convex (not shown) (e.g., see Figure 3D ) or another suitable shape, thereby increasing the light receiving surface area for incident electromagnetic radiation disposed on the substrate 104 and improving the QE of the photodetector 108.

[0055] like Fig.11As illustrated in the cross-sectional view 1100 of , a second isolation structure 302 is formed in the substrate 104. In some embodiments, forming the second isolation structure 302 includes: etching the back side 104b of the substrate 104 to form a DTI opening (not shown) extending into the back side 104b of the substrate 104; and depositing (e.g., CVD, PVD, ALD, sputtering, electroless plating, electroplating, or another suitable deposition process or growth process) the second isolation structure 302 in the DTI opening. In addition, a passivation layer 416 is formed over the back side 104b of the substrate 104. In some embodiments, the passivation layer 416 is deposited by, for example, PVD, CVD, ALD, thermal oxidation, or another suitable deposition process or growth process. In yet other embodiments, the passivation layer 416 is formed in the DTI opening before forming the second isolation structure 302, so that the passivation layer 416 is disposed between the second isolation structure 302 and the substrate 104 (e.g., see Figure 4A ). The second isolation structure 302 may be configured as a DTI structure, a backside deep trench isolation (BDTI) structure, or another suitable isolation structure. In some embodiments, the second isolation structure 302 may be, for example, or include a dielectric material (e.g., silicon nitride, silicon carbide, silicon dioxide, silicon oxycarbide, silicon oxynitride), another suitable dielectric material, a metal material (e.g., copper, aluminum, tungsten), another suitable metal material, or any combination of the foregoing materials.

[0056] like Fig.12 As illustrated in the cross-sectional view 1200 of FIG. 1 , an upper dielectric structure 114 is formed on the passivation layer 416. In some embodiments, the process of forming the upper dielectric structure 114 includes: depositing (e.g., by CVD, PVD, ALD, thermal oxidation, etc.) a dielectric material on the passivation layer 416; and performing a planarization process (e.g., a chemical mechanical polishing (CMP) process) into the dielectric material to form the upper dielectric structure 114, so that the upper surface of the upper dielectric structure 114 is substantially flat (e.g., within the tolerance of the CMP process). In some embodiments, a grid structure 303 is formed on the upper dielectric structure 114, and a color filter 304 is formed on the upper dielectric structure 114 and between the sidewalls of the grid structure 303. In another embodiment, a microlens 306 is formed on the color filter 304, so that the microlens 306 has a convex upper surface. In other embodiments, the grid structure 303 , the color filter 304 and / or the microlens 306 may be deposited separately, for example, by CVD, PVD, ALD, sputtering, electroless plating, electroplating, or another suitable deposition process or growth process.

[0057] Fig.13A method 1300 is described for forming an image sensor including an absorption enhancement structure according to the present disclosure, wherein the absorption enhancement structure includes a plurality of protrusions disposed along a surface of a substrate. Although method 1300 is described and / or elaborated as a series of actions or events, it should be understood that the method is not limited to the described order or actions. Therefore, in some embodiments, the actions may be performed in an order different from that described, and / or may be performed simultaneously. In addition, in some embodiments, the described actions or events may be subdivided into multiple actions or events, which may be performed at separate times or simultaneously with other actions or sub-actions. In some embodiments, some of the described actions or events may be omitted, and other undescribed actions or events may be included.

[0058] At act 1302, a photodetector is formed within a substrate. Figure 5 Cross-sectional view 500 corresponding to some embodiments of act 1302 is illustrated.

[0059] At act 1304, a masking layer is formed over the back side of the substrate. Figure 6 Cross-sectional view 600 corresponding to some embodiments of act 1304 is illustrated.

[0060] At act 1306, a first patterning process is performed on the back side of the substrate based on the masking layer to define a plurality of recesses within the back side of the substrate. Figure 7 Cross-sectional view 700 corresponding to some embodiments of act 1306 is illustrated.

[0061] At act 1308, a second patterning process is performed on the back side of the substrate to enlarge the grooves and form an absorption enhancement structure comprising a plurality of protrusions disposed along the back side of the substrate. Each protrusion comprises opposing curved sidewalls. Figure 8 Cross-sectional view 800 corresponding to some embodiments of act 1308 is illustrated.

[0062] At act 1310, a third patterning process is performed on the protrusions such that each protrusion has an upper portion overlying a lower portion, wherein a shape of the upper portion is different than a shape of the lower portion. Fig.10 Cross-sectional view 1000 corresponding to some embodiments of act 1310 is illustrated.

[0063] At act 1312, a deep trench isolation (DTI) structure is formed within the backside of the substrate such that the DTI structure laterally encloses the photodetector. Fig.11 Cross-sectional view 1100 corresponding to some embodiments of act 1312 is illustrated.

[0064] At act 1314, a color filter is formed over the photodetector. Fig.12Cross-sectional view 1200 corresponding to some embodiments of act 1314 is illustrated.

[0065] At act 1316, microlenses are formed over the color filters. Fig.12 Cross-sectional view 1200 corresponding to some embodiments of act 1316 is illustrated.

[0066] Thus, in some embodiments, the present disclosure is directed to an image sensor including an absorption enhancement structure comprising a plurality of protrusions disposed along a surface of a substrate, wherein each protrusion comprises opposing curved sidewalls.

[0067] In some embodiments, the present application provides an image sensor, comprising: a substrate, comprising a front surface and a back surface; a photodetector, disposed in the substrate; and an absorption enhancement structure, disposed along the back surface of the substrate and overlying the photodetector, wherein the absorption enhancement structure comprises a plurality of protrusions extending outward from the back surface of the substrate, and wherein each protrusion has relative curved side walls.

[0068] In some embodiments, the above-mentioned image sensor also includes: an upper dielectric structure overlying the absorption enhancement structure, wherein the upper dielectric structure includes a plurality of convex protrusions arranged along the bottom surface of the upper dielectric structure, wherein each of the plurality of convex protrusions is laterally spaced apart between adjacent protrusions of the absorption enhancement structure.

[0069] In some embodiments, in the above image sensor, each of the plurality of protrusions includes opposing inclined sidewalls directly overlying the opposing curved sidewalls.

[0070] In some embodiments, in the above image sensor, each of the plurality of protrusions includes a substantially flat upper surface, such that the opposing curved sidewalls are directly below and extend from the substantially flat upper surface.

[0071] In some embodiments, in the above-mentioned image sensor, each of the multiple protrusions includes an upper portion directly overlying a lower portion, wherein the upper portion has a semicircular shape so that the upper surface of each of the multiple protrusions is convex, and wherein the lower portion includes the relative curved side walls.

[0072] In some embodiments, the above-mentioned image sensor also includes: a deep trench isolation (DTI) structure, which is arranged in the substrate, wherein the deep trench isolation structure extends from the back side surface of the substrate to a point below the upper surface of the photodetector, wherein the deep trench isolation structure laterally encloses the photodetector; and a passivation layer, which is arranged along the back side surface of the substrate, wherein the passivation layer contacts the upper surface of each of the multiple protrusions and the relative curved side walls.

[0073] In some embodiments, in the above image sensor, the passivation layer is disposed between the deep trench isolation structure and the substrate.

[0074] In some embodiments, the above-mentioned image sensor further includes: an internal connection structure, which is arranged along the front surface of the substrate, wherein the internal connection structure includes an internal connection dielectric structure, a plurality of conductive through holes and a plurality of conductive wirings.

[0075] In some embodiments, in the above image sensor, it further includes: a color filter overlying the absorption enhancement structure, wherein the color filter is configured to allow a first wavelength range to pass through and block a second wavelength range different from the first wavelength range; and

[0076] The microlens is overlying the color filter and comprises a convex upper surface.

[0077] In some embodiments, the present application provides an integrated chip, which includes: a substrate having a front surface and a back surface; an internal connection structure arranged along the front surface of the substrate; a photodetector arranged in the substrate; an absorption enhancement structure arranged along the back surface of the substrate, wherein the absorption enhancement structure includes a plurality of first protrusions and a corresponding plurality of grooves located in the back surface, the corresponding plurality of grooves intersecting with the first protrusions in a meshing manner, wherein each first protrusion includes relative curved side walls; and an upper dielectric structure overlying the back surface of the substrate, wherein the upper dielectric structure includes a plurality of second protrusions arranged along the lower surface of the upper dielectric structure, wherein each second protrusion has a convex lower surface and fills a corresponding groove among the plurality of grooves, wherein the refractive index of the upper dielectric structure is less than the refractive index of the substrate.

[0078] In some embodiments, the integrated chip described above further includes: a passivation layer disposed between the absorption enhancement structure and the upper dielectric structure, wherein the passivation layer directly contacts the plurality of first protrusions and directly contacts the plurality of second protrusions.

[0079] In some embodiments, the above-mentioned integrated chip also includes: a deep trench isolation (DTI) structure extending from the back side surface of the substrate to a point below the back side surface of the substrate, wherein the passivation layer is arranged between the deep trench isolation structure and the substrate.

[0080] In some embodiments, in the above integrated chip, the passivation layer extends vertically and continuously from above the backside surface of the substrate to the interconnect structure.

[0081] In some embodiments, in the above-mentioned integrated chip, each of the multiple first protrusions includes an upper portion directly overlying a lower portion, wherein the upper portion has a rectangular shape and the lower portion includes the relative curved side walls, and wherein the upper portion includes relative inclined side walls directly overlying the relative curved side walls.

[0082] In some embodiments, in the above integrated chip, an upper surface of each of the plurality of first protrusions is convex.

[0083] In some embodiments, in the above-mentioned integrated chip, it also includes: a grid structure overlying the backside surface of the substrate, wherein the photodetector is laterally spaced apart between the sidewalls of the grid structure. In some embodiments, the present application provides a method for forming an image sensor, the method comprising: performing an ion implantation process to form a photodetector in a substrate; depositing a dielectric layer on the backside surface of the substrate; forming a masking layer on the dielectric layer, wherein the masking layer includes a plurality of sidewalls defining a first plurality of openings, wherein the first plurality of openings expose the upper surface of the dielectric layer; performing a first patterning process on the dielectric layer and the substrate to form a plurality of grooves in the substrate; and performing a second patterning process on the substrate to enlarge the grooves and form an absorption enhancement structure along the backside surface of the substrate, wherein the absorption enhancement structure includes a plurality of protrusions each having curved opposite sidewalls.

[0084] In some embodiments, in the above method, the first patterning process includes performing chemical dry etching at a bias voltage greater than zero, wherein the second patterning process includes performing the chemical dry etching at a zero bias voltage to form the multiple protrusions and performing a wet etching process to remove the dielectric layer.

[0085] In some embodiments, the above method also includes: performing a third patterning process on the multiple protrusions to expand the multiple grooves, wherein after performing the third patterning process, each of the multiple protrusions includes an upper portion directly overlying a lower portion, wherein the upper portion has a rectangular shape and the lower portion includes the relative curved sidewalls; and depositing a passivation layer on the substrate, wherein the passivation layer extends continuously along each of the multiple protrusions.

[0086] In some embodiments, in the above method, the third patterning process includes exposing the plurality of protrusions to one or more wet etchants, wherein the one or more wet etchants include tetramethylammonium hydroxide.

[0087] The foregoing summarizes the features of several embodiments so that those skilled in the art may better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they may easily use the present disclosure as a basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also appreciate that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and modifications may be made herein without departing from the spirit and scope of the present disclosure.

Claims

1. An image sensor, comprising: A substrate, comprising a front surface and a back surface; A photodetector, disposed in the substrate; an absorption enhancement structure disposed along the backside surface of the substrate and overlying the photodetector, wherein the absorption enhancement structure comprises a plurality of protrusions extending outwardly from the backside surface of the substrate, and wherein each of the plurality of protrusions comprises opposing curved sidewalls; a passivation layer disposed along the backside surface of the substrate, wherein the passivation layer contacts an upper surface of each of the plurality of protrusions and the opposing curved sidewalls; as well as An interconnect structure is disposed along the front surface of the substrate, wherein the interconnect structure includes an interconnect dielectric structure, a plurality of conductive through holes, and a plurality of conductive wirings, The passivation layer extends vertically and continuously from above the backside surface of the substrate to the interconnect structure.

2. The image sensor according to claim 1, further comprising: An upper dielectric structure overlies the absorption enhancement structure, wherein the upper dielectric structure includes a plurality of convex protrusions disposed along a bottom surface of the upper dielectric structure, wherein each convex protrusion of the plurality of convex protrusions is laterally spaced between adjacent protrusions of the absorption enhancement structure. 3 . The image sensor of claim 1 , wherein each of the plurality of protrusions comprises opposing inclined sidewalls directly overlying the opposing curved sidewalls. 4 . The image sensor of claim 1 , wherein each of the plurality of protrusions comprises a planar upper surface such that the opposing curved sidewalls are directly below and extend from the planar upper surface.

5. The image sensor of claim 1 , wherein each of the plurality of protrusions comprises an upper portion directly overlying a lower portion, wherein the upper portion has a semicircular shape such that an upper surface of each of the plurality of protrusions is convex, and wherein the lower portion comprises the opposing curved sidewalls.

6. The image sensor according to claim 1, further comprising: A deep trench isolation structure is disposed in the substrate, wherein the deep trench isolation structure extends from the backside surface of the substrate to a point below the upper surface of the photodetector, wherein the deep trench isolation structure laterally encloses the photodetector. 7 . The image sensor according to claim 6 , wherein the passivation layer is disposed between the deep trench isolation structure and the substrate.

8. The image sensor according to claim 1, further comprising: a color filter overlying the absorption enhancement structure, wherein the color filter is configured to pass a first wavelength range and block a second wavelength range different from the first wavelength range; as well as The microlens is overlying the color filter and comprises a convex upper surface.

9. An integrated chip, comprising: A substrate, comprising a front surface and a back surface; An internal connection structure is arranged along the front surface of the substrate; A photodetector, disposed in the substrate; an absorption enhancement structure disposed along the backside surface of the substrate, wherein the absorption enhancement structure comprises a plurality of first protrusions and a corresponding plurality of grooves in the backside surface, the corresponding plurality of grooves intersecting the plurality of first protrusions in a meshing manner, wherein each of the plurality of first protrusions comprises opposing curved sidewalls; an upper dielectric structure overlying the backside surface of the substrate, wherein the upper dielectric structure comprises a plurality of second protrusions disposed along a lower surface of the upper dielectric structure, wherein each of the plurality of second protrusions comprises a convex lower surface and fills a corresponding groove of the plurality of grooves, wherein a refractive index of the upper dielectric structure is less than a refractive index of the substrate; as well as a passivation layer disposed between the absorption enhancement structure and the upper dielectric structure, wherein the passivation layer directly contacts the plurality of first protrusions and directly contacts the plurality of second protrusions, The passivation layer extends vertically and continuously from above the backside surface of the substrate to the interconnect structure.

10. The integrated chip according to claim 9, further comprising: A deep trench isolation structure extends from the backside surface of the substrate to a point below the backside surface of the substrate, wherein the passivation layer is disposed between the deep trench isolation structure and the substrate.

11. An integrated chip according to claim 9, wherein each of the plurality of first protrusions includes an upper portion directly overlying a lower portion, wherein the upper portion has a rectangular shape and the lower portion includes the relative curved sidewalls, and wherein the upper portion includes relative inclined sidewalls directly overlying the relative curved sidewalls. 12 . The integrated chip according to claim 9 , wherein an upper surface of each of the plurality of first protrusions is convex.

13. The integrated chip according to claim 9, further comprising: A grid structure overlies the backside surface of the substrate, wherein the photodetectors are laterally spaced apart between sidewalls of the grid structure.

14. A method of forming an image sensor, comprising: performing an ion implantation process to form a photodetector in the substrate; depositing a dielectric layer over the backside surface of the substrate; forming a masking layer over the dielectric layer, wherein the masking layer includes a plurality of sidewalls defining a first plurality of openings, the first plurality of openings exposing an upper surface of the dielectric layer; performing a first patterning process on the dielectric layer and the substrate to form a plurality of recesses in the substrate; performing a second patterning process on the substrate to enlarge the plurality of grooves and form an absorption enhancement structure along the backside surface of the substrate, wherein the absorption enhancement structure includes a plurality of protrusions each including opposing curved sidewalls; as well as A passivation layer is deposited over the substrate, wherein the passivation layer continuously extends along each of the plurality of protrusions, wherein the passivation layer continuously extends vertically from over the backside surface of the substrate to an interconnect structure.

15. The method of forming an image sensor according to claim 14, wherein the first patterning process includes performing chemical dry etching at a bias voltage greater than zero, wherein the second patterning process includes performing the chemical dry etching at a zero bias voltage to form the plurality of protrusions and performing a wet etching process to remove the dielectric layer.

16. The method of forming an image sensor according to claim 14, further comprising: A third patterning process is performed on the plurality of protrusions to enlarge the plurality of grooves, wherein after performing the third patterning process, each of the plurality of protrusions includes an upper portion directly overlying a lower portion, wherein the upper portion has a rectangular shape and the lower portion includes the opposing curved sidewalls. 17 . The method of forming an image sensor according to claim 16 , wherein the third patterning process comprises exposing the plurality of protrusions to one or more wet etchants, wherein the one or more wet etchants comprise tetramethylammonium hydroxide.

Images