Passive transmission line receiver with reduced interference

Abstract

This application relates to passive transmission line receivers with reduced interference. Improved electronic structures are disclosed for propagating logic states between superconducting digital logic gates using a three-junction interferometer in a receiver circuit to reduce reflected signals that would otherwise cause distortion of signals transmitted between the gates. Other improved electronic structures include passive transmission lines (PTLs) with transmission line matching circuitry that has previously been avoided. The matching circuitry minimizes the generation and propagation of spurious pulses emitted by Josephson junctions used in the digital logic gates.

Description

[0001] Cross Reference to Related Applications - Priority Claim

[0002] This application claims priority to U.S. Provisional Application No. 62 / 983,392, filed February 28, 2020, entitled “Interference-Reducing Passive Transmission Line Receiver,” the entirety of which is incorporated herein by reference.

[0003] Government Rights

[0004] This invention was made with government support under the Intelligence Advanced Research Projects Activity (IARPA) agency awarded W911NF-17-9-0001. The government has certain rights in the invention. TECHNICAL FIELD

[0005] The present invention relates generally to electronic circuits, and more particularly to Josephson junction circuits and transmission lines. BACKGROUND

[0006] Superconducting circuit systems based on Josephson junctions are used to implement digital logic systems. A Josephson junction is generally a circuit element that includes two superconducting electrodes separated, for example, by a thin insulating tunnel barrier, which can support a current that flows indefinitely without the need to apply any voltage. Despite the challenges faced by the technology, one of the major benefits is a large reduction in power consumption relative to semiconductor technology and digital logic circuits. This benefit can be realized even though systems employing Josephson junction circuit elements must be operated at temperatures close to absolute zero. The possibility of realizing this benefit has led to great interest in Josephson technology. One example of a program that has sought to exploit this benefit is the federal SuperTools program, in which Synopsys, Inc. of Mountain View, California, played a leading role. SUMMARY

[0007] Embodiments of a method and apparatus for reducing data errors caused by spurious pulses generated due to a specific combination of clock frequency and line length used in a circuit having a passive transmission line (PTL) and a PTL driver circuit that transmits single-through-quantum (SFQ) pulses into the PTL. An electronic structure for propagating logic states between superconducting digital logic gates is also disclosed. The structure includes a PTL and a transmission line matching circuit system that minimizes the generation and propagation of spurious pulses emitted by Josephson junctions used in the digital logic gates. In some embodiments disclosed herein, a novel receiver circuit is used that isolates the SFQ-generating junction from the PTL. The PTL terminates in an inductor instead of a Josephson junction. A triple-junction interferometer is configured for amplification and isolation. Using some of the disclosed embodiments of the receiver circuit, a large portion of the backpropagation interference signal that would otherwise be generated is eliminated. What remains is low-amplitude damped ringing that dissipates rapidly. This remaining portion has a much smaller effect than the larger pulse signal generated by a conventional receiver, resulting in an improved receiver with improved reception and overall performance.

[0008] In other embodiments disclosed herein, a conventional receiver is used, but the PTL terminates at the driver with a matching resistor. In some such embodiments, the driver is designed to be insensitive to backpropagation pulses. Due to the termination of the matching resistor, the backpropagation pulses disappear without any harmful effect. Such embodiments eliminate the negative effects of clock frequency and line length-dependent data errors caused by spurious pulses from the transmission line.

[0009] This overview and abstract do not limit the breadth, scope or applicability of the claimed invention, but rather the invention as claimed herein is limited only by the language of the claims themselves. Attached Figure Description

[0010] The disclosed methods and apparatus according to one or more various embodiments are described with reference to the accompanying drawings. The drawings are provided for illustrative purposes only and depict only examples of some embodiments of the disclosed methods and apparatus. These drawings are provided to facilitate the reader's understanding of the disclosed methods and apparatus. They should not be considered as limiting the breadth, scope, or applicability of the claimed invention. It should be noted that these drawings are not necessarily drawn to scale for clarity and ease of explanation.

[0011] Figure 1 A simplified diagram showing a typical PTL driver or receiver.

[0012] Figure 2 Display according to Figure 1 The diagram shows simplified schematics of some embodiments of the circuits depicted.

[0013] Figure 3 Display the input signal and when the input signal is applied toFigure 2 An example of the output signal obtained when the circuit is used, where the PTL has a propagation delay of 10 ps.

[0014] Figure 4 An example is shown of an input signal and the resulting output signal when applied to the circuit shown in 2, where the PTL has a propagation delay of 9 ps.

[0015] Figure 5 Display according to Figure 7 The diagram shows simplified schematics of some embodiments of the circuits depicted.

[0016] Figure 6 Display the input signal and when applied to Figure 5 Examples of the output signals obtained when the circuit is described in the figure.

[0017] Figure 7 A simplified schematic diagram of a receiver circuit according to some embodiments of the methods and apparatus disclosed herein is shown.

[0018] Figure 8A It includes Figure 6 A simplified schematic diagram of an example of the receiver circuit 800 shown in the figure.

[0019] Figure 8B It is one of them Figure 8A The circuit shown is a simplified schematic diagram of an embodiment in which the inductors are divided into a first independent inductor and a second independent inductor, and a third bias current source to the receiver is provided between the first independent inductor and the second independent inductor.

[0020] Figure 8C Showing used in Figure 7 The circuit used in other embodiments of the circuit.

[0021] Figure 8D The receiver circuitry shown therein is Figure 7 The receiver circuit is similar to that used in other embodiments, but without an inductor between the receiver's input terminal and the receiver's reference potential terminal.

[0022] Figure 9 Display transmission to Figures 8A-8D An example of a circuit receiving a signal.

[0023] Figure 10 Display transmission to Figures 8A-8D Examples of the current and voltage of the signal received by the circuit.

[0024] In the drawings, which are incorporated in and constitute a part of this specification, reference numerals are used to generally consecutively refer to like components and features of the drawings, as consistent with generally accepted engineering practices. However, the reference numerals in the drawings are not necessarily meant to convey a relationship between the illustrated components and features, nor are the individual components and features necessarily outlined in the claims, and the inventors maintain that the scope of the claimed invention encompasses any and all combinations of components, features, and / or acts recited in the specification and / or drawings. DETAILED DESCRIPTION

[0025] Josephson junctions were found to be useful in digital logic circuits that rely on the quantum mechanical quantization of magnetic flux. The quantum mechanical quantization of magnetic flux results in the quantization of magnetic flux when it passes through a hole or loop in a superconductor. One use that implements the quantum mechanical quantization of magnetic flux in a logic circuit is known as single flux quantum (SFQ) logic. Although SFQ logic itself has numerous variants, all such variants utilize flux storage and transport that is affected by pulses emitted by Josephson junctions that are typically shunted by resistors in SFQ circuits. When a Josephson junction emits a voltage pulse, it injects a single quantum of magnetic flux into a connected inductor. This type of pulse is called an "SFQ pulse." Rapid single flux quantum (RSFQ) devices can achieve pulse widths as narrow as a few picoseconds.

[0026] A logic circuit can be generated in which logic states propagate from one gate to another through the propagation of such pulses. Historically, SFQ pulses were transported via a Josephson transmission line (JTL) consisting of a small series inductor, with a Josephson junction connected to ground at the intersection. The inductor tends to have a fairly small inductance value, resulting in a relatively long Josephson transmission line with many junctions. Each junction is biased, thus consuming current and dissipating power. Furthermore, each junction presents a delay in signal propagation. However, such lines maintain the essential properties of SFQ pulses with high reliability.

[0027] In a very large scale integrated circuit (VLSI) environment, the use of JTLs to interconnect gates cannot be chosen due to large and variable delays through the JTLs and further due to the lack of viable automated routing design tools. One alternative is to use passive transmission lines (PTLs) that include stripline structures. Superconducting stripline structures have extremely low power dissipation. However, PTLs require driver circuits to drive the lines with non-SFQ voltage pulses and then convert the received pulses back into SFQ pulses at the receivers.

[0028] Nonetheless, one benefit of using PTLs for interconnection is that designers can use existing routing tools provided within existing electronic design automation (EDA) systems to design PTL circuits. Such tools are essential to manage many design tradeoffs and overcome the technical challenges inherent in designing circuits using PTLs.

[0029] Some of the challenges that arise in circuit design using PTLs are due to the fact that PTL driver circuits are always composed of junctions that emit SFQ pulses into transmission lines. This creates two problems.

[0030] The first problem involves a tradeoff between balancing wiring density and transmission line width. In order to achieve high wiring density, it is desirable to use narrow transmission lines. However, as the transmission lines are made narrower, the characteristic impedance of the lines increases. Higher impedance results in less pulse energy being injected into the lines, due in part to the limited amplitude of SFQ pulses. With less pulse energy, it can be necessary to provide receivers with higher sensitivity or to lower the noise immunity of the receivers, or both. For line widths in the range of one to a few microns, the approximate impedance of PTLs ranges from a few ohms to 20 ohms. Such line widths are considered to be quite large for CMOS integrated circuits and can increase the difficulty of designing such CMOS integrated circuits.

[0031] The second problem caused by junctions emitting SFQ pulses into transmission lines is the generation and propagation of spurious pulses, which can cause subsequent data errors. One reason for the generation and propagation of such spurious pulses is that the simplest form of Josephson PTL receiver is composed of a single junction biased near its threshold. While a pulse from the transmission line has enough energy to raise the junction above its threshold and thus cause an SFQ pulse to be generated as desired, the same pulse will also propagate backward along the transmission line toward the driver. Over time, this backward propagating pulse will gradually die out after reflecting off the end of the transmission line. However, if these reflections coincide with subsequent data pulses, false triggers can result, causing data errors. "Tuning" the clock frequency and transmission line delay to avoid coinciding reflections with data pulses is difficult to achieve in an LSI environment and reduces chip flexibility by constraining the clock frequency. That is, tuning the length of an interconnect (changing the length to fit an application) to avoid certain timing windows when using a clock frequency assumed in the design will likely not work in a densely wired layout because it is difficult to change the physical layout to tune (i.e., modify) the transmission line length.

[0032] To overcome some of these problems, it would be desirable to reduce or eliminate the need to trade off circuit density, line width, and impedance in circuits using both PTLs and the associated PTL driver circuits that emit SFQ pulses into PTLs. In addition, it would be desirable to reduce the likelihood of data errors due to spurious pulses without having to tune the clock frequency and transmission line delay in such circuits.

[0033] All of the circuits disclosed herein can be designed, simulated, and optimized using electronic circuit design tools that are commercially available or can be obtained through open source resources. These tools use device and circuit primitive libraries that are developed for general circuit design and optimization. The resulting circuit design can then be used to manufacture the device at a suitable foundry. The concepts and general implementation of the circuits presented here are independent of the specific libraries and foundries employed. Thus, the circuits disclosed herein are improved circuits relative to circuits in which a series of Josephson junctions are used to propagate single flux quantum (SFQ) pulses between the gates of the circuit, making the use of such electronic circuit design tools impossible.

[0034] Figure 1 A simplified view of a conventional passive transmission line (PTL) receiver 100 is shown. In the case of a driver, the figure is flipped from left to right so that the signals will be considered to originate as SFQ pulses across a Josephson junction 101. The generated pulses are applied through a resistor 103 to a PTL 105. In the case of a receiver 100, pulses from the PTL 105 are applied through a resistor 103 to a biased Josephson junction 101, inducing an SFQ pulse from the junction 101. In some embodiments, the resistor 103 has a resistance of 0 Ω (i.e., a short).

[0035] A "resonance" effect in the system can result in data errors occurring at very specific transmission line delays (or physical line lengths) when operating at a specific clock frequency.

[0036] Figure 2 An example of a circuit 200 in which two Josephson junctions 202, 203 are used within a PTL driver 204 is shown. A third Josephson junction 205 is used in a receiver 207. Some component values are provided as examples and will vary in other embodiments of the disclosed circuit. The PTL 208 between the PTL driver 204 and the receiver 207 has a delay of 10 picoseconds. A resistor 206 in series with the PTL 208 has a value of 1 ohm in the example shown and serves to break the superconducting loop. In this example, the value of the resistor 206 is much lower than the 16 ohm impedance of the PTL 208.

[0037] A pulse from the PTL driver 204 will enter the PTL 208, propagate from left to right, and be applied to the receiver junction 205. Thus, the receiver junction 205 will switch, emitting an SFQ pulse. This pulse will enter the PTL 208 on the right and propagate along the PTL 208 from right to left. As the pulse reaches the end of the PTL 208, it will be reflected and become a forward propagating pulse with a reduced amplitude by the reflection coefficient (R-Z) / (R+Z), where R is the value of the resistor 206 and Z is the impedance of the PTL 208. For Figure 2In the case of a short, the reflection coefficient is a negative value close to 1. If the resulting reflected pulse coincides with a data pulse, the two will at least partially cancel, resulting in a data error. This is the basis of the "ringing" effect. In some embodiments of the disclosed circuit, the impedance of resistor 206 is chosen to be the same as the impedance of PTL 208. This results in a reflection coefficient of zero. Thus, there is no reflected pulse and the "ringing" effect is eliminated.

[0038] Ringing effects occur rarely because the pulse width is narrow, resulting in a low probability that timing will cause cancellation. However, in VLSI circuits where there can be thousands of such transmission lines, the joint probability of resulting cancellations is much greater. Because simple circuits usually do not have major errors when operating, designers are not aware of the effect.

[0039] Figure 3 An example of the input signal 302 and the resulting output signal 304 is shown when the input signal 302 is applied to the circuit 200. The signals 302, 304 are generated from a simulation in which PTL 208 has an impedance of 16.0 ohms and the delay through PTL 208 is 10 picoseconds. The output signal 304 is essentially a faithful representation of the input signal 302, albeit delayed by the transmission line delay of the PTL. In particular, note that the series of 3 pulses including pulse 306 just before the 0.2 ns mark is nearly identical to the series of 3 pulses including pulse 308 in the input signal 302. Thus, it appears that even if a reflection occurs, the circuit functions in an acceptable manner because the reflection appears to occur at a time that results in minimal distortion of the output signal.

[0040] Figure 4 A plot of the input signal 402 and the output signal 404 is shown for the same circuit in Figure 2 However, the time delay through PTL 208 is reduced from 10 ps to 9 ps. Due to the difference of only 1 picosecond, the output signal 404 is severely distorted by some of the data pulses (e.g., pulse 306 seen in the output signal of Figure 3 but missing in the output signal 404). The missing pulses reflect the distortion caused by the ringing effect at certain clock frequencies and certain transmission line delays. The ringing effect causes a back-propagating pulse to reflect from the Josephson junction 205 of receiver 207, with a polarity inversion relative to the driver side, resulting in some pulses being canceled at the receiver 207 as can be seen in the output signal 404.

[0041] To analyze the signal in PTL 208, one can conceptually replace each of the Josephson junctions 202, 203, 204 with an ideal voltage source whose voltage is exactly the same as the voltage seen across the respective Josephson junction. Then the signal found in PTL 208 is the superposition of the signal generated by the voltage source and the reflection induced at the end of PTL 208.

[0042] Ideally, reflectionless transmission can be achieved by matching the resistances at the two ends of PTL 208. However, in practice this is impossible to accomplish because it is considered impractical due to the amount of signal power that would be lost in the resistors needed to create the resistance match. This is because the amplitude of the pulse launched onto PTL 208 is limited by the amplitude generated by the Josephson junction, which is a characteristic of the junction given the manufacturing technology. For example, in the manufacturing process of the Lincoln Laboratory SFQ5ee Josephson circuits (as used to model the specific characteristics of the Josephson junctions in the Federal SuperTools program), the generated amplitude is approximately 0.69 mV. The peak current of the pulse in the line is the amplitude value generated by the Josephson junction divided by the sum of the resistors 206 and the characteristic impedance of PTL 208 (R + Z). In a practical design, the characteristic impedance Z is made as high as possible in order to make the line width as narrow as possible to maximize the wiring density. Thus, by reducing the value of resistor 206 R by a large amount (e.g., setting R equal to 0 ohms), one obtains more than twice the current in the pulse.

[0043] It is further noted that even if the impedance at the receiver end of PTL 208 is matched, when receiver junction 205 switches in response to a received pulse, a spurious pulse is still generated. That is because receiver 207 becomes a generator, emitting a counter-propagating pulse into PTL 208. Due to the reflection at the assumed unmatched driver end of PTL 208, the counter-propagating pulse will be reflected as a negative forward-propagating pulse. In a typical case, the driver end of PTL 208 is driven directly by driver junction 203 and the reflection coefficient is -1, as determined from the formula for the reflection coefficient (RZ) / (R + Z) when the resistance R of driver resistor 206 is 0. If the negative spurious pulse coincides exactly with the data pulse, the two will cancel and a data error will result (the receiver will not detect any pulse).

[0044] Figure 5 The same circuit topology is shown with Figure 2 the resistor 506 having a value equal to the impedance of PTL 508, which in this example is 16.0 ohms. In one example, the delay of PTL 508 remains at 9.0 picoseconds, which is a value known to be susceptible to the resonance effect.

[0045] Figure 6The simulated input signal 602 and output signal 604 are shown. Compared to the output signal 404, the output signal 604 has Figure 5 The circuit with the values shown in the middle produces an output signal 604 with minimal detectable distortion. That is, the output pulse train of the output signal 604 is a faithful delayed representation of the pulse train at the input signal 602. Thus, matching the impedance of the PTL 508 to the impedance of the resistor 506 successfully mitigates the "resonance" effect.

[0046] In other embodiments disclosed herein, receiver circuits are disclosed that reduce the effect of back-propagating signals by providing some degree of input / output isolation.

[0047] Figure 7 A receiver circuit 700 using a three-junction interferometer 712 is shown. Three Josephson junctions 702, 704, 706, along with two associated inductors 708, 710, form the three-junction interferometer 712. The interferometer 712 is sensitive to a current injected into an input terminal 714. The critical current of the first Josephson junction 702 is twice the critical current of the second Josephson junction 704 and the third Josephson junction 706. Two bias current sources 720, 722 are provided. A current injected through the input terminal 714 will cause the second Josephson junction 704 to switch, which in turn causes the first Josephson junction 702 and the third Josephson junction 706 to switch. The switching of the first Josephson junction 702 isolates the input terminal 714 from the switching of the third Josephson junction 706. The inductor 708 coupled between the input terminal 714 and a reference potential terminal 716 coupled to a reference potential, such as ground, acts as a sink for the remaining current through the first Josephson junction 702, preventing the formation of an interfering signal that might otherwise be emitted through the input terminal 714 back into the PTL coupled to the input terminal 714 (see PTL 208 in Figure 8C The present circuit 700 reduces the amplitude of the interfering signal that would otherwise be produced to a negligible degree.

[0048] Figure 8A is a simplified schematic of a circuit 800 that includes a receiver circuit 801 similar to the circuit 700. Note that in a particular embodiment of the receiver circuit 801, the bias current source 722 is not needed. In the particular circuit 801, the Josephson junction 706 has a critical current much lower than the Josephson junction 704 and thus can be operated without the bias current source 722 as desired. However, in other embodiments, such as the embodiment shown in Figure 8C it can be necessary or desirable to provide the bias current source 722.

[0049] Figure 8Bis a simplified schematic of circuit 802 used in other embodiments in which inductor 710 can be split into two independent inductors 808, 810 and bias current source 806 is disposed between the inductor 808 and the inductor 810. The particular values of the components are provided as an example of an embodiment of circuit 800. However, other values will be used in other embodiments designed for particular implementations. In this example, a 16 ohm resistor 506 is disposed at the receiver side of PTL 208 before receiver 803 to provide an impedance match to the 16 ohm characteristic impedance of PTL 208. With the circuit element values specified in Figure 8A Match PTL 208 on the receiver side. Inductance 708 to ground (18 pico hen in this example) reduces the transient signal that would otherwise be launched back into PTL 208 when the three receiver junctions 804, 806, 808 are switched.

[0050] Figure 8C Circuit 804 is shown used in other embodiments in which circuit 700 is used. As noted above with respect to Figure 7 Circuit 804 is shown used in other embodiments in which circuit 700 is used. As noted above with respect to

[0051] Figure 8D Circuit 804 is shown used in other embodiments in which circuit 700 is used. As noted above with respect to

[0052] Figure 9 Input signal 902 and output signal 904 of circuit 800 are shown. Output signal 904 has minimal distortion (i.e., is a faithful representation of input signal 902 delayed by PTL 208). There is no "resonance" effect in essence for other values of transmission line delay (different lengths). The new receiver essentially eliminates resonance by not launching large pulse signals back into PTL 208.

[0053] Figure 10 Signals and details of the element values shown in Figure 8A are shown. In this case, in addition to Figure 9In addition to the input pulse 902 and the output pulse 904 described in the middle, the current 1002 into the driver side of the passive PTL 208 is also shown. This shows that the current pulse 1004 coincides with the voltage pulse 1006 generated by the driver, and later on the same trace, the return from the receiver as a small transient signal 1008 when an incident pulse is received. Note that this signal is much smaller than the incident pulse 1006 and is essentially balanced with respect to positive and negative current. This is unlikely to cause an error.

[0054] The features, structures, functionalities or characteristics described herein can be used in any combination of two or more such features, structures, functionalities or characteristics, whether or not such features, structures, functionalities or characteristics or combinations thereof address any of the problems disclosed herein. Moreover, the particular embodiments disclosed are not intended to limit the scope of the patent claims, but to support such claims.

[0055] In light of the detailed description, those of skill in the art will appreciate that numerous variations of the disclosed embodiments are possible and will support the claimed invention.

[0056] The disclosed embodiments are neither exhaustive nor limit the precise structure claimed. The scope of the claimed invention and embodiments is intended to be defined by the appended claims and their equivalents.

[0057] Several embodiments of the claimed invention have been described. It is to be understood that various modifications can be made without departing from the spirit and scope of the invention. For example, some of the steps described above can be irrelevant to order, and thus can be performed in an order different from that described. Also, some of the steps described above can be optional. Various activities described with respect to the methods identified above can be executed in repetitive, serial, or parallel fashion. It is to be understood that the foregoing description is intended to illustrate and not limit the scope of the claimed invention, which is defined by the scope of the appended claims, and that other embodiments are within the scope of the claims.

Claims

1. A three-junction interferometer, comprising: an input port; a reference potential terminal; a first Josephson junction having a first terminal and a second terminal, the first terminal coupled to the input port; a second Josephson junction having a first terminal and a second terminal, the first terminal of the second Josephson junction coupled to the second terminal of the first Josephson junction and the second terminal of the second Josephson junction coupled to the reference potential terminal; a first inductor having a first terminal and a second terminal, the first terminal of the first inductor coupled to the second terminal of the first Josephson junction; and a third Josephson junction having a first terminal and a second terminal, the first terminal of the third Josephson junction coupled to the second terminal of the first inductor and the second terminal of the third Josephson junction coupled to the reference potential terminal.

2. The three-junction interferometer of claim 1, further comprising a second inductor having a first terminal and a second terminal, the first terminal of the second inductor coupled to the first terminal of the first Josephson junction and the second terminal of the second inductor coupled to the reference potential terminal.

3. The three-junction interferometer of claim 1, further comprising a first current source having a current input port and a current output port, the current input port coupled to the reference potential terminal and the current output port coupled to the first terminal of the second Josephson junction.

4. The three-junction interferometer of claim 3, further comprising a second current source having a current input port and a current output port, the current input port of the second current source coupled to the reference potential terminal and the current output port of the second current source coupled to the first terminal of the third Josephson junction.

5. The three-junction interferometer of claim 2, further comprising an impedance matching device having a first terminal and a second terminal, the first terminal of the impedance matching device coupled to the input port and the second terminal of the impedance matching device configured to receive a signal from a transmission line having a characteristic impedance, wherein an impedance of the impedance matching device matches the characteristic impedance of the transmission line.

6. The three-junction interferometer of claim 1, further comprising an impedance matching device having a first terminal and a second terminal, the first terminal of the impedance matching device coupled to the input port and the second terminal of the impedance matching device configured to receive a signal from a transmission line having a characteristic impedance, wherein the impedance of the impedance matching device matches the characteristic impedance of the transmission line.

7. A three-junction interferometer, comprising: (a) an input port; (b) a reference potential terminal; (c) a first Josephson junction having a first terminal and a second terminal, the first terminal coupled to the input port; ​ (d) A second Josephson junction having a first terminal and a second terminal, wherein the first terminal of the second Josephson junction is coupled to the second terminal of the first Josephson junction, and the second terminal of the second Josephson junction is coupled to the reference potential terminal; (e) A first inductor having a first terminal and a second terminal, wherein the first terminal of the first inductor is coupled to the second terminal of the first Josephson junction; (f) A first current source having a current input port and a current output port, the current input port being coupled to a second terminal of a second inductor; (g) The second inductor having a first terminal and a second terminal, wherein the first terminal of the second inductor is coupled to the first terminal of the current output port of the first current source; (h) A third Josephson junction having a first terminal and a second terminal, the first terminal of the third Josephson junction being coupled to the second terminal of the second inductor, and the second terminal of the third Josephson junction being coupled to the reference potential terminal.

8. The triple junction interferometer according to claim 7, further comprising a second current source having a current input port and a current output port, the current input port of the second current source being coupled to the reference potential terminal, and the current output port of the second current source being coupled to the second terminal of the first Josephson junction.

9. The three-junction interferometer of claim 7, further comprising an impedance matching device having a first terminal and a second terminal, the first terminal of the impedance matching device being coupled to an input port of the three-junction interferometer and the second terminal of the impedance matching device being configured to receive an input signal.

10. A digital logic circuit, comprising: (a) A driver circuit configured to receive a single-through-quantum (SFQ) input signal and convert the SFQ input signal into a non-SFQ voltage, the driver circuit comprising: (1) A first inductor having a first terminal and a second terminal; (2) A second inductor having a first terminal and a second terminal, wherein the first terminal of the second inductor is coupled to the second terminal of the first inductor; (3) A driving resistor having a first terminal and a second terminal, wherein the first terminal of the driving resistor is coupled to the second terminal of the second inductor; (4) A first Josephson junction having a first terminal and a second terminal, the first terminal of the first Josephson junction being coupled to the second terminal of the first inductor, and the second terminal of the first Josephson junction being coupled to a reference potential; and (5) A second Josephson junction having a first terminal and a second terminal, wherein the first terminal of the second Josephson junction is coupled to the second terminal of the second inductor, and the second terminal of the second Josephson junction is coupled to a reference potential; (b) a passive transmission line PTL having a driver end and a receiver end, the receiver end coupled to the second terminal of the driver resistance and having an impedance matched to the impedance of the driver resistance; and (c) a receiver comprising: (1) a third Josephson junction having a first terminal and a second terminal, the first terminal of the third Josephson junction coupled to the receiver end of the PTL and the second terminal of the third Josephson junction coupled to the reference potential.

11. The digital logic circuit of claim 10, wherein the driver circuit further comprises: (a) a first current source having a current input port and a current output port, the current input port of the first current source coupled to a reference potential, the current output port of the first current source coupled to the first terminal of the first Josephson junction; (b) a second current source having a current input port and a current output port, the current input port of the second current source coupled to a reference potential, the current output port of the second current source coupled to the first terminal of the second Josephson junction; and wherein the receiver further comprises: (a) a third current source having a current input port and a current output port, the current input port of the third current source coupled to a reference potential, the current output port of the third current source coupled to the first terminal of the third Josephson junction.

12. The digital logic circuit of claim 10, the receiver further comprising: (a) a fourth Josephson junction having a first terminal and a second terminal, the first terminal of the fourth Josephson junction coupled to the second terminal of the driver resistance and the second terminal of the fourth Josephson junction coupled to the first terminal of the first Josephson junction, such that the fourth Josephson junction is interpolated between the second terminal of the driver resistance and the first terminal of the third Josephson junction; (b) a third inductance having a first terminal and a second terminal, the first terminal of the third inductance coupled to the first terminal of the fourth Josephson junction and the second terminal of the third inductance coupled to the reference potential; (c) a fourth inductance having a first terminal and a second terminal, the first terminal of the fourth inductance coupled to the second terminal of the fourth Josephson junction; and (d) a fifth Josephson junction having a first terminal and a second terminal, the first terminal of the fifth Josephson junction coupled to the second terminal of the fourth inductance and the second terminal of the fifth Josephson junction coupled to the reference potential.

13. The digital logic circuit of claim 12, wherein the driver circuit further comprises: (a) a first current source having a current input port and a current output port, the current input port of the first current source coupled to a reference potential, the current output port of the first current source coupled to the first terminal of the first Josephson junction; and (b) a second current source having a current input port and a current output port, the current input port of the second current source coupled to a reference potential, the current output port of the second current source coupled to the first terminal of the second Josephson junction; and wherein the receiver further comprises: (a) a third current source having a current input port and a current output port, the current input port of the third current source coupled to a reference potential, the current output port of the third current source coupled to the first terminal of the third Josephson junction; and (b) a fourth current source having a current input port and a current output port, the current input port of the fourth current source coupled to the reference potential, and the current output port of the fourth current source coupled to the second terminal of the fourth inductor.

14. The digital logic circuit of claim 13, wherein the drive resistance and the PTL have an impedance of 16 ohms.

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