Memory device with two-transistor vertical memory cell

Abstract

Some embodiments include devices and methods of forming the devices. One of the devices includes a memory cell, first, second, and third data lines, and first and second access lines. The first data line is electrically coupled to a first channel region of a first transistor. The second data line is electrically coupled to the first channel region. The third data line is electrically coupled to a second channel region of a second transistor, the second channel region being electrically coupled to a charge storage structure and between the charge storage structure of the first transistor and the third data line. The first access line is located on a first level of the device. The second access line is located on a second level of the device. The charge storage structure is located on a level of the device between the first and second levels.

Description

[0001] Priority application

[0002] This application claims the benefit of priority to U.S. Provisional Application No. 62 / 785,154, filed on December 26, 2018, which is incorporated herein by reference in its entirety. Background Art

[0003] Memory devices are widely used in computers and many other electronic items to store information. Memory devices are generally classified into two types: volatile memory devices and non-volatile memory devices. Examples of volatile memory devices include dynamic random access memory (DRAM) devices. Examples of non-volatile memory devices include flash memory devices (e.g., flash memory sticks). Memory devices generally have many memory cells that store information. In volatile memory devices, if the supply power is disconnected from the memory device, the information stored in the memory cells is lost. In non-volatile memory devices, the information stored in the memory cells is retained even if the supply power is disconnected from the memory device.

[0004] The description herein relates to volatile memory devices. Most conventional volatile memory devices store information in the form of electric charge in a capacitor structure contained in a memory cell. As the demand for device storage density increases, many conventional techniques provide ways to reduce the size of the memory cell in order to increase the device storage density for a given device area. However, if the memory cell size shrinks to a certain size, then physical limitations and manufacturing constraints may set challenges for such conventional techniques. Unlike some conventional memory devices, the memory devices described herein include features that may overcome the challenges faced by conventional techniques. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 A block diagram is shown of an apparatus in the form of a memory device including volatile memory cells according to some embodiments described herein.

[0006] Figure 2 A schematic diagram illustrating a portion of a memory device including a memory array of two-transistor (2T) memory cells according to some embodiments described herein.

[0007] Figure 3 Showing some embodiments described herein Figure 2 A memory device including example voltages used during a read operation of an even-numbered memory cell of the memory device.

[0008] Figure 4 Showing some embodiments described herein Figure 2A memory device including example voltages used during a read operation of odd memory cells of the memory device.

[0009] Figure 5 Showing some embodiments described herein Figure 2 A memory device of the invention is provided, including example voltages used during a write operation of the memory device.

[0010] Figure 6 A schematic diagram showing a portion of a memory device including a shared read / write data line in each memory cell according to some embodiments described herein.

[0011] Figure 7 A schematic diagram showing a portion of a memory device including a shared access line for two transistors per memory cell according to some embodiments described herein.

[0012] Figure 8 A schematic diagram showing a portion of a memory device including a shared read / write data line in each memory cell and a shared access line for two transistors of each memory cell according to some embodiments described herein.

[0013] Fig. 9 A schematic diagram showing a portion of a memory device including a ground connection in each memory cell according to some embodiments described herein.

[0014] Fig.10 A schematic diagram showing a portion of a memory device including a ground connection in each memory cell and a shared access line for two transistors of each memory cell according to some embodiments described herein.

[0015] Fig.11 A top view showing the structure of a memory device according to some embodiments described herein.

[0016] FIG. 12A to FIG. 18B shows the formation of some embodiments described herein Fig.11 of the memory device.

[0017] Fig.19A and Fig.19B A side view of the structure of a memory device according to some embodiments described herein is shown, including a ground connection coupled to each memory cell of the memory device.

[0018] Fig. 20A , Fig. 20B and Fig. 20C Different views of the structure of a memory device including multiple stacks of memory cells according to some embodiments described herein are shown. DETAILED DESCRIPTION

[0019] The memory devices described herein include volatile memory cells, wherein each of the memory cells may include two transistors (2T). One of the two transistors has a charge storage structure that may form a memory element of the memory cell to store information. The memory devices described herein may have a structure that allows the size of the memory device to be relatively smaller than that of similar conventional memory devices (e.g., a 4F2 cell footprint). The described memory devices may include signal access lines for controlling the two transistors of the memory cell. This may result in reduced power dissipation and improved processing. Reference is made below to Figures 1 to 19B Other improvements and benefits of the described memory device and variations thereof are discussed.

[0020] Figure 1 A block diagram of an apparatus in the form of a memory device 100 including volatile memory cells according to some embodiments described herein is shown. The memory device 100 includes a memory array 101, which may contain memory cells 102. The memory device 100 is a volatile memory device (e.g., a DRAM device) such that the memory cells 102 are volatile memory cells. Therefore, if the supply power (e.g., the supply voltage Vcc) is disconnected from the memory device 100, the information stored in the memory cells 102 may be lost (e.g., invalid). Hereinafter, Vcc is mentioned to represent some voltage level, however, it is not limited to the supply voltage (e.g., Vcc) of the memory device (e.g., memory device 100). For example, if the memory device (e.g., memory device 100) has an internal voltage generator (e.g., Vcc) that generates an internal voltage based on Vcc, the memory device 100 may be disconnected from the supply power (e.g., Vcc). Figure 1 ), then such internal voltage may be used instead of Vcc.

[0021] In the physical structure of the memory device 100, each of the memory cells 102 may include transistors (e.g., two transistors) vertically formed in different levels (e.g., stacked on top of each other in different layers) above a substrate (e.g., a semiconductor substrate) of the memory device 100. The structure of the memory array 101 including the memory cells 102 may include the following reference Figures 2 to 19B Describes the structure of the memory array and memory cells.

[0022] like Figure 1, memory device 100 may include access lines (e.g., word lines) 104 and data lines (e.g., bit lines) 105. Memory device 100 may use signals on access lines 104 (e.g., word line signals) to access memory cells 102 and use signals on data lines 105 to provide information (e.g., data) to be stored (e.g., written) in memory cells 102 or read (e.g., sensed) from memory cells 102.

[0023] The memory device 100 may include an address register 106 to receive address information ADDR (e.g., row address signals and column address signals) on a line (e.g., address line) 107. The memory device 100 may include a row access circuit (e.g., X-decoder) 108 and a column access circuit (e.g., Y-decoder) 109 operable to decode the address information ADDR from the address register 106. Based on the decoded address information, the memory device 100 may determine which memory cells 102 will be accessed during a memory operation. The memory device 100 may perform a write operation to store information in the memory cell 102, and perform a read operation to read (e.g., sense) the information in the memory cell 102 (e.g., previously stored information). The memory device 100 may also perform an operation (e.g., a refresh operation) to refresh (e.g., keep valid) the value of the information stored in the memory cell 102. Each of memory cells 102 may be configured to store information that may represent at most one bit (e.g., a single bit having binary 0 (“0”) or binary 1 (“1”) or more than one bit (e.g., multiple bits having a combination of at least two binary bits).

[0024] Memory device 100 may receive supply voltages on lines 130 and 132, respectively, including supply voltages Vcc and Vss. Supply voltage Vss may operate at ground potential (e.g., having a value of substantially zero volts). Supply voltage Vcc may include an external voltage supplied to memory device 100 from an external power source such as a battery or an alternating current to direct current (AC-DC) converter circuit.

[0025] like Figure 1 As shown in , the memory device 100 may include a memory control unit 118, which includes circuits (e.g., hardware components) to control memory operations (e.g., read and write operations) of the memory device 100 based on control signals on lines (e.g., control lines) 120. Examples of signals on lines 120 include row access select signals RAS*, column access select signals CAS*, write enable signals WE*, chip select signals CS*, clock signals CK, and clock enable signals CKE. These signals may be part of the signals provided to the DRAM device.

[0026] like Figure 1, memory device 100 may include lines (e.g., global data lines) 112 that may carry signals DQ0 through DQN. In a read operation, the value of the information (e.g., “0” or “1”) provided to line 112 (in the form of signals DQ0 through DQN) (to be read from memory cell 102) may be based on the value of the signal on data line 105. In a write operation, the value of the information (e.g., “0” or “1”) provided to data line 105 (to be stored in memory cell 102) may be based on the value of the signals DQ0 through DQN on line 112.

[0027] Memory device 100 may include sense circuits 103, select circuits 115, and input / output (I / O) circuits 116. Column access circuits 109 may selectively activate signals on lines (e.g., select lines) based on address signals ADDR. Select circuits 115 may respond to signals on lines 114 to select signals on data lines 105. The signals on data lines 105 may represent the value of information to be stored in memory cell 102 (e.g., during a write operation) or the value of information to be read (e.g., sensed) from memory cell 102 (e.g., during a read operation).

[0028] I / O circuitry 116 may be operable to provide information read from memory cell 102 to line 112 (e.g., during a read operation) and to provide information from line 112 (e.g., provided by an external device) to data line 105 for storage in memory cell 102 (e.g., during a write operation). Line 112 may include a node within memory device 100 or a pin (or solder ball) on a package in which memory device 100 may reside. Other devices external to memory device 100 (e.g., a hardware memory controller or a hardware processor) may communicate with memory device 100 via lines 107, 112, and 120.

[0029] The memory device 100 may include other components not shown in the figure. Figure 1 1 to avoid obscuring the example embodiments described herein. At least a portion of the memory device 100 (eg, a portion of the memory array 101) may include the same Figures 2 to 19B Similar or identical structure and operation to any of the memory devices described.

[0030] Figure 2 Schematic diagram showing a portion of a memory device 200 including a memory array 201 according to some embodiments described herein. The memory device 200 may correspond to Figure 1 For example, the memory array 201 may be formed Figure 1 A portion of the memory array 101. Figure 2As shown, the memory device 200 may include memory cells 210 to 214, 220 to 224, and 230 to 234, which are volatile memory cells (e.g., DRAM cells). For simplicity, similar or identical elements among the memory cells 210 to 214, 220 to 224, and 230 to 234 have the same reference numbers. Also for simplicity, the memory cells 210 to 214, 220 to 224, and 230 to 234 are sometimes collectively referred to as "memory cells" of the memory device 200.

[0031] Each memory cell in the memory device 200 may include two transistors T1 and T2. Therefore, each memory cell in the memory device 200 may be referred to as a 2T memory cell (e.g., a 2T gain cell). Each of the transistors T1 and T2 may include a field effect transistor (FET). The transistor T1 may include a charge storage-based structure (e.g., a floating gate-based structure). Figure 2 As shown, each of the memory cells 210 to 214 may include a charge storage structure FG, which may include a floating gate of the transistor T1. The charge storage structure FG may form a memory element of a corresponding memory cell among the memory cells 210 to 214. The charge storage structure FG may store charge. The value (e.g., "0" or "1") of the information stored in a particular memory cell among the memory cells 210 to 214 may be based on the amount of charge in the charge storage structure FG of the particular memory cell.

[0032] Transistor T1 may include a channel region Ch1. Transistor T2 may include a channel region Ch2. In the physical structure of memory device 200, each of channel regions Ch1 and Ch2 may include a semiconductor material structure (eg, a pancake-shaped semiconductor material (eg, a layer of silicon or polysilicon)).

[0033] In each memory cell in the memory device 200, the transistor T1 may have a source terminal (at Figure 2 not marked in the figure) and the drain terminal (in Figure 2 In the physical structure of the memory device 200, the source terminal, the channel region Ch1, and the drain terminal of the transistor T1 of each memory cell in the memory device 200 may be formed of a single structure (e.g., a single piece) of the same material (e.g., a material having the same conductivity type (e.g., n-type or p-type)).

[0034] In each memory cell in the memory device 200, the transistor T2 may have a source terminal (at Figure 2 not marked in the figure) and the drain terminal (in Figure 2In the physical structure of the memory device 200, the source terminal, the channel region Ch2, and the drain terminal of the transistor T2 of each memory cell in the memory device 200 may be formed of a single structure (e.g., a single piece) of the same material (e.g., a material having the same conductivity type (e.g., n-type or p-type)).

[0035] like Figure 2 As shown, the channel region Ch2 of the transistor T2 of a specific memory cell among the memory cells of the memory device 200 may be electrically coupled to (e.g., directly coupled to) the charge storage structure FG of the specific memory cell. Therefore, during the operation (e.g., write operation) of the memory device 200, a circuit path (e.g., a current path) may be formed between the transistor T2 of the specific memory cell (e.g., between the channel region Ch2 of the transistor T2) and the charge storage structure FG of the specific memory cell.

[0036] The channel region Ch1 of the transistor T1 of a specific memory cell among the memory cells of the memory device 200 may be electrically coupled to (e.g., directly coupled to) the channel region Ch1 of the transistor T1 of at least one (one or more) adjacent memory cells. For example, the channel region Ch1 of the transistor T1 of the memory cell 212 may be electrically coupled to the channel region Ch1 of the transistor T1 of the memory cell 211 and the channel region Ch1 of the transistor T1 of the memory cell 213.

[0037] like Figure 2 As shown, memory cells 210 to 214 may be arranged into a memory cell group 201. 0 , 201 1 , 201 2 , 201 3 and 201 4 (201 0 By 201 4 ). Figure 2 Five memory cell groups 201 are shown as an example. 0 By 201 4 However, the memory device 200 may include more than five memory cell groups. 0 By 201 4 The same number of memory cells may be included in each group. 0 The memory cell group 201 may include memory cells 210, 220, and 230. 1 The memory cell group 201 may include memory cells 211, 221, and 231. 2The memory cell group 201 may include memory cells 212, 222, and 232. 3 The memory cell group 201 may include memory cells 213, 223, and 233. 4 Memory cells 214, 224, and 234 may be included. Figure 2 Memory cell group 201 is shown as an example. 1 By 201 4 Three memory cells in each of the memory cell groups 201. 1 By 201 4 The number of memory cells in may be different from three.

[0038] The memory device 200 may perform a write operation to store information in a memory cell, and perform a read operation to read (e.g., sense) information from a memory cell. The memory device 200 may be configured to function as a DRAM device. However, unlike some conventional DRAM devices that store information in a structure such as a container of a capacitor, the memory device 200 may store information in the form of charge in a charge storage structure FG (which may be a floating gate structure). As mentioned above, the charge storage structure FG may include a floating gate of a transistor T1. Therefore, the memory device 200 may be referred to as a floating gate-based DRAM device.

[0039] like Figure 2 As shown, memory device 200 may include access lines (e.g., word lines) 241W, 242W, 243W, 241R, 242R, and 243R, which may carry corresponding signals (e.g., word line signals) WL1W, WL2W, WL3W, WL1R, WL2R, and WL3R. Access lines (e.g., write word lines) 241W, 242W, and 243W and access lines (e.g., read word lines) 241R, 242R, and 243R may be used to access memory cell group 201. 1 By 201 4 Each of the access lines 241W, 242W, 243W, 241R, 242R, and 243R may be structured as at least one conductive line (eg, one conductive line or a plurality of conductive lines that may be electrically coupled (eg, shorted) to each other).

[0040] The access lines 241W, 242W, 243W, 241R, 242R, and 243R may be selectively activated (e.g., one at a time) during an operation (e.g., a read or write operation) of the memory device 200 to access a selected memory cell (or multiple selected memory cells) among the memory cells 210 to 215. The selected cell may be referred to as a target cell. In a read operation, information may be read from a selected memory cell (or multiple selected memory cells). In a read operation, the same memory cell group (memory cell group 201) may be selected each time. 0 , 201 1 , 201 2 , 201 3 or 201 4 ) to read information from the selected memory cell. In a read operation, different memory cell groups (e.g., memory cell group 201) sharing the same access line may be selected in parallel (or may be selected sequentially). 1 By 201 4 ) to read information from a selected memory cell.

[0041] In a write operation, information can be stored in a selected memory cell (or multiple selected memory cells). In a write operation, the same memory cell group (memory cell group 201) can be selected each time. 0 , 201 1 , 201 2 , 201 3 or 201 4 ) to store information in the selected memory cell. In a write operation, different memory cell groups (e.g., memory cell group 201) sharing the same access line may be selected in parallel (or may be selected sequentially). 1 By 201 4 ) to store information in a selected memory cell.

[0042] In the memory device 200, the gate of each of the transistors T1 and T2 may be part of (eg, may form part of) a corresponding access line (eg, a corresponding word line). Figure 2 As shown, the gate of transistor T1 of each of memory cells 210 to 214 may be part of access line 241R. The gate of transistor T1 of each of memory cells 220 to 224 may be part of access line 242R. The gate of transistor T1 of each of memory cells 230 to 234 may be part of access line 243R.

[0043] The gate of transistor T2 of each of memory cells 210-214 may be part of access line 241W. The gate of transistor T2 of each of memory cells 220-224 may be part of access line 242W. The gate of transistor T2 of each of memory cells 230-234 may be part of access line 243W.

[0044] Memory device 200 may include data lines (e.g., read data lines, also referred to as read digit lines) 250, 251, 252, 253, 254, and 255, which may carry corresponding signals (e.g., read data line signals, also referred to as read digit line signals) DL0, DL1, DL2, DL3, DL4, and DL5, and data lines (e.g., write data lines, also referred to as write digit lines) 260, 261, 262, 263, and 264, which may carry corresponding signals (e.g., write data line signals, also referred to as write digit line signals) DLW0, DLW1, DLW2, DLW3, and DLW4. Each of data lines 250 to 255 and 260 to 264 may be structured as a conductive line.

[0045] The data line may be a common data line (eg, a shared data line) of memory cells in the same memory cell group. 0 In the embodiment, data lines (eg, read data lines) 250 and 251 may be shared by memory cells 210 , 220 , and 230 , and data line (eg, write data line) 260 may be shared by memory cells 210 , 220 , and 230 .

[0046] During a read operation, the memory device 200 may selectively use data lines 250 to 255 to obtain data from the memory cell group 201. 0 By 201 4 During a write operation, memory device 200 may use data lines 260 to 264 to provide information to be stored in memory cell group 201. 0 By 201 4 The information in the selected memory cell in .

[0047] The memory device 200 may include a read path (e.g., a circuit path). Information read from a selected memory cell during a read operation may be obtained through the read path coupled to the selected memory cell. The read path of a particular memory cell may include a current path (e.g., a read current path) passing through the channel region Ch1 of the transistor T1 of the particular memory cell and two read data lines coupled (e.g., directly coupled) to the channel region Ch1 of the transistor T1 of the particular memory cell. For example, each of the memory cells 210, 220, and 230 may include a read path including a current path passing through the channel region Ch1 of the transistor T1 of the corresponding memory cell among the memory cells 210, 220, and 230 and data lines (e.g., read data lines) 250 and 251. In another example, each of the memory cells 211, 221, and 231 may include a read path including a current path through a channel region Ch1 of a transistor T1 of a corresponding memory cell among the memory cells 211, 221, and 231 and data lines (e.g., read data lines) 251 and 252. Because the transistor T1 may be used in the read path to read information from the corresponding memory cell during a read operation, the transistor T1 may be referred to as a read transistor, and the channel region Ch1 of the transistor T1 may be referred to as a read channel region.

[0048] The memory device 200 may include a write path (e.g., a circuit path). Information to be stored in a selected memory cell during a write operation may be provided to the selected memory cell through the write path coupled to the selected memory cell. The write path of a particular memory cell may include a current path (e.g., a write current path) through the channel region Ch2 of the transistor T2 of the particular memory cell and a data line coupled (e.g., directly coupled) to the channel region Ch2 of the transistor T2 of the particular memory cell. For example, each of the memory cells 210, 220, and 230 may include a write path including a current path through the channel region Ch2 of the transistor T2 of the corresponding memory cell among the memory cells 210, 220, and 230 and a data line (e.g., a write data line) 260. In another example, each of the memory cells 211, 221, and 231 may include a write path including a current path through the channel region Ch2 of the transistor T2 of the corresponding memory cell among the memory cells 211, 221, and 231 and a data line (e.g., a write data line) 261. Because transistor T2 may be used in a write path to store information in a corresponding memory cell during a write operation, transistor T2 may be referred to as a write transistor, and a channel region of transistor T2 may be referred to as a write channel region.

[0049] Each of transistors T1 and T2 may have a threshold voltage (Vt). Transistor T1 has a threshold voltage Vt1. Transistor T2 has a threshold voltage Vt2. During a write operation, transistor T2 of a particular memory cell (e.g., a selected memory cell) may be controlled (e.g., turned on) to transfer information (to be stored in the particular memory cell) from a corresponding write data line to the charge storage structure FG of the particular memory cell.

[0050] During a read operation, the transistor T1 of a particular memory cell (e.g., a selected memory cell) may be controlled (e.g., turned on) to transfer information (e.g., previously stored information) from the particular memory cell to a corresponding data line coupled to the transistor T1 of the particular memory cell. Figure 2 In the connection of the memory device 200 of FIG. 1 , the charge storage structure FG of the transistor T1 may be referred to as the “back gate” of the transistor T1. In a read operation to read (e.g., sense) information from a selected memory cell, the threshold voltage Vt1 of the transistor T1 of the selected memory cell may be switched by the bias of the charge storage structure FG (e.g., back gate) of the transistor T1. The connection of the charge storage structure FG of the transistor T1 and the transistor T2 of the memory device 200 (e.g., back gate) Figure 2 ) can help use a relatively low operating bias voltage to control the transistor T1 of the selected memory cell, thereby reducing the power consumption of the memory device 200.

[0051] The memory cells of the memory device 200 may be divided (e.g., logically divided) into even memory cells and odd memory cells. In the physical structure of the memory device 200, the memory cells (e.g., memory cells that share the same access line) may be located close to each other such that the even memory cells are interleaved with the odd memory cells (or vice versa). For example, an even memory cell may be located close to two odd memory cells, and an odd memory cell may be located close to two even memory cells. As an example, in Figure 2 , memory cells 210, 212, 214, 220, 222, 224, 230, 232, and 234 may be referred to as even memory cells, and memory cells 211, 213, 221, 223, 231, and 233 may be referred to as odd memory cells.

[0052] Even memory cells may include memory cells located at even positions (e.g., positions associated with even addresses). Odd memory cells may include memory cells located at odd addresses (e.g., positions associated with odd addresses). The terms "even" (e.g., as used in even memory cells) and "odd" (e.g., as used in odd memory cells) are for convenience in distinguishing one portion of memory cells of the memory device 200 from another portion of memory cells of the memory device 200. However, the terms "even" and "odd" may be used interchangeably with each other.

[0053] In a read operation, the memory device 200 may access the even memory cells during a time interval to read information from the even memory cells, and access the odd memory cells during another time interval to read information from the odd memory cells. In the same read operation, the even memory cells may be accessed and read before the odd memory cells are accessed and read. Alternatively, in the same read operation, the odd memory cells may be accessed and read before the even memory cells are accessed and read.

[0054] Figure 3 Showing some embodiments described herein Figure 2 Memory device 200 includes example voltages V0, V1, V2, V3, V4, and V5 used during read operations of even memory cells. Figure 3 Assume that memory cells 210, 212, and 214 are even memory cells and selected memory cells (e.g., target memory cells) during a read operation to read (e.g., sense) information stored (e.g., previously stored) in memory cells 210, 212, and 214. Assume that other memory cells ( Figure 3 The memory cells of the memory device 200 other than the memory cells 210, 212 and 214 in FIG. 2 are non-selected memory cells. This means that Figure 3 In the example of , when information is read from the memory cells (selected memory cells) 210, 212, and 214, these non-selected memory cells are not accessed, and information stored in the non-selected memory cells is not read.

[0055] exist Figure 3 , voltages V0, V1, V2, V3, V4, and V5 may represent different voltages applied to access lines 241W, 241R, 242W, 242R, 243W, and 243R and data lines (e.g., read data lines) 250 to 255 during a read operation of the memory device 200. Each of the currents (e.g., read currents) I0, I2, and I4 may represent a current flowing through a corresponding read path including a selected memory cell and two corresponding data lines coupled to the selected memory cell. Figure 3As shown, the current I0 can represent the current flowing through the data lines 250 and 251 and the memory cell 210 (in Figure 3 I2 may represent the current flowing through the read path including data lines 252 and 253 and memory cell 212 (in the example of the selected memory cell). Figure 3 The current I4 may represent the current flowing through the read path including data lines 254 and 255 and memory cell 214 (in the example of the selected memory cell). Figure 3 In the example of , the current in the read path of the selected memory cell).

[0056] exist Figure 3 In the read operation shown, voltages V1, V2, V3, and V4 may have values ​​such that transistors T1 and T2 of each of memory cells 220-224 and 230-234 (unselected memory cells in this example) are turned off (eg, remain off).

[0057] The voltage V0 may have a value of 0V (e.g., ground), and the voltage V5 may have a value (voltage value) to turn on the transistor T1 of each of the memory cells (selected memory cells) 210, 212, and 214 and to turn off (or keep off) the transistor T1 of each of the memory cells 211 and 213. This enables information to be read from the memory cells 210, 212, and 214.

[0058] The memory device 200 can determine the values ​​(e.g., binary values) of the information stored in the memory cells 210, 212, and 214 based on the values ​​(e.g., analog values) of the currents I0, I2, and I4, respectively. For example, a detection circuit (not shown) of the memory device 200 can be used to convert the values ​​of the currents I0, I2, and I4 (or the values ​​of the voltages on the data lines 251, 252, and 255) into the values ​​of the information read from the selected memory cell (e.g., "0", "1", or a combination of multi-bit values).

[0059] Figure 4 Showing some embodiments described herein Figure 2 Memory device 200 includes example voltages V0, V1, V2, V3, V4, and V5 used during read operations of odd memory cells. Figure 4 Assume that memory cells 211 and 213 are odd memory cells and selected memory cells (e.g., target memory cells) during a read operation to read (e.g., sense) information stored (e.g., previously stored) in memory cells 211 and 213. Assume that other memory cells ( Figure 4 The memory cells of the memory device 200 other than the memory cells 211 and 213 in FIG. 2 are non-selected memory cells. This means that Figure 4In the example of , when information is read from the memory cells (selected memory cells) 211 and 213, these non-selected memory cells are not accessed, and information stored in the non-selected memory cells is not read.

[0060] exist Figure 4 , voltages V0, V1, V2, V3, V4, and V5 may represent different voltages applied to access lines 241W, 241R, 242W, 242R, 243W, and 243R and data lines (e.g., read data lines) 250 to 255 during a read operation of the memory device 200. Each of the currents (e.g., read currents) I1 and I3 may represent a current flowing through a corresponding read path including a selected memory cell and two corresponding data lines coupled to the selected memory cell. Figure 4 As shown, current I1 may represent a current flowing through a read path including data lines 251 and 252 and memory cell 211. Current I3 may represent a current flowing through a read path including data lines 253 and 254 and memory cell 213.

[0061] exist Figure 4 In the read operation shown, voltages V1, V2, V3, and V4 may have values ​​such that transistors T1 and T2 of each of memory cells 220-224 and 230-234 (unselected memory cells in this example) are turned off (eg, remain off).

[0062] The voltage V0 may have a value of 0V (e.g., ground), and the voltage V5 may have a value (voltage value) to turn on the transistor T1 of each of the memory cells (selected memory cells) 211 and 213 and turn off (or keep off) the transistor T1 of each of the memory cells 210, 212, and 214. This enables information to be read from the memory cells 211 and 213.

[0063] The memory device 200 can determine the value (e.g., binary value) of the information read from the memory cells 211 and 213 based on the values ​​(e.g., analog values) of the currents I1 and I3, respectively. For example, a detection circuit (not shown) of the memory device 200 can be used to convert the values ​​of the currents I1 and I3 (or the values ​​of the voltages on the data lines 251 and 254) into the value of the information read from the selected memory cell (e.g., "0", "1", or a combination of multi-bit values).

[0064] Figure 3 and Figure 4 The instance read operations of can be different read operations executed at different times. However, Figure 3 and Figure 4The example read operations of can be part of the same read operation. In the example, memory cells 210, 211, 212, 213, and 214 can be selected memory cells. Therefore, the reading of memory cells 210, 212, and 214 can be performed before (or, can be performed after) the reading of memory cells 211 and 213.

[0065] Figure 5 Showing some embodiments described herein Figure 2 A memory device of the invention includes example voltages V6, V7, V8, V9, Vx, VDL0, VLD1, VDL2, VDL3, and VLD4 used during a write operation of the memory device. Figure 5 Assume that memory cells 210, 211, 212, 213, and 214 are selected memory cells (e.g., target memory cells) during a write operation to store information in memory cells 210, 211, 212, 213, and 214. Assume that memory cells 220 to 224 and 230 to 234 are non-selected memory cells. This means that Figure 5 In the example of , when information is stored in memory cells (selected memory cells) 210, 211, 212, 213, and 214, memory cells 220 to 224 and 230 to 234 are not accessed, and information (eg, new information) is not stored in memory cells 220 to 224 and 230 to 234.

[0066] exist Figure 5 , voltages V6, V7, V8, V9, Vx, VDL0, VLD1, VDL2, VDL3, and VLD4 may represent different voltages applied to access lines 241W, 241R, 242W, 242R, 243W, and 243R and data lines (e.g., write data lines) 260 to 264 during a write operation of the memory device 200.

[0067] exist Figure 5 In the write operation shown, voltages V6, V7, V8, and V9 may have values ​​such that transistors T1 and T2 of each of memory cells 220-224 and 230-234 (non-selected memory cells in this example) are turned off (eg, remain off).

[0068] like Figure 5As shown, each of the data lines (e.g., read data lines) 250-255 may have a voltage Vx applied to it or be in a "FLOAT" condition. The voltage Vx may have a value of 0V (e.g., ground) or another value different from 0V. Placing a particular conductive line (e.g., data lines 250-255) in a FLOAT condition during a particular operation may include causing the potential on the particular conductive line to vary or "float" (e.g., by not coupling the particular conductive line to a fixed potential (e.g., ground or other voltage). Figure 5 In an example write operation, each of the data lines 250-255 can be placed in a FLOAT condition by, for example, decoupling each of the data lines 250-255 from ground or a fixed positive voltage source. This allows the potential on each of the data lines 250-255 to change (e.g., "float") during an operation in which the memory cells 210-214 (in this example, the selected memory cells) store information.

[0069] exist Figure 5 In an example write operation of , the values ​​of voltages VDL0, VLD1, VDL2, VDL3, and VLD4 may be based on the values ​​of information to be stored in memory cells 210, 211, 212, 213, and 214, respectively. For example, if the information to be stored in memory cell 210 has one value (e.g., "0"), the voltage VDL0 may have one value (e.g., VDL0=0V). If the information to be stored in memory cell 210 has another value (e.g., "1"), the voltage VDL0 may have another value (e.g., VDL0>0V). Similarly, each of the voltages VLD1, VDL2, VDL3, and VLD4 may have different values ​​(e.g., 0V and another value different from 0V) based on the information to be stored in the corresponding memory cell among the memory cells 211, 212, 213, and 214.

[0070] exist Figure 5 During a write operation of , the voltage V6 may have a value to turn on the transistor T2 of each of the memory cells 210 to 214 (the selected memory cells in this example) and form a write path between the charge storage structure FG of each of the memory cells 210 to 214 and the corresponding write data line among the data lines 260 to 264. A current (e.g., a write current) may be formed between the charge storage structure FG of each of the memory cells 210 to 214 and the corresponding write data line among the data lines 260 to 264. This current may affect (e.g., change) the amount of charge on the charge storage structure FG of the memory cells 210 to 214, thereby reflecting the value of the information to be stored in the memory cells 210 to 214.

[0071] exist Figure 5In an example write operation, the values ​​of voltages VDL0, VLD1, VDL2, VDL3, and VLD4 may respectively discharge or charge the charge storage structure FG of memory cells 210, 211, 212, 213, and 224, so that the resulting charge on the charge storage structure FG of a particular memory cell among the memory cells 210, 211, 212, 213, and 224 (e.g., the charge retained after the discharge or charge action) may reflect the value of the information stored in the particular memory cell.

[0072] Figure 6 Schematic diagram showing a portion of a memory device 600 including a shared read / write data line in each memory cell according to some embodiments described herein. The memory device 600 may be Figure 2 Therefore, for simplicity, similar or identical elements between memory devices 200 and 600 have the same reference numerals, and their descriptions are not repeated.

[0073] like Figure 6 As shown, the memory device 600 may include data lines (shared read / write data lines) 660, 661, 662, 663, 664, and 665 (660 to 660). Each of the data lines 660 to 660 may be shared by the transistors T1 and T2 of the corresponding memory cells. For example, the data line (e.g., shared read / write data line) 660 may be shared by the transistors T1 and T2 of each of the memory cells 210, 220, and 230. The data line (e.g., shared read / write data line) 661 may be shared by the transistors T1 and T2 of each of the memory cells 211, 221, and 231. The data line (e.g., shared read / write data line) 662 may be shared by the transistors T1 and T2 of each of the memory cells 212, 222, and 232. A data line (e.g., a shared read / write data line) 663 may be shared by transistors T1 and T2 of each of memory cells 213, 223, and 233. A data line (e.g., a shared read / write data line) 664 may be shared by transistors T1 and T2 of each of memory cells 214, 224, and 234.

[0074] like Figure 6 As shown, data lines 660, 661, 662, 663, and 664 may be provided with signals DL1 / DLW0, DL2 / DLW1, DL3 / DLW2, DL4 / DLW3, and DL5 / DLW4, respectively. During operation (e.g., a read or write operation) of memory device 600, signal DL1 / DLW0 may be provided with the same Figures 3 to 5For example, during a read operation of memory device 600, signal DL1 / DLW0 may be provided with a voltage similar to that provided to the above reference. Figure 2 and Figure 3 In another example, during a write operation of the memory device 600, the signal DL1 / DLW0 may be provided with a voltage similar to that provided to the above reference signal DL1. Figure 5 Similarly, signals DL2 / DLW1, DL3 / DLW2, DL4 / DLW3, and DL5 / DLW4 may be provided with voltages corresponding to the voltages of the signal DLW0 described above. Figure 3 , Figure 4 and Figure 5 voltages similar to (or the same as) those of the memory device 600, depending on the operation of the memory device 600 (eg, a read or write operation).

[0075] Figure 7 Schematic diagram showing a portion of a memory device 700 including a shared access line for transistors T1 and T2 for each memory cell according to some embodiments described herein. The memory device 700 may be Figure 2 Therefore, for simplicity, similar or identical elements between the memory devices 200 and 700 have the same reference numerals, and their descriptions are not repeated.

[0076] like Figure 7 As shown, the memory device 600 may include access lines (word lines) 741, 742, and 743. Each of the access lines 741, 742, and 743 may be shared by the transistors T1 and T2 of the corresponding memory cells, so that the same access line can be used to control (e.g., turn on or off) the transistors T1 and T2 of the corresponding memory cells. For example, the access line (e.g., shared access line) 741 may be shared by the transistors T1 and T2 of each of the memory cells 210, 211, 212, 213, and 214. This means that a single access line (e.g., access line 741) can be used to control (e.g., turn on or off) the transistors T1 and T2 of the memory cell 210. Similarly, the access line 741 can be used to control (e.g., turn on or off) the transistors T1 and T2 of each of the memory cells 211, 212, 213, and 214.

[0077] In another example, an access line (e.g., a shared access line) 742 can be shared by the transistors T1 and T2 of each of the memory cells 220, 221, 222, 223, and 224. This means that a single access line (e.g., access line 742) can be used to control (e.g., turn on or off) the transistors T1 and T2 of each of the memory cells 220, 221, 222, 223, and 224.

[0078] In another example, an access line (e.g., a shared access line) 743 can be shared by the transistors T1 and T2 of each of the memory cells 230, 231, 232, 233, and 234. This means that a single access line (e.g., access line 742) can be used to control (e.g., turn on or off) the transistors T1 and T2 of each of the memory cells 230, 231, 232, 233, and 234.

[0079] like Figure 7 As shown, access lines 741, 742, and 743 may be provided with signals WL1, WL2, and WL3, respectively. Each of signals WL1, WL2, and WL3 may be provided with different voltages during different operations of memory device 700 (eg, read and write operations).

[0080] As mentioned above Figure 2 As described, transistor T1 may have a threshold voltage Vt1, and transistor T2 may have a threshold voltage Vt2. Figure 7 In the embodiment, the values ​​of threshold voltages Vt1 and Vt2 may be different so that a single access line (e.g., access line 741, 742, or 743) may be used to control transistors T1 and T2 of corresponding memory cells. The value of threshold voltage Vt2 may be greater than the value of threshold voltage Vt2 (e.g., Vt2>Vt1).

[0081] During a read operation of the memory device 700, the signals WL1, WL2, and WL3 may be provided with voltages such that the transistor T1 of a selected memory cell (or multiple selected memory cells) of the memory device 700 may be turned on, and the transistor T1 of each non-selected memory cell in the memory device 700 may be turned off (when the transistor T1 of the selected memory cell is turned on). During a read operation of the memory device 700, the signals WL1, WL2, and WL3 may be provided with voltages such that the transistor T2 of each memory cell (selected and non-selected memory cells) in the memory device 700 may be turned off. The voltages provided to the signals WL1, WL2, and WL3 during the read operation may be different from the voltages provided to the signals WL1, WL2, and WL3 during the read operation. Figure 5 The voltages respectively provided to the signals WL1R, WL2R and WL3R are similar or the same.

[0082] As an example, if at least one of the memory cells 210, 211, 212, 213, and 214 is selected during a read operation (to read information from the selected one memory cell (or multiple memory cells)), the signals WL1, WL2, and WL3 may be provided with a voltage (e.g., the access lines 741, 742, and 743 may be applied with a voltage) so that the transistor T2 of each of the memory cells 210 to 214, 220 to 224, and 230 to 234 may be turned off, and the transistor T1 of each of the memory cells 220 to 224 and 230 to 234 may be turned off. In this example, the signal WL1 may be provided with a voltage so that the transistor T1 of the selected one memory cell (or multiple selected memory cells) among the memory cells 210 to 214 may be turned on. This enables information to be read (e.g., sensed) from the selected one memory cell (or multiple selected memory cells) among the memory cells 210 to 214.

[0083] During a write operation of the memory device 700, the signals WL1, WL2, and WL3 may be provided with voltages such that the transistor T2 of a selected memory cell (or a plurality of memory cells) of the memory device 700 may be turned on, and the transistor T2 of each non-selected memory cell in the memory device 700 may be turned off (when the transistor T2 of the selected memory cell is turned on). The voltages provided to the signals WL1, WL2, and WL3 during a write operation may be different from the voltages provided to the signals WL1, WL2, and WL3. Figure 5 The voltages respectively provided to signals WL1W, WL2W and WL3W are similar or identical.

[0084] As an example, if at least one of the memory cells 210, 211, 212, 213, and 214 is selected during a write operation (to store information in the selected memory cell (or cells)), the signals WL1, WL2, and WL3 may be provided with a voltage (e.g., the access lines 741, 742, and 743 may be applied with a voltage) so that the transistor T2 of each of the memory cells 220 to 224 and 230 to 234 may be turned off. In this example, the signal WL1 may be provided with a voltage so that the transistor T2 of the selected memory cell (or cells) among the memory cells 210 to 214 may be turned on. This enables information to be stored in the selected memory cell (or cells) among the memory cells 210 to 214.

[0085] Figure 8 Schematic diagram of a portion of a memory device 800 including a shared read / write data line in each memory cell and a shared access line for two transistors in each memory cell according to some embodiments described herein. The memory device 800 may be a memory device 200 ( Figure 2 )、Memory device 600( Figure 6 ) and the memory device 700 ( Figure 7 ). Therefore, for simplicity, similar or identical elements between memory devices 200, 600, 700, and 800 have the same reference numerals, and their descriptions are not repeated. Figure 8 As shown, the memory device 800 may include Figure 6 A portion of the memory device 600 (eg, a shared read / write data line) and Figure 7 Memory device 800 may include a portion of memory device 700 (eg, a shared access line for transistors T1 and T2 in each memory cell) (eg, a combination of elements). Memory device 800 may include the same as described above with reference to Figure 6 and Figure 7 The operations of the described memory devices 600 and 700 are similar (or identical) operations (eg, read and write operations).

[0086] Fig. 9 A schematic diagram showing a portion of a memory device 900 including a ground connection in each memory cell according to some embodiments described herein. The memory device 900 may be Figure 2 Therefore, for simplicity, similar or identical elements between memory devices 200 and 900 have the same reference numerals, and their descriptions are not repeated.

[0087] like Fig. 9 As shown, the memory device 900 may include data lines (e.g., read data lines) 950, 951, 952, 953, and 954, conductive lines 990A, 990B, and 990C, and a ground connection (e.g., a ground node) 999. Each of the memory cells 210-214, 220-224, and 230-234 may include a terminal (e.g., a source terminal of transistor T1) that may be coupled (e.g., may be grounded) to the ground connection 999 through a corresponding conductive line among the conductive lines 990A, 990B, and 990C.

[0088] During a read operation, data lines 950, 951, 952, 953, and 954 may be provided with a voltage (e.g., carried by signals DL0, DL1, DL2, DL3, and DL4, respectively) so that a current associated with a selected memory cell (e.g., a combination of currents I0, I2, and I4 or a combination of currents I1 and I3) may flow through a read path of the corresponding selected memory cell. For example, if an even memory cell is selected, each of the signals DL0, DL2, and DL4 may be provided with a voltage having a positive value, and each of the signals DL1 and DL3 may be provided with a voltage of 0V. In another example, if an odd memory cell is selected, each of the signals DL1 and DL3 may be provided with a voltage having a positive value, and each of the signals DL0, DL2, and DL4 may be provided with a voltage of 0V.

[0089] The memory device 900 may perform a read operation to read information (e.g., previously stored information) from even memory cells and odd memory cells at different time intervals. The even memory cells may be read before or after the reading of the odd memory cells. Fig. 9 , a combination of even-numbered memory cells that may be read during a read operation (e.g., one combination at a time) may include a combination of memory cells 210, 212, and 214, a combination of memory cells 220, 222, and 224, or a combination of memory cells 230, 232, and 234. A combination of odd-numbered memory cells that may be read during a read operation (e.g., one combination at a time) may include a combination of memory cells 211 and 213, a combination of memory cells 221 and 223, or a combination of memory cells 231 and 233.

[0090] Fig. 9 The currents I0, I2, and I4 in may represent the current flowing in the read path of the corresponding even memory cell selected during the read operation. The currents I1 and I3 may represent the current flowing in the read path of the corresponding odd memory cell selected during the read operation. The read path may include a current path between one of the data lines 950 to 954 and one of the conductive lines 990A, 990B, and 990C. As mentioned above, the even memory cells and the odd memory cells may be selected one at a time (e.g., selected at different times). Therefore, the currents I0, I2, and I4 may appear at a certain time interval during the reading of the even memory cells, and the currents I1 and I3 may appear at another time interval during the reading of the odd memory cells.

[0091] For example, if memory cells (e.g., even memory cells) 210, 212, and 214 are selected during a read operation, current I0 may represent a current flowing in a read path including data line 950, transistor T1 of memory cell 210, and conductive line 990A; current I2 may represent a current flowing in a read path including data line 952, transistor T1 of memory cell 212, and conductive line 990B; and current I4 may represent a current flowing in a read path including data line 954, transistor T1 of memory cell 214, and conductive line 990C.

[0092] In another example, if memory cells (e.g., odd memory cells) 211 and 213 are selected during a read operation, current I1 may represent a current flowing in a read path including data line 951, transistor T1 of memory cell 211, and conductive line 990A, and current I3 may represent a current flowing in a read path including data line 953, transistor T1 of memory cell 213, and conductive line 990B.

[0093] Memory device 900 may include write operations similar to the write operations of memory device 200. For example, memory device 900 may perform write operations to store information in selected memory cells, where the values ​​of the information to be stored may be based on the values ​​(e.g., voltage values) provided to signals DLW0, DLW1, DLW2, DLW3, and DLW4.

[0094] Fig.10 Schematic diagram showing a portion of a memory device 1000 including a ground connection in each memory cell and a shared access line for transistors T1 and T2 of each memory cell according to some embodiments described herein. The memory device 1000 may be a memory device 200 ( Figure 2 )、Memory device 700( Figure 7 ) and a memory device 900 ( Fig. 9 ). Therefore, for simplicity, similar or identical elements between memory devices 200, 700, 900, and 1000 have the same reference numerals, and their descriptions are not repeated. For example, as Fig. 9 Memory device 900, memory device 1000 may include memory cells where each memory cell may include a terminal (e.g., a source terminal) coupled to ground connection 999. In another example, as Figure 7 The memory device 700 of FIG. 1000 may include transistors T1 and T2 of each memory cell in the memory device 1000 that are controlled by a single access line (eg, one of the access lines 741, 742, and 743). The memory device 1000 may include the same memory cell as described above with reference to FIG. Figure 7 and Fig. 9 The operations of the described memory devices 700 and 900 are similar (or identical) operations (eg, read and write operations).

[0095] Fig.11 1 shows a top view of the structure of a memory device 1100 according to some embodiments described herein. For simplicity, Fig.11 Some elements (eg, materials) forming part of the memory device 1100 are omitted. Fig.11 As shown in , elements of memory device 1100 can be positioned relative to the X direction and the Y direction (e.g., the XY plane). Lines AA and BB indicate cross-sectional lines showing the positions of some elements of memory device 1100 relative to the X direction and the Y direction, respectively, during a process (described below) of forming memory device 1100.

[0096] The memory device 1100 may include memory cells 210', 211', and 212' (which may represent Figure 2 Memory cells 210, 211 and 212 of the memory device 200); memory cells 220', 221' and 222' (which may respectively represent Figure 2 Memory cells 220, 221 and 222 of the memory device 200); memory cells 230', 231' and 232' (which may respectively represent Figure 2 Memory units 230, 231 and 232 of the memory device 200); and memory units 240', 241' and 242'. Fig.11 As shown, each memory cell in the memory device 1100 may include transistors T1 and T2, which may represent Figures 2 to 8 The transistors T1 and T2 of each memory cell in the memory device shown in FIG. Fig.11 As shown, the transistor T2 of each memory cell in the memory device 1100 may include a channel region Ch2 (eg, a write channel). The transistors T1 and T2 of each memory cell in the memory device 1100 may be located at the location of the channel region Ch2 of the transistor T2 of the corresponding memory cell.

[0097] like Fig.11 As shown, the memory device 1100 may include data lines (e.g., read data lines) 1650, 1651, 1652, and 1653, and data lines (e.g., write data lines) 1861, 1862, and 1863. Each of the data lines 1650, 1651, 1652, 1653, 1861, 1862, and 1863 may have a length extending along the Y direction.

[0098] Memory device 1100 may include conductive lines 1741W′, 1741W″, 1742W′, 1742W″, 1743W′, 1743W″, 1744W′, and 1744W″, which may be part of access lines (e.g., write word lines) of memory device 1100. Each of conductive lines 1741W′, 1741W″, 1742W′, 1742W″, 1743W′, 1743W″, 1744W′, and 1744W″ may have a length extending along the X direction.

[0099] Memory device 1100 may include conductive lines 1441R′, 1441R″, 1442R′, 1442R″, 1443R′, 1443R″, 1444R′, and 1444R″, which may be below (e.g., from) respective conductive lines 1741W′, 1741W″, 1742W′, 1742W″, 1743W′, 1743W″, 1744W′, and 1744W″. Fig.11 Conductive lines 1441R', 1441R", 1442R', 1442R", 1443R', 1443R", 1444R', and 1444R" may be part of other access lines (e.g., read word lines) of memory device 1100. Each of conductive lines 1441R', 1441R", 1442R', 1442R", 1443R', 1443R", 1444R', and 1444R" may have a length extending along the X direction.

[0100] FIG. 12A to FIG. 18B shows the formation of some embodiments described herein Fig. 12A and 12B Some or all of the processes for forming the memory device 1100 may be used to form the memory device 1100 described above. Figures 2 to 10 The memory device 200, 600, 700 or 800 described herein. In the following description, a figure marked with an "A" next to a figure number (e.g., Fig. 12A , Fig.13A , Fig.14A , Fig.15A , Fig.16A , Fig.17A and Fig.18A ) is along Fig.11 1100 of line AA of the memory device ( Fig.11 ) of a drawing (e.g., a cross-sectional view). A drawing immediately adjacent to a drawing number marked with a "B" (e.g., Fig. 12B , Fig. 13B , Fig. 14B , Fig. 15B , Fig. 16B , Fig. 17B and Fig.18B ) is along Fig.11 Memory device 1100 ( Fig.11 ) of the device (e.g., a cross-sectional view).

[0101] Fig. 12A and Fig. 12B The memory device 1100 is shown after dielectric material 1290, semiconductor material 1210, and dielectric material 1235 are formed in corresponding levels (e.g., layers) above substrate 1298 along the Z direction. The Z direction (e.g., vertical direction) is a direction perpendicular to substrate 1298 (e.g., outward from the substrate). The Z direction is also perpendicular to the X direction and the Y direction. Substrate 1298 can be a semiconductor substrate (e.g., a silicon-based substrate) or other type of substrate. Semiconductor material 1210 can include silicon, polysilicon (e.g., doped or undoped polysilicon), or other semiconductor material (or multiple materials). Dielectric material 1290, semiconductor material 1210, and dielectric material 1235 can be formed in a sequential manner of materials (e.g., one material layer) one after another in different levels of memory device 1100 above substrate 1298. For example, Fig. 12A and 12B The process used in the embodiment may include forming (eg, depositing) a dielectric material (eg, silicon dioxide SiO 2 ) 1290, a semiconductor material (e.g., silicon) 1210 is formed (e.g., deposited) over the dielectric material 1290, and a dielectric material 1235 (e.g., silicon nitrite SiN) is formed (e.g., deposited) over the semiconductor material 1210. 4 ). In alternative structures of the memory device 1100 , the dielectric material 1290 , the substrate 1298 , or both may be omitted such that the semiconductor material 1210 is the substrate of the memory device 1100 .

[0102] Fig.13A and Fig. 13B The memory device 1100 is shown after the trenches 1301, 1302, and 1303 are formed and then other elements including a charge storage structure FG, a dielectric material 1311, and a dielectric material 1312 are formed in the trenches 1301, 1302, and 1303. Each of the dielectric materials 1311 and 1312 may include silicon oxide (e.g., silicon dioxide). The material of the charge storage structure FG may include a structure of semiconductor material, which may include a block (e.g., a layer) of semiconductor material (e.g., polysilicon) or a block (e.g., a layer) of metal.

[0103] Forming trenches 1301, 1302, and 1303 may include removing a portion of dielectric material 1235 and a portion of semiconductor material 1210 at the locations of trenches 1301, 1302, and 1303. Each of trenches 1301, 1302, and 1303 may have a length along the Y direction, a width along the X direction (shorter than the length), and a bottom (not labeled) disposed on a corresponding portion of semiconductor material 1210. Dielectric material 1311, charge storage structure FG, and dielectric material 1312 may be formed in a sequential order, which may include forming dielectric material 1311, forming charge storage structure FG, and then forming dielectric material 1312.

[0104] Fig.14A and Fig. 14B Memory device 1100 is shown in which dielectric material (e.g., gate oxide) 1411, conductive lines (e.g., conductive regions) 1441R', 1441R", 1442R', 1442R", 1443R', 1443R", 1444R', and 1444R" (collectively referred to as conductive lines 1441R-1444R), and dielectric material 1412 are formed in respective trenches 1401, 1402, 1403, 1404, and 1405, following formation of trenches 1401, 1402, 1403, 1404, and 1405. Dielectric material 1411 may include silicon dioxide or other dielectric materials. Dielectric material 1412 may include silicon nitride or other dielectric materials. Each of conductive lines 1441R-1444R may include metal, conductively doped polysilicon, or other conductive materials.

[0105] Forming trenches 1401, 1402, 1403, 1404, and 1405 may include removing a portion of dielectric material 1235, a portion of semiconductor material 1210, a portion of dielectric material 1311, a portion of dielectric material 1312, and a portion of charge storage structure FG at the locations of trenches 1401, 1402, and 1403. Each of trenches 1401, 1402, 1403, 1404, and 1405 may have a length along the X direction, a width along the Y direction (shorter than the length), and a bottom (not labeled) disposed on a corresponding portion of semiconductor material 1210. Fig.14A and Fig. 14B As shown, in the Z direction, relative to the position of the charge storage structure FG, the bottom of each of the trenches 1401, 1402, 1403, 1404, and 1405 may be lower than (e.g., deeper than) the bottom of each of the trenches 1301, 1302, 1303, and 1304. Therefore, conductive lines 1441R-1444R may be formed under the charge storage structure FG of each memory cell in the memory device 1100. This may improve the operation of the memory device 1100 (e.g., allowing a lower operating bias voltage to be used on the access line).

[0106] Each of the conductive lines 1441R-1444R may have a length extending along the X direction, a width extending along the Z direction, and a thickness extending along the Y direction. Fig.14A As shown, each of conductive line 1441R (which is formed in trench 1401) and conductive line 1441R″ (which is formed in trench 1402) may have a length extending along the X direction, a width extending along the Z direction (e.g., smaller than the length), and a thickness extending along the Y direction (e.g., smaller than the width).

[0107] like Fig.14A As shown, a portion of memory device 1100 may form a portion of memory cells 220', 221', and 222' (in the X direction). Fig. 14B As shown, a portion of the memory device 1100 may form a portion of the memory cells 212', 222', 232', and 242' (in the Y direction). A portion of the semiconductor material 1210 may form a channel region Ch1 of a transistor T1 ("T1" is not labeled) of a corresponding memory cell (e.g., memory cell 212', 222', 232', or 242'). Each of the charge storage structures FG may form Fig.14A and Fig. 14B The memory cells shown are memory elements of corresponding memories. Fig.14A and Fig. 14B The memory cells 220', 221', 212', 222' and 232' in the embodiment may respectively represent Figure 2 Memory cells 220, 221, 212, 222 and 232.

[0108] Fig.14A and Fig. 14B The conductive lines 1441R-1444R in the memory device 1100 may form part of an access line (e.g., a read word line) of the memory device 1100. The conductive lines 1441R-1444R may include multiple pairs of conductive lines that may be electrically coupled together (e.g., shorted to each other) via conductive connections. For example, the process of forming the memory device 1100 may include forming a conductive connection (not shown) that may include a conductive material (e.g., a metal) to electrically couple the conductive lines (a pair of conductive lines) 1442R' and 1442R" to each other. Similarly, the process of forming the memory device 1100 may include forming a conductive connection (not shown) that may include a conductive material (e.g., a metal) to electrically couple the conductive lines 1441R' and 1441R" ( Fig. 14B ) are electrically coupled to each other; forming a conductive connection (not shown) to connect the conductive lines 1443R' and 1443R" ( Fig. 14B ) are electrically coupled to each other; and a conductive connection (not shown) is formed to connect the conductive lines 1444R' and 1444R" ( Fig. 14B) are electrically coupled to each other.

[0109] like Fig.14A and Fig. 14B As shown, each pair of conductive lines among the conductive lines 1441R-1444R may be located on opposite sides (relative to the Y direction) of the channel region Ch1 of the corresponding memory cell. Each pair of conductive lines among the conductive lines 1441R-1444R may form a dual gate (e.g., a read word line) and may be located (e.g., may be formed) under a corresponding charge storage structure FG of the corresponding memory cell. For example, the conductive lines 1441R and 1441R" may form a dual gate (e.g., a read word line) located under the charge storage structure FG of the memory cell 212'.

[0110] Some of the conductive lines 1441R-1444R may form part of an access line, which may represent Figure 2 For example, conductive lines 1441R and 1441R″ may be electrically coupled together (eg, by a pair of lines that may represent Figure 2 The conductive lines 1442R′ and 1442R″ may be electrically coupled together (eg, by a conductive connection (not shown) that may represent the access line 241R). Figure 2 The conductive lines 1443R′ and 1443R″ may be electrically coupled together (eg, by a conductive connection (not shown) that may represent the access line 242R). Figure 2 The conductive connection (not shown) of access line 243R is coupled together).

[0111] Fig.15A and Fig. 15B It is shown that when forming the dielectric material 1511 ( Fig.15A )、Dielectric material 1512( Fig. 15B ) and material (or materials) 1520. Forming dielectric material 1511 may include removing dielectric material 1312 ( Fig.14A ) to expose the charge storage structure FG (eg, to expose the top surface thereof), and then a dielectric material 1511 (eg, a dielectric material 1512) may be formed in the space portion where the dielectric material 1312 has been removed. Fig.15A 1502, 1503, and 1504). Dielectric material 1512 may be formed by depositing an initial dielectric material and moving (e.g., by etching) a portion of the initial dielectric material at trenches 1501, 1502, 1503, and 1504. The remaining portion of the initial dielectric material (which is outside trenches 1501, 1502, 1503, and 1504) forms dielectric material 1512.

[0112] Material 1520 may be formed (eg, deposited) by depositing one or more materials (examples of material 1520 are described below) in trenches 1501, 1502, 1503, and 1504. Fig.15A and Fig. 15B As shown, material 1520 may be formed (eg, deposited) directly over each charge storage structure FG such that material 1520 may be electrically coupled to (eg, directly coupled to) each charge storage structure FG.

[0113] The material 1520 may be subsequently processed to form a channel region (e.g., a write channel region) of a transistor (e.g., transistor T2) of a corresponding memory cell among the memory cells (e.g., memory cells 212', 222', 232', and 242') of the memory device 1100. For example, the material 1520 may be subsequently processed to form a channel region (e.g., a write channel region) of a transistor (e.g., transistor T2) of a corresponding memory cell among the memory cells (e.g., memory cells 212', 222', 232', and 242') of the memory device 1100. Figure 2 A channel region Ch2 of a transistor T2 of a corresponding memory cell among the memory cells of the memory device 1100 .

[0114] Fig.15A The material 1520 may include a semiconductor material. The semiconductor material may include an oxide material. Examples of oxide materials include semiconductive oxide materials, transparent conductive oxide materials, and other oxide materials.

[0115] As an example, the material 1520 may include at least one of the following: zinc tin oxide (ZTO), indium zinc oxide (IZO), zinc oxide (ZnO x ), Indium Gallium Zinc Oxide (IGZO), Indium Gallium Silicon Oxide (IGSO), Indium Oxide (InO x 、In 2 O 3 ), tin oxide (SnO 2 )、TiOx、ZnOx x O y N z ), magnesium zinc oxide (Mg x Zn y O z ), indium zinc oxide (In x Zn y O z ), Indium Gallium Zinc Oxide (In x Ga y Zn z O a ), zirconium indium zinc oxide (Zr x In y Zn z O a ), Hafnium Indium Zinc Oxide (Hf x In y Znz O a ), tin indium zinc oxide (Sn x In y Zn z O a ), aluminum oxide, tin, indium, zinc (Al x Sn y In z Zn a O d ), Silicon Indium Zinc Oxide (Si x In y Zn z O a ), zinc tin oxide (Zn x Sn y O z ), aluminum zinc tin oxide (Al x Zn y Sn z O a ), gallium zinc tin oxide (Ga x Zn y Sn z O a )、Zirconium oxide zinc tin (Zr x Zn y Sn z O a ), indium gallium silicon oxide (InGaSiO) and gallium phosphide (GaP).

[0116] The materials listed above are examples of material 1520. However, other materials than those listed above (eg, materials with relatively higher band gaps) may also be used.

[0117] The use of the materials listed above in the memory device 1100 provides improvements and benefits to the memory device 1100 over some other materials. For example, during a read operation to read information from a selected memory cell (e.g., memory cell 212', 222', 232', or 242') of the memory device 1100, charge from the charge storage structure FG of the selected memory cell may leak from the selected memory cell. The use of the materials listed above for the channel region of the transistor (e.g., transistor T2) of the corresponding memory cell may reduce or prevent such leakage. This improves the accuracy of the information read from the selected memory cell and improves the retention of information stored in the memory cells of the memory devices described herein (e.g., memory device 1100).

[0118] Fig.16A and Fig. 16BMemory device 1100 is shown after forming trenches 1601, 1602, 1603, and 1604 followed by forming data lines (e.g., read data lines) 1650, 1651, 1652, and 1653, dielectric materials 1611 and 1612, and material (or materials) 1520 in trenches 1601, 1602, 1603, and 1604. Dielectric material 1611 may include silicon dioxide or other dielectric materials. Dielectric material 1612 may include silicon nitride or other dielectric materials. Each of data lines 1650, 1651, 1652, and 1653 may include metal, conductively doped polysilicon, or other conductive materials.

[0119] Forming trenches 1601, 1602, 1603, and 1604 may include removing a portion of material 1520, a portion of dielectric material 1511, and dielectric material 1235 at the locations of trenches 1601, 1602, 1603, and 1604 to expose semiconductor material 1210. Each of trenches 1601, 1602, 1603, and 1604 may have a length along the Y direction, a width along the X direction (shorter than the length), and a bottom (not labeled) disposed on a corresponding portion of semiconductor material 1210.

[0120] The dielectric material 1611, the data lines 1650, 1651, 1652, and 1653, and the dielectric material 1612 may be formed in a sequential order, which may include forming the dielectric material 1611, forming the data lines 1650, 1651, 1652, and 1653 after forming the dielectric material 1611, and then forming the dielectric material 1612. Fig.16A and 16B As shown, data lines 1650, 1651, 1652 and 1653 can be formed (e.g., deposited) directly above the semiconductor material 1210 (e.g., formed on the bottom of the corresponding grooves 1601, 1602, 1603 and 1604), so that the data lines 1650, 1651, 1652 and 1653 can be electrically coupled to (e.g., directly coupled to) the semiconductor material 1210.

[0121] Fig.17A and Fig. 17BMemory device 1100 is shown in which dielectric material (e.g., gate oxide) 1711, conductive lines (e.g., conductive regions) 1741W', 1741W", 1742W', 1742W", 1743W', 1743W", 1744W', and 1744W" (collectively 1741W-1744W), and dielectric material 1712 are formed in respective trenches 1701, 1702, 1703, 1704, and 1705, followed by formation of trenches 1701, 1702, 1703, 1704, and 1705. Dielectric material 1711 may include silicon dioxide or other dielectric materials. Dielectric material 1712 may include silicon nitride or other dielectric materials. Each of conductive lines 1741W-1744W may include metal, conductively doped polysilicon, or other conductive materials.

[0122] Forming trenches 1701, 1702, 1703, 1704, and 1705 may include removing a portion of dielectric material 1512 and a portion of material 1520 at the locations of trenches 1701, 1702, 1703, 1704, and 1705. Each of trenches 1701, 1702, 1703, 1704, and 1705 may have a length along the X direction, a width along the Y direction (shorter than the length), and a bottom (not labeled) disposed on a corresponding portion of dielectric material 1612.

[0123] Each of the conductive lines 1741W-1744W may have a length extending along the X direction, a width extending along the Z direction, and a thickness extending along the Y direction. Fig.17A As shown, each of conductive line 1741W' (which is formed in trench 1701) and conductive line 1741W" (which is formed in trench 1702) may have a length extending along the X direction, a width extending along the Z direction (e.g., less than the length), and a thickness extending along the Y direction (e.g., less than the width).

[0124] Conductive lines 1741W-1744W may form part of access lines (e.g., write word lines) of memory device 1100. Conductive lines 1741W-1744W may include multiple pairs of conductive lines that may be electrically coupled together (e.g., shorted to each other) via conductive connections. For example, the process of forming memory device 1100 may include forming conductive connection 1742' (which may include a conductive material (e.g., metal)) to electrically couple conductive lines (a pair of conductive lines) 1742W' and 1742W" to each other. Similarly, the process of forming memory device 1100 may include forming conductive connections (not shown) to electrically couple conductive lines 1741W' and 1741W" ( Fig. 17B ) are electrically coupled to each other to form a conductive connection (not shown) to connect conductive lines 1743W' and 1743W" ( Fig. 17B) are electrically coupled to each other, and a conductive connection (not shown) is formed to connect the conductive lines 1744W' and 1744W" ( Fig. 17B ) are electrically coupled to each other.

[0125] like Fig.17A and Fig. 17B As shown, each pair of conductive lines among the conductive lines 1741W-1744W may be located on opposite sides (relative to the Y direction) of the channel region Ch2 of the corresponding memory cell. Each pair of conductive lines among the conductive lines 1741W-1744W may form a double gate (e.g., a write word line) and may be located (e.g., may be formed) above a corresponding charge storage structure FG of the corresponding memory cell.

[0126] Some of the conductive lines 1741W-1744W may form part of an access line, which may represent Figure 2 For example, conductive lines 1741W′ and 1741W″ may be electrically coupled together (eg, by a pair of lines that may represent Figure 2 The conductive lines 1742W′ and 1742W″ may be electrically coupled together (eg, by a conductive connection (not shown) that may represent the access line 241W). Figure 2 The conductive lines 1743W′ and 1743W″ may be electrically coupled together (eg, by a conductive connection (not shown) that may represent the access line 242W). Figure 2 The conductive connection (not shown) of access line 243W is coupled together).

[0127] Fig.18A and Fig.18B Memory device 1100 is shown after forming data lines (e.g., write data lines) 1860, 1861, and 1862 and dielectric material 1812. Each of data lines 1860, 1861, and 1862 may include metal, conductively doped polysilicon, or other conductive materials. Dielectric material 1812 may include silicon nitride or other dielectric materials.

[0128] like Fig.18A As shown, each of the materials 1520 may form a channel region Ch2 of a transistor T2 (which is located above transistor T1) of a corresponding memory cell. Fig.18A and Fig.18B Only the transistors T1 and T2 of the memory cell 222' are marked. The transistors T1 and T2 of other memory cells (eg, memory cells 220' and 221') are not marked. The transistors T1 and T2 of the memory cell 222' may be represented by Figure 2 Transistors T1 and T2 of a memory cell 222 of a memory device 200 .

[0129] like Fig.18A and Fig.18B As shown, each of the data lines 1860, 1861, and 1862 may be electrically coupled to (e.g., directly coupled to) the channel region Ch2 of the transistor T2 of the corresponding memory cell along the X direction, and may be electrically coupled to (e.g., directly coupled to) the channel region Ch2 of the transistor T2 of the memory cell along the Y direction.

[0130] like Fig.18A As shown, portions 1851, 1852, and 1853, wherein portions 1851 and 1852 may be located on opposite sides of the charge storage structure FG of the memory cell 222', and portion 1853 may be located between portions 1851 and 1852. Portions 1851, 1852, and 1853 of the semiconductor material 1210 may respectively form a channel region (e.g., channel region Ch1), a source terminal, and a drain terminal of the transistor T1 of the memory cell 222'. Thus, the source terminal, the channel region Ch1, and the drain terminal of the transistor T1 of the memory cell 222' may be formed by a single structure (e.g., a single piece) of the same material (e.g., the same portion of the material 1210). The transistor T1 of the other memory cells of the memory device 1100 has a structure similar to that of the transistor T1 of the memory cell 222'. For simplicity, such similar structures are not described herein. Fig.18A , current I may represent current flowing through a path (eg, a read path) including data lines 1652 and 1653 during a read operation of memory device 1100. Such a read operation may include reading information from memory cell 222' (eg, a selected memory cell).

[0131] like Fig.18A As shown, the material 1520 directly coupled to the data line 1862 can form the channel region Ch2 of the transistor T2 of the memory cell 222', the source terminal of the transistor T2 of the memory cell 222' (which is directly coupled to the data line 1862), and the drain terminal of the transistor T2 (which is directly coupled to the charge storage structure FG of the memory cell 222'). Therefore, the source terminal, the channel region, and the drain terminal of the transistor T2 of the memory cell 222' can be formed by a single structure (e.g., a single piece) of the same material (e.g., the material 1520, which is directly coupled to the data line 1862). The transistors T2 of the other memory cells of the memory device 1100 have a similar structure to the transistor T2 of the memory cell 222'. For simplicity, such similar structures are not described herein.

[0132] refer to Figures 11 to 18B The description of forming memory device 1100 may include other processes for forming a complete memory device. Such processes are omitted in the above description to avoid obscuring the subject matter described herein.

[0133] Fig.19A and Fig.19B 1 shows a side view of the structure of a memory device 1900 according to some embodiments described herein, including a ground connection 1999 coupled to each memory cell of the memory device 1900. The memory device 1900 may have a configuration similar to Fig.11 1 is a top view of a top view of a memory device 1100 shown in FIG. 1 and may include a memory device similar to memory device 1100 ( Figures 11 to 18B ) of an element. For example, Fig.19A A side view of the memory device 1900 in the XZ direction is shown, similar to Fig.18A 1100 is a side view of a memory device 1100. Fig.19B A side view of the memory device 1900 in the YZ direction is shown, similar to Fig.18B 1100 is a side view of a memory device 1100.

[0134] like Fig.19A and Fig.19B As shown, memory device 1900 may include substrate 1998 and dielectric material 1990, which may be similar to memory device 1100 ( Figures 11 to 18B ) substrates 1198 and 1190. The memory device 1900 may include a memory cell, such as Fig.19A The memory cells 220", 221" and 222 and Fig.19B Memory cells 212", 222", 232" and 242" (memory cell 222" can be seen in Fig.19A and Fig.19B Memory units 220", 221", 222", 212", 232", and 242" may represent Fig. 9 Memory cells 220 , 221 , 222 , 212 , 232 , and 242 of the memory device 900 .

[0135] like Fig.19A and Fig.19B As shown, each memory cell in the memory device 1900 may include a 2T memory cell having transistors T1 and T2 formed in the Z direction (e.g., arranged vertically). The transistor T1 of each memory cell in the memory device 1900 may include a charge storage structure FG. The transistors T1 and T2 of each memory cell in the memory device 1900 may include channel regions Ch1 and Ch2, respectively. In the same memory cell, the channel region Ch2 may be electrically coupled to the charge storage structure FG of the memory cell. The materials of the channel regions Ch1 and Ch2 of the memory device 1900 may be the same as those described above with reference to Figures 2 to 18B The materials of the channel regions Ch1 and Ch2 of the described memory device are similar or identical.

[0136] like Fig.19A and Fig.19B As shown, a portion of the channel region Ch1 (which may also be the source terminal of transistor T1) may be coupled to a ground connection 1999. The ground connection 1999 may represent Fig. 9 The ground connection 999 of the memory device 900 is provided.

[0137] Memory device 1900 may include access lines (e.g., read word lines) formed by conductive lines 1941R′, 1941R″, 1942R′, 1942R″, 1943R′, 1943R″, 1944R′, and 1944R″, wherein each pair of these conductive lines (e.g., a pair of conductive lines 1941R′ and 1941R″) may be electrically coupled to each other. Memory device 1900 may include access lines (e.g., write word lines) formed by conductive lines 1941W′, 1941W″, 1942W′, 1942W″, 1943W′, 1943W″, 1944W′, and 1944W″, wherein each pair of these conductive lines (e.g., a pair of conductive lines 1941W′ and 1941W″) may be electrically coupled to each other.

[0138] The memory device 1900 may include data lines (e.g., read data lines) 1950, 1951, and 1952, each of which may be electrically coupled to a channel region Ch1 of a transistor T1 of a corresponding memory cell. The memory device 1900 may include data lines (e.g., write data lines) 1960, 1961, and 1962, each of which may be electrically coupled to a channel region Ch1 of a transistor T2 of a corresponding memory cell of the memory device 1900. The operation (e.g., reading and writing) of the memory device 1900 may be similar to the memory device 900 ( Fig. 9 ) and the memory device 1000 ( Fig.10 ) operations.

[0139] Fig. 20A , Fig. 20B and Fig. 20C Different views of the structure of a memory device 2000 including multiple stacks of memory cells according to some embodiments described herein are shown. Fig. 20A An exploded view (eg, in the Z direction) of memory device 2000 is shown. Fig. 20B Side views (eg, cross-sectional views) in the X-direction and the Z-direction of the memory device 200 are shown. Fig. 20C Side views (eg, cross-sectional views) in the Y direction and the Z direction of the memory device 2000 are shown.

[0140] like Fig. 20A As shown in FIG. 1 , the memory device 2000 may include a stack (a stack of memory cells) 20050 , 2005 1 , 2005 2 and 2005 3 , the stacks are shown separated from each other in the exploded view to help facilitate easy viewing of the stack structure of the memory device 2000. In fact, the stack 2005 0 , 2005 1 , 2005 2 and 2005 3 The stacks may be attached to each other in an arrangement where one stack may be formed (eg, stacked) on top of another stack on a substrate (eg, a semiconductor (eg, silicon) substrate) 2099. Fig. 20A As shown in the stack 2005 0 , 2005 1 , 2005 2 and 2005 3 It can be formed in the Z direction perpendicular to the substrate 2099 (for example, formed vertically in the Z direction relative to the substrate 2099).

[0141] like Fig. 20A As shown in the stack 2005 0 , 2005 1 , 2005 2 and 2005 3 Each of the stacks 2005 may have memory cells arranged in the X direction and the Y direction (eg, arranged in rows in the X direction and arranged in columns in the Y direction). 0 May include memory unit 2010 0 , 2011 0 , 2012 0 and 2013 0 (eg, arranged in rows), memory cells 2020 0 、2021 0 、2022 0 and 2023 0 (eg, arranged in rows) and memory cells 2030 0 、2031 0 , 2032 0 and 2033 0 (eg, arranged in rows).

[0142] Stack 2005 1 May include memory unit 2010 1 , 2011 1 , 2012 1 and 2013 1 (eg, arranged in rows), memory cells 2020 1 、2021 1、2022 1 and 2023 1 (eg, arranged in rows) and memory cells 2030 1 、2031 1 , 2032 1 and 2033 1 (eg, arranged in rows).

[0143] Stack 2005 2 May include memory unit 2010 2 , 2011 2 , 2012 2 and 2013 2 (eg, arranged in rows), memory cells 2020 2 、2021 2 、2022 2 and 2023 2 (eg, arranged in rows) and memory cells 2030 2 、2031 2 , 2032 2 and 2033 2 (eg, arranged in rows).

[0144] Stack 2005 3 May include memory unit 2010 3 , 2011 3 , 2012 3 and 2013 3 (eg, arranged in rows), memory cells 2020 3 、2021 3 、2022 3 and 2023 3 (eg, arranged in rows) and memory cells 2030 3 、2031 3 , 2032 3 and 2033 3 (eg, arranged in rows).

[0145] like Fig. 20A As shown in the stack 2005 0 , 2005 1 , 2005 2 and 2005 3 The stack 2005 may be positioned (eg, formed vertically in the Z direction) on the levels (eg, portions) 2050, 2051, 2052, and 2053 of the memory device 2000, respectively. 0 , 2005 1 , 2005 2 and 2005 3The arrangement forms a 3-dimensional (3D) structure of the memory cells of the memory device 2000, wherein different levels of the memory cells of the memory device 2000 may be positioned (e.g., formed) in different levels (e.g., different vertical portions) 2050, 2051, 2052, and 2053 of the memory device 2000.

[0146] The stack can be formed one stack at a time 2005 0 , 2005 1 , 2005 2 and 2005 3 For example, you can group 2005 0 , 2005 1 , 2005 2 and 2005 3 The order of forming stacks 2005 0 , 2005 1 , 2005 2 and 2005 3 (For example, first form stack 2005 1 And finally formed a stack 2005 3 In this example, another stack (eg, stack 2005) may be used. 0 ) or after formation of a memory cell in another stack (eg, stack 2005 2 ) is formed before forming a stack (eg, stack 2005 1 Alternatively, the stack 2005 may be formed in parallel (eg, simultaneously) 0 , 2005 1 , 2005 2 and 2005 3 , so that stacks can be formed in parallel 2005 0 , 2005 1 , 2005 2 and 2005 3 For example, memory cells in levels 2050, 2051, 2052, and 2053 of memory device 2000 may be formed in parallel.

[0147] Stack 2005 0 , 2005 1 , 2005 2 and 2005 3 The structure of each memory cell may include the above reference Figures 1 to 19B The structure of the memory cell described. For example, stack 2005 0 , 2005 1 , 2005 2 and 20053 The structure of the memory cell of may include the structure of the memory cell of the memory devices 1100 and 1900 .

[0148] The memory device 2000 may include data lines (eg, bit lines) and access lines (eg, word lines) to access the stack 2005. 0 , 2005 1 , 2005 2 and 2005 3 For simplicity, Fig. 20A The data lines and access lines of the memory cells are omitted. However, the data lines and access lines of the memory device 2000 may be similar to those described above with reference to Figures 1 to 19B Data lines and access lines of a memory device are described.

[0149] Fig. 20A As an example, a system comprising four stacks (e.g., 2005 0 , 2005 1 , 2005 2 and 2005 3 ) of the memory device 2000. However, the number of stacks may be different from four. Fig. 20A A stack 2005 is shown as an example of a level (eg, layer) including memory cells. 0 , 2005 1 , 2005 2 and 2005 3 However, at least one of the stacks (e.g., stack 2005 0 , 2005 1 , 2005 2 and 2005 3 One or more of) may have two (or more) levels of memory cells. Fig. 20A An example is shown, in which stack 2005 0 , 2005 1 , 2005 2 and 2005 3 Each of includes four memory cells in the X direction (eg, in a row) and three memory cells in the Y direction (eg, in a column). However, the number of memory cells in a row, in a column, or both may vary.

[0150] The description of apparatus (e.g., memory devices 100, 200, 600, 700, 800, 900, 1000, 1100, and 1900) and methods (e.g., the operation of memory devices 100, 200, 600, 700, 800, 900, and 1000 and the method of forming memory device 1100) is intended to provide a general understanding of the structure of various embodiments and is not intended to provide a complete description of all elements and features of apparatus that can utilize the structure described herein. An apparatus herein refers to, for example, a device (e.g., any one of memory devices 100, 200, 600, 700, 800, 900, 1000, 1100, and 1900) or a system (e.g., an electronic article that can include any one of memory devices 100, 200, 600, 700, 800, 900, 1000, 1100, and 1900).

[0151] References Figures 1 to 19B Any of the described components may be implemented in a number of ways, including via software simulation. Thus, the apparatus (e.g., memory devices 100, 200, 600, 700, 800, 900, 1000, 1100, and 1900) or portions of each of these memory devices described above may be characterized herein as one or more "modules." Such modules may include hardware circuits, single and / or multi-processor circuits, memory circuits, software program modules and objects, and / or firmware, and combinations thereof, as required and / or appropriate for the particular implementation of the various embodiments. For example, these modules may be included in a system operation simulation package, such as a software electrical signal simulation package, a power usage and range simulation package, a capacitance-inductance simulation package, a power / heat dissipation simulation package, a signal transmission-reception simulation package, and / or a combination of software and hardware to operate or simulate the operation of the various potential embodiments.

[0152] The memory devices described herein (e.g., memory devices 100, 200, 600, 700, 800, 900, 1000, 1100, and 1900) may be included in devices (e.g., electronic circuits) such as high-speed computers, communication and signal processing circuits, single or multi-processor modules, single or multiple embedded processors, multi-core processors, message information switches, and application-specific modules including multi-layer, multi-chip modules. These devices may further be included as subcomponents within a variety of other devices (e.g., electronic systems) such as televisions, cellular phones, personal computers (e.g., laptop computers, desktop computers, handheld computers, tablet computers, etc.), workstations, radios, video players, audio players (e.g., MP3 (Motion Picture Experts Group, Audio Layer 3) players), vehicles, medical devices (e.g., heart monitors, blood pressure monitors, etc.), set-top boxes, etc.

[0153] References Figures 1 to 19B The described embodiments include devices and methods of forming the devices. One of the devices includes a memory cell, first, second, and third data lines, and first and second access lines. Each of the first, second, and third data lines includes a length extending in a first direction, and each of the first and second access lines includes a length extending in a second direction. The memory cell includes: a first transistor including a charge storage structure and a first channel region electrically separated from the charge storage structure; and a second transistor including a second channel region electrically coupled to the charge storage structure. The first data line is electrically coupled to the first channel region. The second data line is electrically coupled to the first channel region. The third data line is electrically coupled to the second channel region, the second channel region being between the charge storage structure and the third data line. The first access line is located on a first level of the device and is separated from the first channel by a first dielectric. The second access line is located on a second level of the device and is separated from the second channel by a second dielectric. The charge storage structure is located on a level of the device between the first and second levels. Other embodiments including additional devices and methods are described.

[0154] In the detailed description and claims, the terms "on," one "on" another, used with respect to two or more elements (e.g., materials), mean at least some contact between the elements (e.g., between the materials). The term "over" means that the elements (e.g., materials) are in close proximity, but may have one or more additional intervening elements (e.g., materials) such that contact is possible but not required. Neither "on" nor "over" implies any directionality as used herein unless so stated.

[0155] In the detailed description and claims, a list of items joined by the term "at least one of" may mean any combination of the listed items. For example, if items A and B are listed, the phrase "at least one of A and B" means only A; only B; or A and B. In another example, if items A, B, and C are listed, the phrase "at least one of A, B, and C" means only A; only B; only C; A and B (excluding C); A and C (excluding B); B and C (excluding A); or all of A, B, and C. Item A may contain a single element or multiple elements. Item B may contain a single element or multiple elements. Item C may contain a single element or multiple elements.

[0156] In the detailed description and claims, a list of items joined by the term "one of" may mean only one of the listed items. For example, if items A and B are listed, the phrase "one of A and B" means only A (not including B) or only B (not including A). In another example, if items A, B, and C are listed, the phrase "one of A, B, and C" means only A; only B; or only C. Item A may contain a single element or multiple elements. Item B may contain a single element or multiple elements. Item C may contain a single element or multiple elements.

[0157] The above description and drawings illustrate some embodiments of the subject matter of the present invention to enable those skilled in the art to practice the embodiments of the subject matter of the present invention. Other embodiments may incorporate structural, logical, electrical, process and other changes. Examples represent possible variations only. Portions and features of some embodiments may be included in those portions and features of other embodiments, or replace those portions and features. After reading and understanding the above description, those skilled in the art will understand many other embodiments.

Claims

1. A memory device, comprising: A memory unit comprising: a first transistor comprising a charge storage structure and a first channel region electrically separated from the charge storage structure; as well as a second transistor including a second channel region electrically coupled to the charge storage structure; a first data line electrically coupled to the first channel region; a second data line electrically coupled to the first channel region; a third data line electrically coupled to the second channel region, the second channel region being between the charge storage structure and the third data line, each of the first, second and third data lines comprising a length extending in a first direction; a first access line located on a first level of the memory device and separated from the first channel by a first dielectric; A second access line is located on a second level of the memory device and is separated from the second channel by a second dielectric, the charge storage structure is located on a level of the memory device between the first and second levels, and each of the first and second access lines includes a length extending in a second direction.

2. The memory device of claim 1, further comprising An additional memory unit comprising: a first additional transistor including an additional charge storage structure and a first additional channel region electrically separated from the additional charge storage structure; and a second additional transistor comprising a second additional channel region electrically coupled to the additional charge storage structure; a fourth data line electrically coupled to the first additional channel region; a fifth data line electrically coupled to the second additional channel region, the second additional channel region being between the additional charge storage structure and the fifth data line, the fourth and fifth data lines comprising a length extending in the first direction, wherein The first access line includes a portion spanning a portion of the first channel region and a portion of the first additional channel region; and The second access line includes a portion spanning a portion of the second channel region and a portion of the second additional channel region.

3. The memory device of claim 1, further comprising a substrate, wherein the memory cell is located above the substrate, and a distance between the first access line and the substrate is smaller than a distance between the charge storage structure and the substrate. The memory device of claim 3 , wherein the first channel region is electrically coupled to the first additional channel region.

5. The memory device of claim 1 , wherein the first channel region comprises: a first portion located on a first side of the charge storage structure; a second portion located on a second side of the charge storage structure; and The third part is located between the charge storage structure and the substrate. The memory device of claim 1 , wherein the first and second channel regions comprise different materials.

7. The memory device of claim 1, wherein the charge storage structure comprises a semiconductor material.

8. The memory device of claim 1, wherein the charge storage structure comprises a metal.

9. The memory device of claim 1, wherein the second channel region comprises at least one of: zinc tin oxide (ZTO), indium zinc oxide (IZO), zinc oxide (ZnO x ), Indium Gallium Zinc Oxide (IGZO), Indium Gallium Silicon Oxide (IGSO), Indium Oxide (InO x , In2O3), tin oxide (SnO2), titanium oxide (TiO x ), zinc oxynitride (Zn x O y N z ), magnesium zinc oxide (Mg x Zn y O z ), Indium Zinc Oxide (In x Zn y O z ), Indium Gallium Zinc Oxide (In x Ga y Zn z O a ), zirconium indium zinc oxide (Zr x In y Zn z O a ), Hafnium Indium Zinc Oxide (Hf x In y Zn z O a ), tin indium zinc oxide (Sn x In y Zn z O a ), aluminum oxide, tin, indium, zinc (Al x Sn y In z Zn a O d ), Silicon Indium Zinc Oxide (Si x In y Zn z O a ), zinc tin oxide (Zn x Sn y O z ), aluminum zinc tin oxide (Al x Zn y Sn z O a ), gallium zinc tin oxide (Ga x Zn y Sn z O a )、Zirconium oxide zinc tin (Zr x Zn y Sn z O a ), indium gallium silicon oxide (InGaSiO) and gallium phosphide (GaP).

10. The memory device of claim 1, further comprising a connection electrically coupling the first access line to the second access line.

11. The memory device of claim 8, wherein the first channel region is to conduct current between the first and second data lines during operations performed on the memory cell.

12. The memory device of claim 2, wherein: the first channel region to conduct current between the first and second data lines during operations performed on the first memory cell; and The first additional channel region will conduct current between the second and third data lines during operations performed on the second memory cell.

13. The memory device of claim 1, wherein the first and second transistors have different threshold voltages.

14. A memory device comprising: A memory unit comprising: a first transistor comprising a charge storage structure and a first channel region electrically separated from the charge storage structure; as well as a second transistor including a second channel region electrically coupled to the charge storage structure; a ground connection coupled to a first portion of the first channel region; a first data line electrically coupled to a second portion of the first channel region; a second data line electrically coupled to the second channel region, the second channel region being between the charge storage structure and the second data line, each of the first and second data lines comprising a length extending in a first direction; a first access line located on a first level of the memory device and separated from the first channel region by a first dielectric; A second access line is located on a second level of the memory device and is separated from the second channel region by a second dielectric, the first data line is located on a third level of the memory device, the first level is between the second and third levels, and each of the first and second access lines includes a length extending in a second direction.

15. The memory device of claim 14, further comprising An additional memory unit comprising: a first additional transistor including an additional charge storage structure and a first additional channel region coupled to the ground connection and electrically separated from the additional charge storage structure; and a second additional transistor comprising a second additional channel region electrically coupled to the additional charge storage structure; a third data line electrically coupled to the first additional channel region; a fourth data line electrically coupled to the second additional channel region, the second additional channel region being between the additional charge storage structure and the fourth data line, the third and fourth data lines comprising a length extending in the first direction, wherein The first access line includes a portion spanning a portion of the first channel region and a portion of the first additional channel region; and The second access line includes a portion spanning a portion of the second channel region and a portion of the second additional channel region.

16. The memory device of claim 14, further comprising a trench including a bottom, wherein the charge storage structure is formed in a first location of the trench, the second channel region is formed in a second location of the trench, and the charge storage structure is between the bottom of the trench and the second channel region.

17. The memory device of claim 16, wherein the charge storage structure and the second channel region comprise different materials.

18. A method of forming a memory device, comprising: forming a first transistor of a memory cell, including forming a charge storage structure and a first channel region electrically separated from the charge storage structure; forming a second transistor of the memory cell, including forming a second channel region electrically coupled to the charge storage structure; forming a first data line having a length extending in a first direction and electrically coupled to the first channel region; forming a second data line having a length extending in the first direction and electrically coupled to the first channel region; forming a third data line having a length extending in the first direction and electrically coupled to the second channel region such that the second channel region is between the charge storage structure and the third data line; a first access line formed on a first level of the memory device and separated from the first channel region by a first dielectric; as well as A second access line is formed on a second level of the memory device and separated from the second channel region by a second dielectric, so that the charge storage structure is on a level between the first and second levels of the memory device, and each of the first and second access lines is formed to have a length extending in a second direction.

19. The method of claim 18, wherein forming the first access line comprises: forming a first conductive line on a first side of a portion of the first channel region; and A second conductive line is formed on a second side of the portion of the first channel region opposite the first side.

20. The method of claim 19, wherein forming the first and second conductive lines comprises: forming a first trench in a semiconductor material; forming a second trench in the semiconductor material; forming a first dielectric material in the first trench; forming a second dielectric material in the second trench; forming a first conductive material in the first trench to form the first conductive line from the conductive material in the first trench, such that the first conductive line is electrically separated from the semiconductor material by the first dielectric material; as well as A second conductive material is formed in the second trench to form the second conductive line from the conductive material in the second trench, such that the second conductive line is electrically separated from the semiconductor material by the second dielectric material.

21. The method of claim 18, wherein forming the charge storage structure comprises: forming a trench in a semiconductor material; forming a dielectric material in the trench; and A material is formed in the trench to form the charge storage structure from the material such that the material is electrically separated from the semiconductor material by the dielectric material.

22. The method of claim 18, wherein forming the second access line comprises: forming a first conductive line on a first side of a portion of the second channel region; and A second conductive line is formed on a second side of the portion of the second channel region opposite the first side.

23. The method of claim 22, wherein forming the first and second conductive lines comprises: forming a first trench in the dielectric material; forming a second trench in the dielectric material; forming a first additional dielectric material in the first trench; forming a second additional dielectric material in the second trench; forming a first conductive material in the first trench to form the first conductive line from the conductive material in the first trench, such that the first conductive line is electrically separated from the dielectric material by the first additional dielectric material; and A second conductive material is formed in the second trench to form the second conductive line from the conductive material in the second trench such that the second conductive line is electrically separated from the dielectric material by the second additional dielectric material.

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