Display device

Abstract

The display device includes: a display panel including gate lines extending in a first direction, sub-gate lines extending in a second direction intersecting the first direction and electrically connected to the gate lines, first data lines, second data lines, first pixels, and second pixels; and a driving circuit providing a gate signal and a data signal, wherein a second capacitance between a second drain electrode and a second gate electrode of the second pixel is larger than a first capacitance between a first drain electrode and a first gate electrode of the first pixel.

Description

Technical Field

[0001] The present invention relates to a display device. Background Art

[0002] A liquid crystal display device is formed of two display substrates on which pixel electrodes, common electrodes, etc. are formed, and a liquid crystal layer interposed between the two display substrates. When a voltage is applied to the pixel electrode and the common electrode, an electric field is generated between the pixel electrode and the common electrode. Thereby, the orientations of a plurality of liquid crystal molecules in the liquid crystal layer can be determined, and the polarization of incident light can be controlled to display an image.

[0003] The display panel of the liquid crystal display device includes gate lines, data lines, and pixels. Each pixel may include a switching transistor, a liquid crystal capacitor, and a storage capacitor, respectively. After each pixel is applied with a gate signal through the gate line, a data voltage corresponding to an image can be provided to the data line, thereby an image can be displayed.

[0004] Recently, efforts have been made in various aspects to minimize the border area around the display panel. On the other hand, as the size of the display panel increases, a problem of uneven display quality of an image has been raised. Summary of the Invention

[0005] An object of the present invention is to provide a display device capable of minimizing the border area around a display panel while improving display quality.

[0006] According to one feature of the present invention for achieving the above object, a display device includes: a display panel including gate lines extending in a first direction, sub-gate lines extending in a second direction intersecting the first direction and electrically connected to the gate lines, first data lines and second data lines extending in the first direction, first pixels connected to the sub-gate lines and the first data lines, and second pixels connected to the sub-gate lines and the second data lines; and a driving circuit configured to provide a gate signal to the gate lines and provide data signals to the first data lines and the second data lines. The first pixel includes a first source electrode connected to the first data line, a first drain electrode connected to a common electrode, and a first gate electrode connected to the sub-gate line. The second pixel includes a second source electrode connected to the second data line, a second drain electrode connected to the common electrode, and a second gate electrode connected to the sub-gate line. A second capacitance between the second drain electrode and the second gate electrode of the second pixel is larger than a first capacitance between the first drain electrode and the first gate electrode of the first pixel.

[0007] In an exemplary embodiment, it may be that an overlapping area between the second drain electrode and the second gate electrode of the second pixel is greater than an overlapping area between the first drain electrode and the first gate electrode of the first pixel.

[0008] In an exemplary embodiment, it may be that the second drain electrode of the second pixel includes a main drain electrode disposed apart from the second source electrode and a sub-drain electrode protruding from the main drain electrode, the second gate electrode of the second pixel includes a main gate electrode overlapping with the second source electrode and the main drain electrode and a sub-gate electrode protruding from the main gate electrode, and a part of the sub-drain electrode overlaps with a part of the sub-gate electrode in a plane.

[0009] In an exemplary embodiment, it may be that the sub-drain electrode does not overlap with the main gate electrode.

[0010] In an exemplary embodiment, it may be that the sub-gate electrode does not overlap with the main drain electrode.

[0011] In an exemplary embodiment, it may be that the number of gate lines is equal to the number of data lines.

[0012] In an exemplary embodiment, it may be that the first pixel and the second pixel are disposed adjacent to each other in the second direction, the first pixel is disposed adjacent to the gate line, the second pixel is away from the gate line, and the first pixel is provided between the second pixel and the gate line.

[0013] In an exemplary embodiment, it may be that the number of data lines is more than the number of gate lines.

[0014] In an exemplary embodiment, it may be that the driving circuit includes: a flexible circuit board connected to one side of the display panel; and a driving chip mounted on the flexible circuit board to provide the gate signal and the data signal.

[0015] Other features of the present invention relate to a display device including: a display panel including a plurality of gate lines extending in a first direction, a plurality of sub-gate lines extending in a second direction intersecting the first direction and electrically connected to the plurality of gate lines respectively, a plurality of data lines extending in the first direction, and a plurality of first pixels and a plurality of second pixels respectively connected to the plurality of sub-gate lines and the plurality of data lines; and a driving circuit configured to provide a plurality of gate signals to the plurality of gate lines respectively and a plurality of data signals to the plurality of data lines respectively. The plurality of first pixels are connected to the i-th sub-gate line among the plurality of sub-gate lines, and the plurality of first pixels are arranged adjacent to the i-th to (i + k)-th (i and k are natural numbers respectively) gate lines among the plurality of gate lines. The plurality of first pixels respectively include a first source electrode connected to a corresponding data line among the plurality of data lines, a first drain electrode connected to a common electrode, and a first gate electrode connected to the sub-gate line. The plurality of second pixels respectively include a second source electrode connected to a corresponding data line among the plurality of data lines, a second drain electrode connected to the common electrode, and a second gate electrode connected to the sub-gate line. A second capacitance between the second drain electrode and the second gate electrode of each of the plurality of second pixels is larger than a first capacitance between the first drain electrode and the first gate electrode of each of the plurality of first pixels.

[0016] In an exemplary embodiment, it may be that an overlapping area between the second drain electrode and the second gate electrode of each of the plurality of second pixels is larger than an overlapping area between the first drain electrode and the first gate electrode of the first pixel.

[0017] In an exemplary embodiment, it may be that the second drain electrode of each of the plurality of second pixels includes a main drain electrode configured away from the second source electrode and a sub-drain electrode protruding from the main drain electrode. The second gate electrode of the second pixel includes a main gate electrode overlapping with the second source electrode and the main drain electrode and a sub-gate electrode protruding from the main gate electrode. A part of the sub-drain electrode overlaps with a part of the sub-gate electrode in a plane.

[0018] In an exemplary embodiment, it may be that the sub-drain electrode does not overlap with the main gate electrode.

[0019] In an exemplary embodiment, it may be that the sub-gate electrode does not overlap with the main drain electrode.

[0020] In an exemplary embodiment, it may be that the plurality of gate signals provided to the plurality of gate lines are sequentially activated to an effective level every other horizontal period and maintained at the effective level within k + 1 horizontal periods.

[0021] In an exemplary embodiment, it may be that an odd number of data lines among the plurality of data lines are arranged on the left side of the plurality of first pixels and the plurality of second pixels, an even number of data lines among the plurality of data lines are arranged on the right side of the plurality of first pixels and the plurality of second pixels, and the plurality of first pixels and the plurality of second pixels are respectively connected to any one of the odd number of data lines and the even number of data lines.

[0022] In an exemplary embodiment, it may be that the odd number of data lines among the plurality of data lines alternately transmit a positive polarity data signal and a negative polarity data signal in each frame, and the even number of data lines among the plurality of data lines alternately transmit the negative polarity data signal and the positive polarity data signal in each frame.

[0023] In an exemplary embodiment, it may be that each of the first pixels and each of the second pixels arranged in the same column in the first direction are alternately connected to the odd number of data lines arranged on the left side and the even number of data lines arranged on the right side.

[0024] In an exemplary embodiment, it may be that the driving circuit includes: a flexible circuit board connected to one side of the display panel; and a driving chip mounted on the flexible circuit board to provide the plurality of gate signals and the plurality of data signals.

[0025] In an exemplary embodiment, it may be that the display panel further includes a first substrate, a second substrate facing the first substrate, and a liquid crystal layer disposed between the first substrate and the second substrate, and the plurality of gate lines, the plurality of sub-gate lines, the plurality of data lines, the plurality of first pixels, and the plurality of second pixels are disposed on the first substrate.

[0026] (Advantages of the Invention)

[0027] A display device having the above-described configuration can dispose a driving circuit for driving gate lines and data lines on one side of the display panel, thereby minimizing the bezel area of the display device. In addition, the display device has a compensation pattern for compensating for a charging rate deviation between pixels in a specific pixel. Therefore, it is possible to prevent a decrease in display quality caused by a charging rate deviation between pixels. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a plan view of a display device according to an embodiment of the present invention.

[0029] Figure 2 is an equivalent circuit diagram of a pixel according to an embodiment of the present invention.

[0030] Figure 3 is a cross-sectional view of a pixel according to an embodiment of the present invention.

[0031] Figure 4 It is a diagram showing the pixel arrangement of a display panel related to an exemplary embodiment of the present invention.

[0032] Figure 5 Exemplarily shows Figure 4 each gate signal provided to each of the gate lines shown.

[0033] Figure 6 Exemplarily shows the first gate signal provided to the first gate line, the second gate signal provided to the second gate line, and Figure 4 the pixel voltage of the pixel shown.

[0034] Figure 7 Exemplarily shows the first gate signal provided to the first gate line, the sixth gate signal provided to the sixth gate line, and Figure 4 the pixel voltage of the pixel shown.

[0035] Figure 8 It is a diagram showing the pixel arrangement of a display panel related to an exemplary embodiment of the present invention.

[0036] Figure 9 It is a plan view of a first pixel and a second pixel related to an exemplary embodiment of the present invention.

[0037] Figure 10 It is a plan view of a first pixel and a second pixel related to an exemplary embodiment of the present invention.

[0038] Figure 11 It is a diagram showing the pixel arrangement of a display panel related to an exemplary embodiment of the present invention.

[0039] Figure 12 It is a diagram showing the pixel arrangement of a display panel related to an exemplary embodiment of the present invention.

[0040] (Reference Signs)

[0041] 100: Driving controller; 200: Driving circuit; 210: Driving chip; 220: Flexible circuit board; MCB: Main circuit board; DP: Display panel; TR: Pixel transistor; GE: Gate electrode; DE: Drain electrode; SE: Source electrode; PE: Pixel electrode; STE: Energy storage electrode. Detailed Description

[0042] In this specification, when it is mentioned that a certain component (or region, layer, part, etc.) is located on, connected to, or combined with another component, it means that it can be directly arranged / connected / combined on the other component, or a third component can also be arranged therebetween.

[0043] Like reference symbols denote like elements. In addition, in the respective drawings, the thickness, ratio, and size of each element are exaggerated for effective illustration of the technical content. "And / or" includes any one or more combinations that can define the relevant elements.

[0044] The terms first, second, etc. may be used to describe various elements, but the elements are not limited to these terms. These terms are only used for the purpose of differentiating one element from another. For example, without departing from the scope of the claims of the present invention, the first element may be named the second element, and similarly, the second element may also be named the first element. Singular expressions include plural expressions when there is no clear contrary meaning in the text.

[0045] In addition, terms such as "below", "lower side", "above", "upper side", etc. are used to describe the connection relationships of the respective components shown in the drawings. These terms are relative concepts and are described based on the directions shown in the drawings.

[0046] Terms such as "comprising" or "having" should be understood as referring to the presence of the features, numbers, steps, operations, elements, components, or combinations thereof described in the specification, and do not preclude the presence or additional possibility of one or more other features, numbers, steps, operations, elements, components, or combinations thereof in advance.

[0047] Unless otherwise defined, all terms (including technical and scientific terms) used in this specification have the same meaning as commonly understood by those skilled in the art. In addition, terms such as those defined in commonly used dictionaries should be interpreted as having a consistent meaning in the relevant technical context, and are clearly defined herein as long as they are not interpreted as ideal or overly formal meanings.

[0048] Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0049] Figure 1 is a plan view of a display device according to an embodiment of the present invention.

[0050] As Figure 1 shown, the display device according to an embodiment of the present invention includes a display panel DP, a main circuit board MCB, a driving controller 100, and a driving circuit 200.

[0051] The display panel DP is not particularly limited. For example, it may include various display panels such as a liquid crystal display panel, an organic light emitting display panel, an electrophoretic display panel, and an electrowetting display panel. In this embodiment, the liquid crystal display panel is used to illustrate the display panel DP. On the other hand, a liquid crystal display device including a liquid crystal display panel may further include a polarizer, a backlight unit, etc. which are not shown.

[0052] The display panel DP includes a first substrate DS1, a second substrate DS2 spaced apart from the first substrate DS1, and a liquid crystal layer LCL disposed between the first substrate DS1 and the second substrate DS2 (refer to Figure 3 ). In a plane, the display panel DP includes a display area DA in which a plurality of pixels PX11 to PXnm are arranged and a non-display area NDA surrounding the display area DA.

[0053] The display panel DP includes gate lines GL1 to GLn, sub-gate lines SGL1 to SGLn, data lines DL1 to DLm, and pixels PX11 to PXnm disposed on the first substrate DS1.

[0054] The gate lines GL1 to GLn extend in a first direction DR1 and are arranged in sequence in a second direction DR2. The sub-gate lines SGL1 to SGLn extend in the second direction DR2 and are arranged in sequence in the first direction DR1. The first direction DR1 and the second direction DR2 cross each other. In an exemplary embodiment, the first direction DR1 may be orthogonal to the second direction DR2. The data lines DL1 to DLm extend in the first direction DR1 and are arranged in sequence in the second direction DR2. The sub-gate lines SGL1 to SGLn are respectively electrically connected to the corresponding gate lines among the gate lines GL1 to GLn.

[0055] The data lines DL1 to DLm may be arranged parallel to the gate lines GL1 to GLn, and the data lines DL1 to DLm may be arranged to cross the sub-gate lines SGL1 to SGLn.

[0056] In an exemplary embodiment, the number of gate lines GL1 to GLn may be equal to the number of data lines DL1 to DLm. In other embodiments, the number of data lines DL1 to DLm may be more than the number of gate lines GL1 to GLn. When the number of gate lines GL1 to GLn is equal to the number of data lines DL1 to DLm, one data line and one gate line may be alternately arranged in the second direction DR2. When the number of data lines DL1 to DLm is more than the number of gate lines GL1 to GLn, x (x is a positive integer) data lines and one gate line may be alternately arranged in the second direction DR2.

[0057] Only a part of the plurality of pixels PX11 to PXnm is illustrated in Figure 1 . The pixels PX11 to PXnm are respectively connected to corresponding sub-gate lines among the sub-gate lines SGL1 to SGLn and corresponding data lines among the data lines DL1 to DLm.

[0058] The plurality of pixels PX11 to PXnm may be divided into a plurality of groups according to the colors to be displayed. The plurality of pixels PX11 to PXnm may display one of the primary colors. The primary colors may include red, green, blue, and white. The present invention is not limited thereto, and the primary colors may also include various colors such as yellow, cyan, and magenta.

[0059] The driving circuit 200 receives a control signal from the driving controller 100. The driving controller 100 may be mounted on the main circuit board MCB. The driving controller 100 may receive image data and a control signal from an external graphics control unit (not shown). The driving circuit 200 generates gate signals G1 to Gn (refer to Figure 5 ) based on the control signal received from the driving controller 100, and outputs the gate signals G1 to Gn to the gate lines GL1 to GLn. The driving circuit 200 may sequentially output the gate signals G1 to Gn as an effective level (e.g., high level) every horizontal period 1H. For example, the gate signals G1 to Gn may be maintained as an effective level (e.g., high level) within four horizontal periods 4H, respectively.

[0060] In addition, the driving circuit 200 generates a data signal related to the image data provided from the driving controller 100 based on the control signal received from the driving controller 100. The driving circuit 200 outputs the data signal to the data lines DL1 to DLm. The data signal may include a positive-polarity data signal having a positive value with respect to the common voltage and / or a negative-polarity data signal having a negative value. Among the respective data signals applied to the data lines DL1 to DLm within each horizontal period 1H, some may have a positive polarity and some may have a negative polarity. The polarity of the data signal may be inverted every frame to prevent deterioration of the liquid crystal.

[0061] The driving circuit 200 may include a driving chip 210 and a flexible circuit board 220 on which the driving chip 210 is mounted. The display device may include a driving circuit 200 composed of a plurality of driving chips 210 and a plurality of flexible circuit boards 220. The flexible circuit board 220 is electrically connected to the main circuit board MCB and the first substrate DS1. The plurality of driving chips 210 respectively supply gate signals to corresponding gate lines among the gate lines GL1 to GLn, and supply corresponding data signals to corresponding data lines among the data lines DL1 to DLm.

[0062] In Figure 1 it is illustrated that one driving chip 210 generates both a gate signal and a data signal, but the present invention is not limited thereto. For example, a gate driving chip that generates a gate signal and a data driving chip that generates a data signal may be composed of separately independent chips, and thus may be mounted on one flexible circuit board 220.

[0063] Each driving chip 210 may be electrically connected to one end of the first substrate DS1 by Figure 1 the chip-on-film (COF) method shown. In other embodiments, each driving chip 210 may be directly disposed on the non-display area NDA of the display panel DP by the chip-on-glass (COG) method.

[0064] The flexible circuit board 220 has excellent flexibility. Therefore, a part of the flexible circuit board 220 whose one end is connected to the display panel DP may be bent, and thus may be disposed on the back surface of the display panel DP together with the main circuit board MCB. In the non-display area NDA adjacent to the display area DA of the display panel DP in the second direction DR2, no driving circuit and / or driving chip is disposed and / or connected, and thus the area of the non-display area NDA may be minimized.

[0065] Figure 2 is an equivalent circuit diagram of a pixel according to an embodiment of the present invention. Figure 3 is a cross-sectional view of a pixel according to an embodiment of the present invention. Figure 1 The pixels PX11 to PXnm shown may respectively have Figure 2 the equivalent circuit shown.

[0066] As Figure 2 shown, the pixel PXij includes a pixel thin film transistor (hereinafter referred to as a pixel transistor) TR, a liquid crystal capacitor Clc, and a storage capacitor Cst. Hereinafter, in this specification, a transistor means a thin film transistor. In an embodiment of the present invention, the storage capacitor Cst may be omitted.

[0067] The pixel transistor TR is electrically connected to the i-th sub-gate line SGLi and the j-th data line DLj. The pixel transistor TR transfers the data signal received from the j-th data line DLj to the liquid crystal capacitor Clc in response to the gate signal received from the i-th sub-gate line SGLi.

[0068] The liquid crystal capacitor Clc is charged with a voltage corresponding to the data signal transferred from the pixel transistor TR. According to the amount of charge stored in the liquid crystal capacitor Clc, the alignment of the liquid crystal director included in the liquid crystal layer LCL (refer to Figure 3 ) changes. According to the alignment of the liquid crystal director, the light incident on the liquid crystal layer is transmitted or blocked.

[0069] The storage capacitor Cst is connected in parallel with the liquid crystal capacitor Clc. The storage capacitor Cst maintains the alignment of the liquid crystal director for a certain period of time (e.g., 1 horizontal period 1H).

[0070] As Figure 3 shown, the pixel transistor TR includes a gate electrode GE connected to the i-th sub-gate line SGLi (refer to Figure 2 ), an active layer AL overlapping with the gate electrode GE, a source electrode SE connected to the j-th data line DLj (refer to Figure 2 ), and a drain electrode DE disposed away from the source electrode SE.

[0071] The liquid crystal capacitor Clc includes a pixel electrode PE and a common electrode CE. The storage capacitor Cst includes a storage electrode STE.

[0072] The i-th sub-gate line SGLi and the storage electrode STE are disposed on one surface of the first substrate DS1. The gate electrode GE branches from the i-th sub-gate line SGLi. The i-th sub-gate line SGLi and the storage electrode STE may include metals such as aluminum (Al), silver (Ag), copper (Cu), molybdenum (Mo), chromium (Cr), tantalum (Ta), titanium (Ti), or their alloys. The i-th sub-gate line SGLi and the storage electrode STE may include a multi-layer structure, such as a titanium layer and a copper layer.

[0073] A first insulating layer 10 covering the gate electrode GE and the storage electrode STE is disposed on one surface of the first substrate DS1. The first insulating layer 10 may include at least one of an inorganic substance and an organic substance. The first insulating layer 10 may be an organic film or an inorganic film. The first insulating layer 10 may include a multi-layer structure, such as a silicon nitride layer and a silicon oxide layer.

[0074] The active layer AL overlapping with the gate electrode GE is disposed on the first insulating layer 10. The active layer AL may include a semiconductor layer and an ohmic contact layer. The semiconductor layer is disposed on the first insulating layer 10, and the ohmic contact layer is disposed on the semiconductor layer.

[0075] A drain electrode DE and a source electrode SE are disposed on the active layer AL. The drain electrode DE and the source electrode SE are configured to be away from each other. The drain electrode DE and the source electrode SE partially overlap with the gate electrode GE respectively.

[0076] A second insulating layer 20 covering the active layer AL, the drain electrode DE, and the source electrode SE is disposed on the first insulating layer 10. The second insulating layer 20 may include at least one of an inorganic substance and an organic substance. The second insulating layer 20 may be an organic film or an inorganic film. The second insulating layer 20 may include a multilayer structure, such as a silicon nitride layer and a silicon oxide layer.

[0077] A third insulating layer 30 is disposed on the second insulating layer 20. The third insulating layer 30 provides a flat surface. The third insulating layer 30 may include an organic substance.

[0078] A pixel electrode PE is disposed on the third insulating layer 30. The pixel electrode PE is connected to the drain electrode DE through a contact hole CH penetrating the second insulating layer 20 and the third insulating layer 30. An alignment film (not shown) covering the pixel electrode PE may be disposed on the third insulating layer 30.

[0079] A color filter layer CF is disposed on one surface of the second substrate DS2. A common electrode CE is disposed on the color filter layer CF. A common voltage is applied to the common electrode CE. An alignment film (not shown) covering the common electrode CE may be disposed on the common electrode CE. Another insulating layer may also be disposed between the color filter layer CF and the common electrode CE.

[0080] The pixel electrode PE and the common electrode CE disposed sandwiching the liquid crystal layer LCL form a liquid crystal capacitor Clc. In addition, the drain electrode DE and the storage electrode STE disposed sandwiching the first insulating layer 10 form a storage capacitor Cst. The storage electrode STE receives a storage voltage. The storage voltage may have the same value as the common voltage provided to the common electrode CE.

[0081] On the other hand, Figure 3 The cross-section of the pixel PXij shown is merely an example. Different from Figure 3 the example, at least one of the color filter layer CF and the common electrode CE may be disposed on the first substrate DS1. In other words, the liquid crystal display panel according to the present embodiment may include pixels of a VA (Vertical Alignment) mode, a PVA (Patterned Vertical Alignment) mode, an IPS (in-plane switching) mode, an FFS (fringe-field switching) mode, a PLS (Plane to Line Switching) mode, etc.

[0082] Figure 4It is a diagram showing the pixel arrangement of a display panel DP1 related to an exemplary embodiment of the present invention.

[0083] Referring to Figure 4 , the display panel DP1 includes gate lines GL1 to GL8, sub-gate lines SGL1 to SGL8, data lines DL1 to DL8, a plurality of first pixels PXa, and a plurality of second pixels PXb. The gate lines GL1 to GL8 extend in a first direction DR1 and are arranged in sequence in a second direction DR2. The sub-gate lines SGL1 to SGL8 extend in the second direction DR2 and are arranged in sequence in the first direction DR1. The first direction DR1 and the second direction DR2 intersect each other. In the exemplary embodiment, the first direction DR1 and the second direction DR2 may be orthogonal. The data lines DL1 to DL8 extend in the first direction DR1 and are arranged in sequence in the second direction DR2. The sub-gate lines SGL1 to SGL8 are respectively electrically connected to the corresponding gate lines among the gate lines GL1 to GL8. The gate lines GL1 to GL8 and the data lines DL1 to DL8 are configured to be adjacent to each other.

[0084] The plurality of first pixels PXa and the plurality of second pixels PXb may respectively include a pixel transistor TR, a liquid crystal capacitor Clc, and a storage capacitor Cst as shown in Figure 2 . Each of the plurality of first pixels PXa and the plurality of second pixels PXb is respectively connected to the corresponding sub-gate line among the sub-gate lines SGL1 to SGL8 and the corresponding data line among the data lines DL1 to DL8. Each gate signal provided by the gate lines GL1 to GL8 can be transmitted to the plurality of first pixels PXa and the plurality of second pixels PXb through the sub-gate lines SGL1 to SGL8.

[0085] The plurality of first pixels PXa and / or the plurality of second pixels PXb arranged in the same row in the second direction DR2 are connected to the same sub-gate line. The plurality of first pixels PXa and / or the plurality of second pixels PXb arranged in the same column in the first direction DR1 are connected to the same data line.

[0086] Figure 5 Exemplarily showing the gate signals G1 to G8 provided to the gate lines GL1 to GL8 as shown in Figure 4 .

[0087] Referring to Figure 5 , the gate signals G1 to G8 sequentially transition to an effective level (e.g., high level). The gate signals G1 to G8 are signals provided by the driving chip 210 as shown in Figure 1 . The gate signals G1 to G8 can be sequentially activated every one horizontal period 1H. The gate signals G1 to G8 can be maintained at the effective level respectively within four horizontal periods 4H. One horizontal period 1H may refer to Figure 4The time for providing data signals to all of the plurality of first pixels PXa and / or the plurality of second pixels PXb within a row in the second direction DR2 shown.

[0088] Figure 6 Exemplary representation of a first gate signal G1 provided to a first gate line GL1, a second gate signal G2 provided to a second gate line GL2, and Figure 4 the pixel voltage PV11 of the pixel PX11 shown. The pixel voltage PV11 of the pixel PX11 is Figure 2 the voltage of the node N1 of the pixel PXij shown.

[0089] Referring to Figure 2 、 Figure 4 、 Figure 5 and Figure 6 , at a first time point t1, if the first gate signal G1 transitions to a high level, the pixel transistor TR of the pixel PX11 is turned on, and according to the data signal provided through the first data line DL1, the pixel voltage PV11 of the pixel PX11 rises. Ideally, the pixel voltage PV11 provided to the pixel electrode PE of the liquid crystal capacitor Clc and the storage capacitor Cst should be maintained at a certain level within one frame.

[0090] However, due to the parasitic capacitance Cgd between the gate electrode GE and the drain electrode DE (refer to Figure 3 ), at a second time point t2, when the first gate signal G1 transitions to a low level, the pixel voltage PV11 decreases by an amount corresponding to the kick-back voltage Vkba.

[0091] Then, at a third time point t3, when the second gate signal G2 transitions to a low level, the pixel voltage PV11 of the pixel PX11 can decrease by an amount corresponding to the kick-back voltage Vkbb. This is caused by the fringe field generated due to the pixel PX11 being adjacent to the second gate line GL2. As a result, the pixel voltage PV11 of the pixel PX11 decreases by an amount corresponding to the voltage Vkb12, which is the sum of the kick-back voltages Vkba and Vkbb, i.e., Vkba + Vkbb.

[0092] Figure 7 Exemplary representation of a first gate signal G1 provided to a first gate line GL1, a sixth gate signal G6 provided to a sixth gate line GL6, and Figure 4 the pixel voltage PV16 of the pixel PX16 shown. The pixel voltage PV16 of the pixel PX16 is Figure 2 the voltage of the node N1 of the pixel PXij shown.

[0093] Referring to Figure 2 、 Figure 4 、 Figure 5 andFigure 7 , at the first time point t1, if the first gate signal G1 transitions to a high level, the pixel transistor TR of the pixel PX16 is turned on, and according to the data signal provided through the sixth data line DL6, the pixel voltage PV16 of the pixel PX16 rises.

[0094] At the second time point t2, when the first gate signal G1 transitions to a low level, due to the parasitic capacitance Cgd between the gate electrode GE and the drain electrode DE (refer to Figure 3 ), the pixel voltage PV16 decreases by an amount corresponding to the kick-back voltage Vkbc.

[0095] Then, at the fourth time point t4, if the sixth gate signal G6 transitions to a high level, the pixel voltage PV16 of the pixel PX16 rises by an amount corresponding to the kick-back voltage Vkbd. In addition, at the fifth time point t5, if the sixth gate signal G6 transitions to a low level, the pixel voltage PV16 of the pixel PX16 decreases by an amount corresponding to the kick-back voltage Vkbe. That is, the kick-back voltage Vkb16 of the pixel voltage PV16 of the pixel PX16 decreases by an amount corresponding to the kick-back voltage Vkbc and then rises by an amount corresponding to the kick-back voltage Vkbd, and then decreases again by an amount corresponding to the kick-back voltage Vkbe. If it is assumed that Vkbd = Vkbe, the kick-back voltage Vkb16 of the pixel voltage PV16 of the pixel PX16 is substantially equal to the kick-back voltage Vkbc.

[0096] Figure 6 The kick-back voltage Vkb12 of the pixel PX11 shown is greater than Figure 7 the kick-back voltage Vkb16 of the pixel PX16 shown. As Figure 5 shown, when the gate signals G1 to G8 are sequentially activated every one horizontal period 1H and are maintained at an effective level within four horizontal periods 4H, the kick-back voltages of the multiple first pixels PXa arranged adjacent to the (i + 3)-th gate line starting from the i-th column of the i-th row are greater than the kick-back voltages of the pixels adjacent to other gate lines, that is, the multiple second pixels PXb. For example, the kick-back voltages of the four pixels PX11 to PX14 (i.e., the multiple first pixels PXa) connected to the first sub-gate line SGL1 of the first row are each greater than the kick-back voltages of the pixels PX15 to PX18 (i.e., the multiple second pixels PXb). In addition, the kick-back voltages of the multiple first pixels PXa connected to the second sub-gate line SGL2 of the second row and connected to the second data line DL2 to the fifth data line DL5 are greater than the kick-back voltages of the multiple second pixels PXb connected to the remaining data lines DL1, DL6 to DL8. The kick-back voltage deviation as described above may cause non-uniformity of the image displayed on the display panel DP.

[0097] In an exemplary embodiment of the present invention, the gate-drain capacitance Cgd of each of a plurality of second pixels PXb (e.g., pixels PX15 to PX18) is designed to be greater than the gate-drain capacitance Cgd of each of a plurality of first pixels PXa (e.g., pixels PX11 to PX14). If the gate-drain capacitance Cgd of each of the plurality of second pixels PXb becomes larger, the kickback voltage of each of the plurality of second pixels PXb increases. That is, the kickback voltage of each of the plurality of second pixels PXb becomes equal to the kickback voltage of each of the plurality of first pixels PXa. As a result, it is possible to prevent a decrease in display quality caused by a deviation in the kickback voltage between the plurality of first pixels PXa and the plurality of second pixels PXb. A scheme for increasing the gate-drain capacitance Cgd of each of the plurality of second pixels PXb will be described in detail later.

[0098] Figure 8 FIG. is a diagram showing the pixel arrangement of a display panel DP2 according to an exemplary embodiment of the present invention.

[0099] Referring to Figure 8 , the display panel DP2 includes gate lines GL1 to GL5, sub-gate lines SGL1 to SGL5, data lines DL1 to DL30, a plurality of first pixels PXa, and a plurality of second pixels PXb. The gate lines GL1 to GL5 extend in a first direction DR1 and are arranged in sequence in a second direction DR2. The sub-gate lines SGL1 to SGL5 extend in the second direction DR2 and are arranged in sequence in the first direction DR1. The first direction DR1 and the second direction DR2 intersect each other. In the exemplary embodiment, the first direction DR1 and the second direction DR2 may be orthogonal. The data lines DL1 to DL30 extend in the first direction DR1 and are arranged in sequence in the second direction DR2. The sub-gate lines SGL1 to SGL5 are respectively electrically connected to corresponding ones of the gate lines GL1 to GL5. The gate lines GL1 to GL5 and the data lines DL1 to DL30 may be arranged in parallel.

[0100] In Figure 8 the illustrated embodiment, the number of the data lines DL1 to DL30 is greater than the number of the gate lines GL1 to GL5. Therefore, one of the gate lines GL1 to GL5 may be arranged every six data lines among the data lines DL1 to DL30. In the exemplary embodiment, the number of the data lines DL1 to DL30 may be twice the number of the plurality of first pixels PXa and the plurality of second pixels PXb arranged in the same row in the second direction DR2. That is, each data line is arranged adjacent to the left and right sides of the plurality of first pixels PXa and the plurality of second pixels PXb arranged in the same row in the second direction DR2.

[0101] In an exemplary embodiment, a plurality of first pixels PXa and a plurality of second pixels PXb in the i-th row are connected to an i-th sub-gate line SGLi connected to an i-th gate line GLi. The plurality of first pixels PXa in the i-th row are pixels that are connected to the i-th sub-gate line SGLi and are arranged adjacent to the i-th gate line GLi to the (i + k)-th gate line GLi + k (i and k are natural numbers, respectively). The plurality of second pixels PXb are the remaining pixels other than the plurality of first pixels PXa. When the gate signals G1 to G5 supplied to the gate lines GL1 to GL5 are sequentially activated every other horizontal period 1H and maintained at an effective level within four horizontal periods 4H, k may be 3.

[0102] The plurality of first pixels PXa and the plurality of second pixels PXb may each include Figure 2 a pixel transistor TR, a liquid crystal capacitor Clc, and a storage capacitor Cst as shown. Each of the plurality of first pixels PXa and the plurality of second pixels PXb is connected to a corresponding sub-gate line among the sub-gate lines SGL1 to SGL5 and a corresponding data line among the data lines DL1 to DL30. Each gate signal supplied through the gate lines GL1 to GL5 may be supplied to the plurality of first pixels PXa and the plurality of second pixels PXb through the sub-gate lines SGL1 to SGL5.

[0103] The plurality of first pixels PXa and / or the plurality of second pixels PXb arranged in the same row in the second direction DR2 are connected to the same sub-gate line. The plurality of first pixels PXa and / or the plurality of second pixels PXb arranged in the same column in the first direction DR1 are alternately connected to the data line adjacent to the left side and the data line adjacent to the right side. In Figure 8 the example shown, the plurality of first pixels PXa and / or the plurality of second pixels PXb arranged in the same column in the first direction DR1 are alternately connected to the data line adjacent to the left side and the data line adjacent to the right side in units of two. For example, in a predetermined frame, it may be that the odd-numbered data lines DL1, DL3, DL5,... are driven by a positive-polarity data signal, and the even-numbered data lines DL2, DL4, DL6,... are driven by a negative-polarity data signal.

[0104] Figure 8 Among the pixels of the display panel DP2 shown, a part of them is adjacent to the gate line extending in the first direction DR1, and another part is not directly adjacent to the gate line. The gate signals G1 to G5 shown may be respectively supplied to the gate lines GL1 to GL5. Figure 5 as shown.

[0105] As in Figure 6 and Figure 7As described above, when the gate signals G1 to G5 are sequentially activated every horizontal period 1H and maintained at an effective level within four horizontal periods 4H, the kickback voltage of the plurality of first pixels PXa adjacent to the i-th row and the i-th gate line to the (i + 3)-th gate line is greater than the kickback voltage of the plurality of second pixels PXb. For example, the kickback voltage of each of the seven pixels PX11, PX13, PX14, PX16, PX17, PX19, and PX20 connected to the first sub-gate line SGL1 of the first row is greater than the kickback voltage of each of the pixels PX12, PX15, PX18, and PX21 to PX25. The pixels PX11, PX13, PX14, PX16, PX17, PX19, and PX20 are adjacent to the gate lines GL1, GL2, GL3, and GL4, respectively, so the kickback voltage may increase due to the influence of the fringe field.

[0106] The pixels PX12 arranged between the pixels PX11 and PX13, the pixels PX15 arranged between the pixels PX14 and PX16, and the pixels PX18 arranged between the pixels PX17 and PX19 are not arranged to be directly adjacent to the gate lines, so they are not affected by the fringe field. The pixel PX21 connected to the first sub-gate line SGL1 is also not arranged to be directly adjacent to the gate lines, so it is not affected by the fringe field.

[0107] The pixels PX22 and PX23 connected to the first sub-gate line SGL1 reduce the kickback voltage when the fifth gate signal G5 migrates from a low level to a high level after the first gate signal G1 migrates to a low level, and increase the kickback voltage when the fifth gate signal G5 migrates from a high level to a low level, so the kickback voltage is small. The pixels PX24 and PX25 connected to the first sub-gate line SGL1 are not arranged to be directly adjacent to the gate lines, so they are not affected by the fringe field.

[0108] In addition, the kickback voltage of each pixel connected to the second sub-gate line SGL2 of the second row and adjacent to the second gate line GL2 to the fifth gate line GL5 is greater than the kickback voltage of each other pixel. The kickback voltage deviation as described above may cause non-uniformity of the image displayed on the display panel DP2.

[0109] In an exemplary embodiment of the present invention, the first pixel PXa may be a pixel adjacent to a gate line and affected by a kickback voltage caused by a gate signal transmitted through the adjacent gate line. The second pixel PXb may be a pixel that is not adjacent to the gate line or is configured to be adjacent to the gate line but is not affected by the kickback voltage caused by the gate signal transmitted through the adjacent configured gate line. A "pixel not adjacent to the gate line" refers to a pixel that is not directly adjacent to the gate line, but is far from the gate line, and other pixels (e.g., the first pixel PXa) are provided between the pixel and the gate line, so as not to be affected by the fringe field.

[0110] The gate-drain capacitances Cgd of the plurality of second pixels PXb are each designed to be greater than the gate-drain capacitances Cgd of the plurality of first pixels PXa. If the gate-drain capacitances Cgd of the plurality of second pixels PXb become larger, the kickback voltages of the plurality of second pixels PXb will increase. That is, the kickback voltages of the plurality of second pixels PXb will become equal to the kickback voltages of the plurality of first pixels PXa. As a result, a reduction in display quality caused by a deviation in the kickback voltages between the plurality of first pixels PXa and the plurality of second pixels PXb can be prevented. Hereinafter, a scheme for increasing the gate-drain capacitances Cgd of the plurality of second pixels PXb will be described in detail.

[0111] Figure 9 is a plan view of the first pixel PXa and the second pixel PXb according to an exemplary embodiment of the present invention. In Figure 9 shown as an example of the first pixel PX33 and the second pixel PX32 as the first pixel PXa and the second pixel PXb for illustration. Figure 8 shown as an example of the first pixel PX33 and the second pixel PX32 as the first pixel PXa and the second pixel PXb for illustration. Figure 8 Other first pixels and second pixels shown may also be formed of the same structure as the first pixel PX33 and the second pixel PX32 shown in Figure 9 shown as an example of the first pixel PX33 and the second pixel PX32 as the first pixel PXa and the second pixel PXb for illustration.

[0112] Figure 9 shown, the first pixel PXa is the pixel PX33 adjacent to the gate line, and the second pixel PXb is the pixel PX32 not adjacent to the gate line, but the present invention is not limited thereto. As described in Figure 8 The first pixel PXa may be any one of a plurality of pixels configured adjacent to the gate line and affected by the kickback voltage caused by the gate signal transmitted through the adjacent gate line. The second pixel PXb may be any one of a plurality of pixels not adjacent to the gate line. In addition, the second pixel PXb may be any one of a plurality of pixels configured adjacent to the gate line but not affected by the kickback voltage caused by the gate signal transmitted through the adjacent configured gate line.

[0113] The first pixel PXa is connected to the fifth data line DL5 and is also connected to the second sub - gate line SGL2. In the second direction DR2, a sixth data line DL6 can be arranged adjacent to the fifth data line DL5.

[0114] The first pixel PXa includes a first pixel transistor TRa, a first storage electrode STEa, and a first pixel electrode PEa. The first pixel transistor TRa includes a first source electrode SEa, a first drain electrode DEa, and a first gate electrode GEa. The first gate electrode GEa can be electrically connected to the second gate line GL2 through a gate contact hole CHg. The first drain electrode DEa can be arranged above the first gate electrode GEa and away from the first source electrode SEa.

[0115] The first drain electrode DEa is electrically connected to the first pixel electrode PEa through a drain contact hole CHa. Therefore, if the first pixel transistor TRa is turned on in response to a gate signal applied from the second sub - gate line SGL2, the first pixel transistor TRa can output a data signal applied from the fifth data line DL5 to the first drain electrode DEa. The data signal output through the first drain electrode DEa is applied to the first pixel electrode PEa. A part of the first drain electrode DEa overlaps with the first storage electrode STEa and the first pixel electrode PEa.

[0116] In Figure 9 it is shown that the first storage electrode STEa and the first pixel electrode PEa each have a quadrilateral shape, but the shapes of the first storage electrode STEa and the first pixel electrode PEa are not limited to this. For example, the first storage electrode STEa can have a polygonal shape. The first pixel electrode PEa can include a plurality of fine slits separated by a distance in micrometers. Through the fine slits, the liquid crystal molecules of the liquid crystal layer LCL (shown in Figure 3 ) can be pre - tilted in different directions in domains.

[0117] The second pixel PXb is connected to the third data line DL3 and is also connected to the second sub - gate line SGL2. In the second direction DR2, a fourth data line DL4 can be arranged adjacent to the third data line DL3.

[0118] The second pixel PXb includes a second pixel transistor TRb, a second storage electrode STEb, and a second pixel electrode PEb. The second pixel transistor TRb includes a second source electrode SEb, a second drain electrode DEb, and a second gate electrode GEb. The second gate electrode GEb can be electrically connected to the second gate line GL2 through a gate contact hole CHg. The first gate electrode GEa of the first pixel transistor TRA and the second gate electrode GEb of the second pixel transistor TRb can be part of a second sub-gate line SGL2 extending in the second direction DR2. The second sub-gate line SGL2 is electrically connected to the second gate line GL2 through a gate contact hole CHg. The second drain electrode DEb can be disposed above the second gate electrode GEb and away from the second source electrode SEb.

[0119] The second drain electrode DEb is electrically connected to the second pixel electrode PEb through a drain contact hole CHb. Therefore, if the second pixel transistor TRb is turned on in response to a gate signal applied from the second sub-gate line SGL2, the second pixel transistor TRb can output a data signal applied from the third data line DL3 to the second drain electrode DEb. The data signal output through the second drain electrode DEb is applied to the second pixel electrode PEb. A part of the second drain electrode DEb overlaps with the second storage electrode STEb and the second pixel electrode PEb.

[0120] In Figure 9 is shown the case where the second storage electrode STEb and the second pixel electrode PEb are each quadrilateral in shape, but the shapes of the second storage electrode STEb and the second pixel electrode PEb are not limited thereto. For example, the second storage electrode STEb can have a polygonal shape. The second pixel electrode PEb can include a plurality of fine gaps spaced apart by a distance in micrometers. Through the fine gaps, each liquid crystal molecule of the liquid crystal layer LCL (shown in Figure 3 ) can be pre-tilted in different directions in units of domains.

[0121] The second gate electrode GEb includes a main gate electrode GE_M and a sub-gate electrode GE_S. The second drain electrode DEb includes a main drain electrode DE_M and a sub-drain electrode DE_S.

[0122] The main gate electrode GE_M overlaps with the second source electrode SEb and the main drain electrode DE_M of the second drain electrode DEb. The sub-gate electrode GE_S has a shape protruding from the main gate electrode GE_M in the first direction DR1.

[0123] The sub-drain electrode DE_S of the second drain electrode DEb has a shape that protrudes from the main drain electrode DE_M in the second direction DR2. A part of the sub-gate electrode GE_S overlaps with a part of the sub-drain electrode DE_S in a plane to form an overlapping region OVA1. The capacitance formed by the overlapping region OVA1 between the sub-gate electrode GE_S and the sub-drain electrode DE_S can increase the gate-drain capacitance Cgd between the second gate electrode GEb and the second drain electrode DEb. The sub-drain electrode DE_S does not overlap with the main gate electrode GE_M in a plane, and the sub-gate electrode GE_S does not overlap with the main drain electrode DE_M in a plane.

[0124] As Figure 9 shown, the first pixel electrode PEa of the first pixel PXa is configured to be adjacent to the second gate line GL2. Therefore, due to the influence of the edge field, the kickback voltage of the first pixel PXa is greater than the kickback voltage of the second pixel PXb. By designing the gate-drain capacitance Cgd of the second pixel PXb to be greater than the gate-drain capacitance Cgd of the first pixel PXa, the kickback voltage of the second pixel PXb can be made equal to the kickback voltage of the first pixel PXa. As a result, a reduction in display quality caused by a deviation in kickback voltage between the first pixel PXa and the second pixel PXb can be prevented.

[0125] The area of the overlapping region OVA1 between the sub-gate electrode GE_S and the sub-drain electrode DE_S is determined according to the gate-drain capacitance Cgd of the second pixel PXb that can compensate for the deviation between the kickback voltage of the first pixel PXa and the kickback voltage of the second pixel PXb.

[0126] Figure 10 is a plan view of the first pixel PXa and the second pixel PXb according to an exemplary embodiment of the present invention. Figure 10 The first pixel PXa and the second pixel PXb shown are substantially the same as the first pixel PXa and the second pixel PXb shown Figure 9 shown, so repeated descriptions are omitted.

[0127] Referring to Figure 10 , the second gate electrode GEb includes a main gate electrode GE_M and a sub-gate electrode GE_S. The second drain electrode DEb includes a main drain electrode DE_M and a sub-drain electrode DE_S.

[0128] The main gate electrode GE_M overlaps with the second source electrode SEb and the main drain electrode DE_M of the second drain electrode DEb. The sub-gate electrode GE_S has a shape that protrudes from the main gate electrode GE_M in the first direction DR1.

[0129] The sub-drain electrode DE_S of the second drain electrode DEb has a shape protruding from the main drain electrode DE_M in the opposite direction of the second direction DR2. A part of the sub-gate electrode GE_S and a part of the sub-drain electrode DE_S overlap on a plane, thereby forming an overlapping region OVA2. The capacitance formed by the overlapping region OVA2 between the sub-gate electrode GE_S and the sub-drain electrode DE_S can increase the gate-drain capacitance Cgd between the second gate electrode GEb and the second drain electrode DEb.

[0130] Figure 11 FIG. is a diagram showing a pixel arrangement of a display panel DP3 according to an exemplary embodiment of the present invention.

[0131] Refer to Figure 11 , the display panel DP3 includes gate lines GL1 to GL6, sub-gate lines SGL1 to SGL4, SGL1' to SGL4', data lines DL1 to DL36, a plurality of first pixels PXa, and a plurality of second pixels PXb. The gate lines GL1 to GL6 extend in a first direction DR1 and are arranged in sequence in a second direction DR2. The sub-gate lines SGL1 to SGL4, SGL1' to SGL4' extend in the second direction DR2 and are arranged in sequence in the first direction DR1. The data lines DL1 to DL36 extend in the first direction DR1 and are arranged in sequence in the second direction DR2. The sub-gate lines SGL1 to SGL4, SGL1' to SGL4' are respectively electrically connected to corresponding gate lines among the gate lines GL1 to GL4. The gate lines GL1 to GL6 and the data lines DL1 to DL36 can be arranged in parallel.

[0132] In Figure 11 In the illustrated embodiment, two sub-gate lines are connected to one gate line. For example, the sub-gate line SGL1 and SGL1' are connected to the gate line GL1. The sub-gate line SGL2 and SGL2' are connected to the gate line GL2. The sub-gate line SGL3 and SGL3' are connected to the gate line GL3. The sub-gate line SGL4 and SGL4' are connected to the gate line GL4. Although not illustrated, the gate lines GL5 and GL6 may also be respectively connected to two sub-gate lines.

[0133] In addition, in Figure 11In the illustrated embodiment, the number of data lines DL1 to DL36 is greater than the number of gate lines GL1 to GL6. One of the gate lines GL1 to GL6 may be arranged among the data lines DL1 to DL36 every six data lines. In an exemplary embodiment, the number of data lines DL1 to DL36 may be twice the number of a plurality of first pixels PXa and a plurality of second pixels PXb arranged in the same row in the second direction DR2. That is, each of the data lines may be arranged adjacent to the left and right sides of the plurality of first pixels PXa and the plurality of second pixels PXb arranged in the same row in the second direction DR2, respectively.

[0134] As Figure 2 shown, the plurality of first pixels PXa and the plurality of second pixels PXb may each include a pixel transistor TR, a liquid crystal capacitor Clc, and a storage capacitor Cst. Each of the plurality of first pixels PXa and the plurality of second pixels PXb may be connected to a corresponding sub-gate line among sub-gate lines SGL1 to SGL4, SGL1' to SGL4' and a corresponding data line among data lines DL1 to DL36. Each gate signal provided through the gate lines GL1 to GL4 may be transmitted to the plurality of first pixels PXa and the plurality of second pixels PXb through the sub-gate lines SGL1 to SGL4, SGL1' to SGL4'.

[0135] In Figure 11 the illustrated example, two rows are commonly connected to the same gate line through two sub-gate lines. For example, the plurality of first pixels PXa and the plurality of second pixels PXb connected to the sub-gate lines SGL1 and SGL1' commonly receive the gate signal provided through the gate line GL1.

[0136] In an exemplary embodiment, the plurality of first pixels PXa and the plurality of second pixels PXb in the (2i - 1)th (e.g., odd-numbered) row are connected to the sub-gate line SGLi connected to the ith gate line GLi. The plurality of first pixels PXa and the plurality of second pixels PXb in the 2ith (e.g., even-numbered) row are connected to the sub-gate line SGLi' connected to the ith gate line GLi. The plurality of first pixels PXa in the (2i - 1)th row are pixels arranged adjacent to the ith gate line GLi to the (i + k)th (i and k are natural numbers, respectively) gate line GLi + k. The plurality of second pixels PXb are the remaining pixels except for the plurality of first pixels PXa. When the gate signals G1 to G6 are sequentially activated every one horizontal period 1H and maintained at an effective level within four horizontal periods 4H, k may be 3.

[0137] A plurality of first pixels PXa and / or a plurality of second pixels PXb arranged in the same row in the second direction DR2 are connected to the same sub-gate line. A plurality of first pixels PXa and / or a plurality of second pixels PXb arranged in the same column in the first direction DR1 may be alternately connected to a data line adjacent on the left side and a data line adjacent on the right side. In Figure 11 In the example shown, a plurality of first pixels PXa and / or a plurality of second pixels PXb arranged in the same column in the first direction DR1 are alternately connected to a data line adjacent on the left side and a data line adjacent on the right side one by one. For example, in a predetermined frame, odd-numbered data lines (DL1, DL3, DL5, …) may be driven by a data signal of positive polarity, and even-numbered data lines (DL2, DL4, DL6, …) may be driven by a data signal of negative polarity.

[0138] As previously Figure 6 and Figure 7 As described in, when the gate signals G1 to G6 are sequentially activated every other horizontal period 1H and maintained at an effective level within four horizontal periods 4H, in the 2i - 1th row, the kickback voltage of a plurality of first pixels PXa arranged adjacent to the i-th gate line to the i + 3-th gate line is greater than the kickback voltage of a plurality of second pixels PXb. For example, the kickback voltage of each of the seven pixels PX11, PX13, PX14, PX16, PX17, PX19, PX20 connected to the first sub-gate line SGL1 in the first row is greater than the kickback voltage of each of the pixels PX12, PX15, PX18, PX21 to PX28. The pixels PX11, PX13, PX14, PX16, PX17, PX19, PX20 are adjacent to the gate lines GL1, GL2, GL3, GL4 respectively, so due to the influence of the edge field, the kickback voltage may become larger.

[0139] The pixels PX12 arranged between the pixels PX11 and PX13, the pixels PX15 arranged between the pixels PX14 and PX16, and the pixels PX18 arranged between the pixels PX17 and PX19 are configured not to be directly adjacent to the gate line, so they are not affected by the edge field. The pixel PX21 connected to the first sub-gate line SGL1 is also configured not to be directly adjacent to the gate line, so it is not affected by the edge field.

[0140] The pixels PX22 and PX23 connected to the sub-gate line SGL1 reduce the kickback voltage when the fifth gate signal G5 migrates from low level to high level after the first gate signal G1 migrates to low level, and increase the kickback voltage when the fifth gate signal G5 migrates from high level to low level, so the kickback voltage is small. The pixels PX24 and PX27 connected to the first sub-gate line SGL1 are configured not to be directly adjacent to the gate line, so they are not affected by the edge field.

[0141] Each pixel connected to the sub-gate line SGL1’ receives the same gate signal as the sub-gate line SGL1 through the gate line GL1. Therefore, the arrangement order of the multiple first pixels PXa and the multiple second pixels PXb in two adjacent rows in the first direction DR1 can be the same..

[0142] Figure 11 The multiple first pixels PXa and the multiple second pixels PXb shown may have the same shape as Figure 9 and Figure 10 the first pixel PXa and the second pixel PXb shown. That is, it is designed such that the gate-drain capacitance Cgd of the second pixel PXb is greater than the gate-drain capacitance Cgd of the first pixel PXa, so that the kickback voltage of the second pixel PXb can be equal to the kickback voltage of the first pixel PXa. As a result, it is possible to prevent a decrease in display quality caused by a deviation in kickback voltage between the first pixel PXa and the second pixel PXb.

[0143] Figure 12 FIG. is a diagram showing the pixel arrangement of the display panel DP4 according to an exemplary embodiment of the present invention.

[0144] Referring to Figure 12 , the display panel DP4 includes gate lines GL1 to GL12, sub-gate lines SGL1 to SGL8, data lines DL1 to DL18, multiple first pixels PXa, and multiple second pixels PXb. The gate lines GL1 to GL12 extend in the first direction DR1 and are arranged in sequence in the second direction DR2. The sub-gate lines SGL1 to SGL8 extend in the second direction DR2 and are arranged in sequence in the first direction DR1. The data lines DL1 to DL18 extend in the first direction DR1 and are arranged in sequence in the second direction DR2. The sub-gate lines SGL1 to SGL8 are respectively electrically connected to the corresponding gate lines among the gate lines GL1 to GL8. The gate lines GL1 to GL12 and the data lines DL1 to DL18 can be arranged in parallel.

[0145] In Figure 12 the embodiment shown, the number of the data lines DL1 to DL18 is more than the number of the gate lines GL1 to GL12. Two gate lines among the gate lines GL1 to GL12 can be arranged every three data lines among the data lines DL1 to DL18. In the exemplary embodiment, the number of the data lines DL1 to DL18 can be equal to the number of the multiple first pixels PXa and the multiple second pixels PXb arranged in the same row in the second direction DR2. For example, the multiple first pixels PXa and the multiple second pixels PXb can be connected to each data line adjacent to each other on the left side.

[0146] As Figure 2As shown, a plurality of first pixels PXa and a plurality of second pixels PXb may each include a pixel transistor TR, a liquid crystal capacitor Clc, and a storage capacitor Cst. The plurality of first pixels PXa and the plurality of second pixels PXb are respectively connected to corresponding sub-gate lines among sub-gate lines SGL1 to SGL8 and corresponding data lines among data lines DL1 to DL18. Each gate signal provided through gate lines GL1 to GL12 is transmitted to the plurality of first pixels PXa and the plurality of second pixels PXb through sub-gate lines SGL1 to SGL8.

[0147] In an exemplary embodiment, the plurality of first pixels PXa and the plurality of second pixels PXb in the i-th row are connected to the i-th sub-gate line SGLi connected to the i-th gate line GLi. The plurality of first pixels PXa in the i-th row are pixels arranged adjacent to the i-th gate line GLi to the (i + k)-th (i and k are natural numbers respectively) gate line GLi + k. The plurality of second pixels PXb are the remaining pixels other than the plurality of first pixels PXa. When the gate signals G1 to G12 provided to gate lines GL1 to GL12 are sequentially activated every one horizontal period 1H and are maintained at an effective level within four horizontal periods 4H, k may be 3.

[0148] As described above Figure 6 and Figure 7 As described in the foregoing, when the gate signals G1 to G11 provided to gate lines GL1 to GL11 are sequentially activated every one horizontal period 1H and are maintained at an effective level within eight horizontal periods 8H, the kickback voltage of the plurality of first pixels PXa arranged adjacent to the i-th gate line to the (i + 7)-th gate line in the i-th row is greater than the kickback voltage of the plurality of second pixels PXb. For example, the kickback voltage of each of the seven pixels PX11, PX13, PX14, PX16, PX17, PX19, PX20 connected to the first sub-gate line SGL1 of the first row is greater than the kickback voltage of each of the pixels PX12, PX15, PX18, PX21 to PX28. The pixels PX11, PX13, PX14, PX16, PX17, PX19, PX20 are adjacent to gate lines GL2 to GL8 respectively, so due to the influence of the fringe field, the kickback voltage may increase.

[0149] The pixels PX12 arranged between pixels PX11 and PX13, the pixels PX15 arranged between pixels PX14 and PX16, and the pixels PX18 arranged between pixels PX17 and PX19 are not arranged to be directly adjacent to each gate line, and thus are not affected by the fringe field. The pixels PX21 to PX28 connected to the sub-gate line SGL1 are not affected by the kickback voltage and the fringe field.

[0150] Figure 12The multiple first pixels PXa and the multiple second pixels PXb shown may have the same shape as the first pixel PXa and the second pixel PXb shown in Figure 9 and Figure 10 That is, by designing the gate-drain capacitance Cgd of the second pixel PXb to be greater than the gate-drain capacitance Cgd of the first pixel PXa, the kickback voltage of the second pixel PXb can be made equal to the kickback voltage of the first pixel PXa. As a result, a reduction in display quality caused by a deviation in the kickback voltage between the first pixel PXa and the second pixel PXb can be prevented.

[0151] As described above, the preferred embodiments of the present invention have been described with reference to the embodiments, but those skilled in the art should be able to understand that the present invention can be modified or changed in various ways without departing from the spirit of the present invention described in the claims and the technical field.

[0152] Therefore, the technical scope of the present invention is not limited to the content described in the detailed description of the specification, and should be determined by the scope of the claims.

Claims

1. A display device, comprising: a display panel including gate lines extending in a first direction, sub-gate lines extending in a second direction intersecting the first direction and electrically connected to the gate lines, first data lines and second data lines extending in the first direction, first pixels connected to the sub-gate lines and the first data lines, and second pixels connected to the sub-gate lines and the second data lines; and a driving circuit configured to provide a gate signal to the gate lines and data signals to the first data lines and the second data lines, wherein the first pixel includes a first source electrode connected to the first data line, a first drain electrode connected to a first pixel electrode, and a first gate electrode connected to the sub-gate line, the second pixel includes a second source electrode connected to the second data line, a second drain electrode connected to a second pixel electrode, and a second gate electrode connected to the sub-gate line, the first pixel is disposed adjacent to the gate line, the second pixel is away from the gate line, and the first pixel is provided between the second pixel and the gate line, and a second capacitance between the second drain electrode and the second gate electrode of the second pixel is larger than a first capacitance between the first drain electrode and the first gate electrode of the first pixel.

2. The display device according to claim 1, wherein an overlapping area between the second drain electrode and the second gate electrode of the second pixel is larger than an overlapping area between the first drain electrode and the first gate electrode of the first pixel.

3. The display device according to claim 1, wherein the second drain electrode of the second pixel includes a main drain electrode disposed apart from the second source electrode and a sub-drain electrode protruding from the main drain electrode, the second gate electrode of the second pixel includes a main gate electrode overlapping with the second source electrode and the main drain electrode and a sub-gate electrode protruding from the main gate electrode, and a part of the sub-drain electrode overlaps with a part of the sub-gate electrode in a plane.

4. The display device according to claim 3, wherein the sub-drain electrode does not overlap with the main gate electrode.

5. The display device according to claim 3, wherein the sub-gate electrode does not overlap with the main drain electrode.

6. The display device according to claim 1, wherein the number of the gate lines is equal to the number of the data lines.

7. The display device according to claim 1, wherein the first pixel and the second pixel are disposed adjacent to each other in the second direction.

8. The display device according to claim 7, wherein the number of the data lines is more than the number of the gate lines.

9. The display device according to claim 1, wherein the driving circuit includes: a flexible circuit board connected to one side of the display panel; and a driving chip mounted on the flexible circuit board to provide the gate signal and the data signal.

10. A display device, comprising: A display panel, including a plurality of gate lines extending in a first direction, a plurality of sub-gate lines extending in a second direction intersecting the first direction and electrically connected to the plurality of gate lines respectively, a plurality of data lines extending in the first direction, and a plurality of first pixels and a plurality of second pixels respectively connected to the plurality of sub-gate lines and the plurality of data lines; And A driving circuit, providing a plurality of gate signals to the plurality of gate lines respectively, and providing a plurality of data signals to the plurality of data lines respectively, The plurality of first pixels are connected to the i-th sub-gate line among the plurality of sub-gate lines, and the plurality of first pixels are arranged adjacent to the i-th gate line to the (i + k)-th gate line among the plurality of gate lines, where i and k are natural numbers respectively, The plurality of first pixels respectively include a first source electrode connected to a corresponding data line among the plurality of data lines, a first drain electrode connected to a first pixel electrode, and a first gate electrode connected to the sub-gate line, The plurality of second pixels respectively include a second source electrode connected to a corresponding data line among the plurality of data lines, a second drain electrode connected to a second pixel electrode, and a second gate electrode connected to the sub-gate line, Each of the plurality of second pixels is away from a specific gate line in a manner of being separated by a corresponding first pixel among the plurality of first pixels, and the specific gate line is a gate line among the i-th gate line to the (i + k)-th gate line that is adjacent to the corresponding first pixel, A second capacitance between the second drain electrode and the second gate electrode of each of the plurality of second pixels is larger than a first capacitance between the first drain electrode and the first gate electrode of each of the plurality of first pixels.

11. The display device according to claim 10, Wherein, An overlapping area between the second drain electrode and the second gate electrode of each of the plurality of second pixels is larger than an overlapping area between the first drain electrode and the first gate electrode of the first pixel.

12. The display device according to claim 10, Wherein, The second drain electrode of each of the plurality of second pixels includes a main drain electrode arranged away from the second source electrode and a sub-drain electrode protruding from the main drain electrode, The second gate electrode of the second pixel includes a main gate electrode overlapping with the second source electrode and the main drain electrode and a sub-gate electrode protruding from the main gate electrode, A part of the sub-drain electrode overlaps with a part of the sub-gate electrode in a plane.

13. The display device according to claim 12, Wherein, The sub-drain electrode does not overlap with the main gate electrode.

14. The display device according to claim 12, Wherein, The sub-gate electrode does not overlap with the main drain electrode.

15. The display device according to claim 10, Wherein, The plurality of gate signals provided to the plurality of gate lines are sequentially activated to an effective level every other horizontal period and are maintained at the effective level within k + 1 horizontal periods.

16. The display device according to claim 10, Wherein, An odd number of data lines among the plurality of data lines are arranged on the left side of the plurality of first pixels and the plurality of second pixels. An even number of data lines among the plurality of data lines are arranged on the right side of the plurality of first pixels and the plurality of second pixels. The plurality of first pixels and the plurality of second pixels are respectively connected to any one of the odd number of data lines and the even number of data lines.

17. The display device according to claim 16, wherein, the odd number of data lines among the plurality of data lines alternately transmit a positive polarity data signal and a negative polarity data signal in each frame. the even number of data lines among the plurality of data lines alternately transmit the negative polarity data signal and the positive polarity data signal in each frame.

18. The display device according to claim 16, wherein, each of the first pixels and each of the second pixels arranged in the same column in the first direction among the plurality of first pixels and the plurality of second pixels are alternately connected to corresponding odd number of data lines among the odd number of data lines and corresponding even number of data lines among the even number of data lines.

19. The display device according to claim 10, wherein, the driving circuit includes: a flexible circuit board connected to one side of the display panel; and a driving chip mounted on the flexible circuit board to provide the plurality of gate signals and the plurality of data signals.

20. The display device according to claim 10, wherein, the display panel further includes: a first substrate; a second substrate facing the first substrate; and a liquid crystal layer disposed between the first substrate and the second substrate, the plurality of gate lines, the plurality of sub-gate lines, the plurality of data lines, the plurality of first pixels, and the plurality of second pixels are disposed on the first substrate.

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