Memory array including memory cell strings and method for forming a memory array including memory cell strings

Abstract

The present application relates to a memory array including a string of memory cells and a method for forming a memory array including a string of memory cells. The memory array includes a conductor layer including a conductor material. The memory array includes laterally spaced memory blocks each including a vertical stack directly above the conductor layer, the vertical stack including alternating insulating layers and conductive layers. The conductive material of the lowest of the conductive layers directly abuts the conductive material of the conductor layer. The channel material string of the memory cells extends through the insulating layer and the conductive layer. Intermediate material is laterally between the laterally adjacent memory blocks and longitudinally along the laterally adjacent memory blocks. The conductive material in the lowest conductive layer directly abuts the channel material of individual ones of the channel material string. The conductive material has a composition different from that of the conductive material and is above and directly abutting the conductive material. Other embodiments are disclosed, including methods.

Description

Technical Field

[0001] Embodiments disclosed herein relate to memory arrays and to methods for forming memory arrays. Background Art

[0002] Memory is an integrated circuit system used in computer systems to store data. Memory can be fabricated as one or more arrays of individual memory cells. Memory cells can be written to or read from using digit lines (which may also be called bit lines, data lines, or sense lines) and access lines (which may also be called word lines). Sense lines conductively interconnect memory cells along the columns of the array, and access lines conductively interconnect memory cells along the rows of the array. Each memory cell can be uniquely addressed by a combination of sense and access lines.

[0003] Memory cells can be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for extended periods of time without power. Non-volatile memory is typically designated as memory with a retention time of at least about 10 years. Volatile memory dissipates and is therefore refreshed / rewritten to maintain data storage. Volatile memory can have a retention time of milliseconds or less. Regardless, the memory cell is configured to hold or store memory in at least two different selectable states. In a binary system, the states are considered to be "0" or "1." In other systems, at least some individual memory cells can be configured to store information in more than two levels or states.

[0004] A field-effect transistor is an electronic component that can be used in memory cells. These transistors include a pair of conductive source / drain regions with a semiconducting channel region between them. A conductive gate is adjacent to the channel region and separated from it by a thin gate insulator. Applying a suitable voltage to the gate allows current to flow from one source / drain region to the other through the channel region. When the voltage is removed from the gate, current flow through the channel region is substantially prevented. Field-effect transistors may also include additional structures, such as a reversibly programmable charge storage region as part of the gate structure between the gate insulator and the conductive gate.

[0005] Flash memory is a type of memory that is widely used in modern computers and devices. For example, modern personal computers may store the BIOS on a flash memory chip. As another example, it is increasingly common for computers and other devices to utilize flash memory in solid-state drives instead of conventional hard disk drives. As yet another example, flash memory is prevalent in wireless electronic devices because it enables manufacturers to support new communication protocols as they become standardized and to provide the ability to remotely upgrade devices for enhanced features.

[0006] NAND can be the basic architecture of integrated flash memory. A NAND cell device includes at least one select device coupled in series with a series combination of memory cells (and the series combination is often referred to as a NAND string). The NAND architecture can be configured in a three-dimensional arrangement, including vertically stacked memory cells that individually include vertical transistors that can be reversibly programmed. Control circuitry or other circuitry can be formed below the vertically stacked memory cells. Other volatile or non-volatile memory array architectures can also include vertically stacked memory cells that individually include transistors.

[0007] The memory array may be arranged in memory pages, memory blocks, and partial blocks (e.g., sub-blocks), and memory planes, such as shown and described in any of U.S. Patent Application Publications Nos. 2015 / 0228651, 2016 / 0267984, and 2017 / 0140833. A memory block may at least partially define the longitudinal profiles of individual word lines in individual word line layers of vertically stacked memory cells. Connections to these word lines may occur in a so-called "staircase structure" at the ends or edges of the array of vertically stacked memory cells. The staircase structure includes individual "steps" (alternatively referred to as "steps" or "stairs") that define contact areas for individual word lines, with vertically extending conductive vias contacting the contact areas to provide electrical access to the word lines. Summary of the Invention

[0008] In one aspect, the present application provides a method for forming a memory array including a string of memory cells, comprising: forming a conductor layer including a conductor material on a substrate; forming a stack including vertically alternating first and second layers above the conductor layer, the stack including laterally spaced memory blocks with horizontally elongated trenches therebetween, the string of channel material extending through the first and second layers, the material of the first layers having a composition different from that of the second layers, the lowest of the first layers being thicker than the first layers above it, the second layer of material of the second layer immediately above the lowest first layer including an upper first insulating material and a lower second material below the upper first insulating material, the lower second material having a composition different from that of the upper first insulating material; selecting selectively isotropically etching the first layer of material relative to the second layer of material to form void spaces in the first layer; depositing a conductive material into the trenches and into the void spaces in the first layer, the conductive material filling the void spaces in the first layer above the lowest first layer, the conductive material not completely filling the void spaces in the lowest first layer; etching the conductive material from the lowest first layer; and after etching the conductive material, depositing a conductive material into the void spaces of the lowest first layer under the lower second material in the second layer immediately above the lowest first layer, the conductive material directly electrically coupling the channel material of individual ones of the channel material strings and the conductor material of the conductor layer together.

[0009] In another aspect, the present application provides a method for forming a memory array including strings of memory cells, comprising: forming a conductor layer including a conductor material on a substrate; forming a stack including vertically alternating first and second layers above the conductor layer, the stack including laterally spaced memory blocks with horizontally elongated trenches therebetween, strings of channel material extending through the first and second layers, the material of the first layers having a composition different from that of the second layers, the lowest of the first layers being thicker than the first layers above it; a second layer of material of the second layer immediately above the lowest first layer including an upper insulating material, a lower material, and an intermediate material vertically between the upper insulating material and the lower material; the intermediate material having a composition different from that of the lower material and that of the upper insulating material; selectively isotropically etching the first layer of material relative to the second layer of material to form void spaces in the first layer; depositing a conductive material into the trenches and into the void spaces in the first layer; wherein the conductive material fills the void space in the first layer above the lowest first layer, the conductive material not completely filling the void space in the lowest first layer; selectively etching the conductive material from the lowest first layer relative to the lower material in the second layer immediately above the lowest first layer to leave the lower material under the intermediate material in the second layer immediately above the lowest first layer; after etching the conductive material, selectively etching the lower material in the second layer immediately above the lowest first layer relative to the lower surface of the intermediate material to expose the lower surface; and after etching the lower material in the second layer immediately above the lowest first layer, depositing a conductive material into the void space of the lowest first layer under the intermediate material in the second layer immediately above the lowest first layer, the conductive material directly electrically coupling the channel material of the individual ones of the channel material strings and the conductor material of the conductor layer together.

[0010] On the other hand, the present application provides a memory array including a string of memory cells, comprising: a conductor layer including a conductor material; each comprising a vertically spaced-apart memory block directly above the conductor layer, the vertical stack comprising alternating insulating layers and conductive layers, the conductive material of the lowest of the conductive layers directly abutting the conductor material of the conductor layer, and the channel material string of the memory cell extending through the insulating layer and the conductive layer; an intervening material, which is laterally between the laterally adjacent memory blocks and longitudinally along the laterally adjacent memory blocks; the conductive material in the lowest conductive layer directly abutting the channel material of individual ones of the channel material string; and the insulating layer immediately above the lowest conductive layer comprising an upper first insulating material and a lower second insulating material below the upper first insulating material, the lower second insulating material having a composition different from that of the upper first insulating material.

[0011] On the other hand, the present application provides a memory array including a string of memory cells, comprising: a conductor layer including a conductor material; each comprising a vertically spaced-apart memory block directly above the conductor layer, the vertical stack comprising alternating insulating layers and conductive layers, the conductive material of the lowest of the conductive layers directly abutting the conductor material of the conductor layer, and the channel material string of the memory cell extending through the insulating layer and the conductive layer; an intervening material that is laterally between the laterally adjacent memory blocks and longitudinally along the laterally adjacent memory blocks; and the conductive material in the lowest conductive layer directly abutting the channel material of individual ones of the channel material string, and a conductive material having a composition different from that of the conductive material being above and directly abutting the conductive material.

[0012] In yet another aspect, the present application provides a memory array comprising a string of memory cells, comprising: a conductor layer comprising a conductor material; laterally spaced memory blocks each comprising a first vertical stack directly above the conductor layer, the first vertical stack comprising alternating insulating layers and conductive layers, the conductive material of the lowest of the conductive layers directly abutting the conductive material of the conductor layer, the channel material strings of memory cells extending through the insulating and conductive layers; an intervening material laterally between and longitudinally along the laterally adjacent memory blocks; the conductive material in the lowest conductive layer directly abutting the channel material; the channel material of an individual one of the string of channel materials; and a second vertical stack transverse to the first vertical stack, the second vertical stack comprising: alternating first and second insulating layers, the lowest of the first insulating layers being thicker than the first insulating layer above it, the first insulating layer comprising a first insulating material, the second insulating layer comprising a second insulating material having a composition different from that of the first insulating layer; and the second insulating layer immediately above the lowest first insulating layer comprising an upper insulating material and a lower material below the upper insulating material, the lower material having a composition different from that of the upper insulating material. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a diagrammatic cross-sectional view of a portion of a substrate under processing according to an embodiment of the present invention and is a diagrammatic cross-sectional view through Figure 2 Intercepted by line 1-1 in.

[0014] Figure 2 It passes through Figure 1 A diagrammatic cross-sectional view taken along line 2-2 in FIG.

[0015] Figure 3-4 yes Figure 1 and 2 Magnified view of a portion of.

[0016] Figure 5-26 is in process according to some embodiments of the present invention Figure 1-4 Diagrammatic sequential cross-sectional, expanded, enlarged and / or partial views of the structure or parts thereof.

[0017] Figure 27 yes Figure 2 and 21 A diagrammatic cross-sectional view of another portion of a substrate. DETAILED DESCRIPTION

[0018] Embodiments of the present invention encompass methods for forming a memory array, such as a NAND or other memory cell array that may have at least some under-array peripheral control circuitry (e.g., under-array CMOS). Embodiments of the present invention also encompass memory arrays that are independent of the manufacturing method (e.g., NAND architecture). A first example method embodiment references Figure 1-26 described, and can be considered a "gate-last" or "replacement-gate" process, starting with Figure 1-4 .

[0019] Figure 1 and 2 A construction 10 is shown having an array or array region 12 in which vertically extending strings of transistors and / or memory cells are to be formed. Construction 10 includes a base substrate 11 having any one or more of a conductive / conductor / conductive, semiconductive / semiconductive / semiconductive, or insulating / insulator / insulating (i.e., electrically insulating in this context) material. The various materials are formed vertically on base substrate 11. The materials are formed on Figure 1-4 1. The depicted material may be positioned adjacent to, vertically inwardly of, or vertically outwardly of the depicted material. For example, other partially or fully fabricated components of the integrated circuit system may be disposed somewhere above, around, or within base substrate 11. Control and / or other peripheral circuitry for operating components within an array of vertically extending strings of memory cells (e.g., array 12) may also be fabricated, which may be completely or partially within the array or sub-array. Furthermore, multiple sub-arrays may be fabricated and operated independently, sequentially, or in other manners relative to one another. As used herein, a "sub-array" may also be considered an array.

[0020] The conductor material 17 (eg, WSi xA conductor layer 16 of conductively doped polysilicon (conductively doped polysilicon) is formed over substrate 11. Conductor layer 16 may include portions of control circuitry (e.g., peripheral under-array circuitry and / or a common source line or plate) for controlling read and write access to transistors and / or memory cells to be formed within array 12. A stack 18 comprising vertically alternating insulating layers 20* and conductive layers 22* is formed over conductor layer 16 (* is used as a suffix to encompass all such components designated with the same numerical value, which may or may not have other suffixes). An example thickness for each of layers 20* and 22* is 22 to 60 nanometers. Only a small number of layers 20* and 22* are shown, but stack 18 is more likely to include dozens, a hundred, or more layers 20* and 22*. Other circuitry, which may or may not be part of the peripheral and / or control circuitry, may be between conductor layer 16 and stack 18. For example, multiple vertically alternating layers of conductive and insulating materials of such circuitry may be below the lowest of conductive layers 22* and / or above the uppermost of conductive layers 22*. For example, one or more select gate layers (not shown) may be between conductor layer 16 and the lowest conductive layer 22*, and one or more select gate layers may be above the uppermost of conductive layers 22*. Alternatively or additionally, at least one of the depicted uppermost and lowest conductive layers 22* may be a select gate layer. Regardless, conductive layer 22* (alternatively referred to as the first layer) may not include conductive material, and insulating layer 20* (alternatively referred to as the second layer) may not include insulating material or be insulating when processed in conjunction with the "gate-last" or "replacement-gate" example method embodiments initially described herein. Example conductive layer 22* includes a first material 26 (e.g., silicon nitride), which may be fully or partially sacrificial. Example insulating layer 20* includes a second material 24 (e.g., silicon dioxide), the composition of which is different from that of first material 26 and which may be fully or partially sacrificial.

[0021] In some embodiments, the lowest first layer 22z is thicker than the first layer 22* above it, and in one such embodiment, is at least 1.5 times thicker than the first layer 22* above it. In one embodiment and as shown, the lowest first layer 22z does not directly abut the conductor material 17 of the conductor layer 16, for example, where the lowest second layer 20z is vertically located between the conductor material 17 of the conductor layer 16 and the lowest first layer 22z. Alternatively, the lowest first layer can directly abut the conductor material of the conductor layer (not shown). In one embodiment, the lowest second layer 20z directly abuts the top 19 of the conductor material 17 of the conductor layer 16. In one embodiment, the lowest second layer 20z is thinner than the second layer 20* above it. In one embodiment, the second layer 20x immediately above the lowest first layer 22z (i.e., the next higher second layer 20x) is thicker than the second layer 20* above it.

[0022] The second layer material of the second layer 20x immediately above the lowest first layer 22z (i.e., no other second layer is vertically located between the lowest first layer 22z and the second layer 20x immediately above it) includes an upper first insulating material 21 and a lower second material 23 below the upper first insulating material 21, wherein the composition of the lower second material 23 is different from the composition of the upper first insulating material 21. In one such embodiment, the lower second material 23 is thinner than the upper first insulating material 21. Regardless, the upper insulating material 21 can have the same composition as material 24. In some embodiments, the second layer material of the second layer 20x immediately above the lowest first layer 22z can be considered to include an upper insulating material 21, a lower material 27, and an intermediate material 23 vertically located between the upper insulating material 21 and the lower material 27, wherein the composition of the intermediate material 23 is different from the composition of the lower material 27 and the composition of the upper insulating material 21 (in some embodiments, the lower material 27 is optional). In some such embodiments, upper insulating material 21 and lower material 27 have the same thickness as each other. Regardless, in some embodiments, upper insulating material 21 and lower material 27 have the same composition as each other (e.g., the same composition as material 24), and in other embodiments, have different compositions from each other. In some embodiments, lower second material 23 / intermediate material 23 includes at least one of conductively doped polysilicon, non-conductively doped polysilicon, carbon-doped polysilicon, silicon nitride, undoped silicon nitride, carbon-doped silicon nitride, and a metal material.

[0023] A trench opening 25 is formed (e.g., by etching) through insulating layer 20* and conductive layer 22* to conductor layer 16. Trench opening 25 may taper radially inward as one moves deeper into stack 18 (not shown). In some embodiments, trench opening 25 may extend into conductor material 17 of conductor layer 16, as shown, or may terminate at the top (not shown). Alternatively, as an example, trench opening 25 may terminate at the top of or within the lowest insulating layer 20. Extending trench opening 25 at least into conductor material 17 of conductor layer 16 is to provide an anchoring effect for the material within trench opening 25. An etch stop material (not shown) may be within or atop conductor material 17 of conductor layer 16 to help stop etching of trench opening 25 relative to conductor layer 16, if desired. Such an etch stop material may be sacrificial or non-sacrificial.

[0024] Horizontally elongated trenches 40 are formed (e.g., by anisotropic etching) into stack 18 to form laterally spaced memory block regions 58. Trenches 40 may have respective bottoms directly against (atop or within) conductor material 17 of conductor layer 16 (as shown), or may have respective bottoms that are vertically coincident with or below the bottom of conductor layer 16 or conductor material 17 (not shown). By way of example and for simplicity only, channel openings 25 are shown arranged in groups or columns of staggered rows of four and five channel openings 25 per row, and arranged in laterally spaced memory block regions 58 that will comprise laterally spaced memory blocks 58 in the finished circuitry configuration. As used herein, "block" generally encompasses "sub-blocks." Memory block regions 58 and resulting memory blocks 58 (not shown) may be considered to be longitudinally elongated and, for example, oriented along direction 55. Any alternative existing or future-developed arrangements and configurations may be used.

[0025] Transistor channel material may be formed vertically in individual channel openings along the insulating layer and the conductive layer, thereby comprising individual strings of channel material that are directly electrically coupled to the conductive material in the conductive layer. Individual memory cells of the resulting example memory array may include a gate region (e.g., a control gate region) and a memory structure laterally positioned between the gate region and the channel material. In one such embodiment, the memory structure is formed to include a charge blocking region, a storage material (e.g., a charge storage material), and an insulating charge transfer material. The storage material (e.g., a floating gate material such as doped or undoped silicon, or a charge trapping material such as silicon nitride, metal dots, etc.) of the individual memory cells is positioned vertically along the individual charge blocking regions. The insulating charge transfer material (e.g., a bandgap-engineered structure comprising a nitrogen-containing material (e.g., silicon nitride) sandwiched between two insulating oxides (e.g., silicon dioxide)) is positioned laterally between the channel material and the storage material.

[0026] Figure 1-4 One embodiment is shown in which charge blocking material 30, storage material 32, and charge transfer material 34 have been formed vertically along insulating layer 20* and conductive layer 22* in individual channel openings 25. Transistor materials 30, 32, and 34 (e.g., memory cell materials) can be formed, for example, by depositing their respective thin layers over stack 18 and within individual openings 25 and then planarizing such transistor materials back to at least the top surface of stack 18.

[0027] Channel material 36 is also formed vertically along insulating layer 20* and conductive layer 22* in channel opening 25, thereby including individual operative channel material strings 53 in channel opening 25. Channel material 36 can be considered to have a lowest surface 71. In one embodiment, memory cell materials (e.g., 30, 32, and 34) are located along strings of channel material 53, and a second layer of material (e.g., 24) is located horizontally between immediately adjacent strings of channel material 53. Due to the proportions, materials 30, 32, 34, and 36 are located horizontally between adjacent strings of channel material 53. Figure 1 and 2 37. Example channel material 36 comprises a suitably doped crystalline semiconductor material, such as one or more of silicon, germanium, and so-called III / V semiconductor materials (e.g., GaAs, InP, GaP, and GaN). An example thickness of each of materials 30, 32, 34, and 36 is 25 to 100 angstroms. A stamp etch may be performed to remove materials 30, 32, and 34 from a base (not shown) of channel opening 25 to expose conductor layer 16 such that channel material 36 directly abuts conductor material 17 of conductor layer 16. Such a stamp etch may occur individually with respect to each of materials 30, 32, and 34 (as shown), or may occur only with respect to some of the materials (not shown). Alternatively, and by way of example only, no stamp etch may be performed, and channel material 36 may be directly electrically coupled to conductor material 17 of conductor layer 16 solely through a separate conductive interconnect (not shown). Channel opening 25 is shown as including a radially central solid dielectric material 38 (e.g., spin-on dielectric, silicon dioxide, and / or silicon nitride). Alternatively, and by way of example only, the radially central portion within channel opening 25 may include void space (not shown) and / or be free of solid material (not shown).

[0028] refer to Figure 5 and 6 , first layer material 26 (not shown) is selectively etched isotropically relative to second layer material 24 (and in one embodiment, as shown, selectively relative to materials 17, 21, 23, and 27) to form void space 35 in first layer 22* (e.g., using liquid or vapor H3PO4 as the primary etchant, where material 26 is silicon nitride and the other exposed materials include one or more oxides or polysilicon). Some of lower second material 23 / intermediate material 23 may thereby be laterally etched (not shown).

[0029] refer to Figure 7 and 8 , conductive material 48 is deposited into trench 40 and into void space 35 in first layer 22*. Conductive material 48 fills void space 35 in first layer 22* above lowest first layer 22z and does not completely fill void space 35 in lowest first layer 22z.

[0030] refer to Figure 9-11 , conductive material 48 is etched (e.g., isotropically) from the lowest first layer 22z. This can be performed selectively relative to at least the uppermost portion of conductor material 17 of conductor layer 16 and relative to materials 21, 23, and 27, as shown. Furthermore, such etching can remove any remaining conductive material 48 that has been located in trench 40 by previous processing (as shown). Furthermore, some lateral recessing of material 48 and / or 23 can be performed relative to the sidewalls of trench 40 defined by material 24 (not shown). In one embodiment in which lower material 27 is present, as shown, etching conductive material 48 from the lowest first layer 22z is performed selectively relative to lower material 27 in the next higher second layer 20x, leaving lower material 27 beneath intermediate material 23 in the next higher second layer 20x immediately above the lowest first layer 22z. Practitioners can select an appropriate isotropic etching chemistry to selectively etch conductive material 48 relative to material 24. As examples, the W conductive material 48 may be isotropically etched selectively with respect to the SiO 2 material 24 and the polysilicon material 23 using a mixture of ammonia and hydrogen peroxide or a mixture of sulfuric acid and hydrogen peroxide.

[0031] Figure 12-15 1 and 2. Subsequent processing is shown wherein, in one embodiment, material 30 (e.g., silicon dioxide), material 32 (e.g., silicon nitride), and material 34 (e.g., silicon dioxide or a combination of silicon dioxide and silicon nitride) are etched to expose sidewalls 41 of channel material 36 of channel material string 53. Regardless, in one embodiment wherein lower material 27 is present, as shown Figure 11 As shown in FIG, the lower material 27 (at Figure 12-14 1 ) is selectively etched relative to a lower surface 31 of the intermediate material 23 to expose the lower surface. As an example, consider an embodiment in which material 23 is polysilicon, materials 21, 24 and 27 are silicon dioxide, and memory cell materials 30, 32 and 34 are each one or more of a silicon dioxide and a silicon nitride layer. In such an example, the depicted construction can be produced by using modified or different chemistries to selectively etch silicon dioxide and silicon nitride sequentially relative to each other. As an example, a 100:1 (by volume) solution of water to HF will selectively etch silicon dioxide relative to silicon nitride, while a 1000:1 (by volume) solution of water to HF will selectively etch silicon nitride relative to silicon dioxide. Thus, in such an example, such etching chemistries can be used in an alternating manner to achieve the desired effect of etching the silicon dioxide and silicon nitride sequentially relative to each other. Figure 14 and 15 The example configuration shown. Practitioners can select other chemistries to etch other different materials where desired. Figure 14 and 15The lower material 27 (not shown) is shown as Figure 12 , but in some embodiments it may not be removed until later.

[0032] refer to Figure 16 and 17 In one embodiment, conductive / conductive material 42 is deposited into void space 35 of lowermost first layer 22z below (and, in one embodiment, directly above) lower second material 23 / intermediate material 23 in next higher second layer 20x, directly against exposed sidewalls 41 of channel material 36 of channel material string 53, and directly against uppermost surface 43 of conductor material 17 of conductor layer 16. For example, if none of conductor material 17 is subsequently etched, uppermost surface 43 may be the same as top 19. This is merely one example whereby conductive material 42 is deposited to directly electrically couple channel material 36 of individual channel material strings 53 and conductor material 17 of conductor layer 16 together (e.g., via channel material sidewalls 41). In one embodiment, at least the uppermost portion of conductor material 17 of conductor layer 16 has the same composition as conductive material 42 (e.g., both are conductively doped polysilicon). Alternatively, the conductive material 42 has a composition that is different from the composition of at least the uppermost portion of the conductor material 17 of the conductor layer 16 .

[0033] refer to Figure 18 and 19 , conductive material 42 has been removed from trench 40, for example, by a timed isotropic etch that may be selective with respect to materials 21, 23, 24, 48, and 17. This may cause conductive material 42 to be laterally recessed in direction 39 toward string of channel material 53, as shown. This may cause some etching of conductor material 17 upon exposure (not shown). An example etching chemistry where material 42 is conductively doped polysilicon, materials 21 and 24 are silicon dioxide, material 23 is silicon nitride, and material 48 is W is tetramethylammonium hydroxide. If material 23 has the same composition as conductive material 24, material 23 may also be laterally etched thereby (not shown).

[0034] refer to Figure 20-26, intervening material 57 is formed to be laterally between and longitudinally along laterally adjacent memory blocks 58. Intervening material 57 can provide lateral electrical isolation (insulation) between laterally adjacent memory blocks. This can include one or more of insulating, semiconducting, and conductive materials, and in any case can facilitate shorting of conductive layers 22* to each other in the finished circuitry configuration. Example insulating materials are one or more of SiO2, Si3N4, Al2O3, and undoped polysilicon. Intervening material 57 can include through-array vias (TAVs) and is not shown. By way of example only, intervening material 57 is shown as a composite including insulating material 67 (e.g., silicon nitride), insulating material 68 (e.g., silicon dioxide), and insulating material 69 (e.g., undoped polysilicon). In one embodiment, as shown, intervening material 57 includes insulating material (e.g., 67) directly against conductor material 17 of conductor layer 16, and in one embodiment, the insulating material (e.g., 67) of intervening material 57 extends laterally in direction 39 toward channel material string 53 to be directly below what is now the lowest second layer 20x, which will eventually become the finished circuit system structure. Additionally and regardless, in one embodiment, as shown, in the finished circuit system structure, conductive material 48 of first layer 22* above lowest first layer 22z extends laterally into insulating material (e.g., 67) of intervening material 57 in direction 70 away from channel material string 53.

[0035] In one embodiment, as shown, the lowest surface 71 ( Figure 22 and 25 ) never directly abuts any of the conductor materials 17 in the conductor layer 16 .

[0036] Conductive material 48 forms vertically extending strings 49 of individual conductive lines 29 (eg, word lines) and individual transistors and / or memory cells 56. The transistors and / or memory cells 56 are generally located at Figure 26 Indicated in brackets, and some Figure 21 、 23 , 24 and 25 are indicated by dashed outlines, where the transistors and / or memory cells 56 are substantially annular or ring-shaped in the depicted example. Alternatively, the transistors and / or memory cells 56 may not completely surround the individual channel openings 25, such that each channel opening 25 may have two or more vertically extending strings 49 (e.g., multiple transistors and / or memory cells surround the individual channel openings in a separate conductive layer, where there may be multiple word lines per channel opening in the separate conductive layer and not shown). The conductive material 48 can be seen as having ends 50 ( Figure 26). In the depicted embodiment, control gate region 52 includes individual portions of individual conductive lines 29. Materials 30, 32, and 34 can be considered as memory structures 65 located laterally between control gate region 52 and channel material 36. In one embodiment, as shown with respect to the example "gate-last" processing, conductive material 48 of conductive layer 22 is formed after forming channel opening 25 and / or trench 40. As mentioned above, the lowest first layer 22z can be a select gate layer (e.g., in which no operational memory cells are formed).

[0037] A charge blocking region (e.g., charge blocking material 30) is located between the storage material 32 and the respective control gate regions 52. The charge blocking member may have the following functions in a memory cell: in programming mode, the charge blocking member may prevent charge carriers from escaping from the storage material (e.g., floating gate material, charge trapping material, etc.) toward the control gate, and in erase mode, the charge blocking member may prevent charge carriers from flowing from the control gate into the charge storage material. Thus, the charge blocking member may be used to block charge migration between the control gate region and the storage material of each memory cell. As shown, the example charge blocking region comprises insulator material 30. By way of further example, the charge blocking region may comprise a laterally (e.g., radially) outer portion of the storage material (e.g., material 32), where such storage material is insulating (e.g., in the absence of any dissimilar composition material between the insulating storage material 32 and the conductive material 48). Regardless, as an additional example, the intersection of the storage material and the conductive material of the control gate may be sufficient to function as a charge blocking region in the absence of any separate composition insulator material 30. Furthermore, the intersection of conductive material 48 and material 30 (if present), in conjunction with insulator material 30, can act as a charge blocking region and, alternatively or additionally, can act as a lateral outer region of insulating storage material, such as silicon nitride material 32. Example material 30 is one or more of hafnium silicon oxide and silicon dioxide.

[0038] Any other properties or aspects as shown and / or described herein with respect to other embodiments may be used in the embodiments shown and described with reference to the above embodiments.

[0039] Alternative embodiment configurations may be generated from the method embodiments described above or in other ways. Regardless, embodiments of the present invention encompass memory arrays regardless of the method of manufacture. However, such memory arrays may have any of the properties described herein in the method embodiments. Similarly, the method embodiments described above may incorporate, form, and / or have any of the properties described with respect to the device embodiments.

[0040] In one embodiment, a memory array (e.g., 12) including strings (e.g., 49) of memory cells (e.g., 56) includes a conductor layer (e.g., 16) comprising a conductive material (e.g., 17). The memory array includes laterally spaced memory blocks (e.g., 58), each comprising a vertical stack (e.g., 18) directly above the conductor layer. The vertical stack comprises alternating insulating layers (e.g., 20*) and conductive layers (e.g., 22*). The conductive material (e.g., 42) of the lowest conductive layer (e.g., 22z) directly abuts the conductive material of the conductor layer. In one such embodiment, the lowest conductive layer is thicker than the conductive layer above it. The string of channel material (e.g., 53) of the memory cell (e.g., 56) extends through the insulating and conductive layers. Intervening material (e.g., 57) is laterally between and longitudinally along laterally adjacent memory blocks. The conductive material in the lowest conductive layer directly abuts the channel material (e.g., 36) of each of the strings of channel material. The insulating layer immediately above the lowest conductive layer (e.g., 20x) comprises an upper first insulating material (e.g., 21) and a lower second insulating material (e.g., 23) below the upper first insulating material, wherein the lower second insulating material has a composition different from that of the upper first insulating material. In one such embodiment, the upper first insulating material comprises silicon dioxide, and the lower second insulating material comprises undoped polysilicon. In one such embodiment, the upper first insulating material comprises silicon dioxide, and the lower second insulating material comprises silicon nitride. In one such embodiment, the lower second insulating material is thinner than the upper first insulating material. In one such embodiment, the lowest conductive layer is thicker than the conductive layer above it. In one such embodiment, the intervening material comprises an insulating material directly abutting the conductive material of the conductive layer. In one such embodiment, the conductive material directly abuts the sidewalls (e.g., 41) of the channel material of the individual channel material strings. Any other properties or aspects as shown and / or described herein with respect to other embodiments may be used.

[0041] In one embodiment, a memory array (e.g., 12) including strings (e.g., 49) of memory cells (e.g., 56) includes a conductor layer (e.g., 16) comprising a conductive material (e.g., 17). The memory array includes laterally spaced memory blocks (e.g., 58), each comprising a vertical stack (e.g., 18) directly above the conductor layer. The vertical stack comprises alternating insulating layers (e.g., 20*) and conductive layers (e.g., 22*). The conductive material (e.g., 42) of the lowest conductive layer (e.g., 22z) directly abuts the conductive material of the conductor layer. In one such embodiment, the lowest conductive layer is thicker than the conductive layer above it. The string of channel material (e.g., 53) of the memory cell (e.g., 56) extends through the insulating and conductive layers. Intervening material (e.g., 57) is laterally between and longitudinally along laterally adjacent memory blocks. The conductive material in the lowest conductive layer directly abuts the channel material (e.g., 36) of each of the strings of channel material. A conductive material (e.g., 23) having a composition different from that of the conductive material is over and directly against the conductive material. In one such embodiment, the conductive material comprises conductively doped polysilicon, and the conductive material comprises a metallic material. Any other properties or aspects shown and / or described herein with respect to other embodiments may be used.

[0042] When materials 23 and 42 have the same composition in a finished construction, they may be indistinguishable from one another (e.g., their interfaces may be indistinguishable). Regardless, in one embodiment, a memory array (e.g., 12) including strings (e.g., 49) of memory cells (e.g., 56) includes a conductor layer (e.g., 16) comprising a conductive material (e.g., 17). The memory array includes laterally spaced memory blocks (e.g., 58) each comprising a first vertical stack (e.g., 18) directly above the conductive layer, the first vertical stack comprising alternating insulating layers (e.g., 20*) and conductive layers (e.g., 22*). The conductive material (e.g., 42) of the lowest conductive layer (e.g., 22z) directly abuts the conductive material of the conductive layer. The string (e.g., 53) of the channel material of the memory cell (e.g., 56) extends through the insulating and conductive layers. Intervening material (e.g., 57) is laterally located between and longitudinally along the laterally adjacent memory blocks. The conductive material in the lowest conductive layer directly abuts the channel material (e.g., 36) of an individual of the string of channel materials. The second vertical stack is positioned transversely to the first vertical stack. For example, Figure 27 Deemed to include Figure 20-261 and 2. The second insulating layer 75 is a portion of the illustrated construction and additionally has a second vertical stack 75 positioned transversely to the first vertical stack 18. Such a second vertical stack includes alternating first insulating layers (e.g., 22*) and second insulating layers (e.g., 20*), wherein the lowest of the first insulating layers (e.g., 22z) is thicker than the first insulating layer above it. The first insulating layers include a first insulating material (e.g., 26), and the second insulating layers include a second insulating material (e.g., 21, 24, and / or 27) having a composition different from the composition of the first insulating layers. The second insulating layer (e.g., 22x) immediately above the lowest first insulating layer includes an upper insulating material (e.g., 21) and a lower material (e.g., 23) below the upper insulating material, wherein the lower material has a composition different from the composition of the upper insulating material. In one such embodiment, the second insulating layer immediately above the lowest first insulating layer includes a lowest insulating material below the lower material. For example, and by way of example only, Figure 27 Such a structure 10 (and Figure 2 and 20 -26 configuration) can produce regions in which trenches 40 are not formed, whereby material 26 is not removed therefrom. Any other attributes or aspects shown and / or described herein with respect to other embodiments may be used.

[0043] The above-described processing or construction can be considered with respect to an array of components formed as or within a single stack or stack of such components, the stack or stack being above or as part of an underlying base substrate (although a single stack / stack may have multiple layers). Control and / or other peripheral circuitry for operating or accessing such components within the array may also be formed anywhere as part of the finished construction, and in some embodiments may be below the array (e.g., below-array CMOS). Regardless, one or more additional such stacks / stacks may be provided or fabricated above and / or below the stacks / stacks shown or described above. Furthermore, the array of components in different stacks / stacks may be the same or different relative to each other, and different stacks / stacks may have the same thickness or different thicknesses relative to each other. Intervening structures may be provided between vertically adjacent stacks / stacks (e.g., additional circuitry and / or dielectric layers). Furthermore, different stacks / stacks may be electrically coupled relative to each other. Multiple stacks / stacks may be fabricated separately and sequentially (e.g., one on top of another), or two or more stacks / stacks may be fabricated substantially simultaneously.

[0044] The assemblies and structures discussed above can be used in integrated circuits / circuitry systems and can be incorporated into electronic systems. Such electronic systems can be used, for example, in memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and can include multi-layer, multi-chip modules. The electronic system can be any of a wide range of systems, such as cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting, vehicles, clocks, televisions, cellular phones, personal computers, automobiles, industrial control systems, aircraft, and the like.

[0045] As used herein, unless otherwise indicated, "vertical," "higher," "upper," "lower," "top," "above," "bottom," "above," "below," "below," "under," "upward," and "downward" generally refer to a vertical direction. "Horizontal" refers to a general direction along the surface of the primary substrate (i.e., within 10 degrees) and may be relative to the direction in which the substrate is handled during manufacturing, and vertical is a direction generally orthogonal thereto. Reference to "exactly horizontal" is to a direction along the surface of the primary substrate (i.e., no degree deviation therefrom) and may be relative to the direction in which the substrate is handled during manufacturing. Furthermore, as used herein, "vertical" and "horizontal" are generally perpendicular directions relative to each other and have nothing to do with the orientation of the substrate in three-dimensional space. Additionally, "extending vertically" and "extending vertically" refer to a direction that is tilted at least 45° from exactly horizontal. Furthermore, "extending vertically," "extending vertically," "extending horizontally," "extending horizontally," and similar terms relative to a field effect transistor are references to the orientation of the channel length of the transistor along which current flows between the source / drain regions during operation. For bipolar junction transistors, "vertically extending," "vertically extending," "horizontally extending," "horizontally extending," and the like refer to the orientation of the substrate length along which current flows between the emitter and the collector in operation. In some embodiments, any component, feature, and / or region that extends vertically extends vertically or within 10° of vertical.

[0046] Furthermore, "directly above," "directly below," and "directly beneath" require at least some lateral overlap (i.e., horizontally) of the two recited areas / materials / components relative to each other. Furthermore, the use of "above" without a preceding "directly" requires only that some portion of the recited area / material / component that is above another recited area / material / component is vertically outboard of the other recited area / material / component (i.e., regardless of whether there is any lateral overlap between the two recited areas / materials / components). Similarly, the use of "below" and "beneath" without a preceding "directly" requires only that some portion of the recited area / material / component that is below / beneath the other recited area / material / component is vertically inboard of the other recited area / material / component (i.e., regardless of whether there is any lateral overlap between the two recited areas / materials / components).

[0047] Any of the materials, regions, and structures described herein may be uniform or non-uniform, and in any case may be continuous or discontinuous over any overlying material. When one or more example compositions are provided for any material, the material may comprise, consist essentially of, or consist of the one or more compositions. Furthermore, unless otherwise indicated, each material may be formed using any suitable current or future developed technique, with atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation being examples.

[0048] In addition, "thickness" (preceded by a non-directional adjective) used alone is defined as the average straight-line distance perpendicular to the nearest surface of a given material or region having a different composition from the nearest adjacent material or region. In addition, the various materials or regions described herein may have a substantially constant thickness or a variable thickness. If having a variable thickness, then unless otherwise indicated, the thickness refers to the average thickness, and such materials or regions will have a minimum thickness and a maximum thickness due to the variable thickness. As used herein, "different composition" only requires that those parts of the two materials or regions discussed that can directly abut each other are chemically and / or physically different, such as when the materials or regions are non-homogeneous. If the two stated materials or regions are not directly abutting each other, then in the case of such materials or regions being non-homogeneous, "different composition" only requires that those parts of the two stated materials or regions that are closest to each other are chemically and / or physically different. Herein, a material, region or structure is "directly abutting" another material, region or structure when the stated materials, regions or structures are in at least some physical contact with each other. In contrast, "over," "on," "adjacent," "along," and "against" without being preceded by "directly" encompass "directly against" as well as configurations in which intervening materials, regions, or structures result in no physical, touching contact of the stated materials, regions, or structures relative to one another.

[0049] As used herein, regions, materials, and components are "electrically coupled" relative to one another if, during normal operation, electrical current can flow continuously from one region, material, and component to another, primarily through the movement of subatomic positive and / or negative charges when sufficient subatomic positive and / or negative charges are generated. Another electronic component may be between and electrically coupled to the region, material, and components. In contrast, when region, material, and components are referred to as being "directly electrically coupled," there are no intervening electronic components (e.g., no diodes, transistors, resistors, transducers, switches, fuses, etc.) between the directly electrically coupled region, material, and components.

[0050] Any use of "row" and "column" herein is for convenience in distinguishing one series or orientation of features from another series or orientation of features, and components have been or may be formed along such "rows" and "columns." "Row" and "column" are used synonymously with respect to any series of regions, components, and / or features, regardless of function. Regardless, rows can be straight and / or curved and / or parallel and / or non-parallel relative to each other, as can columns. Furthermore, rows and columns can intersect at 90° relative to each other, or at one or more other angles (i.e., other than straight angles).

[0051] The components of any of the conductive / conductor / conductive materials herein may be metallic materials and / or conductively doped semiconductive / semiconductive / semiconductive materials. "Metallic material" refers to any one or combination of elemental metals, any mixture or alloy of two or more elemental metals, and any one or more conductive metal compounds.

[0052] As used herein, "selective" with respect to etching, removal, deposition, and / or formation is one in which a stated material is acted upon at a ratio of at least 2:1 by volume relative to another stated material. Additionally, any use of selectively depositing, selectively growing, or selectively forming is one in which one material is deposited, grown, or formed relative to another stated material or materials at a ratio of at least 2:1 by volume relative to at least the first 75 angstroms.

[0053] Unless otherwise indicated, the use of "or" herein includes either or both.

[0054] in conclusion

[0055] In some embodiments, a method for forming a memory array including strings of memory cells includes forming a conductive layer including conductive material on a substrate. A stack including vertically alternating first and second layers is formed above the conductive layer. The stack includes laterally spaced memory blocks with horizontally elongated trenches therebetween. Strings of channel material extend through the first and second layers. The material of the first layer has a composition different from that of the second layer. The lowest of the first layers is thicker than the first layer above it. The second layer of material immediately above the lowest first layer includes an upper first insulating material and a lower second material below the upper first insulating material. The lower second material has a composition different from that of the upper first insulating material. The first layer of material is selectively and isotropically etched relative to the second layer of material to form void spaces in the first layer. Conductive material is deposited into the trenches and into the void spaces in the first layer. The conductive material fills the void spaces in the first layer above the lowest first layer. The conductive material does not completely fill the void spaces in the lowest first layer. The conductive material is etched from the lowest first layer. After the conductive material is etched, a conductive material is deposited into the void space of the lowest first layer below the lower second material in the second layer immediately above the lowest first layer. The conductive material directly electrically couples the channel material of individual ones of the channel material strings and the conductor material of the conductor layer.

[0056] In some embodiments, a method for forming a memory array including strings of memory cells includes forming a conductive layer including conductive material on a substrate. A stack including vertically alternating first and second layers is formed above the conductive layer. The stack includes laterally spaced memory blocks with horizontally elongated trenches therebetween. Strings of channel material extend through the first and second layers. The material of the first layer has a composition different from that of the second layer. The lowest of the first layers is thicker than the first layer above it. The second layer of material immediately above the lowest first layer includes an upper insulating material, a lower material, and an intermediate material vertically located between the upper insulating material and the lower material. The intermediate material has a composition different from that of the lower material and that of the upper insulating material. The first layer of material is selectively and isotropically etched relative to the second layer of material to form a void space in the first layer. Conductive material is deposited into the trenches and into the void space in the first layer. The conductive material fills the void space in the first layer above the lowest first layer. The conductive material does not completely fill the void space in the lowest first layer. The conductive material is selectively etched from the lowest first layer relative to the lower material in the second layer immediately above the lowest first layer, leaving the lower material beneath the intermediate material in the second layer immediately above the lowest first layer. Following the conductive material etching, the lower material in the second layer immediately above the lowest first layer is selectively etched relative to a lower surface of the intermediate material to expose the lower surface. Following the etching of the lower material in the second layer immediately above the lowest first layer, conductive material is deposited beneath the intermediate material in the second layer immediately above the lowest first layer into the void space of the lowest first layer. The conductive material directly electrically couples the channel material of individual ones of the channel material strings and the conductor material of the conductor layer.

[0057] In some embodiments, a memory array including strings of memory cells includes a conductor layer comprising a conductive material. The memory array includes laterally spaced memory blocks, each comprising a vertical stack directly above the conductive layer, the vertical stack comprising alternating insulating and conductive layers. The conductive material of the lowest conductive layer directly abuts the conductive material of the conductive layer. Strings of channel material of memory cells extend through the insulating and conductive layers. Intervening material is laterally located between and longitudinally along laterally adjacent memory blocks. The conductive material in the lowest conductive layer directly abuts the channel material of individual ones of the strings of channel material. The insulating layer immediately above the lowest conductive layer comprises an upper first insulating material and a lower second insulating material below the upper first insulating material. The lower second insulating material has a composition different from that of the upper first insulating material.

[0058] In some embodiments, a memory array including strings of memory cells includes a conductor layer comprising a conductive material. The memory array includes laterally spaced memory blocks, each comprising a vertical stack directly above the conductive layer, the vertical stack comprising alternating insulating and conductive layers. The conductive material of the lowest conductive layer directly abuts the conductive material of the conductive layer. Strings of channel material of memory cells extend through the insulating and conductive layers. Intervening material is laterally between and longitudinally along laterally adjacent memory blocks. The conductive material in the lowest conductive layer directly abuts the channel material of individual ones of the strings of channel material. Conductive material has a composition different from that of the conductive material and is above and directly abuts the conductive material.

[0059] In some embodiments, a memory array including strings of memory cells includes a conductor layer comprising a conductive material. The memory array includes laterally spaced memory blocks, each comprising a first vertical stack directly above the conductive layer, the first vertical stack comprising alternating insulating and conductive layers. The conductive material of the lowest conductive layer directly abuts the conductive material of the conductive layer. Strings of channel material of memory cells extend through the insulating and conductive layers. Intervening material is laterally located between and longitudinally along laterally adjacent memory blocks. The conductive material in the lowest conductive layer directly abuts the channel material of individual strings of channel material. A second vertical stack is transverse to the first vertical stack. The second vertical stack comprises alternating first and second insulating layers. The lowest first insulating layer is thicker than the first insulating layer above it. The first insulating layer comprises a first insulating material. The second insulating layer comprises a second insulating material having a different composition than the first insulating layer. The second insulating layer immediately above the lowest first insulating layer comprises an upper insulating material and a lower material below the upper insulating material. The lower material has a composition different from a composition of the upper insulating material.

[0060] As specified, the subject matter disclosed herein has been described in language more or less specific with respect to structural and methodological features. However, it should be understood that the claims are not limited to the specific features shown and described, as the components disclosed herein include example embodiments. Accordingly, the claims are to be given the full scope as written and should be appropriately interpreted in accordance with the doctrine of equivalents.

Claims

1. A method for forming a memory array including a string of memory cells, comprising: forming a conductor layer including a conductor material on a substrate; forming a stack comprising vertically alternating first and second layers over the conductor layer, the stack comprising laterally spaced apart memory blocks having horizontally elongated trenches therebetween, strings of channel material extending through the first and second layers, the material of the first layers having a composition different from that of the second layers, the lowest of the first layers being thicker than the first layers above it, the second layer of material of the second layer immediately above the lowest first layer comprising an upper first insulating material and a lower second material below the upper first insulating material, the lower second material having a composition different from that of the upper first insulating material; selectively isotropically etching the first layer of material relative to the second layer of material to form void spaces in the first layer; depositing a conductive material into the trench and into the void space in the first layer, the conductive material filling the void space in the first layer above the lowest first layer, the conductive material not completely filling the void space in the lowest first layer; etching said conductive material from said lowermost first layer; as well as After etching the conductive material, a conductive material is deposited into the void space of the lowest first layer under the lower second material in the second layer immediately above the lowest first layer, the conductive material directly electrically coupling the channel material of individual ones of the channel material strings and the conductor material of the conductor layer. 2 . The method of claim 1 , comprising etching away all of the conductive material in the trenches prior to depositing the conductive material. 3 . The method of claim 1 , wherein at least an uppermost portion of the conductor material of the conductor layer has the same composition as the electrically conductive material. The method of claim 1 , wherein the lowermost first layer is at least 1.5 times thicker than the first layer above it. 5 . The method of claim 1 , wherein the lowermost first layer does not directly abut the conductor material of the conductor layer during the isotropic etching. 6 . The method of claim 5 , wherein a lowermost of the second layers is vertically located between the conductor material of the conductor layer and the lowermost first layer during the isotropic etching. The method of claim 6 , wherein the lowermost second layer is thinner than the second layer thereover during the isotropic etching. 8 . The method of claim 7 , wherein the second layer immediately above the lowermost first layer is thicker than the second layer thereabove during the isotropic etching.

9. The method of claim 1, wherein the conductive material has a different composition than at least an uppermost portion of the conductor material of the conductor layer.

10. The method of claim 1, wherein a lowermost surface of the channel material of the string of channel materials never directly abuts any of the conductor materials in the conductor layer.

11. The method of claim 1, wherein the conductive material in the void spaces of the lowermost first layer directly abuts against sidewalls of the channel material of the string of channel materials.

12. The method of claim 1, wherein the conductive material in the void spaces of the lowermost first layer directly abuts an uppermost surface of the conductive material of the conductor layer.

13. The method of claim 1, wherein the lower second material comprises at least one of: conductively doped polysilicon, conductively non-doped polysilicon, carbon-doped polysilicon, silicon nitride, undoped silicon nitride, carbon-doped silicon nitride, and a metal material.

14. The method of claim 1, wherein the lower second material is thinner than the upper first insulating material.

15. The method of claim 1, wherein the conductive material directly abuts the lower second material in the second layer immediately above the lowermost first layer.

16. A method for forming a memory array comprising strings of memory cells, comprising: forming a conductor layer including a conductor material on a substrate; forming a stack comprising vertically alternating first and second layers above the conductor layer, the stack comprising laterally spaced apart memory blocks with horizontally elongated trenches therebetween, strings of channel material extending through the first and second layers, the material of the first layers having a composition different from that of the second layers, the lowest of the first layers being thicker than the first layers above it; the second layer material of the second layer immediately above the lowest first layer comprising an upper insulating material, a lower material, and an intermediate material vertically between the upper insulating material and the lower material; the intermediate material having a composition different from that of the lower material and that of the upper insulating material; selectively isotropically etching the first layer of material relative to the second layer of material to form void spaces in the first layer; depositing a conductive material into the trench and into the void space in the first layer, the conductive material filling the void space in the first layer above the lowest first layer, the conductive material not completely filling the void space in the lowest first layer; selectively etching the conductive material from the lowest first layer relative to the underlying material in the second layer immediately above the lowest first layer to leave the underlying material beneath the intermediate material in the second layer immediately above the lowest first layer; After etching the conductive material, selectively etching the lower material in the second layer immediately above the lowermost first layer relative to a lower surface of the intermediate material to expose the lower surface; as well as After etching the lower material in the second layer immediately above the lowest first layer, a conductive material is deposited into the void space of the lowest first layer under the intermediate material in the second layer immediately above the lowest first layer, the conductive material directly electrically coupling the channel material of the individual ones of the channel material strings and the conductor material of the conductor layer.

17. The method of claim 16, wherein the intermediate material comprises at least one of: conductively doped polysilicon, conductively non-doped polysilicon, carbon-doped polysilicon, silicon nitride, undoped silicon nitride, carbon-doped silicon nitride, and a metal material.

18. The method of claim 16, wherein the intermediate material is thinner than the upper insulating material and the lower material.

19. The method of claim 16, wherein the conductive material directly abuts the intermediate material in the second layer immediately above the lowermost first layer.

20. A memory array comprising a memory cell string, comprising: a conductor layer comprising a conductor material; each comprising a vertical stack of laterally spaced-apart memory blocks directly above the conductor layer, the vertical stack comprising alternating insulating and conductive layers, the conductive material of the lowest of the conductive layers directly abutting the conductive material of the conductive layers, the strings of channel material of the memory cells extending through the insulating and conductive layers; an intervening material laterally disposed between the laterally adjacent memory blocks and longitudinally along the laterally adjacent memory blocks; the conductive material in the lowest conductive layer directly abuts the channel material of individual ones of the strings of channel materials; as well as The insulating layer immediately above the lowest conductive layer includes an upper first insulating material and a lower second insulating material below the upper first insulating material, the lower second insulating material having a composition different from that of the upper first insulating material.

21. The memory array of claim 20 wherein the upper first insulating material comprises silicon dioxide and the lower second insulating material comprises undoped polysilicon.

22. The memory array of claim 20 wherein the upper first insulating material comprises silicon dioxide and the lower second insulating material comprises silicon nitride.

23. The memory array of claim 20, wherein the lower second insulating material is thinner than the upper first insulating material.

24. The memory array of claim 20 wherein the lowermost of the conductive layers is thicker than the conductive layers above it.

25. The memory array of claim 20 wherein the intervening material comprises an insulating material directly against the conductor material of the conductor layer.

26. The memory array of claim 20 wherein the conductive material is directly against sidewalls of the channel material of the individual strings of channel material.

27. A memory array comprising a string of memory cells, comprising: a conductor layer comprising a conductor material; each comprising a vertical stack of laterally spaced-apart memory blocks directly above the conductor layer, the vertical stack comprising alternating insulating and conductive layers, the conductive material of the lowest of the conductive layers directly abutting the conductive material of the conductive layers, the strings of channel material of the memory cells extending through the insulating and conductive layers; an intervening material laterally disposed between the laterally adjacent memory blocks and longitudinally along the laterally adjacent memory blocks; as well as The conductive material in the lowest conductive layer is directly against the channel material of individual ones of the strings of channel materials, and a conductive material having a composition different from that of the conductive material is above and directly against the conductive material.

28. The memory array of claim 27 wherein the conductive material is directly against sidewalls of the channel material of the individual strings of channel material.

29. The memory array of claim 27 wherein the conductive material comprises conductively doped polysilicon and the conductive material comprises a metallic material.

30. The memory array of claim 27 wherein the lowermost of the conductive layers is thicker than the conductive layers above it.

31. The memory array of claim 27 wherein the intervening material comprises an insulating material directly against the conductor material of the conductor layer.

32. A memory array comprising a string of memory cells, comprising: a conductor layer comprising a conductor material; laterally spaced memory blocks each comprising a first vertical stack directly above the conductor layer, the first vertical stack comprising alternating insulating and conductive layers, the conductive material of the lowest of the conductive layers directly abutting the conductive material of the conductor layers, strings of channel material of memory cells extending through the insulating and conductive layers; an intervening material laterally disposed between the laterally adjacent memory blocks and longitudinally along the laterally adjacent memory blocks; the conductive material in the lowest conductive layer directly abuts the channel material of individual ones of the strings of channel materials; as well as A second vertical stack transverse to the first vertical stack, the second vertical stack comprising: alternating first and second insulating layers, a lowest of the first insulating layers being thicker than the first insulating layer thereover, the first insulating layers comprising a first insulating material, and the second insulating layers comprising a second insulating material having a composition different from that of the first insulating layer; as well as The second insulating layer immediately above the lowermost first insulating layer includes an upper insulating material and a lower material below the upper insulating material, the lower material having a composition different from that of the upper insulating material.

33. The memory array of claim 32 wherein the lower material is thinner than the upper insulating material.

34. The memory array of claim 32 wherein the upper insulating material is silicon dioxide.

35. The memory array of claim 32 wherein the lower material is polysilicon.

36. The memory array of claim 32 wherein the upper insulating material is silicon dioxide and the lower material is polysilicon.

37. The memory array of claim 32 wherein the second insulating layer immediately above the lowest first insulating layer comprises a lowest insulating material under the lower material.

38. The memory array of claim 37 wherein the lower material is thinner than each of the upper insulating material and the lower insulating material.

39. The memory array of claim 38, wherein the upper insulating material and the lower insulating material have the same thickness as each other.

40. The memory array of claim 37 wherein the upper insulating material and the lowermost insulating material have the same composition as one another.

41. The memory array of claim 40 wherein the composition is silicon dioxide and the lower material comprises polysilicon.

42. The memory array of claim 32 wherein the lowermost of the conductive layers is thicker than the conductive layers above it.

43. The memory array of claim 32 wherein the intervening material comprises an insulating material directly against the conductor material of the conductor layer.

44. The memory array of claim 32 wherein the conductive material is directly against sidewalls of the channel material of the individual strings of channel material.

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