Storage repair system based on polymorphic BISR chain

Abstract

The invention relates to the technical field of integrated circuit repair, in particular to a storage repair system based on a polymorphic BISR chain, the system divides storage units in a chip into a plurality of repair modules, and a plurality of off-chip registers contained in each repair module form a plurality of first off-chip register chains; when the memory unit in the chip is repaired, the memory unit can be repaired at the same time through the plurality of first off-chip register chains, so that the repair duration of the memory unit of the chip is determined according to the maximum chain length of each first off-chip register chain; compared with the prior art that the repair duration of the chip storage unit is determined according to the sum of the chain lengths of all the off-chip registers, the storage repair time is greatly shortened, the storage repair efficiency is further improved, in the storage repair process, the storage unit can adopt a parallel repair mode or a serial repair mode, and the repair efficiency is improved. Storage repair can be compatible with memory cells of different repair types.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit repair, and particularly to a memory repair system based on a multi-morphology BISR chain. Background Art

[0002] With the rapid development of emerging applications such as artificial intelligence, big data, and the Internet of Things, as well as the continuous progress of the process technology, the amount of data that a chip needs to process is increasing, and the proportion of on-chip memory is also increasing. The increasing chip area and the number of on-chip memories lead to an increase in the defect probability of on-chip memories, which in turn brings challenges to chip yield and cost. In order to improve chip yield, a repair solution needs to be provided for on-chip memories, including adding a redundant array to the on-chip memory, adding a built-in self-analysis circuit corresponding to the on-chip memory, and adding a non-volatile memory to store and read the repair data analyzed by the built-in self-analysis circuit.

[0003] When the built-in self-test of the memory detects a defect inside the memory, if the memory has a redundant array, the built-in self-analysis circuit will analyze appropriate repair data to select an appropriate redundant array to replace the defective row or column, thereby achieving the repair of the memory. After the built-in self-analysis circuit finishes analyzing, the analyzed repair data will be updated to the built-in self-repair register chain (BISR chain). The BISR chain is connected to the controller of the on-chip non-volatile memory. By shifting the BISR chain, the repair data can be directly or compressed and stored in the on-chip non-volatile memory.

[0004] In the prior art, there are usually two types of BISR registers, external and internal, corresponding to two types of memory repairs, parallel and serial, respectively. The process of updating the repair data from the built-in self-analysis circuit to the external BISR register is relatively simple and fast, and can be completed through parallel sampling between registers, generally only requiring one to two clock cycles. However, updating the repair data from the built-in self-analysis circuit to the internal BISR register requires serial shifting, and the number of required clock cycles is proportional to the length of the internal BISR chain.

[0005] However, when adopting a parallel strategy to repair the memory, the external BISR register requires relatively complex control logic. In the case of a large number of on-chip memories, each on-chip memory needs to correspond to an external BISR register and control logic, which in turn leads to an excessive chip area. In order to simplify the control logic, the prior art usually adopts a serial strategy to repair the memory. However, in the case of a large number of on-chip memories, the length of the formed BISR chain will also be relatively long, resulting in a long time-consuming for memory repair, and even causing the system power-on time of the chip to fail to meet the expected requirements.

[0006] Therefore, how to improve the efficiency of memory repair in chips has become an urgent problem to be solved. Summary of the Invention

[0007] In view of the above technical problems, the technical solution adopted by the present invention is as follows: A storage repair system based on a multi-form BISR chain, the system includes: M repair modules, a non-volatile memory, and a control unit corresponding to the non-volatile memory, where each repair module corresponds to a first selector, and M is a positive integer.

[0008] The m-th repair module a m contains N(m) storage units. In a m the i-th storage unit b i corresponds to an off-chip register c i and b i also corresponds to a repair type, the repair type includes a serial type and a parallel type. When the repair type corresponding to b i is the serial type, b i includes an on-chip register d i , m is an integer in the range of [1, M], and i is an integer in the range of [1, N(m)].

[0009] In a m when b i is of the parallel type, b i is connected to c i .

[0010] When b i is of the serial type, if i = 1, then the input ends of c i , d i are both connected to the output end of the first selector corresponding to a m . If i ≠ 1, then the input ends of c i , d i are both connected to the output end of c i-1 .

[0011] When b i is of the parallel type, if i = 1, then the input end of c i is connected to the output end of the first selector corresponding to a m . If i ≠ 1, then the input end of c i is connected to the output end of c i-1 .

[0012] When i = N(m), if m ≠ M, then the output end of c i is respectively connected to the first input end of the first selector corresponding to a m and a m+1is connected to the second input terminal of the corresponding first selector. If m = M, then c i The output terminals of are respectively connected to a m The first input terminal of the corresponding first selector and the input terminal of the control unit are connected.

[0013] When m = 1, a m The second input terminal of the corresponding first selector is connected to the output terminal of the control unit.

[0014] When each first selector selects the first input terminal, a plurality of off-chip registers respectively included in M repair modules form M first off-chip register chains, and the first off-chip register chains are used to support the repair of each storage unit in the corresponding repair module.

[0015] Compared with the prior art, the present invention has obvious beneficial effects. By means of the above technical solutions, a storage repair system based on a multi-form BISR chain provided by the present invention can achieve considerable technical progressiveness and practicality, and has wide utilization value in the industry. It has at least the following beneficial effects: The present invention divides the storage units in the chip into multiple repair modules, and a plurality of off-chip registers respectively included in each repair module form multiple first off-chip register chains. When repairing the storage units in the chip, the multiple first off-chip register chains can be used for repair simultaneously, so that the repair duration of the chip storage units is determined according to the maximum chain length of each first off-chip register chain. Compared with the prior art in which the repair duration of the chip storage units is determined according to the sum of the chain lengths of all off-chip registers, the storage repair time is greatly reduced, thereby improving the storage repair efficiency. Moreover, during the storage repair process, the storage units can adopt a parallel repair mode or a serial repair mode, and the storage repair can be compatible with storage units of different repair types. Description of the Drawings

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0017] Figure 1 It is a schematic structural diagram of a storage repair system based on a multi-form BISR chain provided by Embodiment 1 of the present invention; Figure 2 It is a schematic flow diagram of a storage repair system based on multiple parallel BISR chains provided by Embodiment 2 of the present invention; Figure 3Schematic diagram of a storage repair system based on multiple parallel BISR chains provided in the second embodiment of the present invention. Detailed implementation manners

[0018] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts fall within the protection scope of the present invention.

[0019] The first embodiment of the present invention provides a storage repair system based on multi-form BISR chains. The system includes: M repair modules, a non-volatile memory, and a control unit corresponding to the non-volatile memory, where each repair module corresponds to a first selector, and M is a positive integer; The mth repair module a m contains N(m) storage units. In a m the ith storage unit b i corresponds to an off-chip register c i and b i also corresponds to a repair type, and the repair type includes a serial type and a parallel type. When the repair type corresponding to b i is the serial type, b i includes an on-chip register d i , m is an integer within the range of [1, M], and i is an integer within the range of [1, N(m)]; In a m when b i is of the parallel type, b i is connected to c i ; When b i is of the serial type, if i = 1, the input ends of c i and d i are both connected to the output end of the first selector corresponding to a m . If i ≠ 1, the input ends of c i and d i are both connected to the output end of c i-1 ; When b i is of the parallel type, if i = 1, the input end of c i is connected to the output end of the first selector corresponding to a m . If i ≠ 1, the input end of c i is connected to the output end of c i-1 ; When i = N(m), if m ≠ M, then c iThe output terminals are respectively connected to a m The first input terminal of the corresponding first selector and a m+1 The second input terminal of the corresponding first selector. If m = M, then c i The output terminals are respectively connected to a m The first input terminal of the corresponding first selector and the input terminal of the control unit; When m = 1, a m The second input terminal of the corresponding first selector is connected to the output terminal of the control unit; When each first selector selects the first input terminal, several off-chip registers respectively included in M repair modules form M first off-chip register chains, and the first off-chip register chains are used to support the repair of each storage unit in the corresponding repair module.

[0020] Among them, the repair module can be controlled by a Memory Built In Self Test Controller (MBIST Controller). Each repair module can respectively correspond to a memory built-in self-test controller. The repair module includes several storage units. The storage units included in any repair module can be configured by the implementer. The non-volatile memory can use an electrically fusible link (eFuse). Different from on-chip registers and off-chip registers, the non-volatile memory can retain data without an external power supply. The control unit corresponding to the non-volatile memory can be used to configure the gating situation of each first selector, and configure the clock frequency to further configure the serial shift time of each repair module.

[0021] Specifically, the number of storage units included in each repair module can be different, and the repair types of the included storage units can be different. The repair types can include serial types and parallel types. The on-chip registers can be used to support the repair of serial-type storage units.

[0022] In a m When b i Is of the parallel type, b i Is connected to c i C i Directly sends the repair data to b through the port of b i i .

[0023] When b i Is of the serial type, d i Needs to obtain the repair data in the way of bit-by-bit serial input. If i = 1, then c i And d i The input terminals of are both connected to a mis connected to the output terminal of the corresponding first selector, that is, the input terminals of c1 and d1 are both connected to the output terminal of the first selector corresponding to the repair module to which they belong. If i ≠ 1, then c i , d i 's input terminals are both connected to the output terminal of c i-1 , that is, c i , d i 's input terminals are both connected to the output terminal of the previous external register.

[0024] When b i is of parallel type, if i = 1, then the input terminal of c i is connected to the output terminal of the first selector corresponding to a m , that is, the input terminal of c1 is connected to the output terminal of the first selector corresponding to the repair module to which it belongs. If i ≠ 1, then the input terminal of c i is connected to the output terminal of c i-1 , that is, c i 's input terminals are both connected to the output terminal of the previous external register, thus forming the external register chain of a m .

[0025] When i = N(m), it means that c i is the last storage unit of the repair module to which it belongs. If m ≠ M, then the output terminal of c i is respectively connected to the first input terminal of the first selector corresponding to a m and the second input terminal of the first selector corresponding to a m+1 , that is, when c i the repair module to which it belongs is not the last repair module, c i is respectively connected to the first input terminal of the first selector corresponding to the repair module to which it belongs and the second input terminal of the first selector corresponding to the next repair module. If m = M, then the output terminal of c i is respectively connected to the first input terminal of the first selector corresponding to a m and the input terminal of the control unit, that is, when c i the repair module to which it belongs is the last repair module, c i is respectively connected to the first input terminal of the first selector corresponding to the repair module to which it belongs and the input terminal of the control unit of the non-volatile memory.

[0026] When m = 1, it means that a m is the first repair module, and the second input terminal of the first selector corresponding to a m is connected to the output terminal of the control unit, that is, the second input terminal of the first selector corresponding to the first repair module is connected to the output terminal of the control unit.

[0027] When each first selector selects the first input terminal, a number of off-chip registers respectively included in M repair modules form M first off-chip register chains. The identifier of the first input terminal can be 1. Correspondingly, the identifier of the second input terminal can be 0. When each first selector selects the first input terminal, for any one repair module, the input terminal of the first storage unit in this repair module receives the data from the output terminal of the last storage unit in this repair module. That is, this repair module only serially transmits the repair data in the off-chip registers it includes, without the repair data outside the repair module. Furthermore, each repair module corresponds to a first off-chip register chain respectively.

[0028] See Figure 1 , which is a schematic structural diagram of a storage repair system based on a multi-form BISR chain provided in the first embodiment of the present invention. This schematic structural diagram takes two repair modules, with each repair module including three storage units as an example. For the convenience of distinguishing and describing, the two repair modules are respectively marked as repair module 1 and repair module 2. The three storage units included in repair module 1 are respectively storage unit 11, storage unit 12, and storage unit 13 and the off-chip registers corresponding to each storage unit respectively. Storage unit 12 is of the parallel type, and storage unit 11 and storage unit 13 are of the serial type. The three storage units included in repair module 2 are respectively storage unit 21, storage unit 22, and storage unit 23 and the off-chip registers corresponding to each storage unit respectively. Storage unit 22 is of the serial type, and storage unit 21 and storage unit 23 are of the parallel type.

[0029] The first off-chip register chain is used to support the repair of each storage unit in the corresponding repair module. When it is necessary to repair the storage unit in the repair module, a single repair module performs serial transmission of repair data through its corresponding first off-chip register chain. It can be known that if the sum of the chain lengths of the off-chip registers included in the first off-chip register chain is L, then after this repair module performs serial shift by L bits through its corresponding first off-chip register chain, the serial transmission can be completed.

[0030] In a specific implementation manner, the on-chip register includes an input terminal, a clock port, and a reset port. The reset port is used to initialize the state of the corresponding on-chip register; When repairing any one storage unit of the serial type, the on-chip register corresponding to this storage unit receives a clock signal through the clock port and performs bit-by-bit transmission of repair data according to the clock signal.

[0031] Among them, the clock port can be used to receive the clock signal provided by the control unit of the non-volatile memory, so as to control the shift time interval of the on-chip register.

[0032] In a specific implementation manner, when bi When it is of the parallel type, b i includes an input terminal; When repairing any storage unit of the parallel type, the storage unit receives repair data through the input terminal it includes.

[0033] Among them, the storage unit of the parallel type can directly receive repair data through the input terminal without serial shifting in. That is, the bit width of the input terminal of the storage unit of the parallel type is the same as the sum of the bit widths of the repair data and the repair enable flag bit.

[0034] In a specific implementation manner, the on-chip register further includes an output terminal, and each storage unit of the serial type corresponds to a second selector; Correspondingly, when b i is of the serial type, if i≠1 and the repair type corresponding to b i-1 is of the serial type, then the input terminals of c i and d i are both connected to the output terminal of the second selector corresponding to b i-1 ; When b i is of the parallel type, if i≠1 and the repair type corresponding to b i-1 is of the serial type, then the input terminal of c i is connected to the output terminal of the second selector corresponding to b i-1 ; When b i is of the serial type, the output terminal of c i is connected to the first input terminal of the second selector corresponding to b i , and the output terminal of d i is connected to the second input terminal of the second selector corresponding to b i .

[0035] Among them, the second selector can be used to select and pass the output of the off-chip register and the output of the second on-chip register.

[0036] In a specific implementation manner, when a path test of the on-chip register is required, each second selector is selected to pass the second input terminal.

[0037] Among them, in the test stage, in order to enable the path of the on-chip register to be tested, in this embodiment, each second selector is selected to pass the second input terminal. That is, through the second selector, the output of the on-chip register of the current storage unit is sent to the next storage unit instead of the output of the off-chip register of the current storage unit, so that the effectiveness of each on-chip register can be determined in the path test stage.

[0038] In a specific embodiment, when each first selector selects the second input terminal, all off-chip registers form a second off-chip register chain, and the second off-chip register chain is used to support the non-volatile memory to record the repair data of each off-chip register.

[0039] Among them, when each first selector selects the second input terminal, all off-chip registers included in each repair module form a second off-chip register chain. When the non-volatile memory has not stored the repair data of each storage unit, through serial shifting of this second off-chip register chain, the repair data of each off-chip register is directly or compressed and stored in the non-volatile memory.

[0040] In a specific embodiment, each storage unit corresponds to a built-in self-test circuit, and the built-in self-test circuit is used to analyze the repair data of the corresponding storage unit and send the repair data of the corresponding storage unit to the off-chip register of the corresponding storage unit; For any one repair module, according to the total bit width of the repair data of each storage unit included in this repair module, determine the chain length corresponding to this repair module; According to the chain length corresponding to this repair module and a preset clock cycle, determine the repair time of this repair module; Take the maximum value of the repair times of each repair module as the overall time; According to the overall time and a preset time threshold, determine the repair module to which each storage unit belongs.

[0041] Among them, when using the first off-chip register chain for storage unit repair, the overall time is the maximum value of the repair times of each first off-chip register chain. When the overall time is less than the preset time threshold, it can be considered that the duration of the overall storage repair meets the expectation, and the current repair module division method can be used for repair. When the overall time is greater than or equal to the preset time threshold, it can be considered that the duration of the overall storage repair exceeds the expectation, and the storage units included in the repair module need to be adjusted. The adjustment methods can include adding new repair modules and adjusting the storage units in the repair module to other repair modules. The implementer can determine the adjustment methods of each repair module according to the actual situation.

[0042] In a specific embodiment, each repair module corresponds to a shift counter; For any one repair module, determine the bit width of the shift counter corresponding to this repair module according to the chain length corresponding to this repair module; According to the bit widths of the shift counters corresponding to each repair module respectively, determine the area increase; According to the area increase and a preset increase threshold, determine the repair module to which each storage unit belongs.

[0043] Among them, when using the first off-chip register chain for storage cell repair, additional control logic needs to be added to the repair module, thereby increasing the chip area. The increase in the chip area is mainly related to the bit width of the shift counter.

[0044] When the increase in area is greater than or equal to the preset increase threshold, it can be considered that the increase in area exceeds the expectation, and the storage cells included in each repair module need to be adjusted. When the increase in area is less than the preset increase threshold, it can be considered that the increase in area meets the expectation, and the current repair module division method can be used for repair.

[0045] In one embodiment, the division method of the repair module is jointly determined according to the above overall time consumption and increase in area. If only considering the overall time consumption, obviously taking a single storage cell as a repair module has the lowest overall time consumption. If only considering the increase in area, obviously taking all storage cells as a repair module has the smallest increase in area. When the overall time consumption is less than the preset time consumption threshold and the increase in area is less than the preset increase threshold, a reasonable repair module division method can be obtained.

[0046] In the first embodiment of the present invention, the storage cells in the chip are divided into multiple repair modules, and several off-chip registers respectively included in each repair module form multiple first off-chip register chains. When repairing the storage cells in the chip, multiple first off-chip register chains can be used for repair simultaneously, so that the repair duration of the chip storage cells is determined according to the maximum chain length of each first off-chip register chain. Compared with the prior art where the repair duration of the chip storage cells is determined according to the sum of the chain lengths of all off-chip registers, the storage repair time is greatly reduced, thereby improving the storage repair efficiency. Moreover, during the storage repair process, the storage cells can adopt a parallel repair method or a serial repair method, and the storage repair can be compatible with storage cells of different repair types.

[0047] The second embodiment of the present invention provides a storage repair system based on multiple parallel BISR chains. The system includes: P repair modules and their corresponding target register chains, a non-volatile memory, and its corresponding control unit, where the non-volatile memory stores compressed repair data respectively corresponding to each target register chain, and P is a positive integer; For any target register chain, the target register chain determines the status information of the target register chain according to its own repair status and read status. The repair status is initially the unrepaired status, and the read status is initially the request read status; When there is no current register chain, the control unit determines the current register chain from each target register chain whose status information meets the conditions; When there is a current register chain, the control unit sends the compression repair data corresponding to the current register chain from the non-volatile memory to the current register chain in a per-sub-data manner, where the compression repair data includes a number of sub-data, and the sub-data belongs to uncompressed sub-data or compressed sub-data; If the current register chain receives uncompressed sub-data, it continues to read the next sub-data; If the current register chain receives compressed sub-data, it stops reading the next sub-data, decompresses the latest received compressed sub-data, determines that the reading state of the current register chain is the stop reading state, and changes the current register chain to the target register chain; For any target register chain, if the target register chain finishes decompressing the latest received compressed sub-data, it determines that the reading state of the target register chain is the request reading state; If the target register chain receives all the sub-data in the compression repair data corresponding to the target register chain and the latest received compressed data is decompressed, it determines that the repair state of the target register chain is the repaired state; When the repair states corresponding to all the target register chains are the repaired states respectively, the repair of the P repair modules is completed.

[0048] Among them, the target register chain is used to support the repair of each storage unit in the corresponding repair module. When it is necessary to repair the storage unit in the repair module, a single repair module performs serial transmission of repair data through its corresponding target register chain. In this embodiment, the target register chain is stored in the non-volatile memory in a compressed form, which is manifested as compression repair data. The repair data is binary data. When any data bit in the repair data is 1, it means that the array corresponding to the data bit needs to be repaired. When any data bit in the repair data is 0, it means that the array corresponding to the data bit does not need to be repaired. In this embodiment, the compression method is specifically as follows: send the repair data to the non-volatile memory bit by bit. If the current data bit is 1, send the current data bit as uncompressed sub-data to the non-volatile memory. If the current data bit is 0, count the number of consecutive 0 data bits, and send the counting result as compressed sub-data to the non-volatile memory. Then, for W consecutive 0 data bits, only compressed sub-data with a width of log2W bits is required to be stored in the non-volatile memory, effectively saving the storage space of the non-volatile memory. And since usually the number of faulty arrays in the chip will not be too large, otherwise it will be regarded as a defective chip, so the compression method of this embodiment can usually achieve a high compression rate.

[0049] See Figure 2, which is a schematic flowchart of a storage repair system based on multiple parallel BISR chains provided in the second embodiment of the present invention, where Y represents meeting the corresponding conditions and N represents not meeting the corresponding conditions.

[0050] Specifically, when the current register chain receives the compressed sub-data, it is necessary to decompress the compressed sub-data by decrementing the counter. It can be seen that for the compressed sub-data with a width of log2W bits, it takes W clock cycles to complete the decompression. During these W clock cycles for decompression, the current register chain will not continue to receive sub-data. Therefore, in order to improve the repair efficiency in this embodiment, when the current register chain decompresses the latest received compressed sub-data, the current register chain is changed to the target register chain. After the change, there will be a situation where the current register chain does not exist, and it is necessary for the control unit to determine a new current register chain from each target register chain whose status information meets the conditions. When the target register chain corresponding to the previous current register chain is in the decompression process, it cannot be determined as the current register chain again.

[0051] In a specific implementation manner, the status information includes a busy state and an idle state; The target register chain determines the status information of the target register chain according to its own repair status and read status, including: If the repair status of the target register chain is the unrepaired state and the read status of the target register chain is the request read status, then determine that the status information of the target register chain is the busy state; Otherwise, determine that the status information of the target register chain is the idle state.

[0052] Among them, the busy state can represent that the corresponding target register chain needs to read the corresponding compressed repair data from the non-volatile memory, and the idle state can represent that the corresponding target register chain does not need to read the corresponding compressed repair data from the non-volatile memory.

[0053] Specifically, when the repair status of any target register chain is the unrepaired state and the read status of the target register chain is the stop read status, the status information of the target register chain is the idle state.

[0054] When the repair status of any target register chain is the repaired state, the status information of the target register chain is also the idle state.

[0055] In a specific implementation manner, when there is no current register chain, the control unit determines the current register chain from each target register chain whose status information meets the conditions, including: When there is no current register chain, the control unit determines the current register chain from each target register chain whose status information is the busy state.

[0056] Among them, since the busy state can indicate that the corresponding target register chain needs to read the corresponding compressed repair data from the non-volatile memory, the current register chain is determined from each target register chain with the state information being the busy state.

[0057] In a specific implementation manner, when there is no current register chain, the control unit determines the current register chain from each target register chain with the state information being the busy state, including: When there is no current register chain, the control unit arbitrates a target register chain from each target register chain with the state information being the busy state according to a preset priority as the current register chain.

[0058] Among them, since all target register chains need to be repaired when the repair is completed, there is no need to set a special priority. In this embodiment, the preset priority order can be set according to the identifier of the target register chain, that is, the first target register chain has the highest priority, and the last target register chain has the lowest priority.

[0059] It should be noted that the implementer can select other arbitration methods according to the actual situation, such as polling arbitration, etc. No matter which arbitration method is used to determine the current register chain, it is within the protection scope of this embodiment.

[0060] In a specific implementation manner, the p-th repair module f p contains S(p) storage units. In f p , the g-th storage unit h g corresponds to an off-chip register k g , h g also corresponds to a repair type, and the repair type includes a serial type and a parallel type. When the repair type corresponding to h g is the serial type, h g includes an on-chip register l g , p is an integer within the range of [1, P], and g is an integer within the range of [1, S(p)]; In f p , the S(p) off-chip registers in f p form the p-th target register chain. Among them, when h g is of the parallel type, k g is connected to h g ; When h g is of the serial type, if g = 1, the input ends of k g and l g are both connected to the output end of the control unit. If g ≠ 1, then k g, l g The input ends of both are connected to k g-1 's output end; When h g is of the parallel type, if g = 1, then k g 's input end is connected to the output end of the control unit, if g ≠ 1, then k g 's input end is connected to k g-1 's output end; When g = S(p), k g 's output end is connected to the input end of the control unit.

[0061] Among them, each repair module can be controlled by the control unit. The repair module includes several storage units. The storage units included in any repair module can be configured by the implementer. The non-volatile memory can use an electrically fusible link (eFuse). Different from on-chip registers and off-chip registers, the non-volatile memory can maintain data without an external power supply. The control unit corresponding to the non-volatile memory can also be used to configure the clock frequency and thus configure the serial shift time of each repair module.

[0062] Specifically, the number of storage units included in each repair module can be different, and the repair types of the included storage units can be different. The repair types can include serial type and parallel type. The on-chip register can be used to support the repair of serial-type storage units.

[0063] In f p when h g is of the parallel type, k g is connected to h g , and k g directly sends the repair data to h g through the port of h g . When h g is of the serial type, l g needs to obtain the repair data by the way of bit-by-bit serial input.

[0064] See Figure 3, which is a schematic structural diagram of a storage repair system based on multiple parallel BISR chains provided in the second embodiment of the present invention. This schematic structural diagram takes two repair modules, with each repair module containing three storage units as an example. For ease of distinction and description, the two repair modules are respectively marked as repair module 3 and repair module 4. The three storage units included in repair module 3 are respectively storage unit 31, storage unit 32, and storage unit 33, and the off-chip registers corresponding to each storage unit. Storage unit 32 is of the parallel type, and storage unit 31 and storage unit 33 are of the serial type. The three storage units included in repair module 4 are respectively storage unit 41, storage unit 42, and storage unit 43, and the off-chip registers corresponding to each storage unit. Storage unit 42 is of the serial type, and storage unit 41 and storage unit 43 are of the parallel type.

[0065] In a specific implementation manner, the on-chip register includes an input end, a clock port, and a reset port. The reset port is used to initialize the state of the corresponding on-chip register. When repairing any serial-type storage unit, the on-chip register corresponding to this storage unit receives a clock signal through the clock port and performs bit-by-bit transmission of repair data according to the clock signal.

[0066] Among them, the clock port can be used to receive the clock signal provided by the control unit of the non-volatile memory, so as to control the shift time interval of the on-chip register.

[0067] In a specific implementation manner, when h g is of the parallel type, h g includes an input end; When repairing any parallel-type storage unit, this storage unit receives repair data through the input end it includes.

[0068] Among them, the parallel-type storage unit can directly receive repair data through the input end without performing shift serial input. That is, the bit width of the input end of the parallel-type storage unit is the same as the sum of the bit widths of the repair data and the repair enable flag bit.

[0069] In a specific implementation manner, the on-chip register further includes an output end, and each serial-type storage unit corresponds to a second selector; Correspondingly, when h g is of the serial type, if g≠1 and the repair type corresponding to h g-1 is of the serial type, then the input ends of k g and l g are both connected to the output end of the second selector corresponding to h g-1 ; When h gWhen it is of the parallel type, if g ≠ 1 and h g-1 The corresponding repair type is of the serial type, then k g The input end of is connected to the output end of the second selector corresponding to h g-1 ; When h g is of the serial type, the output end of k g is connected to the first input end of the second selector corresponding to h g , and the output end of l g is connected to the second input end of the second selector corresponding to h g .

[0070] Among them, the second selector can be used to select the output of the off-chip register and the output of the on-chip register. When the second selector selects the second input end, the path test of the on-chip register can be performed, that is, the output of the on-chip register of the current storage unit is sent to the next storage unit through the second selector, rather than the output of the off-chip register of the current storage unit, so that the effectiveness of each on-chip register can be determined during the path test stage.

[0071] It should be noted that the multi-form BISR chain provided in the above-mentioned Embodiment 1 and the multiple parallel BISR chains provided in Embodiment 2 can exist in an MBIST repair system at the same time. For example, the target register chain in Embodiment 2 can include multiple repair sub-modules, and each repair sub-module corresponds to a first off-chip register chain respectively.

[0072] In this Embodiment 2, status information is set for each target register chain, so that the control unit can determine the current register chain according to the status information of each target register chain, read the corresponding compressed repair data in the non-volatile memory from the current register chain, and when the current register chain needs to decompress the received compressed sub-data, change the current register chain, so that multiple target register chains can read the compressed repair data in parallel. Compared with the situation in the prior art where multiple register chains are used and one register chain needs to wait until the repair is completed before another register chain can be repaired, the storage repair efficiency can be effectively improved.

[0073] Although some specific embodiments of the present invention have been described in detail by way of examples, those skilled in the art should understand that the above examples are only for illustration and not for limiting the scope of the present invention. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of the present invention. The scope disclosed by the present invention is defined by the appended claims.

Claims

1. A storage repair system based on a multi - form BISR chain, characterized in that, The system includes: M repair modules, a non-volatile memory, and a control unit corresponding to the non-volatile memory, where each repair module corresponds to a first selector, and M is a positive integer; The m-th repair module a m contains N(m) storage units. In a m , the i-th storage unit b i corresponds to an off-chip register c i . b i also corresponds to a repair type, and the repair type includes a serial type and a parallel type. When the repair type corresponding to b i is the serial type, b i includes an on-chip register d i , where m is an integer in the range of [1, M], and i is an integer in the range of [1, N(m)]. In a m when b i is of the parallel type, b i is connected to c i ; When b i is of the serial type, if i = 1, then the input ends of c i and d i are both connected to the output end of the first selector corresponding to a m . If i ≠ 1, then the input ends of c i and d i are both connected to the output end of c i-1 . When b i is of the parallel type, if i = 1, then the input end of c i is connected to the output end of the first selector corresponding to a m ; if i ≠ 1, then the input end of c i is connected to the output end of c i-1 ; When i = N(m), if m ≠ M, then the output terminals of c i are respectively connected to the first input terminal of the first selector corresponding to a m and the second input terminal of the first selector corresponding to a m+1 If m = M, then the output terminals of c i are respectively connected to the first input terminal of the first selector corresponding to a m and the input terminal of the control unit; When m = 1, a m The second input terminal of the corresponding first selector is connected to the output terminal of the control unit; When all the first selectors are gated to the first input terminal, M first off-chip register chains are formed by a number of off-chip registers included in the M repair modules respectively, and the first off-chip register chains are used to support the repair of each storage unit in the corresponding repair module.

2. The storage repair system based on the polymorphic BISR chain according to claim 1, characterized in that, The on-chip register includes an input terminal, a clock port, and a reset port, and the reset port is used to initialize the state of the corresponding on-chip register; When repairing any serial-type storage unit, the on-chip register corresponding to the storage unit receives a clock signal through the clock port and transmits the repair data bit by bit according to the clock signal.

3. The storage repair system based on the polymorphic BISR chain according to claim 1, characterized in that, When b i is of the parallel type, b i includes an input end; When repairing any parallel-type storage unit, the storage unit receives repair data through the input terminal included therein.

4. The storage repair system based on the multi-morphological BISR chain according to claim 2, wherein, The on-chip register further includes an output terminal, and each serial-type storage unit corresponds to a second selector respectively; Accordingly, when b i is of the serial type, if i≠1 and b i-1 corresponding repair type is of the serial type, then c i , d i input ends of are both connected to the output end of the second selector corresponding to b i-1 ; When b i is of the parallel type, if i ≠ 1 and b i-1 corresponds to a repair type of the serial type, then the input end of c i is connected to the output end of the second selector corresponding to b i-1 ; When b i is of serial type, the output terminal of c i is connected to the first input terminal of the second selector corresponding to b i , and the output terminal of d i is connected to the second input terminal of the second selector corresponding to b i .

5. The storage repair system based on the polymorphic BISR chain according to claim 4, wherein When on-chip register path testing is required, all the second selectors are gated to the second input terminal.

6. The storage repair system based on the multi-morphological BISR chain according to claim 1, characterized in that, When all the first selectors are gated to the second input terminal, a second off-chip register chain is formed by all the off-chip registers, and the second off-chip register chain is used to support the non-volatile memory to record the repair data of each off-chip register.

7. The storage repair system based on the polymorphic BISR chain according to claim 1, wherein Each storage unit corresponds to a built-in self-analysis circuit, and the built-in self-analysis circuit is used to analyze the repair data of the corresponding storage unit and send the repair data of the corresponding storage unit to the off-chip register of the corresponding storage unit; For any repair module, the chain length corresponding to the repair module is determined according to the total bit width of the repair data of each storage unit included in the repair module; According to the chain length corresponding to the repair module and a preset clock cycle, the repair time of the repair module is determined; The maximum value among the repair times of each repair module is used as the overall time; According to the overall time and a preset time threshold, the repair module to which each storage unit belongs is determined.

8. The storage repair system based on the polymorphic BISR chain according to claim 7, wherein Each repair module corresponds to a shift counter respectively; For any repair module, the bit width of the shift counter corresponding to the repair module is determined according to the chain length corresponding to the repair module; According to the bit widths of the shift counters corresponding to each repair module respectively, the area increase amount is determined; According to the area increase amount and a preset increase amount threshold, the repair module to which each storage unit belongs is determined.

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