Light emitting device including flip chip light emitting diode

Abstract

A light emitting device including a flip chip light emitting diode is disclosed, the flip chip light emitting diode comprising: a plurality of semiconductor layers, including a first semiconductor layer and a second semiconductor layer, a light emitting active region being arranged between the first semiconductor layer and the second semiconductor layer; a multilayer reflector, arranged close to the plurality of semiconductor layers, including a metal reflector layer and a dielectric reflector layer, wherein the dielectric reflector layer is arranged between the metal reflector layer and the plurality of semiconductor layers; a passivation layer, arranged between the metal reflector layer and a first electrical contact and a second electrical contact; and a first array of conductive micro contacts, extending through the passivation layer and providing electrical communication between the first electrical contact and the first semiconductor layer; a second array of conductive micro contacts, extending through the passivation layer and providing electrical communication between the second electrical contact and the second semiconductor layer; a barrier layer, comprising a plurality of metals arranged between the metal reflector layer and the passivation layer; the plurality of semiconductor layers forming a mesa.

Description

[0001] This application is a divisional application of patent application No. 2016800703748, with invention name “LOW OPTICAL LOSS FLIP CHIP SOLID-STATE LIGHTING DEVICE”, which entered the national stage on May 31, 2018, and has an international application number of PCT / US2016 / 054372 with an international application date of September 29, 2016. The entire contents of the application are incorporated herein by reference.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This application claims priority to U.S. Provisional Patent Application No. 62 / 235,908, filed on October 1, 2015, which is hereby incorporated by reference in its entirety as if fully set forth herein. Technical Field

[0004] The present disclosure relates to solid-state lighting devices including light emitting diodes, including embodiments directed to a solid-state light emitting device having a highly reflective reflector and embodiments incorporating luminescent materials. Background Art

[0005] The use of solid-state light emitters, such as light emitting diodes (LEDs), is growing in both consumer and commercial applications. Advances in LED technology have resulted in highly efficient and mechanically robust light sources with long service lives. Accordingly, modern LEDs have been able to support a wide variety of new display applications and are increasingly being used in general lighting applications, often replacing incandescent and fluorescent light sources.

[0006] An LED is a solid-state device that converts electrical energy into light and generally includes one or more active layers (or active regions) of semiconductor material arranged between oppositely doped n-type and p-type layers. When a bias is applied across the doped layers, holes and electrons are injected into the one or more active layers where they recombine to produce emission such as visible light or ultraviolet emission. For example, the active region can be made of silicon carbide, gallium nitride, gallium phosphide, aluminum nitride, and / or gallium arsenide-based materials and / or organic semiconductor materials. Photons generated by the active region are emitted in all directions.

[0007] Generally, it is desirable to operate an LED at the highest light emission efficiency, which can be measured by emission intensity related to output power (e.g., in lumens per watt). A practical goal of enhancing emission efficiency is to maximize the extraction of light emitted through the active area in the desired direction of light transmission. Light extraction and external quantum efficiency of LEDs are limited by a variety of factors, including internal reflections. According to the well-understood extrapolation of Snell's law, photons that reach the surface (interface) between the surface of the LED and the surrounding environment will be refracted or internally reflected. If a photon is repeatedly internally reflected, it will eventually be absorbed and never provide visible light emitted from the LED.

[0008] To increase the chances of photons escaping the LED—particularly flip-chip devices where the transparent substrate represents the exposed light emitting surface—it has been found useful to pattern, roughen, or otherwise texture the transparent substrate to provide a varying surface that increases the probability of refraction over internal reflection and thereby enhances light extraction. Exemplary (but not limiting) techniques and structures for providing surface features on the exterior surface of an LED are described in the following commonly assigned U.S. patents, which are incorporated herein by reference: U.S. Patent Nos. 7,829,906; 7,211,803; 6,888,167; 6,821,804; 6,791,119; 6,747,298; and 6,657,236. While this approach can be used, its practical use is limited to at least certain contexts. For example, mechanical approaches can introduce stresses or cause breakage of the wave material, and may also be limited in terms of location to the manufacturing sequence in which the approach is employed. Chemical (e.g., photolithography etching) methods may also be limited by the manufacturing sequence in terms of their location to avoid misalignment and / or microfeature damage during subsequent LED chip manufacturing and / or to avoid chemical incompatibilities with LED chip layers if etching is performed after chip fabrication.

[0009] Another way to improve light extraction efficiency is to provide a reflective surface that reflects the generated light so that the light can contribute to useful emission from the LED chip.LEDs have been developed with internal reflective surfaces or layers that reflect the generated light. Figure 1 1 is a schematic cross-sectional view of an LED chip 1 having an LED 2 mounted on a base 4 via a metal bonding layer 6. The LED 2 further includes a p-contact / reflector 8 between the LED 2 and the metal bonding layer 6, and the reflector 8 typically includes a metal such as silver (Ag). series, such as those commercially available from Cree, Inc. This arrangement is utilized in commercially available LEDs such as LEDs. The reflector 8 is integrated with the LED chip 1 and can cause light emitted from the active area of ​​the LED chip to be reflected back toward the base 4 toward the primary emitting surface. The reflector 8 also reflects TIR light toward the primary emitting surface that is textured in appearance. For each reflector surface, due to the reflectivity value of less than 100%, some light can be absorbed by the reflector 8. Some metals can have a reflectivity of less than 95% in the wavelength range of interest.

[0010] Additional LED chips have been developed with internal reflectors that include structures that allow electrical signals to pass through such reflectors. Such structures can include various combinations of conductive features (e.g., layers and / or vias) and insulating features (e.g., dielectrics and / or passivation layers).

[0011] In certain applications that require the addition of phosphors or other luminescent materials to solid-state lighting devices (e.g., including flip chips), there are challenges in achieving one or more of the following goals: ensuring adequate coverage of edge-emitting chip surfaces and edge boundaries (thereby avoiding leakage of uncovered emission); avoiding undesirable far-field light characteristics; and reducing light flux losses when diffuse reflective materials are applied to the submount surrounding the emitter chip.

[0012] Those skilled in the art are continually seeking improved light emitting diodes and solid-state lighting devices (including flip chips) that have reduced optical losses and provide desired lighting characteristics that overcome challenges associated with conventional lighting devices. Those skilled in the art are also continually seeking improved light emitting devices and methods that overcome challenges associated with adding phosphors or luminescent materials to solid-state lighting devices, including devices that include one or more flip chips. Summary of the invention

[0013] The present disclosure relates to solid-state lighting devices including light emitting diodes, and in a specific aspect, to devices including low optical loss flip-chip LEDs that incorporate a multilayer reflector and incorporate a light-transmitting substrate patterned along an inner surface adjacent to a semiconductor layer. The presence of the light-transmitting substrate patterned along the inner surface and the multilayer reflector allows for reduced optical losses of the flip-chip LED, while having reduced manufacturing costs and manufacturing steps. In an additional aspect, the present disclosure relates to a method for manufacturing a converted luminescent solid-state light-emitting device in which a surface of one or more emitter chips is coated with a luminescent material. In a further aspect, the present disclosure relates to a solid-state light-emitting device including an elevated emitter chip and / or a light-transmitting fillet material proximate to an edge emitting surface of the emitter chip, such as can be used to ensure adequate luminescent material coverage of the edge emitting surface and / or reduce light flux losses when diffuse reflective material is present proximate to the emitter chip.

[0014] In one aspect, a light emitting device comprises a flip chip light emitting diode (LED), the flip chip light emitting diode comprising a light transmissive substrate, a plurality of semiconductor layers, a multilayer reflector, and a passivation layer. The light transmissive substrate comprises a patterned surface, the patterned surface comprising at least one of (a) a plurality of recessed features and (b) a plurality of raised features. The plurality of semiconductor layers are adjacent to the patterned surface and comprise a first semiconductor layer containing a first type of dopant and a second semiconductor layer containing a second type of dopant, wherein a light emitting active region is arranged between the first semiconductor layer and the second semiconductor layer. The multilayer reflector is arranged close to the plurality of semiconductor layers and comprises a metal reflector layer and a dielectric reflector layer, wherein the dielectric reflector layer is arranged between the metal reflector layer and the plurality of semiconductor layers. The passivation layer is arranged between the metal reflector layer and (i) a first electrical contact and (ii) a second electrical contact, wherein the first electrical contact is arranged to be in conductive communication with the first semiconductor layer, and the second electrical contact is arranged to be in conductive communication with the second semiconductor layer.

[0015] In various embodiments, the foregoing LED may include additional features. In a particular embodiment, the light emitting device further includes: a first array of conductive microcontacts extending through the passivation layer and providing electrical communication between the first electrical contact and the first semiconductor layer; and at least one conductive path providing electrical communication between the second electrical contact and the second semiconductor layer. In a particular embodiment, at least one conductive path providing electrical communication between the second electrical contact and the second semiconductor layer includes a second array of conductive microcontacts extending through the passivation layer. In a particular embodiment, the dielectric reflector layer may include at least one of a plurality of conductive vias extending through the dielectric reflector layer and arranged to contact at least one of the first semiconductor layer and the second semiconductor layer. In a particular embodiment, the substrate may include sapphire; alternatively, the substrate may include silicon, silicon carbide, a III-nitride material (e.g., GaN), or any combination of the foregoing materials (e.g., silicon on sapphire, etc.). Other substrate materials may be used. In a particular embodiment, the first semiconductor layer is deposited on a patterned surface. In a particular embodiment, the dielectric reflector layer is arranged on the second semiconductor layer. In a particular embodiment, a central portion of the plurality of semiconductor layers forms a mesa extending in a direction away from the substrate, a peripheral portion of the plurality of semiconductor layers forms at least one recess that laterally bounds the mesa, and a portion of each of the dielectric reflector layer, the metal reflector layer, and the passivation layer extends into the at least one recess. In a particular embodiment, at least a portion of the passivation layer surrounds the multilayer reflector from the periphery and prevents exposure of the multilayer reflector. In a particular embodiment, the light emitting device further includes a barrier layer disposed between the metal reflector layer and the passivation layer, wherein at least one (or both) of the first array and the second array of conductive microcontacts extends through the barrier layer. In a particular embodiment, the light emitting device further includes a metal-containing interlayer (which may include aluminum), the metal-containing interlayer disposed in the passivation layer between the barrier layer and the first electrical contact and the second electrical contact. In a particular embodiment, the light emitting device includes at least one of the following features (a) to (c): (a) the dielectric reflector layer includes silicon dioxide, (b) the metal reflector layer includes silver, and (c) the passivation layer includes silicon nitride. In a specific embodiment, the first semiconductor layer includes an n-type material and the second semiconductor layer includes a p-type material. In a specific embodiment, the light emitting active region includes at least one Group III-nitride material or at least one Group III-phosphide material. In a specific embodiment, the light emitting active region includes a multi-quantum well region. In a specific embodiment, the light emitting device further includes a light emitting material arranged on the light-transmissive surface of the substrate. In a specific embodiment, the substrate includes a thickness of at least 120 microns, at least 150 microns, at least 170 microns, or another thickness threshold specified herein.

[0016] On the other hand, a light emitting device includes a flip chip light emitting diode (LED), the flip chip light emitting diode including a light-transmitting substrate, a plurality of semiconductor layers, a dielectric reflector layer, a metal reflector layer, a passivation layer, a first array of conductive microcontacts, and at least one conductive path. The light-transmitting substrate includes a patterned surface, the patterned surface includes at least one of (a) a plurality of recessed features and (b) a plurality of raised features. The plurality of semiconductor layers are arranged adjacent to the patterned surface and include a first semiconductor layer containing a first type of dopant and a second semiconductor layer containing a second type of dopant, wherein a light emitting active region is arranged between the first semiconductor layer and the second semiconductor layer. The dielectric reflector layer is adjacent to the second semiconductor layer and includes at least one of a plurality of conductive vias, the plurality of conductive vias extending through the dielectric reflector layer and arranged to contact at least one of the first semiconductor layer and the second semiconductor layer. The metal reflector layer is arranged on the dielectric reflector layer and arranged to contact at least one of the plurality of conductive vias. The passivation layer is arranged between the metal reflector layer and (i) the first electrical contact and (ii) the second electrical contact. The first array of electrically conductive microcontacts extends through the passivation layer and provides electrical communication between the first electrical contacts and the first semiconductor layer. The at least one electrically conductive path provides electrical communication between the second electrical contacts and the second semiconductor layer.

[0017] In various embodiments, the aforementioned LED may include additional features. In a particular embodiment, at least one conductive path providing electrical communication between the second electrical contact and the second semiconductor layer includes a second array of conductive microcontacts extending through the passivation layer. In a particular embodiment, the substrate includes sapphire; alternatively, the substrate may include silicon carbide or a group III-nitride material (e.g., GaN). In a particular embodiment, the first semiconductor layer is deposited on a patterned surface. In a particular embodiment, a dielectric reflector layer is arranged on the second semiconductor layer. In a particular embodiment, a central portion of the plurality of semiconductor layers forms a table extending in a direction away from the substrate, a peripheral portion of the plurality of semiconductor layers forms at least one recess that laterally defines the table, and a portion of each of the dielectric reflector layer, the metal reflector layer, and the passivation layer extends into at least one recess. In a particular embodiment, at least a portion of the passivation layer surrounds each of the dielectric reflector layer and the metal reflector layer from the periphery and prevents each of the dielectric reflector layer and the metal reflector layer from being exposed. In a particular embodiment, the light emitting device further includes a barrier layer disposed between the metal reflector layer and the passivation layer, wherein at least one of the first array of microcontacts and the second array of microcontacts extends through the barrier layer. In a particular embodiment, the light emitting device further includes a metal-containing interlayer (e.g., including aluminum), the metal-containing interlayer being disposed within the passivation layer between the barrier layer and (i) the first electrical contact and (ii) the second electrical contact. In a particular embodiment, the light emitting device includes one of the following features (a) to (c): (a) the dielectric reflector layer includes silicon dioxide, (b) the metal reflector layer includes silver, and (c) the passivation layer includes silicon nitride. In a particular embodiment, the first semiconductor layer includes an n-type material and the second semiconductor layer includes a p-type material. In a particular embodiment, the light emitting active region includes at least one Group III-nitride material or at least one Group III-phosphide material. In a particular embodiment, the light emitting active region includes a multi-quantum well region. In a particular embodiment, the lumiphoric material is disposed above the light-transmitting surface of the substrate. In particular embodiments, the substrate can include a thickness of at least 120 microns, at least 150 microns, at least 170 microns, or another thickness threshold specified herein.

[0018] On the other hand, a solid-state lighting device includes: a base; a solid-state emitter chip supported by the base, the solid-state emitter chip including a plurality of emission surfaces including a top emission surface and at least one edge emission surface arranged along the periphery of the top emission surface; and a light-transmitting chamfered material arranged on or above the base around the periphery of the solid-state emitter chip and arranged to contact at least one edge emission surface. The presence of the chamfered material along at least one edge emission surface can facilitate the coating (e.g., spraying) of a luminescent material (e.g., a phosphor) over at least one edge emission surface. In a specific embodiment, the solid-state lighting device further includes at least one luminescent material arranged over the top emission surface and arranged over at least a portion of the chamfered material. In a specific embodiment, the chamfered material has a maximum height proximate to at least one edge emission surface, the chamfered material includes a minimum height away from at least one edge emission surface, and the maximum height is no higher than the level of the top emission surface. In a specific embodiment, the chamfered material includes silicone and / or at least one luminescent material. As disclosed herein, in a specific embodiment, the solid-state emitter chip includes a flip chip.

[0019] On the other hand, a solid-state light emitting device includes: a submount including a base plate and a plurality of electrical contact areas; a diffuse reflective material disposed over at least a portion of the submount; at least one flip-chip light emitting diode including a p-electrode, an n-electrode, a top emitting surface, and at least one edge emitting surface disposed along a periphery of the top emitting surface; and a solder material disposed to establish contact between the p-electrode and at least one first contact area of ​​the plurality of electrical contact areas, and disposed to establish contact between the n-electrode and at least one second contact area of ​​the plurality of electrical contact areas; wherein at least one edge emitting surface is elevated to a height of at least about 15 microns, at least about 20 microns, at least about 25 microns, or at least about 30 microns above the base plate of the submount. In a specific embodiment, any one or more of the foregoing minimum heights are limited to an upper limit of not greater than about 70 microns, not greater than about 60 microns, or not greater than about 50 microns, not greater than about 40 microns, or not greater than about 30 microns. The presence of a flip chip that is significantly elevated relative to a base including a reflective material coating can reduce or minimize the probability that the reflective material coating is otherwise disposed on at least one edge emitting surface of the flip chip (and reflects the emission of at least one edge emitting surface of the flip chip). In a specific embodiment, the solid state light emitting device further includes at least one luminescent material disposed on the top emitting surface and on at least one edge emitting surface. In a specific embodiment, the solder material includes flux or solder paste (e.g., gold tin solder paste). In a specific embodiment, the solid state light emitting device further includes a light-transmitting chamfer material, which is arranged to form a chamfer in contact with at least one edge emitting surface and in contact with the base plate or the diffuse reflective material. In a specific embodiment, the chamfer includes a maximum height close to at least one edge emitting surface, the chamfer includes a minimum height away from at least one edge emitting surface, and the maximum height is not higher than the horizontal plane of the top emitting surface. In a specific embodiment, the chamfer material includes silicone and / or at least one luminescent material. In a specific embodiment, the diffuse reflective material includes titanium dioxide.

[0020] On the other hand, a method for manufacturing a solid-state light-emitting device for conversion luminescence is provided, the solid-state light-emitting device for conversion luminescence includes a solid-state emitter chip, the solid-state emitter chip includes a plurality of emitting surfaces including a top emitting surface and at least one edge emitting surface arranged along the periphery of the top emitting surface. The method includes: spraying a coating composition including at least one luminescent material on at least some of the plurality of emitting surfaces in a first direction using at least one nozzle; and spraying a coating composition including at least one luminescent material on at least some of the plurality of emitting surfaces in a second direction using at least one nozzle; wherein the first direction is different from the second direction, and at least one of the first direction and the second direction is not perpendicular to the top emitting surface. In a specific embodiment, the angle between the first direction and the top emitting surface is in the range of 10 degrees to 80 degrees. In a specific embodiment, the method further includes: diffusing a light-transmitting chamfer-forming material to contact at least one edge emitting surface and to contact a substrate located below the solid-state emitter chip, thereby generating a chamfer along at least one edge emitting surface, wherein the spraying of the coating composition including at least one luminescent material in the first direction and the second direction using at least one nozzle includes: spraying the coating composition on the chamfer. In certain embodiments, the chamfer comprises a maximum height proximate to at least one edge emitting surface, the chamfer comprises a minimum height away from at least one edge emitting surface, and the maximum height is no higher than a level of a top emitting surface. In certain embodiments, the material forming the chamfer comprises silicone and / or at least one luminescent material. In certain embodiments, the method further comprises: during said spraying of a coating composition comprising at least one luminescent material in a first direction and a second direction using at least one nozzle, causing relative movement between at least one nozzle and the solid state emitter chip. As disclosed herein, in certain embodiments, the solid state emitter chip comprises a flip chip.

[0021] On the other hand, a method for manufacturing a solid-state light-emitting device for conversion luminescence is provided, the solid-state light-emitting device for conversion luminescence includes a solid-state emitter chip, the solid-state emitter chip includes a plurality of emitting surfaces including a top emitter surface and including at least one edge emitting surface arranged along the periphery of the top emitting surface. The method includes: diffusing a chamfer forming material to contact at least one edge emitting surface and to contact a substrate located below the solid-state emitter chip, and thereby generating a chamfer along at least one edge emitting surface; and spraying a coating composition including at least one luminescent material onto the top emitting surface and the chamfer using at least one nozzle. In a specific embodiment, the chamfer includes a maximum height close to at least one edge emitting surface, the chamfer includes a minimum height away from at least one edge emitting surface, and the maximum height is lower than the top emitting surface. In a specific embodiment, using at least one nozzle includes: spraying the coating composition onto the top emitting surface and the chamfer in a first direction, and includes: spraying the coating composition onto the top emitting surface and the chamfer in a second direction, wherein the first direction is different from the second direction, and each of the first direction and the second direction is not perpendicular to the top emitting surface. In a specific embodiment, the chamfer forming material includes silicone and / or at least one luminescent material. As disclosed herein, in certain embodiments, the solid state emitter chip comprises a flip chip.

[0022] On the other hand, a method for manufacturing at least one converted luminescent solid-state emitter chip includes: positioning a template on a substrate, the substrate supporting at least one solid-state emitter chip including at least one luminescent surface, the template including at least one window registering at least one solid-state emitter chip to expose at least one luminescent surface; and applying at least one luminescent material on the exposed at least one luminescent surface of the at least one solid-state emitter chip, and the presence of the template prevents at least a portion of the substrate from receiving the at least one luminescent material. In a specific embodiment, the at least one luminescent surface includes a top emitting surface and at least one edge emitting surface arranged along the periphery of the top emitting surface, wherein the exposed at least one luminescent surface includes at least a portion of the top emitting surface and at least one edge emitting surface. In a specific embodiment, the method further includes: removing the template from the substrate. In a specific embodiment, the at least one solid-state emitter chip includes a plurality of solid-state emitter chips, and the method further includes: dividing the substrate into a plurality of sections, each section including at least one solid-state emitter chip from the plurality of solid-state emitter chips. In a specific embodiment, the at least one solid-state emitter chip includes a plurality of solid-state emitter chips, and the at least one window includes a plurality of windows. As disclosed herein, in a specific embodiment, the at least one solid-state emitter chip includes at least one flip chip.

[0023] On the other hand, a method for manufacturing at least one converted luminescent solid-state light-emitting device includes: arranging a plurality of solid-state emitter chips on a releasable viscous material; coating the plurality of solid-state emitter chips with at least one luminescent material; applying energy to the releasable viscous material to reduce the adhesion of the releasable viscous material; and removing the coated plurality of solid-state emitter chips from the releasable viscous material. In a specific embodiment, each of the plurality of solid-state emitter chips comprises a flip chip. In a specific embodiment, the coating comprises spraying a coating composition comprising at least one luminescent material onto the plurality of solid-state emitter chips using at least one nozzle. In a specific embodiment, the spraying of the coating composition comprises: spraying the coating composition in at least one direction that is not perpendicular to the top emission surface of each of the plurality of solid-state emitter chips. In a specific embodiment, the removal comprises: independently picking up each coated solid-state emitter chip of the plurality of solid-state emitter chips from the releasable viscous material, and placing each coated solid-state emitter chip on at least one substrate or base. As disclosed herein, in a specific embodiment, the plurality of solid-state emitter chips comprises a plurality of flip chips.

[0024] In certain embodiments, one or more flip chip LEDs disclosed herein may be implemented in a solid state emitter (or LED) package.As disclosed herein, in certain embodiments, a lighting fixture or bulb may include one or more flip chip LEDs.

[0025] In another aspect, the present disclosure is directed to a method of illuminating an object, a space, or an environment comprising utilizing a solid-state lighting device as disclosed herein.

[0026] On the other hand, for additional advantages, any of the above aspects, and / or individual aspects and features described herein can be combined. Any of the individual features and elements disclosed herein can be combined with one or more other disclosed features and elements, unless otherwise indicated herein.

[0027] Those skilled in the art will recognize the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in conjunction with the accompanying drawing figures. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate several aspects of the disclosure and together with the description serve to explain the principles of the disclosure.

[0029] Figure 1 is a schematic cross-sectional representation of a portion of a conventional LED chip including an internal reflector and a textured light emitting surface.

[0030] Figure 2Ais a schematic cross-sectional representation of selected (semiconductor) layers of a subassembly implementing a flip-chip LED according to certain embodiments of the present disclosure.

[0031] Figure 2B is a schematic cross-sectional representation of a selected layer of multiple quantum wells of a flip-chip LED according to certain embodiments of the present disclosure.

[0032] Figure 3A is a side cross-sectional view of a flip chip LED according to one embodiment of the present disclosure, the flip chip LED including a light transmissive surface patterned to be proximate to a semiconductor layer of the LED, including a multilayer reflector proximate to the semiconductor layer, and including a passivation layer between the multilayer reflector and electrical contacts of the LED.

[0033] Figure 3B yes Figure 3A Side cross-sectional view of an LED mounted to a submount and covered with a layer of luminescent material.

[0034] Figure 4A is a side cross-sectional view of a flip chip LED according to one embodiment of the present disclosure, the flip chip LED including a light-transmissive surface patterned to be close to a semiconductor layer of the LED, a multilayer reflector including a major surface and side surfaces close to a table formed by the semiconductor layer, and a passivation layer between the multilayer reflector and electrical contacts of the LED.

[0035] Figure 4B yes Figure 4A Side cross-sectional view of an LED mounted to a submount and covered with at least one layer of luminescent material.

[0036] Figure 5 is a photograph of an enlarged portion of an assembly including four flip-chip LEDs during manufacturing prior to dicing to separate the LED chips from each other.

[0037] Fig. 6A is a top plan view of a flip chip LED including a substrate having an outer surface including sloped sidewalls and a recessed top surface according to one embodiment of the present disclosure.

[0038] Figure 6B yes Fig. 6A Side elevation view of a flip chip LED in FIG.

[0039] Figure 6C yes Fig. 6A and Figure 6B A bottom-up plan view of a flip-chip LED in FIG.

[0040] Fig. 7A According to one embodiment of the present disclosure, FIG. 6A to FIG. 6CTop perspective view of an LED package of a single flip chip LED.

[0041] Figure 7B yes Fig. 7A A bottom perspective view of an LED package in FIG.

[0042] Fig. 8A is a schematic top plan view of a portion of an LED package including a plurality of flip-chip LEDs according to one embodiment of the present disclosure.

[0043] Figure 8B yes Fig. 8A A cross-sectional view of a portion of an LED package.

[0044] Fig. 9 is a plot of K-factor values ​​(representing the ratio of white brightness to blue brightness, with higher values ​​representing greater white conversion efficiency) for: (i) a flip-chip (comparative) LED of a conversion phosphor, made by a process comprising bonding an assembly comprising a growth substrate and an epitaxial layer to a carrier substrate, wherein a reflective layer is provided between the carrier substrate and the epitaxial layer, followed by removal of the growth substrate and top surface patterning or texturing of the exposed epitaxial layer surface; and (ii) a low optical loss flip-chip LED of a conversion phosphor according to an embodiment of the present disclosure, constructed on an internally patterned sapphire substrate.

[0045] Fig.10 : are plots of normalized luminous flux at three different target color rendering values ​​(E2: 70CRI, E3: 75CRI, E5: 80CRI) for the following two cases: (i) a comparative example LED, made by a process comprising bonding an assembly comprising a growth substrate and an epitaxial layer to a carrier substrate, wherein a reflective layer is provided between the carrier substrate and the epitaxial layer, followed by removal of the growth substrate and top surface patterning or texturing of the exposed epitaxial layer surface; and (ii) a flip-chip LED incorporating an internally patterned sapphire substrate according to one embodiment, thereby comparing color rolloff characteristics.

[0046] Fig.11 is a schematic illustration of an apparatus for vertically spraying a solid-state light emitter chip supported by a substrate.

[0047] Fig. 12A is a schematic illustration of an apparatus for angled spray coating of a plurality of solid state light emitter flip chips supported by a substrate.

[0048] Fig. 12B is a schematic side cross-sectional view of a plurality of solid state light emitter flip chips supported by a substrate and covered by a coating of luminescent material.

[0049] Fig.13 is a schematic illustration of an apparatus for angled spray coating of a solid state light emitter flip chip supported by a substrate using an angled nozzle directed toward an upper corner of the flip chip.

[0050] Fig.14A is a schematic side cross-sectional view of a solid state light emitter flip chip supported by a substrate, wherein the solid state light emitter flip chip has a light transmissive chamfer material disposed around the periphery of the chip and in contact with an edge emitting surface of the chip.

[0051] Fig. 14B yes Fig.14A Schematic side cross-section of a chip covered with a coating of luminescent material.

[0052] Fig.15A is a schematic side cross-sectional view of a solid state light emitter flip chip supported by a substrate, wherein the solid state light emitter flip chip has a light transmissive chamfer material including a luminescent material disposed around the periphery of the chip and in contact with an edge emitting surface of the chip.

[0053] Fig. 15B yes Fig.15A Schematic side cross-section of a chip covered with a coating of luminescent material.

[0054] Fig.16A is a top view photograph of a light emitting device including a solid state light emitter flip chip and an electrostatic discharge chip mounted to a submount.

[0055] Fig. 16B After adding a light-transmitting clear chamfer material arranged on a base around the periphery of the flip chip and arranged to contact the edge emitting surface of the flip chip, according to Fig.16A A top view photo of a lighting device.

[0056] Fig.17A is a top view photograph of a light emitting device including a solid state light emitter flip chip after adding a light transmissive chamfer material including a light emitting material disposed on a submount around the periphery of the flip chip and disposed in contact with an edge emitting surface of the flip chip.

[0057] Fig. 17B After adding additional coatings of luminescent material, Fig.17A A top view photo of the light emitting device in the.

[0058] Fig.18 is a top view photograph of six interconnected light emitting devices each comprising a hemispherical lens overlying a coating of luminescent material and a solid state light emitter flip chip supported by a submount, each device having no chamfer material between the flip chip and the submount.

[0059] Fig.19 is a top view photograph of six interconnected light emitting devices each comprising a hemispherical lens overlying a coating of luminescent material and a solid state light emitter flip chip supported by a submount, each device including chamfer material between the flip chip and the submount.

[0060] Fig. 20A is a perspective schematic assembly diagram of a substrate supporting three solid-state light emitter chips and a template layer defining three windows before the template layer is applied to the substrate.

[0061] Fig. 20B After the template layer is applied to the substrate (with the window for the aligned solid-state light emitter chip), Fig. 20A Schematic diagram of the substrate and template layer in FIG.

[0062] Fig. 20C After the luminescent material is applied to the emitting surface of the solid-state light emitter chip and after the template layer is removed, Fig. 20B A three-dimensional schematic diagram of the substrate and the solid-state light emitter chip.

[0063] Fig.21A is a top view photograph of nine interconnected light emitting devices, each comprising a solid state light emitter flip chip supported by a substrate, after applying the light emitting material to the emitting surface of the solid state light emitter flip chip through a template window, with a majority of each substrate being free of the light emitting material.

[0064] Fig. 21B yes Fig.21A A magnified top view photograph of a solid-state light emitter flip chip coated with a light-emitting material.

[0065] Fig.22A is a schematic illustration of a perspective view of an assembly of six solid state light emitter flip chips supported by releasable tape prior to spraying of the luminescent material.

[0066] Fig. 22B It is to use luminescent materials to coat the solid-state light emitter flip chip with a releasable tape. Fig.22A In a perspective schematic illustration of an assembly, the releasable tape is arranged close to an energy source.

[0067] Fig. 22C After applying energy to reduce the adhesion of the releasable tape and after removing the solid-state light emitter flip chip coated with a single luminescent material Fig. 22B A schematic perspective view of the components in FIG.

[0068] Fig.23A is a top view photograph of an assembly of sixteen solid state light emitter flip chips supported by releasable tape after spraying of the light emitting material.

[0069] Fig. 23B yes Fig.23A An enlarged stereogram photograph of a portion of the assembly.

[0070] Fig.23C is a top view photograph of the releasable tape layer coated with luminescent material after removal of sixteen solid state light emitter flip chips coated with luminescent material.

[0071] Fig.23D is a side perspective photograph of a solid state light emitter flip chip coated with luminescent material after the chip has been removed from the releasable tape layer.

[0072] Fig.24A is a top view photograph of a plurality of interconnected light emitting devices, each comprising a solid state light emitter flip chip coated with a light emitting material supported by a submount, after coating each flip chip via a releasable tape coating method.

[0073] Fig. 24B yes Fig.24A An enlarged top view photograph of a portion of a single light emitting device in FIG.

[0074] Fig.24C yes Fig.24A An enlarged stereogram photograph of a portion of a single light emitting device in FIG.

[0075] Fig.25A is a side cross-sectional schematic illustration of a portion of a light emitting device including a solid state light emitter flip chip mounted to a submount at a conventional height, with a diffuse reflective layer disposed over the submount arranged in contact with an edge emitting surface of the flip chip.

[0076] Fig.25B is a side cross-sectional schematic illustration of a portion of another light emitting device including a solid state light emitter flip chip mounted to a submount at an elevated height, with a diffuse reflective layer disposed over the submount that is not in contact with an edge emitting surface of the flip chip.

[0077] Fig.26 is a side cross-sectional schematic illustration of a solid state light emitter flip chip covered with a top sprayed layer of luminescent material, drops of anti-wicking material disposed over a top surface of the luminescent material layer and a reflective layer in contact with a side surface of the luminescent material layer.

[0078] Fig. 27 is a side cross-sectional schematic illustration of a solid state light emitter flip chip covered with top sprayed and angled sprayed layers of luminescent material with drops of anti-wicking material disposed over a top surface of the luminescent material layer and a reflective layer in contact with a side surface of the luminescent material layer.

[0079] Fig.28is a side cross-sectional schematic illustration of a solid state light emitter flip chip covered with top sprayed and angled sprayed layers of luminescent material, a light transmissive chamfered material comprising a luminescent material layer in contact with a side surface of the luminescent material layer, and a reflective layer in contact with a portion of the chamfered material.

[0080] Fig.29 is a side cross-sectional schematic illustration of a solid state light emitter flip chip covered with top sprayed and angled sprayed layers of luminescent material, the light transmissive chamfered material comprising a luminescent material layer in contact with a side surface of the luminescent material layer.

[0081] Fig.30 is a side cross-sectional schematic illustration of a solid state light emitter flip chip, a chamfered reflective layer contacts the edge of the flip chip, and a top-sprayed luminescent material layer covers the top surface of the flip chip and covers the reflective layer disposed over the edge of the flip chip.

[0082] Fig.31 is a side cross-sectional schematic illustration of a solid state light emitter flip chip arranged to be supported by a substrate, the flip chip and the substrate being covered with top sprayed and angled sprayed layers of light emitting material, drops of anti-wicking material being arranged above the top surface of the light emitting material layer, and a reflective layer being in contact with the side surfaces of the light emitting material layer.

[0083] Fig.32 is a schematic side cross-sectional illustration of a solid state light emitter flip chip arranged to be supported by a substrate, the flip chip and the substrate being covered with top sprayed and angled sprayed layers of luminescent material, and a reflective material layer disposed over portions of the luminescent material remote from side surfaces of the luminescent material layer.

[0084] Fig.33 The present invention is a schematic side cross-sectional view of a solid-state light emitter flip chip arranged to be supported by a substrate, a chamfered reflective layer portion is in contact with an edge of the flip chip, a top-sprayed luminescent material layer covers the top surface of the flip chip and covers the chamfered reflective layer portion arranged above the edge of the flip chip, drops of anti-wicking material are arranged above the top surface of the luminescent material, and the reflective material layer is arranged to contact the side surface of the luminescent material layer. DETAILED DESCRIPTION

[0085] Various embodiments disclosed herein relate to solid-state lighting devices including light-emitting diodes, such as devices including low optical loss flip-chip LEDs incorporating a multilayer reflector and incorporating a light-transmitting substrate patterned along an inner surface adjacent to a semiconductor layer. Preferably, the multilayer reflector spans approximately the entire area of ​​a light-emitting active region disposed between oppositely doped semiconductor layers of the LED, or more preferably, spans an area exceeding the active region of the LED. In additional aspects, the present disclosure relates to a method for manufacturing a solid-state light-emitting device for conversion light emission, wherein the surface of one or more solid-state light emitter chips is coated with a light-emitting material, such as may include angled spraying, chamfer formation prior to spraying, template island coating, and releasable tape coating. In a further aspect, the present disclosure relates to a solid-state light-emitting device including an elevated emitter chip and / or a light-transmitting chamfered material proximate to an edge emitting surface of the emitter chip, such as may be used to ensure adequate light-emitting material coverage of the edge emitting surface and / or reduce light flux loss in the presence of diffuse reflective material proximate to the emitter chip.

[0086] The embodiments described herein represent the necessary information to enable those skilled in the art to implement the embodiments and illustrate the best mode of implementing the embodiments. Upon reading the following description in accordance with the attached drawings, those skilled in the art will be able to understand the concepts of the present disclosure and will be able to recognize these concepts rather than the applications specifically addressed herein. It should be understood that these concepts and applications fall within the scope of the present disclosure and the appended claims.

[0087] It should be understood that, although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the present disclosure, a first element may be defined as a second element, and similarly, a second element may be defined as a first element. As used herein, the term "and / or" includes any and all combinations of one or more associated listed items.

[0088] It should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element or extending "in" another element, it can be directly located on another element or directly extend into another element or there can also be an intermediate element. On the contrary, when an element is referred to as being "directly located" on another element or "directly" extending into another element "in", there is no intermediate element. Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element or extending "on" another element, it can be directly located on another element or directly extend onto another element, or there can also be an intermediate element. On the contrary, when an element is referred to as being "directly located" on another element or "directly extending" on another element "on", there is no intermediate element. It should also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected to or coupled to another element, or there can be an intermediate element. On the contrary, when an element is referred to as being "directly connected" or "directly coupled" to another element, there is no intermediate element.

[0089] Relative terms used herein, such as "below" or "above" or "on" or "under", may describe one element, layer, or region in relation to another element, layer, or region as illustrated in the figures. It should be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

[0090] The terms used herein are for the purpose of describing specific embodiments only and are not intended to limit the present disclosure. As used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should be further understood that the terms "comprises", "comprising", "includes", and / or "including" used herein specify the presence of the features, wholes, steps, operations, elements, and / or parts, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, parts, and / or groups thereof.

[0091] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It should be further understood that the terms used herein should be interpreted as having a meaning consistent with their meaning in the context of this specification and the relevant technical field and will not be interpreted in an idealized or excessive formal sense unless explicitly defined herein.

[0092] As used herein, the "active region" of a solid-state light emitting device refers to the region where majority and minority carriers (e.g., holes and electrons) recombine to generate light. Generally, the active region according to embodiments disclosed herein can include a double heterostructure or a well structure such as a quantum well structure.

[0093] The solid-state light emitting device disclosed herein may include at least one solid-state light source (e.g., LED) and one or more luminescent materials (also referred to herein as luminophores) arranged to receive the emission of at least one solid-state light source. The luminescent material may include one or more of a phosphor, a scintillator, a luminescent ink, a quantum dot material, a daylight strip, and the like. Generally, the solid-state light source may generate light having a first dominant wavelength. At least one luminophore receiving at least a portion of the light generated by the solid-state light source may re-emit light having a second dominant wavelength different from the first dominant wavelength. The solid-state light source and the one or more luminescent materials may be selected such that their combined output produces light having one or more desired characteristics such as color, color point, intensity, and the like. In a particular embodiment, the aggregate emission of one or more flip-chip LEDs, optionally in combination with one or more luminescent materials, may be arranged to provide cool white, mid-white, or warm white light within a color temperature range such as from 2500K to 10000K. In a particular embodiment, luminescent materials having dominant wavelengths of cyan, green, amber, yellow, orange, and / or red may be used. In certain embodiments, the luminescent material may be added to one or more emitting surfaces (e.g., the top surface or one or more edge surfaces) by methods such as spraying, dipping, liquid diffusion, powder coating, inkjet printing, etc. In certain embodiments, the luminescent material may be dispersed in an encapsulant, adhesive, or other bonding medium.

[0094] As used herein, a layer or region of an LED is considered to be "transparent" when at least 90% of the radiation from the LED incident on the transparent layer or region emerges through the transparent region. For example, in the context of manufacturing blue and / or green LEDs from gallium nitride-based materials, silicon dioxide can provide a transparent insulating layer (e.g., at least 90% transparent), while indium tin oxide (ITO) can provide a transparent conductive layer (e.g., at least 90% transparent), as measured by considering the transmission and reflection components on the sapphire substrate. Moreover, as used herein, a layer or region of an LED is considered to be "reflective" or implement a "reflector" when at least 90% of the angularly averaged radiation emitted from the LED active area and incident on the layer or region is reflected back into the active area. For example, in the context of gallium nitride-based blue and / or green LEDs, silver (e.g., at least 90% reflective) can be considered a reflective material. In the case of ultraviolet (UV) LEDs, appropriate materials can be selected to provide the desired (and in some embodiments) high reflectivity and / or the desired (and in some embodiments) low absorption.

[0095] As previously mentioned, various embodiments herein relate to solid-state light emitting devices including light emitting diodes, such as devices including low optical loss flip-chip LEDs that incorporate a multilayer reflector and incorporate a light-transmitting (preferably transparent) substrate patterned along an inner surface adjacent to a semiconductor layer, etc. The flip-chip LED includes spaced-anode and cathode contacts extending along the same face, and the face is opposite to the face defined by the light-transmitting (preferably transparent) substrate. Flip-chip LEDs can also be defined as horizontal structures, as opposed to vertical structures having contacts on opposite faces of the LED chip.

[0096] In certain embodiments, a light-transmissive (preferably, transparent) substrate comprises a patterned inner surface adjacent to a semiconductor layer, and the patterned surface comprises at least one of (a) a plurality of recessed features and (b) a plurality of raised features. In certain embodiments, the substrate may comprise sapphire; alternatively, the substrate may comprise silicon, silicon carbide, a III-nitride material (e.g., GaN), another epitaxially compatible crystalline material, or any combination of the foregoing (e.g., silicon on sapphire, etc.). The substrate may be patterned by any of a variety of methods known in the art, including (but not limited to) forming nanoscale features by etching (e.g., photolithographic etching) using any suitable etchant, optionally in combination with one or more masks. Any desired number, shape, pitch, and configuration of features may be provided. In certain embodiments, the patterned substrate may comprise one or more of the following: stripes, dots, curved features, circular features, polygonal features, conical features, truncated conical features, etc. After patterning, the patterned surface can be optionally planarized by conventional methods (e.g., by polishing, chemical mechanical polishing, or any suitable process), and the patterned surface can be cleaned by conventional methods to make the patterned surface susceptible to epitaxy. Thereafter, one or more epitaxial layers can be grown thereon, including oppositely doped semiconductor layers with active regions disposed therebetween.

[0097] It should be noted that the cost of sapphire, silicon, and silicon-on-sapphire substrate materials can be significantly lower than higher performance silicon carbide or group III-nitride substrates, but, as described herein, the use of an internally patterned substrate together with a multilayer reflector can allow a flip-chip LED that incorporates a lower cost (e.g., sapphire) substrate to achieve comparable performance levels to a flip-chip LED manufactured on an externally roughened silicon carbide substrate (which lacks patterning on its inner surface). Mainly due to high material costs, conventional silicon carbide substrates are thin and may be supported by non-natural support materials. As described herein, when using a lower cost substrate (e.g., sapphire) for flip-chip LED manufacturing, an economical thick natural substrate can be used without any non-natural support materials for mechanical support. The proposed new solution can provide a faster manufacturing cycle time for manufacturing flip-chip LEDs with less capital. In addition, due to the additional support of the thick natural (e.g., sapphire) substrate, the resulting flip-chip LED can be more reliable.

[0098] As set forth above, the subsequent formation of patterned features on the surface of the substrate, various semiconductor layers (including oppositely doped semiconductor layers with active regions disposed therebetween) can be epitaxially grown on or over the patterned surface of the substrate. In particular embodiments, the growth of epitaxial layers on or over the patterned surface can improve the epitaxial growth process by encouraging the destruction of dislocation defects, thereby providing higher crystal quality. In addition, the presence of patterned features on the inner surface of the substrate provides a varying surface that increases the probability of refraction of light in the substrate, as opposed to internal reflection of light in the semiconductor layer adjacent to the substrate. Both improved crystal quality and improved light extraction are beneficial to improving the light output from a flip-chip LED incorporating the substrate.

[0099] After epitaxially growing the semiconductor layer on the patterned substrate, various other structures (e.g., mesa-defining recesses, multilayer reflectors, barrier layers, passivation layers, interlayers, microcontact arrays, and electrical contacts) can be formed on the semiconductor layer. Those skilled in the art will recognize that multiple LED chips can be manufactured simultaneously on a single wafer (e.g., a six-inch diameter wafer, or a wafer of any suitable size), and then the LED chips can be separated into individual pieces by dicing or any other suitable technique.

[0100] Combination FIG. 2A to FIG. 4B Various details of at least specific layers of exemplary LED structures utilizing Group III nitride (e.g., GaN, InGaN, AlGaN) semiconductor materials are described. It should be appreciated that the present disclosure is not limited to light emitting structures based on Group III nitride semiconductor materials and similar structures can be fabricated utilizing other (e.g., arsenide, phosphide, etc.) material types.

[0101] Figure 2Ais a schematic cross-sectional representation of selected (semiconductor) layers of an epitaxial subassembly 10 implementing a flip-chip LED according to a particular embodiment of the present disclosure, which layers are not drawn to scale. The epitaxial subassembly 10 includes oppositely doped first and second semiconductor layers (e.g., n-GaN layer 11 and p-GaN layer 12) having a multiple quantum well (MQW) active region 15 disposed therebetween. Optionally, one or more buffer layers (e.g., n-type AlGaN and / or unintentionally doped GaN, not shown) of constant or graded composition can be disposed between the patterned substrate and the doped first semiconductor layer 11. In a particular embodiment, the doped first semiconductor layer 11 can include an n-type layer disposed adjacent to the patterned substrate (not shown). In a particular embodiment, the doped first semiconductor layer 11 can be doped with silicon, such as, for example, less than about 5×10 19 cm -3 levels, etc., and may have any suitable thickness ranging from tens to thousands of angstroms.

[0102] A spacer layer 13 (e.g., undoped GaN) and / or a superlattice structure 14 (which may include alternating layers of silicon-doped GaN and / or InGaN) are optionally disposed between the doped first semiconductor layer 11 and the active region 15. If present, the superlattice structure 14 may provide a better surface for the growth of the nitride (e.g., InGaN-based) active region 15 and may affect the operating voltage. Although not wishing to be bound by any theory of operation, it is currently believed that the stress effects in the superlattice structure 14 provide a growth surface that facilitates the growth of the active region 15 containing high-quality InGaN. Appropriate selection of the thickness and composition of the superlattice structure 14 can reduce the operating voltage and / or enhance the optical efficiency. In a specific embodiment including the superlattice structure 14, the superlattice structure 14 may include InGaN. x Ga 1-x N and In y Ga 1-y N, wherein x is between 0 and 1 (inclusive), and x is not equal to y. In a particular embodiment, x=0, and thus, the superlattice structure 14 includes alternating layers of GaN and InGaN. In a particular embodiment, the superlattice structure 14 may include about 5 to about 50 periods (wherein one period is equal to the number of InGaN layers forming the repeating layers of the superlattice structure 14). x Ga 1-x N layer and In y Ga 1-y One repetition of N layers).

[0103] The active region 15 includes a plurality of light-emitting wells, which include a thin layer of a low-bandgap semiconductor material sandwiched between a higher bandgap cladding or confinement layer, and in some embodiments, the light-emitting well can be a quantum well. As known to those skilled in the art, a well layer is a very thin layer (usually less than about 50nm) of a semiconductor material surrounded by a barrier layer or confinement layer having a higher bandgap than the quantum well layer. The barrier layer forms a quantum well together with the well layer. Specifically, the quantum well layer is so thin that the allowable energy level of the quantum well is presented as a discrete value, and therefore, compared with the bulk material having a stable distribution of allowable energy levels, the quantum well exhibits a high-density state at the lowest allowable (discrete) energy level. Compared with bulk recombination / emission, quantum wells can generate photons by carrier recombination with improved efficiency and / or spectral purity. When electrons fill the space in the crystal lattice occupied by holes and move to a lower energy state, carrier recombination occurs, thereby releasing energy in the form of heat and / or light. In various embodiments, the well may or may not be thin enough to be characterized as a quantum well. In the specific embodiment disclosed herein, the active region 15 includes a plurality of barrier well cells (such as Figure 2B The multi-well structure shown in FIG.

[0104] In a particular embodiment, an optional capping layer 16 may be disposed on the active region 15 and may include an undoped GaN, AlGaN and / or AlInGaN layer. In a particular embodiment, the capping layer 16 may have a thickness in the range of 1 angstrom to 300 angstroms. As used herein, "undoped" refers to a layer or region that is not intentionally doped with impurities, and is synonymous with "unintentionally doped." It should be recognized that Group III nitride-based materials are typically naturally grown n-type, and therefore, the capping layer 16 may be n-type growth. In a particular embodiment, the capping layer 16 may have a thickness of at least about 40 angstroms.

[0105] The doped second semiconductor layer 12 may include a p-type nitride-based layer such as GaN, AlGaN, or AlInGaN doped with a p-type impurity such as magnesium. In a particular embodiment, the doped second semiconductor layer 12 may have a thickness ranging from 0 angstroms to 300 angstroms, and in some cases, may have a thickness of about 150 angstroms.

[0106] In certain embodiments, the PN junction 17 may be formed at the junction between the doped second semiconductor layer 12 and the cap layer 16. The PN junction 17 serves as a mechanism for injecting minority carriers into the active region 15, where the carriers can recombine with majority carriers to generate photons and produce light emission. In certain embodiments, the PN junction 17 is preferably located at or near the active region 15, such as at a position less than 1000 m from the active region 15. Therefore, the injected minority carriers can diffuse into the active region 15 with high probability and recombine with the majority carriers in the quantum well.

[0107] Figure 2B The barrier well unit of an exemplary active region 15 implementing a multi-quantum well structure is shown. The exemplary active region 15 can provide a specific embodiment. Figure 2A . The active region 15 includes a multi-well structure in which a plurality of InGaN well layers 20-1 to 20-N (where N is a variable of any suitable value) are separated by intervening barrier layers 18-1 to 18-N in an alternating manner and covered with an additional barrier layer 18-N+1. The barrier layers 18-1 to 18-N may generally include GaN, AlGaN, InGaN, or AlInGaN; however, the indium composition of the barrier layers 18-1 to 18-N and 18-N+1 is preferably less than the indium composition of the well layers 20-1 to 20-N, such that the barrier layers 18-1 to 18-N and 18-N+1 have a higher band gap than the well layers 20-1 to 20-N. In a particular embodiment, the barrier layers 18-1 to 18-N and 18-N+1 and the well layers 20-1 to 20-N may be undoped (i.e., not intentionally doped with impurity atoms such as silicon or magnesium). In other embodiments, specifically, if ultraviolet emission is desired, the barrier layers 18-1 to 18-N and 18-N+1 may be doped with silicon. In the active region 15, each well layer 20-1 to 20-N is positioned between two barrier layers 18-1 to 18-N and 18-N+1 to form a plurality of quantum wells 25-1 to 25-N each including a well layer and two barrier layers. Each combination of a barrier layer 18-1 to 18-N and an adjacent well layer 20-1 to 20-N may also be referred to as being included in a "barrier-well unit", and Figure 2B 1 and 2 , a plurality of barrier-well units 22 - 1 to 22 -N are shown sequentially arranged and covered with an additional barrier layer 18 -N+1, thereby forming an active region 15 including a plurality of quantum wells 25 - 1 to 25 -N.

[0108] As previously mentioned, various embodiments herein relate to a device comprising a low optical loss flip chip LED incorporating a multilayer reflector and incorporating a patterned substrate. The multilayer reflector preferably comprises a dielectric reflector layer adjacent to an oppositely doped semiconductor layer and a metal reflector layer located on the dielectric reflector layer. In addition to providing a light reflection effect, the multilayer reflector may also provide a conductive effect and / or a current distribution effect.

[0109] In certain embodiments, the dielectric reflector layer includes a material having a refractive index different from (e.g., lower than) an oppositely doped semiconductor layer (disposed adjacent to the active region). In certain embodiments, the dielectric layer may include a refractive index less than an adjacent layer to promote total internal reflection. In certain embodiments, a metal reflector layer is disposed on or adjacent to the dielectric reflector layer and used in conjunction with the dielectric reflector layer to enhance reflection such that any portion of light that passes through the dielectric reflector layer can be reflected by the metal reflector layer back to the active region.

[0110] The use of a multilayer reflector within an LED can reduce optical losses of light emitted through the active area in a direction toward the submount or in other undesirable directions away from the primary light emitting surface of the LED. The multilayer reflector can be positioned to reflect the light to allow the light to propagate from the LED chip in the desired direction.

[0111] In certain embodiments, the dielectric reflector layer can be disposed directly on a doped (eg, p-doped) semiconductor layer adjacent to the LED active region. In other embodiments, one or more intermediate layers can be disposed between the dielectric reflector layer and the doped semiconductor layer.

[0112] The dielectric reflector layer may include any one or more of a variety of materials. In certain embodiments, the dielectric reflector layer may include two or more sublayers of dielectric material having different material concentrations and / or compositions. In certain embodiments, the dielectric reflector layer includes silicon dioxide (SiO2). In other embodiments, dielectric materials such as Si, Ge, MgO, etc. may be used. x 、ZnO、SiN x 、SiO x , AlN, Al2O3, and alloys, and combinations thereof. Other materials having a lower or higher refractive index than the material of the doped semiconductor layer (e.g., p-GaN) are arranged between the dielectric reflector layer and the active region. In a specific embodiment, the dielectric reflector layer has a refractive index in the range of 1% to 50%, or 5% to 40%, or 5% to 30% lower than the material of the adjacent doped semiconductor layer. For example, GaN and SiO2 have refractive indices of 2.4 and 1.46, respectively, representing a 39% difference between the two materials. The thickness of the dielectric reflector layer can vary depending on the material composition, but in a specific embodiment, the dielectric reflector layer can have a thickness of at least about 0.2 microns, about 0.5 microns, at least about 0.5 microns, or in the range of from about 0.2 microns to about 0.7 microns.

[0113] For the metal reflector layer of the multilayer reflector, various metals can be used. In a specific embodiment, the metal reflector layer may include Ag, Au, Al, or a combination thereof, and may include multiple sublayers. As mentioned previously, each reflection from the metal layer is necessarily accompanied by a loss of light, and these losses are significant for photons (e.g., light) that pass through multiple passes and reflections within the LED. Reflection by TIR is generally lossless, so that when a larger portion of the light is reflected by TIR rather than by a metal reflector, optical losses are reduced. In a specific embodiment, the metal reflector layer may include Ag in combination with at least one other metal, or in other embodiments, may be substantially composed of Ag.

[0114] In a particular embodiment, an adhesive layer may be provided between the dielectric reflector layer and the metal reflector layer to promote adhesion between these layers. If provided, the adhesive layer may include various materials such as TiO, TiON, TiO2, TaO, TaON, Ta2O5, AlO or a combination thereof, preferably TiON. In a particular embodiment, the adhesive may have a thickness ranging from a few angstroms (e.g., 3 angstroms to 10 angstroms) to 1000 angstroms or more. The thickness and material of the adhesive layer should be selected to minimize the absorption of light passing therethrough.

[0115] In a particular embodiment, the multilayer reflector includes a dielectric reflector layer disposed on a metal reflector layer, and a plurality of conductive vias extend through the dielectric reflector layer and are disposed in contact with the metal reflector layer. In a particular embodiment, at least some of the vias in combination with the metal reflector layer can provide a conductive path through the insulating dielectric reflector layer to allow electrical signals to be propagated (e.g., through a doped semiconductor layer such as p-GaN) to an active region of the LED. In a particular embodiment, at least some of the vias in combination with the metal reflector layer can enhance the spreading of current into at least a portion of the active region. In a particular embodiment, some of the vias defined by a portion of the dielectric reflector layer can be used for the spreading of electrical signals to or from the active region, while other vias defined by another portion of the dielectric reflector layer can be used to enhance current distribution, but not necessarily for the spreading of electrical signals to or from the active region. In view of this, an area of ​​the metal reflector layer can simultaneously provide two or more utilities of light reflection, conduction, and current distribution.

[0116] A multilayer reflector including a dielectric reflector layer defining vias and including a metal reflector layer close to the dielectric reflector layer can be formed in various ways. In one embodiment, after epitaxially growing oppositely doped semiconductor layers with active regions arranged therebetween, a dielectric reflector material (e.g., SiO2) can be deposited on the surface of the semiconductor layer located at the far end of the substrate. Thereafter, (e.g., p-via) holes can be defined in the dielectric reflector layer. After formation, the holes can be filled with metal that occurs simultaneously with the deposition of the metal reflector layer to form conductive vias. The holes in the dielectric reflector material can be formed by conventional etching processes or mechanical processes such as micro-drilling. The holes can have various shapes and sizes. In a specific embodiment, the holes defined by the dielectric reflector layer can have a circular cross-section with a diameter of less than 20 microns. In a specific embodiment, holes with other cross-sectional shapes (e.g., square, elliptical, hexagonal, pentagonal, etc.) can be provided. In some embodiments, the holes defined in the dielectric reflector layer can have a diameter in the range of 1 micron to 8 microns. In certain embodiments, adjacent holes can be spaced apart by an edge-to-edge distance in a range of 5 microns to 100 microns, in a range of 10 microns to 40 microns, or in a range of 20 microns to 30 microns. In certain embodiments, any one or more of the size, shape, and spacing of the holes can be uniform or non-uniform over part or all of the dielectric reflector layer.

[0117] After forming the holes in the dielectric reflector layer, metal can be deposited (e.g., via sputtering or any suitable process) into the holes and the exposed surface of the dielectric reflector layer to form a metal reflector layer. Thereafter, a barrier layer can be formed on the metal reflector layer, and examples of suitable materials that can be used to form the barrier layer include, but are not limited to, sputtered Ti / Pt followed by evaporated Au bulk material, or sputtered Ti / Ni followed by evaporated Ti / Au bulk material.

[0118] In a particular embodiment, a central portion of the plurality of semiconductor layers (including the light emitting active region) forms a table extending in a direction away from the substrate, and a peripheral portion of the plurality of semiconductor layers forms at least one recess that laterally bounds the table. In a particular embodiment, the multilayer reflector is disposed substantially over the entire major surface of the table (e.g., at least about 90%, at least about 92%, or at least about 95% of the major surface of the table), and the recess comprises a passivation material (e.g., SiN). The at least one recess that bounds the table can be formed by etching the plurality of semiconductor layers. In a particular embodiment, the multilayer reflector is disposed substantially over the entire major surface of the table (e.g., at least about 90%, at least about 92%, or at least about 95% of the major surface of the table), and the multilayer reflector further extends beyond the major surface of the table into at least one recess ("surrounding" the active region), and at least a portion of the passivation material further extends into the recess to peripherally surround the multilayer reflector and prevent exposure of the multilayer reflector. The portion of the multilayer reflector extending into the at least one recess is preferably absent from the conductive via extending through the dielectric reflector material, so that only insulating material is arranged in contact with the lateral boundaries of the light emitting active area.

[0119] In a particular embodiment, the barrier layer can be disposed proximate to the metal reflector layer to prevent metal migration from the metal reflector layer. Examples of suitable materials for forming the barrier layer include, but are not limited to, sputtered Ti / Pt followed by evaporated Au bulk material, or sputtered Ti / Ni followed by evaporated Ti / Au bulk material. Other combinations of these or other materials may be used to form the barrier layer, according to particular embodiments. In a particular embodiment, the barrier layer may define an array of openings containing a passivation material and a lateral encapsulated array of conductive microcontacts extending therethrough, and the microcontacts provide a conductive path between an external electrical contact and one of the doped semiconductor layers of the LED for propagation of current to or from the active region.

[0120] As previously mentioned, in a particular embodiment, a passivation layer is disposed between the metal reflector layer and (i) the first electrical contact and (ii) the second electrical contact. In a particular embodiment, the passivation layer comprises a suitable durable and insulating material such as silicon nitride. Other materials may be used for the passivation layer. In a particular embodiment, the passivation layer comprises a metal-containing interlayer (e.g., comprising Al or another suitable metal) disposed therein. In a particular embodiment, the interlayer may be used as a crack reduction feature, such as to prevent cracks in the insulating layer from propagating to a major surface of the insulating layer (e.g., close to an external contact of the LED). In a particular embodiment, the passivation layer interlayer may define a first array and a second array of openings using a first array and a second array of conductive microcontacts extending therethrough, wherein the microcontacts provide a conductive path between the external electrical contacts and the oppositely doped semiconductor layers of the LED for propagation of current to and from the active region. The presence of the passivation material between the microcontacts and the openings defined in the interlayer may prevent conductive communication between the array of microcontacts and the interlayer.

[0121] In a particular embodiment, a separate first electrical contact and a second electrical contact are arranged on a single surface of a passivation layer of a flip chip LED. In one embodiment, a first electrical contact (e.g., an n-contact or cathode) can be arranged to be in conductive communication with a first semiconductor layer (e.g., an n-GaN layer) proximate to an active region, and a second electrical contact (e.g., a p-contact or anode) can be arranged to be in conductive communication with a second semiconductor layer (e.g., a p-GaN layer) proximate to an active region. In this embodiment, conductive communication between the first electrical contact and the first semiconductor layer is provided by a first array of microcontacts, the first array of microcontacts extending through the passivation layer, the metal-containing interlayer, the barrier layer, the metal reflector layer, the dielectric reflector layer, the first semiconductor layer, and the active region. In addition, in this embodiment, conductive communication between the second electrical contact and the second semiconductor layer is provided by a metal reflector layer, a via defined in the dielectric reflector layer, and a second array of microcontacts (the second array of microcontacts extending through the passivation layer, the metal-containing interlayer, and the barrier layer to reach the metal reflector layer).

[0122] In a specific embodiment, a flip chip LED can be manufactured by various steps, including: (a) patterning the surface of a substrate; (b) epitaxially growing a plurality of semiconductor layers, the plurality of semiconductor layers sandwiching a light emitting active region located on or adjacent to the patterned surface; (c) forming at least one recess in a portion of the semiconductor layer (including the active region) to define a table; (d) forming a multilayer reflector (including a dielectric reflector layer and a metal reflector layer defining a via) on or adjacent to at least one layer of the plurality of semiconductor layers; (e) forming a barrier layer on or adjacent to the metal reflector layer; (f) forming a dielectric reflector layer and a plurality of reflectors on or adjacent to the barrier layer; and (g) forming a dielectric reflector layer and a metal reflector layer on or adjacent to the metal reflector layer. (g) forming a first passivation layer on or adjacent to the barrier layer; (h) forming an interlayer on the first passivation layer portion; (i) forming a second passivation layer portion on the interlayer and the first passivation layer portion; (j) defining openings through the respective layers (e.g., via etching or micro-punching) for receiving first and second arrays of microcontacts; (k) filling the aforementioned openings with a conductive material to form the first and second arrays of microcontacts; and (l) forming electrical contacts on the surface of the second passivation layer portion, with the first electrical contact being in conductive communication with the first array of microcontacts and the second electrical contact being in conductive communication with the second array of microcontacts. With respect to step (j), it should be noted that defining openings through the respective layers in a single or sequential manner can be beneficial in facilitating alignment of the openings. In particular embodiments, one or more of the aforementioned steps can be omitted, and / or additional steps can be added. In particular embodiments, one or more of the aforementioned steps can be split into sub-portions, and / or a person skilled in the art can change the temporary order of two or more steps as desired.

[0123] Figure 3AA flip chip LED 100 is shown including an inner light-transmitting surface 104, including a multilayer reflector proximate to a semiconductor layer, according to one embodiment, the inner light-transmitting surface 104 being patterned proximate to the semiconductor layer of the LED 100. The LED 100 includes a light-transmitting (preferably transparent) substrate 105 having an outer major surface 101, a side surface 102, and a patterned surface 104 having a plurality of recessed and / or raised features 107. A plurality of semiconductor layers 111, 112 sandwiching a light-emitting active region 115 are adjacent to the patterned surface 104 and can be deposited via vapor phase epitaxy or any other suitable deposition process. In one embodiment, the first semiconductor layer 111 proximate to the substrate 105 implements an n-doped material (e.g., n-GaN), and the second semiconductor layer 112 implements a p-doped material (e.g., p-GaN). A central portion of the multiple semiconductor layers 111, 112 including the active region 115 extends in a direction away from the substrate 105 to form a mesa 119 that is laterally defined by at least one recess 129 comprising a passivation material (e.g., silicon nitride as part of the passivation layer 140) and vertically defined by a surface extension 111A of the first semiconductor layer 111.

[0124] The multilayer reflector is arranged close to the second semiconductor layer 112 (e.g., on the second semiconductor layer 112), and the multilayer reflector is composed of a dielectric reflector layer 130 and a metal reflector layer 132. The dielectric reflector layer 130 is arranged between the metal reflector layer 132 and the second semiconductor layer 112. In a specific embodiment, the dielectric reflector layer 130 includes silicon dioxide, and the metal reflector layer 132 includes silver. A plurality of conductive vias 131-1, 131-2 are defined in the dielectric reflector layer 130 and are preferably arranged to contact between the second semiconductor layer 112 and the metal reflector layer 132. In a specific embodiment, the conductive vias 131-1, 131-2 include substantially the same material as the metal reflector layer 132. In particular embodiments, at least one (preferably both) of the dielectric reflector layer 130 and the metal reflector layer 132 are disposed over substantially all of the major surface of the mesa 119 terminated by the second semiconductor layer 112 (e.g., at least about 90%, at least about 92%, or at least about 95% of the major (e.g., lower) surface of the mesa portion of the second semiconductor layer 112).

[0125] The barrier layer 138 (including portions 138-1 and 138-2) is preferably disposed between the metal reflector layer 132 and the passivation layer 140. In a particular embodiment, the barrier layer 138 comprises sputtered Ti / Pt followed by evaporated Au, or sputtered Ti / Ni followed by evaporated Ti / Au. In a particular embodiment, the barrier layer 138 can be used to prevent migration of metal from the metal reflector layer 132. The passivation layer 140 is disposed between the barrier layer 138 and (i) a first externally accessible electrical contact 151 and (ii) a second externally accessible electrical contact 152, both of which are disposed along the lower surface 144 of the flip chip LED 100 separated by a gap 149. In a particular embodiment, the passivation layer 140 comprises silicon nitride. The passivation layer 140 includes a metal-containing interlayer 145 disposed therein, wherein the interlayer 145 may include (or consist essentially of) Al or another suitable metal.

[0126] The LED 100 includes a first array and a second array of microcontacts 153, 154 extending through the passivation layer 140, the first array of microcontacts 153 providing conductive communication between a first electrical contact 151 and a doped (e.g., n-doped) first semiconductor layer 111, and the second array of microcontacts 154 providing conductive communication between a second electrical contact 152 and a (e.g., p-doped) second semiconductor layer 112. The first array of microcontacts 153 extends from the first electrical contact 151 (e.g., n-contact), through the passivation layer 140, through an opening defined in the interlayer 145, through an opening 142 defined in the first portion 138-1 of the barrier layer 138, through an opening defined in the first portion 132-1 of the metal reflector layer 132, through an opening defined in the first portion 130-1 of the dielectric reflector layer 130, through the second semiconductor layer 112, and through the active region 115, terminating in the first semiconductor layer 111. Within the opening defined in the interlayer 145, the first portion 138-1 of the barrier layer 138, the first portion 132-1 of the metal reflector layer 132, and the first portion 130-1 of the dielectric reflector layer 130, the dielectric material of the dielectric layer 130 laterally encapsulates the microcontact 153 to prevent electrical contact between the microcontact and the corresponding layers 145, 138, 132, 130. A set of vias 131-1 defined in the first portion 130-1 of the dielectric reflector layer 130 contacts the first portion 130-1 of the dielectric reflector layer 130 and the first semiconductor layer 112, which is beneficial to promote current distribution in the active region 115. A second array of microcontacts 154 extends from the second electrical contact 152 through the passivation layer 140 and through the opening defined in the interlayer 145 to at least one of (i) the second portion 138-2 of the barrier layer 138 and (ii) the second portion 132-2 of the metal reflector layer 132, wherein electrical communication is established between the metal reflector layer 132 and the second semiconductor layer 112 through a set of vias 131-2 defined in the second portion of the dielectric reflector layer 130-2. In certain embodiments, although the second array of microcontacts 154 is preferred, in other embodiments, a single second microcontact may replace the second array of microcontacts 154. Similarly, in certain embodiments, although it is preferred to define a plurality of vias 131-2 in the second portion of the dielectric reflector layer 130-2, in other embodiments, a single via or other suitable conductive path may replace the plurality of vias 131-2.

[0127] After formation of the passivation layer 140, one or more side portions 106 extending between the outer main surface 101 of the substrate 105 and the surface extension 111A of the first semiconductor layer 111 are not covered with the passivation material. The side portions 106 implement a non-passivated side surface.

[0128] Figure 3B Shows Figure 3A The flip chip LED 100 in FIG. 1 is mounted to a submount 160 and covered with a layer 170 of at least one luminescent material. The submount 160 includes a first contact pad 161 and a second contact pad 162 disposed proximate to the electrical contacts 151, 152, respectively. Conductive communication between the contact pads 161, 162 and the electrical contacts 151, 152 separated by a gap 149 may be established using solderless, solder flux, or other conventional attachment means. Figure 3B As shown in FIG. 1 , a layer 170 of at least one luminescent material is arranged to cover the top surface 101 , the non-passivated side surfaces 106 , and the passivated side surfaces (ie, the sidewalls of the passivation layer 140 ), and the submount 160 .

[0129] refer to Figure 3A and Figure 3B In operation of the flip chip LED 100, current can flow from the first electrical contact (e.g., n-contact or cathode) 151 (e.g., through the contact pad 161), the first set of microcontacts 153, and the (n-doped) first semiconductor layer 111 to the active region 115 to generate light emission. Current flows from the active region 115 through the (p-doped) second semiconductor layer 112, the via 131-2, the metal reflector layer portion 132-2, the barrier layer portion 138-2, and the second set of microcontacts 154 to the second electrical contact (e.g., p-contact or anode) 152. The emission generated by the active region 115 initially propagates in all directions, and the reflector layers 130, 132 serve to reflect the emission in a direction generally toward the substrate 105. When the emission reaches the light-transmissive patterned inner surface 104 disposed between the substrate 105 and the first semiconductor layer 111, the concave / convex features 107 disposed in or on the patterned inner surface 104 promote refraction at the inner surface 104 rather than reflection, thereby increasing the chance of the photon passing through the first semiconductor layer 111 into the substrate 105 and then exiting the LED 100 through the top surface 101 and the non-passivated side surface 106. When the surface of the LED 100 is covered with one or more luminescent materials 170 (e.g., Figure 3B As shown), at least a portion of the emission emitted from LED 100 can be up-converted or down-converted by one or more luminescent materials 170.

[0130] The luminescent materials described herein may be or include one or more of phosphors, scintillators, luminescent inks, quantum dot materials, daylight strips, and the like. The luminescent materials may be provided in any suitable manner, for example, directly coated on one or more surfaces of an LED, dispersed in an encapsulation material configured to cover one or more LEDs, and / or coated on one or more optical or support elements (e.g., by powder coating, inkjet printing, etc.). In particular embodiments, the luminescent materials may be down-converted or up-converted, and combinations of both down-converting and up-converting materials may be provided. In particular embodiments, a plurality of different (e.g., different compositions) luminescent materials arranged to produce different peak wavelengths may be arranged to receive emissions from one or more LED chips.

[0131] In various configurations, one or more luminescent materials may be disposed on one or more portions of a flip chip LED and / or on a submount. In certain embodiments, one or more surfaces of a flip chip LED may be conformally coated with one or more luminescent materials, while other surfaces of the LED and / or associated submounts may be free of luminescent materials. In certain embodiments, the top surface of a flip chip LED may include luminescent materials, while one or more side surfaces of the flip chip LED may be free of luminescent materials. In certain embodiments, all or substantially all of the outer surfaces of a flip chip LED (e.g., except for surfaces defining contacts or mounting) are coated or otherwise covered with one or more luminescent materials. In certain embodiments, one or more luminescent materials may be disposed to be arranged in a substantially uniform manner on one or more surfaces of a flip chip LED; in other embodiments, one or more luminescent materials may be disposed to be arranged in a non-uniform manner on or on one or more surfaces of a flip chip LED relative to one or more of material composition, concentration, and thickness. In certain embodiments, the loading percentage of one or more luminescent materials on or in one or more outer surfaces of a flip chip LED may vary. In certain embodiments, one or more luminescent materials can be patterned on portions of one or more surfaces of a flip chip LED to include one or more stripes, dots, curves, or polygonal shapes. In certain embodiments, multiple luminescent materials can be arranged in different discrete regions or discrete layers on or above a flip chip LED.

[0132] In certain embodiments, the luminescent material may be disposed on the light-transmissive surface of the substrate, and the substrate may include a thickness of at least 120 microns, at least 150 microns, at least 170 microns, at least 200 microns, at least 230 microns, at least 250 microns (optionally, the upper end of the aforementioned minimum thickness values ​​is subject to any of the aforementioned thickness values), or another thickness threshold specified herein. Without intending to be limited by any specified theory of operation, it is currently believed that providing a relatively thick substrate according to one or more of the aforementioned thickness thresholds can improve the conversion efficiency of the flip-chip LED converted by the luminophore due to one or more of the following phenomena: (i) increasing the physical separation (distance) between the outer major (e.g., top) surface of the substrate and the multilayer reflector, and (ii) reducing the luminous flux on the luminescent material disposed on or above the outer surface of the substrate.

[0133] The benefits of reduced optical losses may be more significant and important for larger LED die sizes (e.g., substrate widths of at least about 1.2 mm, at least about 1.4 mm, at least about 2 mm, or larger). Larger die have a greater reliance on reflector reflectivity due to more interactions of light with internal LED reflectors before light escapes. The benefits of reduced optical losses may also be more significant when making warm white (as opposed to cool white) emitters because warm white emitters typically involve a greater amount of light reflected back to the LED chip (e.g., due to conversion of multiple phosphor materials or material layers such as yellow and red layers).

[0134] Figure 4AA flip chip LED 200 is shown according to another embodiment, the LED 200 includes an inner light transmissive surface 204 patterned to be proximate to the semiconductor layer of the LED, and includes a multilayer reflector proximate to the semiconductor layer and "surrounding" the peripheral portion of the semiconductor layer (including the active region). The LED 200 includes a light transmissive (preferably transparent) substrate 205 having an outer major surface 201, a side surface 202, and a patterned surface 204 having a plurality of concave and / or convex features 207. A plurality of (e.g., epitaxially deposited) semiconductor layers 211, 212 sandwiching a light emitting active region 215 are adjacent to the patterned surface 204. In one embodiment, the first semiconductor layer 211 proximate to the substrate 205 implements an n-doped material (e.g., n-GaN) and the second semiconductor layer 212 implements a p-doped material (e.g., p-GaN). The central portion of the plurality of semiconductor layers 211, 212 including the active region 215 extends in a direction away from the substrate 205 to form a mesa 219 that is laterally bounded by at least one recess 229 comprising a passivation material (e.g., silicon nitride as part of the passivation layer 240) and vertically bounded by a surface extension 211A of the first semiconductor layer 211. The at least one recess 229 further includes peripheral "surrounding" portions 230', 232' of the dielectric reflector layer 230 and the metal reflector layer 232, respectively.

[0135] The dielectric reflector layer 230 implements a multilayer reflector in combination with the metal reflector layer 232. The dielectric reflector layer 230 is arranged between the metal reflector layer 232 and the second semiconductor layer 212. In a specific embodiment, the dielectric reflector layer 230 includes silicon dioxide, and the metal reflector layer 232 includes silver. Several conductive vias 231-1, 231-2 are defined in the dielectric reflector layer 230 and are preferably arranged to contact between the second semiconductor layer 212 and the metal reflector layer 232. In a specific embodiment, the conductive vias 231-1, 231-2 include substantially the same material as the metal reflector layer 232. In particular embodiments, at least one (preferably both) of the dielectric reflector layer 230 and the metal reflector layer 232 are disposed over substantially all of the major surface of the mesa 219 terminated by the second semiconductor layer 212 (e.g., at least about 90%, at least about 92%, or at least about 95% of the major (e.g., lower) surface of the mesa portion of the second semiconductor layer 212).

[0136] like Figure 4AAs shown, at least one recess 229 includes a peripheral “surrounding” portion 230′ of the dielectric reflector layer 230 that defines a peripheral portion of the second semiconductor layer 212, the active region 215, and a segment of the first semiconductor layer 211 that forms the mesa 219. The “surrounding” portion 230′ of the dielectric reflector layer 230 further extends to and along a portion of the surface extension 211A of the first semiconductor layer 211. In addition, at least one recess 229 includes a peripheral “surrounding” portion 232′ of the metal reflector layer 232, which is arranged to contact the “surrounding” portion 230′ of the dielectric reflector layer 230 and extend beyond the active region 215, but not to contact the surface extension 211A of the first semiconductor layer 211. Within the at least one recess 229, the "surrounding" portions 230', 232' are peripherally bounded by the passivation material of the passivation layer 240. The presence of the passivation material (e.g., moisture-proof SiN) in the at least one recess 229 that laterally covers the multilayer reflector prevents exposure of any portion of the dielectric reflector layer 230 and the metal reflector layer 232. If any portion of the dielectric reflector layer 230 (e.g., a permeable material such as SiO2) extended to the exposed edge of the LED 200, this would potentially provide a path for moisture to be drawn into contact with portions of the metal (e.g., Al-containing) reflector layer 232, which would be expected to result in deleterious chemical reactions.

[0137] The barrier layer 238 (including portions 238-1 and 238-2) is preferably disposed between the metal reflector layer 232 and the passivation layer 240. In certain embodiments, the barrier layer 238 may be used to prevent metal migration from the metal reflector layer 232 and may include sputtered Ti / Pt followed by evaporated Au, or sputtered Ti / Ni followed by evaporated Ti / Au.

[0138] A passivation layer 240 is additionally disposed between the barrier layer 238 and (i) a first externally accessible electrical contact 251 and (ii) a second externally accessible electrical contact 252, the contacts 251, 252 being disposed along a lower surface 244 of the flip chip LED 200 and separated by a gap 249. In a particular embodiment, the passivation layer 240 comprises silicon nitride. The passivation layer 240 comprises a metal-containing interlayer 245 disposed therein, wherein the interlayer 245 may comprise (or consist essentially of) Al or another suitable metal.

[0139] The first and second arrays of microcontacts 253, 254 extend through the passivation layer 240, with the first array of microcontacts 253 providing conductive communication between the first electrical contact 251 and the doped (e.g., n-doped) first semiconductor layer 211, and the second array of microcontacts 254 providing conductive communication between the second electrical contact 252 and the (e.g., p-doped) second semiconductor layer 212. The first array of microcontacts 253 extends from the first electrical contact 251 (e.g., n-contact), through the passivation layer 240, through the opening defined in the interlayer 245, through the opening 242 defined in the first portion 238-1 of the barrier layer 238, through the opening defined in the first portion 232-1 of the metal reflector layer 232, through the opening defined in the first portion 230-1 of the dielectric reflector layer 230, through the second semiconductor layer 212, and through the active region 215, terminating in the first semiconductor layer 211. Within the opening defined in the interlayer 245, the first portion 238-1 of the barrier layer 238, the first portion 232-1 of the metal reflector layer 232, and the first portion 230-1 of the dielectric reflector layer 230, the dielectric material of the dielectric reflector layer 230 laterally encapsulates the microcontact 253 to prevent electrical contact between the microcontact and the corresponding layers 245, 238, 232, 230. A set of vias 231-1 defined in the first portion 230-1 of the dielectric reflector layer 230 contacts the first portion 230-1 of the dielectric reflector layer 230 and the first semiconductor layer 212, which is beneficial to promote current distribution in the active region 215. A second array of microcontacts 254 extends from the second electrical contact 252 through the passivation layer 240 and through the opening defined in the interlayer 245 to at least one of (i) a second portion 238-2 of the barrier layer 238 and (ii) a second portion 232-2 of the metal reflector layer 232, wherein electrical communication is established between the metal reflector layer 232 and the second semiconductor layer 212 through a set of vias 231-2 defined in the second portion of the dielectric reflector layer 230-2.

[0140] After the formation of the passivation layer 240, one or more side portions 206 extending between the outer surface 201 of the substrate 205 and the surface extension 211A of the first semiconductor layer 211 are not covered with the passivation material. The side portions 206 implement a non-passivated side surface.

[0141] Figure 4B Shows Figure 4A The flip chip LED 200 in FIG. 1 is mounted to a submount 260 and covered with a layer of at least one luminescent material 270. The submount 260 includes a first contact pad 261 and a second contact pad 262 disposed proximate to the electrical contacts 251, 252, respectively. Conductive communication between the contact pads 261, 262 and the electrical contacts 251, 252 may be established using solder flux (not shown) or other conventional means. Figure 4B As shown in FIG. 2 , a layer of at least one luminescent material 270 is arranged to cover the top surface 201 , the non-passivated side surfaces 206 , and the passivated side surfaces (ie, the sidewalls of the passivation layer 240 ), and the submount 260 .

[0142] The electrical operation of the flip chip LED 200 is combined with Figure 2A and Figure 2B The disclosed LED 100 is substantially the same as described. Supplying an electric current between the first electrical contact 251 and the second electrical contact 252 results in light emission being generated through the active region 215. The emission generated through the active region 215 initially propagates in all directions, and the reflector layers 230, 232 serve to reflect the emission in a direction generally toward the substrate 205. When the emission reaches the internal light-transmissive patterned surface 204 disposed between the substrate 205 and the first semiconductor layer 211, the recessed / convex patterned features 207 disposed in or on the internal patterned surface 204 promote refraction at the internal patterned surface 204, rather than reflection, thereby increasing the chances of photons passing through the first semiconductor layer 211 into the substrate 205 and then exiting the LED 200 through the top surface 201 and the non-passivated side surfaces 206. When the surface of the LED 200 is covered with one or more luminescent materials 270 (e.g., Figure 4B ), at least a portion of the emission from the flip chip LED 200 may be up-converted or down-converted by one or more luminescent materials 270. Figure 4B A generally uniform thickness layer of luminescent material 270 is shown covering the entire flip chip LED 200 and submount 260, however, it should be appreciated that in certain embodiments, one or more luminescent materials may be provided according to any suitable configuration disclosed herein.

[0143] Figure 5 The manufacturing process includes four steps according to Figure 4A Photograph of a magnified portion of an assembly of a flip-chip LED (plotted in different quadrants). Figure 5 The upper and lower portions in the figure show the first and second arrays of micro-contacts 253, 254, and the "surrounding" portion 230' of the dielectric reflector layer 230 and the passivation layer 240 arranged in the recess 229. Separation regions 289 devoid of passivation material are provided between different flip chip LEDs, and the separation regions 289 are cut away during the sawing operation of separating the LEDs.

[0144] although FIG. 3A to FIG. 4BA flip chip LED having a substantially planar outer major surface and substantially vertical sidewalls is shown, however, in certain embodiments, a flip chip LED can include a non-planar (e.g., patterned, roughened, textured, or grooved) major outer surface and / or sidewalls that are non-vertical (tilted) relative to the major (e.g., top) outer surface. Such features can further enhance light extraction and / or beam shaping while integrating the benefits of the internal patterned substrate and internal multilayer reflector described above.

[0145] FIG. 6A to FIG. 6C A top view, a side view, and a bottom view of a flip chip LED 300 including a substrate 305 according to one embodiment are shown, respectively, the substrate 305 having an outer surface including an inclined sidewall 302 and a top surface 301 defined by a groove (e.g., a groove including an X shape). The light emitting material layer is not shown, but it should be recognized that in certain embodiments, the flip chip LED 300 may include a light emitting material. The inner light transmissive surface 304 of the substrate 305 is square in shape (e.g., the length of the side may be about 1 mm) and is patterned to include a plurality of concave and / or convex features. The top surface 301 has a smaller area, and the sides of the top surface 301 are shorter than the sides of the inner surface 304 (e.g., the length is about 642 microns) to define an area ratio between the outer surface and the inner surface of about 0.41. In certain embodiments, the area ratio of the outer surface to the inner surface is in a range from about 0.3 to about 0.45. In certain embodiments, the substrate can be larger, such as a square shape having side lengths in a range from 1.15 mm to 2.5 mm or more, in a range from 1.4 mm to 2.0 mm or more, or in another desired range, etc. The functional region 339 preferably includes the features previously described herein, including a semiconductor layer containing an active region, a multilayer reflector, a barrier layer, a passivation layer, an interlayer, and a first array and a second array of microcontacts, etc.; however, to avoid unnecessary repetition, such regions are not shown. The bottom surface of the flip chip LED 300 includes a cathode contact 351 and an anode contact 352 separated by a gap 349, and the gap 349 is preferably less than about 100 microns (e.g., in a range from 10 microns to 100 microns, or in a range from 50 microns to 75 microns). In certain embodiments, the total attachment area (i.e., the combined surface area of ​​the contacts 351, 352) can be greater than 70%, 80%, or 90% of the total surface area of ​​the lower surface 344 of the flip chip LED 300.

[0146] In particular embodiments, one or more flip chip LEDs disclosed herein may be mounted or otherwise included in an LED package, which may include one or more of the following features: a single base or mounting element supporting the one or more LEDs; a single lead frame arranged to direct power to the one or more LEDs; a single reflector (located outside the one or more LEDs) arranged to reflect at least a portion of the emission received from the one or more LEDs; a single lens arranged to transmit at least a portion of the emission generated by the one or more LEDs; a single diffuser arranged to diffuse at least a portion of the emission generated by the one or more LEDs; a single heat sink or heat spreader arranged to disperse or transfer heat generated by the one or more LEDs; a single pair of LED mounting pads arranged for electrical coupling to the one or more LEDs; and a single electrostatic discharge protection element arranged to provide electrostatic discharge protection for the one or more LEDs.

[0147] Fig. 7A and Figure 7B An LED package 399 according to one embodiment is shown, comprising FIG. 6A to FIG. 6C A single flip chip LED 300 is shown. The flip chip LED 300 includes a top surface 301 defining an X-shaped groove 303, with inclined (non-vertical) sidewalls 302 extending to a square-shaped base. The LED package 399 includes a generally square-shaped (e.g., alumina ceramic) base 360, which has a cathode pad 361 and an anode pad 362 separated by a gap 396. The flip chip LED 300 is mounted to bridge the gap 396 to electrically communicate with the cathode pad 361 and the anode pad 362. A lens 390 is arranged above the flip chip LED 300 and the cathode pad 361 and the anode pad 362, and the lens 390 includes a hemispherical center portion and a square-shaped base portion. A cathode contact 371 and an anode contact 372 are arranged on the bottom surface of the base 360 ​​(electrically coupled to the top side cathode pad 361 and the anode pad 362, respectively, through internal vias (not shown)). The heat sink 379 is further disposed along the bottom surface of the submount 360 between the cathode contact 371 and the anode contact 372 .

[0148] In certain embodiments, a lighting device may include an array of multiple flip-chip LEDs disclosed herein. The lighting device may include an LED package, a bulb, a lamp, a light emitting device, and the like.

[0149] Fig. 8A and Figure 8BA plan view and a cross-sectional view of an array of six flip-chip LED wafers 400A-400F electrically coupled in parallel between a cathode pad 484 and an anode pad 486 of a base 480 are shown. In a particular embodiment, the LEDs may be coupled in series or in a series-parallel configuration. An electrostatic discharge (ESD) protection device 494 may be electrically coupled between the cathode pad 484 and the anode pad 486. The illustrated portion of the anode pad 486 may extend between opposing portions of the cathode pad 484, and the flip-chip LED wafer spans a gap 496 defined between the opposing portions. The gap 496 between the cathode pad 484 and the anode pad 486 may be filled with a reflective insulating fill material 492, thereby reducing the absorption of light by the base 480. In a particular embodiment, all of the LED wafers 400A-400F may be disposed under or within a single lens 490. The electrical contacts 451B, 452B, 451E, 452E may be bonded to the cathode pad 484 and the anode pad 486 using solder flux 488. Figure 8B As shown, the flip chip LEDs 400B, 400E each include a conformally coated light emitting material layer 470B, 470E (arranged only on the upper surface and side wall surfaces of the LED); however, in other embodiments, one or more light emitting materials may be provided (e.g., covering the entire LED and portions of the cathode pad 484 and the anode pad 486 and / or the base 480) according to any suitable configuration disclosed herein.

[0150] In certain embodiments, one or more flip chip LEDs can be arranged in a surface mount device, wherein the component layers are mounted to or placed directly on the surface of a printed circuit board (PCB) or other mounting element without the need for an intervening submount.

[0151] To evaluate the potential benefits of the present disclosure, flip chip LEDs incorporating the multilayer reflectors described herein and incorporating internally patterned 1.15 mm square sapphire substrates were constructed and compared to conventional flip chip LEDs manufactured by a process that includes bonding an assembly comprising a growth substrate and epitaxial layers to a carrier substrate with a reflective layer between the carrier substrate and the epitaxial layers, followed by removal of the growth substrate and top surface patterning or texturing of the exposed epitaxial layer surfaces, such conventional device features being described in U.S. Patent Application Publication No. 2008 / 0179611 to Chitnis et al. (incorporated herein by reference). During manufacturing, the flip chip LEDs incorporating the internally patterned sapphire substrates were annealed at an elevated temperature after epitaxial growth in a nitrogen atmosphere for a period of at least 20 minutes. Each LED included a blue peak wavelength of 447 nm, was arranged to excite emission of a yellow phosphor material, and provided aggregate emission having a color rendering index (CRI) value of 80 at a temperature of 85°C. Fig. 9is a plot of K factor values ​​(representing the ratio of white brightness (lumens) to blue brightness (lumens)) of corresponding flip-chip LEDs, where a higher K factor represents a greater white conversion efficiency. Fig. 9 As shown, a 3.6% improvement in K-factor (white conversion efficiency) is obtained using a new flip chip LED device incorporating an internally patterned sapphire substrate, as compared to a comparative flip chip LED device manufactured by the following process, namely, comprising bonding an assembly comprising a growth substrate and an epitaxial layer to a carrier substrate, wherein a reflective layer is disposed between the carrier substrate and the epitaxial layer, followed by removal of the growth substrate and top surface patterning or texturing of the exposed epitaxial layer surface. This improvement in K-factor means that the new flip chip LED device incorporating an internally patterned sapphire substrate exhibits a measured improvement in conversion of blue light to white light over the comparative flip chip LED device. It should be noted that the new flip chip LED device incorporating an internally patterned sapphire substrate does not require the epitaxial layer to be removed from the (SiC) growth substrate and then bonded to a carrier substrate, wherein the reflective layer is disposed intermediately between the epitaxial layer and the carrier substrate, and the new flip chip LED device enables fewer manufacturing steps to be completed at a lower cost. Therefore, the embodiments described herein can allow high performance levels to be obtained at a reduced cost.

[0152] Fig.10 is a plot of normalized luminous flux for three different target color renderings (E2: 70CRI, E5: 75CRI, E7: 80CRI) for a comparative flip-chip LED (made by a process that includes removing the epitaxial layers from a growth substrate and bonding to a carrier with a reflective intermediate layer) and a flip-chip LED incorporating an internally patterned sapphire substrate according to one embodiment. Different CRI values ​​with corresponding E values ​​were obtained by combining emitters with different phosphors or phosphor combinations. Each type of LED was normalized to its E2 brightness; thus, for each E2 value, a value of 1 was obtained. Fig.10 As shown, the novel flip-chip LED incorporating an internally patterned sapphire substrate exhibits less luminous flux loss when combined with a phosphor that produces a higher CRI value. This suggests that the benefits of reduced optical losses associated with the novel internally patterned (e.g., sapphire) substrate combined with a multilayer reflector are more significant when manufacturing warm white (as opposed to cool white) emitters, as warm white emitters typically involve a greater amount of light reflected back to the LED chip (e.g., due to conversion of multiple phosphor materials or material layers such as yellow and red phosphors).

[0153] A flip chip typically includes a top emitting surface and one or more edge emitting surfaces that peripherally bound the top emitting surface. As previously noted, when adding luminescent material to solid-state light emitter chips (including flip chips), it is challenging to achieve one or more of the following goals: (a) ensure adequate coverage of the edge emitting chip surface and edge boundaries (thereby avoiding leakage of unconverted emission); (b) avoid undesirable far-field light characteristics; and (c) reduce light flux losses when diffuse reflective material is applied to the base around the emitter chip. With respect to problem (a), the inventors have discovered that conventional vertical spraying (using a nozzle arranged to release luminescent material in a direction perpendicular to the top emitting surface) is not well suited for depositing luminescent material on edge emitting surfaces and edge boundaries, such that portions of edge surfaces and corners may not be completely covered (or may not be uniformly covered) with luminescent material. When luminescent material coverage is inconsistent or incomplete, unnecessary leakage of unconverted emission may occur in selected areas. With respect to problem (b), when a phosphor-converted solid-state light emitter flip chip including an edge-emitting chip surface is supported by a submount or other substrate, the presence of external light-emitting material on the surface of the submount or substrate that is separate from the flip chip may cause the external light-emitting material to generate additional emissions that interfere with producing desired or consistent far-field light characteristics. With respect to problem (c), if the diffuse reflective material covers the edge-emitting surface, the addition of diffuse reflective material (e.g., titanium dioxide) to the light-emitting device close to the edge-emitting surface of the emitter chip may reduce the overall luminous flux. The various embodiments described below address one or more of the above-described problems.

[0154] Fig.11 is a schematic illustration of an apparatus for vertically spraying a solid-state light emitter chip supported by a substrate. A composition including a light-emitting material can be sprayed onto a solid-state light emitter chip 501 supported by a base or substrate 500 using a nozzle 509, the light emitter chip 501 including a top emitting surface 502 and an edge emitting surface 503. When the nozzle 509 is conventionally oriented to spray the light-emitting material in a direction perpendicular to the top emitting surface 502, it is difficult to ensure that the edge emitting surface 503 (as well as the corners and transitions between the top emitting surface 502 and the edge emitting surface 503) is completely and / or substantially uniformly covered with the light-emitting material. As a result, unnecessary leakage of unconverted emission may occur in selected areas along the edge emitting surface 503 and / or the corners and transitions.

[0155] In order to overcome the limitations associated with conventional vertical spraying methods for adding luminescent materials to solid-state light emitter chips (including flip chips), the inventors have developed an angled spraying method. According to the method, the top and edge emitting surfaces of one or more solid-state light emitter chips can be sprayed using one or more nozzles oriented not perpendicular to the top emitting surface of one or more solid-state light emitter chips, preferably in combination with the relative translation between the angled nozzles and the light emitter chips. In a specific embodiment, one or more nozzles can be used to spray a coating composition including at least one luminescent material onto at least some of the emitting surfaces of one or more solid-state light emitter chips in a first direction, and one or more nozzles can be used to spray a coating composition including at least one luminescent material onto at least some of the emitting surfaces of one or more solid-state light emitter chips in a second direction, wherein the second direction is different from the first direction, and each of the first direction and the second direction is not perpendicular to the top emitting surface of the one or more solid-state light emitter chips. In a particular embodiment, each of the first direction and the second direction is at an angle ranging from about 10 degrees to about 80 degrees, or from about 20 degrees to about 70 degrees, or from about 30 degrees to about 60 degrees, or from about 35 degrees to about 55 degrees, or from about 45 degrees to 50 degrees from the plane defined by the top surface of the one or more solid-state light emitter chips. In a particular embodiment, the spraying consistency on the surface of at least one solid-state light emitter chip can be controlled by modifying the spraying angle of the jet. In a particular embodiment, relative translation can be implemented between one or more angled nozzles and one or more emitter chips, and multiple spraying channels can be used. In a particular embodiment, one or more angled spraying steps can be performed before, after, or simultaneously with one or more vertical or vertical spraying steps. In a particular embodiment, after one or more spraying channels in the first direction, before one or more spraying channels in the second direction begin, the workpiece or substrate carrying one or more solid-state emitters and / or one or more nozzles can be translated and / or rotated. In certain embodiments, a mixture of different luminescent materials (eg, yellow / green and orange / red light emitters) can be included in a single coating composition used to coat one or more solid state light emitter chips.Other combinations of light emitters can be used.

[0156] In a particular embodiment, a combination of top (vertical) and angled spraying steps may include an array of offset lines of area coverage above an array of solid state light emitter flip chips. In a particular embodiment, a combination of top (vertical) and angled spraying steps may include at least one initial top spraying pass, multiple angled spraying passes utilizing at least one rotation of the panel supporting the array of solid state light emitter flip chips, and at least one subsequent top spraying pass. In a particular embodiment, a combination of top (vertical) and angled spraying steps may include at least two initial top spraying passes, at least four angled spraying passes utilizing rotation of the panel supporting the array of solid state light emitter flip chips (e.g., during the second and third angled spraying passes), and at least two subsequent top spraying passes.

[0157] In certain embodiments involving spray coating of one or more luminescent materials over a solid-state light emitter chip, a thermal panel spray coating process such as disclosed in US Pat. No. 8,940,561 (hereby incorporated herein by reference) may be used.

[0158] Fig. 12A is a schematic illustration of an apparatus for angled spray coating of a plurality of solid state light emitter flip chips 511 supported by a substrate 510, wherein each flip chip 511 includes a top emitting surface 512, at least one side emitting surface 513, and a bottom contact 514. One or more nozzles 519A, 519B are disposed above the flip chips 511 and are oriented not perpendicular to the top emitting surface 512, but at an angle "A" relative to the top emitting surface 512 (preferably, within a range from 10 degrees to about 80 degrees or another range disclosed herein). In certain embodiments, one or more vertical nozzles 519C may be used in addition to, or in place of, one of the angled nozzles 519A, 519B. As Fig. 12AAs shown, the first nozzle 519A can be oriented in a first direction, and one or more second nozzles 519B, 519C can be oriented in a second direction, wherein the second direction is different from the first direction, and at least one of the first direction and the second direction is not perpendicular to the top emitting surface 512. In a particular embodiment, both angled spraying and vertical spraying steps can be used simultaneously or according to different channels of the nozzles above one or more solid-state light emitter chips. In a particular embodiment, the number of angled spraying channels and / or the number of angled nozzles can be approximately the same as the number of vertical (top) spraying channels and / or the number of vertical (top) nozzles used to coat one or more solid-state light emitter chips; in other embodiments, the number of angled spraying channels and / or the number of angled nozzles can be greater or less than the comparative number of vertical spraying channels and / or vertical nozzles used to coat one or more solid-state light emitter chips. In a particular embodiment, one or more nozzles can be used, and relative movement between the spray head and / or the panel or substrate supporting the emitter chip can be used to allow the nozzle to coat portions of the emitter chip from different directions. Fig. 12B is a schematic side cross-sectional view of a plurality of solid state light emitter flip chips 511 supported by a substrate 510 after spraying a light emitting material 516 onto the substrate 510 and the top emitting surface 512 and the edge emitting surface 513 of each chip 511 using at least one angled spraying step (optionally in combination with at least one top or vertical spraying step). The use of the angled spraying method disclosed herein allows for improved coverage of the edge emitting surface as well as corners and transitions (between the edge emitting surface and the top emitting surface) by one or more light emitting materials.

[0159] Fig.13 is a schematic illustration of an apparatus for spraying a solid state light emitter flip chip 541 supported by a substrate 540 at an angle using angled nozzles 549A, 549B directed toward different (upper) corners of the flip chip 541. The method allows each nozzle to simultaneously coat multiple edge emitting surfaces 543 of the flip chip 541 as well as at least a portion of the top emitting surface 542. In certain embodiments, a vertical nozzle (not shown) may additionally be used to coat the light emitting material above the top emitting surface 542. Although Fig.13Two angled nozzles 549A, 549B are shown, however, in certain embodiments, a single angled nozzle may be used to coat at least one flip chip in multiple passes from opposite corners of the at least one flip chip. In this embodiment, the at least one flip chip may be rotated between angled spray passes (e.g., by rotating a panel or substrate supporting the at least one flip chip) to allow one angled nozzle to coat the at least one flip chip from multiple directions (e.g., coating on different corners of the same flip chip).

[0160] In a specific embodiment utilizing angled spraying, a method for manufacturing a solid-state light-emitting device for luminophore conversion is provided, the solid-state light-emitting device comprising a solid-state emitter chip comprising a plurality of emitting surfaces (including a top emitting surface and including at least one edge emitting surface arranged along the periphery of the top emitting surface). The method comprises: spraying a coating composition comprising at least one luminescent material onto at least some of the plurality of emitting surfaces in a first direction using at least one nozzle; and spraying a coating composition comprising at least one luminescent material onto at least some of the plurality of emitting surfaces in a second direction using at least one nozzle; wherein the first direction is different from the second direction, and at least one of the first direction and the second direction is not perpendicular to the top emitting surface. In a specific embodiment, the angle between the first direction and the top emitting surface is in a range from 10 degrees to 80 degrees. In a specific embodiment, both the first direction and the second direction are not perpendicular to the top emitting surface. In a specific embodiment, the first direction or the second direction may be perpendicular to the top emitting surface. In a specific embodiment, the method further includes: dispersing a light-transmitting chamfer-forming material to contact at least one edge emitting surface and to contact a substrate located below the solid-state light emitter chip, thereby generating a chamfer along at least one edge emitting surface, wherein the spraying of a coating composition comprising at least one luminescent material in a first direction and a second direction using at least one nozzle includes spraying the coating composition over the chamfer. In a specific embodiment, the chamfer includes a maximum height close to at least one edge emitting surface, the chamfer includes a minimum height away from at least one edge emitting surface, and the maximum height is not higher than the horizontal plane of the top emitting surface. In a specific embodiment, the chamfer-forming material includes silicone and / or at least one luminescent material. In a specific embodiment, the method further includes: during the spraying of the coating composition comprising at least one luminescent material in a first direction and a second direction using at least one nozzle, relative movement is performed between the at least one nozzle and the solid-state light emitter chip. As disclosed herein, in a specific embodiment, the solid-state light emitter chip includes a flip chip.

[0161] As an alternative to or in addition to using an angled spraying method, one or more light-transmitting chamfers may be formed along the edge emitting surface of one or more solid-state emitter chips to improve the integrity and / or uniformity of coating the edge emitting surface with one or more luminescent materials. The chamfer serves as a balancing element to produce a less steep and more gradual transition between the edge emitting surface of the solid-state emitter chip and the adjacent top surface of the base or substrate supporting the solid-state emitter chip. After the chamfer is formed around the periphery of the solid-state emitter chip, the chamfer and the top emitting surface of the emitter chip may be sprayed with one or more luminescent materials. In a specific embodiment, the spraying of the luminescent material over the chamfer (with the top emitting surface) may be performed using one or more nozzles arranged perpendicular to the top emitting surface of the solid-state emitter chip. In other embodiments, the spraying of the luminescent material over the chamfer (with the top emitting surface) may be performed using one or more nozzles arranged not perpendicular to the top emitting surface of the solid-state emitter chip. In a particular embodiment, the chamfer can be formed by dispersing a chamfer forming material such as silicone around the edge emitting surface of the solid state emitter chip, and then allowing the chamfer material to absorb around the periphery of the solid state emitter and cure (harden). In a particular embodiment, the chamfer material includes a maximum height close to at least one edge emitting surface and includes a minimum height away from at least one edge emitting surface, wherein the maximum height is no higher than the horizontal plane of the top emitting surface. In a particular embodiment, the chamfer can be transparent in nature. In other embodiments, the chamfer can include one or more luminescent materials arranged to convert the wavelength of light received from the solid state light emitter chip. Whether or not the chamfer includes a luminescent material, the chamfer can be covered by an additional coating of one or more luminescent materials.

[0162] Fig.14A 5 is a schematic side cross-sectional view of a solid-state light emitter flip chip 521 (including a top emitting surface 522, an edge emitting surface 523, and a bottom contact 524) supported by a substrate 520, and a light-transmitting transparent chamfer material 525 is arranged around the periphery of the chip 521 and in contact with the edge emitting surface 523 of the chip 521. Fig.14A As shown, chamfer material 525 includes a maximum height proximate edge emitting surface 523 and includes a minimum height distal from edge emitting surface 523 , wherein the maximum height is no higher than the level of top emitting surface 522 . Fig. 14B yes Fig.14ASchematic side cross-section of a chip 521 in FIG. 5 with a chamfer material 525 covered by a coating of a luminescent material 526. The presence of the chamfer material 525 allows for improved coverage of the light emitter chip 521 by a layer 526 of one or more luminescent materials, thereby reducing or eliminating leakage of unconverted light (i.e., light emitted by the solid-state light emitter chip 521 that does not pass through the luminescent material layer 526).

[0163] In a particular embodiment, a solid-state lighting device includes: a base; a solid-state emitter chip supported by the base, the solid-state emitter chip including a plurality of emitting surfaces including a top emitting surface and including at least one edge emitting surface arranged along the periphery of the top emitting surface; and a light-transmitting chamfered material arranged on or above the base around the periphery of the solid-state emitter chip and arranged to contact at least one edge emitting surface. The presence of the chamfered material along at least one edge emitting surface can facilitate coating (e.g., spraying) of a luminescent material (e.g., a phosphor) over at least one edge emitting surface. In a particular embodiment, at least one luminescent material is arranged over the top emitting surface and over at least a portion of the chamfered material. In a particular embodiment, the chamfered material includes a maximum height proximate to at least one edge emitting surface, the chamfered material includes a minimum height away from at least one edge emitting surface, and the maximum height is no higher than the level of the top emitting surface. In a particular embodiment, the chamfered material includes silicone and / or at least one luminescent material. As disclosed herein, in a particular embodiment, the solid-state emitter chip includes a flip chip.

[0164] Fig.15A 5 is a schematic side cross-sectional view of a solid-state light emitter flip chip 531 (including a top emitting surface 532, an edge emitting surface 533, and a bottom contact 534) supported by a substrate 530, and a light-transmitting chamfered material 535 includes at least one luminescent material arranged around the periphery of the chip 531 and in contact with the edge emitting surface 533 of the chip 531. Fig.15A As shown, chamfer 535 includes a maximum height proximal to edge emitting surface 533 and includes a minimum height distal to edge emitting surface 533 , wherein the maximum height is no higher than the level of top emitting surface 532 . Fig. 15B yes Fig.15A535 is covered by a coating of luminescent material 536. The presence of chamfer 535 allows for improved coverage of emitter chip 531 by luminescent material (including luminescent material contained in chamfer material 535 and luminescent material contained in covering luminescent material layer 536), thereby reducing or eliminating leakage of uncovered light (i.e., light emitted by solid-state emitter chip 531 that does not undergo interaction with luminescent material contained in chamfer material 535 or luminescent material layer 536). In certain embodiments, one or more of the luminescent material composition, luminescent material concentration, and luminescent material particle size may be different between chamfer 535 and luminescent material layer 536. In other embodiments, some or all of the luminescent material composition, luminescent material concentration, and luminescent material particle size in chamfer 535 and luminescent material layer 536 may be substantially the same.

[0165] Fig.16A is a top view photograph of a light emitting device including a solid state light emitter flip chip 551 and an electrostatic discharge (ESD) chip 559 mounted to a base 550 before chamfer formation. Fig. 16B After the light-transmitting transparent chamfer 555 arranged on the base 550 around the periphery of the flip chip 551 and arranged to contact the edge emitting surface of the flip chip 551 is formed, according to Fig.16A Chamfer 555 may be in contact with ESD chip 559. Chamfer 555 serves as a balancing element to create a less steep and more gradual transition between the edge emitting surface of flip chip 551 and submount 550.

[0166] Fig.17A is a top view photograph of a light emitting device including a solid state light emitter flip chip 561 after adding a light transmissive chamfer 565 containing a light emitting material arranged on a base 560 around the periphery of the flip chip 561 and arranged to contact the edge emitting surface of the flip chip 561. Fig. 17B After the light emitting material 566 is sprayed on the flip chip 561, the chamfer 565, and the base 560, Fig.17A A top view photo of the light emitting device in the.

[0167] Fig.18 is a top view photograph of six interconnected light emitting devices, each including a hemispherical lens overlying a coating of luminescent material and a solid-state light emitter flip chip supported by a submount, with no chamfer material between the flip chip and the submount for each device. Under each hemispherical lens, the rectangular outline of each flip chip is visible.

[0168] Fig.19is a top view photograph of six interconnected light emitting devices, each including a hemispherical lens overlying a coating of luminescent material and a solid-state light emitter flip chip supported by a submount, each device including a chamfer disposed peripherally around the flip chip to contact the submount. Because each chamfer acts as a balancing element to create a less abrupt and more gradual transition between the edge emitting surface of the flip chip and the submount, Fig.19 Under each hemispherical lens, the outline of each rectangular flip chip is not visible.

[0169] In a specific embodiment, a method for manufacturing a solid-state light-emitting device for luminophore conversion is provided, the solid-state light-emitting device comprising a solid-state emitter chip having a plurality of emitting surfaces (including a top emitting surface and including at least one edge emitting surface arranged along the periphery of the top emitting surface). The method comprises: dispersing a chamfer forming material to contact at least one edge emitting surface and to contact a substrate located below the solid-state emitter chip, and thereby generating a chamfer along at least one edge emitting surface; and spraying a coating composition comprising at least one luminescent material onto the top emitting surface and the chamfer using at least one nozzle. In a specific embodiment, the chamfer comprises a maximum height of the proximal end of at least one edge emitting surface, the chamfer comprises a minimum height of the distal end of at least one edge emitting surface, and the maximum height is lower than the top emitting surface. In a specific embodiment, using at least one nozzle comprises: spraying the coating composition onto the top emitting surface and the chamfer in a first direction, and comprises: spraying the coating composition onto the top emitting surface and the chamfer in a second direction, wherein the first direction is different from the second direction, and each of the first direction and the second direction is not perpendicular to the top emitting surface. In a specific embodiment, the chamfer forming material comprises silicone and / or at least one luminescent material. As disclosed herein, in certain embodiments, the solid state emitter chip comprises a flip chip.

[0170] As previously proposed, when a solid-state light emitter flip chip including a light emitter conversion of an edge-emitting chip surface is supported by a base or other substrate, the presence of external light-emitting material on the surface of the base or substrate separated from the flip chip can cause the external light-emitting material to generate additional emission that interferes with the generation of desired or consistent far-field light characteristics. To address this problem, the inventors have developed a method for selectively generating islands of light-emitting material covering one or more emitting surfaces of a solid-state light emitter chip (e.g., a flip chip) using a template while preventing adjacent surfaces of the base or substrate from being coated with the light-emitting material. The method includes: generating a template defining one or more windows corresponding to one or more solid-state emitter chips, registering the template on a substrate or base supporting the one or more solid-state emitter chips to expose the surface of the one or more solid-state emitter chips accessible through the window, applying a coating of one or more light-emitting materials to the exposed surface of the one or more solid-state emitter chips, and removing the template. The dimensions of the template (including the placement and dimensions of the window, the thickness of the template, etc.) can be used to control the area of ​​the one or more solid-state emitter chips that receive the light-emitting material. In particular embodiments, a first template layer having windows providing access to one or more ESD devices can be used to allow the ESD devices to be selectively coated with a reflective material, and a second template layer having windows providing access to one or more solid-state emitter chips (e.g., flip chips) can be used to allow one or more solid-state emitter chips to be selectively coated with one or more light-emitting materials.

[0171] Fig. 20A 601C. 608A-608C is a perspective schematic assembly diagram of a substrate 600 supporting three solid-state light emitter chips 601A-601C before a template layer 607 is applied to the substrate 600. The substrate 600 may include a base area for the solid-state light emitter chips 601A-601C. Each solid-state light emitter chip 601A-601C may include a top emitting surface 602A-602C and an edge emitting surface 603A-603C. The template layer 607 defines windows 608A-608C arranged to be registered with the solid-state emitter chips 601A-601C.

[0172] Fig. 20B After applying a template layer 607 to the substrate 600 having windows 608A-608C registered for the solid-state light emitter chips 601A-601C, Fig. 20A Schematic diagram of the substrate 600, the light emitter chips 601A-601C, and the template layer 607. Fig. 20BAs shown, in a particular embodiment, the windows 608A-608C can be slightly larger than the solid-state light emitter chips 601A-601C to expose not only the top emitting surfaces 602A-602C, but also the edge emitting surfaces 603A-603C of the solid-state light emitter chips 601A-601C to receive a coating of luminescent material. In a particular embodiment, each window 608A-608C can have an edge length that is 10 to 30 percent greater than the edge length of the corresponding solid-state light emitter chip 601A-601C.

[0173] Fig. 20C After the luminescent material 606A-606C is applied to the emitting surfaces (eg, the top emitting surfaces 602A-602C and the edge emitting surfaces 603A-603C) of the solid-state light emitter chips 601A-601C, and then removed Fig. 20B The template layer 607 shown in FIG. Fig. 20B Schematic diagram of a three-dimensional substrate 600 and solid-state light emitter chips 601A-601C.

[0174] Fig.21A 6 is a top view photograph of nine interconnected light emitting devices, each comprising a solid state light emitter flip chip 611 supported by a substrate 610, after applying light emitting material 616 to the emitting surface of the solid state light emitter flip chip 611 through a template window, with the majority of each substrate 610 being free of light emitting material. If desired, narrow tab portions 618 of the substrate 610 are arranged to allow the nine light emitting devices to be cut and separated from each other. The substrate 610 may be coated with a diffuse reflective material such as titanium dioxide. Fig. 21B yes Fig.21A An enlarged view of a solid state light emitter flip chip 611 coated with a light emitting material and located on a substrate 610 is shown.

[0175] In a specific embodiment, a method for manufacturing at least one luminophore-converted solid-state emitter chip includes: positioning a template on a substrate supporting at least one solid-state emitter chip including at least one light emitting surface, the template including at least one window in register with the at least one solid-state emitter chip to expose the at least one light emitting surface; and applying at least one light emitting material on the exposed at least one light emitting surface of the at least one solid-state emitter chip, and the presence of the template prevents at least a portion of the substrate from receiving the at least one light emitting material. In a specific embodiment, the at least one light emitting surface includes a top emitting surface and at least one edge emitting surface arranged along the periphery of the top emitting surface, and wherein the exposed at least one light emitting surface includes at least a portion of the top emitting surface and the at least one edge emitting surface. In a specific embodiment, the method further includes removing the template from the substrate. In a specific embodiment, the at least one solid-state emitter chip includes a plurality of solid-state emitter chips, and the method further includes: dividing the substrate into a plurality of sections, each section including at least one solid-state emitter chip from the plurality of solid-state emitter chips. In a specific embodiment, the at least one solid-state emitter chip includes a plurality of solid-state emitter chips, and the at least one window includes a plurality of windows. As disclosed herein, in a specific embodiment, the solid-state emitter chip includes a flip chip.

[0176] In a particular embodiment, the solid-state light emitter chip may be sprayed before being placed on the base. In a particular embodiment, the solid-state light emitter chips may be arranged in an array on a releasable tape and sprayed with a coating composition including one or more luminescent materials (e.g., using the angled spraying technique disclosed herein). In a particular embodiment, the releasable tape may include a releasable adhesive having an adhesive property, and the adhesive property is weakened after exposure to energy (e.g., ultraviolet or other radiation, thermal energy, etc.). After spraying, the releasable tape may be exposed to energy to reduce the adhesion of the releasable adhesive material, and the coated solid-state emitter chip may be removed from the tape and placed on one or more bases or other support structures as needed. In a particular embodiment, an automated (e.g., robotic) pick-and-place device may be used to selectively remove the coated solid-state emitter chips from the releasable tape and place the chips on the base of the solid-state emitter device. In this way, the solid-state emitter chip may be coated with one or more luminescent materials without causing the luminescent material to be coated on the base, thereby eliminating the poor far-field characteristics that may be generated due to the entire base surface being covered with luminescent materials.

[0177] Fig.22Ais a perspective schematic illustration of an assembly of six solid state light emitter flip chips 701 supported by releasable tape 700 prior to being sprayed with luminescent material (eg, using an angled nozzle 709). Each flip chip 701 includes a top emitting surface 702 and an edge emitting surface 703. Fig. 22B After coating the solid state light emitter flip chip 701 and the releasable tape 700 with the luminescent material 706, Fig.22A , a releasable tape 700 is arranged in proximity to an energy source 711. Energy source 711 can be used to supply energy to the releasable tape 700 to reduce the adhesion of the adhesive material, thereafter allowing the coated solid state light emitter flip chip 701 to be removed. Fig. 22C After applying energy to reduce the adhesion of the releasable tape 700 and removing the solid-state light emitter flip chip 701 coated with a single light emitting material, Fig. 22B Schematic illustration of a perspective view of an assembly in FIG. The coated flip chip 701 includes a luminescent material 706 located on a top emitting surface 702 and an edge emitting surface 703 . Fig. 22C The coated flip chip 701 in can be removed and placed on a submount of a solid state emitter device using a pick and place apparatus or other suitable apparatus.

[0178] Fig.23A is a top view photograph of an assembly of sixteen solid state light emitter flip chips supported by releasable tape after angled spray coating with luminescent material. Each coated flip chip is elevated relative to the releasable tape. Fig. 23B yes Fig.23A An enlarged perspective photograph of a portion of the assembly shows that the top emitting surface and the edge emitting surface of the flip chip are completely coated with the luminescent material.

[0179] Fig.23C is a top view photograph of a layer of releasable tape coated with luminescent material after sixteen solid state light emitter flip chips coated with luminescent material have been removed, thereby exposing sixteen square areas of the releasable tape.

[0180] Fig.23D is a side perspective photograph of a solid state light emitter flip chip coated with luminescent material after the chip has been removed from the layer of releasable tape. Fig.23D Shown are the top emitting surface and the edge emitting surface of the flip chip fully coated with the luminescent material.

[0181] Fig.24A is a top view photograph of a plurality of interconnected light emitting devices, each comprising a solid-state light emitter flip chip coated with a light emitting material placed on a base. FIG. 22A to FIG. 22C Each flip chip is coated with the releasable tape coating method described above. Fig.24A As shown, the submount does not contain a luminescent material, but a luminescent material coating is present on each flip chip. Fig. 24B yes Fig.24A An enlarged top view photograph of a portion of a single light emitting device in FIG. Fig.24C yes Fig.24A An enlarged stereoscopic photograph of a portion of a single light emitting device in FIG.

[0182] In a specific embodiment, a method for manufacturing a solid-state light-emitting device for at least one luminophore conversion includes: arranging a plurality of solid-state emitter chips on a releasable adhesive material; coating the plurality of solid-state emitter chips with at least one luminescent material; applying energy to the releasable adhesive material to reduce the adhesion of the releasable adhesive material; and removing the coated plurality of solid-state emitter chips from the releasable adhesive material. In a specific embodiment, each of the plurality of solid-state emitter chips comprises a flip chip. In a specific embodiment, the coating step comprises spraying a coating composition comprising at least one luminescent material onto the plurality of solid-state emitter chips using at least one nozzle. In a specific embodiment, the spraying of the coating composition comprises: spraying the coating composition in at least one direction that is not perpendicular to the top emission surface of each of the plurality of solid-state emitter chips. In a specific embodiment, the removal step comprises: individually picking up each coated solid-state emitter chip of the plurality of solid-state emitter chips from the releasable adhesive material, and placing each coated solid-state emitter chip on at least one substrate or base. As disclosed herein, in a specific embodiment, the plurality of solid-state emitter chips comprises a plurality of flip chips.

[0183] In particular embodiments, the presence of a flip chip that is significantly elevated relative to a base that includes a reflective material coating (e.g., titanium dioxide) can reduce or minimize the probability that the reflective material coating would otherwise be disposed above (and reflect emission from) at least one edge emitting surface of the flip chip. Fig.25Ais a schematic side cross-sectional view of a portion of a light emitting device including a solid state light emitter flip chip 801 including bottom contacts 813, 814 mounted to a submount 800 with solder material regions 815, 816 at a conventional height (e.g., a vertical distance of about 10 microns separating the edge emitting surface 803 (or bottom semiconductor layer 808) of the flip chip 801 from the upper surface of the submount 800). In a particular embodiment, the top emitting surface 802 and the edge emitting surface 803 may be coated with one or more luminescent materials (not shown). A reflective layer 807 is disposed above the submount 800 and is arranged to contact the edge emitting surface 803 of the flip chip 801. When the reflective layer 807 contacts the edge emitting surface 803, the reflective layer 807 tends to adversely reflect the emission back into the flip chip 801, thereby reducing the luminous flux of the flip chip 801. When the titanium dioxide material contacts the edge emitting surface of the flip chip, the inventors observed a luminous flux reduction in the range of 2% to 3.6%.

[0184] like Fig.25B As shown in , a preferred arrangement to reduce or eliminate light flux losses involves significantly elevating the flip chip relative to the submount. Fig.25B821, the bottom contacts 833, 834 of the solid-state light emitter flip chip 821 are mounted to the submount 820 with solder material regions 835, 836 at a conventional height (e.g., the edge emitting surface 823 (or bottom semiconductor layer 828) of the flip chip 821 is separated from the upper surface of the submount 820 by at least about 15 microns, at least about 20 microns, at least about 25 microns, at least about 30 microns, or another threshold distance specified herein). In a specific embodiment, any one or more of the aforementioned minimum heights can be limited by an upper limit of not more than about 70 microns, not more than about 60 microns, not more than about 50 microns, (not) more than about 40 microns, or not more than about 30 microns. In a specific embodiment, the top emitting surface 822 and the edge emitting surface 823 can be coated with one or more light emitting materials (not shown). The diffuse reflective layer 827 is disposed above the base 820, but the diffuse reflective layer 827 does not contact the edge emitting surface 823 of the flip chip 821 due to the elevation of the flip chip 821 relative to the base 820. In certain embodiments, the elevation of the flip chip 821 can be achieved by increasing the thickness of the contacts 833, 834, by increasing the thickness of the solder material regions 835, 836, or by increasing the thickness of both the contacts 833, 834 and the solder material regions 835, 836. Raising the solid state emitter chip relative to the base (e.g., using an increased thickness of solder material) has made counters into conventional practice because it can be shown to inhibit heat transfer, produce cracks, and / or produce difficulties in determining the level of the solid state emitter chip relative to the base. For this reason, certain embodiments propose an upper threshold of about 70 microns for the separation distance. To reduce the probability of cracks, in certain embodiments, the solder material (e.g., solder paste or flux) can include gold tin solder paste.

[0185] In a specific embodiment incorporating an elevated solid-state emitter chip, a solid-state light emitting device includes: a submount including a bottom plate and a plurality of electrical contact areas; a diffuse reflective material disposed over at least a portion of the submount; at least one flip-chip light emitting diode including a p-electrode, an n-electrode, a top emitting surface, and at least one edge emitting surface disposed along a periphery of the top emitting surface; and a solder material disposed to establish contact between the p-electrode and at least one first contact area of ​​the plurality of electrical contact areas, and disposed to establish contact between the n-electrode and at least one second contact area of ​​the plurality of electrical contact areas; wherein at least one edge emitting surface is elevated to a height of at least about 15 microns, at least about 20 microns, at least about 25 microns, or at least about 30 microns above the bottom plate of the submount. In a specific embodiment, any one or more of the aforementioned minimum heights may be limited by an upper limit of no greater than about 70 microns, no greater than about 60 microns, no greater than about 50 microns, no greater than about 40 microns, or no greater than about 30 microns. The presence of a flip chip that is significantly elevated relative to a base including a reflective material coating can reduce or minimize the probability that the reflective material coating is otherwise disposed on at least one edge emitting surface of the flip chip (and reflects the emission of at least one edge emitting surface). In a specific embodiment, at least one luminescent material is disposed on the top emitting surface and at least one edge emitting surface. In a specific embodiment, the solder material includes flux or solder paste (e.g., gold tin solder paste). In a specific embodiment, a light-transmitting chamfer material can be arranged to form a chamfer in contact with at least one edge emitting surface and in contact with a base plate or a diffuse reflective material. In a specific embodiment, the chamfer includes a maximum height of the proximal end of at least one edge emitting surface, the chamfer includes a minimum height of the distal end of at least one edge emitting surface, and the maximum height is not higher than the level of the top emitting surface. In a specific embodiment, the chamfer material includes silicone and / or at least one luminescent material. In a specific embodiment, the diffuse reflective material includes titanium dioxide.

[0186] In certain embodiments, the elevated solid state light emitter chips disclosed herein can be complementary to the peripheral chamfers containing luminescent materials disclosed herein to reduce the probability of unconverted light being emitted along the lower lateral periphery of the flip chip.

[0187] Although specific embodiments previously described herein involve the need to avoid contact between reflective material and the edge emitting surface of a solid state emitter flip chip in order to extract maximum lumens, in other embodiments, it may be desirable to position reflective material along or against the edge emitting surface of a solid state emitter flip chip (or against the luminescent material covering the edge emitting surface of the solid state emitter flip chip) to provide desired beam characteristics. Determining whether to position reflective material against or along the edge emitting surface of a solid state emitter flip chip represents a trade-off between increasing light extraction and reducing the potential need for secondary optics. The edge emitting surface is responsible for emitting approximately 2% to 3% of the total lumens. However, most of the lumens of a solid state light emitter flip chip are emitted from the primary (e.g., top) emitting surface. Because most of the light generated by the solid state light emitter flip chip is emitted from the primary (e.g., top) emitting surface, it is desirable to avoid obstruction of the primary (e.g., top) emitting surface by reflective material.

[0188] A method for providing a reflective material (such as titanium dioxide, etc.) against or adjacent to the side surface of one or more solid-state light emitter flip chips involves spreading a liquid containing the reflective material and allowing the material to surround the flip chip. In a specific example, specifically, when the luminescent material is coated on the surface of the flip chip, the reflective material may tend to be undesirably adsorbed on the main (top) emitting surface. To avoid this possibility, in a specific embodiment, the anti-wicking material can be arranged on the top surface of at least a portion of the luminescent material layer covering the top emitting surface of the solid-state light emitter flip chip. In a specific embodiment, the anti-wicking material is applied as a droplet that can be at least partially bent via a thermal method. In a specific embodiment, the anti-wicking material includes a light-transmitting adhesive such as a silicone resin preferably containing fused silica (e.g., 10 micron glass beads). In a specific embodiment, the anti-wicking material includes a silicone resin and fused silica present in a weight percentage of 2:1 to 1:1 to provide good control of the shape and position of the droplets of the anti-wicking material. Although glass beads (fused silica) tend to scatter light, however, glass beads with similar refractive indices tend to generate primarily small angle scattering, which tends to mix the transmitted light emission without significantly attenuating the transmission. In certain embodiments, low concentrations of additional scattering materials (e.g., fused silica or titanium dioxide) may also be present in the anti-wicking material, but preferably, the concentration is not so high as to significantly attenuate light transmission.

[0189] Fig.26842 and 843, respectively, are covered with a top portion 846A and a side portion 846B of a light emitting material layer 846 deposited by top spraying (i.e., spraying from a nozzle oriented perpendicular to the top emitting surface 842). Because the light emitting material layer 846 is deposited by top spraying, the side portion 846B is thinner than the top portion 846A. Drops of anti-wicking material 849 are arranged on the top portion 846A of the light emitting material layer 846, and a reflective material layer 847 is arranged to contact the side portion 846B of the light emitting material layer 846. The presence of the anti-wicking material 849 prevents the reflective material layer 847 from being adsorbed on the top portion 846A of the light emitting material layer 846.

[0190] Fig. 27 85 is a schematic side cross-sectional view of a solid state light emitter flip chip 851 including a top emitting surface 852 and an edge emitting surface 853, wherein the top emitting surface 852 and the edge emitting surface 853 are respectively covered with a top portion 856A and a side portion 856B of a light emitting material layer 856 deposited by both top (vertical) spraying and angled (non-vertical) spraying. Due to the use of both top (vertical) spraying and angled (non-vertical) spraying, the side portion 856B and the top portion 856A can have approximately the same thickness. A drop of anti-wicking material 859 is arranged on the top portion 856A of the light emitting material 856, and a reflective material layer 857 is arranged to contact the side portion 856B of the light emitting material 856. The presence of the anti-wicking material 859 prevents the reflective material layer 857 from being adsorbed on the top portion 856A of the light emitting material layer 856.

[0191] Fig.28 86 is a schematic side cross-sectional view of a solid state light emitter flip chip 851 including a top emitting surface 862 and an edge emitting surface 863, wherein the top emitting surface 862 and the edge emitting surface 863 are respectively covered with a top portion 866A and a side portion 866B of a light emitting material layer 866 deposited by both top (vertical) spraying and angled (non-vertical) spraying. A light transmissive chamfer material 865 containing light emitting material is arranged in contact with the side portion 866B of the light emitting material layer 866, and a light reflecting material layer 867 is arranged in contact with a portion of the chamfer material 865. The chamfer material 865 is preferably smooth in nature and is not conducive to adsorption by the light reflecting material 867, which can be arranged on a substrate or base (not shown) supporting the solid state light emitter flip chip 861.

[0192] Fig.29 and Fig.28 Much the same, but without the reflective material layer. Fig.29 87 is a schematic side cross-sectional view of a solid state light emitter flip chip 871 including a top emitting surface 872 and an edge emitting surface 873, wherein the top emitting surface 872 and the edge emitting surface 873 are respectively covered with a top portion 876A and a side portion 876B of a light emitting material layer 876 deposited by both top (vertical) spraying and angled (non-vertical) spraying. A light transmissive chamfer material 875 containing the light emitting material is arranged in contact with the side portion 876B of the light emitting material layer 876.

[0193] Fig.30 is a side cross-sectional schematic illustration of a solid state light emitter flip chip 881 arranged to be supported by a substrate or base (not shown), the flip chip 881 including a top emitting surface 882 and an edge emitting surface 883. A chamfered reflective material layer 885 is arranged to contact the edge emitting surface 883. The presence of the chamfered reflective material layer 885 enables a luminescent material layer 886 (including a top portion 886A and an angled side portion 886B) to be deposited by top (vertical) spraying over the top emitting surface 882 and the chamfered reflective material layer 885 without involving non-uniformities of the angled side portion 886B of the luminescent material layer 886. The chamfered reflective material layer 885 along the edge emitting surface 883 prevents potential non-uniformities in light conversion and accompanying differences in light color that may otherwise exist in the absence of the reflective material 885.

[0194] Fig.31 891 is a side cross-sectional schematic illustration of a solid state light emitter flip chip 891 arranged to be supported by a substrate or submount (not shown). The flip chip 891 includes a top emitting surface 892 and an edge emitting surface 893 covered with a top portion 896A and a side portion 896B of a light emitting material layer 896 deposited by both top (vertical) spraying and angled (non-vertical) spraying, respectively. A base portion 896C of the light emitting material layer 896 is arranged to cover the substrate or submount supporting the flip chip 891. Drops of anti-wicking material 899 are arranged on top of the top portion 896A of the light emitting material layer 896, and a reflective material layer 897 is arranged to contact the side portion 896B of the light emitting material layer 896. The presence of the anti-wicking material 899 prevents the reflective material layer 897 from being adsorbed on the top portion 896A of the light emitting material layer 896.

[0195] Fig.329 is a side cross-sectional schematic illustration of a solid state light emitter flip chip 901 arranged to be supported by a substrate or submount (not shown). The flip chip 901 includes a top emitting surface 902 and an edge emitting surface 903 covered with a top portion 906A and a side portion 906B of a light emitting material layer 906 deposited by both top (vertical) spraying and angled (non-vertical) spraying, respectively. A base portion 906C of the light emitting material layer 906 is arranged to cover the substrate or submount supporting the flip chip 901. A reflective material layer 907 is disposed on the base portion 906C of the light emitting material 906 separated from the side portion 906B of the light emitting material layer 906.

[0196] Fig.33 91 is a schematic side cross-sectional view of a solid state light emitter flip chip 911 arranged to be supported by a substrate or submount (not shown), the flip chip 911 including a top emitting surface 912 and an edge emitting surface 913. A chamfered reflective material layer 915 is arranged to contact the edge emitting surface 913. A luminescent material layer 916 is deposited by top (vertical) spraying, thereby producing a top portion 916A located above the top emitting surface 912, a side portion 916B located above the chamfered reflective material layer 915, and a base portion 916C located above the substrate or submount. Drops of anti-wicking material 919 are arranged on the top portion 916A of the luminescent material layer 916, and a reflective material layer 917 is arranged to contact the side portion 916B of the luminescent material layer 916. The presence of the anti-wicking material 919 prevents the reflective material layer 917 from being adsorbed on the top portion 916A of the luminescent material layer 916.

[0197] The embodiments disclosed herein can provide one or more of the following beneficial technical effects: reducing optical losses in flip chip LEDs (particularly significant and / or beneficial for large wafer sizes and / or when generating warm white light); reducing manufacturing costs when manufacturing flip chip LEDs; reducing cycle times for manufacturing flip chip LEDs; obtaining similar lighting performance using cost-reduced manufacturing methods; improving the mechanical reliability of flip chip LEDs; simplifying device manufacturing; reducing leakage of unconverted emission from LEDs coated with emitters; and reducing adsorption of reflective material onto the portion of the top emitter layer covering the emitting surface of the flip chip LED.

[0198] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the claims that follow.

Claims

1. A light emitting device comprising a flip chip light emitting diode, the flip chip light emitting diode comprising: A plurality of semiconductor layers, including a first semiconductor layer containing a first type of dopant and a second semiconductor layer containing a second type of dopant, wherein a light emitting active region is arranged between the first semiconductor layer and the second semiconductor layer; a multilayer reflector disposed proximate to the plurality of semiconductor layers, the multilayer reflector comprising a metal reflector layer and a dielectric reflector layer, wherein the dielectric reflector layer is disposed between the metal reflector layer and the plurality of semiconductor layers; a passivation layer disposed between the metallic reflector layer and (i) a first electrical contact and (ii) a second electrical contact, wherein the first electrical contact is disposed in conductive electrical communication with the first semiconductor layer and the second electrical contact is disposed in conductive electrical communication with the second semiconductor layer; and a first array of electrically conductive microcontacts extending through the passivation layer from a surface of the passivation layer in contact with the first electrical contacts and providing electrical communication between the first electrical contacts and the first semiconductor layer; a second array of electrically conductive microcontacts extending through the passivation layer from a surface of the passivation layer in contact with the second electrical contacts and providing electrical communication between the second electrical contacts and the second semiconductor layer; a barrier layer comprising a plurality of metals disposed between the metal reflector layer and the passivation layer, wherein at least one of the first array of conductive microcontacts and the second array of conductive microcontacts extends through the barrier layer; The plurality of semiconductor layers form a mesa, the peripheral portions of each of the first semiconductor layer, the light emitting active region and the second semiconductor layer form side walls that laterally define at least one recess of the mesa, the first semiconductor layer has a surface extension that vertically defines the mesa, and the mesa has a main surface that is laterally defined by the side walls, the main surface is of uniform height relative to the surface extension, and the multilayer reflector is arranged above at least 90% of the main surface of the mesa and between the mesa and the passivation layer. 2 . The light emitting device of claim 1 , further comprising a metal-containing interlayer disposed within the passivation layer between the barrier layer and (i) the first electrical contact and (ii) the second electrical contact.

3. The light emitting device according to claim 2, wherein: The metal-containing interlayer includes aluminum.

4. The light emitting device according to claim 1, wherein: The barrier layer includes (i) a sputtered titanium-containing layer and (ii) an evaporated gold-containing layer.

5. The light emitting device according to claim 1, wherein The dielectric reflector layer includes at least one of a plurality of conductive vias extending through the dielectric reflector layer and arranged to contact at least one of the first semiconductor layer and the second semiconductor layer.

6. The light emitting device according to claim 1, wherein: Further including: A light-transmitting substrate comprising sapphire, silicon carbide, silicon or a group III-nitride material.

7. The light emitting device according to claim 6, wherein: The light-transmissive substrate includes a patterned surface including at least one of (a) a plurality of recessed features and (b) a plurality of raised features, wherein the first semiconductor layer is deposited on the patterned surface.

8. The light emitting device according to claim 1, wherein: The dielectric reflector layer is disposed on the second semiconductor layer.

9. The light emitting device according to claim 1, wherein: Portions of each of the metallic reflector layer and the passivation layer extend into the at least one recess.

10. The light emitting device according to claim 1, wherein: At least a portion of the passivation layer peripherally surrounds the multilayer reflector and prevents exposure of the multilayer reflector.

11. The light emitting device of claim 1 , comprising at least one of the following features (a) to (c): (a) the dielectric reflector layer comprises silicon dioxide; (b) the metal reflector layer comprises silver; and (c) the passivation layer comprises silicon nitride.

12. The light emitting device according to claim 1, wherein: The dielectric reflector layer comprises silicon dioxide; The metallic reflector layer comprises silver; and The passivation layer includes silicon nitride.

13. The light emitting device according to claim 1, wherein: The first semiconductor layer includes an n-type material, and the second semiconductor layer includes a p-type material.

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