Display device

Abstract

A display device is provided. The display device comprises: a display panel including sub-pixels and a heat dissipation pad electrically connected to at least one of the sub-pixels; a heat sink disposed on the heat dissipation pad; and an insulating heat dissipation adhesive layer disposed between the heat sink and the heat dissipation pad to bond the heat sink and the heat dissipation pad.

Description

Technical Field

[0001] The invention relates to a display device. Background Art

[0002] Recently, display devices have been developed as thin film display devices such as liquid crystal display (LCD) devices and organic light emitting display (OLED) devices. Therefore, display devices are applied to smart phones, tablet personal computers (PCs), digital cameras, laptop computers, navigation systems, and televisions (TVs). In addition, display devices are applied to instrument panels, central instrument panels, or central information displays (CIDs) provided on dashboards in automobiles.

[0003] Meanwhile, in midsummer, the temperature inside a car can reach 80 to 90° C. Therefore, when a display device applied to a car is driven at a temperature of 80 to 90° C., the internal temperature of the display device rises even higher. As a result, the characteristics of the display device may deteriorate, or the life of the display device may be shortened. Summary of the invention

[0004] Technical issues

[0005] The present invention aims to provide a display device capable of improving heat dissipation effect.

[0006] The objects of the present invention are not limited to the above objects, and other objects not mentioned can be clearly understood by those skilled in the art from the following description.

[0007] Technical Solution

[0008] A display device according to an exemplary embodiment includes: a display panel including sub-pixels and a heat dissipation pad electrically connected to at least one of the sub-pixels; a heat sink disposed on the heat dissipation pad; and an insulating heat dissipation adhesive layer disposed between the heat sink and the heat dissipation pad to bond the heat sink and the heat dissipation pad.

[0009] The display panel further includes a conductive line configured to electrically connect the at least one of the sub-pixels and the heat dissipation pad.

[0010] The display panel further includes a second power voltage line to which a second power voltage is applied, and the conductive line crosses the second power voltage line.

[0011] The display panel further includes a sealant surrounding a display area where the sub-pixels are disposed, and the conductive lines cross the sealant.

[0012] The sealant is disposed on an outer side of the second power voltage line, and the heat dissipation pad is disposed on an outer side of the sealant.

[0013] Each of the sub-pixels includes a light-emitting element and a driving transistor, wherein the driving transistor is configured to control a current flowing from a first power supply voltage line to the light-emitting element according to a data voltage applied to a gate electrode of the driving transistor, wherein the first power supply voltage line is applied with a first power supply voltage higher than the second power supply voltage.

[0014] The first power supply voltage is applied to the wire, and the wire is provided on the second power supply voltage line.

[0015] Each of the sub-pixels further includes an initialization transistor configured to initialize the gate electrode of the driving transistor to an initialization voltage.

[0016] The initialization voltage is applied to the conductive line, and the conductive line is provided on the second power supply voltage line.

[0017] Each of the sub-pixels further includes a scan transistor configured to supply the data voltage to the gate electrode of the driving transistor according to a scan signal.

[0018] The data voltage is applied to the conductive line, and the conductive line is disposed on the second power voltage line.

[0019] The scan signal is applied to the conductive line, and the conductive line is disposed on the same layer as the second power supply voltage line.

[0020] The conductive line includes a scan connection electrode disposed on the second power supply voltage line.

[0021] Each of the sub-pixels further includes a light emission control transistor configured to block a current flowing from the first power supply voltage line through the drive transistor to the light emitting element according to a light emission control signal.

[0022] The light emitting control signal is applied to the conductive line, and the conductive line is disposed on the same layer as the second power supply voltage line.

[0023] Each of the sub-pixels further includes a light-blocking layer disposed below an active layer of the driving transistor, and the conductive line is connected to the light-blocking layer.

[0024] The conductive line is disposed below the second power voltage line.

[0025] The display panel further includes a second power voltage line to which a second power voltage is applied, and the conductive line is connected to the second power voltage line.

[0026] The display panel includes a first substrate and a second substrate disposed on the first substrate, and the heat dissipation pad is disposed on a side of the first substrate that is not covered by the second substrate.

[0027] The heat sink is disposed on a portion of an upper surface, a side surface, and a portion of a lower surface of the first substrate.

[0028] The display panel further includes a display pad disposed on the other side of the first substrate that is not covered by the second substrate.

[0029] The display device further includes a flexible circuit board attached to the display pad of the display panel.

[0030] The insulating heat dissipation adhesive layer is a thermally conductive silicone adhesive.

[0031] Details of other embodiments are included in the detailed description and accompanying drawings.

[0032] Beneficial Effects

[0033] In a display device according to an embodiment, a wire electrically connected to a sub-pixel may be connected to a heat dissipation pad formed in a non-display area of ​​a display panel. Therefore, heat generated in the wire electrically connected to the sub-pixel may be dissipated through the heat dissipation pad, the insulating heat dissipation adhesive layer, and the heat sink. Therefore, degradation of characteristics of the display device or shortening of the life of the display device due to an increase in the internal temperature of the display device may be improved.

[0034] The effects according to the embodiment are not limited to the above contents, and more various effects are included in the specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 is a perspective view showing a display device according to an embodiment.

[0036] Figure 2 It is shown Figure 1 An exploded perspective view of an example of a display device in FIG.

[0037] Figure 3 It is shown along Figure 1 A cross-sectional view of an example taken along line II' in FIG.

[0038] Figure 4 It is shown Figure 3 A plan view of an example of a display panel.

[0039] Figure 5 yes Figure 4 An enlarged plan view of area A in FIG.

[0040] Figure 6 It is shown Figure 4 A plan view of an example of a sub-pixel in FIG.

[0041] Figure 7 It is shown along Figure 5 A cross-sectional view of an example taken along line II-II'.

[0042] Figure 8 It is shown along Figure 6 A cross-sectional view of an example taken along line III-III'.

[0043] Fig. 9 It is shown along Figure 5 A cross-sectional view of another example taken along line II-II' in FIG.

[0044] Fig.10 It is shown Figure 3 A plan view of another example of a display panel in FIG.

[0045] Fig.11 yes Fig.10 Enlarged plan view of area B in the middle.

[0046] Fig.12 It is shown along Fig.11 A cross-sectional view of an example taken along line IV-IV' in FIG.

[0047] Fig.13 It is shown Figure 3 A plan view of yet another example of a display panel in FIG.

[0048] Fig.14 It is shown Figure 3 A plan view of yet another example of a display panel in FIG.

[0049] Fig.15 yes Fig.14 An enlarged plan view of area C in FIG.

[0050] Fig.16 It is shown along Fig.15 A cross-sectional view of an example taken along line V-V' in FIG.

[0051] Fig.17 It is shown Figure 3 A plan view of yet another example of a display panel in FIG.

[0052] Fig.18 It is shown Figure 3 A plan view of yet another example of a display panel in FIG.

[0053] Fig.19 yes Fig.18 An enlarged plan view of area E in FIG.

[0054] Fig. 20 It is shown along Fig.19 A cross-sectional view of an example taken along line VI-VI'.

[0055] Fig.21 It is shown Figure 3 A plan view of yet another example of a display panel in FIG.

[0056] Fig. 22 yes Fig.21 An enlarged plan view of area F in FIG.

[0057] Fig.23 It is shown along Fig. 22 A cross-sectional view of an example taken along line VII-VII'.

[0058] Fig.24 and Fig.25 is an exemplary diagram showing an example in which a display device according to one embodiment is applied to a car. DETAILED DESCRIPTION

[0059] The advantages and features of the present invention and the methods of achieving the advantages and features of the present invention will become apparent with reference to the embodiments described in detail below in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms that are different from each other, and these embodiments, combined with the common knowledge in the technical field to which the present invention belongs, make the disclosure of the present invention complete. The present invention is provided to fully inform the scope of the present invention to those who own the present invention, and the present invention is limited only by the scope of the claims.

[0060] When an element or layer is referred to as being "on" another element or layer, this includes all cases where the element or layer is directly "on" the other element or layer or an intervening element or layer is interposed between the element or layer and the other element or layer. Throughout the specification, the same reference numerals refer to the same elements. The shapes, sizes, proportions, angles, quantities, etc. disclosed in the drawings for describing the embodiments are exemplary, and the present invention is not limited to what is shown.

[0061] Although the terms first, second, etc. are used to describe various elements, it goes without saying that these elements are not limited by these terms. These terms are only used to distinguish one component from another component. Therefore, it goes without saying that within the technical concept of the present invention, the first component mentioned below can be named as the second component.

[0062] Each of the features of the various embodiments of the present invention may be partially or fully combined with each other, various technical associations and drives are possible, and each of the embodiments may be implemented independently of each other, or may be implemented together in an associated relationship.

[0063] Hereinafter, specific embodiments will be described with reference to the accompanying drawings.

[0064] Figure 1 is a perspective view showing a display device according to an embodiment. Figure 2 It is shown Figure 1 An exploded perspective view of an example of a display device in FIG. Figure 3 It is shown along Figure 1 A cross-sectional view of an example taken along line II' in FIG.

[0065] Reference Figures 1 to 3 , a display device 10 according to one embodiment includes a cover window 100 , a touch sensing device 200 , a touch circuit board 210 , a display panel 300 , a display circuit board 310 , a panel lower member 400 , a heat sink 500 , and a lower cover 800 .

[0066] In the specification, "upper", "top" and "upper surface" refer to the direction in which the touch sensing device 200 is disposed relative to the display panel 300, that is, the Z-axis direction, and "lower", "bottom" and "lower surface" refer to the direction in which the lower cover 800 is disposed relative to the display panel 300, that is, the direction opposite to the Z-axis direction. In addition, "left", "right", "upper" and "lower" refer to directions in the case where the display panel 300 is viewed in a plan view. For example, "left" refers to the direction opposite to the X-axis direction, "right" refers to the X-axis direction, "upper" refers to the Y-axis direction, and "lower" refers to the direction opposite to the Y-axis direction.

[0067] In addition, the display device 10 may be any one of an organic light-emitting display device, a liquid crystal display device, a plasma display device, a field emission display device, an electrophoretic display device, an electrowetting display device, a quantum dot light-emitting display device, and a micro LED display device. In the following, the display device 10 is described with emphasis on being an organic light-emitting display device, but the present invention is not limited thereto.

[0068] The display device 10 may have a rectangular shape in a plan view. Figure 1 As shown in , the display device 10 may have a rectangular planar shape having a short side in a first direction (X-axis direction) and a long side in a second direction (Y-axis direction). Each of the corners where the short side in the first direction (X-axis direction) and the long side in the second direction (Y-axis direction) intersect may be rounded to have a shape such as Figure 1The planar shape of the display device 10 is not limited to a rectangular shape, and may be formed in other polygonal shapes, a circular shape, or an elliptical shape.

[0069] The cover window 100 may be disposed on the display panel 300 to cover the upper surface of the display panel 300. Therefore, the cover window 100 may play a role in protecting the upper surface of the display panel 300. The cover window 100 may be formed by Figure 3 The adhesive layer 110 shown in FIG. 1 is attached to the touch sensing device 200. The adhesive layer 110 may be an optically clear adhesive film (OCA) or an optically clear resin (OCR).

[0070] The cover window 100 may include a transmission portion that transmits the image of the display panel 300 and a light-blocking portion corresponding to an area other than the transmission portion. The light-blocking portion of the cover window 100 may be formed to be opaque so that unnecessary components other than the image of the display panel 300 are not visually recognized by the user. Alternatively, the light-blocking portion of the cover window 100 may be formed by a decorative layer on which a pattern that can be shown to the user when the image is not displayed is formed. For example, a company's logo or various characters may be patterned on the light-blocking portion of the cover window 100.

[0071] The cover window 100 may be made of glass, sapphire and / or plastic. The cover window 100 may be formed to be rigid or flexible.

[0072] The touch sensing device 200 may be disposed between the cover window 100 and the display panel 300. The touch sensing device 200 is a device for sensing a touch position of a user, and may be implemented in a capacitive method such as a self-capacitive method or a mutual-capacitive method, or an infrared method.

[0073] like Figure 3 As shown in , the touch sensing device 200 may be provided on an upper substrate of the display panel 300. Alternatively, the touch sensing device 200 may be formed integrally with the display panel 300. In this case, the upper substrate of the display panel 300 may be omitted, and the touch sensing device 200 may be formed on an encapsulation film of the display panel 300. In addition, the touch sensing device 200 may include a pressure sensor capable of sensing pressure of a user.

[0074] In order to prevent a situation in which external light is reflected by the lines of the touch sensing device 200 or the lines of the display panel 300 and thus visibility of an image displayed by the display panel 300 is deteriorated, a polarizing film may be disposed on the touch sensing device 200 .

[0075] The touch circuit board 210 may be attached to one side of the touch sensing device 200. Specifically, the touch circuit board 210 may be attached to the pads TP provided on one side of the touch sensing device 200 using a first anisotropic conductive film (TACF). Figure 3 As shown in FIG. 1 , a touch connection terminal may be provided on the touch circuit board 210, and the touch connection terminal may be connected to the first connector 330 of the display circuit board 310. The touch circuit board 210 may be a flexible printed circuit board or a chip on film.

[0076] The touch driving circuit 220 may apply a touch driving signal to the touch sensing device 200 , sense a sensing signal from the touch driving circuit 220 , and analyze the sensing signal to calculate a user's touch position. The touch driving circuit 220 may be formed as an integrated circuit and mounted on the touch circuit board 210 .

[0077] The display panel 300 may include a display area DA and a non-display area NDA. The display area DA is an area where an image is displayed, and the non-display area NDA is an area where an image is not displayed, and the non-display area NDA may be a peripheral area of ​​the display area NDA. Figure 2 As shown in FIG. 1 , the non-display area NDA may be disposed to surround the display area DA, but is not limited thereto. The display area DA may overlap with the transmissive portion of the cover window 100 , and the non-display area NDA may overlap with the light blocking portion of the cover window 100 .

[0078] The display panel 300 may include a first substrate 301 , a second substrate 303 , and a pixel array layer 302 disposed between the first substrate 301 and the second substrate 303 .

[0079] The first substrate 301 may be formed of plastic or glass. When the first substrate 301 is formed of plastic, the first substrate 301 may be formed of polyethersulfone (PES), polyacrylate (PA), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallyl ester, polyimide (PI), polycarbonate (PC), cellulose triacetate (CAT), cellulose acetate propionate (CAP), or a combination thereof.

[0080] The pixel array layer 302 may include a thin film transistor layer and a light emitting element layer using an organic light emitting element as a light emitting element, and sub-pixels may be formed in a matrix form. Figure 8 A detailed description of the pixel array layer 302 is described.

[0081] The first substrate 301 and the second substrate 303 may be bonded to each other by the sealant 304. Since the sealant 304 is disposed at the edge of the display panel 300, the pixel array layer 302 may be sealed by the sealant 304.

[0082] The display pad DP may be disposed on one side of the first substrate 301 that is not covered by the second substrate 303. In addition, a heat dissipation pad 305 may be disposed on the other side of the first substrate 301 that is not covered by the second substrate 303. The heat dissipation pad 305 may be connected to a wire that is electrically connected to at least one of the sub-pixels of the pixel array layer 302.

[0083] Will refer to later Figures 4 to 9 A detailed description of the display panel 300 is described.

[0084] Reference Figure 3 , the display circuit board 310 may be attached to one side of the display panel 300. Specifically, one end of the display circuit board 310 may be attached to the display pad DP provided at one side of the display panel 300 through the second anisotropic conductive film DACF. The other end of the display circuit board 310 may be attached to the lower surface of the panel lower member 400 through the adhesive member 610. The touch circuit board 210 and the display circuit board 310 may be flexible printed circuit boards, and as shown in FIG. Figure 3 As shown in FIG. 1 , the touch circuit board 210 and the display circuit board 310 may be bent from an upper portion to a lower portion of the display panel 300 . The display circuit board 310 may be connected to the touch connection terminal of the touch circuit board 210 through the first connector 330 .

[0085] The display driving circuit 320 outputs signals and voltages for driving the display panel 300 through the display circuit board 310. Specifically, the display driving circuit 320 can receive digital video data and timing signals from the outside, and can convert the digital video data into analog positive / negative data voltages to supply the analog positive / negative data voltages to the data lines DL through the display pads DP. In addition, the display driving circuit 320 generates and supplies a scan control signal for controlling the scan driving part GDC through the scan control line SCL. In addition, the display driving circuit 320 can drive the power supply voltage (e.g., Figure 4 As shown in FIG. 1 , a first power supply voltage supplied to a first power supply voltage line VDL, a second power supply voltage supplied to a second power supply voltage line VSL, and an initialization voltage supplied to an initialization voltage line VIL are output to the display pad DP.

[0086] The display driving circuit 320 may be formed as an integrated circuit and mounted on the display circuit board 310 , but is not limited thereto. For example, the display driving circuit 320 may be attached to one side of the display panel 300 .

[0087] The panel lower member 400 may be disposed on the lower surface of the display panel 300. The panel lower member 400 may include at least one of a heat dissipation layer for effectively dissipating heat of the display panel 300, an electromagnetic wave shielding layer for shielding electromagnetic waves, a light blocking layer for blocking external incident light, a light absorbing layer for absorbing light incident from the outside, and a buffer layer for absorbing impact from the outside.

[0088] The light absorbing layer may be disposed under the display panel 300. The light absorbing layer prevents transmission of light and prevents elements disposed under the light absorbing layer from being visually recognized from an upper portion of the display panel 300. The light absorbing layer may include a light absorbing material such as a black pigment or dye.

[0089] The buffer layer may be disposed below the light absorbing layer. The buffer layer absorbs external impacts and prevents damage to the display panel 300. The buffer layer may be formed of a single layer or a plurality of layers. For example, the buffer layer may be formed of a polymer resin such as polyurethane, polycarbonate, polypropylene, or polyethylene, or may include a material having elasticity, such as a sponge formed of foamed rubber, urethane-based materials, or acrylic-based materials. The buffer layer may be a cushion layer.

[0090] The heat dissipation layer may be disposed below the buffer layer. The heat dissipation layer may include a first heat dissipation layer including graphite or carbon nanotubes and a second heat dissipation layer formed of a metal film capable of shielding electromagnetic waves and having excellent thermal conductivity, such as copper, nickel, ferrite or silver.

[0091] The heat sink 500 may be attached to the other side of the display panel 300. Specifically, the heat sink 500 may be attached to the heat dissipation pad 305 provided at the other side of the display panel 300 through the insulating heat dissipation adhesive layer 510. The insulating heat dissipation adhesive layer 510 may be a thermally conductive silicone adhesive. The heat sink 500 may include graphite or a metal material having high thermal conductivity such as copper, nickel, ferrite, or silver.

[0092] The heat sink 500 may be disposed on a portion of the upper surface of the first substrate 301, one side surface of the first substrate 301, and a portion of the lower surface of the first substrate 301. In addition, the heat sink 500 may be disposed on one side surface of the second substrate 303 of the display panel 300 and one side surface of the touch sensing device 200. That is, the heat sink 500 may be formed as follows: Figure 3 As shown in shape, and may be disposed to surround one side, for example, an upper side surface, of the first substrate 301 .

[0093] The lower cover 800 may be disposed below the panel lower member 400. The lower cover 800 may form the outer portion of the lower surface of the display device 10. The lower cover 800 may be formed in a bowl shape to accommodate the display panel 300. The sidewall of the lower cover 800 may contact the edge of the cover window 100. In this case, the sidewall of the lower cover 800 may be attached to the edge of the cover window 100 by an adhesive member.

[0094] The lower cover 800 may be fastened to the panel lower member 400 and / or the heat sink 500 by a fixing member such as a screw, or may be attached to the panel lower member 400 and / or the heat sink 500 by an adhesive member such as an adhesive or an adhesive tape. The lower cover 800 may include plastic and / or metal. The lower cover 800 may include stainless steel (SUS) or aluminum (Al) to improve the heat dissipation effect. In this case, the heat dissipated to the heat sink 500 may be effectively dissipated to the outside through the lower cover 800.

[0095] Meanwhile, when the display device 10 according to one embodiment is applied to a car, the display device 10 may be designed to inject wind from the air conditioner into the space between the panel lower member 400 and the lower cover 800, and in this case, the internal temperature of the display device 10 may be easily lowered.

[0096] according to Figures 1 to 3 In the embodiment shown in FIG. 5 , the heat transferred to the heat dissipation pad 305 of the display panel 300 through the insulating heat dissipation adhesive layer 510 and the heat sink 500 can be dissipated. Therefore, the characteristic degradation of the display device 10 or the shortening of the life of the display device 10 due to the increase of the internal temperature of the display device 10 can be improved.

[0097] Figure 4 It is shown Figure 3 A plan view of an example of a display panel.

[0098] exist Figure 4 In the embodiment, for the convenience of description, the second substrate 303 of the display panel 300 is omitted. Figure 4 In the figure, for the convenience of description, only the sub-pixel PX, the scan line SL, the light emitting control line EL, the data line DL, the initialization voltage line VIL, the first power supply voltage line VDL, the second power supply voltage line VSL, the sealant 304, the heat dissipation pad 305, the display pad DP and the scan driving part GDC of the display panel 300 are shown.

[0099] Reference Figure 4, the sub-pixels PX are arranged in the display area DA. Each of the sub-pixels PX may be connected to at least one of the scan lines SL, at least one of the light emission control lines EL, at least one of the data lines DL, at least one of the first power supply voltage lines VDL, and at least one of the initialization voltage lines VIL. Figure 6 A detailed description of the sub-pixel PX is described.

[0100] The scan line SL and the light emission control line EL may be formed parallel to each other in a first direction (X-axis direction). The data line DL and the first power supply voltage line VDL may be formed parallel to each other in a second direction (Y-axis direction) crossing the first direction (X-axis direction).

[0101] The data line DL may be electrically connected to the display pad DP through the data routing line DRL. Therefore, the data line DL may receive a data voltage. Some of the data routing lines DRL may overlap with the first power supply voltage electrode VDE. In this case, the data routing line DRL may be disposed on the first power supply voltage electrode VDE.

[0102] The first power supply voltage line VDL may be connected to a first power supply voltage electrode VDE disposed in the non-display area NDA. The first power supply voltage electrode VDE may be disposed outside the lower portion of the display area DA. The first power supply voltage electrode VDE may be electrically connected to the display pad DP through a first power routing line VRL. Thus, the first power supply voltage electrode VDE may receive a first power supply voltage.

[0103] The initialization voltage line VIL may be formed in parallel in the second direction (Y-axis direction) in the non-display area NDA. The initialization voltage line VIL may be formed in parallel in the first direction (X-axis direction) in the display area DA. Therefore, the initialization voltage line VIL formed in the second direction (Y-axis direction) in the non-display area NDA may be connected to the initialization voltage line VIL parallel in the first direction (X-axis direction) in the display area DA. The initialization voltage line VIL formed in the second direction (Y-axis direction) in the non-display area NDA may be connected to the display pad DP to receive the initialization voltage. The initialization voltage may be a voltage lower than the first power supply voltage.

[0104] like Figure 4 As shown in the figure, the scan driving part GDC may be disposed on the left side of the first substrate 301, but is not limited thereto. The scan driving part GDC may be disposed on the right side of the first substrate 301, or may be disposed on both the left and right sides of the first substrate 301. The scan driving part GDC may be disposed in the non-display area NDA. The scan driving part GDC may be disposed outside the left portion of the initialization voltage line VIL, which is disposed outside the left portion of the display area DA.

[0105] The scan driving part GDC receives a scan control signal through a scan control line SCL connecting the scan driving part GDC and the display pad DP. The scan driving part GDC may generate a scan signal and a light emitting control signal based on the scan control signal. The scan driving part GDC may output a scan signal to the scan line SL, and may output a light emitting control signal to the light emitting control line EL.

[0106] The second power supply voltage line VSL may be disposed in the non-display area NDA and may be disposed outside at least three sides of the display area DA. Figure 4 As shown in , the second power supply voltage line VSL can be set on the left outer side, the upper outer side and the right outer side of the display area DA. The second power supply voltage line VSL can be connected to the display pad DP to receive the ground voltage or the second power supply voltage. The second power supply voltage can be a voltage lower than the first power supply voltage. Since the display area DA is arranged to be surrounded by the second power supply voltage line VSL, external static electricity can be discharged by the second power supply voltage line VSL. Therefore, the display area DA can be protected from external static electricity. In addition, the second power supply voltage line VSL can be connected to the light emitting element layer EML (see Figure 8 That is, the second power supply voltage line VSL may be electrically connected to the cathode of each of the sub-pixels PX.

[0107] The sealant 304 may be disposed in the non-display area NDA and may be disposed to surround the display area DA. Figure 4 As shown in , the sealant 304 may be disposed on the left outer side, upper outer side, right outer side, and lower outer side of the display area DA. The sealant 304 may be disposed on the outer side of the second power supply voltage line VSL, which is located on the left outer side, upper outer side, and right outer side of the display area DA.

[0108] The sealant 304 may be glass frit, a photocurable sealant, or a thermosetting sealant. When the sealant 304 is glass frit, after melting the glass frit by laser, the first substrate 301 and the second substrate 303 may be bonded to each other while solidifying the melted glass frit. When the sealant 304 is a photocurable sealant or a thermosetting sealant, after coating the photocurable sealant or the thermosetting sealant on the first substrate 301 and disposing the second substrate 303, ultraviolet (UV) rays are irradiated or heat is applied to cure the sealant, and thus the first substrate 301 and the second substrate 303 may be bonded to each other.

[0109] The display pad DP and the heat dissipation pad 305 are disposed in the non-display area NDA. The display pad DP may be disposed at an edge of one side of the first substrate 301, and the heat dissipation pad 305 may be disposed at an edge of the other side of the first substrate 301. For example, the display pad DP may be disposed at a lower edge of the first substrate, and the heat dissipation pad 305 may be disposed at an upper edge of the first substrate 301. The heat dissipation pad 305 may be disposed on the outside of the sealant 304. For example, the heat dissipation pad 305 may be disposed on the upper outside of the sealant 304.

[0110] The heat dissipation pad 305 may be connected to a conductive line (eg, a first power supply voltage line VDL) that is electrically connected to at least one of the sub-pixels PX. Figure 5 As shown in , the first power voltage line VDL may cross the second power voltage line VSL and the sealant 304 at the upper outer side of the display area DA. Figure 5 It is shown that the first power supply voltage line VDL is disposed on the second power supply voltage line VSL, and the sealant 304 is disposed on the first power supply voltage line VDL. In addition, Figure 5 It is shown that the first power supply voltage line VDL and the heat dissipation pad 305 are disposed on the same layer.

[0111] Figure 6 It is shown Figure 4 A plan view of an example of a sub-pixel in FIG.

[0112] Figure 6 It is shown that each of the sub-pixels PX includes seven transistors DT and ST1 to ST6 and one capacitor C1 , but the present specification is not limited thereto.

[0113] Reference Figure 6 , each of the sub-pixels PX may include a driving transistor DT, first to sixth switching transistors ST1 to ST6 , and a capacitor C1 .

[0114] The driving transistor DT may include a driving active layer DT_ACT, a driving gate electrode DT_G, a driving source electrode DT_S, and a driving drain electrode DT_D. The driving active layer DT_ACT may overlap with the driving gate electrode DT_G. The driving gate electrode DT_G may include a first driving gate electrode DT_G1 and a second driving gate electrode DT_G2. The second driving gate electrode DT_G2 may be disposed on the first driving gate electrode DT_G1, and the first driving gate electrode DT_G1 and the second driving gate electrode DT_G2 may be connected to each other through a first contact hole CNT1. The first driving gate electrode DT_G1 may overlap with the driving active layer DT_ACT, and the second driving gate electrode DT_G2 may be connected to the drain electrode D2 of the second switching transistor ST2 through a second contact hole CNT2. The driving source electrode DT_S may be connected to the drain electrode D1 of the first switching transistor ST1. The driving drain electrode DT_D may be connected to the source electrode S2 of the second switching transistor ST2 and the source electrode S6 of the sixth switching transistor ST6.

[0115] The first switching transistor ST1 may include a first active layer ACT1, a first gate electrode G1, a first source electrode S1, and a first drain electrode D1. The first gate electrode G1 is a portion of the k-th scan line SLk (k is a positive integer greater than or equal to 2), and may be an overlapping region between the first active layer ACT1 and the k-th scan line SLk. The first source electrode S1 may be connected to the data line DL through a third contact hole CNT3. The first drain electrode D1 may be connected to the source electrode DT_S of the driving transistor DT.

[0116] The second switching transistor ST2 may include a second active layer ACT2, a second gate electrode G2, a second source electrode S2, and a second drain electrode D2. The second gate electrode G2 is a portion of the k-th scan line SLk and may be an overlapping region between the second active layer ACT2 and the k-th scan line SLk. The second source electrode S2 may be connected to the drain electrode DT_D of the driving transistor DT. The second drain electrode D2 may be connected to the gate electrode DT_G of the driving transistor DT.

[0117] Meanwhile, the second switching transistor ST2 may be formed as a double transistor. Figure 6 As shown in , the second switching transistor ST2 may include two second active layers ACT2 and two second gate electrodes G2.

[0118] The third switching transistor ST3 may include a third active layer ACT3, a third gate electrode G3, a third source electrode S3, and a third drain electrode D3. The third gate electrode G3 is a portion of the k-1th scan line SLk-1, and may be an overlapping region between the third active layer ACT3 and the k-1th scan line SLk-1. The third source electrode S3 may be connected to the gate electrode DT_G of the driving transistor DT and the drain electrode D2 of the second switching transistor ST2. The third drain electrode D3 may be connected to the initialization voltage line VIL through a fourth contact hole CNT4.

[0119] Meanwhile, the third switch transistor ST3 may be formed as a double transistor. Figure 6 As shown in , the third switching transistor ST3 may include two third active layers ACT3 and two third gate electrodes G3.

[0120] The fourth switching transistor ST4 may include a fourth active layer ACT4, a fourth gate electrode G4, a fourth source electrode S4, and a fourth drain electrode D4. The fourth gate electrode G4 is a portion of the k-1th scan line SLk-1, and may be an overlapping region between the fourth active layer ACT4 and the k-1th scan line SLk-1. The fourth source electrode S4 may be connected to the anode of the organic light emitting element. The fourth drain electrode D4 may be connected to the initialization voltage line VIL through the fourth contact hole CNT4.

[0121] Specifically, the initialization voltage line VIL is connected to the initialization connection electrode VIE through the fifth contact hole CNT5, and the initialization connection electrode VIE can be connected to the drain electrode D3 of the third switching transistor ST3 through the fourth contact hole CNT4. The initialization connection electrode VIE can be arranged to intersect the k-1th scan line SLk-1. In addition, the anode can be connected to the anode connection electrode ANDE through the anode contact hole AND_CNT, and the anode connection electrode ANDE can be connected to the source electrode S4 of the fourth switching transistor ST4 through the sixth contact hole CNT6.

[0122] The fifth switching transistor ST5 may include a fifth active layer ACT5, a fifth gate electrode G5, a fifth source electrode S5, and a fifth drain electrode D5. The fifth gate electrode G5 is a portion of the kth light emission control line EMLk and may be an overlapping region between the fifth active layer ACT5 and the kth light emission control line EMLk. The fifth source electrode S5 may be connected to the source electrode DT_S of the driving transistor DT and the drain electrode D1 of the first switching transistor ST1. The fifth drain electrode D5 may be connected to the first power supply voltage line VDL through the seventh contact hole CNT7.

[0123] The sixth switching transistor ST6 may include a sixth active layer ACT6, a sixth gate electrode G6, a sixth source electrode S6, and a sixth drain electrode D6. The sixth gate electrode G6 is a portion of the kth light emission control line EMLk and may be an overlapping region between the sixth active layer ACT6 and the kth light emission control line EMLk. The sixth source electrode S6 may be connected to the drain electrode DT_D of the driving transistor DT and the source electrode S2 of the second switching transistor ST2. The sixth drain electrode D6 may be connected to the anode of the organic light emitting element.

[0124] The first electrode CE1 of the capacitor C1 may be substantially identical to the gate electrode DT_G of the driving transistor DT, and the second electrode CE2 may overlap the gate electrode DT_G of the driving transistor DT and may be connected to the first power supply voltage line VDL through the eighth contact hole CNT8 .

[0125] Figure 7 It is shown along Figure 5 A cross-sectional view of an example taken along line II-II' in FIG. Figure 8 It is shown along Figure 6 A cross-sectional view of an example taken along line III-III'.

[0126] Reference Figure 7 and Figure 8 A thin film transistor layer TFTL and a light emitting element layer EML are formed on the first substrate 301. The thin film transistor layer TFTL includes an active layer ACT, a first gate layer GTL1, a second gate layer GTL2, a data metal layer DTL, a gate insulating film 130, a first interlayer insulating film 141, a second interlayer insulating film 142, a protective film, and a planarization film 160.

[0127] A buffer film BF may be formed on one surface of the first substrate 301. The buffer film BF may be formed on one surface of the first substrate 301 to protect the organic light emitting layer 172 of the thin film transistor and the light emitting element layer EML from moisture penetrating through the first substrate 301, which is susceptible to moisture penetration. The buffer film BF may be formed of a plurality of alternately stacked inorganic films. For example, the buffer film BF may be formed as a multilayer in which one or more inorganic films such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately stacked. The buffer film BF may be omitted.

[0128] The active layer ACT may be formed on the first substrate 301 or the buffer film BF. The active layer ACT may include polycrystalline silicon, single crystal silicon, low temperature polycrystalline silicon, amorphous silicon, or an oxide semiconductor. Fig.23 As shown in FIG. 4 , a light blocking layer BSM for blocking external light from being incident on the active layer ACT may be formed under the active layer ACT.

[0129] In the case where the active layer ACT is made of polysilicon, when the active layer ACT is doped with ions, the ion-doped active layer ACT may have conductivity. Therefore, the active layer ACT may include source and drain electrodes of the driving transistor DT and the first to sixth switching transistors ST1 to ST6 and the active layer.

[0130] The gate insulating film 130 may be formed on the active layer ACT. The gate insulating film 130 may be formed of an inorganic film such as a silicon nitride layer, a silicon nitride oxide layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0131] The first gate layer GTL1 may be formed on the gate insulating film 130. The first gate layer GTL1 may include a first gate electrode DT_G1 of the driving transistor DT, a scan line SL, a light emission control line EL, and a second power supply voltage line VSL. The first gate layer GTL1 may be formed as a single layer or a plurality of layers formed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys thereof.

[0132] The first interlayer insulating film 141 may be formed on the first gate layer GTL1. The first interlayer insulating film 141 may be formed of an inorganic film such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The first interlayer insulating film 141 may include a plurality of inorganic films.

[0133] The second gate layer GTL2 may be formed on the first interlayer insulating film 141. The second gate layer GTL2 may include an initialization voltage line VIL and a second electrode CE2 of the capacitor C1. The second gate layer GTL2 may be formed as a single layer or multiple layers of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys thereof.

[0134] The second interlayer insulating film 142 may be formed on the second gate layer GTL2. The second interlayer insulating film 142 may be formed of an inorganic film such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The second interlayer insulating film 142 may include a plurality of inorganic films.

[0135] The data metal layer DTL may be formed on the second interlayer insulating film 142. The data metal layer DTL may include a data line DL, a first power voltage line VDL, a second gate electrode DT_G2 of the driving transistor DT, an anode connection electrode ANDE, and an initialization connection electrode VIE. The data metal layer DTL may be formed as a single layer or a plurality of layers formed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys thereof.

[0136] A planarization film 160 for planarizing steps due to the active layer ACT, the first gate layer GTL1, the second gate layer GTL2, and the data metal layer DTL may be formed on the data metal layer DTL. The planarization film 160 may be formed of an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0137] Meanwhile, a protective film may be additionally formed between the data metal layer DTL and the planarization film 160. The protective film may be formed of an inorganic film such as a silicon nitride layer, a silicon nitride oxide layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0138] Figure 8 The driving transistor DT, the first switching transistor ST1, and the sixth switching transistor ST6 are shown to be formed in an upper gate (top gate) manner in which the gate electrode is positioned above the active layer, but it should be noted that the present specification is not limited thereto. That is, the driving transistor DT, the first switching transistor ST1, and the sixth switching transistor ST6 may be formed in a lower gate (bottom gate) manner in which the gate electrode is positioned below the active layer or in a dual gate manner in which the gate electrode is positioned both above and below the active layer. In addition, the second switching transistor ST2 to the fifth switching transistor ST5 may also be formed in an upper gate manner, a lower gate manner, or a dual gate manner.

[0139] The light emitting element layer EML is formed on the thin film transistor layer TFTL and includes a light emitting element 170 and a pixel defining film 180 .

[0140] The light emitting elements 170 and the pixel defining film 180 are formed on the planarization film 160. Each of the light emitting elements 170 may include a first electrode 171, an organic light emitting layer 172, and a second electrode 173.

[0141] The first electrode 171 may be formed on the planarization film 160. The first electrode 171 is connected to the source electrode of the thin film transistor through a contact hole passing through the protective film and the planarization film 160.

[0142] In a top emission structure that emits light in the direction of the second electrode 173 relative to the organic light emitting layer 172, the first electrode 171 may be formed of a metal material having a high reflectivity, such as a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy, and a stacked structure of an APC alloy and ITO (ITO / APC / ITO). The APC alloy is an alloy of silver (Ag), palladium (Pd), and copper (Cu).

[0143] The pixel definition film 180 may be formed to divide the first electrode 171 on the planarization film 160 for defining the sub-pixels PX (see Figure 4 ). The pixel defining film 180 may be formed to cover the edge of the first electrode 171. The pixel defining film 180 may be formed of an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0144] In the sub-pixel PX (see Figure 4 ), a first electrode 171, an organic light emitting layer 172, and a second electrode 173 are sequentially stacked to represent a region where holes from the first electrode 171 and electrons from the second electrode 173 are combined in the organic light emitting layer 172 and thus emit light. Figure 4 ) may include a red sub-pixel that emits red light, a green sub-pixel that emits green light, and a blue sub-pixel that emits blue light.

[0145] The organic light emitting layer 172 is formed on the first electrode 171 and the pixel defining film 180. The organic light emitting layer 172 may emit light of a predetermined color by including an organic material. For example, the organic light emitting layer 172 may include a hole transport layer, an organic material layer, and an electron transport layer. In this case, the organic light emitting layer 172 of the red sub-pixel may emit red light, the organic light emitting layer 172 of the green sub-pixel may emit green light, and the organic light emitting layer 172 of the blue sub-pixel may emit blue light. Alternatively, the sub-pixel PX (see Figure 4 ) can emit white light. In this case, the red sub-pixel can overlap with the red color filter layer, the green sub-pixel can overlap with the green color filter layer, and the blue sub-pixel can overlap with the blue color filter layer.

[0146] The second electrode 173 is formed on the organic light emitting layer 172. The second electrode 173 may be formed to cover the organic light emitting layer 172. The second electrode 173 may be commonly formed on the sub-pixel PX (see Figure 4 A capping layer may be formed on the second electrode 173.

[0147] In the top emission structure, the second electrode 173 may be formed of a transparent conductive material (TCO) such as ITO and IZO capable of transmitting light or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). When the second electrode 173 is formed of a semi-transmissive metal material, light emitting efficiency may be improved due to the microcavity.

[0148] The second substrate 303 is disposed on the light emitting element layer EML. In a vacuum state, the space between the light emitting element layer EML and the second substrate 303 may be empty. Alternatively, a filling film may be disposed between the light emitting element layer EML and the second substrate 303. In this case, the filling film may be an epoxy filling film or a silicone filling film. Alternatively, an encapsulation film may be formed between the light emitting element layer EML and the second substrate 303. The encapsulation film may include at least one inorganic layer to prevent oxygen or moisture from penetrating into the light emitting element layer EML. In addition, the encapsulation layer may include at least one organic film to protect the light emitting element layer EML from foreign matter such as dust.

[0149] Since the second power supply voltage line VSL is formed by the first gate layer GTL1, and the first power supply voltage line VDL and the heat dissipation pad 305 are formed by the data metal layer DTL, Figure 7 As shown in , the first power supply voltage line VDL may be disposed on the second power supply voltage line VSL to cross the second power supply voltage line VSL. Therefore, the first power supply voltage line VDL is not short-circuited with the second power supply voltage line VSL and may be connected to the heat dissipation pad 305.

[0150] Reference Figure 7 , the insulating heat dissipation adhesive layer 510 may be disposed on the heat dissipation pad 305, and the heat sink 500 may be disposed on the insulating heat dissipation adhesive layer 510. That is, the insulating heat dissipation adhesive layer 510 is used to bond the heat sink 500 to the heat dissipation pad 305. The insulating heat dissipation adhesive layer 510 may be a thermally conductive silicone adhesive. The heat sink 500 may include graphite or a metal material with high thermal conductivity such as copper, nickel, ferrite, or silver. Therefore, the heat of the first power supply voltage line VDL may be dissipated through the heat dissipation pad 305, the insulating heat dissipation adhesive layer 510, and the heat sink 500. Therefore, the degradation of the characteristics of the display device 10 or the shortening of the life of the display device 10 caused by the increase in the internal temperature of the display device 10 can be improved.

[0151] like Figure 7As shown in , the sealant 304 may be disposed on the first power supply voltage line VDL and the planarization film 160. In this case, since the first power supply voltage line VDL may be exposed to the outside, the pixel defining film 180 may be disposed to cover the first power supply voltage line VDL, and the sealant 304 may also be disposed on the pixel defining film 180. In this case, the insulating heat dissipation adhesive layer 510 may be disposed in the contact hole through which the heat dissipation pad 305 is exposed through the pixel defining film 180.

[0152] Alternatively, in order to prevent the first power supply voltage line VDL from being exposed to the outside, as Fig. 9 As shown in , the display panel 300 may further include a first power connection electrode VCE connecting each of the first power voltage lines VDL and the heat dissipation pad 305. Figure 8 and Fig. 9 , the first power connection electrode VCE may be formed by the first gate layer GTL1 like the second power voltage line VSL. In this case, each of the first power voltage lines VDL may be connected to the first power connection electrode VCE through the ninth contact hole CNT9, which passes through the first interlayer insulating film 141 and the second interlayer insulating film 142 to expose the first power connection electrode VCE. In addition, the heat dissipation pad 305 may be connected to the first power connection electrode VCE through the tenth contact hole CNT10, which passes through the first interlayer insulating film 141 and the second interlayer insulating film 142 to expose the first power connection electrode VCE. The heat dissipation pad 305 may be completely covered by the insulating heat dissipation adhesive layer 510. In addition, the first interlayer insulating film 141 and the second interlayer insulating film 142 may be formed on the first power connection electrode VCE, and the sealant 304 may be formed on the second interlayer insulating film 142.

[0153] according to Figures 7 to 9 In the embodiment shown in FIG. 5 , since the second power supply voltage line VSL is formed by the first gate layer GTL1, and the first power supply voltage line VDL and the heat dissipation pad 305 are formed by the data metal layer DTL, the first power supply voltage line VDL may not be short-circuited with the second power supply voltage line VSL, and may be connected to the heat dissipation pad 305. Therefore, the heat of the first power supply voltage line VDL may be dissipated through the heat dissipation pad 305, the insulating heat dissipation adhesive layer 510, and the heat sink 500. Therefore, the degradation of the characteristics of the display device 10 or the shortening of the life of the display device 10 due to the increase of the internal temperature of the display device 10 may be improved.

[0154] Fig.10 It is shown Figure 3 A plan view of another example of a display panel in FIG. Fig.11 yes Fig.10 An enlarged plan view of area B in FIG. Fig.12It is shown along Fig.11 A cross-sectional view of an example taken along line IV-IV' in FIG.

[0155] exist Figures 10 to 12 In the embodiment shown in Figure 4 , Figure 5 and Figure 7 The difference of the embodiment shown in FIG. 1 is that the heat dissipation pad 305A is disposed on the second power supply voltage line VSL and is electrically connected to the second power supply voltage line VSL. Figures 10 to 12 In the Figure 4 , Figure 5 and Figure 7 The description of the embodiment shown in FIG.

[0156] like Fig.10 As shown in FIG. 3 , the second power supply voltage line VSL is disposed inside the sealant 304 located on the left and right sides of the first substrate 301, however, the second power supply voltage line VSL may also be disposed outside the sealant 304 located on the upper side of the first substrate 301. Therefore, the second power supply voltage line VSL may cross the sealant 304 on the upper left and right sides of the first substrate 301. The sealant 304 may be disposed on the second power supply voltage line VSL.

[0157] The heat dissipation pad 305A may be connected to a conductive line (eg, a second power supply voltage line VSL) that is electrically connected to at least one of the sub-pixels PX. Fig.11 As shown in , the heat dissipation pad 305A may overlap with the second power supply voltage line VSL disposed on the first substrate 301. The heat dissipation pad 305A may be disposed on the second power supply voltage line VSL and may be connected to the second power supply voltage line VSL through the eleventh contact hole CNT11. In order to improve the adhesion between the insulating heat dissipation adhesive layer 510 and the heat dissipation pad 305A, the width of the heat dissipation pad 305A in the second direction (Y-axis direction) may be greater than the width of the second power supply voltage line VSL in the second direction (Y-axis direction).

[0158] For example, Fig.12 As shown in , the heat dissipation pad 305A can be connected to the second power supply voltage line VSL through the eleventh contact hole CNT11, and the eleventh contact hole CNT11 passes through the first interlayer insulating film 141 and the second interlayer insulating film 142 to expose the second power supply voltage line VSL. In this case, the sealant 304 can be formed on the first interlayer insulating film 141 and the second interlayer insulating film 142.

[0159] according to Figures 10 to 12In the embodiment shown in FIG. 5 , the second power supply voltage line VSL may be provided on the outer side of the sealant 304 located on one side of the first substrate 301, and the heat dissipation pad 305A may be provided on the power supply voltage line VSL to be connected to the second power supply voltage line VSL. Therefore, the heat of the second power supply voltage line VSL may be dissipated through the heat dissipation pad 305A, the insulating heat dissipation adhesive layer 510, and the heat sink 500. Therefore, the degradation of the characteristics of the display device 10 or the shortening of the life of the display device 10 due to the increase of the internal temperature of the display device 10 may be improved.

[0160] Fig.13 It is shown Figure 3 A plan view of yet another example of a display panel in FIG.

[0161] exist Fig.13 In the embodiment shown in Fig.10 The difference of the embodiment shown in FIG. 1 is that the heat dissipation pad 305B is disposed on the left side of the first substrate 301 instead of the upper side. Fig.13 In the Fig.10 The description of the embodiment shown in FIG.

[0162] Reference Fig.13 , the second power supply voltage line VSL is disposed inside the sealant 304 located on the upper and right sides of the first substrate 301, but may be disposed outside the sealant 304 located on the left side of the first substrate 301. Therefore, the second power supply voltage line VSL may cross the sealant 304 at the upper left side of the first substrate 301. The sealant 304 may be disposed on the second power supply voltage line VSL.

[0163] The heat dissipation pad 305B may overlap the second power supply voltage line VSL disposed on the left side of the first substrate 301. That is, the heat dissipation pad 305B may be disposed on the second power supply voltage line VSL and may be connected to the second power supply voltage line VSL.

[0164] Fig.13 The heat dissipation pad 305B is shown to be disposed on the left side of the first substrate 301, but the present specification is not limited thereto. That is, the heat dissipation pad 305B may be disposed on the right side of the first substrate 301, and in this case, the heat dissipation pad 305B may be disposed on and connected to the second power supply voltage line VSL, which is disposed on the outer side of the sealant 304 located on the right side of the first substrate 301.

[0165] because Fig.13 The enlarged plan view of area B1 in Fig.11 The enlarged plan view of region B is substantially the same and will therefore be omitted. Fig.13 Detailed description of the enlarged plan view of area B1 in FIG.

[0166] according to Fig.13 In the embodiment shown in FIG. 3 , the heat dissipation pad 305B may be disposed not only on the upper side of the first substrate 301 but also on the left or right side of the first substrate 301. In this case, the heat sink 500 may be disposed to surround the left or right side surface of the first substrate 301.

[0167] Fig.14 It is shown Figure 3 A plan view of yet another example of a display panel in FIG. Fig.15 yes Fig.14 An enlarged plan view of area C in FIG. Fig.16 It is shown along Fig.15 A cross-sectional view of an example taken along line V-V' in FIG.

[0168] exist Figures 14 to 16 In the embodiment shown in Figure 4 , Figure 5 and Figure 7 The difference of the embodiment shown in FIG. 1 is that the heat dissipation pad 305C is connected to the initialization voltage line VIL instead of the first power supply voltage line VDL. Figures 14 to 16 In the Figure 4 , Figure 5 and Figure 7 The description of the embodiment shown in FIG.

[0169] The heat dissipation pad 305C may be connected to a conductive line (eg, an initialization voltage line VIL) that is electrically connected to at least one of the sub-pixels PX. Fig.14 As shown in , the initialization voltage line VIL may cross the second power supply voltage line VSL and the sealant 304 outside the upper portion of the display area DA. Fig.15 It is shown that the initialization voltage line VIL is disposed on the second power supply voltage line VSL, and the sealant 304 is disposed on the initialization voltage line VIL. In addition, Fig.15 It is shown that the heat dissipation pad 305C is disposed on the initialization voltage line VIL. In this case, the heat dissipation pad 305C may be connected to the initialization voltage line VIL through the twelfth contact hole CNT12.

[0170] like Fig.16 As shown in FIG. 1 , since the second power supply voltage line VSL is provided by the first gate layer GTL1 (see Figure 8 ) is formed, the initialization voltage line VIL is formed by the second gate layer GTL2 (see Figure 8 ) is formed, and the heat dissipation pad 305C is formed by the data metal layer DTL (see Figure 8 ) is formed, so Fig.16As shown in , the initialization voltage line VIL may be disposed on the second power voltage line VSL to cross the second power voltage line VSL. Therefore, the initialization voltage line VIL is not short-circuited with the second power voltage line VSL and may be connected to the heat dissipation pad 305C.

[0171] In addition, the heat dissipation pad 305C may be connected to the initialization voltage line VIL through the twelfth contact hole CNT12 that penetrates the second interlayer insulating film 142 to expose the initialization voltage line VIL. The heat dissipation pad 305C may be completely covered by the insulating heat dissipation adhesive layer 510. In addition, the second interlayer insulating film 142 may be formed on the initialization voltage line VIL, and the sealant 304 may be formed on the second interlayer insulating film 142.

[0172] according to Figures 14 to 16 In the embodiment shown in FIG. 1 , since the second power supply voltage line VSL is provided by the first gate layer GTL1 (see Figure 8 ) is formed, the initialization voltage line VIL is formed by the second gate layer GTL2 (see Figure 8 ) is formed, and the heat dissipation pad 305C is formed by the data metal layer DTL (see Figure 8 ) is formed, so the initialization voltage line VIL may not be short-circuited with the second power supply voltage line VSL and may be connected to the heat dissipation pad 305C. Therefore, the heat of the initialization voltage line VIL may be dissipated through the heat dissipation pad 305C, the insulating heat dissipation adhesive layer 510, and the heat sink 500. Therefore, the degradation of the characteristics of the display device 10 or the shortening of the life of the display device 10 due to the increase in the internal temperature of the display device 10 may be improved.

[0173] Fig.17 It is shown Figure 3 A plan view of yet another example of a display panel in FIG.

[0174] exist Fig.17 In the embodiment shown in Figure 4 The embodiment shown is different in that the heat dissipation pad 305D is connected to the data line DL instead of the first power supply voltage line VDL. Fig.17 In the Figure 4 The description of the embodiment shown in FIG.

[0175] Reference Fig.17 , the heat dissipation pad 305D may be connected to a wire (eg, a data line DL) that is electrically connected to at least one of the sub-pixels PX. Fig.17 As shown in FIG. 1 , the data line DL may cross the second power supply voltage line VSL and the sealant 304 at an upper outer side of the display area DA. Fig.17It is shown that the data line DL is disposed on the second power supply voltage line VSL, and the sealant 304 is disposed on the data line DL. In addition, Fig.17 It is shown that the heat dissipation pad 305D is disposed on the data line DL.

[0176] The data line DL and the heat dissipation pad 305D are formed by a data metal layer DTL (see Figure 8 ) is formed, due to Fig.17 The enlarged plan view of area D in Figure 5 The enlarged plan view of area A in FIG. 1 is substantially the same, so it will be omitted. Fig.17 Detailed description of the enlarged plan view of area D in FIG.

[0177] Alternatively, in order to prevent the data lines DL from being exposed to the outside, the display panel 300 may further include a data connection electrode connecting each of the data lines DL and the heat dissipation pad 305D. The data connection electrode may be connected to the heat dissipation pad 305D. Fig. 9 The data connection electrode may be formed similarly to the first power connection electrode VCE shown in FIG. Figure 8 ) is formed. In this case, each of the data lines DL may be connected to the data connection electrode through a contact hole that passes through the first interlayer insulating film 141 and the second interlayer insulating film 142 to expose the data connection electrode. In addition, the heat dissipation pad 305D may be connected to the data connection electrode through a contact hole that passes through the first interlayer insulating film 141 to expose the data connection electrode. The heat dissipation pad 305D may be completely covered by the insulating heat dissipation adhesive layer 510.

[0178] according to Fig.17 In the embodiment shown in FIG. 1 , since the second power supply voltage line VSL is provided by the first gate layer GTL1 (see Figure 8 ) is formed, and the data line DL and the heat dissipation pad 305D are formed by the data metal layer DTL (see Figure 8 ) is formed, so the data line DL may not be short-circuited with the second power supply voltage line VSL and may be connected to the heat dissipation pad 305D. Therefore, the heat of the data line DL may be dissipated through the heat dissipation pad 305D, the insulating heat dissipation adhesive layer 510 and the heat sink 500. Therefore, the degradation of the characteristics of the display device 10 or the shortening of the life of the display device 10 due to the increase of the internal temperature of the display device 10 may be improved.

[0179] Fig.18 It is shown Figure 3 A plan view of yet another example of a display panel in FIG. Fig.19 yes Fig.18 An enlarged plan view of area E in FIG. Fig. 20 It is shown along Fig.19A cross-sectional view of an example taken along line VI-VI'.

[0180] exist Figures 18 to 20 In the embodiment shown in Figure 4 , Figure 5 and Figure 7 The difference of the embodiment shown in FIG. 1 is that the heat dissipation pad 305E is disposed on the right side of the first substrate 301 instead of the upper side, and the heat dissipation pad 305E is connected to the scan line SL instead of the first power supply voltage line VDL. Figures 18 to 20 In the Figure 4 , Figure 5 and Figure 7 The description of the embodiment shown in FIG.

[0181] The heat dissipation pad 305E is disposed in the non-display area NDA, and may be disposed on the right side of the first substrate 301. Specifically, the heat dissipation pad 305E may be disposed outside the right portion of the sealant 304.

[0182] The heat dissipation pad 305E may be connected to a conductive line (eg, a scan line SL) that is electrically connected to at least one of the sub-pixels PX. Fig.18 As shown in , the scan line SL may cross the second power supply voltage line VSL and the sealant 304 outside the right portion of the display area DA. Fig.19 In the embodiment, since the scanning line SL and the second power supply voltage line VSL are connected by the first gate layer GTL1 (see Figure 8 ) is formed, and thus each of the scan lines SL may include a scan connection electrode SCE connected to the heat dissipation pad 305E, so that a short circuit between the scan line SL and the second power supply voltage line VSL can be prevented.

[0183] The scan connection electrode SCE may be formed by the second gate layer GTL2 (see Figure 8 ) is formed. In this case, the scan connection electrode SCE may be connected to the scan line SL through the thirteenth contact hole CNT13 that passes through the first interlayer insulating film 141 to expose the scan line SL. In addition, the heat dissipation pad 305E may be connected to the scan connection electrode SCE through the fourteenth contact hole CNT14 that passes through the second interlayer insulating film 142 to expose the scan connection electrode SCE. The heat dissipation pad 305E may be completely covered by the insulating heat dissipation adhesive layer 510.

[0184] The scan connection electrode SCE may be disposed on the second power supply voltage line VSL. The second interlayer insulating film 142 may be formed on the scan connection electrode SCE, and the sealant 304 may be formed on the second interlayer insulating film 142. Alternatively, the second interlayer insulating film 142 and the planarization film 160 may be formed on the scan connection electrode SCE, and the sealant 304 may be formed on the planarization film 160.

[0185] according to Figures 18 to 20 In the embodiment shown in FIG. 1 , since the scan line SL and the second power supply voltage line VSL are formed by the first gate layer GTL1 (see Figure 8 ) is formed, and each of the scan lines SL includes a second gate layer GTL2 (see Figure 8 ) is formed, so the scan connection electrode SCE may not be short-circuited with the second power supply voltage line VSL and may be connected to the heat dissipation pad 305E. Therefore, the heat of the scan line SL may be dissipated through the heat dissipation pad 305E, the insulating heat dissipation adhesive layer 510 and the heat sink 500. Therefore, the degradation of the characteristics of the display device 10 or the shortening of the life of the display device 10 due to the increase of the internal temperature of the display device 10 may be improved.

[0186] at the same time, Figures 18 to 20 It is shown that the heat dissipation pad 305E is disposed on the right side of the first substrate 301 , but the present specification is not limited thereto. That is, the heat dissipation pad 305E may be disposed on the left side of the first substrate 301 .

[0187] also, Figures 18 to 20 The heat dissipation pad 305E is shown to be connected to the scan line SL, but the present specification is not limited thereto. That is, the heat dissipation pad 305E may be connected to the light emission control line EL instead of the scan line SL. In this case, each of the light emission control lines EL may include a second gate layer GTL2 (see Figure 8 ) is formed to prevent a short circuit with the second power supply voltage line VSL.

[0188] Fig.21 It is shown Figure 3 A plan view of yet another example of a display panel in FIG. Fig. 22 yes Fig.21 An enlarged plan view of area F in FIG. Fig.23 It is shown along Fig. 22 A cross-sectional view of an example taken along line VII-VII'.

[0189] exist Figure 21 to Figure 23 In the embodiment shown in Figure 4 The difference of the embodiment shown in FIG. 1 is that the heat dissipation pad 305F is connected to the light blocking layer BSM instead of the first power supply voltage line VDL. Figure 21 to Figure 23In the Figure 4 The description of the embodiment shown in FIG.

[0190] The heat dissipation pad 305F may be connected to a light blocking layer BSM, such as a driving active layer DT_ACT of a driving transistor DT (see Figure 6 ) and the first active layer ACT1 of the first switching transistor ST1 of the sub-pixel PX (see Figure 6 ) to the sixth active layer ACT6 of the sixth switching transistor ST6 (see Figure 6 ), the light blocking layer BSM is disposed below the conductive line electrically connected to at least one of the sub-pixels PX. Fig.21 and Fig.23 As shown in , the light blocking layer BSM may cross the second power supply voltage line VSL and the sealant 304 at the upper outer side of the display area DA. Fig. 22 FIG. 3 shows that a light blocking layer BSM is disposed below the second power supply voltage line VSL, and a sealant 304 is disposed on the light blocking layer BSM. Fig. 22 It is shown that the heat dissipation pad 305F is disposed on the light blocking layer BSM. In this case, the heat dissipation pad 305F may be connected to the light blocking layer BSM through the fifteenth contact hole CNT15.

[0191] like Fig.23 As shown in FIG. 1 , the second power supply voltage line VSL is formed by a first gate layer GTL1 (see Figure 8 ) is formed, and a light blocking layer BSM is formed below the second power supply voltage line VSL. Fig. 22 As shown in , the light blocking layer BSM may be disposed to cross the second power voltage line VSL. Therefore, the light blocking layer BSM may not be short-circuited with the second power voltage line VSL and may be connected to the heat dissipation pad 305F.

[0192] The heat dissipation pad 305F may be connected to the light blocking layer BSM through the fifteenth contact hole CNT15 that passes through the buffer film BF, the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142 to expose the light blocking layer BSM. The heat dissipation pad 305F may be completely covered by the insulating heat dissipation adhesive layer 510. In addition, the buffer film BF, the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142 may be formed on the light blocking layer BSM, and the sealant 304 may be formed on the second interlayer insulating film 142.

[0193] according to Figure 21 to Figure 23 In the embodiment shown in FIG. 1 , since the second power supply voltage line VSL is provided by the first gate layer GTL1 (see Figure 8) is formed, and the light blocking layer BSM is formed under the second power supply voltage line VSL, so the light blocking layer BSM may not be short-circuited with the second power supply voltage line VSL and may be connected to the heat dissipation pad 305F. Therefore, the heat of the light blocking layer BSM may be dissipated through the heat dissipation pad 305F, the insulating heat dissipation adhesive layer 510, and the heat sink 500. Therefore, the degradation of the characteristics of the display device 10 or the shortening of the life of the display device 10 due to the increase of the internal temperature of the display device 10 may be improved.

[0194] Figure 24 to Figure 25 is an exemplary diagram showing an example in which the display device according to one embodiment is applied to a car.

[0195] According to reference Figures 1 to 23 The display device of one embodiment described above can be applied to a car. Fig.24 As shown in , the display device according to one embodiment can be used as a display device 10A applied to an instrument panel of an automobile, a display device 10B applied to a central instrument panel of an automobile, and a display device 10C applied to a central information display (CID) provided on a dashboard of an automobile. Fig.24 As shown in , the display device according to one embodiment can be used as display devices 10D and 10E, and the display devices 10D and 10E are applied to indoor mirror displays to replace the side mirrors of the car. Fig.25 , the display device according to one embodiment can be used as entertainment for rear seat passengers of a car, that is, as a display device 10F provided on the back side of a front seat.

[0196] Although the embodiments of the present invention have been described with reference to the accompanying drawings, those skilled in the art to which the present invention belongs may implement the present invention in other specific ways without changing the technical spirit or essential features of the present invention. You will be able to understand. Therefore, it should be understood that the above embodiments are illustrative and non-restrictive in all aspects.

Claims

1. A display device, comprising: A display panel comprising sub-pixels and a heat dissipation pad electrically connected to at least one of the sub-pixels; A heat sink, arranged on the heat dissipation pad; an insulating heat dissipation adhesive layer, arranged between the heat sink and the heat dissipation pad to adhere the heat sink and the heat dissipation pad, a sealant surrounding a display area where the sub-pixels are disposed, and A conductive line configured to electrically connect the at least one of the sub-pixels and the heat dissipation pad, and wherein the sealant is spaced apart from the insulating heat dissipating adhesive layer, and wherein each of the sub-pixels includes a light emitting element and a driving transistor, the driving transistor being configured to control a current flowing from a first power supply voltage line to the light emitting element according to a data voltage applied to a gate electrode of the driving transistor, and A first supply voltage is applied to the conductor.

2. The display device according to claim 1, wherein: The display panel further includes the display area where the sub-pixels are disposed and a non-display area adjacent to the display area. The display panel further includes a second power supply voltage line to which a second power supply voltage is applied; and The conductive line overlaps the sealant and the second power voltage line in a thickness direction of the display panel.

3. The display device according to claim 2, wherein: The conductive line crosses the sealant and the second power supply voltage line.

4. The display device according to claim 2, wherein: The sealant is disposed outside the second power voltage line; and The heat dissipation pad is disposed outside the sealant.

5. The display device according to claim 2, wherein: The first power supply voltage applied is higher than the second power supply voltage.

6. The display device according to claim 5, wherein: The conductive line is arranged on the second power supply voltage line.

7. The display device according to claim 5, wherein: Each of the sub-pixels further includes an initialization transistor configured to initialize the gate electrode of the driving transistor to an initialization voltage.

8. The display device according to claim 7, wherein: The initialization voltage is applied to the conductive line; and The conductive line is arranged on the second power supply voltage line.

9. The display device according to claim 5, wherein: Each of the sub-pixels further includes a scan transistor configured to supply the data voltage to the gate electrode of the driving transistor according to a scan signal.

10. The display device according to claim 9, wherein: The data voltage is applied to the conductive line; and The conductive line is arranged on the second power supply voltage line.

11. The display device according to claim 9, wherein: The scanning signal is applied to the conductive line; and The conductive line is disposed on the same layer as the second power supply voltage line.

12. The display device according to claim 11, wherein: The conductive line includes a scan connection electrode disposed on the second power supply voltage line.

13. The display device according to claim 5, wherein: Each of the sub-pixels further includes a light emission control transistor configured to block a current flowing from the first power supply voltage line through the drive transistor to the light emitting element according to a light emission control signal.

14. The display device according to claim 13, wherein: The light emitting control signal is applied to the wire; and The conductive line is disposed on the same layer as the second power supply voltage line.

15. The display device according to claim 5, wherein: Each of the sub-pixels further includes a light blocking layer disposed below an active layer of the driving transistor; and The conductive line is connected to the light blocking layer.

16. The display device according to claim 15, wherein: The conductive line is disposed below the second power voltage line.

17. The display device according to claim 1, wherein: The display panel further includes a second power supply voltage line to which a second power supply voltage is applied; and The conductive line is connected to the second power supply voltage line.

18. The display device according to claim 1, wherein: The display panel includes a first substrate and a second substrate disposed on the first substrate; and The heat dissipation pad is disposed on a side of the first substrate that is not covered by the second substrate.

19. The display device according to claim 18, wherein: The heat sink is disposed on a portion of an upper surface, a side surface, and a portion of a lower surface of the first substrate.

20. The display device according to claim 18, wherein: The display panel further includes a display pad disposed on the other side of the first substrate that is not covered by the second substrate. 21 . The display device of claim 20 , further comprising a flexible circuit board attached to the display pad of the display panel.

22. The display device according to claim 1, wherein: The insulating heat dissipation adhesive layer is a thermally conductive silicone adhesive.

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