Storage device and method of operating storage device

Abstract

A storage device and a method of operating the storage device are disclosed. The storage device includes: a host interface for receiving host commands from a host device via the storage interface; one or more memory translation layers for performing one or more operations associated with the host commands to retrieve one or more data blocks associated with the host commands from storage memory; bitmap circuitry including a bitmap for tracking one or more data blocks to be transferred to the host device in a constrained order; and a transfer trigger for triggering data transfer of the one or more data blocks to the host device in a constrained order based on the state of one or more bits of the bitmap.

Description

[0001] This application claims priority and benefit to U.S. Provisional Application No. 62 / 985,824, filed March 5, 2020, entitled “Storage Device for Reducing Production Line Idle Time”, and U.S. Application No. 16 / 896,050, filed June 8, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0002] One or more exemplary embodiments of this disclosure relate to storage devices, and more specifically, to storage devices including configurable data transfer triggers and methods of operating them. Background Technology

[0003] A storage system typically includes a host device and storage devices. The host device can access data stored in the storage device by sending commands to it. For example, the host device can send a read command to the storage device to access data stored in one or more logical blocks of the storage device. In this case, the read command may include several phases, such as a command issuance phase, a data transfer phase, and a response phase. During the command issuance phase, the host device can issue a read command to the storage device, causing the storage device to retrieve the data associated with the read command from the logical blocks stored in the storage device. During the data transfer phase, the storage device can transfer the data corresponding to the read command to the host device, and once all the data has been transferred to the host device, the storage device can send a response to the host device during the response phase (indicating that all data has been successfully transferred).

[0004] The information disclosed above in this background section is intended to enhance the understanding of the background art of this disclosure, and therefore may contain information that does not constitute prior art. Summary of the Invention

[0005] One or more example embodiments of this disclosure relate to a storage device including a configurable automatic data transfer trigger. The storage device can track out-of-order completions to automatically trigger ordered data transfers. In some embodiments, the data transfer trigger of the storage device can be dynamically configurable to reduce or minimize idle time on the data transfer bus.

[0006] According to one or more example embodiments of this disclosure, a storage device includes: a host interface for receiving a host command from a host device via the storage interface; one or more memory translation layers for performing one or more operations associated with the host command to retrieve one or more data blocks associated with the host command from storage memory; bitmap circuitry including a bitmap for tracking one or more data blocks to be transmitted to the host device in a constrained order; and a transmission trigger for triggering data transmission of the one or more data blocks to the host device in a constrained order based on the state of one or more bits of the bitmap.

[0007] In one example embodiment, the one or more data blocks may be retrieved from the storage memory in an order different from the constrained order.

[0008] In one example embodiment, consecutive bits from one or more bits of a bitmap may correspond to a constrained order.

[0009] In one example embodiment, the initial bit from a series of consecutive bits may correspond to the first data block from one or more data blocks in a constrained order.

[0010] In one example embodiment, the next adjacent bit from a series of consecutive bits may correspond to a second data block from one or more data blocks in a constrained order.

[0011] In one example embodiment, the transfer trigger can be configured to trigger a data transfer in response to a specified number of bits, starting from an initial bit, among the one or more bits of the bitmap having a state that changes from an initial state.

[0012] In one example embodiment, the one or more memory translation layers may be configured to set the corresponding bit in the bitmap to a changed state in response to performing the corresponding operation from one or more operations associated with a host command.

[0013] In one example embodiment, the one or more memory translation layers may be configured to set a specified number of bits to a changed state in an order different from the constrained order.

[0014] In one example embodiment, the bitmap circuitry can be configured to dynamically change the specified number of bits based on a threshold.

[0015] In one example embodiment, the threshold can set the specified number of bits and the position of the initial bit from the specified number of bits.

[0016] According to one or more example embodiments of this disclosure, a method for triggering data transfer from a storage device to a host device includes: receiving a host command from the host device via the storage device to retrieve data from storage memory; allocating a bitmap via the storage device in response to the host command; performing one or more operations associated with the host command via the storage device to retrieve one or more data blocks from storage memory; changing the state of a corresponding bit from one or more specified bits in the bitmap via the storage device in response to the completion of execution of a corresponding operation from one or more of the one or more operations; monitoring the specified bits of the bitmap via the storage device; and triggering data transfer of the one or more data blocks via the storage device in a constrained order in response to the specified bits of the bitmap having a state that has changed from an initial state.

[0017] In one example embodiment, the one or more operations associated with a host command may be performed to retrieve the one or more data blocks in an order different from the constrained order.

[0018] In one example embodiment, the one or more specified bits may correspond to one or more consecutive bits of a bitmap, and the one or more consecutive bits may correspond to a constrained order.

[0019] In one example embodiment, the initial bit from a series of consecutive bits may correspond to the first data block from one or more data blocks in a constrained order.

[0020] In one example embodiment, the next adjacent bit from a series of consecutive bits may correspond to a second data block from one or more data blocks in a constrained order.

[0021] In one example embodiment, data transmission can be triggered in response to a specified number of bits, starting from the initial bit, having a changed state.

[0022] In one example embodiment, the method may further include: changing the number of specified bits according to a threshold via a storage device.

[0023] In one example embodiment, the threshold can be set to a specified number of bits and the position of the initial bit from the specified number of bits.

[0024] According to one or more example embodiments of this disclosure, a storage device includes: a storage controller for performing one or more operations associated with a host command received from a host device via a storage interface, the one or more operations being used to retrieve one or more data blocks associated with the host command from storage memory; and bitmap circuitry for tracking one or more data blocks to be transmitted to the host device in a constrained order, the bitmap circuitry including: an allocated bitmap including one or more designated bits corresponding to the constrained order; a comparison bitmap circuitry for generating a comparison bitmap based on a count value and a start position indicating one or more designated bits in the allocated bitmap; and a trigger bitmap circuitry for comparing the allocated bitmap with the comparison bitmap to determine a state of a designated bit in the allocated bitmap, and for triggering data transmission of the one or more data blocks to the host device in the constrained order based on the state of the designated bit. The trigger bitmap circuitry is used to trigger data transmission in response to a designated bit having a state that changes from an initial state.

[0025] In one example embodiment, the storage controller may be configured to change the state of a corresponding bit from a specified bit to a changed state in response to the completion of a corresponding operation from one or more of the operations, and the one or more operations may be completed in an order different from the constrained order. Attached Figure Description

[0026] The above and other aspects and features of this disclosure will become clearer to those skilled in the art from the following detailed description of exemplary embodiments with reference to the accompanying drawings.

[0027] Figure 1 This is a system diagram of a storage system according to one or more exemplary embodiments of the present disclosure.

[0028] Figure 2 This is a block diagram of a storage device according to one or more exemplary embodiments of the present disclosure.

[0029] Figure 3 This is a more detailed block diagram of a storage device according to one or more exemplary embodiments of the present disclosure.

[0030] Figure 4 This is a block diagram of a transmission trigger circuit according to one or more exemplary embodiments of the present disclosure.

[0031] Figure 5 This is a schematic circuit diagram illustrating a mask bitmap circuit according to one or more exemplary embodiments of the present disclosure.

[0032] Figure 6 This is a schematic circuit diagram illustrating a comparison bitmap circuit according to one or more exemplary embodiments of the present disclosure.

[0033] Figure 7 This is a schematic circuit diagram illustrating a trigger bitmap circuit according to one or more example embodiments of the present disclosure.

[0034] Figure 8 This is a flowchart of a method for triggering data transmission according to one or more example embodiments of the present disclosure. Detailed Implementation

[0035] In the following description, exemplary embodiments will be illustrated in more detail with reference to the accompanying drawings, in which the same reference numerals throughout denote the same elements. However, this disclosure may be implemented in a variety of different forms and should not be construed as being limited to the embodiments shown herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete and will fully convey to those skilled in the art the aspects and features of this disclosure. Therefore, processes, elements, and techniques that are not essential for a person of ordinary skill in the art to fully understand the aspects and features of this disclosure may not be described. Unless otherwise stated, the same reference numerals denote the same elements throughout the drawings and written description, and therefore their description need not be repeated.

[0036] A storage device can execute a single read command issued from a host device by performing one or more read operations to retrieve data corresponding to a read command stored in one or more logical blocks on the storage device. For example, depending on the size of the data corresponding to the single read command, the storage device can perform multiple read operations to retrieve portions or blocks of data from the logical blocks. In this case, depending on the workload of the storage device, the read operations can be completed out of order, such that portions or blocks of data retrieved from the logical blocks can be received out of order. However, the storage device can send the data associated with the single read command to the host device in an appropriate order (e.g., a predetermined order or a specific order (e.g., a constrained order)) (e.g., from the lowest logical block address (LBA) to the highest LBA).

[0037] For example, a storage device can execute a read command using a host-to-device command frame, one or more device-to-host data frames, and a device-to-host response frame. The command frame for the read command can specify a start LBA and an LBA count, and a data frame can transmit up to, for example, 1024 bytes of data. In this case, if the read command requires multiple data frames to be transmitted to the host device, the data frames can be transmitted in a predetermined order (e.g., from the lowest LBA to the highest LBA). Furthermore, the storage device can perform multiple read operations to execute a single read command, such that each read operation retrieves, for example, a portion or block of data associated with the single read command (e.g., a page of data) from a corresponding logical block. However, read operations can be completed out of order depending on the workload of the storage device, such that data portions or blocks are retrieved out of order according to the predetermined order in which data is transmitted to the host device. In this case, the storage device can convert the out-of-order operation completion into ordered data frame transmission, sending the data frames to the host device in a predetermined order.

[0038] Furthermore, the storage device can transmit ordered data frames to the host device via a connection established between the storage device and the host device, allowing the connection to be opened and closed as needed or desired. In this case, the connection can be circuit-switched so that when the connection is closed, it is not shared with other host devices and / or other storage devices. Because connection resources may be limited, efficient use of connections can be expected to improve or maximize performance. Additionally, when one of the host device or storage device determines that there are no more data frames to send, the connection can degrade from full-duplex (e.g., bidirectional data transmission) to half-duplex (e.g., unidirectional data transmission). In half-duplex mode, the connection becomes idle, resulting in wasted bandwidth. Therefore, it is desirable to maintain the connection for as short a period as possible to reduce or minimize half-duplex periods, but not so short that the overhead of connection establishment becomes dominant.

[0039] According to one or more example embodiments of this disclosure, a storage device may include a hardware module (e.g., bitmap circuitry) for tracking the completion of out-of-order operations to be converted into ordered data frames for transmission. For example, in some embodiments, the hardware module may include an array of bitmaps, and each bitmap may correspond to a single host command (e.g., a single read command). In this case, each bit of the bitmap may correspond to one of multiple operations (e.g., multiple read operations) that can be executed to perform the single host command (e.g., a single read command). In other words, each bit may correspond to a data portion or block (e.g., a page of data) that is obtained as the result of the completion of a corresponding operation (e.g., a corresponding read operation) among multiple operations (e.g., multiple read operations) associated with the single host command (e.g., a single read command). When each of the data portions or blocks (e.g., a page of data) is received as the result of the completion of the corresponding operation, the state of the corresponding bit in the bitmap may change from an initial state to a changed state (e.g., from 0 to 1). In this scenario, because data portions or blocks can be read out of order, the bits in the bitmap can change to a changed state out of order. Data transfer to the host device can be automatically triggered in response to a sufficient number of bits (e.g., consecutive bits) from the corresponding bitmap, starting from the initial bit (e.g., the least significant bit), having a changed state. This indicates that data is ready to be transferred to the host device in the appropriate order. In one example, the bitmap can be used to track the acquisition of each data block to be transferred to the host device. For example, the bitmap can be used to track whether the acquisition of each data block to be transferred to the host device is complete, and if so, data transfer can be triggered.

[0040] According to one or more example embodiments of this disclosure, a hardware module (e.g., bitmap circuitry) may have dynamically configurable data transfer triggers to improve or maximize bus utilization and / or bus efficiency. For example, in some embodiments, a sufficient number of consecutive bits for automatically triggering data transfers can be dynamically configured based on a suitable or desired threshold, allowing the burst size of the data transfer to be varied. In this case, for example, by ensuring an appropriate amount of data is ready to be sent before the connection is closed, the threshold may be set to minimize or reduce connection establishment overhead, and / or, for example, by ensuring data is ready to be transmitted before the connection is closed, but without causing excessive data to be sent on a single connection, the threshold may minimize or reduce bus idle time. For example, the threshold may be dynamically adjusted as needed or desired at start time, during runtime, and / or on a per-command basis, depending on the performance of the storage device and / or storage system, the application, and / or implementation. Therefore, idle time on the data transfer bus can be reduced, half-duplex connections can be reduced, and performance can be improved.

[0041] In some embodiments, the storage device includes a hardware module (e.g., bitmap circuitry) for automatically triggering data transfers, without using firmware or software. Using firmware or software to manage data transfers can increase complexity, make them difficult to tune, and / or maintain. On the other hand, a hardware module according to some embodiments of this disclosure can automatically trigger data transfers based on the state of bits in a corresponding bitmap, and the data transfer trigger can be dynamically configured as needed or desired. Furthermore, the hardware module can increase parallelism, whereas using firmware or software can result in more serial processing. Therefore, the hardware module (e.g., bitmap circuitry) can improve performance and increase the flexibility of the storage device.

[0042] Figure 1 This is a system diagram of a storage system according to one or more exemplary embodiments of the present disclosure.

[0043] In short, a storage system 100 according to one or more embodiments of this disclosure may include a host device (e.g., a host computer) 102 and a storage device 104. The host device 102 may issue a command to the storage device 104, causing the storage device 104 to retrieve data associated with the command stored in the storage device 104. For example, the host device 102 may be communicatively connected to the storage device 104 (e.g., via storage interface 110) and may issue a read command to the storage device 104, causing data corresponding to the read command to be retrieved (e.g., read) from the storage device 104 and sent to the host device 102. Once all data has been successfully sent to the host device 102, the storage device 104 may send an appropriate response to the host device 102 (indicating that all data associated with the read command has been successfully sent).

[0044] In one or more example embodiments, storage device 104 may include a hardware module (e.g., bitmap circuit 118) for tracking the completion of out-of-order operations and automatically triggering the transmission of ordered data frames. For example, in some embodiments, the hardware module may include an array of bitmaps and auxiliary logic. Each bitmap may include n bits (where n is a natural number greater than 0) representing data to be transmitted for a single read command. For example, each bit may represent a portion or block of data (e.g., a page of data) to be read from storage device 102 (e.g., from storage memory 116). In other words, each bitmap may correspond to a mapping of bits for a single read command, where each bit represents the read state of a portion or block of data corresponding to a single read command. The hardware module may identify the bit number corresponding to the initial bit (e.g., the least significant bit) in a single burst of data to be transmitted and may set the size of the burst in bits. Once a suitable or desired number of consecutive bits from the corresponding bitmap (e.g., starting from the initial bit or least significant bit) have a changed state from the initial state (which can indicate that data is ready to be transmitted to the host device in the appropriate order), the hardware module can automatically trigger the data transmission to the host device 102.

[0045] For more details, see [link to relevant documentation]. Figure 1 The host device 102 may include a host processor 106 and a host memory 108. The host processor 106 may be a general-purpose processor of the host device 102, such as a central processing unit (CPU) core. The host memory 108 may be considered as a high-performance main memory (e.g., primary memory) of the host device 102. For example, in some embodiments, the host memory 108 may include (or may be) volatile memory, such as dynamic random access memory (DRAM). However, this disclosure is not limited thereto, and the host memory 108 may include (or may be) any suitable high-performance main memory (e.g., primary memory) alternative to the host device 102 known to those skilled in the art. For example, in other embodiments, the host memory 108 may be a relatively high-performance non-volatile memory (such as NAND flash memory, phase-change memory (PCM), resistive RAM, spin-transfer torque RAM (STTRAM), any suitable memory based on PCM technology, memristor technology, and / or resistive random access memory (ReRAM)), and may include, for example, chalcogenides.

[0046] Storage device 104 can be considered as an auxiliary storage device capable of permanently storing data accessible by host device 102. In this context, storage device 104 may include (or may be) a relatively slow memory compared to the high-performance memory of host memory 108. For example, in some embodiments, storage device 104 may be auxiliary storage for host device 102, such as a solid-state drive (SSD). However, this disclosure is not limited thereto, and in other embodiments, storage device 104 may include (or may be) any suitable storage device, such as magnetic storage devices (e.g., hard disk drives (HDDs), etc.), optical storage devices (e.g., Blu-ray disc drives, optical disc (CD) drives, digital versatile optical disc (DVD) drives, etc.) and / or other types of flash memory devices (e.g., USB flash drives, etc.). In various embodiments, storage device 104 may conform to large form factor standards (e.g., 3.5-inch hard disk drive form factor), small form factor standards (e.g., 2.5-inch hard disk drive form factor), M.2 form factor, and / or E1.S form factor, etc. In other embodiments, storage device 104 may conform to any suitable or desired derivative of these form factors. For convenience, storage device 104 may be described in the context of SSDs below, but this disclosure is not limited thereto.

[0047] Storage device 104 can be communicatively connected to host device 102 via storage interface 110. Storage interface 110 can (e.g., using connectors and protocols) facilitate communication between host device 102 and storage device 104. In some embodiments, storage interface 110 can facilitate the exchange of storage requests and responses between host device 102 and storage device 104. In some embodiments, storage interface 110 can facilitate data transfer to and from host memory 108 of host device 102 via storage device 104. For example, in one embodiment, storage interface 110 (e.g., connectors and protocols thereof) may include (or may conform to) Small Computer System Interface (SCSI) and / or Serial Attached SCSI (SAS), etc. However, this disclosure is not limited thereto. In other embodiments, storage interface 110 (e.g., connector and its protocol) may conform to other suitable storage interfaces, such as Peripheral Component Interconnect Rapid (PCIe), Remote Direct Memory Access over Ethernet (RDMA), Serial Advanced Technology Attachment (SATA), Fibre Channel, Non-Volatile Memory Rapid (NVMe), and / or NVMe over Fibre (NVMe-oF), etc. In other embodiments, storage interface 110 (e.g., connector and its protocol) may include (or may conform to) various general-purpose interfaces, such as Ethernet, Universal Serial Bus (USB), etc. For convenience, storage interface 110 may be described hereinafter in the context of a SAS interface, but this disclosure is not limited thereto.

[0048] In some embodiments, storage device 104 may include a host interface 112, a storage controller 114, and a storage memory 116. The host interface 112 may be connected to the storage interface 110 and may respond to input / output (I / O) requests received from the host device 102 via the storage interface 110. For example, the host interface 112 may receive commands (e.g., read commands) from the host device 102 via the storage interface 110 and may send commands to the storage controller 114 to retrieve data associated with the command from the storage memory 116. The storage controller 114 may provide an interface for controlling the storage memory 116 and providing access to and from the storage memory 116. For example, the storage controller 114 may include at least one processing circuitry embedded thereon for interface connection with the storage memory 116. The processing circuitry may include, for example, digital circuitry (e.g., a microcontroller, microprocessor, digital signal processor, or logic device (e.g., a field-programmable gate array (FPGA) and / or application-specific integrated circuit (ASIC)) capable of executing data access instructions (e.g., via firmware and / or software) to provide access to data stored in and from storage memory 116 according to the data access instructions. For example, data access instructions may include any suitable data storage and retrieval algorithm (e.g., read / write) instructions, etc. Storage memory 116 may permanently store data received from host device 102 across multiple logical blocks. For example, in one embodiment, storage memory 116 may include non-volatile memory, such as NAND flash memory. However, this disclosure is not limited thereto, and storage memory 116 may include any suitable memory depending on the type of storage device 104 (e.g., disk, magnetic tape, and / or optical disc, etc.).

[0049] Although host interface 112 and storage controller 114 are shown as separate components of storage device 104, this disclosure is not limited thereto. For example, host interface 112 and storage controller 114 are shown as separate components to distinguish between the front end of storage device 104 that receives commands from host device 102 and the back end of storage device 104 that retrieves (e.g., reads) data associated with the commands from storage memory 116. Thus, in various embodiments, host interface 112 may be integrated with storage controller 114 (e.g., as an integrated circuit (IC)) or may be implemented separately from storage controller 114 and attached to storage device 104 (e.g., as a system-on-a-chip (SOC) etc.).

[0050] In one or more example embodiments, storage device 104 may further include bitmap circuitry 118 and transfer circuitry 120. Bitmap circuitry 118 may track out-of-order operation completions and may automatically trigger ordered (e.g., constrained order) data frame transfers. Transfer circuitry 120 may receive triggers (e.g., trigger bits) from bitmap circuitry 118 to transfer data to host device 102 in a predetermined order for corresponding commands. For example, in one embodiment, bitmap circuitry 118 may include an array of bitmaps, and each bitmap may correspond to a single host command. Each bit in a bitmap corresponding to a single host command may represent a portion or block of data (e.g., a page of data) to be read from storage memory 116. For example, a portion or block of data may be the smallest unit of data (such as a page of data) that can be read from storage memory 116 by a single read operation. For a non-limiting example, if a single read command requires reading 5 pages of data from storage memory 116 (e.g., from a logical block of storage memory 116), then 5 bits (e.g., 5 consecutive bits) in the corresponding bitmap can correspond to the 5 pages of data to be read from storage memory 116. The corresponding bits in the bitmap can be changed when each of the 5 pages of data is read from storage memory 116 in any order (e.g., when each corresponding read operation is completed in any order). Once each of the 5 bits has been changed, bitmap circuitry 118 can trigger the transfer of the data corresponding to the single read command to transfer circuitry 120.

[0051] In some embodiments, bitmap circuitry 118 may be implemented as a hardware module (e.g., electronic circuitry) communicatively connected to host interface 112 and storage controller 114. For example, in one embodiment, bitmap circuitry 118 may be implemented as an IC attached to (or mounted on) storage device 104 (e.g., bitmap circuitry 118 may be embedded on the same board or circuit board as storage device 104). For example, bitmap circuitry 118 may be implemented on storage device 104 (e.g., it may be attached to or mounted on storage device 104). However, this disclosure is not limited thereto. For example, in another embodiment, bitmap circuitry 118 may be implemented on a circuit board (e.g., a printed circuit board PCB) separate from the circuit board of storage device 104 and may be communicatively connected to storage device 104.

[0052] Although the transmission circuitry 120 is shown as a separate component of the storage device 104, this disclosure is not limited thereto. For example, the transmission circuitry 120 is shown as a separate component to distinguish data transmission from transmission triggering. Thus, in various embodiments, for example, the transmission circuitry 120 may be implemented as part of the host interface 112 and / or part of the bitmap circuitry 118.

[0053] Figure 2 This is a block diagram of a storage device according to one or more exemplary embodiments of the present disclosure.

[0054] In short, host device 102 can send commands to storage device 104 via storage interface 110. Commands may include Level 1 BAs (Levels of Entries) that cause storage device 104 to execute commands on data stored in storage memory 116 (e.g., in one or more logical blocks of storage memory 116) according to the Level 1 BAs. For example, Level 1 BAs may include a start Level 1 BA and a Level 1 BA count. Storage device 104 can execute commands by performing multiple operations, and the operations can be performed in any order depending on the workload of storage device 104. Once the appropriate number of operations are completed, storage device 104 can transfer data to host device 102 in an appropriate order (e.g., a predetermined order or a specific order) (e.g., from lowest Level 1 BA to highest Level 1 BA) corresponding to the commands.

[0055] For more details, see [link to relevant documentation]. Figure 2 The host interface 112 can receive commands from the host device 102 via the storage interface 110. For example, the command could be a read command, but this disclosure is not limited thereto. The host interface 112 can send commands to the storage controller 114 to perform one or more operations associated with the command, and can allocate a bitmap in the bitmap circuitry 118 for the command. The storage controller 114 can execute one or more operations associated with the command in any order depending on the workload, and can change the state of each bit in the allocated bitmap upon completion of each operation.

[0056] For example, storage controller 114 may include what is commonly referred to as memory translation layer 202 (see [link]). Figure 3 One or more memory translation layers 202_1 and 202_2 (e.g., flash memory translation layers) may be connected to one or more NAND dies 204_1 and 204_2 of the storage memory 116. In this configuration, data associated with a command may be stored in any one or more of the NAND dies 204_1 and 204_2, allowing any one or more of the memory translation layers 202 to perform operations associated with a read command to retrieve a portion or block of data (e.g., a page of data) from their respective NAND dies. Each memory translation layer 202 may include queues for any number of operations for its respective one or more NAND dies, such that one or more operations associated with a command may be completed in any order according to the queues of the memory translation layers 202. Therefore, one or more operations associated with a read command may be completed in any order, allowing the data portion or block of data associated with the command to be read from the NAND dies 204_1 and 204_2 in any order.

[0057] Bitmap circuitry 118 can track the state of bits in an allocated bitmap and can trigger automatic data transfer in response to a sufficient number of bits (e.g., a sufficient number of consecutive bits) having changed states, starting from the initial bit (e.g., the least significant bit). For example, the allocated bitmap can have multiple consecutive bits, and each bit can correspond to one of multiple operations associated with a command. In this case, because operations can be completed out of order, the bits in the allocated bitmap can change out of order corresponding to the completion of out-of-order operations. Therefore, consecutive bits can correspond to a predetermined order of data portions or blocks to be sent to host device 102, such that a sufficient number of consecutive bits having changed states starting from the initial bit can indicate that data is ready to be transmitted to the host device in the appropriate order (e.g., in a predetermined order).

[0058] For a non-limiting example, when a read command requires reading three pages of data from NAND dies 204_1 and 204_2 to send to host device 102 in a predetermined order from the first page, second page, and third page, three consecutive bits can be assigned in an allocated bitmap to correspond to the three pages of data. In this case, the first bit (e.g., the least significant bit) from the three consecutive bits can correspond to the first page, the next bit from the three consecutive bits can correspond to the second page, and the last bit from the three consecutive bits can correspond to the third page, such that the predetermined order of the three pages of data can be maintained according to the order of the bits. Because the three pages of data can be read from NAND dies 204_1 and 204_2 in any order, the storage controller 114 can change the state of the three bits in the allocated bitmap in any order. However, because the data can be sent to host device 102 in a predetermined order, data transfer may not be triggered until at least the initial bit (or some configurable number of consecutive bits starting from the initial bit) has a changed state (indicating that the data of the corresponding page has been received).

[0059] In some embodiments, bitmap circuitry 118 may have a configurable data transfer trigger for controlling the burst size of data to be sent to host device 102. For example, bitmap circuitry 118 may have a configurable threshold for setting an appropriate number of bits, starting from the initial bit, that may have changed states before triggering data transfer. The threshold can be dynamically adjusted to improve the performance of storage device 104. For example, the threshold can be dynamically adjusted to reduce connection establishment overhead, reduce idle time on the data transfer bus, and / or reduce half-duplex connections, etc. Thus, performance can be improved by dynamically adjusting the threshold as needed or desired. Bitmap circuitry 118 may track the state of each bit in an assigned bitmap for a single command, and once an appropriate number of bits, starting from the initial bit in the assigned bitmap, have changed states, bitmap circuitry 118 may trigger transfer circuitry 120 to transfer data to the host device in a predetermined order within a single burst.

[0060] Figure 3 This is a more detailed block diagram of a storage device according to one or more exemplary embodiments of the present disclosure.

[0061] Reference Figure 3 In some embodiments, host interface 112 may include scheduling circuitry 302. Host interface 112 may receive host commands from host device 102, and scheduling circuitry 302 may issue requests to storage controller 114 to perform one or more operations associated with the host command. For example, when the host command is a read command, scheduling circuitry 302 may issue a read request to storage controller 114 to perform one or more read operations associated with the read command, such that each read operation retrieves a portion or block of data (e.g., a page of data) associated with the read command from storage memory 116.

[0062] In some embodiments, scheduling circuitry 302 can identify multiple pages of data that can be read sequentially to execute a single read command, and can issue read requests to storage controller 114 to retrieve multiple pages of data from storage memory 116 (e.g., from NAND dies 204_1 and 204_2) within a threshold-sized block corresponding to a single transfer burst. For example, in some embodiments, scheduling circuitry 302 can generate a data structure (e.g., a direct memory access (DMA) descriptor) DD for each page to be read, and can send the DD index corresponding to the data structure DD to storage controller 114 to read the data of the corresponding page from storage memory 116 (e.g., from NAND dies 204_1 and 204_2). In some embodiments, scheduling circuitry 302 can send multiple read requests (e.g., multiple DD indices) to storage controller 114 for a threshold-sized block that satisfies the size of a single transfer burst, such that the corresponding threshold number of pages are read from storage memory 116 at a time. For example, if the threshold is set to 8, such that 8 consecutive pages of data are transmitted to the host device 102 at a time, the scheduling circuit 302 can generate a data structure DD for each of the 8 pages, and can send the corresponding DD index for the 8 pages to the storage controller 114 to read the 8 pages of data from the storage memory 116.

[0063] In some embodiments, scheduling circuitry 112 may issue a set of read requests to storage controller 114 to read multiple pages of data before the previous data transfer is complete. For example, once a data block of a threshold size associated with a read request is ready to be sent to host device 102, scheduling circuitry 302 may issue the next set of read requests to storage controller 114 to read the next threshold-sized data block from storage memory 116. In this case, the next set of read requests may be for the same read command or for different commands. For a non-limiting example, a single read command may require 15 read operations to retrieve 15 pages of data from storage memory 116, and the threshold may be set to 8 such that once the 8 consecutive bits of the allocated bitmap corresponding to the first 8 pages, starting from the initial bit, have a changed state, the first 8 pages can be transferred to host device 102 at once (e.g., during an open connection). In this case, while the first 8 pages are being transferred to host device 102, scheduling circuitry 302 may issue the next 7 read requests to storage controller 114 in parallel to retrieve the next 7 pages to be transferred to host device 102 during the next transfer burst. Therefore, parallelism can be improved, which can lead to better performance.

[0064] In some embodiments, for example, when more consecutive pages of data for a single host command are ready to be sent at the end of a single transmission burst, scheduling circuitry 302 may extend the single transmission burst to include more pages of data within the single transmission burst. Returning to our example of 15 pages of data, in some embodiments, when the data of the last page (e.g., page 8) is being transmitted to host device 102 in the first transmission burst, if the data of the first page (e.g., page 9) is ready to be transmitted in a second transmission burst, scheduling circuitry 302 may extend the first transmission burst to include the data of the first page (e.g., page 9) of the second transmission burst. Therefore, connection establishment overhead can be reduced.

[0065] In some embodiments, scheduling circuitry 302 may allocate a bitmap in bitmap circuitry 118 for each host command, allowing bitmap circuitry 118 to track out-of-order read operations for each host command. For example, in some embodiments, scheduling circuitry 302 may allocate a bitmap to a single host command and may set a relative start position (e.g., indicating the position of the initial bit) in the bitmap for a single host command, as well as a count value for the number of bits in the bitmap that may have changed states to trigger ordered (e.g., constrained order) data transfers. For example, the count value may correspond to the number of read requests issued to storage controller 114 within a single transfer burst, such that the count value determines the transfer burst size (e.g., a data transfer threshold size) in bits. Thus, in some embodiments, the count value and relative start position may be dynamically set to control the threshold size, which corresponds to the appropriate number of bits that may have changed states to trigger data transfers. In one embodiment, a corresponding bit in a corresponding bitmap may be initially set to an initial state that can be initialized, for example, upon power-up.

[0066] Although scheduling circuitry 302 is shown as part of host interface 112, this disclosure is not limited thereto. For example, in various embodiments, scheduling circuitry 302 may be implemented as a separate circuit (e.g., electronic circuitry) connected to host interface 112 and storage controller 114, may be implemented as part of storage controller 114, may be implemented as part of host interface 112 and storage controller 114, etc. In another embodiment, scheduling circuitry 302 may be implemented in firmware or software, for example, as part of host interface 112 and / or as part of storage controller 114.

[0067] In some embodiments, when a read request is made by storage controller 114 (e.g., by memory translation layer 202), storage controller 114 (or the corresponding memory translation layer 202) may change the corresponding bit in the bitmap to have a changed state (indicating that data of the corresponding page has been read). For example, in some embodiments, storage controller 114 (or the corresponding memory translation layer 202) may provide a readiness index to bitmap circuitry 118 (indicating that a page of data (e.g., a specific bit in the bitmap) corresponding to a specific data structure DD is now available). In some embodiments, portions or blocks of data (e.g., multiple pages of data) read from storage memory 116 may be stored in a buffer, allowing transfer circuitry 120 to send data from the buffer to host device 102. In this case, storage controller 114 (or the corresponding memory translation layer 202) may also send a buffer index to bitmap circuitry 118 (indicating the location of the data of the page used for data transfer).

[0068] Bitmap circuitry 118 can monitor specified bits (e.g., a threshold number of bits starting from the initial bit) in a currently used bitmap (e.g., the bitmap currently assigned to a host command), and can detect bitmaps where specified bits have changed states. When bitmap circuitry 118 detects a bitmap where specified bits have changed states, bitmap circuitry 118 can trigger transfer circuitry 120 to transfer corresponding data in a predetermined order, and can initialize the bits in the bitmap to their initial states for use by subsequent transfers or subsequent commands. In one embodiment, if scheduling circuitry 302 issues a set of read requests to storage controller 114 to read multiple pages of data before the previous data transfer is completed, storage controller 114 can change the bit states before a subsequent data transfer is specified, so that data is available once the next data transfer is specified, and the next data transfer can be triggered immediately once the previous data transfer is completed.

[0069] For example, in some embodiments, bitmap circuitry 118 may include a count status register 304, a ready bitmap register 306, a buffer index register 308, and transfer trigger circuitry (or transfer trigger or data transfer trigger) 310. In one embodiment, count status register 304 may be set by scheduling circuitry 302 to allocate bitmaps for host commands. In one embodiment, count status register 304 may be a 2D array, where each row represents a data transfer index (TR index) corresponding to a single host command. For example, each row may include a count value corresponding to a threshold number of bits that may be set before triggering a corresponding data transfer for a single host command, and a relative start index of bits indicating the relative starting position of the initial bit in the allocated bitmap.

[0070] In one embodiment, the ready bitmap register 306 can be set according to a ready index provided by the storage controller 114 (or the corresponding memory translation layer 202) to change bits in the corresponding bitmap when a read operation is completed. For example, in one embodiment, the ready bitmap register 306 may be a 2D array, where each row corresponds to a specific TR index (e.g., a specific host command). Each row may include a bitmap (e.g., a 64-bit bitmap) comprising multiple bits corresponding to a maximum number of read requests that can be generated by the scheduling circuitry 302 within a single transmit burst. Whenever the storage controller 114 provides a ready index (e.g., by writing the ready index into a special function register (SFR)), the bitmap circuitry 118 may (e.g., according to the TR index) change the state of the corresponding bit in the corresponding bitmap (indicating that the corresponding data portion or block of data (e.g., a page of data) is ready to be transmitted).

[0071] In some embodiments, the buffer index register 308 may be set by the storage controller 114 (or the corresponding memory translation layer 202) to indicate the location of data ready for transmission. For example, when the storage controller 114 reads a specific portion or block of data (e.g., a page of data) from the storage memory 116, the read data may be stored in a buffer to be retrieved during the corresponding data transfer. Therefore, in some embodiments, the buffer index register 308 may include a buffer index indicating the location of data to be transmitted during the corresponding data transfer.

[0072] In some embodiments, the transfer trigger circuit 310 can determine whether an appropriate number of bits (e.g., consecutive bits) in the corresponding bitmap of the ready bitmap register 306 have a changed state (indicating that the data corresponding to the bit is ready to be transferred). For example, in some embodiments, the transfer trigger circuit 310 can monitor a specific bit (e.g., a specific bit identified based on a relative start position and count value) of the currently used bitmap (e.g., the bitmap currently assigned to a host command), and can detect bitmaps in which the specific bit (e.g., a threshold number of bits) has a changed state. In response to detecting a bitmap with a specific bit having a changed state, the transfer trigger circuit 310 can automatically trigger the transfer of the data corresponding to the bitmap. For example, in some embodiments, the transfer trigger circuit 310 can (e.g., according to a TR index) set the trigger bit corresponding to the assigned bitmap to the transfer circuit 120 to trigger the corresponding data transfer. Reference will be made below. Figures 4 to 7 The transmission trigger circuit 310 is described in more detail.

[0073] The transfer circuit 120 can transfer data for a corresponding host command to the host device 102 based on a trigger (e.g., a trigger bit) from the bitmap circuit 118. For example, the transfer circuit 120 may include a transfer register 312, a context generator 314, and a buffer reset trigger 316. The transfer register 312 may be an SFR including a trigger bitmap for initiating data transfer when a corresponding bit (e.g., a trigger bit) in the trigger bitmap is set according to a corresponding TR index received from the transfer trigger circuit 310. The context generator may sort the data corresponding to the bitmap in a predetermined order to initiate data transfer to the host device 102 in a predetermined order. Upon successful data transfer, the buffer reset trigger 316 may release (e.g., reset) the buffer used for the transferred data, making the buffer available for subsequent transfers.

[0074] Figure 4 This is a block diagram of a transmission trigger circuit according to one or more exemplary embodiments of the present disclosure. Figure 5 This is a schematic circuit diagram illustrating a mask bitmap circuit according to one or more exemplary embodiments of the present disclosure. Figure 6 This is a schematic circuit diagram illustrating a comparison bitmap circuit according to one or more exemplary embodiments of the present disclosure. Figure 7 This is a schematic circuit diagram illustrating a trigger bitmap circuit according to one or more example embodiments of the present disclosure.

[0075] Reference Figure 4 The transmission trigger circuit 310 may include a mask bitmap circuit 402, a comparison bitmap circuit 404, and a trigger bitmap circuit 406. In short, the mask bitmap circuit 402 can transform the count value and relative start position in the count status register 304 for a specific host command (e.g., for a specific TR index) to generate a mask bitmap representing the count value relative to the relative start position in bits. The comparison bitmap circuit 404 can generate a comparison bitmap based on the mask bitmap, which can be used to compare the count value with a specified bit in the corresponding bitmap of the ready bitmap register 306 that has a changed state. The trigger bitmap circuit 406 can compare the comparison bitmap with a corresponding bitmap (e.g., the corresponding DD ready bitmap) to generate a trigger bit for automatically triggering data transmission.

[0076] For more details, see [link to relevant documentation]. Figure 5 In some embodiments, the mask bitmap circuit 402 can generate the mask bitmap 502 based on the count value stored in a specific row of the count status register 304 and the relative starting position (e.g., relative starting index). For example, in Figure 5In this context, count states [0] to count states

[255] may represent rows of the count state register 304. In some embodiments, the mask bitmap 502 may be used to handle wrap-up conditions. For example, in one embodiment, if the bitmap in the ready bitmap register 306 is a 64-bit bitmap and the corresponding count value is 64 and the corresponding relative start index is 63, then the mask bitmap 502 may be a 128-bit bitmap (e.g., a bitmap including M[0] to M

[127] ). In this case, when a comparison bitmap is generated from the mask bitmap, the comparison bitmap may be generated as a 64-bit bitmap (e.g., a bitmap including C[0] to C

[63] ) such that the comparison bitmap can be compared with the corresponding 64-bit bitmap in the ready bitmap register 306 (e.g., the corresponding DD ready bitmap). In some embodiments, the comparison bitmap may be generated, for example, by performing a bitwise OR operation on the high 64 bits and low 64 bits of the mask bitmap followed by negation (e.g., inversion). For example, bit 63 in mask bitmap 502 can be set as the initial bit (e.g., bit 0 or least significant bit) of the corresponding comparison bitmap, which has an appropriate number of consecutive bits starting from the initial bit corresponding to the other bits in a specified number of bits (e.g., a threshold number of bits).

[0077] In some embodiments, the mask bitmap circuit 402 can select one of the rows of the count status register 304 based on a TR index received from either the scheduling circuit 302 or the storage controller 114. For example, because the scheduling circuit 302 and the storage controller 114 perform separate processing, the TR index can be received from either the scheduling circuit 302 or the storage controller 114 in any order. The scheduling circuit 302 may provide the TR index, for example, when allocating a bitmap for a host command as discussed above. For example, the scheduling circuit 302 may provide the TR index to allocate a bitmap to a new host command, to set a threshold (e.g., a count value and / or a relative start position) for the next transmission of data associated with an existing host command, to allocate a bitmap for one or more read-ahead requests, and / or to expand the burst size for data transmissions corresponding to a particular host command, etc. For example, when a ready index is provided, the storage controller 114 may provide a TR index such that the corresponding bitmap in the ready bitmap register 306 can be compared to determine whether the appropriate number of bits in the corresponding bitmap have a changed state.

[0078] For example, in some embodiments, the mask bitmap circuit 402 may include a first multiplexer (MUX) 504, a finite state machine (FSM) 506, a second MUX 508, a counting left shift circuit 510, a subtractor circuit 512, and a start left shift circuit 514. The first MUX 504 can select either a first TR index (e.g., a first TR index supplied by the scheduling circuit 302) or a second TR index (e.g., a second TR index supplied by the storage controller 114) as a selection signal for the second MUX 508. In some embodiments, the first MUX 504 may select either the first TR index or the second TR index based on an arbitration signal provided by the FSM 506. For example, since the first TR index and the second TR index can be received in any order as discussed above, the arbitration signal may be provided to handle, for example, situations where the first TR index and the second TR index are received simultaneously or substantially simultaneously. In this case, the arbitration signal can be controlled based on the state of the FSM 506. For example, in one embodiment, because the storage controller 114 can operate during SFR writes, the storage controller 114 can be given a higher priority than the scheduling circuit 302.

[0079] Still refer to Figure 5 In some embodiments, the second MUX 508 can select a row from the rows of the count status register 304 based on either a first TR index or a second TR index. As discussed above, each row in the count status register 304 can include a count value for a bit in the corresponding bitmap and a relative starting position, obtainable based on the TR index. The count left shift circuit 510 can convert the count value into a bitmap. For example, the count left shift circuit 510 can generate an array of bits with a value of 1 followed by the number of 0s (e.g., 1 << count value). For a non-limiting example, assuming the value is 5, the count left shift circuit 510 can generate an array of bits with a value of "100000" (e.g., 1 << 5 = "100000").

[0080] Subtractor circuit 512 can transform the output of counter left shift circuit 510 to generate a number of bits corresponding to the count value with a bit value of 1. For example, subtractor circuit 512 can subtract the value 1 from the output of counter left shift circuit 510 (e.g., 1 << count value - 1). Returning to a non-limiting example of a count value of 5, subtractor circuit 512 can subtract 1 from "100000" according to the output of counter left shift circuit 510, such that the subtractor circuit generates a bitmap with a number of consecutive bits corresponding to the count value having a bit value of 1 (e.g., 100000 - 1 = "11111").

[0081] The start left shift circuit 514 can transform the output of the subtractor circuit to generate a mask bitmap 502 based on the relative start position. For example, the start left shift circuit 514 can shift the output of the subtractor circuit 512 to the left by the number of the relative start position. Returning to a non-limiting example of a count value of 5, if the relative start position is 0, the start left shift circuit 514 can shift the output of the subtractor circuit 512 (e.g., "11111") to the left relative to the start position 0 (e.g., 11111 << 0 = 11111).

[0082] Reference Figure 6 In some embodiments, the comparison bitmap circuit 404 can generate a comparison bitmap 602 based on the mask bitmap 502 for comparison with the bitmap allocated in the ready bitmap register 306. For example, in some embodiments, the comparison bitmap circuit 404 may include a plurality of logic gates (e.g., 604_1 to 604_64) and a plurality of inverters (e.g., 606_1 to 606_64). For example, in some embodiments, each of the plurality of logic gates may be an OR gate for performing a 2-bit OR operation between the high and low bits of the mask bitmap 502. In this case, for example, the first OR gate 604_1 can perform an OR operation between the first bit M[0] and the 65th bit M

[64] of the mask bitmap 502, the second OR gate 604_2 can perform an OR operation between the second bit M[1] and the 66th bit M

[65] of the mask bitmap 502, and so on, such that the 64th OR gate 604_64 performs an OR operation between the 64th bit M

[63] and the 128th bit M

[127] of the mask bitmap 502. Thus, the OR gates can remove the termination conditions as discussed above. The output of each of the OR gates can be inverted by the corresponding one in the inverter. Thus, except for those specified bits (which can be generated to have a bit value of 0) corresponding to the data portion or data block (e.g., a page of data) to be read by the storage controller 114 (or the corresponding memory conversion layer 202), the comparison bitmap 602 can be generated to have all bits of 1.

[0083] Reference Figure 7In some embodiments, the trigger bitmap circuit 406 may compare the comparison bitmap 602 with the allocated bitmap of the ready bitmap register 306 to generate a trigger bit for triggering a data transfer. For example, as discussed above, whenever the storage controller 114 (or the corresponding memory translation layer 202) sends a ready index corresponding to a page of data read from the storage memory 116 (e.g., by writing a ready index into the SFR), the state of the corresponding bit in the allocated bitmap of the ready bitmap register 306 may be set to have a changed state. The trigger bitmap circuit 406 may compare the bit in the corresponding bitmap of the ready bitmap register 306 with the bit in the comparison bitmap 602 to determine whether a specified bit in the allocated bitmap of the ready bitmap register 306 corresponding to a portion or block of data (e.g., a page of data) to be read by the storage controller 114 (or the corresponding memory translation layer 202) has a changed state.

[0084] For example, in some embodiments, the trigger bitmap circuit 406 may include a bitwise OR circuit 704, a reduction AND gate 706, and a demultiplexer (DMUX) 708. The bitwise OR circuit 704 can perform a bitwise OR operation between bits of the comparison bitmap 602 and bits of the allocated bitmap in the ready bitmap register 306. The reduction AND gate 706 can perform an AND operation on the output of the bitwise OR circuit 704, and can output 1 if each output of the bitwise OR circuit 704 has a value of 1, which may indicate that all ready indices have been received, or it can additionally output 0 if any output of the bitwise OR circuit is 0. For example, because the comparison bitmap 602 can have all bits of 1 except for those specified bits (which can have a value of 0) corresponding to the portion or block of data (e.g., a page of data) to be read by the storage controller 114 (or the corresponding memory translation layer 202), the bitwise OR circuit 704 can output all bits of 1 if all specified bits in the allocated bitmap of the ready bitmap register 306 have a changed state (e.g., a value of 1). On the other hand, if any specified bit in the allocated bitmap still has an initial state (e.g., a bit value of 0), the bitwise OR circuit 704 can output 0 for those bits. Therefore, if all ready indices have been received (which sets the corresponding bit in the ready bitmap register 306 to have a value of 1), the reduction AND gate 706 can output 1, or if at least one of the specified bits still has an initial state (e.g., indicating that the ready index for that bit has not yet been received), the reduction AND gate 706 can additionally output 0.

[0085] The DMUX 708 can assign the output from the reducing AND gate 706 to a corresponding bit in the trigger bitmap 702. The corresponding bit in the trigger bitmap 702 can be selected based on a TR index (e.g., a first or second TR index selected by an arbitration signal), and if the corresponding bit (e.g., based on a 1 from the output of the AND gate 706) is set to 1, the corresponding bit in the trigger bitmap 702 (e.g., the bit identified based on the TR index) can be set to 1 to automatically trigger the trigger transfer circuit 310 to initiate an ordered (e.g., constrained sequence) data transfer for a corresponding host command. Therefore, data transfer can be automatically triggered based on the state of a specified bit in the bitmap allocated in the ready bitmap register 306.

[0086] Figure 8 This is a flowchart of a method for triggering data transmission according to one or more example embodiments of the present disclosure. However, the present disclosure is not limited to... Figure 8 The order or number of operations of method 800 shown may be varied and can be changed to any desired order or number of operations as recognized by those skilled in the art. For example, in some embodiments, the order may be varied, or the method may include fewer or additional operations. Furthermore, the operations shown in method 800 may be performed by any suitable component or any suitable combination of components from one or more of the example embodiments described above.

[0087] Reference Figure 8 Method 800 begins, and in operation 805, a host command can be received from the host device to retrieve data from the storage memory. For example, in some embodiments, the host command may be a read command, but this disclosure is not limited thereto. The host command may be received by the storage device from the host device through a storage interface. For example, in some embodiments, host interface 112 may receive host commands from host device 102 through storage interface 110.

[0088] In some embodiments, during operation 810, a bitmap may be allocated for a host command. For example, in some embodiments, host interface 112 or scheduling circuitry 302 may send one or more requests to storage controller 114 to perform one or more operations to retrieve one or more data portions or blocks (e.g., multi-page data) associated with a host command from storage memory 116 (e.g., from one or more logical blocks of storage memory 116). In this case, host interface 112 or scheduling circuitry 302 may allocate a bitmap (e.g., from ready bitmap register 306) to the host command (e.g., according to a TR index) and may send one or more data structures (e.g., DMA descriptors) DD to storage controller 114 to perform one or more operations based on one or more data structures DD. In some embodiments, host interface 112 or scheduling circuitry 302 may provide a count value (e.g., a count value corresponding to the number of requests issued to storage controller 114) and a relative start index (corresponding to an initial bit) for the bits in the allocated bitmap, such that a specific bit in the allocated bitmap can be identified based on the number of requests issued to storage controller (or the number of data structures DD).

[0089] In some embodiments, at operation 815, an operation from one or more operations may be performed to retrieve a portion or block of data from storage memory. For example, storage controller 114 (or a corresponding one in memory translation layer 202) may perform an operation from one or more operations based on a request (or data structure DD) from one or more requests. In some embodiments, the state of a corresponding bit (e.g., a specified bit) in an allocated bitmap may be changed at operation 820. For example, in some embodiments, when an operation from one or more operations completes, the storage controller (or a corresponding one in memory translation layer 202) may (e.g., by issuing a corresponding ready index) change the state of the corresponding bit in the allocated bitmap.

[0090] In operation 825, specified bits of the allocated bitmap can be monitored to determine whether the specified bits have a changed state. For example, in some embodiments, trigger bitmap circuitry 406 can compare a corresponding comparison bitmap with a corresponding ready bitmap (e.g., the allocated bitmap) to determine whether all specified bits have a changed state. If any bit of the specified bits in operation 825 does not have a changed state (e.g., if any bit of the specified bits still has an initial state) (e.g., No in operation 825), method 800 can loop back to operation 815 to monitor the state of the specified bits when one or more operations complete. On the other hand, if all specified bits have a changed state (e.g., Yes in operation 825), ordered data transfer can be triggered in operation 830, and data can be transferred to the host device in operation 835. For example, in some embodiments, data associated with a host command can be sent in a predetermined order (e.g., in a constrained order), regardless of the order in which the operations complete. Once the data has been transferred to the host device, the storage device can send a response indicating that the data has been successfully sent, and method 800 can terminate.

[0091] In the accompanying drawings, for clarity, the relative dimensions of elements, layers, and regions may be exaggerated and / or simplified. It will be understood that although the terms "first," "second," "third," etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or portion from another. Therefore, without departing from the spirit and scope of this disclosure, the first element, component, region, layer, or portion described below may be referred to as the second element, component, region, layer, or portion.

[0092] It will be understood that when an element or layer is referred to as being "on," "connected to," or "bonded to" another element or layer, the element or layer may be directly on, directly connected to, or directly bonded to the other element or layer, or one or more intermediate elements or layers may be present. Additionally, it will be understood that when an element or layer is referred to as being "between" two elements or layers, the element or layer may be the only element or layer between the two elements or layers, or one or more intermediate elements or layers may be present.

[0093] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting of this disclosure. Unless the context clearly indicates otherwise, the singular forms “a” and “an (kind)” as used herein are intended to also include the plural forms. It will also be understood that the terms “comprising,” “including,” and “having” as used in this specification indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one (kind) of” modify the entire list of elements when following a list of elements, without modifying any individual element in that list.

[0094] As used herein, the terms “substantially,” “about,” and similar terms are used as approximate terms rather than terms of degree and are intended to account for inherent biases in measurements or calculations that will be recognized by one of ordinary skill in the art. Furthermore, when describing embodiments of this disclosure, the use of “may” means “one or more embodiments of this disclosure.” As used herein, the terms “use,” “being used,” and “being exploited” may be considered synonymous with the terms “utilize,” “being exploited,” and “being exploited.”

[0095] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms (such as those defined in a general dictionary) shall be interpreted as having the same meaning as they have in the relevant field and / or the context of this specification, and shall not be interpreted in an idealized or overly formal sense, unless expressly defined herein.

[0096] Although some exemplary embodiments have been described, those skilled in the art will readily understand that various modifications to the exemplary embodiments are possible without departing from the spirit and scope of this disclosure. It will be understood that, unless otherwise described, the description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Therefore, it will be understood that the foregoing is illustrative of various exemplary embodiments and is not to be construed as limiting to the specific exemplary embodiments disclosed herein, and that various modifications to the disclosed exemplary embodiments and other exemplary embodiments are intended to be included within the spirit and scope of this disclosure as defined in the appended claims and their equivalents.

Claims

1. A storage device, the storage device comprising: The host interface is used to receive host commands from the host device through the storage interface. One or more memory translation layers are used to perform one or more operations associated with a host command to retrieve one or more data blocks associated with the host command from storage memory; Bitmap circuitry includes an acquired bitmap for tracking each of the one or more data blocks to be transmitted to a host device; as well as A transfer trigger is used to trigger the transfer of one or more data blocks to a host device in a constrained order based on the state of one or more bits of a bitmap. The transmission trigger is configured to trigger data transmission in response to a specified number of bits, starting from an initial bit, among the one or more bits of the bitmap having a state that changes from an initial state. The bitmap circuitry is configured to dynamically change the specified quantity based on a threshold.

2. The storage device according to claim 1, wherein, The one or more data blocks are retrieved from the storage memory in an order different from the constrained order.

3. The storage device according to claim 1, wherein, Successive bits from one or more bits in the bitmap correspond to a constrained order.

4. The storage device according to claim 3, wherein, The initial bit from a consecutive bit corresponds to the first data block from one or more data blocks in a constrained order.

5. The storage device according to claim 4, wherein, The next adjacent bit from a consecutive bit corresponds to a second data block from one or more data blocks in a constrained order.

6. The storage device according to claim 1, wherein, The one or more memory translation layers are configured to set the corresponding bit in the bitmap to a state that has changed from the initial state in response to performing the corresponding operation from one or more operations associated with a host command.

7. The storage device according to claim 6, wherein, The one or more memory translation layers are configured to set the specified number of bits to a state having changed from the initial state in an order different from the constrained order.

8. The storage device according to claim 1, wherein, The threshold is dynamically adjusted to reduce connection establishment overhead, reduce idle time on the data transfer bus, and / or reduce half-duplex connections.

9. The storage device according to claim 1, wherein, The threshold is used to set the position of the specified number of bits and the initial bit from the specified number of bits.

10. A method for triggering data transfer from a storage device to a host device, the method comprising: Receive host commands from host device via storage device to retrieve data from storage memory; Bitmaps are allocated via storage devices for host commands; Perform one or more operations associated with host commands through the storage device to retrieve one or more data blocks from the storage memory; In response to the completion of the execution of the corresponding operation from one or more of the operations, the state of the corresponding bit from one or more specified bits in the bitmap is changed via a storage device; Monitor one or more specified bits of the bitmap via a storage device; as well as In response to one or more designated bits of the bitmap having a state that changes from an initial state, data transmission of the one or more data blocks in a constrained order is triggered via the storage device. The method further includes: changing the number of the one or more specified bits according to a threshold via a storage device.

11. The method according to claim 10, wherein, Perform one or more operations associated with a host command to acquire one or more data blocks in an order different from the constrained order.

12. The method according to claim 10, wherein, The one or more specified bits correspond to one or more consecutive bits of the bitmap, and the one or more consecutive bits correspond to a constrained order.

13. The method according to claim 12, wherein, The initial bit from one or more consecutive bits corresponds to the first data block from one or more data blocks in a constrained order.

14. The method according to claim 13, wherein, The next adjacent bit from one or more consecutive bits corresponds to a second data block from one or more data blocks in a constrained order.

15. The method according to any one of claims 10 to 14, wherein, Data transmission is triggered in response to a specified number of bits, starting from the initial bit, having a state that has changed from the initial state.

16. The method of claim 10, wherein, The threshold is used to set the number of the one or more specified bits and the position of the initial bit from the one or more specified bits.

17. A storage device, the storage device comprising: A storage controller is configured to perform one or more operations associated with host commands received from a host device via a storage interface, the one or more operations being configured to retrieve one or more data blocks associated with the host commands from a storage memory; as well as Bitmap circuitry for tracking the acquisition of each of the one or more data blocks to be transmitted to the host device, the bitmap circuitry comprising: The allocated bitmap includes one or more specified bits corresponding to the constrained order; A comparison bitmap circuit is configured to generate a comparison bitmap based on a count value and a start position of one or more specified bits in an indicated bitmap; and A trigger bitmap circuit is configured to compare an allocated bitmap with a comparison bitmap to determine the state of one or more specified bits in the allocated bitmap, and to trigger data transmission of one or more data blocks to a host device in a constrained order based on the state of the one or more specified bits. The trigger bitmap circuit is used to trigger data transmission in response to one or more designated bits changing from an initial state. The bitmap circuitry is configured to change the number of one or more specified bits based on a threshold.

18. The storage device according to claim 17, wherein, The storage controller is configured to: in response to the completion of a corresponding operation from one or more of the operations, change the state of the corresponding bit from one or more specified bits to the state changed from the initial state, and The one or more operations are performed in a sequence different from the constrained sequence.

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