Electronic packaging

Abstract

The present invention relates to an electronic package, comprising a multi-chip package containing a plurality of electronic components and a stress buffer layer arranged on the multi-chip package, wherein the stress buffer layer contacts the plurality of electronic components so that stress is evenly dispersed in the stress buffer layer and not concentrated in a specific area, thereby avoiding structural stress concentration in the corners of the electronic components.

Description

Technical Field

[0001] The invention relates to a packaging structure, in particular to a heat dissipation type electronic packaging component. Background Art

[0002] With the evolution of technology, the demand trend of electronic products is moving towards heterogeneous integration. For this reason, multi-chip packaging structure (MCM / MCP) is gradually emerging.

[0003] like Figure 1 The multi-chip package structure 1 shown is used to combine multiple semiconductor chips 11 onto a package substrate 10 via multiple solder bumps 13, and to cover the solder bumps 13 and the multiple semiconductor chips 11 with an underfill 14. By packaging multiple semiconductor chips 11 into a module, it has a larger number of I / Os, can greatly increase the computing power of the processor, and reduce the delay time of signal transmission, so as to be applied to high-end products with high-density circuits / high transmission speed / high stacking number / large size design.

[0004] However, if Figure 1 The multi-chip packaging structure 1 shown (the packaging gel and heat sink are omitted in the figure) has an increasing number of semiconductor chips 11 as the functional requirements increase, so the overall planar packaging area of ​​the packaging substrate 10 becomes larger and larger. Therefore, at high temperatures, the overall structure will be warped in a smiling face shape (as shown by the dotted line path L1 in the figure), and at room temperature, it will be warped in a crying face shape (as shown by the dotted line path L2 in the figure), causing the multi-chip packaging structure 1 to be stretched (as shown by the arrow direction X1 in the figure) or contracted (as shown by the arrow direction X2 in the figure) for multiple times. As a result, due to the discontinuous stress between the semiconductor chips 11, the stress at the corners of the semiconductor chips 11 will be too large, causing the bottom glue 14 between the semiconductor chips 11 to be easily broken, thereby causing poor product reliability and low process yield.

[0005] Therefore, how to overcome the above-mentioned problems of the prior art has become a difficult problem that needs to be overcome urgently in the industry. Summary of the invention

[0006] In view of the above-mentioned defects of the prior art, the present invention provides an electronic package to avoid the concentration of structural stress at the corners of electronic components.

[0007] The electronic package of the present invention comprises: a multi-chip package body, which includes a plurality of electronic components and a coating layer combining the plurality of electronic components; and a stress buffer layer, which is arranged on the multi-chip package body to contact the plurality of electronic components and the coating layer.

[0008] In the aforementioned electronic package, at least two of the plurality of electronic components are arranged separately from each other.

[0009] In the aforementioned electronic package, the covering layer is formed between any two of the electronic components.

[0010] In the aforementioned electronic package, the coating layer is a primer.

[0011] In the aforementioned electronic package, the multi-chip package further comprises a supporting structure for supporting and electrically connecting the plurality of electronic components, and the cladding layer is formed on the supporting structure. For example, the supporting structure is a circuit structure without a core layer.

[0012] In the aforementioned electronic package, the multi-chip package further comprises a packaging layer covering the plurality of electronic components and the covering layer. For example, the stress buffer layer further contacts the packaging layer. Alternatively, a surface of the electronic component is flush with the upper surface of the packaging layer.

[0013] The aforementioned electronic package further includes a heat sink coupled to the plurality of electronic components. For example, the heat sink is coupled to the stress buffer layer via a heat dissipation material. Alternatively, the stress buffer layer is disposed between the plurality of electronic components and the heat sink.

[0014] In the aforementioned electronic package, the stress buffer layer is a metal layer.

[0015] From the above, it can be seen that the electronic package of the present invention is mainly arranged on the multi-chip package through the stress buffer layer to connect the non-active surface of each electronic component and the surface of the coating layer, so that the stress is evenly dispersed in the stress buffer layer instead of being concentrated in a specific area. Therefore, compared with the prior art, the electronic package of the present invention can effectively avoid the concentration of structural stress in the corners of the electronic components, thereby avoiding the problems of poor reliability and low process yield caused by the breakage of the electronic components or the coating layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 The figure is a cross-sectional schematic diagram of an existing multi-chip packaging structure.

[0017] Figure 2 It is a cross-sectional schematic diagram of the electronic package of the present invention.

[0018] Figure 2' for Figure 2 A partial enlarged view of .

[0019] Description of Reference Numerals

[0020] 1 Multi-chip packaging structure 10,3 Packaging substrate

[0021] 11 Semiconductor chip 13 Solder bump

[0022] 14,260 Primer 2 Electronic packaging

[0023] 2a Multi-chip package 20 Carrying structure

[0024] 20a first side 20b second side

[0025] 200 Insulation layer 201 Circuit layer

[0026] 21, 21' Electronic component 21a Active surface

[0027] 21b Non-active surface 21c Side surface

[0028] 210 electrode pad 211 conductive bump

[0029] 212: coating layer 212a: upper surface

[0030] 22 Encapsulation layer 22a First surface

[0031] 22b Second surface 23 Heat sink

[0032] 230 heat sink 231 support foot

[0033] 24 stress buffer layer 25 heat dissipation material

[0034] 26 Conductor 27 Adhesive layer

[0035] 30 Conductive elements L1, L2 Dotted line path

[0036] X1,X2 arrow direction. DETAILED DESCRIPTION

[0037] The following describes the implementation of the present invention through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0038] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions under which the present invention can be implemented, so they have no substantial technical significance. Any modification of the structure, change in the proportion relationship, or adjustment of the size should still fall within the scope of the technical contents disclosed by the present invention without affecting the effects and purposes that can be achieved by the present invention. At the same time, the terms such as "upper", "lower", "first", "second", and "one" quoted in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the present invention. The change or adjustment of their relative relationship should also be regarded as the scope of the implementation of the present invention without substantially changing the technical contents.

[0039] Figure 2 and Figure 2' FIG. 2 is a cross-sectional schematic diagram of an electronic package 2 of the present invention. Figure 2 and Figure 2' As shown, the electronic package 2 comprises: a multi-chip package 2a (which comprises a supporting structure 20 , a plurality of electronic components 21 , 21 ′ and a packaging layer 22 ), a stress buffer layer 24 , a heat dissipation material 25 and a heat dissipation element 23 .

[0040] The supporting structure 20 is in the form of a carrier, which is, for example, a package substrate with a core layer, a coreless circuit structure, a Through Silicon Interposer (TSI) with conductive Through-Silicon Via (TSV), or other board types.

[0041] In this embodiment, the carrier structure 20 is a circuit structure without a core layer, which includes at least one insulating layer 200 and at least one circuit layer 201 combined with the insulating layer 200, such as at least one fan-out redistribution layer (RDL). It should be understood that the carrier structure 20 can also be other chip-carrying plates, such as lead frames, wafers, or other plates with metal routing, etc., and is not limited to the above.

[0042] In addition, the supporting structure 20 has a first side 20a and a second side 20b opposite to each other, and a plurality of conductors 26 may be formed on the second side 20b, so that the electronic package 2 may be connected to a package substrate 3 via the conductors 26, and the conductors 26 may be coated by the primer 260. Alternatively, the electronic package 2 may be connected to an electronic device such as a circuit board (not shown) via the conductors 26. For example, the conductor 26 may be a metal column such as a copper column, a metal bump coated with an insulating block, a solder ball, a solder ball with a core copper ball, or other conductive structures.

[0043] In addition, the carrier board manufacturing method of the supporting structure 20 is various. For example, the circuit layer 201 can be manufactured by wafer manufacturing method, and silicon nitride or silicon oxide is formed by chemical vapor deposition (CVD) as the insulating layer 200; or the circuit layer 201 can be formed by general non-wafer manufacturing method, that is, a low-cost polymer dielectric material is used as the insulating layer 200, such as polyimide (PI), polybenzoxazole (PBO), prepreg (PP), molding compound, photosensitive dielectric layer or other materials are formed by coating.

[0044] The multiple electronic components 21, 21' are separately arranged on the first side 20a of the supporting structure 20, and the electronic components 21, 21' are active components, passive components or a combination thereof, wherein the active components are, for example, semiconductor chips, and the passive components are, for example, resistors, capacitors and inductors.

[0045] In the present embodiment, the electronic components 21, 21' are semiconductor chips having an active surface 21a and an inactive surface 21b opposite to each other, and the electrode pad 210 of the active surface 21a is disposed on the circuit layer 201 of the first side 20a of the carrier structure 20 in a flip chip manner through a plurality of conductive bumps 211 such as solder materials, metal pillars or other materials and electrically connected to the circuit layer 201, and the conductive bumps 211 are covered with a coating layer 212 such as a primer; or, the electronic components 21, 21' can be electrically connected to the circuit layer 201 of the carrier structure 20 in a wire bonding manner through a plurality of welding wires (not shown); or, the electronic components 21, 21' can directly contact the circuit layer 201 of the carrier structure 20. Therefore, the required type and number of electronic components can be placed on the carrier structure 20 to enhance its electrical function, and there are many ways for the electronic components 21, 21' to be electrically connected to the carrier structure 20, which are not limited to the above.

[0046] In addition, the coating layer 212 is also formed between the electronic components 21 , 21 ′, such as extending along the side surfaces 21 c of the electronic components 21 , 21 ′, and the inactive surface 21 b of the electronic components 21 , 21 ′ is flush with the upper surface 212 a of the coating layer 212 .

[0047] The packaging layer 22 is formed on the first side 20 a of the supporting structure 20 to cover the electronic components 21 , 21 ′ and the covering layer 212 .

[0048] In this embodiment, the packaging layer 22 has a first surface 22a and a second surface 22b opposite to each other, and the first surface 22a is combined with the first side 20a of the supporting structure 20, and the inactive surface 21b of the electronic component 21 is flush with the second surface 22b of the packaging layer 22 so that the electronic components 21 are exposed on the second surface 22b of the packaging layer 22.

[0049] In addition, the material forming the packaging layer 22 is an insulating material, such as a packaging colloid or packaging material of polyimide (PI) or epoxy resin, which can be formed by molding, lamination or coating.

[0050] The stress buffer layer 24 is disposed on the multi-chip package 2 a to contact the plurality of electronic components 21 , 21 ′ and the encapsulation layer 212 .

[0051] In this embodiment, the stress buffer layer 24 is a metal layer, such as copper, and is formed on the inactive surface 21b of each of the electronic components 21, 21', the upper surface 212a of the coating layer 212 and the second surface 22b of the packaging layer 22 by sputtering or other methods to contact the multiple electronic components 21, 21', the coating layer 212 and the packaging layer 22.

[0052] In addition, forming the stress buffer layer 24 by sputtering can not only reduce the manufacturing cost, but also simplify the manufacturing process, thus facilitating mass production.

[0053] The heat dissipation material 25 is disposed on the stress buffer layer 24 , and the heat dissipation material 25 is a thermal interface material (TIM), such as a high thermal conductivity metal adhesive.

[0054] The heat sink 23 is coupled to the stress buffer layer 24 via the heat sink material 25 , so that the heat sink 23 , the heat sink material 25 and the stress buffer layer 24 serve as a heat dissipation mechanism for the electronic components 21 , 21 ′.

[0055] In this embodiment, the heat sink 23 has a heat sink 230 and a plurality of support legs 231 disposed on the lower side of the heat sink 230. The heat sink 230 is a heat sink type and contacts the heat sink material 25 at the lower side, and the support legs 231 are combined on the package substrate 3 or the first side 20a of the supporting structure 20 via an adhesive layer 27. It should be understood that there are many types of heat sinks 23, such as a sheet type (without support legs 231), and it is not limited to the above.

[0056] In addition, the stress buffer layer 24 is disposed between the plurality of electronic components 21 , 21 ′ and the heat sink 23 .

[0057] In addition, in the subsequent manufacturing process, a plurality of conductive elements 30 may be implanted on the lower side of the package substrate 3, so as to connect an electronic device such as a circuit board (not shown) via the conductive elements 30. For example, the conductive element 30 may be a metal pillar such as a copper pillar, a metal bump coated with an insulating block, a solder ball, a solder ball with a core copper ball, or other conductive structures.

[0058] In summary, the electronic package 2 of the present invention is mainly arranged on the multi-chip package 2a through the stress buffer layer 24 to connect the non-active surface 21b of each electronic component 21, 21' and the upper surface 212a of the coating layer 212, so that the stress is evenly dispersed in the stress buffer layer 24 instead of being concentrated in a specific area. Therefore, compared with the prior art, the electronic package 2 of the present invention can effectively avoid the structural stress from being concentrated in the corners of the electronic components 21, 21' when the overall planar packaging area of ​​the supporting structure 20 is larger, thereby avoiding the electronic components 21, 21' or the coating layer 212 from being broken, resulting in poor reliability and low process yield.

[0059] The above embodiments are only used to illustrate the principles and effects of the present invention, and are not used to limit the present invention. Any person skilled in the art may modify the above embodiments without violating the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as listed in the claims.

Claims

1. An electronic package, characterized in that: include: A multi-chip package, comprising a plurality of electronic components and a coating layer combining the plurality of electronic components; as well as The stress buffer layer is arranged on the multi-chip package to contact the plurality of electronic components and the coating layer so that the stress is evenly dispersed in the stress buffer layer.

2. The electronic package according to claim 1, characterized in that: At least two of the plurality of electronic components are arranged separately from each other.

3. The electronic package according to claim 1, characterized in that: The coating layer is formed between any two of the electronic components.

4. The electronic package according to claim 1, characterized in that: The coating layer is a primer.

5. The electronic package according to claim 1, characterized in that: The multi-chip package also includes a supporting structure for supporting and electrically connecting the plurality of electronic components, and the coating layer is formed on the supporting structure.

6. The electronic package according to claim 5, characterized in that: The bearing structure is a line structure without a core layer.

7. The electronic package according to claim 1, characterized in that: The multi-chip package also includes a packaging layer that covers the multiple electronic components and the covering layer.

8. The electronic package according to claim 7, characterized in that: The stress buffer layer also contacts the packaging layer.

9. The electronic package according to claim 7, characterized in that: A surface of the electronic component is flush with the upper surface of the packaging layer.

10. The electronic package according to claim 1, characterized in that The electronic package also includes a heat sink coupled to the plurality of electronic components.

11. The electronic package according to claim 10, characterized in that: The heat sink is combined with the stress buffer layer via a heat dissipation material.

12. The electronic package according to claim 10, characterized in that: The stress buffer layer is arranged between the plurality of electronic components and the heat sink.

13. The electronic package according to claim 1, characterized in that The stress buffer layer is a metal layer.

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