Vector processor with vector-first and multi-channel configuration

Abstract

The present disclosure provides a vector processor with a vector first and multi-channel configuration. A vector operation for a vector processor may include a single vector or multiple vectors as input. Multiple channels for the input may be used to accelerate the operation in parallel. Furthermore, the vector first configuration may enhance the multiple channels to perform the operation in parallel by reducing the number of elements accessed in the channels.

Description

[0001] Related Applications

[0002] This application claims priority to U.S. Patent Application No. 16 / 356,146, filed on March 18, 2019, and entitled “Vector Processor with Vector First and Multiple Lane Configuration,” the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] Generally, at least some embodiments disclosed herein relate to vector processors.Furthermore, at least some embodiments disclosed herein relate to vector processors having a multi-channel configuration and vector processors having a vector first configuration. Background Art

[0004] A vector processor may be or include a central processing unit (CPU) that implements an instruction set containing instructions that operate on data arrays commonly referred to as vectors. This is different from a scalar processor, in which instructions operate on a single data item. Compared to a scalar processor, a vector processor can significantly improve the performance of certain workloads, particularly numerical simulations and similar tasks. Vector processors appeared in the early 1970s, and most of the supercomputing designs were in the 1970s to the 1990s. The rapid decline in the price-performance ratio of more conventional microprocessor designs (such as scalar processor designs) has led to less development and manufacture of vector processors.

[0005] Typically, conventional CPUs (e.g., scalar-based CPUs) are able to manipulate at most a few pieces of data at a time. For example, such CPUs have instructions that essentially provide to add A to B and store the result in C. The data for A, B, and C are typically pointed out by passing an address to the memory location where the data is held. It takes some time to decode the address and fetch the data from memory, during which time the CPU may be idle waiting for the requested data to appear.

[0006] To reduce the amount of time consumed by these steps, more modern CPUs use a technique called instruction pipelining where instructions are passed through several subunits in sequence. The first subunit reads the addresses and decodes them, the next subunit extracts the values ​​at those addresses, and the next subunit performs the math formula itself. With pipelining, the CPU begins decoding the next instruction even before the first instruction leaves the CPU, similar to a production assembly line. In this way, the address decoder and the other mentioned components are used simultaneously and continuously. Due to the pipelining, any instruction takes the same amount of time to complete.

[0007] Vector processors improve pipelining by allowing such processors to also pipeline the data itself rather than just pipeline instructions. Thus, a vector processor reads a single instruction from memory rather than continually having to decode the instruction and then fetch the data needed to complete the instruction. This allows for reduced decode time and reduced power consumption (e.g., decoding once rather than multiple times with a vector processor). BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments of the present disclosure.

[0009] Figure 1 Example components of an example computing device 100 are shown, in accordance with some embodiments of the present disclosure.

[0010] Figure 2 Example components of an example computing device 200 are shown, in accordance with some embodiments of the present disclosure.

[0011] Figure 3 An example vector first system 300 having two channels is shown, according to some embodiments of the present disclosure.

[0012] Figure 4 and 5 Example operations of method 400 according to some embodiments of the present disclosure are shown.

[0013] Figure 6 An example vector first system 500 having four channels is shown, according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0014] Generally, at least some embodiments disclosed herein relate to vector processors. Moreover, at least some embodiments disclosed herein relate to vector processors with multi-channel configurations and vector processors with vector first configurations. Embodiments disclosed herein provide specific technical solutions for at least the technical problems mentioned in the background technology section and other parts of this application and other technical problems not described herein but recognized by those skilled in the art. At least some embodiments disclosed herein include vector processors with vector first and multi-channel configurations. Vector operations for vector processors may include a single vector or multiple vectors as inputs. Multiple channels for input may be used to accelerate operations in parallel. Moreover, the vector first configuration may enhance multiple channels to perform operations in parallel by reducing the number of elements accessed in the channels. As mentioned, multiple channels for input may be used to accelerate operations in parallel. For example, the operation may be vector A and B addition, or element-by-element multiplication of vectors A and B, or any other type of operation to two or more vectors.

[0015] Each vector of the operation can be divided into multiple channels (k channels) of parallel operation. For example, consider the multiplication of A(i)×B(i) (i=0, 1, 2, ..., (n-1)*k). This can be done in k parallel channels: for parallel channels j=0, 1, 2, ..., k-1, A(m)×B(m) (m=k×i+j, and i=0, 1, 2, ..., n-1). In general, the multiplication "X" can be replaced by another operation (e.g., addition, subtraction, bitwise "or", etc.). The result of the operation on two or more vectors can be a scalar or a vector.

[0016] Moreover, as mentioned, the vector first configuration can enhance multiple channels to perform operations in parallel by reducing the number of elements accessed in the channels. At least some embodiments disclosed herein include components that can use vector registers with multiple channels to implement the vector first configuration, which can reduce the number of elements accessed in the channels to perform operations in parallel more efficiently. For example, one of the components can be a vector first register. The vector first register can be used to indicate whether the first element for the calculation involving the vector can be found. In the absence of the vector first register, the calculation always starts with element 0 of the vector contained in the vector data register. And, if the calculation always starts with element 0 of the vector contained in the vector data register, the entire operand must always be reloaded. However, for vector first processing, only new operands need to be loaded.

[0017] For example, consider the vector A(i) where i = 0, 1, 2, …, n-1. If the vector first register stores m, the elements used for calculation are A(i) where i = m, m+1, …. Problems arise in cases where the vector is split into multiple channels. If a total of k channels are used, channel j has the elements A(k×i + j) of vector A where i = 0, 1, …, and j is 0, 1, …, k-1. To start an operation on the element (k×a + b) where b is non-zero, the problem is that without using the vector first register, the first element will not be in channel zero. Instead, the first element will be in channel b (e.g., rather than in channel zero). To start from the element k×a + b, the elements used in channel j are A(k×i + j) where i = a+1, 1, … and j > b; and for j <= b, the elements used in channel j are A(k×i + j) where i = a, 1, …. The multiplexer of the system can be configured to shift the contents of the channels to channel zero based on b. The multiplexer can be replaced with a shifter that shifts the entire operand from one channel to another. The shift and / or multiplexing can be configured such that the first element (k×a + b) is placed in channel zero. Specifically, shift A(k×i + j) of channel j to channel j-b (for i = a, 1, … and j ≥ b) and channel k + j - b (for i = a+1, 1, … and j < b). With this shift, the operation can start on input element a of channel b up to k-1, and on input element a+1 of channel 0 up to b-1. To start on the element k×a + b, b controls the channel shift; and a / a+1 controls the selection of the first element in the channel. In the two-channel case, this can be simplified to a shift and / or switch based on whether k×a + b is odd or even. Instances of this system can be used with any arrangement of two channels, four channels, sixteen channels, and channels with a power of two. However, the complexity of the hardware changes exponentially with the increase in the number of channels.

[0018] Figure 11. An exemplary component of an exemplary computing device 100 according to some embodiments of the present disclosure is shown. As shown, the device 100 may be communicatively coupled to one or more networks 112. The device 100 includes a vector processor 102 according to some embodiments of the present disclosure. The device 100 also includes at least a bus 104, a main memory 106, a data storage system 108, and a network interface 110. The bus 104 communicatively couples the vector processor 102, the main memory 106, the data storage system 108, and the network interface 110. The device 100 includes a computer system that includes at least a vector processor 102, a main memory 106 (e.g., a read-only memory (ROM), a flash memory, a dynamic random access memory (DRAM) (such as a synchronous DRAM (SDRAM) or a Rambus DRAM (RDRAM)), a static random access memory (SRAM), etc.), and a data storage system 108 that communicate with each other via the bus 104 (which may include multiple buses).

[0019] In other words, Figure 1 1 is a block diagram of an exemplary apparatus 100 having a computer system in which embodiments of the present disclosure may operate. In some embodiments, the computer system may include a set of instructions for causing the machine, when executed, to perform any one or more of the methodologies discussed herein. In such embodiments, the machine may be connected (e.g., via a network interface 110) to other machines in a LAN, an intranet, an extranet, and / or the Internet (e.g., network 112). The machine may operate as a server or a client machine in a client-server network environment, may act as a peer computer in a peer-to-peer (or distributed) network environment (such as the peer-to-peer network described herein), or may act as a server or a client computer in a cloud computing infrastructure or environment.

[0020] The vector processor 102 represents one or more vector processors according to some embodiments of the present disclosure. The vector processor 102 may include a microprocessor, a central processing unit, etc. More specifically, the vector processor 102 may include a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets or a processor implementing a combination of instruction sets, as long as the processor uses: vector instructions, vector registers, vector first and multi-channel configurations. The vector processor 102 may also be one or more special processing devices, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a graphics processing unit (GPU), a network processor, etc. The vector processor 102 may be configured to execute instructions for performing the operations and steps discussed herein. The vector processor 102 may also include a network interface device such as a network interface 110 to communicate through one or more communication networks (such as a network 112).

[0021] The data storage system 108 may include a machine-readable storage medium (also referred to as a computer-readable medium) on which one or more instruction sets or software are stored, and the data storage system may embody at least some aspects of one or more methods or functions described herein. The data storage system 108 may include a non-volatile storage device. The instruction may also reside completely or at least partially in the main memory 106 and / or in the vector processor 102 during the execution of the instruction by the computer system, and the main memory 106 and the vector processor 102 may also constitute a machine-readable storage medium. Although the memory, vector processor, and data storage components are shown as being each a single component in the exemplary implementation, each component should be considered to include a single component or multiple components that can store instructions and perform their corresponding operations. The term "machine-readable storage medium" should also be considered to include any medium that can store or encode instruction sets for machine execution and cause the machine to perform any one or more of the methods of the present disclosure. Therefore, the term "machine-readable storage medium" should be understood to include, but not limited to, solid-state memory, optical media, and magnetic media.

[0022] Figure 2 2 shows example components of an example computing device 200 according to some embodiments of the present disclosure. As shown, the computing device 200 includes a vector processor 102 and a bus 104 and a main memory 106 (see, for example, FIG. Figure 1 ). The computing device 200 may also be or include the computing device 100.

[0023] like Figure 2As shown, the vector processor 102 includes a vector register 202, a scalar register 204, a bus 206, an arithmetic logic unit 208 (ALU 208), and a vector load storage unit 210. Other embodiments of the computing device 200 may include a scalar register 204 that is external to the vector processor 102 or in a unit of the vector processor that is separate from the unit in the vector processor having the vector register 202. The bus 206 communicatively couples the vector register 202, the scalar register 204, the arithmetic logic unit (ALU) 208, and the vector load storage unit 210, and such components may communicate with each other via the bus 206 (which may include multiple buses). The vector register 202 includes multiple vector registers. And, the ALU 208 includes multiple ALUs, for example, arithmetic logic unit (ALU) 0, ALU 1, and ALU N.

[0024] Vector processor 102 includes vector first and multi-channel configuration. Vector processor 102 can be or include one or more central processing units (CPUs), and this CPU implements the instruction of operating on the one-dimensional data array called vector. Vector register 202 in vector processor 102 can include vector register with multiple channel configuration. Scalar register 204 includes scalar register, and this scalar register is the vector first configuration of vector register with multiple channel configuration and provides index and control value. Scalar register can also provide the numerical value used by vector instruction. For example, the vector provided by vector register can be multiplied by the scalar provided by scalar register. Therefore, at least some vector registers 202 can have vector first and multi-channel configuration. Each of these registers can be connected to the corresponding ALU in ALU 208. ALU in ALU 208 can include the combinational digital electronic circuit that performs arithmetic and bitwise operation to integer binary number. In vector processor 102, ALU in ALU208 can be connected to the vector register with vector first and multi-channel configuration.

[0025] Furthermore, scalar registers 204 may include programmable scalar registers. Programmable scalar registers may be used so that a vector provided by a vector register (e.g., one of vector registers 202) may be operated on by a scalar provided by and programmed into one of the programmable scalar registers. For example, one of the operations may include multiplying a vector by a scalar value (e.g., vector A(i)×scalar p).

[0026] The vector load store unit 210 contains circuitry for executing load and store instructions, generating addresses for load and store operations, and loading data from memory or storing data from registers of the vector processor 102 back to memory. The vector load store unit 210 can perform many of the operations described herein, including Figures 4 to 5 The operations of method 400 are as follows.

[0027] The vector registers in register 202 may include vector first and multi-channel configurations. Examples of vector first and multi-channel configurations are explained below. Figures 3 to 6 Examples of vector first and multi-channel configurations are explained in more detail in.

[0028] Each of the computing devices described herein may be a machine capable of executing (sequentially or otherwise) a set of instructions that specifies actions to be taken by the machine. Figure 1 and 2 Each of the computing devices shown illustrates a single machine, but the term "machine" may also be considered to include any collection of machines that individually or jointly execute an instruction set (or multiple instruction sets) to perform any one or more of the methods or operations discussed herein. Furthermore, each of the computing devices shown may each include at least a bus and / or motherboard, one or more controllers (such as one or more CPUs), a main memory that may include a temporary data storage device, at least one type of network interface, a storage system that may include a permanent data storage device, and / or any combination thereof.

[0029] Figure 3 An exemplary vector first system 300 having two channels is shown in accordance with some embodiments of the present disclosure. The vector first system 300 may be part of a vector processor 102 (eg, see Figure 1 Or 2). Vector first system 300 includes a plurality of channels 302 of first vector registers, the first vector registers including vector register channels 301 and 303. In other words, system 300 includes first vector register channel 301 and second vector register channel 303 for two channels of first vector registers (e.g., one of vector registers 202). Although system 300 shows components of the first vector register, the system interacts directly with components of the second vector register. The first vector register and the second vector register each provide corresponding inputs for ALU 304a and ALU 304b of system 300.

[0030] Typically, multiple channels for input can be used to accelerate operations in parallel. As shown, each channel has a corresponding ALU (e.g., ALU 304a and 304b). For example, the operation can be the addition of a first vector and a second vector (i.e., vectors A and B), or the element-by-element multiplication of the vectors, or any other type of operation on two vectors. Each vector of the operation can be divided into multiple channels (k channels) for parallel operations. For example, consider the multiplication of A(i)×B(i) (i=0, 1, 2, ..., (n-1)*k). This can be done in k parallel channels: for parallel channels j=0, 1, 2, ..., k-1, A(m)×B(m) (m=k×i+j, and i=0, 1, 2, ..., n-1). Typically, multiplication "X" can be replaced by another operation (e.g., addition, subtraction, bitwise "or", etc.). The result of parallel processing of operations of parallel lane ALUs (eg, ALUs 304a and 304b) on two or more vectors with two lanes (eg, outputs 314a and 314b) may be a scalar or a vector.

[0031] Moreover, in general, the vector first configuration can enhance multiple channels to perform operations in parallel by reducing the number of elements accessed in the channel. Figures 3 to 6 As shown, the components of system 300 or 500 can implement a vector first configuration (i.e., a vector first and multi-channel configuration) with vector registers having multiple channels, which can reduce the number of elements accessed in the channels to more efficiently perform operations in parallel. For example, one of the components can be a vector first register (e.g., a register storing VFR values ​​320 or 520). The vector first register can be used to indicate whether the first element for a calculation involving a vector can be found. In the absence of a vector first register, the calculation always starts from element 0 of the vector.

[0032] The vector first configuration can enhance multiple channels to perform operations in parallel by reducing the number of elements accessed in the channels. At least some embodiments disclosed herein include components that can use vector registers with multiple channels to implement the vector first configuration, which can reduce the number of elements accessed in the channels to perform operations in parallel more efficiently. For example, one of the components can be a vector first register. The vector first register can be used to indicate whether the first element for the calculation involving the vector can be found. In the absence of the vector first register, the calculation always starts with element 0 of the vector contained in the vector data register. And, if the calculation always starts with element 0 of the vector contained in the vector data register, the entire operand must always be reloaded. However, for vector first processing, only new operands need to be loaded.

[0033] For example, consider vector A(i) (i = 0, 1, 2, …, n - 1). If the vector first register stores m, the elements used for calculation are A(i) (i = m, m + 1, …). Problems occur when the vector is divided into multiple channels. If a total of k channels are used, channel j has elements A(k×i + j) of vector A (i = 0, 1, …), where j is 0, 1, …, k - 1. To start an operation on the element (k×a + b) where b is non - zero, the problem is that without using the vector first register, the first element will not be in channel zero. Instead, the first element will be in channel b. To start from element k×a + b, the elements used in channel j are A(k×i + j) (i = a + 1, 1, … and j > b); and for j <= b, the elements used in channel j are A(k×i + j) (i = a, 1, …).

[0034] One or more multiplexers of the system (e.g., see multiplexers 309 and 311) can be configured to shift the contents of the channels to channel zero according to b. The multiplexers can be replaced with one or more shifters. The shift and / or multiplexing can be configured such that the first element (k×a + b) is placed in channel zero. Specifically, shift A(k×i + j) of channel j to channel j - b (for i = a, 1, … and j ≥ b) and channel k + j - b (for i = a + 1, 1, … and j < b). With this shift, the operation can start on input element a of channel b to k - 1, and on input element a + 1 of channel 0 to b - 1. To start on element k X a + b, b controls the channel shift; and a / a + 1 controls the selection of the first element in the channel. In the two - channel case, this can be simplified to shift and / or switching based on whether k X a + b is odd or even. Instances of the system can be used with any arrangement of two channels, four channels, sixteen channels, and channels that are powers of two. However, the complexity of the hardware changes exponentially with the increase in the number of channels. Figure 3 A two - channel exemplary arrangement of components is shown. And, Figure 6 A four - channel exemplary arrangement is shown.

[0035] Reference Figure 3 In the two - channel example of, the first vector register channel 301 contains vector elements (VE) 305a, 305b, 305c, and 305d, and the second vector register channel 303 contains vector elements (VE) 307a, 307b, 307c, and 307d. Regarding Figure 4 and 5 shown in method 400 more details are described about the use of the elements of the vector register.

[0036] System 300 also includes ALU 304a (ALU for Lane_0) and ALU 304b (ALU for Lane_1) for at least a first vector register and a second vector register. In some embodiments, ALU 304a and 304b may be one of ALU 208, and the first vector register and the second vector register may be two of vector registers 202. Except for the output of the second vector register as a channel input of the ALU, components of the second vector register are not shown, for example, see 308b and 312b.

[0037] ALU 304a is shown as including a first channel input 308a for output transferred from the first vector register channel 301 or the second vector register channel 303 of the first vector register. ALU 304a is also shown as including a first channel input 308b for output transferred from the first vector register channel or the second vector register channel of the second vector register.

[0038] ALU 304b is shown as including a second channel input 312a of the output transferred from the first vector register channel 301 or the second vector register channel 303 of the first vector register. ALU 304b is also shown as including a second channel input 312b of the output transferred from the first vector register channel or the second vector register channel of the second vector register.

[0039] In some embodiments, the ALU of the system (e.g., ALU 304a or 304b) may include an ALU output based on at least one function of the ALU and an input from the same channel output of the first vector register and the second vector register. For example, ALU output 314a may be based on at least one function of ALU 304a and first channel inputs 308a and 308b of the first vector register and the second vector register. Also, ALU output 314b may be based on at least one function of ALU 304b and second channel inputs 312a and 312b of the first vector register and the second vector register. The function of each of ALU 304a and 304b may be the same function for each ALU.

[0040] The system 300 also includes a first 2:1 multiplexer 309 configured to receive the output from the first vector register channel 301 and the output from the second vector register channel 303 as inputs (e.g., inputs 306a and 306b). The first 2:1 multiplexer 309 can also be configured to receive the vector first register value (e.g., VFR value 320) as a select input (e.g., select input 324). As shown, the select input 324 for the first 2:1 multiplexer 309 is received from the output of the scalar register (e.g., the register of the VFR value 320 in the scalar register 313 in the first vector register). The first scalar register can be Figure 2 The first 2:1 multiplexer 309 may also be configured to select an output from the first vector register channel 301 or an output from the second vector register channel 303 based on a select input 324. The first 2:1 multiplexer 309 may also be configured to transmit the selected output to the first channel input 308a of the ALU 304a for the first register.

[0041] The system 300 also includes a second 2:1 multiplexer 311 configured to receive the output from the first vector register channel 301 and the output from the second vector register channel 303 as inputs (e.g., inputs 310a and 310b). The second 2:1 multiplexer 311 can also be configured to receive a VFR value (e.g., VFR value 320) as a select input (e.g., select input 324). As shown, the select input 324 for the second 2:1 multiplexer 311 is received from the output of a scalar register (e.g., a register for VFR value 320 in scalar register 313). The scalar register can be Figure 2 The second 2:1 multiplexer 311 can also be configured to select an output from the first vector register channel 301 or an output from the second vector register channel 303 based on a select input 324. The second 2:1 multiplexer 311 can also be configured to transmit the selected output to the second channel input 312a of the ALU 304b for the first register.

[0042] The scalar registers 313 may also include a VAR register configured to provide element address values ​​(EA values) for the first vector register channel 301 and the second vector register channel 303 by corresponding indexes of the first vector register (e.g., VAR register 322), for example, see Figure 3 and 6, which provide access to the corresponding elements when such values ​​match input 326. In other words, input 326 can be considered as an input having or associated with an EA value.

[0043] Furthermore, scalar registers 313 may include programmable scalar registers. Programmable scalar registers may be used so that a vector provided by a vector register (e.g., a vector register having channels 301 and 303) may be operated on by a scalar provided by and programmed into one of the programmable scalar registers. For example, one of the operations may include multiplying a vector by a scalar value (e.g., vector A(i)×scalar p).

[0044] The VFR value and the EA value can each be stored in a scalar register such as Figure 2 scalar in the scalar register 204 shown in FIG. Figure 4 and 5 The method 400 depicted in FIG. 4 describes the VFR value and the EA value in more detail. The VFR value and the EA value may be used to determine an initial address for accessing a corresponding vector channel (eg, see Figure 3 The vector elements 305a and 307a depicted in Figure 6 Input 326 shows how a component of the vector processor (such as a vector load store unit) selects an element in a vector register lane, where the input for selecting an element comes from the output value of VAR register 322.

[0045] In some embodiments, a vector processor (e.g., Figure 1 and 2 The vector processor 102 shown may include a vector load store unit (e.g., Figure 2 2) and a vector register (e.g., vector register 202). At least one of the registers may include a first vector register channel for two channels of vector registers (e.g., Figure 3 The first vector register channel 301 shown) and the second vector register channel (eg, Figure 3 3. The vector processor may further include an ALU (e.g., ALU 208). The ALU may include an ALU for two or more vector registers (e.g., ALU 304a and 304b).

[0046] The ALU of the vector register may include a first channel input (e.g., input 308a) for output transmitted from the first vector register channel or the second vector register channel of the first vector register. Another ALU of the vector register may include a second channel input (e.g., input 312a) for output transmitted from the first vector register channel or the second vector register channel of the first vector register. The ALU may also include an ALU output based on at least one function of the ALU and the first channel input of the first vector register and the second vector register, for example, see ALU output 314a.

[0047] The ALU of the vector register may include a first channel input (e.g., input 308b) for output transmitted from the first vector register channel or the second vector register channel of the second vector register. The ALU of the vector register may also include a second channel input (e.g., input 312b) for output transmitted from the first vector register channel or the second vector register channel of the second vector register. The ALU may also include an ALU output, which is based on at least one function of the ALU and the second channel input of the first vector register and the second vector register, for example, see ALU output 314b.

[0048] In such embodiments, the bus (e.g., Figure 2 The bus 206 depicted in FIG. 2 may be configured to communicatively couple the vector load store unit, the vector registers, and the arithmetic logic unit.

[0049] The bus may include a first 2:1 multiplexer (e.g., 2:1 multiplexer 309) configured to receive an output from a first vector register channel and an output from a second vector register channel as inputs (e.g., inputs 306a and 306b). The first 2:1 multiplexer may also be configured to receive a vector first register value (VFR value) as a select input (e.g., select input 324). The select input of the first 2:1 multiplexer may be received from an output of a first scalar register (e.g., see scalar register 313, which may be one of the scalar registers in scalar registers 204). The first 2:1 multiplexer may also be configured to select an output from the first vector register channel or an output from the second vector register channel based on the select input, and transmit the selected output to a first channel input (e.g., input 308a) of ALU304a.

[0050] The bus may include a second 2:1 multiplexer (e.g., 2:1 multiplexer 311) configured to receive an output from the first vector register channel and an output from the second vector register channel as inputs (e.g., inputs 310a and 310b). The second 2:1 multiplexer may also be configured to receive the VFR value as a select input (e.g., select input 324). The select input of the second 2:1 multiplexer may be received from an output of a scalar register (e.g., see scalar register 313, which may be one of the scalar registers in scalar registers 204). The second 2:1 multiplexer may also be configured to select an output from the first vector register channel or an output from the second vector register channel based on the select input, and transmit the selected output to a second channel input (e.g., see input 312a) of ALU 304b.

[0051] In some embodiments, a processor may include a vector load store unit, at least one vector register having a first vector register channel and a second vector register channel, at least one programmable scalar register, and a first ALU and a second ALU connected to the vector register and the programmable scalar register so that values ​​provided by the channels of the vector register can be operated on by values ​​provided through the programmable scalar register.

[0052] Furthermore, in such embodiments, the first vector processor may include a vector first register (e.g., VFR) configured to provide a VFR value (e.g., VFR value 320) to the first and second 2:1 multiplexers for use as a select input of the multiplexers. The second vector register ( Figure 3 ) may include a VFR configured to also provide a VFR value to a multiplexer for a second vector register for use as a select input.

[0053] Furthermore, in such embodiments, the vector processor may include an index register (e.g., VAR register 322) for a first vector register channel, the index register being configured to provide an element address value (EA value)—see, e.g., input 326. Furthermore, an index register may also be used for a second vector register channel, the index register being configured to provide an EA value, see, e.g., input 326.

[0054] In such embodiments, the vector processor may further include a vector load storage unit, which may be configured to determine a first initial address for accessing a first vector register channel according to a VFR value and an EA value. The vector load storage unit may also be configured to determine a second initial address for accessing a second vector register channel according to a VFR value and a unit address value. In such embodiments, the ALU may be configured to access the first vector register channel according to the first initial address, and to access the second vector register channel according to the second initial address.

[0055] In such embodiments, the vector load store unit may be configured to increment the EA value, and determine a first next address for accessing the first vector register channel based on the VFR value and the incremented element address value, and determine a second next address for accessing the second vector register channel based on the VFR value and the incremented element address value. The ALU may be configured to access the first vector register channel based on the first next address, and access the second vector register channel based on the second next address.

[0056] Moreover, in such instances, the vector load store unit can be configured to repeatedly increment the first element address value and the second element address value. Thus, the vector load store unit can be configured to change the VFR value when the first element address value is equal to the number of elements in the first vector register lane (e.g., see input 326, which can include an EA value, and the number of vector elements 305a, 305b, 305c, and 305d), and change the VFR value when the second element address value is equal to the number of elements in the second vector register lane (e.g., see input 326, which can include an EA value, and the number of vector elements 307a, 307b, 307c, and 307d).

[0057] In such instances, the vector load storage unit may also be configured to reset the first element address value in the first index and reset the second element address value in the second index. The vector load storage unit may also be configured to determine different first initial addresses for accessing the second vector register channel according to the changed VFR value and the reset unit address value. And, the vector load storage unit may also be configured to determine different second initial addresses for accessing the first vector register channel according to the changed VFR value and the reset unit address value. The ALU may be configured to access the second vector register channel according to different first initial addresses, and access the first vector register channel according to different second initial addresses.

[0058] Moreover, the vector load storage unit may be configured to increment the reset first element address value and the reset second element address value. The vector load storage unit may also be configured to determine different first next addresses for accessing the second vector register channel according to the changed VFR value and the incremented element address value. Moreover, the vector load storage unit may also be configured to determine different second next addresses for accessing the first vector register channel according to the changed VFR value and the incremented element address value. The ALU may be configured to access the second vector register channel according to different first next addresses, and to access the first vector register channel according to different second next addresses.

[0059] In some embodiments, the vector processor may include a third vector register channel and a fourth vector register channel for two additional channels of the first vector register, such that the register includes four channels (see, for example, Figure 6 ). The components used for and working with the third and fourth vector register channels may be similar to the components used for and working with the first and second vector register channels described herein. For example, see Figure 6 , depicting a vector first system with four channels instead of two.

[0060] Figure 4 and 5 400 according to some embodiments of the present disclosure. In some embodiments, a vector load storage unit such as the vector load storage unit 210 may perform or facilitate the operations of the method 400 alone or in combination with other components of the vector processor. In some embodiments, the determinations, increments, and changes described herein may be performed by the vector load storage unit of the vector processor according to instructions stored in the vector load storage unit. In some other embodiments, other components of the vector processor may perform or facilitate the operations of the method 400 and other operations described herein.

[0061] exist Figure 4 In the example, method 400 may be performed for a plurality of vector registers that provide inputs to a plurality of arithmetic logic units (ALUs). For example, method 400 may be performed for a first vector register and a second vector register that each provide inputs to an ALU of a vector processor. In this example, each of the first vector register and the second vector register may include a plurality of channels, and the number of channels of each register may be a power of two, and the number of ALUs that receive inputs from the registers is equal to the number of channels. For example, method 400 may be performed for a plurality of vector registers that each provide inputs to an ALU of a vector processor. Figure 3 and 6Each of the first vector register and the second vector register performs step 402 or any other steps of method 400.

[0062] exist Figure 4 In the method 400, at step 402, a vector first register (VFR) of a vector register having a plurality of channels providing input to an ALU of a vector processor provides a vector first register value (VFR value) for accessing the vector channel. The vector register is a register of a plurality of vector registers providing input to the ALU. The VFR may include, for example, a VFR for a dual channel system (e.g., Figure 3 320) or a VFR for a four-channel system (e.g., Figure 6 501c and 501d). Each of the vector register channels may be used for an ALU in a vector processor (e.g., ALUs 304a and 304b or 504a, 504b, 504c and 504d).

[0063] In other words, step 402 may include providing, by the VFR, a vector first register value (VFR value) for accessing the channel.

[0064] In some embodiments, the number of corresponding vector channels can be any power of two (e.g., two channels, four channels, sixteen channels, etc.). For example, the number of corresponding vector channels can be four (e.g., see Figure 6 , where the vector first system 500 is used for a multi-channel vector having four channels). Also, the number of corresponding vector channels may be two (see, for example, Figure 3 , where the vector first system 300 is used for a multi-channel vector with two channels).

[0065] The corresponding vector register lane and the data (including vector element values ​​and metadata) stored in the corresponding vector register lane may be contained in one of the vector registers (eg, see vector register 202 ).

[0066] At step 404, method 400 continues by passing through the vector register channel (e.g., respectively at Figure 3 and 6 The element address value (EA value) is provided by an index into the VAR register 322 or 522 depicted in FIG. 1 , for example, see Figure 3 and 6 The values ​​"0", "1", "2", and "3" under "EA" are shown in the vector register channel depicted in FIG. The VFR value and the EA value can each be stored in a scalar register (such as Figure 2 A scalar in a scalar register 204 as shown.

[0067] At step 406, method 400 continues by determining an initial address for accessing the vector channel based on the VFR value and the EA value. For examples of initial addresses, see Figure 3 The vector elements 305a and 307a depicted in Figure 6 . In these examples, input 326 or 526 illustrates how a component of a vector processor, such as a vector load store unit, uses elements in a vector register lane, where the input for selecting an element comes from the output value of VAR register 322 or 522.

[0068] At step 408, the method 400 continues with the ALU accessing the vector channel according to the initial address. Access to the corresponding vector channel according to the initial address may be performed via a multiplexer (such as Figure 3 2:1 multiplexers 309 and 311 depicted in the Figure 6 1 multiplexers 505a, 505b, 505c, and 505d) depicted in FIG. 1. As shown in these figures, each channel has a corresponding multiplexer. In some embodiments, the address is used to at least partially control the multiplexer and access to the vector channel. For example, the VFR value and address of each channel can be used in combination to control the input selection for the corresponding multiplexer and access to the vector channel.

[0069] At step 410 , the method 400 continues by incrementing the EA value (eg, changing VAR=0 to VAR=1).

[0070] At step 412, method 400 continues by determining the next address for accessing the vector channel based on the VFR value and the incremented EA value (eg, see Figure 3 The vector elements 305b and 307b depicted in Figure 6 The full addresses "Element_0_1" and "Element_1_1" in the vector register lane depicted in FIG.

[0071] At step 414, method 400 continues by the ALU (eg, via Figure 3 2:1 multiplexers 309 and 311 as depicted in FIG. 1 , or via Figure 64: 1 multiplexers 505a, 505b, 505c, and 505d) depicted in FIG. 4 access the vector channels according to the next address. As mentioned, the address can be used to at least partially control the multiplexers and access to the vector channels, for example, the VFR value and address of each channel can be used in combination to control the input selection for the corresponding multiplexer and access to the vector channels.

[0072] At step 416, method 400 continues to determine whether the EA value is equal to the number of elements in one of the vector channels. When the value of the EA value register is not equal to the number of elements in one of the vector channels, method 400 continues at step 410 to repeatedly increment the EA value (e.g., change VAR=1 to VAR=2, and so on).

[0073] Otherwise, in Figure 5 At step 422 of step 420 shown, the method includes changing the VFR value when the EA value is equal to the number of elements in one of the vector channels.

[0074] For example, if the EA value of the first vector register channel 301 is "3" (which references the fourth element), the EA value is representatively equal to four elements in the channel; and therefore, the VFR value of the first vector register channel 301 is changed at step 422. For this example, in the case where there are two channels, a value of "0" for the VFR of the channel can indicate that the ALU will access elements from the channel via its corresponding multiplexer, while a value of "1" for the VFR of the channel can indicate that the ALU will access elements from the other channel via its corresponding multiplexer. This example combination of operations and parameters can provide vector first processing in multiple channels.

[0075] At step 424, method 400 continues at Figure 5 In sub-step 420 of , the EA value is reset in the index. For example, the reset may include changing the EA value of a channel from "3" to "0" when there are four elements in a channel.

[0076] At step 426, method 400 continues by determining a different initial address for accessing the vector channel based on the changed VFR value and the reset EA value. Figure 3 and 6 (which can be used to access the initial element of the first of the two channels through the ALU input of the second of the two channels when the VFR value has changed), and see Figure 3 and 6 The full address "Element_1_0" in (when the VFR value has changed, it can be used to access the original element of the second channel through the ALU input of the first channel).

[0077] At step 428, method 400 continues by the ALU (eg, via Figure 3 2:1 multiplexers 309 and 311 as depicted in FIG. 1 , or via Figure 6 4:1 multiplexers 505a, 505b, 505c, and 505d) depicted in FIG. 4 access the vector channels according to different initial addresses. In some embodiments, the address is used to at least partially control the multiplexers and access to the vector channels. For example, the VFR value and address of each channel can be used in combination to control the input selection for the corresponding multiplexer and access to the vector channels.

[0078] At step 430 , the method 400 continues to increment the reset EA value (eg, changing VAR=0 to VAR=1, changing VAR=1 to VAR=2, and so on).

[0079] At step 432, method 400 continues to determine a different next address for accessing the corresponding vector lane based on the changed VFR value and the incremented EA value. For example, see full address "Element_0_1" (which can be used to access the next element of the first of the two lanes through the ALU input of the second of the two lanes when the VFR value has changed), and see full address "Element_1_1" (which can be used to access the next element of the second lane through the ALU input of the first lane when the VFR value has changed).

[0080] At step 434, method 400 continues by the ALU (eg, via Figure 3 2:1 multiplexers 309 and 311 as depicted in FIG. 1 , or via Figure 6 4:1 multiplexers 505a, 505b, 505c, and 505d) depicted in FIG. 4 access the vector channels according to different next addresses. In some embodiments, the address is used to at least partially control the multiplexers and access to the vector channels, for example, the VFR value and address of each channel can be used in combination to control the input selection for the corresponding multiplexer and access to the vector channels.

[0081] At step 436, method 400 continues to determine whether the EA value is equal to the number of elements in one of the vector channels. When the EA value is not equal to the number of elements in one of the vector channels, method 400 continues at step 430 to repeatedly increment the EA value (e.g., changing VAR=1 to VAR=2, and so on).

[0082] Otherwise, at step 438, when the EA value is equal to the number of elements in one of the vector channels, the method 400 ends or includes changing the VFR value. The method 400 may then be repeated for new data.

[0083] As mentioned, the number of corresponding vector channels may be two (see, for example, Figure 3 , where the vector first system 300 is for a multi-channel vector processor having two channels). In such examples, providing the VFR value may include providing, by a vector first register (VFR) in a vector register of a first vector channel of an arithmetic logic unit (ALU) for a vector processor, a VFR value for accessing a first vector channel of a plurality of vector channels of the first ALU. Also, in such examples, providing the VFR value may include providing a VFR value for a second vector channel of a second ALU, the VFR value for accessing a second vector channel of the plurality of vector channels.

[0084] Furthermore, in the above-mentioned example, determining the initial address may include determining a first initial address for accessing the first vector channel based on the VFR value and the element address value. Determining the initial address may also include determining a second initial address for accessing the second vector channel based on the VFR value and the element address value. Accessing the vector channel based on the initial address may include accessing the first vector channel by a first ALU in the ALUs based on the first initial address. And, accessing the vector channel based on the initial address may include accessing the second vector channel by a second ALU in the ALUs based on the second initial address.

[0085] Furthermore, in the above-mentioned example, determining the next address may include determining a first next address for accessing a vector channel in the plurality of vector channels based on the VFR value and the incremented element address value. Determining the next address may also include determining a second next address for accessing a vector channel in the plurality of vector channels based on the VFR value and the incremented element address value. Accessing the vector channel based on the next address may include accessing the first vector channel by the first ALU based on the first next address. Furthermore, in such examples, accessing the vector channel based on the next address may include accessing the second vector channel by the second ALU based on the second next address.

[0086] Moreover, in the above-mentioned example, determining different initial addresses may include determining different first initial addresses for accessing the second vector channel according to the changed VFR value and the reset element address value. Moreover, determining different corresponding initial addresses may include determining different second initial addresses for accessing the first vector channel according to the changed VFR value and the reset element address value. In such examples, accessing the vector channel according to different initial addresses may include accessing the second vector channel by the first ALU according to different first initial addresses. Such access to the vector channel may also include accessing the first vector channel by the second ALU according to different second initial addresses.

[0087] Moreover, in the above-mentioned example, determining a different next address may include determining a different first next address for accessing the second vector channel according to the changed VFR value and the incremented element address value. Determining a different next address may also include determining a different second next address for accessing the first channel according to the changed VFR value and the incremented element address value. In such examples, accessing the vector channel according to the different next addresses may include accessing the second vector channel by the first ALU according to the different first next addresses. Moreover, such access to the corresponding vector channel may include accessing the first vector channel by the second ALU according to the different second next addresses.

[0088] As mentioned, at least the determining, incrementing, and changing described herein may be performed by a vector load store unit of a vector processor according to instructions stored in the vector load store unit.

[0089] Furthermore, in some embodiments, the vector processor may include a third vector register channel and a fourth vector register channel for two additional channels of the first vector register, such that the register includes four channels (see, for example, Figure 6 Components used for and working with the third and fourth vector register channels may be similar to the components used for and working with the first and second vector register channels described herein.

[0090] Figure 6 An exemplary vector first system 500 having four channels is shown in accordance with some embodiments of the present disclosure. Vector first system 500 is somewhat similar to vector first system 300; however, system 500 also includes a third vector register channel and a fourth vector register channel for two additional channels of the first vector register, such that the register includes four channels (e.g., see vector register channels 501a, 501b, 501c, and 501d).

[0091] exist Figure 6 In the embodiment, the ALU (e.g., ALU 504a, 504b, 504c, and 504d) also includes a third channel input and a fourth channel input of the first vector register and the second vector register. The first channel input (e.g., channel input 507a) is used for the output transmitted from the first vector register channel, the second vector register channel, the third vector register channel, or the fourth vector register channel of the first vector register. The second channel input (e.g., channel input 509a) is used for the output transmitted from the first vector register channel, the second vector register channel, the third vector register channel, or the fourth vector register channel of the first vector register. The third channel input (e.g., channel input 511a) is used for the output transmitted from the first vector register channel, the second vector register channel, the third vector register channel, or the fourth vector register channel of the first vector register. And, the fourth channel input (e.g., channel input 513a) is used for the output transmitted from the first vector register channel, the second vector register channel, the third vector register channel, or the fourth vector register channel of the first vector register. In other words, the ALU has four channel inputs from the first vector register, each of which can receive information transmitted from the first vector register channel, the second vector register channel, the third vector register channel, or the fourth vector register channel. However, each of the four channel inputs uniquely interfaces with a corresponding output of a corresponding multiplexer belonging to the corresponding vector channel. In some embodiments, each of the ALUs includes an ALU output that is based on at least one function of the ALU and the channel input of the same channel of the first vector register and the second vector register (e.g., see ALU outputs 514a, 514b, 514c, and 514d).

[0092] Moreover, the ALU (e.g., ALU 504a, 504b, 504c, and 504d) also includes a third channel input and a fourth channel input for a first vector register and a second vector register (except for the output of the second vector register as a channel input of the ALU, the components of the second vector register are not shown - for example, see 507b, 509b, 511b, and 513b). The first channel input (e.g., channel input 507b) is used for output transmitted from the first vector register channel, the second vector register channel, the third vector register channel, or the fourth vector register channel of the second vector register. The second channel input (e.g., channel input 509b) is used for output transmitted from the first vector register channel, the second vector register channel, the third vector register channel, or the fourth vector register channel of the second vector register. The third channel input (e.g., channel input 511b) is used for output transmitted from the first vector register channel, the second vector register channel, the third vector register channel, or the fourth vector register channel of the second vector register. And, the fourth channel input (e.g., channel input 513b) is used for the output transmitted from the first vector register channel, the second vector register channel, the third vector register channel or the fourth vector register channel of the second vector register. In other words, the ALU has four channel inputs from the second vector register, and each of these four channel inputs can receive information transmitted from the first vector register channel, the second vector register channel, the third vector register channel or the fourth vector register channel. Similarly, each of these four channel inputs uniquely docks the corresponding output of the corresponding multiplexer belonging to the corresponding vector channel. In some embodiments, each of the ALUs includes an ALU output, which is based on the channel input of the same channel of at least one function of the ALU and the first vector register and the second vector register (e.g., see ALU outputs 514a, 514b, 514c and 514d).

[0093] As shown, for the vector first system 500, the first 2:1 multiplexer is replaced by a first 4:1 multiplexer 505a, and the second 2:1 multiplexer is replaced by a second 4:1 multiplexer 505b. The system 500 also includes a third 4:1 multiplexer 505c and a fourth 4:1 multiplexer 505d.

[0094] The first 4:1 multiplexer 505a can be configured to receive outputs from the first vector register channel, the second vector register channel, the third vector register channel, and the fourth vector register channel as inputs (e.g., input 506). The first 4:1 multiplexer 505a can also be configured to receive the VFR value as a selection input (e.g., selection input 524a). In some instances, the selection input for the first 4:1 multiplexer is received from the output of a scalar register (e.g., a scalar register in scalar register 515). The first 4:1 multiplexer 505a can also be configured to select an output from the first vector register channel, the second vector register channel, the third vector register channel, or the fourth vector register channel based on the selection input, and transmit the selected output to the first channel input of the ALU (e.g., see input 507a).

[0095] The second 4:1 multiplexer 505b can be configured to receive outputs from the first vector register channel, the second vector register channel, the third vector register channel, and the fourth vector register channel as inputs (e.g., input 508). The second 4:1 multiplexer 505b can also be configured to receive the VFR value as a selection input (e.g., selection input 524b). In some instances, the selection input for the second 4:1 multiplexer is received from the output of a scalar register (e.g., a scalar register in scalar register 515). The second 4:1 multiplexer 505b can also be configured to select an output from the first vector register channel, the second vector register channel, the third vector register channel, or the fourth vector register channel based on the selection input, and transmit the selected output to the second channel input of the ALU (e.g., see input 509a).

[0096] The third 4:1 multiplexer 505c can be configured to receive outputs from the first vector register channel, the second vector register channel, the third vector register channel, and the fourth vector register channel as inputs (e.g., input 510). The third 4:1 multiplexer 505c can also be configured to receive the VFR value as a selection input (e.g., selection input 524c). In some instances, the selection input for the third 4:1 multiplexer is received from the output of a scalar register (e.g., a scalar register in scalar register 515). The third 4:1 multiplexer 505c can also be configured to select an output from the first vector register channel, the second vector register channel, the third vector register channel, or the fourth vector register channel based on the selection input, and transmit the selected output to the third channel input of the ALU (e.g., see input 511a).

[0097] The fourth 4:1 multiplexer 505d can be configured to receive outputs from the first vector register channel, the second vector register channel, the third vector register channel, and the fourth vector register channel as inputs (e.g., input 512). The fourth 4:1 multiplexer 505d is also configured to receive the VFR value as a selection input (e.g., selection input 524d). In some instances, the selection input for the fourth 4:1 multiplexer is received from the output of a scalar register (e.g., a scalar register in scalar register 515). The fourth 4:1 multiplexer 505d is also configured to select an output from the first vector register channel, the second vector register channel, the third vector register channel, or the fourth vector register channel based on the selection input, and transmit the selected output to the fourth channel input of the ALU (e.g., see input 513a).

[0098] Furthermore, scalar registers 515 may include programmable scalar registers. Programmable scalar registers may be used so that a vector provided by a vector register (e.g., a vector register having channels 501a, 501b, 501c, and 501d) may be operated on by a scalar provided by and programmed into one of the programmable scalar registers. For example, one of the operations may include multiplying a vector by a scalar value (e.g., vector A(i)×scalar p).

[0099] Some parts of the foregoing detailed description have been presented according to the algorithm and symbolic representation of the operation of the data bit in the computer memory. These algorithmic descriptions and representations are commonly used by those skilled in the art of data processing, so as to most effectively transfer their work essence to those skilled in other fields. The algorithm herein generally refers to a self-consistent sequence of operations that obtain a desired result. These operations are operations that require physical manipulation of physical quantities. Usually, although not necessarily, these quantities take the form of electrical or magnetic signals that can be stored, combined, compared and otherwise manipulated. Sometimes, mainly for the reasons of public use, these signals are referred to as positions, values, elements, symbols, characters, items, numerals or similar names, which have been proven to be convenient.

[0100] It should be remembered, however, that all of these and similar terms will be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may refer to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0101] The present disclosure also relates to an apparatus for performing the operations herein. Such an apparatus may be specifically constructed for the intended purpose, or it may comprise a computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, all of which are each coupled to a computer system bus.

[0102] The algorithms and displays presented herein are not inherently associated with any particular computer or other device. Various systems can be used together with programs according to the teachings herein, or it may be convenient to construct more specialized equipment to perform the method. As described below, structures for various of these systems will occur. In addition, the present disclosure is not described with reference to any particular programming language. It should be understood that various programming languages ​​may be used to implement the teachings of the present disclosure as described herein.

[0103] The present disclosure may be provided in part as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, which may be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. The machine-readable medium includes any mechanism for storing information in a machine (e.g., computer) readable form. In some embodiments, the machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a disk storage medium, an optical storage medium, a flash memory component, etc.

[0104] In the foregoing description, embodiments of the present disclosure have been described with reference to specific exemplary embodiments of the present disclosure. It will be apparent that various modifications may be made thereto without departing from the broader scope and spirit of the embodiments of the present disclosure as set forth in the appended claims. Therefore, this specification and the accompanying drawings should be understood in an illustrative rather than a restrictive sense.

Claims

1. A method for a vector processor, comprising: The first vector register and the second vector register each provide inputs to a plurality of arithmetic logic units ALUs of the vector processor, each of the first vector register and the second vector register comprising a plurality of lanes, and the number of the lanes of each register is a power of two and equal to the number of ALUs receiving inputs from the first vector register and the second vector register; and For each vector register of the first vector register and the second vector register: A vector first register value VFR value for accessing the channel is provided by a vector first register VFR; The element address value EA value is provided by the index of the channel; determining an initial address for accessing the channel according to the VFR value and the EA value; Accessing the channel by the ALU according to the initial address; Incrementing the EA value; determining a next address for accessing the channel according to the VFR value and the incremented EA value; accessing the channel by the ALU according to the next address; Repeating said incrementing of said EA value; When the EA value is equal to the number of elements in one of the channels, changing the VFR value; Resetting the EA value at the index; Determining a different initial address for accessing the channel according to the changed VFR value and the reset EA value; The ALU accesses the channel according to different initial addresses; Incrementing the reset EA value; determining a different next address for accessing the channel based on the changed VFR value and the incremented EA value; and The channel is accessed by the ALU according to the different next address.

2. The method according to claim 1, The determining of the initial address includes: determining a first initial address for accessing a first channel of the channels based on the VFR value and the EA value; and determining a second initial address for accessing a second channel of the channels according to the VFR value and the EA value; and Wherein the accessing of the channel according to the initial address comprises: accessing the first channel by a first ALU among the ALUs according to the first initial address; and The second channel is accessed by a second ALU among the ALUs according to the second initial address.

3. The method according to claim 2, Wherein the determination of the next address comprises: determining a first next address for accessing the first channel according to the VFR value and the incremented EA value; and determining a second next address for accessing the second channel according to the VFR value and the incremented EA value; and Wherein the accessing of the channel according to the next address comprises: accessing the first channel by the first ALU according to the first next address; and The second channel is accessed by the second ALU according to the second next address.

4. The method according to claim 3, The determining of the different initial addresses includes: determining a different first initial address for accessing the second channel according to the changed VFR value and the reset EA value; and determining a different second initial address for accessing the first channel according to the changed VFR value and the reset EA value; and Wherein the accessing of the channel according to the different initial addresses comprises: accessing the second channel by the first ALU according to the different first initial address; and The first channel is accessed by the second ALU according to the different second initial address.

5. The method according to claim 4, Wherein the determination of the different next address comprises: determining a different first next address for accessing the second channel according to the changed VFR value and the incremented EA value; and determining a different second next address for accessing the first channel according to the changed VFR value and the incremented EA value; and Wherein the accessing of the corresponding channel according to different corresponding next addresses comprises: accessing the second channel by the first ALU according to the different first next address; and The first channel is accessed by the second ALU according to the different second next address.

6. The method of claim 1, wherein the number of the channels is four.

7. The method of claim 1, wherein at least the determining, the incrementing, and the changing of the value are performed by a vector load store unit of the vector processor according to instructions in the vector load store unit.

8. A vector processor, comprising: Vector load storage unit; vector registers, at least one of the vector registers comprising a first vector register channel and a second vector register channel for two channels of the vector register; a scalar register, the scalar register comprising a programmable scalar register; an arithmetic logic unit ALU, the ALU comprising a first ALU and a second ALU, the first ALU and the second ALU being connected to the vector register and the programmable scalar register so that the values ​​provided by the channels of the vector register can be operated on by the values ​​provided by the programmable scalar register, the first ALU comprising a first channel input for output transmitted from the first vector register channel or the second vector register channel, and the second ALU comprising a second channel input for output transmitted from the first vector register channel or the second vector register channel; as well as A bus configured to communicatively couple the vector load storage unit, the vector register, and the arithmetic logic unit, the bus comprising: First 2:1 multiplexer, the multiplexer is configured as: receiving as input an output from the first vector register channel and an output from a second vector register channel; Receive the vector first register value VFR value as a selection input; selecting the output from the first vector register channel or the output from the second vector register channel based on the select input; and passing the selected output to the first channel input of the first ALU; and A second 2:1 multiplexer, the multiplexer is configured as: receiving as input the output from the first vector register channel and the output from the second vector register channel; receiving the VFR value as a selection input; selecting the output from the first vector register channel or the output from the second vector register channel based on the select input; and The selected output is passed to the second channel input of the second ALU. 9 . The vector processor of claim 8 , further comprising a vector first register (VFR) configured to provide the VFR value to the first 2:1 multiplexer and the second 2:1 multiplexer.

10. The vector processor of claim 9, further comprising an index register configured to provide an element address EA value, and wherein: The vector load store unit is configured as: Determining a first initial address for accessing the first vector register channel according to the VFR value and the EA value; and determining a second initial address for accessing the second vector register channel according to the VFR value and the EA value; The first ALU is configured to access the first vector register channel according to the first initial address; and The second ALU is configured to access the second vector register channel according to the second initial address.

11. The vector processor of claim 10, wherein: The vector load store unit is configured as: Incrementing the EA value; Determining a first next address for accessing the first vector register channel according to the VFR value and the incremented EA value; and determining a second next address for accessing the second vector register channel according to the VFR value and the incremented EA value; The first ALU is configured to access the first vector register channel according to the first next address; and The second ALU is configured to access the second vector register lane according to the second next address.

12. The vector processor according to claim 11, wherein the vector load store unit is configured to: repeating said incrementing of said EA value; and When the EA value is equal to the number of elements in the first vector register lane or the second vector register, the VFR value is changed.

13. The vector processor of claim 12, wherein: The vector load store unit is configured as: Resetting the EA value at the index; Determine a different first initial address for accessing the second vector register channel according to the changed VFR value and the reset EA value; and determining a different second initial address for accessing the first vector register channel according to the changed VFR value and the reset EA value; The first ALU is configured to access the second vector register channel according to the different first initial address; and The second ALU is configured to access the first vector register channel according to the different second initial address.

14. The vector processor of claim 13, wherein: The vector load store unit is configured as: Incrementing the reset EA value; determining a different first next address for accessing the second vector register channel based on the changed VFR value and the incremented EA; and determining a different second next address for accessing the first vector register channel according to the changed VFR value and the incremented EA; The first ALU is configured to access the second vector register channel according to the different first next address; and The second ALU is configured to access the first vector register channel according to the different second next address.

15. The vector processor of claim 8 further comprising a third vector register lane and a fourth vector register lane for two additional lanes of the vector register such that the register comprises four lanes.

16. A system for a vector processor, comprising: a first vector register channel and a second vector register channel for two channels of the first vector register; a first vector register channel and a second vector register channel for two channels of a second vector register; a first arithmetic logic unit ALU connected to the first vector register and the second vector register, the first arithmetic logic unit comprising, for each of the first vector register and the second vector register, a first channel input for an output transmitted from the first vector register channel or the second vector register channel; a second arithmetic logic unit ALU, the second arithmetic logic unit ALU being connected to the first vector register and the second vector register, the second arithmetic logic unit ALU comprising, for each of the first vector register and the second vector register, a second channel input for an output transmitted from the first vector register channel or the second vector register channel; as well as a bus configured to connect the first vector register and the second vector register to the ALU, and for each of the first vector register and the second vector register, the bus comprises: First 2:1 multiplexer, the multiplexer is configured as: receiving as input an output from the first vector register channel and an output from a second vector register channel; Receive the vector first register value VFR value as a selection input; selecting the output from the first vector register channel or the output from the second vector register channel based on a select input; and passing the selected output to the first channel input of the first arithmetic logic unit ALU; and A second 2:1 multiplexer, the multiplexer is configured as: receiving as input the output from the first vector register channel and the output from the second vector register channel; receiving the VFR value as a selection input; selecting the output from the first vector register channel or the output from the second vector register channel based on the select input; and The selected output is transferred to the second channel input of the second arithmetic logic unit ALU.

17. The system of claim 16, wherein for each of the first and second vector registers, the system further comprises a third vector register channel and a fourth vector register channel for two additional channels of the vector register, such that the register comprises four channels, and wherein there is an ALU for each of the four channels.

18. The system of claim 17, wherein each of the four ALUs comprises a corresponding channel input, and wherein the corresponding channel input is used for output transmitted from the first vector register channel, the second vector register channel, the third vector register channel, or the fourth vector register channel.

19. The system of claim 18, wherein the first 2:1 multiplexer is replaced by a first 4:1 multiplexer, wherein the second 2:1 multiplexer is replaced by a second 4:1 multiplexer, and wherein the system further comprises a third 4:1 multiplexer and a fourth 4:1 multiplexer.

20. The system of claim 19, wherein: The first 4:1 multiplexer is configured as: receiving as input the outputs from the first vector register channel, the second vector register channel, the third vector register channel, and the fourth vector register channel; receiving the VFR value as a selection input; selecting the output from the first vector register channel, the second vector register channel, the third vector register channel, or the fourth vector register channel based on the select input; and transmitting the selected output to a first channel input of a first ALU of the four ALUs; The second 4:1 multiplexer is configured as: receiving as input the outputs from the first vector register channel, the second vector register channel, the third vector register channel, and the fourth vector register channel; receiving the VFR value as a selection input; selecting the output from the first vector register channel, the second vector register channel, the third vector register channel, or the fourth vector register channel based on the select input; and transmitting the selected output to a second channel input of a second ALU of the four ALUs; The third 4:1 multiplexer is configured as: receiving as input the outputs from the first vector register channel, the second vector register channel, the third vector register channel, and the fourth vector register channel; receiving the VFR value as a selection input; selecting the output from the first vector register channel, the second vector register channel, the third vector register channel, or the fourth vector register channel based on the select input; and transmitting the selected output to a third channel input of a third ALU of the four ALUs; and The fourth 4:1 multiplexer is configured as: receiving as input the outputs from the first vector register channel, the second vector register channel, the third vector register channel, and the fourth vector register channel; receiving the VFR value as a selection input; selecting the output from the first vector register channel, the second vector register channel, the third vector register channel, or the fourth vector register channel based on the selection input; and The selected output is transmitted to a fourth channel input of a fourth ALU of the four ALUs.

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