Light emitting device, display device including the same, and method for manufacturing the display device

Abstract

Disclosed are a light-emitting device, a display device including the same, and a method for manufacturing the display device. The display device may include a substrate. Multiple light-emitting element layers may be stacked on the substrate. Each of the light-emitting element layers may include an insulating layer disposed over the entire surface of the substrate, a first electrode and a second electrode disposed on the insulating layer and spaced apart from each other, and multiple light-emitting elements disposed between the first and second electrodes.

Description

Technical Field

[0001] Various embodiments of the present disclosure relate to a light emitting device, a display apparatus having the light emitting device, and a method of manufacturing the display apparatus. Background Art

[0002] Recently, technologies have been developed for manufacturing ultra-small light-emitting elements using materials with highly reliable inorganic crystal structures, as well as for manufacturing light-emitting devices using these elements. For example, technologies have been developed for configuring light sources for light-emitting devices using ultra-small light-emitting elements with small sizes ranging from nanometers to micrometers. Such light-emitting devices can be used in various electronic devices, such as display devices and lighting equipment. Summary of the Invention

[0003] Technical issues

[0004] A typical light emitting device includes sub-pixels arranged in a horizontal structure and emitting light of different colors, such as red, green, and blue, and the resolution of the light emitting device is limited by the size of the sub-pixels and the intervals between the sub-pixels.

[0005] Furthermore, the number of ultra-small light-emitting elements that can be arranged in a unit area (eg, an area corresponding to one sub-pixel) is limited, making it difficult to obtain better luminous flux.

[0006] A technical object of the present disclosure is to provide a light emitting device having improved brightness and / or high resolution and a display apparatus having the same.

[0007] A technical object of the present disclosure is to provide a method for manufacturing a display device.

[0008] Technical Solution

[0009] To achieve the objectives of the present disclosure, a light-emitting device according to an embodiment of the present disclosure may include: a substrate; and a plurality of light-emitting element layers stacked on the substrate. Here, each of the light-emitting element layers may include: an insulating layer disposed over the entire surface of the substrate; a first electrode and a second electrode disposed on the insulating layer and spaced apart from each other; and a plurality of light-emitting elements disposed between the first electrode and the second electrode.

[0010] According to an embodiment, the light emitting device may further include a common electrode layer provided between a first light emitting element layer closest to the substrate among the light emitting element layers and the substrate, and including a first common electrode and a second common electrode spaced apart from each other.

[0011] According to an embodiment, the first electrode may overlap with the first common electrode, and the second electrode may overlap with the second common electrode.

[0012] According to an embodiment, each of the light emitting elements may be a rod-type light emitting diode having a size ranging from a nanometer level to a micrometer level.

[0013] According to an embodiment, each of the light emitting element layers may emit monochromatic light.

[0014] According to an embodiment, at least a portion of the light emitting element layer may emit light of different colors.

[0015] According to an embodiment, the light emitting elements may be provided between the first and second electrodes and the insulating layer, respective first ends of the light emitting elements may be coupled to the first electrode, and respective second ends of the light emitting elements may be coupled to the second electrode.

[0016] According to an embodiment, the light-emitting element layer may include a first light-emitting element layer, a second light-emitting element layer, and a third light-emitting element layer sequentially arranged on a substrate, the first light-emitting element layer including a first light-emitting element configured to emit light of a first color, the second light-emitting element layer including a second light-emitting element configured to emit light of a second color, and the third light-emitting element layer including a third light-emitting element configured to emit light of a third color.

[0017] According to an embodiment, the light-emitting device may further include a dam pattern arranged between a first light-emitting element layer closest to the substrate among a plurality of light-emitting element layers and the substrate, wherein the substrate includes an emission area and a non-emission area surrounding the emission area, the light-emitting element is arranged in the emission area of ​​the substrate, and the thickness of the dam pattern is greater than the thickness of the light-emitting element layer.

[0018] To achieve the purpose of the present disclosure, a light-emitting device according to an embodiment of the present disclosure may include: a substrate; a circuit element layer including a plurality of transistors and a power line; a common electrode layer including a first common electrode and a second common electrode arranged on the substrate and spaced apart from each other; and a plurality of light-emitting element layers sequentially arranged on the common electrode layer, wherein each of the light-emitting element layers includes: an insulating layer arranged on the entire surface of the substrate; a first electrode and a second electrode arranged on the insulating layer and spaced apart from each other; and a plurality of light-emitting elements arranged between the first electrode and the second electrode, wherein the first electrode is connected to one of the transistors and the second electrode is connected to the power line.

[0019] According to an embodiment, the light-emitting element layer may include a first light-emitting element layer, a second light-emitting element layer, and a third light-emitting element layer sequentially arranged on a substrate, the first light-emitting element layer including a first light-emitting element configured to emit light of a first color, the second light-emitting element layer including a second light-emitting element configured to emit light of a second color, and the third light-emitting element layer including a third light-emitting element configured to emit light of a third color.

[0020] According to an embodiment, the first electrode of the first light-emitting element layer is connected to the first transistor among the transistors through a first contact hole passing through the insulating layer of the first light-emitting element layer, and the second electrode of the first light-emitting element layer is connected to the power line through a second contact hole passing through the insulating layer of the first light-emitting element layer.

[0021] According to an embodiment, the first light-emitting element layer further includes a first bridging pattern disposed to be spaced apart from the first electrode and the second electrode of the first light-emitting element layer, the first electrode of the second light-emitting element layer is connected to the second transistor among the transistors through a third contact hole and the first bridging pattern of the first light-emitting element layer, the third contact hole is configured to expose the first bridging pattern by passing through the insulating layer of the second light-emitting element layer, and the second electrode of the second light-emitting element layer is connected to the second electrode of the first light-emitting element layer through a fourth contact hole, and the fourth contact hole is configured to expose the second electrode of the first light-emitting element layer by passing through the insulating layer of the second light-emitting element layer.

[0022] According to an embodiment, the first electrode of the third light-emitting element layer is connected to the third transistor among the transistors through a fifth contact hole passing through the insulating layer of the third light-emitting element layer, and the second electrode of the third light-emitting element layer is connected to the second electrode of the second light-emitting element layer through a sixth contact hole, and the sixth contact hole is configured to expose the second electrode of the second light-emitting element layer by passing through the insulating layer of the third light-emitting element layer.

[0023] To achieve the purpose of the present disclosure, a method for manufacturing a display device includes: preparing a substrate; forming a common electrode layer including a first common electrode and a second common electrode spaced apart from each other on the substrate; forming a first light-emitting element layer on the common electrode layer; and forming a second light-emitting element layer on the first light-emitting element layer, wherein forming the first light-emitting element layer includes: forming a first insulating layer on the common electrode layer; aligning a plurality of first light-emitting elements on the first insulating layer, wherein, in a plan view, the first light-emitting elements are arranged between the first common electrode and the second common electrode; and forming a first electrode on a first end of the first light-emitting element, and forming a second electrode on a second end of the first light-emitting element, respectively.

[0024] According to an embodiment, each of the light emitting elements may be a rod-type light emitting diode having a size ranging from a nanometer level to a micrometer level.

[0025] According to an embodiment, aligning the plurality of first light emitting elements may include: disposing the first light emitting elements on the first insulating layer; and applying a first alternating voltage between the first common electrode and the second common electrode.

[0026] According to an embodiment, the first electrode may overlap at least a portion of the first common electrode, and the second electrode may overlap at least a portion of the second common electrode.

[0027] According to an embodiment, forming a second light-emitting element layer may include: forming a second insulating layer on the first light-emitting element layer; aligning a plurality of second light-emitting elements between the first common electrode and the second common electrode in a plan view; and forming a third electrode on the first end of the second light-emitting element, respectively, and forming a fourth electrode on the second end of the second light-emitting element.

[0028] According to an embodiment, the first light emitting element may emit light of a first color, and the second light emitting element may emit light of a second color.

[0029] Beneficial effects

[0030] The light emitting device and the display apparatus according to the embodiments of the present disclosure may include a light emitting element layer having a multilayer structure in which light emitting elements are arranged in three dimensions, thereby achieving improved brightness and high resolution.

[0031] The method of manufacturing a display device according to an embodiment of the present disclosure can manufacture a display device including a light emitting element layer having a multi-layer structure by repeatedly performing formation of an electric field and alignment of light emitting elements using separate common electrodes that do not contact the light emitting elements. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1a and Figure 1b are a perspective view and a cross-sectional view illustrating a light emitting element according to an embodiment of the present disclosure.

[0033] Figure 2a and Figure 2b are a perspective view and a cross-sectional view illustrating a light emitting element according to another embodiment of the present disclosure.

[0034] Figure 3a and Figure 3b are a perspective view and a cross-sectional view illustrating a light emitting element according to another embodiment of the present disclosure.

[0035] Figure 4 is a perspective view showing a light emitting device according to an embodiment of the present disclosure.

[0036] Figure 5 yes Figure 4 An exploded perspective view of a light emitting device.

[0037] Figure 6 It is shown along Figure 4 FIG. 1 is a cross-sectional view of an example of a light emitting device taken along line II′.

[0038] Figures 7a to 7i Is used to explain the manufacturing Figure 4 A view of the process of light emitting devices.

[0039] Figures 8a to 8e It is used to explain the formation Figure 7e A view of the process of the first electrode and the second electrode.

[0040] Figure 9 is a plan view illustrating a display device according to an embodiment of the present disclosure.

[0041] Figures 10a to 10c It is shown that the Figure 9 A circuit diagram of an example of a pixel in a display device.

[0042] Figure 11 It shows Figure 9 A cross-sectional view of an example of a display device.

[0043] Figures 12a to 12c It is shown that the Figure 9 A plan view of an example of a pixel in a display device.

[0044] Figure 13 is shown along Figure 12c A cross-sectional view of an example of a pixel taken along line II-II'.

[0045] Figure 14 It is shown that the Figure 9 A plan view of an example of a pixel in a display device.

[0046] Figure 15 It is shown that the Figure 9 A plan view of an example of a pixel in a display device.

[0047] Figure 16 It is shown along Figure 15 1 is a cross-sectional view of an example of a pixel taken along line III-III'. DETAILED DESCRIPTION

[0048] Since the embodiments of the present disclosure can be modified in many different forms, reference will now be made in detail to the various embodiments of the present disclosure, specific examples of which are shown in the accompanying drawings and described below. However, the present disclosure can be modified and practiced in various forms without being limited to the following embodiments.

[0049] In order to clearly explain the present disclosure, some elements that are not directly related to the features of the present disclosure may be omitted in the accompanying drawings. In addition, the sizes, ratios, etc. of some elements in the accompanying drawings may be slightly exaggerated. It should be noted that in all the accompanying drawings, the same reference numerals are used to represent the same or similar elements, and therefore repeated description thereof will be omitted.

[0050] Terms such as first and second can be used to identify and describe various components, but they should not limit the various components. In addition, in this specification, it should be understood that terms such as "including" or "having" are only intended to indicate the presence of a feature, number, step, operation, component, part or combination thereof, and are not intended to exclude the possibility that one or more other features, numbers, steps, operations, components, parts or combinations thereof will be present or added. In addition, when a first part such as a layer, film, region or plate is disposed on a second part, the first part can not only be disposed directly on the second part, but a third part can be interposed between them. In addition, the specific positions or directions defined in the following description are described only from a relative standpoint, and it should be noted that the position or direction can be reversed according to, for example, the view or orientation.

[0051] The embodiments of the present disclosure and necessary details are described with reference to the accompanying drawings so that the present disclosure is described in detail so that those skilled in the art can easily practice the present disclosure. In addition, a singular form may include a plural form as long as it is not specifically mentioned in a sentence.

[0052] Figure 1a and Figure 1b 1 is a perspective view and a cross-sectional view showing a light emitting element according to an embodiment of the present disclosure. Figure 1a and Figure 1b , a cylindrical rod-type light emitting element LD is shown in FIG, but the type and / or shape of the light emitting element LD according to the present disclosure is not limited thereto.

[0053] Reference Figure 1a and Figure 1b The light emitting element LD may include a first conductive semiconductor layer 11, a second conductive semiconductor layer 13, and an active layer 12 interposed between the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13. In an example, the light emitting element LD may be configured as a stack in which the first conductive semiconductor layer 11, the active layer 12, and the second conductive semiconductor layer 13 are sequentially stacked in one direction.

[0054] In an embodiment, the light emitting element LD may be provided in the form of a rod extending in one direction. The light emitting element LD may have a first end and a second end in one direction.

[0055] In an embodiment, one of the first and second conductive semiconductor layers 11 and 13 may be disposed on a first end of the light emitting element LD, and the other may be disposed on a second end of the light emitting element LD.

[0056] In an embodiment, the light-emitting element LD may be a rod-type light-emitting diode manufactured in the form of a rod. Here, the term "rod-type" includes a rod-like or bar-like shape having a longitudinal length greater than a lateral length (i.e., having an aspect ratio greater than 1), such as a cylindrical or prismatic shape, and its cross-sectional shape is not particularly limited. For example, the length L of the light-emitting element LD may be greater than its diameter D (or the width of its cross section).

[0057] In an embodiment, the light-emitting element LD may have a size as small as nanometer or micrometer, for example, the diameter D and / or the length L may fall within the micrometer or nanometer range. However, the size of the light-emitting element LD is not limited thereto. For example, the size of the light-emitting element LD may be changed in various ways according to the design conditions of various types of devices (for example, a display device using a light-emitting device using the light-emitting element LD as a light source).

[0058] The first conductive semiconductor layer 11 may include at least one n-type semiconductor layer. For example, the first conductive semiconductor layer 11 may include any one of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN semiconductor materials, and may be doped with a first conductive dopant such as Si, Ge, or Sn. However, the material forming the first conductive semiconductor layer 11 is not limited thereto, and the first conductive semiconductor layer 11 may also be formed of various materials other than the above materials. The thickness of the first conductive semiconductor layer 11 may be, but is not limited to, 500 nm to 5 μm.

[0059] The active layer 12 may be provided on the first conductive semiconductor layer 11 and may be formed to have a single quantum well or multi-quantum well structure. In an embodiment, a capping layer (not shown) doped with a conductive dopant may be formed on and / or below the active layer 12. For example, the capping layer may be formed of an AlGaN layer or an InAlGaN layer. In an embodiment, a material such as AlGaN or AlInGaN may be used to form the active layer 12, and various other materials may also be used to form the active layer 12.

[0060] When an electric field of a predetermined voltage or higher is applied to opposite ends of the light-emitting element LD, the light-emitting element LD can emit light while electron-hole pairs are combined in the active layer 12. Since the light emission through the light-emitting element LD is controlled based on the aforementioned principle, the light-emitting element LD can be used as a light source for various light-emitting devices and pixels of display devices. The thickness of the active layer 12 may be, but is not limited to, 10 nm to 200 nm.

[0061] The second conductive semiconductor layer 13 may be provided on the active layer 12 and may include a semiconductor layer of a different type than the first conductive semiconductor layer 11. For example, the second conductive semiconductor layer 13 may include at least one p-type semiconductor layer. For example, the second conductive semiconductor layer 13 may include a semiconductor material corresponding to at least one of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may be doped with a second conductive dopant such as Mg. However, the material forming the second conductive semiconductor layer 13 is not limited thereto, and the second conductive semiconductor layer 13 may also be formed of various materials in addition to the above materials. The thickness of the second conductive semiconductor layer 13 may be, but is not limited to, 50 nm to 500 nm.

[0062] According to an embodiment, the light emitting element LD may further include an insulating film INF disposed on its surface. The insulating film INF may be formed on the surface of the light emitting element LD so as to surround at least the outer peripheral surface of the active layer 12, and may also surround a portion of each of the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13. Here, the insulating film INF may expose opposite ends of the light emitting element LD having different polarities. For example, the insulating film INF may expose the first end of each of the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13, for example, rather than covering the cylinder, the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13 may be exposed on respective opposite ends of the light emitting element LD in the longitudinal direction.

[0063] In an embodiment, the insulating film INF may include but is not limited to at least one insulating material of SiO 2 , Si 3 N 4 , Al 2 O 3 , and TiO 2 . In other words, the material forming the insulating film INF is not limited to a specific material and the insulating film INF may be formed of various well-known insulating materials.

[0064] In an embodiment, the light emitting element LD may further include additional components as well as the first conductive semiconductor layer 11, the active layer 12, the second conductive semiconductor layer 13, and the insulating film INF. For example, the light emitting element LD may further include one or more fluorescent layers, active layers, semiconductor layers, and / or electrode layers disposed on first ends of the first conductive semiconductor layer 11 and / or the second conductive semiconductor layer 13.

[0065] Figure 2a and Figure 2b are a perspective view and a cross-sectional view illustrating a light emitting element according to another embodiment of the present disclosure. Figure 3a and Figure 3b are a perspective view and a cross-sectional view illustrating a light emitting element according to another embodiment of the present disclosure.

[0066] Reference Figure 2a and Figure 2b The light emitting element LD may further include at least one electrode layer 14 disposed on one end of the second conductive semiconductor layer 13 .

[0067] Reference Figure 3a and Figure 3b The light emitting element LD may further include at least one additional electrode layer 15 disposed on one end of the first conductive semiconductor layer 11 .

[0068] Each of the electrode layers 14 and 15 may be, but is not limited to, an ohmic contact electrode. Furthermore, each of the electrode layers 14 and 15 may include a metal or a conductive metal oxide and may be formed using, for example, chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), and oxides or alloys thereof, alone or in combination with one another. The electrode layers 14 and 15 may be substantially transparent or translucent. Thus, light generated from the light-emitting element LD may be emitted to the outside of the light-emitting element LD after passing through the electrode layers 14 and 15. The thickness of each of the electrode layers 14 and 15 may be, but is not limited to, 1 nm to 200 nm.

[0069] In an embodiment, the insulating film INF may at least partially surround the outer surfaces of the electrode layers 14 and 15, or may not surround them. In other words, the insulating film INF may be selectively formed on the surfaces of the electrode layers 14 and 15. In addition, the insulating film INF may be formed to expose opposite ends of the light-emitting element LD having different polarities, for example, to expose at least one region of each of the electrode layers 14 and 15. However, the present disclosure is not limited thereto, and the insulating film INF may not be provided.

[0070] An insulating film INF may be provided on the surface of the light-emitting element LD, for example, on the surface of the active layer 12, thereby preventing the active layer 12 from being short-circuited with at least one electrode (for example, at least one of the contact electrodes coupled to opposite ends of the light-emitting element LD). Therefore, the electrical stability of the light-emitting element LD can be ensured.

[0071] Furthermore, an insulating film INF is formed on the surface of the light-emitting element LD, thereby minimizing defects on the surface of the light-emitting element LD and improving the lifespan and efficiency of the light-emitting element LD. Furthermore, the insulating film INF is formed on the light-emitting element LD, and thus, even if the light-emitting elements LD are arranged closer to each other, it is possible to prevent an undesirable short circuit from occurring between the plurality of light-emitting elements LD.

[0072] In an embodiment, the light-emitting element LD may be manufactured by a surface treatment process (e.g., coating). For example, when a plurality of light-emitting elements LD are mixed with a fluid solution and provided to corresponding emission regions (e.g., emission regions of corresponding pixels), the light-emitting elements LD may be uniformly distributed without agglomerating in the solution. Here, the emission region may be a region where light is emitted from the light-emitting element LD and may be distinguished from a non-emission region that does not emit light.

[0073] Light-emitting devices including light-emitting elements LD can be used in various types of devices requiring light sources, as well as in display devices. For example, multiple ultra-small light-emitting elements LD can be arranged in each pixel area of ​​a display panel, and the light-emitting elements LD can be used to configure the emission unit of each pixel. However, the application field of the light-emitting elements LD in the present disclosure is not limited to display devices. For example, the light-emitting elements LD can also be used in other types of devices requiring light sources, such as lighting devices.

[0074] Figure 4 : is a perspective view showing a light emitting device according to an embodiment of the present disclosure. Figure 4 In the figure, the light emitting device EU is shown as a reference that can be used Figures 1a to 3b The light emitting element LD described above is an example of a device as a light source. Figure 4 , the light emitting device EU is briefly illustrated based on its unit emission region. Here, the unit emission region may be a unit region from which light is emitted, and may be, for example, a region capable of independently adjusting brightness and / or color of emitted light.

[0075] Figure 5 yes Figure 4 An exploded perspective view of the light emitting device. Figure 5 In the figure, we show Figure 4 The layers included in . Figure 6 It is shown along Figure 4 FIG. 1 is a cross-sectional view of an example of a light emitting device taken along line II′.

[0076] Reference Figures 4 to 6 , the light emitting device EU may include a substrate SUB, a common electrode layer AEL, and light emitting element layers LDL1 , LDL2 , and LDL3 .

[0077] The substrate SUB may form a base member for the light emitting device EU.

[0078] Depending on the embodiment, the substrate SUB may be a rigid or flexible substrate, and there are no particular limitations on its material or properties. For example, the substrate SUB may be a rigid substrate made of glass or reinforced glass, or a flexible substrate formed of a thin film made of plastic or metal. Furthermore, the substrate SUB may be, but is not limited to, a transparent substrate. In some examples, the substrate SUB may be a translucent substrate, an opaque substrate, or a reflective substrate.

[0079] The common electrode layer AEL (or alignment electrode layer) may be provided on the substrate SUB and may include a first common electrode AELT1 (or a first alignment electrode) and a second common electrode AELT2 (or a second alignment electrode).

[0080] The first common electrode AELT1 and the second common electrode AELT2 may be disposed in the unit emission region and spaced apart from each other, and may be disposed such that at least portions thereof face each other.

[0081] According to an embodiment, each of the first common electrode AELT1 and the second common electrode AELT2 may include a rod electrode and at least one branch electrode (hereinafter referred to as a branch electrode). The rod electrode may extend in the second direction DR2 within the corresponding unit emission region. When the light emitting device EU includes a plurality of unit emission regions, the rod electrode extends from the corresponding unit emission region to another unit emission region. The branch electrode may extend from the rod electrode in the first direction DR1 intersecting with the second direction DR2. For example, Figure 5 As shown in , each of the first common electrode AELT1 and the second common electrode AELT2 may include four branch electrodes branching from the rod electrode. The branch electrodes of the first common electrode AELT1 and the branch electrodes of the second common electrode AELT2 may be alternately arranged in the second direction DR2 while being spaced apart from each other by a predetermined interval. The separation distance (or spacing) between the branch electrodes of the first common electrode AELT1 and the second common electrode AELT2 may be less than or equal to the length of each of the light emitting elements LD, but the separation distance is not limited thereto. The line width and thickness of each of the first common electrode AELT1 and the second common electrode AELT2 may vary depending on the voltage applied thereto, and the line width of each of the first common electrode AELT1 and the second common electrode AELT2 may be in the range from 100 nm to 50 μm, and the thickness of each of the first common electrode AELT1 and the second common electrode AELT2 may be in the range from 0.1 μm to 10 μm.

[0082] However, the shapes and / or mutual arrangement relationship of the first common electrode AELT1 and the second common electrode AELT2 may be changed in various ways.

[0083] At the same time, despite Figure 5 , each of the first common electrode AELT1 and the second common electrode AELT2 is shown as including four branch electrodes, but the present disclosure is not limited thereto. In an example, each of the first common electrode AELT1 and the second common electrode AELT2 may include three or fewer branch electrodes or five or more branch electrodes, and in another example, the first common electrode AELT1 may include two branch electrodes, and the second common electrode AELT2 may include one branch electrode (see Figure 16 ).

[0084] Each of the first common electrode AELT1 and the second common electrode AELT2 may include at least one conductive material. In an example, each of the first common electrode AELT1 and the second common electrode AELT2 may include, but is not limited to, a material corresponding to at least one of a metal (such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Ti, or an alloy thereof), a conductive oxide (such as ITO, IZO, ZnO, or ITZO), and a conductive polymer (such as PEDOT).

[0085] In an embodiment, each of the first common electrode AELT1 and the second common electrode AELT2 may have a single-layer or multi-layer structure. In an example, the first common electrode AELT1 may have a multi-layer structure including a first reflective electrode and a first conductive cover layer, and the second common electrode AELT2 may have a multi-layer structure including a second reflective electrode and a second conductive cover layer.

[0086] The reflective electrode of each of the first common electrode AELT1 and the second common electrode AELT2 may be made of a conductive material having uniform reflectivity. In an example, the reflective electrode may include, but is not limited to, at least one of metals such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, and alloys thereof.

[0087] The light emitting element layers LDL1, LDL2, and LDL3 may be sequentially arranged on the substrate SUB and the common electrode layer AEL along a third direction DR3. Here, the third direction DR3 may be substantially perpendicular to the first direction DR1 and the second direction DR2.

[0088] In an embodiment, the light-emitting element layers LDL1, LDL2, and LDL3 may include a first light-emitting element layer LDL1 (or a first emission unit or a first light-emitting electrode assembly), a second light-emitting element layer LDL2 (or a second emission unit or a second light-emitting electrode assembly) disposed on the first light-emitting element layer LDL1, and a third light-emitting element layer LDL3 (or a third emission unit or a third light-emitting electrode assembly) disposed on the second light-emitting element layer LDL2. However, the light-emitting element layers LDL1, LDL2, and LDL3 are not limited thereto, and the light-emitting element layers LDL1, LDL2, and LDL3 may include two or four or more light-emitting element layers. Hereinafter, the first light-emitting element layer LDL1, the second light-emitting element layer LDL2, and the third light-emitting element layer LDL3 will be described assuming that the light-emitting device EU includes the first light-emitting element layer LDL1, the second light-emitting element layer LDL2, and the third light-emitting element layer LDL3.

[0089] Each of the first light emitting element layer LDL1, the second light emitting element layer LDL2, and the third light emitting element layer LDL3 may include an insulating layer INS, a first electrode ELT1, a second electrode ELT2, and a light emitting element LD. Here, each of the light emitting elements LD may be based on Figures 1a to 3b Since the first light-emitting element layer LDL1, the second light-emitting element layer LDL2, and the third light-emitting element layer LDL3 are substantially the same as or similar to each other, the first light-emitting element layer LDL1, the second light-emitting element layer LDL2, and the third light-emitting element layer LDL3 will be fully described based on the first light-emitting element layer LDL1.

[0090] The first light emitting element layer LDL1 may be disposed on the substrate SUB and may include a first insulating layer INS1 , first and second electrodes ELT1 and ELT2 , and a first light emitting element LD1 .

[0091] The first insulating layer INS1 may be disposed on the substrate SUB and the common electrode layer AEL. For example, the first insulating layer INS1 may cover at least a portion of each of the first and second common electrodes AELT1 and AELT2, or may be disposed on the entire surface of the substrate SUB.

[0092] The first insulating layer INS1 may be formed as a single layer or a multi-layer structure and may include at least one inorganic insulating material and / or at least one organic insulating material. For example, each first insulating layer INS1 may include various types of well-known organic / inorganic insulating materials (including SiN x ), and the material forming the first insulating layer INS1 is not particularly limited.

[0093] The first light emitting element LD1 may be disposed on the first insulating layer INS1 .

[0094] In an embodiment, each of the light emitting elements LD (or the first light emitting element LD1) may be a light emitting diode made of a material having an inorganic crystal structure and having an ultra-small size ranging from a nanometer scale to a micrometer scale. For example, each of the light emitting elements LD may be a Figures 1a to 3b The ultra-small rod-type light-emitting diode shown in any one of the above examples has a size ranging from the nanometer level to the micrometer level. However, the type of light-emitting element LD applicable to the present disclosure is not limited thereto. For example, each of the light-emitting elements LD can be formed by growth and can be, for example, a light-emitting diode having a core-shell structure with a size ranging from the nanometer level to the micrometer level.

[0095] In an embodiment, in a plan view, the light emitting element LD may be disposed between the first common electrode AELT1 and the second common electrode AELT2 facing each other (or between the first electrode ELT1 and the second electrode ELT2). The light emitting element LD may be aligned (or arranged) in the second direction DR2. In other words, the longitudinal direction of the light emitting element LD may be the same as the second direction DR2. However, the alignment direction of the light emitting element LD is not limited thereto. For example, at least one of the light emitting elements LD may be arranged in a diagonal direction.

[0096] In an embodiment, each of the first light emitting element layer LDL1, the second light emitting element layer LDL2 and the third light emitting element layer LDL3 emits monochromatic light, wherein at least some of the first light emitting element layer LDL1, the second light emitting element layer LDL2 and the third light emitting element layer LDL3 can emit light of different colors (or a single color).

[0097] For example, the first light-emitting element layer LDL1 may include first light-emitting elements LD1 that emit light of a first color, the second light-emitting element layer LDL2 may include second light-emitting elements LD2 that emit light of a second color, and the third light-emitting element layer LDL3 may include third light-emitting elements LD3 that emit light of a third color. For example, each of the first light-emitting elements LD1 may be a red light-emitting diode that emits red light, each of the second light-emitting elements LD2 may be a green light-emitting diode that emits green light, and each of the third light-emitting elements LD3 may be a blue light-emitting diode that emits blue light.

[0098] However, the first light-emitting element layer LDL1, the second light-emitting element layer LDL2, and the third light-emitting element layer LDL3 are not limited thereto, and the first light-emitting element layer LDL1, the second light-emitting element layer LDL2, and the third light-emitting element layer LDL3 (or the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3) can emit light of the same color.

[0099] The light emitting elements LD may be coupled to each other in parallel through the first and second electrodes ELT1 and ELT2 in the corresponding light emitting element layers LDL1 , LDL2 , or LDL3 .

[0100] The light emitting element LD may be disposed between the first electrode ELT1 and the second electrode ELT2. In addition, each of the light emitting elements LD may be disposed between the first electrode ELT1, the second electrode ELT2, and the first insulating layer INS1, a first end of each of the light emitting elements LD may be in contact with or coupled to the first electrode ELT1, and a second end of each of the light emitting elements LD may be in contact with or coupled to the second electrode ELT2.

[0101] The light emitting elements LD arranged in the unit emission region may be aggregated to form one light source (or one pixel PXL). In an example, when a driving current flows through the light emitting device EU (or one pixel PXL) during each frame period, the light emitting element LD coupled between the first electrode ELT1 and the second electrode ELT2 of the sub-pixel in the forward direction may emit light having a brightness corresponding to the driving current.

[0102] The first electrode ELT1 and the second electrode ELT2 can be arranged in the unit emission region and can be spaced apart from each other, and can be arranged so that they at least partially face each other. The shapes and arrangement relationship of the first electrode ELT1 and the second electrode ELT2 can be substantially the same as or similar to the shapes and arrangement relationship of the first common electrode AELT1 and the second common electrode AELT2. At least one of the first electrode ELT1 and the second electrode ELT2 can be separated from the first common electrode AELT1 and the second common electrode AELT2 and can be electrically isolated from the first common electrode AELT1 and the second common electrode AELT2 by a first insulating layer INS1 (or insulating layer INS). In this case, when a voltage (e.g., an alternating current (AC) voltage) for aligning the light-emitting element LD is applied to the first common electrode AELT1 and the second common electrode AELT2, the light-emitting element LD connected between the first electrode ELT1 and the second electrode ELT2 can be prevented from being damaged by the voltage. However, the present disclosure is not limited to this, and for example, the first electrode ELT1 can be electrically separated from the first common electrode AELT1, but the second electrode ELT2 can be electrically connected to the second common electrode AELT2.

[0103] According to an embodiment, the first electrode ELT1 may include at least one first sub-electrode ELT_S1 (hereinafter, referred to as the first sub-electrode ELT_S1), and the second electrode ELT2 may include at least one second sub-electrode ELT_S2 (hereinafter, referred to as the second sub-electrode ELT_S2). The first sub-electrode ELT_S1 and the second sub-electrode ELT_S2 may extend in the first direction DR1 in the unit emission region and may be arranged parallel to each other in the second direction DR2 while being spaced apart from each other by a predetermined interval.

[0104] The first sub-electrode ELT_S1 may overlap with the branch electrodes of the first common electrode AELT1, and the second sub-electrode ELT_S2 may overlap with the branch electrodes of the second common electrode AELT2. The first sub-electrode ELT_S1 may have the same line width as the branch electrodes of the first common electrode AELT1 and may completely overlap with the first common electrode AELT1. Similarly, the second sub-electrode ELT_S2 may have the same line width as the branch electrodes of the second common electrode AELT2 and may completely overlap with the second common electrode AELT2.

[0105] According to an embodiment, the first electrode ELT1 may further include a first connection electrode CNL1 coupled to the first sub-electrode ELT_S1. For example, the first connection electrode CNL1 may extend in the second direction DR2 and may be coupled to be integrated with the first sub-electrode ELT_S1. For example, the first sub-electrode ELT_S1 may be formed by branching from the first connection electrode CNL1 into at least one portion. When the first sub-electrode ELT_S1 and the first connection electrode CNL1 are formed to be integrated with each other, the first connection electrode CNL1 may be considered to be a region of the first electrode ELT1. However, the present disclosure is not limited thereto. For example, in another embodiment of the present disclosure, the first sub-electrode ELT_S1 and the first connection electrode CNL1 may be formed separately and then may be electrically coupled to each other through at least one contact hole or through-hole not shown.

[0106] For example, the first connection electrode CNL1 may have a different line width from the first common electrode AELT1 and may partially overlap or may not overlap with the first connection electrode CNL1.

[0107] Similarly, the second electrode ELT2 may further include a second connection electrode CNL2 coupled to the second sub-electrode ELT_S2. Since the arrangement of the second connection electrode CNL2 and its coupling relationship with the second sub-electrode ELT_S2 are substantially the same as those of the first connection electrode CNL1 and its coupling relationship with the first sub-electrode ELT_S1, a repeated description thereof will be omitted. The second connection electrode CNL2 may extend from a corresponding unit emission region to other unit emission regions.

[0108] In an embodiment, the first electrode ELT1 may be formed on a first end of the light emitting element LD and may then be physically and / or electrically coupled to the first end of the light emitting element LD. Similarly, the second electrode ELT2 may be formed on a second end of the light emitting element LD and may then be physically and / or electrically coupled to the second end of the light emitting element LD.

[0109] The first electrode ELT1 and the second electrode ELT2 may include one or more metal materials selected from the group consisting of aluminum (Al), titanium (Ti), indium (In), gold (Au), and silver (Ag), or one or more transparent materials selected from the group consisting of indium tin oxide (ITO), ZnO:Al, and a CNT-conductive polymer composite. When the first electrode ELT1 and the second electrode ELT2 include two or more types of electrode-forming materials, the first electrode ELT1 and the second electrode ELT2 may have a structure in which the two or more types of electrode-forming materials are stacked.

[0110] As referenced above Figures 4 to 6 As described, the light-emitting device EU according to the embodiment of the present disclosure may include a plurality of stacked light-emitting element layers LDL1, LDL2, and LDL3 (or an emission unit or a light-emitting electrode assembly). The emission unit may include light-emitting element layers LDL1, LDL2, and LDL3 having a three-dimensional stacked structure. Therefore, in a limited area (i.e., a unit emission area), the number of light-emitting elements LD installed per unit area can be increased, and the brightness of the light-emitting device EU (or display device) can be improved.

[0111] Furthermore, when the light-emitting element layers LDL1, LDL2, and LDL3 configure red, green, and blue sub-pixels, respectively, a full-color light-emitting device EU can be formed within a single unit emission region within one pixel PXL (i.e., a pixel PXL that emits full-color light). That is, the light-emitting element layers LDL1, LDL2, and LDL3 of different colors are arranged within a limited area (i.e., the unit emission region), thereby realizing a light-emitting device EU (or display device) with high resolution (or high definition).

[0112] Figures 7a to 7i Is used to explain the manufacturing Figure 4 A view of the process of light emitting devices.

[0113] Reference Figure 4 and Figure 7a , the first common electrode AELT1 and the second common electrode AELT2 (or the common electrode layer AEL) may be formed on the substrate SUB (or in the unit emission region of the substrate SUB).

[0114] The area and shape of the substrate SUB are not limited and can be changed by considering the area of ​​the first common electrode AELT1 and the second common electrode AELT2 formed on the substrate SUB, the size of the light emitting element LD, the number of light emitting elements LD to be mounted, etc. The thickness of the substrate SUB can be 100 μm to 1 mm. The area of ​​the first common electrode AELT1 and the second common electrode AELT2 (or the area of ​​the unit electrode) can be 10 μm 2 Up to 100cm 2 .

[0115] Afterwards, if Figure 7b As shown in FIG, a first insulating layer INS1 may be formed on the first common electrode AELT1 and the second common electrode AELT2.

[0116] According to an embodiment, the first insulating layer INS1 may be formed by any one of plasma enhanced chemical vapor deposition (PECVD), electron beam deposition, atomic layer deposition, and sputtering deposition, but the present disclosure is not limited thereto.

[0117] The first insulating layer INS1 may include a layer selected from SiO2, Si3N4, SiN x , Al2O3, HfO2, Y2O3, and TiO2. Furthermore, the first insulating layer INS1 may have a thickness of 1 nm to 100 μm, and may vary depending on a voltage (e.g., an alignment voltage) of a power source applied to the first and second common electrodes AELT1 and AELT2, a length of the light emitting element LD, a distance between the first and second common electrodes AELT1 and AELT2, and the like.

[0118] Afterwards, if Figure 7c As shown in FIG, the first light emitting element LD1 may be prepared in the form of being diffused in the first solution SOL1, and may be disposed on the first insulating layer INS1.

[0119] The first solution SOL1 can be produced by mixing the first light-emitting elements LD1 with a dispersion solvent. The dispersion solvent can be in the form of ink or paste, and the solvent can be selected from at least one of acetone, water, alcohol, and toluene as a volatile solvent. However, the type of dispersion solvent is not limited to the above types, and any type of solvent can be used without restriction, as long as the solvent can evaporate satisfactorily without exerting physical and chemical effects on the first light-emitting elements LD1. The first solution SOL1 can include the first light-emitting elements LD1 corresponding to 0.001 to 100% by weight of the weight of the dispersion solvent. When the first solution SOL1 includes less than 0.001% by weight of the first light-emitting elements LD1, the number of first light-emitting elements LD1 coupled to electrodes (e.g., the first electrode ELT1 and the second electrode ELT2) may be small. In contrast, when the first solution SOL1 includes more than 100% by weight of the first light-emitting elements LD1, alignment between the first light-emitting elements LD1 may be hindered.

[0120] Therefore, if Figure 7d As shown in FIG, when a predetermined voltage is applied to the first and second common electrodes AELT1 and AELT2, an electric field is formed between the first and second common electrodes AELT1 and AELT2, and then the first light emitting element LD1 can be self-aligned between the first and second common electrodes AELT1 and AELT2 in a plan view. When the first light emitting element LD1 has been aligned, the solvent is volatilized or removed using another additional method, and thus the light emitting element LD can be stably arranged on the first insulating layer INS1.

[0121] For example, when a first voltage V1 is applied between the first common electrode AELT1 and the second common electrode AELT2, an electric field may be formed between the first common electrode AELT1 and the second common electrode AELT2, thereby generating polarization in the first light-emitting element LD1. Consequently, the first light-emitting element LD1 may be arranged with a directional bias due to the electrostatic attraction between adjacent common electrodes AELT1 or AELT2. When the first common electrode AELT1 is positive and the second common electrode AELT2 is negative, the first end of the first light-emitting element LD1, which has a negative charge, may be positioned on the first insulating layer INS1 based on the position of the first common electrode AELT1, and the second end of the first light-emitting element LD1, which has a positive charge, may be positioned on the first insulating layer INS1 based on the position of the second common electrode AELT2.

[0122] In an embodiment, the first voltage V1 may have a voltage level of 0.1V to 2000V. When the voltage level of the first voltage V1 is less than 0.1V, the alignment efficiency of the first light-emitting element LD1 may deteriorate. When the voltage level of the first voltage V1 is greater than 2000V, the first insulating layer INS1 may be damaged, and leakage current, electrical short circuit, or electrode damage may occur. Furthermore, the frequency of the first voltage V1 may be in the range of 10Hz to 100GHz, and the first voltage V1 may be, for example, a sine wave with a frequency of 90kHz to 100MHz. When the frequency is less than 10Hz, the number of installed first light-emitting elements LD1 may be significantly reduced, and the orientation of the first light-emitting elements LD1 may be highly irregular. When the frequency is greater than 100GHz, the first light-emitting element LD1 is not adaptable to rapidly changing AC power, and thus the mountability of the first light-emitting element LD1 may be reduced, and the orientation bias may also be reduced.

[0123] Afterwards, if Figure 7e As shown in FIG, the first electrode ELT1 and the second electrode ELT2 may be formed on opposite ends of each of the first light emitting elements LD1. The first light emitting element LD1 may be stably coupled between the first electrode ELT1 and the second electrode ELT2. Figures 8a to 8e A process of forming the first electrode ELT1 and the second electrode ELT2 is described.

[0124] Afterwards, if Figure 7f As shown in FIG, a second insulating layer INS2 may be formed on the first light emitting element layer LDL1 (i.e., the first insulating layer INS1, the first light emitting element LD1, and the first and second electrodes ELT1 and ELT2). A method of forming the second insulating layer INS2 may be substantially the same as or similar to the method of forming the first insulating layer INS1.

[0125] Afterwards, if Figure 7g As shown in FIG, the second light emitting element LD2 may be prepared in a diffused form in the second solution SOL2, and then the second light emitting element LD2 may be disposed on the second insulating layer INS2. Figure 7h As shown in , when the second voltage V2 is supplied to the first common electrode AELT1 and the second common electrode AELT2, an electric field is formed between the first common electrode AELT1 and the second common electrode AELT2, and then the second light emitting element LD2 can be self-aligned between the first common electrode AELT1 and the second common electrode AELT2 in a plan view. Thereafter, as Figure 7i As shown in FIG, the first electrode ELT1 and the second electrode ELT2 may be formed on opposite ends of each of the second light emitting elements LD2, respectively.

[0126] That is, it can be repeated once to form Figures 7b to 7e The first light emitting element layer LDL1 shown in FIG. Figure 5 ) process, and thereby the second light emitting element layer LDL2 can be formed (see Figure 5 ). Similarly, the formation can be repeated once more. Figures 7f to 7i The second light emitting element layer LDL2 shown in FIG. Figure 5 ) process, and thereby the third light emitting element layer LDL3 can be formed (see Figure 5 ).

[0127] In an embodiment, the second voltage V2 applied to the first and second common electrodes AELT1 and AELT2 when forming the second light-emitting element layer LDL2 may have a higher voltage level and / or frequency than the first voltage V1 applied to the first and second common electrodes AELT1 and AELT2 when forming the first light-emitting element layer LDL1. That is, since the electric field may be relatively reduced when forming the second light-emitting element layer LDL2, the reduction in the electric field may be compensated by increasing the voltage level and / or frequency of the second voltage V2, and the number of second light-emitting elements LD2 mounted on the second light-emitting element layer LDL2 may be adjusted to the number of first light-emitting elements LD1. Similarly, the third voltage (not shown) applied to the first and second common electrodes AELT1 and AELT2 when forming the third light-emitting element layer LDL3 may have a higher voltage level and / or frequency than the second voltage V2 applied to the first and second common electrodes AELT1 and AELT2 when forming the second light-emitting element layer LDL2. However, the present disclosure is not limited thereto, and the first voltage V1 , the second voltage V2 , and the third voltage may have the same voltage level and / or frequency.

[0128] Figures 8a to 8e It is used to explain the formation Figure 7e A view of the process of the first electrode and the second electrode. Figures 8a to 8e The process of forming the first electrode ELT1 and the second electrode ELT2 in the embodiment is applicable to each of the first light-emitting element layer LDL1, the second light-emitting element layer LDL2 and the third light-emitting element layer LDL3, so the configuration (for example, the substrate SUB, the additional light-emitting element layer, etc.) provided below the first electrode ELT1 and the second electrode ELT2 is not limited to the configuration (for example, the substrate SUB, the additional light-emitting element layer, etc.) Figures 8a to 8e It is simply shown as a common electrode layer AEL.

[0129] First, refer to Figure 7e and Figure 8a , a common electrode layer AEL having a light emitting element LD aligned on one surface thereof may be prepared.

[0130] like Figure 8bAs shown in , the common electrode layer AEL may be coated with a photoresist, or alternatively, a photoresist layer PR may be formed on the common electrode layer AEL. The photoresist layer PR may include a photoresist commonly used in the art. The common electrode layer AEL may be coated with the photoresist by any one of spin coating, spray coating, and screen printing. The thickness of the photoresist layer PR may be varied by considering the thickness of the first electrode ELT1 and the second electrode ELT2 to be formed on the common electrode layer AEL, and the thickness of the photoresist layer PR may be, for example, 0.1 μm to 10 μm. However, the present disclosure is not limited thereto.

[0131] Afterwards, if Figure 8c As shown in FIG, a mask MASK in which patterns corresponding to the first and second electrodes ELT1 and ELT2 are printed may be provided on the photoresist layer PR, and a top of the mask MASK may be exposed to ultraviolet UV (or ultraviolet radiation).

[0132] Afterwards, if Figure 8d As shown in FIG, the photoresist layer PR is immersed in a typical photoresist solvent, so that the exposed portion of the photoresist layer PR can be removed. That is, the portion of the photoresist layer PR in which the first electrode ELT1 and the second electrode ELT2 are to be formed can be removed.

[0133] Afterwards, if Figure 8e As shown in FIG, an electrode forming material M_ELT may be deposited on the photoresist layer PR. The electrode forming material M_ELT may be the same as the material forming the first electrode ELT1 and the second electrode ELT2.

[0134] After the electrode forming material M_ELT has been deposited, the photoresist layer PR formed on the common electrode layer AEL can be removed using a photoresist remover. Here, the photoresist remover can be any one of acetone, N-methylpyrrolidone (1-methyl-2-pyrrolidone (NMP)) and dimethyl sulfoxide (DMSO).

[0135] As the photoresist layer PR is removed, the first electrode ELT1 and the second electrode ELT2 may be formed on the common electrode layer AEL.

[0136] At the same time, despite Figures 8a to 8e Schematic diagram showing the manufacturing of the first electrode ELT1 and the second electrode ELT2 , but the present disclosure is not limited thereto. Figures 8a to 8e The manufacturing method in FIG. 4 can also be applied to the first common electrode AELT1 and the second common electrode AELT2. That is, the first common electrode AELT1 and the second common electrode AELT2 and the first electrode ELT1 and the second electrode ELT2 can be formed using the same manufacturing method.

[0137] Figure 91 is a plan view showing a display device according to an embodiment of the present disclosure. Figure 9 In the embodiment, a display device, particularly a display panel PNL provided in the display device is shown as a reference. Figures 1a to 3b The light emitting element LD described or reference Figure 4 The light emitting device EU is described as an example of a device of a light source. According to the embodiment, Figure 9 The structure of the display panel PNL is briefly shown based on the display area DA. However, in some embodiments, at least one driving circuit (eg, at least one of a scan driver and a data driver) and / or a plurality of lines not shown may be further provided on the display panel PNL.

[0138] Reference Figure 9 The display panel PNL may include a substrate SUB and pixels PXL disposed on the substrate SUB. In detail, the display panel PNL and the substrate SUB may include a display area DA in which an image is displayed, and a non-display area NDA other than the display area DA.

[0139] In an embodiment, the display area DA may be provided in the center portion of the display panel PNL, and the non-display area NDA may be provided along the peripheral portion of the display panel PNL in a manner surrounding the display area DA. However, the positions of the display area DA and the non-display area NDA are not limited thereto and may also be changed.

[0140] The substrate SUB may form a base member for the display panel PNL. For example, the substrate SUB may form a base member for the lower panel (eg, the lower plate of the display panel PNL). Figure 4 The described substrate SUB is substantially the same or similar, and thus repeated description thereof will be omitted.

[0141] An area on the substrate SUB is defined as a display area DA in which the pixels PXL are disposed, and the remaining area thereof is defined as a non-display area NDA. For example, the substrate SUB may include a display area DA including a plurality of pixel regions in which the pixels PXL (or pixels PXL1, PXL2, and PXL3) are formed, and a non-display area NDA disposed around the display area DA. Various lines and / or internal circuits connected to the pixels PXL in the display area DA may be disposed in the non-display area NDA.

[0142] Each pixel PXL may include at least one light emitting element LD driven in response to a corresponding scan signal and a corresponding data signal, for example, according to Figures 1a to 3b The at least one rod-type light emitting diode of any one of the embodiments of the present invention may form a light source of the pixel PXL.

[0143] In addition, the pixel PXL may include a light emitting element layer having a 3D structure. For example, the pixel PXL may have the same structure as that of the above reference Figure 4 The described light-emitting devices EU have essentially the same structure.

[0144] Despite Figure 9 , an embodiment in which the pixels PXL are arranged in the display area DA in the form of stripes is shown, but the present disclosure is not limited thereto. For example, the pixels PXL may be arranged in the form of various well-known pixel arrays.

[0145] In an embodiment, the pixel PXL may be configured as an active pixel. However, the type, structure, and / or driving scheme of the pixel PXL applicable to the display device according to the present disclosure are not particularly limited. For example, each pixel PXL may be implemented as a pixel of a display device having various well-known passive or active structures.

[0146] Figures 10a to 10c It is shown that the Figure 9 A circuit diagram of an example of a pixel in a display device. Figures 10a to 10c , different embodiments of a pixel PXL that may be provided in an active display device (eg, an active light emitting display device) are shown.

[0147] First, refer to Figure 10a , the pixel PXL may include an emission unit LSU and a pixel circuit PXC for driving the emission unit LSU. Figure 4 Multiple light-emitting element layers are described (for example, a first light-emitting element layer LDL1, a second light-emitting element layer LDL2, and a third light-emitting element layer LDL3), so the pixel PXL may include multiple emission units corresponding to the light-emitting element layers and multiple pixel circuits (for example, three pixel circuits) for driving the emission units (for example, the first light-emitting element layer LDL1, the second light-emitting element layer LDL2, and the third light-emitting element layer LDL3) independently of each other.

[0148] In an embodiment, the emission unit LSU may include a plurality of light-emitting elements LD coupled in parallel between a first power supply VDD and a second power supply VSS. Here, the first power supply VDD and the second power supply VSS may have different potentials. For example, the first power supply VDD may be set as a high-potential power supply, and the second power supply VSS may be set as a low-potential power supply. Here, the potential difference between the first power supply VDD and the second power supply VSS may be set to a threshold voltage or greater than the threshold voltage of the light-emitting element LD during at least one light emission period of the pixel PXL.

[0149] At the same time, despite Figure 10a, the light-emitting elements LD are shown as being connected in parallel with each other in the same direction (e.g., a forward direction) between the first power supply VDD and the second power supply VSS, but the present disclosure is not limited thereto. For example, some of the light-emitting elements LD may be connected in the forward direction between the first power supply VDD and the second power supply VSS, and other light-emitting elements LD may be connected in the reverse direction. In another example, at least one pixel PXL may include only a single light-emitting element LD.

[0150] In an embodiment, a first end of each light emitting element LD may be commonly coupled to a corresponding pixel circuit PXC via a first electrode, and may be commonly coupled to a first power supply VDD via the pixel circuit PXC and a first power line PL1. A second end of each light emitting element LD may be commonly coupled to a second power supply VSS via a second electrode and a second power line PL2.

[0151] The emission unit LSU may emit light having a brightness corresponding to a driving current applied thereto through the corresponding pixel circuit PXC. Thus, a predetermined image may be displayed in the display area DA.

[0152] The pixel circuit PXC can be coupled to the scan line Si and the data line Dj of the corresponding pixel PXL. For example, when the pixel PXL is arranged in the i-th row and the j-th column of the display area DA, the pixel circuit PXC of the pixel PXL can be coupled to the i-th scan line Si and the j-th data line Dj of the display area DA. The pixel circuit PXC may include a first transistor T1 and a second transistor T2, and a storage capacitor Cst.

[0153] The first transistor T1 (or driving transistor) may be coupled between a first power supply VDD and a first electrode of the firing unit LSU. A gate electrode of the first transistor T1 is coupled to a first node N1. The first transistor T1 may control a driving current provided to the firing unit LSU in response to a voltage at the first node N1.

[0154] The second transistor T2 (or switching transistor) may be coupled between the data line Dj and the first node N1. A gate electrode of the second transistor T2 may be coupled to the scan line Si.

[0155] When a scan signal having a gate-on voltage (e.g., a low voltage) is supplied from the scan line Si, the second transistor T2 is turned on, thereby electrically coupling the data line Dj and the first node N1 to each other. During each frame period, a data signal of a corresponding frame is supplied to the data line Dj and may be transmitted to the first node N1 via the second transistor T2. Thus, a voltage corresponding to the data signal is charged into the storage capacitor Cst.

[0156] A first electrode of the storage capacitor Cst may be coupled to the first power source VDD, and a second electrode thereof may be coupled to the first node N1. The storage capacitor Cst may charge a voltage corresponding to a data signal supplied to the first node N1 during each frame period and may maintain the charged voltage until a data signal of a subsequent frame is supplied.

[0157] Despite Figure 10a In the embodiment of the present invention, all of the transistors (eg, the first transistor T1 and the second transistor T2) included in the pixel circuit PXC have been shown as P-type transistors, but the present disclosure is not limited thereto. In other words, at least one of the first transistor T1 and the second transistor T2 may be changed to an N-type transistor.

[0158] For example, Figure 10b As shown in FIG, both the first transistor T1 and the second transistor T2 can be N-type transistors. Except that the connection positions of some circuit elements are changed according to the change of transistor types, Figure 10b The pixel PXL shown in FIG may have Figure 10a The configuration and operation of the pixel PXL are substantially similar to those of the pixel PXL. Therefore, the description of Figure 10b Description of the pixel PXL.

[0159] Meanwhile, the structure of the pixel circuit PXC is not limited to Figure 10a and Figure 10b That is, the pixel circuit PXC can be implemented as a pixel circuit having various well-known structures and / or driving schemes. In an example, the pixel circuit PXC can be as follows Figure 10c The embodiment shown in FIG.

[0160] refer to Figure 10c , the pixel circuit PXC may also be coupled to at least one additional scan line (or control line) in addition to the scan line Si for the corresponding horizontal line. For example, the pixel circuit PXC of the pixel PXL arranged in the i-th row of the display area DA may also be coupled to the (i-1)th scan line Si-1 and / or the (i+1)th scan line Si+1. In addition, according to an embodiment, the pixel circuit PXC may also be coupled to other power supplies in addition to the first power supply VDD and the second power supply VSS. For example, the pixel circuit PXC may also be coupled to an initialization power supply Vint. According to an embodiment, the pixel circuit PXC may include first to seventh transistors T1 to T7 and a storage capacitor Cst.

[0161] The first transistor T1 may be coupled between the first power supply VDD and the first electrode of the firing unit LSU. A gate electrode of the first transistor T1 may be coupled to the first node N1. The first transistor T1 may control a driving current provided to the firing unit LSU in response to a voltage of the first node N1.

[0162] The second transistor T2 may be coupled between the data line Dj and the first electrode of the first transistor T1. The gate electrode of the second transistor T2 may be coupled to the corresponding scan line Si. When a scan signal having a gate-on voltage is supplied from the scan line Si, the second transistor T2 may be turned on, thereby electrically coupling the data line Dj to the first electrode of the first transistor T1. Therefore, when the second transistor T2 is turned on, the data signal supplied from the data line Dj may be transmitted to the first transistor T1.

[0163] The third transistor T3 may be coupled between the second electrode of the first transistor T1 and the first node N1. A gate electrode of the third transistor T3 may be coupled to a corresponding scan line Si. When a scan signal having a gate-on voltage is supplied from the scan line Si, the third transistor T3 may be turned on, thereby being coupled to the first transistor T1 in the form of a diode.

[0164] The fourth transistor T4 may be coupled between the first node N1 and the initialization power supply Vint. A gate electrode of the fourth transistor T4 may be coupled to a previous scan line, for example, the (i-1)th scan line Si-1. When a scan signal having a gate-on voltage is supplied to the (i-1)th scan line Si-1, the fourth transistor T4 may be turned on, thereby transmitting the voltage of the initialization power supply Vint to the first node N1. Here, the voltage of the initialization power supply Vint may be less than or equal to the lowest voltage of the data signal.

[0165] The fifth transistor T5 may be coupled between the first power supply VDD and the first transistor T1. A gate electrode of the fifth transistor T5 may be coupled to a corresponding emission control line, for example, the i-th emission control line Ei. When an emission control signal having a gate-off voltage (for example, a high voltage) is supplied to the emission control line Ei, the fifth transistor T5 may be turned off, and in the remaining cases, the fifth transistor T5 may be turned on.

[0166] The sixth transistor T6 may be coupled between the first transistor T1 and the first electrode of the emission unit LSU (e.g., the second node N2). The gate electrode of the sixth transistor T6 may be coupled to a corresponding emission control line, e.g., the i-th emission control line Ei. When an emission control signal having a gate-off voltage is supplied to the emission control line Ei, the sixth transistor T6 may be turned off, and may be turned on otherwise.

[0167] The seventh transistor T7 can be coupled between the first electrode of the emission unit LSU and the initialization power supply Vint. The gate electrode of the seventh transistor T7 can be coupled to any one of the scan lines in the subsequent stage, for example, the (i+1)th scan line Si+1. When a scan signal having a gate-on voltage is supplied to the (i+1)th scan line Si+1, the seventh transistor T7 can be turned on, thereby supplying the voltage of the initialization power supply Vint to the first electrode of the emission unit LSU.

[0168] The storage capacitor Cst may be coupled between the first power source VDD and the first node N1 and may store a voltage corresponding to the data signal supplied to the first node N1 and the threshold voltage of the first transistor T1 during each frame period.

[0169] Despite Figure 10c In the embodiment of the present invention, the transistors (e.g., the first transistor T1 to the seventh transistor T7) included in the pixel circuit PXC have been shown as P-type transistors, but the present disclosure is not limited thereto. For example, at least one of the first transistor T1 to the seventh transistor T7 may be changed to an N-type transistor. In addition, in this case, the voltage level of the control signal (e.g., the scan signal and / or the data signal) used to control at least one of the first transistor T1 to the seventh transistor T7 may be changed.

[0170] In addition, the structure of the pixel PXL applicable to the present disclosure is not limited to Figures 10a to 10c , and the pixel PXL may have various well-known structures. For example, the pixel circuit PXC included in the pixel PXL may be implemented as a pixel circuit having various well-known structures and / or driving schemes. In addition, in other embodiments of the present disclosure, the pixel PXL may be configured in a passive light-emitting display device or the like. In this case, the pixel circuit PXC may be omitted, and each of the first and second electrodes of the emission unit LSU may be directly connected to the scan line Si, the data line Dj, the power line, and / or the control line.

[0171] Figure 11 It shows Figure 9 A cross-sectional view of an example of a display device.

[0172] Reference Figure 9 and Figure 11 The display device (or display panel PNL) may include a substrate SUB, a pixel circuit layer PCL, a common electrode layer AEL, and a plurality of light emitting element layers LDL1, LDL2, and LDL3. Since the substrate SUB, the common electrode layer AEL, and the light emitting element layers LDL1, LDL2, and LDL3 may be the same as those in the above reference Figures 4 to 6The described substrate SUB, common electrode layer AEL, and light emitting element layers LDL1, LDL2, and LDL3 are substantially the same, so repeated descriptions thereof will be omitted.

[0173] The pixel circuit layer PCL may be provided between the substrate SUB and the light emitting element layers LDL1, LDL2 and LDL3, or between the substrate SUB and the common electrode layer AEL. The pixel circuit layer PCL may include the above reference Figures 10a to 10c The pixel circuit PXC is described.

[0174] exist Figure 11 In the embodiment, although the pixel circuit layer PCL is shown as being disposed between the substrate SUB and the light-emitting element layers LDL1, LDL2, and LDL3, the present disclosure is not limited thereto. For example, the pixel circuit layer PCL may be disposed above the substrate SUB and the light-emitting element layers LDL1, LDL2, and LDL3, as well as a transmissive member (or opening) for transmitting light emitted from the light-emitting element layers LDL1, LDL2, and LDL3 in the third direction DR3. That is, the arrangement of the pixel circuit layer PCL may be modified in various ways.

[0175] Figures 12a to 12c It is shown that the Figure 9 A plan view of an example of a pixel in a display device. Figures 12a to 12c , the structure of the pixel PXL is shown based on the light emitting element layer on which the light emitting element LD of the pixel PXL is arranged. Figure 11 The first light emitting element layer LDL1 is described in Figure 12a As shown in FIG, the second light emitting element layer LDL2 is Figure 12b As shown in FIG, and the third light emitting element layer LDL3 is Figure 12c Shown in.

[0176] Reference Figure 9 as well as Figures 12a to 12c , the pixel PXL may be formed in a pixel area PXA defined on a substrate SUB. The pixel area PXA may include an emission area EMA in which at least one pair of first and second electrodes ELT1 and ELT2 and at least one light emitting element LD coupled between the first and second electrodes ELT1 and ELT2 are arranged. The emission area EMA may be formed by a pixel defining layer (e.g., bank patterns PW1, PW2, see Figure 16 )limited.

[0177] The pixel PXL may include a first pixel circuit PXC1, a second pixel circuit PXC2, and a third pixel circuit PXC3 corresponding to the first light emitting element layer LDL1, the second light emitting element layer LDL2, and the third light emitting element layer LDL3, respectively. Although the first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3 may be sequentially arranged in the pixel area PXA along the first direction DR1, this arrangement is merely exemplary, and the arrangement of the pixel circuits PXC1, PXC2, and PXC3 is not limited thereto. According to an embodiment, the first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3 may be formed as described above with reference to FIG. Figure 11 The pixel circuit layer PCL (or the circuit element layer including circuit elements such as transistors) is described.

[0178] like Figure 12a As shown in FIG, in the pixel area PXA (or emission area EMA) of the first light emitting element layer LDL1, the pixel PXL may include a first electrode ELT1 and a second electrode ELT2 arranged to be spaced apart from each other, and a first light emitting element LD1 coupled between the first electrode ELT1 and the second electrode ELT2. Since the first electrode ELT1 and the second electrode ELT2 and the first light emitting element LD1 are respectively connected to the above reference Figure 4 The described first and second electrodes ELT1 and ELT2 and the first light emitting element LD1 are substantially the same or similar, and thus repeated description thereof will be omitted.

[0179] In an embodiment, the first electrode ELT1 of the first light emitting element layer LDL1 may include a first protrusion ELT_P1 formed to protrude from a portion of the first electrode ELT1 corresponding to the first pixel circuit PXC1 to a non-emission region (ie, outside the emission region EMA).

[0180] The first electrode ELT1 may be coupled to the first pixel circuit PXC1 through the first protrusion ELT_P1 and the first contact hole CH1. Figures 10a to 10c In an embodiment, the first contact hole CH1 may be disposed outside the emission area EMA. However, the present disclosure is not limited thereto, and in an example, the first contact hole CH1 may be disposed inside the emission area EMA.

[0181] According to an embodiment, the pixel PXL may further include bridge patterns BRP1 and BRP2 disposed in the pixel area PXA of the first light-emitting element layer LDL1. For example, the pixel PXL may further include a first bridge pattern BRP1 and a second bridge pattern BRP2. The first bridge pattern BRP1 may be disposed to correspond to the second pixel circuit PXC2 in the non-emission region of the pixel PXL and may be spaced apart from the first and second electrodes ELT1 and ELT2. The first bridge pattern BRP1 may be used to couple the first electrode ELT1 of the second light-emitting element layer LDL2 to the second pixel circuit PXC2. Similar to the first bridge pattern BRP1, the second bridge pattern BRP2 may be disposed to correspond to the third pixel circuit PXC3 in the non-emission region of the pixel PXL and may be spaced apart from the first and second electrodes ELT1 and ELT2. The second bridge pattern BRP2 may be used to couple the first electrode ELT1 of the third light-emitting element layer LDL3 to the third pixel circuit PXC3. In an embodiment, at least one of the first and second bridge patterns BRP1 and BRP2 may be omitted.

[0182] In an embodiment, the second electrode ELT2 may be coupled to a power source (eg, reference numeral 20) through the second contact hole CH2 and a power line (not shown) coupled thereto. Figure 10a In an embodiment, the second contact hole CH2 may be disposed outside the emission area EMA of the pixel PXL. However, the present disclosure is not limited thereto, and the second contact hole CH2 may be disposed inside the emission area EMA.

[0183] like Figure 12b As shown in FIG, in the pixel area PXA (or emission area EMA) of the second light emitting element layer LDL2, the pixel PXL may include a first electrode ELT1 and a second electrode ELT2 arranged to be spaced apart from each other, and a second light emitting element LD2 coupled between the first electrode ELT1 and the second electrode ELT2. Since the first electrode ELT1 and the second electrode ELT2 and the second light emitting element LD2 are similar to those in the above reference Figure 5 The described first and second electrodes ELT1 and ELT2 and the second light emitting element LD2 are substantially the same or similar, and thus repeated description thereof will be omitted.

[0184] In an embodiment, the first electrode ELT1 of the second light-emitting element layer LDL2 may include a second protrusion ELT_P2. The second protrusion ELT_P2 may be formed to protrude from a portion of the first electrode ELT1 corresponding to the second pixel circuit PXC2 to a non-emission region (i.e., to the outside of the emission region EMA). In addition, the second protrusion ELT_P2 may overlap with the first bridge pattern BRP1 of the first light-emitting element layer LDL1 and may be coupled to the first bridge pattern BRP1 of the first light-emitting element layer LDL1 through the third contact hole CH3. That is, the first electrode ELT1 of the second light-emitting element layer LDL2 may be coupled to the second pixel circuit PXC2 through the second protrusion ELT_P2, the third contact hole CH3, and the first bridge pattern BRP1 of the first light-emitting element layer LDL1, for example. Figures 10a to 10c The pixel circuit PXC shown in any one of .

[0185] According to an embodiment, the pixel PXL may further include at least one second bridge pattern BRP2 disposed in the pixel area PXA of the second light-emitting element layer LDL2. For example, the pixel PXL may further include the second bridge pattern BRP2, wherein the second bridge pattern BRP2 may be disposed to correspond to the third pixel circuit PXC3 in the non-emission area of ​​the pixel PXL and may be spaced apart from the first electrode ELT1 and the second electrode ELT2. Furthermore, the second bridge pattern BRP2 of the second light-emitting element layer LDL2 may overlap with the second bridge pattern BRP2 of the first light-emitting element layer LDL1. The second bridge pattern BRP2 may be used to couple the first electrode ELT1 of the third light-emitting element layer LDL3 to the third pixel circuit PXC3.

[0186] like Figure 12c As shown in FIG, in the pixel area PXA (or emission area EMA) of the third light emitting element layer LDL3, the pixel PXL may include a first electrode ELT1 and a second electrode ELT2 arranged to be spaced apart from each other, and a third light emitting element LD3 coupled between the first electrode ELT1 and the second electrode ELT2. Since the first electrode ELT1 and the second electrode ELT2 and the third light emitting element LD3 are similar to those in the above reference Figure 5 The described first and second electrodes ELT1 and ELT2 and the third light emitting element LD3 are substantially the same or similar, and thus repeated description thereof will be omitted.

[0187] In an embodiment, the first electrode ELT1 of the third light-emitting element layer LDL3 may include a third protrusion ELT_P3. The third protrusion ELT_P3 may be formed to protrude from a portion of the first electrode ELT1 corresponding to the third pixel circuit PXC3 to a non-emission region (i.e., to the outside of the emission region EMA). In addition, the third protrusion ELT_P3 may overlap with the second bridge pattern BRP2 of the second light-emitting element layer LDL2 and may be coupled to the second bridge pattern BRP2 of the second light-emitting element layer LDL2 through a fourth contact hole CH4. That is, the first electrode ELT1 of the third light-emitting element layer LDL3 may be coupled to the third pixel circuit PXC3 through the third protrusion ELT_P3, the fourth contact hole CH4, and the second bridge pattern BRP2 of the second light-emitting element layer LDL2 (and the second bridge pattern BRP2 of the first light-emitting element layer LDL1), for example. Figures 10a to 10c The pixel circuit PXC shown in any one of .

[0188] Figure 13 is shown along Figure 12c A cross-sectional view of an example of a pixel taken along line II-II'.

[0189] Reference Figure 9 、 Figure 11 、 Figure 12c and Figure 13 The pixel circuit layer PCL and the light emitting element layers LDL1, LDL2, and LDL3 may be sequentially arranged in the pixel area PXA of the substrate SUB. In an embodiment, a common electrode layer AEL may be further provided between the pixel circuit layer PCL and the first light emitting element layer LDL1.

[0190] In an embodiment, the pixel circuit layer PCL and the light emitting element layers LDL1 , LDL2 , and LDL3 may be formed on the entire surface of the display area DA of the display panel PNL.

[0191] In an embodiment, the pixel circuit layer PCL may include circuit elements forming the pixel circuit PXC of the pixel PXL.

[0192] For example, the pixel circuit layer PCL may include a plurality of transistors arranged in the pixel area PXA, for example, Figure 10a and Figure 10b The first transistor T1. Although Figure 13 , but the pixel circuit layer PCL may include a storage capacitor Cst disposed in the pixel region PXA, various types of signal lines (eg, Figure 10a and Figure 10b scanning lines Si and data lines Dj), and various types of power lines (eg, Figures 10a to 10c , for transmitting the first power source VDD and the second power source VSS, respectively).

[0193] In an embodiment, the pixel circuit layer PCL may have a cross-sectional structure substantially the same as or similar to the cross-sectional structure of the plurality of transistors (e.g., the first transistor T1) provided in the pixel circuit PXC. However, the present disclosure is not limited thereto, and in other embodiments, at least some of the plurality of transistors may have different types and / or structures.

[0194] In addition, the pixel circuit layer PCL may include a plurality of insulating layers. For example, the pixel circuit layer PCL may include a buffer layer BFL, a gate insulating layer GI, an interlayer insulating layer ILD, and a passivation layer PSV sequentially stacked on one surface of the substrate SUB.

[0195] In embodiments, the buffer layer (BFL) can prevent impurities from diffusing into circuit components. The buffer layer (BFL) can be configured as a single-layer structure, but can also be configured as a multilayer structure having two or more layers. When the buffer layer (BFL) is configured as a multilayer structure, each layer can be formed of the same material or different materials. Depending on the embodiment, the buffer layer (BFL) can be omitted.

[0196] In an embodiment, the first transistor T1 may include a semiconductor layer SCL, a gate electrode GE, a first transistor electrode ET1, and a second transistor electrode ET2. Meanwhile, according to an embodiment, although Figure 13 In the embodiment, the first transistor T1 is shown as having a first transistor electrode ET1 and a second transistor electrode ET2 formed separately from the semiconductor layer SCL, but the present disclosure is not limited thereto. For example, in another embodiment of the present disclosure, the first transistor electrode ET1 and / or the second transistor electrode ET2 provided in at least one transistor arranged in the pixel area PXA may be configured to be integrated with the corresponding semiconductor layer SCL.

[0197] The semiconductor layer SCL may be disposed on the buffer layer BFL. For example, the semiconductor layer SCL may be disposed between the substrate SUB on which the buffer layer BFL is formed and the gate insulating layer GI. The semiconductor layer SCL may include a first region in contact with the first transistor electrode ET1, a second region in contact with the second transistor electrode ET2, and a channel region disposed between the first region and the second region. In an embodiment, one of the first region and the second region may be a source region, and the other may be a drain region.

[0198] In an embodiment, the semiconductor layer SCL may be a semiconductor pattern formed of polycrystalline silicon, amorphous silicon, an oxide semiconductor, etc. In addition, the channel region of the semiconductor layer SCL may be an intrinsic semiconductor as a semiconductor pattern not doped with impurities, and the first and second regions of the semiconductor layer SCL may be semiconductor patterns doped with predetermined impurities.

[0199] The gate electrode GE may be disposed on the semiconductor layer SCL with the gate insulating layer GI interposed therebetween. For example, the gate electrode GE may be disposed between the gate insulating layer GI and the interlayer insulating layer ILD to overlap at least a portion of the semiconductor layer SCL.

[0200] The first transistor electrode ET1 and the second transistor electrode ET2 may be disposed on the semiconductor layer SCL and the gate electrode GE with at least one interlayer insulating layer ILD interposed therebetween. For example, the first transistor electrode ET1 and the second transistor electrode ET2 may be interposed between the interlayer insulating layer ILD and the passivation layer PSV. The first transistor electrode ET1 and the second transistor electrode ET2 may be electrically coupled to the semiconductor layer SCL. For example, the first transistor electrode ET1 and the second transistor electrode ET2 may be coupled to the first region and the second region of the semiconductor layer SCL, respectively, via contact holes passing through the gate insulating layer GI and the interlayer insulating layer ILD.

[0201] Meanwhile, according to an embodiment, at least one transistor (eg, Figure 10a and Figure 10b Any one of the first transistor electrode ET1 and the second transistor electrode ET2 of the first transistor T1 shown in FIG may be electrically coupled to the bridge electrode ELT_BRP disposed on the top of the passivation layer PSV through a fifth contact hole CH5 passing through the passivation layer PSV.

[0202] In an embodiment, at least one signal line and / or power line coupled to the pixel PXL may be provided on the same layer as the first electrode of the circuit elements forming the pixel circuit PXC. For example, the power line PL (e.g., the second power line PL2 for providing the second power supply VSS) may be provided on the same layer as the gate electrode GE of the first transistor T1 and may be coupled to the second common electrode AELT2 provided on top of the passivation layer PSV via a bridge pattern BRP provided on the same layer as the first transistor electrode ET1 and the second transistor electrode ET2 and at least one second contact hole CH2 passing through the passivation layer PSV. However, the structure and / or position of the power line PL may be varied in various ways.

[0203] The common electrode layer AEL may include a first common electrode AELT1 and a second common electrode AELT2. Figure 6 The described first common electrode AELT1 and the second common electrode AELT2 are substantially the same, and thus repeated description thereof will be omitted.

[0204] The common electrode layer AEL may further include a bridge electrode ELT_BRP. The bridge electrode ELT_BRP may be arranged to be connected to the common electrode layer AEL. Figure 12a The second bridge pattern BRP2 of the first light emitting element layer LDL1 is described to overlap. The bridge electrode ELT_BRP may couple the first electrode ELT1 of the third light emitting element layer LDL3 and the first transistor T1 (or first transistor electrode ET1) of the pixel circuit layer PCL to each other.

[0205] The light emitting element layers LDL1, LDL2 and LDL3 may include a first light emitting element LD1, a second light emitting element LD2 and a third light emitting element LD3 of the pixel PXL, respectively. Figure 6 The described light emitting element layers LDL1 , LDL2 , and LDL3 are substantially the same, and thus repeated description thereof will be omitted.

[0206] Combined with the above reference Figures 12a to 12c As described, the second electrode ELT2 of the first light-emitting element layer LDL1 can be connected to the second common electrode AELT2 via a through hole passing through the first insulating layer INS1, the second electrode ELT2 of the second light-emitting element layer LDL2 can be connected to the second electrode ELT2 of the first light-emitting element layer LDL1 via a through hole passing through the second insulating layer INS2, and the second electrode ELT2 of the third light-emitting element layer LDL3 can be connected to the second electrode ELT2 of the second light-emitting element layer LDL2 via a through hole passing through the third insulating layer INS3.

[0207] In an embodiment, the first electrode ELT1 of the third light emitting element layer LDL3 can be connected to the first transistor T1 (or the first transistor electrode ET1) of the pixel circuit layer PCL via at least one through hole passing through the insulating layers INS1, INS2 and INS3 (for example, the first sub-through hole CH3_1, the second sub-through hole CH3_2 and the third sub-through hole CH3_3 passing through the first insulating layer INS1, the second insulating layer INS2 and the third insulating layer INS3, respectively) and the bridging electrode ELT_BRP.

[0208] As mentioned above Figures 12a to 13As described, the pixel PXL may include a pixel circuit layer PCL, a common electrode layer AEL, and a first light-emitting element layer LDL1, a second light-emitting element layer LDL2, and a third light-emitting element layer LDL3 sequentially stacked on a substrate SUB, and the first light-emitting element layer LDL1, the second light-emitting element layer LDL2, and the third light-emitting element layer LDL3 may be connected to a first pixel circuit PXC1, a second pixel circuit PXC2, and a third pixel circuit PXC3 respectively formed on the pixel circuit layer PCL.

[0209] Since the light emitting element layers LDL1 , LDL2 , and LDL3 corresponding to different colors are three-dimensionally arranged in a limited area (ie, the pixel area PXA), the display device (or display panel PNL) may have improved brightness.

[0210] In addition, the light emitting element layers LDL1 , LDL2 , and LDL3 respectively form sub-pixels emitting light of different colors (eg, red, green, and blue), and thus the display device (or display panel PNL) may have high resolution (or high definition).

[0211] At the same time, despite Figure 13 , the second common electrode AELT2 is shown as being coupled to the corresponding second electrodes ELT2 of the light emitting element layers LDL1, LDL2, and LDL3, but the present disclosure is not limited thereto. For example, the second electrode ELT2 of each of the light emitting element layers LDL1, LDL2, and LDL3 may be coupled to the power line PL via a separate bridge electrode, rather than being coupled to the second common electrode AELT2.

[0212] Figure 14 It is shown that the Figure 9 A plan view of an example of a pixel in a display device. Figure 14 Based on the above reference Figure 11 and Figure 12c The third light emitting element layer LDL3 is described to show the structure of the pixel PXL.

[0213] In addition to the arrangement of the first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3 and the coupling of the first electrode ELT1 to the pixel circuit PXC, Figure 14 The pixel PXL can be compared with the above reference Figures 12a to 12c The pixels PXL described are substantially the same or similar, and therefore, repeated description thereof will be omitted.

[0214] Reference Figure 14The pixel PXL may include a first pixel circuit PXC1, a second pixel circuit PXC2, and a third pixel circuit PXC3, and the first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3 may be sequentially arranged in the second direction DR2.

[0215] The first electrode ELT1 (or the first connection electrode CNL1 ) of each of the light emitting element layers LDL1 , LDL2 , and LDL3 may include a protrusion corresponding to a corresponding pixel circuit (ie, the first pixel circuit PXC1 , the second pixel circuit PXC2 , and the third pixel circuit PXC3 ).

[0216] like Figure 14 As shown in FIG, the first electrode ELT1 of the third light emitting element layer LDL3 may include a third protrusion ELT_P3. The third protrusion ELT_P3 may be formed to protrude from a portion of the first electrode ELT1 corresponding to the third pixel circuit PXC3 to the edge of the pixel area PXA. However, Figure 14 The protruding direction of the third protrusion ELT_P3 shown in FIG. 1 is merely exemplary and is not limited thereto.

[0217] The third protrusion ELT_P3 may be coupled to the third pixel circuit PXC3 through the fifth contact hole CH5. Figure 12c and Figure 13 The described coupling configuration between the third protrusion ELT_P3 and the third pixel circuit PXC3 is substantially the same, and thus a repeated description thereof will be omitted.

[0218] Similarly, the first protrusion ELT_P1 is formed from the first light emitting element layer LDL1 (see Figure 12a ) of the first electrode ELT1 corresponding to the first pixel circuit PXC1 protrudes, and the first protrusion ELT_P1 can be coupled to the first pixel circuit PXC1 through the first contact hole CH1. The second protrusion ELT_P2 is formed from the second light emitting element layer LDL2 (see Figure 12b ) a portion of the first electrode ELT1 corresponding to the second pixel circuit PXC2 protrudes, and the second protrusion ELT_P2 may be coupled to the second pixel circuit PXC2 through the third contact hole CH3.

[0219] As referenced above Figure 14 As described, the pixel circuits PXC1 , PXC2 , and PXC3 and the configuration for coupling the light emitting element layers LDL1 , LDL2 , and LDL3 to the pixel circuits PXC1 , PXC2 , and PXC3 may be modified in various forms.

[0220] Figure 15 It is shown that the Figure 9 A plan view of an example of a pixel in a display device. Figure 15 Based on the above reference Figure 11 and Figure 12c The third light emitting element layer LDL3 is described to show the structure of the pixel PXL. Figure 16 It is shown along Figure 15 A cross-sectional view of an example of a pixel taken along line III-III'. Figure 16 , the pixel circuit layer PCL is omitted, and the structure of the pixel PXL is schematically shown based on the light emitting element layers LDL1 , LDL2 , and LDL3 .

[0221] Reference Figures 14 to 16 , Figure 15 The Pixel PXL with Figure 14 The difference of the Pixel PXL is that Figure 15 The pixel PXL further includes a first bank pattern PW1 and a second bank pattern PW2 .

[0222] In an embodiment, the first bank pattern PW1 and the second bank pattern PW2 may be arranged in the non-emission area NEMA and may be disposed along at least a portion of an edge of the emission area EMA.

[0223] like Figure 16 As shown in FIG, the first bank pattern PW1 and the second bank pattern PW2 may be provided on the substrate SUB (or reference Figure 13 The pixel circuit layer PCL described above is disposed on the pixel circuit layer PCL). The first embankment pattern PW1 and the second embankment pattern PW2 may be arranged in the emission area EMA and spaced apart from each other. The first embankment pattern PW1 and the second embankment pattern PW2 may protrude from the substrate SUB in the height direction. In an embodiment, the height H1 of the first embankment pattern PW1 may be the same as the height H2 of the second embankment pattern PW2, but the present disclosure is not limited thereto. The heights of the first embankment pattern PW1 and the second embankment pattern PW2 may be greater than the heights of the light emitting element layers LDL1, LDL2 and LDL3 (i.e., the light emitting element layers LDL1, LDL2 and LDL3 other than the first embankment pattern PW1 and the second embankment pattern PW2), and the heights of the first embankment pattern PW1 and the second embankment pattern PW2 may be equal to or greater than 2 μm, or may be equal to or greater than 2.5 μm.

[0224] According to an embodiment, the first bank pattern PW1 may be disposed between the substrate SUB and the first common electrode AELT1 , and the second bank pattern PW2 may be disposed between the substrate SUB and the first common electrode AELT1 .

[0225] According to embodiments, the first and second bank patterns PW1 and PW2 may have various shapes. Figure 16As shown in the example, each of the first and second bank patterns PW1 and PW2 may have a trapezoidal cross-sectional shape whose width decreases as it approaches its top. In this case, each of the first and second bank patterns PW1 and PW2 may have an inclined surface on at least one side surface thereof. However, the shapes of the first and second bank patterns PW1 and PW2 are not limited thereto.

[0226] The first bank pattern PW1 and the second bank pattern PW2 may include an insulating material, which may include an inorganic material and / or an organic material. For example, the first bank pattern PW1 and the second bank pattern PW2 may include at least one inorganic layer, which may include various well-known inorganic insulating materials and SiN x or SiO x Alternatively, the first and second bank patterns PW1 and PW2 may include at least one organic layer and / or a photoresist layer including various well-known organic insulating materials, or the first and second bank patterns PW1 and PW2 may be formed of a single-layer or multi-layer insulator including a combination of organic and inorganic materials. That is, the materials forming the first and second bank patterns PW1 and PW2 may be varied in various ways.

[0227] In an embodiment, in the step of providing the light emitting elements LD1, LD2 and LD3 to the emission area EMA, the first embankment pattern PW1 and the second embankment pattern PW2 can be used as a baffle structure for preventing the solution in which the light emitting elements LD1, LD2 and LD3 are mixed with each other from flowing into the emission area EMA of the adjacent pixel PXL, or for controlling a predetermined amount of solution to be provided to each emission area EMA.

[0228] According to an embodiment, the first and second bank patterns PW1 and PW2 may serve as a reflective member. In an example, the first and second bank patterns PW1 and PW2, together with the first common electrode AELT1 disposed on top thereof, may serve as a reflective member for improving the optical efficiency of the pixel PXL by inducing light emitted from the corresponding light emitting elements LD1, LD2, and LD3 in a desired direction.

[0229] The first common electrode AELT1 may be disposed on top of the first and second bank patterns PW1 and PW2. The first common electrode AELT1 may extend from the emission area EMA to the non-emission area NEMA and then cover at least a portion of one side surface (e.g., one side surface adjacent to the emission area EMA) and a top surface of the first and second bank patterns PW1 and PW2.

[0230] Meanwhile, while the first common electrode AELT1 is described as covering at least portions of the first and second bank patterns PW1 and PW2, the present disclosure is not limited thereto. For example, the first and second common electrodes AELT1 and AELT2 may be arranged in the emission area EMA, and a separate reflective electrode, distinct from the first and second common electrodes AELT1 and AELT2, may cover at least portions of the first and second bank patterns PW1 and PW2. In this case, the reflective electrode may be formed using the same process as the first and second common electrodes AELT1 and AELT2.

[0231] In an embodiment, the first common electrode AELT1 disposed on top of the first and second bank patterns PW1 and PW2 may have a shape corresponding to the shapes of the first and second bank patterns PW1 and PW2. For example, although the first common electrode AELT1 has an inclined surface or a curved surface corresponding to the first and second bank patterns PW1 and PW2, it may protrude in the height direction (or thickness direction) of the light emitting element layers LDL1, LDL2, and LDL3.

[0232] Each of the first common electrode AELT1 and the second common electrode AELT2 may include at least one conductive material. In an example, each of the first common electrode AELT1 and the second common electrode AELT2 may include, but is not limited to, a material corresponding to at least one of a metal (such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Ti, or an alloy thereof), a conductive oxide (such as ITO, IZO, ZnO, or ITZO), and a conductive polymer (such as PEDOT).

[0233] Furthermore, each of the first common electrode AELT1 and the second common electrode AELT2 can be configured as a single-layer structure or a multi-layer structure. In an example, each of the first common electrode AELT1 and the second common electrode AELT2 can include at least one reflective electrode layer. Furthermore, each of the first electrode ELT1 and the second electrode ELT2 can optionally include at least one of at least one transparent electrode layer disposed above and / or below the reflective electrode layer and at least one conductive cover layer configured to cover the top of the reflective electrode layer and / or the transparent electrode layer.

[0234] In an embodiment, the reflective electrode layer of each of the first common electrode AELT1 and the second common electrode AELT2 may be made of a conductive material having uniform reflectivity. In some examples, the reflective electrode layer may include, but is not limited to, at least one of metals such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, and alloys thereof. In other words, the reflective electrode layer may be made of various types of reflective conductive materials. When each of the first common electrode AELT1 and the second common electrode AELT2 includes a reflective electrode layer, light emitted from opposite ends of each of the light-emitting elements LD1, LD2, and LD3 can also travel in the direction of displaying an image (e.g., the front direction). In particular, when the first common electrode AELT1 and the second common electrode AELT2 are arranged to face the opposite ends of the light-emitting elements LD1, LD2, and LD3 while having inclined or curved surfaces corresponding to the shapes of the first and second bank patterns PW1 and PW2, light emitted from the opposite ends of each of the light-emitting elements LD1, LD2, and LD3 can also be reflected from the first and second common electrodes AELT1 and AELT2 and can also travel in the front direction of the display panel PNL (for example, in an upward direction from the substrate SUB). Therefore, the efficiency of light emitted from the light-emitting elements LD1, LD2, and LD3 can be improved.

[0235] In addition, the transparent electrode layer of each of the first common electrode AELT1 and the second common electrode AELT2 can be made of various types of transparent electrode materials. For example, the transparent electrode layer may include, but is not limited to, ITO, IZO, or ITZO. In an embodiment, each of the first common electrode AELT1 and the second common electrode AELT2 can be configured as a three-layer structure having a stacked structure of ITO / Ag / ITO. In this way, when each of the first common electrode AELT1 and the second common electrode AELT2 is configured as a multilayer structure of two or more layers, the voltage drop attributable to signal delay (RC delay) can be minimized. Therefore, the desired voltage can be effectively transmitted to the light-emitting element LD.

[0236] Furthermore, when each of the first and second common electrodes AELT1 and AELT2 includes a conductive cover layer covering the reflective electrode layer and / or the transparent electrode layer, the reflective electrode layer of the first and second common electrodes AELT1 and AELT2 can be protected from damage due to a fault occurring during a process for manufacturing the pixel PXL. However, the conductive cover layer may be selectively included in the first and second common electrodes AELT1 and AELT2 and may be omitted depending on the embodiment. Furthermore, the conductive cover layer may be considered a component of the first and second common electrodes AELT1 and AELT2, or a separate component disposed on the first and second common electrodes AELT1 and AELT2.

[0237] The first insulating layer INS1, the second insulating layer INS2, the third insulating layer INS3 and the fourth insulating layer INS4 may be sequentially disposed on the first common electrode AELT1 and the second common electrode AELT2, and the first electrode ELT1 and the second electrode ELT2 and the first light emitting element LD1, the second light emitting element LD2 and the third light emitting element LD3 may be disposed between the first insulating layer INS1, the second insulating layer INS2, the third insulating layer INS3 and the fourth insulating layer INS4. Figures 6 to 13 The configurations of the described light emitting element layers LDL1 , LDL2 , and LDL3 are substantially the same, and thus repeated descriptions thereof will be omitted.

[0238] As referenced above Figure 15 and Figure 16 As described, the pixel PXL may include bank patterns PW1 and PW2 defining the emission area EMA and a reflective electrode covering inner surfaces of the bank patterns PW1 and PW2 (i.e., side surfaces adjacent to the emission area EMA). Therefore, the efficiency of light emitted from the pixel PXL may be improved.

[0239] At the same time, the above reference Figure 15 and Figure 16 The described pixel PXL can also be applied to Figures 4 to 6 That is, Figures 4 to 6 The light emitting device EU may further include a bank pattern defining an emission area EMA (or a unit emission area) and a reflective electrode (or a common electrode) covering an inner surface of the bank pattern.

[0240] At the same time, in the embodiments of the present disclosure, corresponding sub-pixels can form corresponding light-emitting devices. For example, the first sub-pixel corresponding to the red sub-pixel can form a red light-emitting device, the second sub-pixel corresponding to the green sub-pixel can form a green light-emitting device, and the third sub-pixel corresponding to the blue sub-pixel can form a blue light-emitting device. In addition, the full-color pixel PXL including the first sub-pixel, the second sub-pixel, and the third sub-pixel can form a full-color light-emitting device. That is, the embodiments of the present disclosure are not necessarily limited to display devices and can also be widely applied to other types of devices that require a light source.

[0241] Although the spirit and scope of the present disclosure have been described in detail by way of exemplary embodiments, it should be noted that the above embodiments are merely illustrative and should not be considered as limiting. In addition, it should be understood by those skilled in the art that various changes, substitutions and replacements may be made herein without departing from the scope of the present disclosure as defined by the appended claims.

[0242] The scope of the present disclosure is not limited by the detailed description of this specification, but should be defined by the appended claims. In addition, all changes or modifications of the present disclosure derived from the meaning and scope of the claims and their equivalents should be interpreted as being included in the scope of the present disclosure.

Claims

1. A light-emitting device comprising: substrate; a bank pattern disposed on the substrate; a plurality of light-emitting element layers stacked on the substrate; as well as a common electrode layer disposed between a first light-emitting element layer closest to the substrate among the light-emitting element layers and the substrate, and including a first common electrode and a second common electrode spaced apart from each other, Wherein, each of the light emitting element layers includes: an insulating layer disposed on the entire surface of the substrate; a first electrode and a second electrode disposed on the insulating layer and spaced apart from each other, wherein the first electrode is electrically separated from the first common electrode and the second electrode is electrically coupled to the second common electrode; and a plurality of light emitting elements disposed between the first electrode and the second electrode, and The bank pattern includes a first bank pattern and a second bank pattern disposed between the first common electrode and the substrate, and the first common electrode covers the entire side surface and at least a portion of the top surface of each of the first bank pattern and the second bank pattern.

2. The light emitting device according to claim 1, wherein: The first electrode overlaps with the first common electrode, and The second electrode overlaps with the second common electrode.

3. The light emitting device according to claim 1, wherein Each of the light emitting elements is a rod-type light emitting diode having a size ranging from nanometer order to micrometer order. The light emitting device according to claim 3 , wherein: Each of the light emitting element layers emits monochromatic light. The light emitting device according to claim 3 , wherein: At least a portion of the light emitting element layer emits light of a different color.

6. The light emitting device according to claim 1, wherein: The light emitting element is provided between the first electrode, the second electrode and the insulating layer, The first ends of the light emitting elements are respectively coupled to the first electrode, and Respective second ends of the light emitting elements are coupled to the second electrode.

7. The light emitting device according to claim 1, wherein: The light emitting element layer includes the first light emitting element layer, the second light emitting element layer and the third light emitting element layer sequentially provided on the substrate, The first light-emitting element layer includes a first light-emitting element configured to emit light of a first color, the second light-emitting element layer includes second light-emitting elements configured to emit light of a second color, and The third light-emitting element layer includes third light-emitting elements configured to emit light of a third color. The light emitting device according to claim 1 , wherein: The substrate includes an emitting region and a non-emitting region surrounding the emitting region, wherein the light emitting element is arranged in the emission region of the substrate, Wherein, the thickness of the bank pattern is greater than the thickness of the light emitting element layer.

9. Display devices, including: substrate; a bank pattern disposed on the substrate; a circuit element layer, including multiple transistors and power lines; as well as a common electrode layer, comprising a first common electrode and a second common electrode, wherein the first common electrode and the second common electrode are disposed on the substrate and spaced apart from each other; as well as A plurality of light emitting element layers are sequentially arranged on the common electrode layer, Wherein, each of the light emitting element layers includes: an insulating layer disposed on the entire surface of the substrate; a first electrode and a second electrode disposed on the insulating layer and spaced apart from each other; and A plurality of light emitting elements are provided between the first electrode and the second electrode, wherein the first electrode is coupled to one of the transistors and electrically separated from the first common electrode, and the second electrode is coupled to the power line and electrically coupled to the second common electrode, and The bank pattern includes a first bank pattern and a second bank pattern disposed between the first common electrode and the substrate, and the first common electrode covers the entire side surface and at least a portion of the top surface of each of the first bank pattern and the second bank pattern.

10. The display device according to claim 9, wherein: The light-emitting element layer includes a first light-emitting element layer, a second light-emitting element layer and a third light-emitting element layer sequentially provided on the substrate, The first light-emitting element layer includes a first light-emitting element configured to emit light of a first color, the second light-emitting element layer includes second light-emitting elements configured to emit light of a second color, and The third light-emitting element layer includes third light-emitting elements configured to emit light of a third color.

11. The display device according to claim 10, wherein: The first electrode of the first light emitting element layer is coupled to a first transistor among the transistors through a first contact hole passing through the insulating layer of the first light emitting element layer, and The second electrode of the first light emitting element layer is coupled to the power line through a second contact hole penetrating the insulating layer of the first light emitting element layer.

12. The display device according to claim 11, wherein: The first light emitting element layer further includes a first bridge pattern, and the first bridge pattern is disposed to be spaced apart from the first electrode and the second electrode of the first light emitting element layer. The first electrode of the second light-emitting element layer is coupled to a second transistor among the transistors through a third contact hole and the first bridge pattern of the first light-emitting element layer, wherein the third contact hole is configured to expose the first bridge pattern by passing through the insulating layer of the second light-emitting element layer. The second electrode of the second light emitting element layer is coupled to the second electrode of the first light emitting element layer through a fourth contact hole configured to expose the second electrode of the first light emitting element layer by passing through the insulating layer of the second light emitting element layer.

13. The display device according to claim 12, wherein: The first electrode of the third light emitting element layer is coupled to a third transistor among the transistors through a fifth contact hole, the fifth contact hole passing through the insulating layer of the third light emitting element layer, and The second electrode of the third light emitting element layer is coupled to the second electrode of the second light emitting element layer through a sixth contact hole configured to expose the second electrode of the second light emitting element layer by passing through the insulating layer of the third light emitting element layer.

14. A method for manufacturing a display device, comprising: preparing the substrate; forming a bank pattern including a first bank pattern and a second bank pattern on the substrate; forming a common electrode layer including a first common electrode and a second common electrode spaced apart from each other on the bank pattern, the first common electrode covering the entire side surface and at least a portion of the top surface of each of the first bank pattern and the second bank pattern; forming a first light-emitting element layer on the common electrode layer; as well as forming a second light emitting element layer on the first light emitting element layer, Wherein, forming the first light-emitting element layer includes: forming a first insulating layer on the common electrode layer; aligning a plurality of first light emitting elements on the first insulating layer, wherein the first light emitting elements are disposed between the first common electrode and the second common electrode in a plan view; and First electrodes are formed on the first ends of the plurality of first light emitting elements, and second electrodes are formed on the second ends of the plurality of first light emitting elements.

15. The method according to claim 14, wherein Each of the first light emitting elements is a rod-type light emitting diode having a size ranging from nanometer order to micrometer order.

16. The method according to claim 14, wherein Aligning the plurality of first light emitting elements comprises: disposing the first light emitting element on the first insulating layer; and A first alternating current voltage is applied between the first common electrode and the second common electrode.

17. The method according to claim 16, wherein: The first electrode overlaps at least a portion of the first common electrode, and The second electrode overlaps with at least a portion of the second common electrode.

18. The method according to claim 16, wherein Forming the second light-emitting element layer includes: forming a second insulating layer on the first light-emitting element layer; In a plan view, a plurality of second light emitting elements are aligned between the first common electrode and the second common electrode; and A third electrode is formed on the first ends of the plurality of second light emitting elements, and a fourth electrode is formed on the second ends of the plurality of second light emitting elements.

19. The method according to claim 18, wherein: The first light emitting element emits light of a first color, and The second light emitting element emits light of a second color.

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