Display device and transistor

Abstract

According to an embodiment, a display device is provided, comprising: a display panel having a pixel portion configured with a plurality of pixels and a peripheral portion arranged around the pixel portion; a driving circuit arranged in the peripheral portion to drive the pixel. A transistor is arranged in the pixel portion or the peripheral portion, and the transistor comprises a semiconductor layer, a first and a second gate electrode overlapping the semiconductor layer, a source electrode, and a drain electrode. The source electrode is formed to cover at least a first channel region that is an overlapping region of the first gate electrode and the semiconductor layer when viewed from above. The drain electrode is formed to cover at least a second channel region that is an overlapping region of the second gate electrode and the semiconductor layer when viewed from above.

Description

Technical Field

[0001] Embodiments of the present invention relate to a display device and a transistor. Background Art

[0002] Generally, an electrophoretic display device (EPD: Electrophoretic Display) in which an electrophoretic element is sandwiched between a device substrate and a counter substrate is known.

[0003] According to the electrophoretic display device, by driving the pixel transistor included in each pixel arranged in the electrophoretic display device, for example, white or black can be displayed in each pixel.

[0004] However, the driving voltage of the electrophoretic display device is relatively high, and a high voltage is also applied to the above-mentioned pixel transistor.

[0005] Therefore, in the electrophoretic display device, there is a possibility that characteristic abnormality or operation abnormality may occur due to heat generated by a high voltage applied to the pixel transistor.

[0006] Prior Art Literature

[0007] Patent Literature

[0008] Patent Document 1: Japanese Patent Application Publication No. 2009-049080 Summary of the invention

[0009] Therefore, an object of the present invention is to provide a display device and a transistor capable of suppressing abnormalities caused by heat generation.

[0010] According to an embodiment, a display device is provided, comprising: a display panel having a pixel portion configured with a plurality of pixels and a peripheral portion arranged around the pixel portion; and a driving circuit arranged in the peripheral portion to drive the pixel. A transistor is arranged in the pixel portion or the peripheral portion, and the transistor comprises: a semiconductor layer having a first end and a second end; a first gate electrode overlapping the semiconductor layer at a position close to the first end; a second gate electrode overlapping the semiconductor layer between the first gate electrode and the second end; a source electrode connected to the first end; and a drain electrode connected to the second end. The first and second gate electrodes are arranged on a first layer. The source electrode and the drain electrode are arranged on a second layer different from the first layer. The source electrode is formed to cover at least a first channel region as an overlapping region of the first gate electrode and the semiconductor layer when viewed from above. The drain electrode is formed to cover at least a second channel region as an overlapping region of the second gate electrode and the semiconductor layer when viewed from above. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1It is a plan view showing an example of the structure of the display device according to the first embodiment.

[0012] Figure 2 This is a diagram showing an example of a cross section of a pixel along the first direction.

[0013] Figure 3 FIG. 1 is a plan view showing an example of a pixel transistor.

[0014] Figure 4 This is a diagram showing an example of a cross section of a pixel along the first direction in a comparative example of the present embodiment.

[0015] Figure 5 It is a plan view showing an example of a pixel transistor in a comparative example of the present embodiment.

[0016] Figure 6 This is a diagram for explaining an example of the structure of a source electrode and a drain electrode.

[0017] Figure 7 This is a diagram for explaining an example of the structure of a protection diode.

[0018] Figure 8 This is a diagram showing an example of a top-gate pixel transistor.

[0019] Fig. 9 This is a diagram showing an example of a cross section of a pixel along the first direction in the second embodiment.

[0020] Fig.10 FIG. 1 is a plan view showing an example of a pixel transistor in this embodiment.

[0021] Fig.11 FIG. 1 is a plan view showing another example of the pixel transistor in this embodiment.

[0022] Fig.12 This is a diagram showing an example of a top-gate pixel transistor. DETAILED DESCRIPTION

[0023] Hereinafter, the present embodiment will be described with reference to the accompanying drawings. In addition, the disclosure is only an example, and appropriate changes that can be easily thought of by those skilled in the art to maintain the main purpose of the invention are of course included in the scope of the present invention. In addition, in order to make the description clearer, the drawings sometimes schematically represent the width, thickness, shape, etc. of each part compared to the actual method, but this is only an example and does not limit the interpretation of the present invention. In addition, in this specification and each figure, the same reference figure mark is marked for the constituent elements that perform the same or similar functions as the figures already described, and sometimes repeated detailed descriptions are appropriately omitted.

[0024] (First embodiment)

[0025] Figure 1 1 is a plan view showing an example of the structure of the display device according to the first embodiment. Figure 1 In the example shown, the first direction X, the second direction Y, and the third direction Z are orthogonal to each other, but may intersect each other at angles other than 90 degrees. The first direction X and the second direction Y correspond to directions parallel to the main surface of the substrate constituting the display device DSP, and the third direction Z corresponds to the thickness direction of the display device DSP. In the present embodiment, the position on the front end side of the arrow representing the third direction Z is referred to as the upper side (or simply referred to as the upper side), and the position on the rear end side of the arrow is referred to as the lower side (or simply referred to as the lower side). In addition, assuming that there is an observation position for observing the display device DSP on the front end side of the arrow representing the third direction Z, observation from the observation position to the XY plane defined by the first direction X and the second direction Y is referred to as top view.

[0026] Figure 1 The display device DSP shown in the figure includes a display panel 1 including a first substrate SUB1 and a second substrate SUB2. The display panel 1 includes a display area DA as a pixel portion and a non-display area NDA as a peripheral portion provided around the pixel portion.

[0027] The display area DA is located in a region where the first substrate SUB1 and the second substrate SUB2 overlap each other in a plan view. In the display area DA (pixel portion), a plurality of pixels PX are arranged in a matrix in the first direction X and the second direction Y.

[0028] The non-display area NDA is formed in a frame shape. A driving circuit including gate drivers GD1 and GD2 and a source driver SD (a driving circuit for driving the display panel 1 ) is located in the non-display area NDA and is provided on the first substrate SUB1 .

[0029] The flexible wiring substrate 2 is connected to the first substrate SUB1. The IC chip 3 is connected to the flexible wiring substrate 2. Alternatively, the IC chip 3 may be connected to the first substrate SUB1. Alternatively, the gate drivers GD1 and GD2 and the source driver SD may be built into the IC chip 3, for example.

[0030] In the display device DSP according to the present embodiment, protection diodes 4 and 5 may be provided on the first substrate SUB1. The protection diode 4 is disposed between the flexible wiring substrate 2 and the source driver SD, and the signal supplied via the protection diode 4 is input to the source driver SD. The protection diode 5 is disposed at positions corresponding to the gate drivers GD1 and GD2, respectively, and the signal supplied via the protection diode 5 is input to the gate drivers GD1 and GD2.

[0031] Figure 2FIG. 4 shows an example of a cross section of a pixel PX provided in a pixel portion along the first direction X. Figure 2 As shown, the first substrate SUB1 includes a base material 11 and insulating films 12 to 15 .

[0032] The substrate 11 is an insulating substrate formed of insulating glass or a resin such as a polyimide resin. Since the substrate 11 is located on the opposite side of the observation position relative to the second substrate SUB2, it is, for example, an opaque substrate, but may also be a transparent substrate.

[0033] Here, the pixel PX (pixel circuit) includes a pixel transistor (thin film transistor) SW as a switching element, but in this embodiment, the pixel transistor SW has a dual-gate structure, that is, the pixel transistor SW includes a semiconductor layer SC, two gate electrodes GE1 and GE2, a source electrode SE and a drain electrode DE.

[0034] The gate electrodes GE1 and GE2 are located on the substrate 11 and are covered by an insulating film (gate insulating film) 12. The gate electrodes GE1 and GE2 are formed of metal materials such as aluminum (Al), titanium (Ti), silver (Ag), molybdenum (Mo), tungsten (W), copper (Cu), chromium (Cr), or alloys combining these metal materials. In addition, the gate electrodes GE1 and GE2 may be either a single-layer structure or a stacked structure.

[0035] The semiconductor layer SC is located on the insulating film 12 and is covered by the insulating film 13. The semiconductor layer SC is arranged at a position overlapping with the gate electrodes GE1 and GE2 in a plan view. The semiconductor layer SC is formed of, for example, polycrystalline silicon (for example, low-temperature polycrystalline silicon), but may also be formed of amorphous silicon or an oxide semiconductor.

[0036] In addition, Figure 2 In the illustrated example, the pixel transistor SW is a bottom-gate transistor in which gate electrodes GE1 and GE2 are arranged between the substrate 11 and the semiconductor layer SC (that is, below the semiconductor layer SC).

[0037] The source electrode SE and the drain electrode DE are located on the insulating film 13 and are covered by the insulating film 14. The source electrode SE and the drain electrode DE are formed of the same material, for example, the above-mentioned metal material.

[0038] The source electrode SE is in contact with (connected to) the semiconductor layer SC in a through hole CH1 penetrating the insulating film 13 . The drain electrode DE is in contact with (connected to) the semiconductor layer SC in a through hole CH2 penetrating the insulating film 13 .

[0039] That is, the transistor SW comprises: a semiconductor layer SC; a gate electrode GE1, overlapping with the semiconductor layer SC at a position close to one end (first end) EP1 of the semiconductor layer SC; a gate electrode GE2, overlapping with the semiconductor layer SC between the gate electrode GE1 and the other end (second end) EP2; a source electrode SE, connected to the end EP1 of the semiconductor layer SC; and a drain electrode DE, connected to the end EP2 of the semiconductor layer SC.

[0040] In addition, the gate electrodes GE1 and GE2 are connected to the scanning lines, and the source electrode SE is connected to the signal line. Figure 2 The scan line and signal line are omitted.

[0041] The capacitor electrode 100 is located on the insulating film 14 and is covered by the insulating film (capacitor insulating film) 15. The capacitor electrode 100 is a transparent electrode formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The capacitor electrode 100 can also be formed of an opaque metal material (non-transparent conductive material). Figure 2 Although omitted in the figure, the capacitor electrode 100 may be in contact with a power supply line, for example.

[0042] The pixel electrode PE is located on the insulating film 15. One pixel electrode PE is provided for each of the plurality of pixels PX arranged in the display area DA.

[0043] The pixel electrode PE contacts the drain electrode DE in the through hole CH3 penetrating the insulating film 14 and the through hole CH4 penetrating the insulating film 15. The pixel electrode PE is a transparent electrode formed of a transparent conductive material such as the above-mentioned ITO or IZO. The pixel electrode PE can be formed of a metal material (non-transparent conductive material) with light reflectivity. The pixel electrode PE overlaps with the capacitor electrode 100 through the insulating film 15 to form a capacitor of the pixel PX.

[0044] The insulating films 12, 13 and 15 correspond to inorganic insulating films formed of inorganic materials such as silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), etc. These insulating films 12, 13 and 15 may each have a single layer structure or a stacked structure.

[0045] The insulating film 14 is equivalent to an organic insulating film (organic planarizing film) formed of an organic material such as acrylic resin. The insulating film 14 is formed to be thicker than the above-mentioned inorganic insulating film (insulating films 12, 13 and 15). By forming the organic insulating film with a predetermined thickness, the concavities and convexities below the organic insulating film are absorbed, and the organic insulating film becomes flat. As a result, the concavities and convexities of the capacitor electrode or the pixel electrode formed on the organic insulating film can be suppressed.

[0046] Here, the display device DSP according to the present embodiment is, for example, an electrophoretic display device (EPD: Electrophoretic Display). In this case, the second substrate SUB2 includes a base material 21 , a common electrode CE, and an electrophoretic element 22 .

[0047] The base material 21 is formed of insulating glass or resin such as polyimide resin. Since the base material 21 is located on the observation position side with respect to the first substrate SUB1, it is a transparent base material.

[0048] The common electrode CE is located between the substrate 21 and the electrophoretic element 22. The common electrode CE is a transparent electrode formed of a transparent conductive material such as ITO or IZO. The common electrode CE and the capacitor electrode 100 have the same potential.

[0049] The electrophoretic element 22 is located between the pixel electrode PE and the common electrode CE. The electrophoretic element 22 is formed of a plurality of microcapsules 30 arranged with almost no gaps in the XY plane.

[0050] The microcapsule 30 has a particle size of, for example, about 20 μm to 70 μm. Also, about 1 to 10 microcapsules 30 are arranged on the pixel electrode PE in a rectangular or polygonal shape with a side length of about 100 to several hundred μm.

[0051] The microcapsule 30 includes a dispersion medium 31, a plurality of black particles 32, and a plurality of white particles 33. The outer shell 34 of the microcapsule 30 is formed of a transparent resin such as an acrylic resin.

[0052] The dispersion medium 31 is a liquid in which the black particles 32 and the white particles 33 are dispersed in the microcapsules 30 .

[0053] The black particles 32 and the white particles 33 are, for example, so-called electrophoretic particles, and have charges of opposite polarities to each other. For example, the black particles 32 are positively charged, and the white particles 33 are negatively charged.

[0054] In addition, the microcapsule 30 may include electrophoretic particles of other colors such as red, green, blue, yellow, cyan, and magenta in addition to the black particles 32 and the white particles 33. The electrophoretic particles of other colors may replace at least one of the black particles 32 and the white particles 33.

[0055] When the pixel PX in the electrophoretic element 22 of the above structure displays black, the pixel electrode PE is relatively kept at a higher potential than the common electrode CE. That is, when the potential of the common electrode CE is used as the reference potential, the pixel electrode PE is kept at a positive polarity. As a result, the positively charged black particles 32 are attracted to the common electrode CE, and on the other hand, the negatively charged white particles 33 are attracted to the pixel electrode PE. As a result, when the pixel PX is observed from above the second substrate SUB2 (i.e., the observation position), it is visually confirmed to be black.

[0056] On the other hand, when the pixel PX displays white, the pixel electrode PE is relatively kept at a low potential compared to the common electrode CE. That is, when the potential of the common electrode CE is used as the reference potential, the pixel electrode PE is kept at a negative polarity. As a result, the negatively charged white particles 33 are attracted to the common electrode CE side, and on the other hand, the positively charged black particles 32 are attracted to the pixel electrode PE. As a result, when the pixel PX is observed from above the second substrate SUB2 (i.e., the observation position), it is visually confirmed to be white.

[0057] In addition, the first substrate SUB1 and the second substrate SUB2 are bonded together by an adhesive layer 40. Figure 2 In the example shown, the adhesive layer 40 is located between the pixel electrode PE and the electrophoretic element 22 .

[0058] Figure 3 2 is a plan view showing an example of the pixel transistor SW in this embodiment. As described above, the pixel transistor SW has a dual-gate structure including two gate electrodes (ie, the gate electrodes GE1 and GE2).

[0059] like Figure 3 As shown, the gate electrodes GE1 and GE2 are formed on the same layer as the scan line G and are connected to the scan line G. The scan line G extends along the first direction X and is connected to the first layer. Figure 1 The source electrode SE is connected to a signal line S, which is formed on the same layer as the source electrode SE and the drain electrode DE. The signal line S extends along the second direction Y and is connected to the gate driver GD1 and GD2. Figure 1 The pixel transistor SW is located at the intersection of the scanning line G and the signal line S.

[0060] The gate electrodes GE1 and GE2 are arranged side by side at intervals in the first direction X. In addition, the gate electrodes GE1 and GE2 are arranged at positions overlapping with the semiconductor layer SC.

[0061] In addition, the gate electrodes GE1 and GE2 are formed in the same shape and the same size (area) in a plan view.

[0062] The source electrode SE is electrically connected to the semiconductor layer SC in the through hole CH1. The drain electrode DE is electrically connected to the semiconductor layer SC in the through hole CH2. In addition, the pixel electrode PE is electrically connected to the drain electrode DE in the through hole CH4. In this case, the drain electrode DE also functions as a base of a contact portion that contacts the pixel electrode PE.

[0063] Here, the gate electrode GE1 includes a first end GE1a along the signal line S and a second end GE1b provided between the first end GE1a and the gate electrode GE2. With respect to the gate electrode GE1, the source electrode SE extends along the gate line G and overlaps both the first end GE1a and the second end GE1b in a plan view.

[0064] In addition, the gate electrode GE2 includes a third end GE2a along a direction intersecting (for example, orthogonal to) the gate line G and a fourth end GE2b provided between the third end GE2a and the gate electrode GE1. Relative to the gate electrode GE2, the drain electrode DE extends along the gate line G and overlaps with both the third end GE2a and the fourth end GE2b when viewed from above.

[0065] That is, in the present embodiment, the source electrode SE is formed to completely cover the gate electrode GE1 (the upper part of the channel region corresponding to the gate electrode GE1) in the first direction X, and the drain electrode DE is formed to completely cover the gate electrode GE2 (the upper part of the channel region corresponding to the gate electrode GE2). The channel region refers to a region CHN1 in the semiconductor layer where the gate electrode GE1 is orthogonally projected and overlaps with the gate electrode GE1, and a region CHN2 where the gate electrode GE2 is orthogonally projected and overlaps with the gate electrode GE2.

[0066] In addition, Figure 3 In the example shown, the end of the source electrode SE on the drain electrode DE side coincides with the end GE1b of the gate electrode GE1 when viewed from above, but the source electrode SE only needs to completely cover the gate electrode GE1 in the first direction X. Therefore, the end of the source electrode SE on the drain electrode DE side may further extend beyond the end GE1b of the gate electrode GE1 on the gate electrode GE2 side.

[0067] Similarly, the end portion of the drain electrode DE on the source electrode SE side may further extend beyond the end portion GE2 b of the gate electrode GE2 .

[0068] Next, the function of the display device DSP according to the present embodiment will be described. Figure 4 is a diagram showing a cross section of a pixel PX in a comparative example of the present embodiment along the first direction X. In addition, Figure 5 It is a top view of the pixel transistor SW′ in a comparative example of the present embodiment.

[0069] In addition, Figure 4 and Figure 5 In the above Figure 2 and Figure 3 The same parts are marked as Figure 2 and Figure 3 Here, the same reference numerals are omitted. Figure 2 and Figure 3 The same description applies to the following parts.

[0070] In the comparative example of the present embodiment, the pixel transistor SW' has a single-gate structure, that is, the pixel transistor SW' has one gate electrode GE', one source electrode SE, and one drain electrode DE.

[0071] In the comparative example of the present embodiment, the source electrode SE does not overlap with the gate electrode GE' in a plan view. In addition, the drain electrode DE' overlaps only a portion of the gate electrode GE' on the drain electrode DE side in a plan view.

[0072] That is, the difference between the comparative example of the present embodiment and the present embodiment is that the pixel transistor SW′ has a single-gate structure, and the gate electrode GE′ is not completely covered by the source electrode SE and the drain electrode DE.

[0073] Here, it is assumed that an image is displayed in the display device DSP' involved in the comparative example of the present embodiment. In this case, along with the switch drive of the pixel transistor SW', a high voltage of, for example, 40 V or more is applied to the pixel transistor SW'. Therefore, a strong electric field is generated in the channel region CHN' of the pixel transistor SW', and hot carriers are accelerated.

[0074] As a result, high heat due to generation of hot carriers is locally generated in the channel region CHN′ (region of the semiconductor layer SC overlapping the gate electrode GE′), and the organic insulating film (insulating film 14 ) formed on the upper portion of the pixel transistor SW′ may be burned out.

[0075] Such burnout of the organic insulating film affects the threshold characteristics (Vth characteristics) of the pixel transistor SW′, thus causing characteristic abnormalities and operational abnormalities of the pixel transistor SW′.

[0076] In addition, Figure 4 and Figure 5 In the example shown, the drain electrode DE partially overlaps the gate electrode GE'. However, if the drain electrode DE only partially overlaps, it is impossible to prevent the organic insulating film from being burned under a high voltage applied in the electrophoretic display device.

[0077] Here, in order to prevent the burnout of the organic insulating film, in a comparative example of the present embodiment, a structure in which the gate electrode GE′ is completely covered (overlapped) with the drain electrode DE (drain metal) is considered, for example.

[0078] On the other hand, it can be considered that in such a structure, the electric field generated by the voltage state of the drain electrode DE affects the channel region CHN', causing the transistor characteristics to change. That is, it can be considered that in terms of circuit design, the pixel transistor (including the source electrode SE and the drain electrode DE) has an asymmetric structure as a whole, and the transistor characteristics change (asymmetric) when the source electrode SE is positively applied and the drain electrode DE is negatively applied and when they are reversed. Therefore, sometimes the good transistor characteristics are damaged.

[0079] In contrast, in this embodiment, the pixel transistor SW has a dual-gate structure, forming a source electrode SE covering one gate electrode GE1 in the dual-gate structure (the channel region corresponding to the gate electrode GE1), and forming a drain electrode DE covering another gate electrode GE2 (the channel region corresponding to the gate electrode GE2).

[0080] Thus, heat generated in the channel region corresponding to the gate electrode GE1 is dispersed by the source electrode SE, and heat generated in the channel region corresponding to the gate electrode GE2 is dispersed by the drain electrode DE.

[0081] As described above, in the present embodiment, the pixel transistor SW includes: a semiconductor layer SC having a first end EP1 and a second end EP2; a gate electrode (first gate electrode) GE1 overlapping the semiconductor layer SC at a position close to the first end EP1 of the semiconductor layer SC; a gate electrode (second gate electrode) GE2 overlapping the semiconductor layer SC between the gate electrode GE1 and the second end EP2 of the semiconductor layer SC; a source electrode SE connected to the first end EP1 of the semiconductor layer SC; and a drain electrode DE connected to the second end EP2 of the semiconductor layer SC. In addition, in the present embodiment, the gate electrodes GE1 and GE2 are arranged on different layers from the source electrode SE and the drain electrode DE.

[0082] In the present embodiment, the source electrode SE overlaps with the end portions GE1a and GE1b of the gate electrode GE1 in a plan view, and the drain electrode DE overlaps with the end portions GE2a and GE2b of the gate electrode GE2 in a plan view.

[0083] That is, in this embodiment, on the basis of setting the pixel transistor SW to a dual-gate structure, the source electrode SE and the drain electrode DE are respectively extended to overlap with the gate electrodes GE1 and GE2 (the source electrode SE and the drain electrode DE are covered until the intermediate node). As a result, the heat generated by the pixel transistor caused by the driving of the display device DSP (for example, the electrophoretic display device) at a high voltage can be dispersed (dissipated) by the source electrode SE and the drain electrode DE. As a result, local heat transfer to the organic insulating film can be suppressed, and the organic insulating film can be prevented from being burned (that is, the allowable withstand voltage is increased), so that abnormalities caused by heat can be suppressed.

[0084] In the present embodiment, the gate electrodes GE1 and GE2 have the same shape and area (size) in a plan view, and the area of ​​the portion where the gate electrode GE1 overlaps with the source electrode SE is the same as the area of ​​the portion where the gate electrode GE2 overlaps with the drain electrode DE.

[0085] That is, in this embodiment, by making the width of the source electrode SE overlapping with the channel region (first channel region) CHN1 corresponding to the gate electrode GE1 and the width of the drain electrode DE overlapping with the channel region (second channel region) CHN2 corresponding to the gate electrode GE2 the same (i.e., the metal width), the transistor characteristics (Vth, on-current) during SD inversion become symmetrical, and from the perspective of driving design, good transistor characteristics that easily ensure a margin can be obtained.

[0086] Here, in the present embodiment, the source electrode SE only needs to extend to a position where the end of the source electrode SE coincides with the end of the channel region CHN1 corresponding to the gate electrode GE1 (that is, the source electrode SE overlaps with the end of the channel region CHN1 corresponding to the first end GE1a of the gate electrode GE1 and the end of the channel region CHN1 corresponding to the second end GE1b), but the source electrode SE may also extend to a position where the end of the source electrode SE exceeds the end of the channel region CHN1 corresponding to the gate electrode GE1. In other words, in the present embodiment, the source electrode SE is formed to cover at least the channel region CHN1 corresponding to the gate electrode GE1 when viewed from above.

[0087] Similarly, in the present embodiment, the drain electrode DE only needs to extend to a position where the end of the drain electrode DE coincides with the end of the channel region CHN2 corresponding to the gate electrode GE2 (that is, the drain electrode DE overlaps with the end of the channel region CHN2 corresponding to the third end GE2a of the gate electrode GE2 and the end of the channel region CHN2 corresponding to the fourth end GE2b), but the drain electrode DE may also extend to a position where the end of the drain electrode DE exceeds the end of the channel region CHN2 corresponding to the gate electrode GE2. In other words, in the present embodiment, the drain electrode DE is formed to cover at least the channel region CHN2 corresponding to the gate electrode GE2 when viewed from above.

[0088] In this case, in order to improve the efficiency of heat dissipation in the above-mentioned heat generation, it is preferred that the areas of the source electrode SE and the drain electrode DE are both large. As a result, it can be considered that the end of the source electrode SE beyond the second end GE1b of the gate electrode GE1 and the end of the drain electrode DE beyond the second end GE2b of the gate electrode GE2 are close to each other between the gate electrodes, but if they are too close, the source electrode SE and the drain electrode DE are electrically connected and there is a possibility of short circuit. Therefore, it is assumed that the end of the source electrode SE and the end of the drain electrode DE are close to the extent that they do not short circuit. In addition, in order to prevent the source electrode SE and the drain electrode DE from short circuiting, for example, the corner (end) of the source electrode SE on the drain electrode DE side and the corner (end) of the drain electrode DE on the source electrode SE side may also be chamfered.

[0089] In addition, the source electrode SE is connected to the signal line S with a large area (formed integrally), so even if heat is generated in the channel region corresponding to the gate electrode GE1, the heat can be easily dissipated to the signal line S side (easily released). On the other hand, the drain electrode DE is formed in an island shape, and it is difficult to dissipate heat compared to the source electrode SE. Figure 6 As shown, for example, a width W1 (first width) of the source electrode SE extending beyond the gate electrode GE1 is formed to be smaller than a width W2 (second width) of the drain electrode DE extending beyond the gate electrode GE2 .

[0090] According to such a structure, the drain electrode DE can be formed larger, and the effect of dispersing heat generated in the channel region CHN2 corresponding to the gate electrode GE2 can be improved.

[0091] In addition, in this embodiment, the pixel transistor SW included in the pixel portion (display area DA) is mainly described, but this embodiment can also be applied to, for example, a protection diode (protection circuit) included in the peripheral portion (non-display area NDA).

[0092] Here, refer to Figure 7An example of the structure of the protection diode is briefly described. Figure 1 At least one of the protection diodes 4 and 5 shown has Figure 7 The structure shown is sufficient.

[0093] The protection diodes 4 and 5 specifically include thin film transistors connected to diodes, and the threshold voltage of the protection diodes 4 and 5 is made higher than that of the pixel transistor included in the pixel PX. Such protection diodes 4 and 5 can protect the pixel transistor (pixel circuit) when a surge current enters.

[0094] like Figure 7 As shown, in the protection diodes 4 and 5, the gate electrode has a structure in which gate electrode portions (first gate electrode portions) 201 arranged in the order of gate electrodes GE1 and GE2 and gate electrode portions (second gate electrode portions) 202 arranged in the order of gate electrodes GE2 and GE1 are alternately arranged.

[0095] For such gate electrodes, the source electrode SE and the drain electrode DE are formed in a comb-teeth shape and arranged to mesh with each other in a plan view. Thus, the source electrode SE is arranged at a position overlapping with the gate electrode GE1, and the drain electrode DE is arranged at a position overlapping with the gate electrode GE2.

[0096] exist Figure 7 In the protection diodes 4 and 5 shown, similarly to the pixel transistor SW, the gate electrode GE1 is covered by the source electrode SE, and the gate electrode GE2 is covered by the drain electrode DE, so that the heat generated in the channel region of the transistor can be dispersed. Figure 7 , the semiconductor layer SC is omitted.

[0097] The protection diodes 4 and 5 are described here, but even other transistors included in the peripheral portion can also be configured as a dual-gate structure and form source and drain electrodes that overlap the two gate electrodes, respectively, so that the heat generated in the channel region of the transistor can be dispersed.

[0098] In addition, in this embodiment, the case where the pixel transistor SW is a bottom-gate transistor is described, but if Figure 8 As shown, this embodiment can also be applied to a top-gate transistor in which the gate electrodes GE1 and GE2 are arranged between the source electrode SE and the drain electrode DE and the semiconductor layer SC (that is, on the semiconductor layer SC).

[0099] exist Figure 8In the example shown, the first substrate SUB1 includes a base material 11 and insulating films 12 to 15 as in the case of a bottom-gate type, but an undercoat layer 16 is further provided between the base material 11 and the semiconductor layer SC. The undercoat layer 16 corresponds to an inorganic insulating film formed of an inorganic material. Figure 2 The same parts are omitted here for detailed description.

[0100] In addition, in this embodiment, the case where the display device DSP is an electrophoretic display device is mainly described, but the transistor described in this embodiment can also be applied to display devices other than electrophoretic display devices (for example, liquid crystal display devices). In addition, the transistor described in this embodiment can also be applied to electronic devices other than display devices. The same is true for the following embodiments.

[0101] (Second Embodiment)

[0102] Next, the second embodiment will be described. In addition, since the structure of the display device involved in this embodiment is the same as that of the first embodiment, Figure 1 Provide explanation.

[0103] Fig. 9 FIG. 1 is a diagram showing an example of a cross section of a pixel PX in the present embodiment along the first direction X. Figure 2 The same parts are marked with the same reference numerals and their detailed descriptions are omitted. Figure 2 The different parts are explained.

[0104] In the first embodiment, the source electrode SE overlaps with the gate electrode GE1 and the drain electrode DE overlaps with the gate electrode GE2. This embodiment is different from the first embodiment in that a floating metal (metal member) is arranged at a position overlapping with the gate electrodes GE1 and GE2.

[0105] like Fig. 9 As shown, the floating metal FM is located on the insulating film 13 and is covered by the insulating film 14. In addition, the floating metal FM is arranged on the same layer as the source electrode SE and the drain electrode DE and is sandwiched between the source electrode SE and the drain electrode DE. In addition, the floating metal FM is formed using the above-mentioned metal material.

[0106] In addition, Fig. 9 In the example shown, the pixel transistor SW is a bottom-gate transistor.

[0107] Fig.10 FIG. 1 is a top view of the pixel transistor SW in this embodiment. Figure 3The same parts are marked with the same reference numerals, and their detailed description is omitted. Figure 3 The different parts are explained.

[0108] The pixel transistor SW in this embodiment has a double gate structure similarly to the first embodiment described above.

[0109] The source electrode SE is electrically connected to the semiconductor layer SC in the through hole CH1 , and the drain electrode DE is electrically connected to the semiconductor layer SC in the through hole CH2 .

[0110] In addition, in the present embodiment, the source electrode SE does not overlap with the gate electrodes GE1 and GE2 in a plan view. Similarly, the drain electrode DE does not overlap with the gate electrodes GE1 and GE2 in a plan view.

[0111] Here, in the present embodiment, as described above, the floating metal FM is formed at a position sandwiched between the source electrode SE and the drain electrode DE.

[0112] The floating metal FM overlaps all of the end portions GE1 a and GE1 b of the gate electrode GE1 and the end portions GE2 a and GE2 b of the gate electrode GE2 .

[0113] In this case, the floating metal FM extends at least to a position where the end of the source electrode SE side of the floating metal FM coincides with the end GE1a of the gate electrode GE1 when viewed from above, and extends at least to a position where the end of the drain electrode DE side of the floating metal FM coincides with the end GE2a of the gate electrode GE2 when viewed from above.

[0114] That is, in the present embodiment, the floating metal FM that completely covers the gate electrodes GE1 and GE2 (the upper portions of the channel regions CHN1 and CHN2 corresponding to the gate electrodes GE1 and GE2 , respectively) in the first direction X is formed.

[0115] exist Fig.10 In the example shown, both ends of the floating metal FM in the first direction X are respectively aligned with the end GE1a of the gate electrode GE1 and the end GE2a of the gate electrode GE2 when viewed from above, but the floating metal FM only needs to cover the gate electrodes GE1 and GE2. Therefore, both ends of the floating metal FM may further extend toward both the source electrode SE side and the drain electrode DE side, or may further extend toward only one of the source electrode SE side and the drain electrode DE side.

[0116] As described above, in this embodiment, on the basis of setting the pixel transistor SW to a dual-gate structure, a floating metal FM (metal component) is configured at a position overlapping with the gate electrode GE1 (the channel region CHN1 corresponding to the gate electrode GE1) and the gate electrode GE2 (the channel region CHN2 corresponding to the gate electrode GE2).

[0117] Thus, heat generated in the channel region CHN1 corresponding to the gate electrode GE1 and heat generated in the channel region CHN2 corresponding to the gate electrode GE2 are dispersed by the floating metal FM.

[0118] Therefore, in the present embodiment, heat transfer to the organic insulating film can be suppressed, and burnout of the organic insulating film can be prevented, so abnormalities due to heat generation can be suppressed.

[0119] In addition, in the above Fig.10 In the example shown, when viewed from above, the width of the floating metal FM in the second direction Y is narrower than the width of the gate electrodes GE1 and GE2 in the second direction Y, but the width of the floating metal FM in the second direction Y may be further extended in the second direction Y. Thus, the area of ​​the floating metal FM can be increased and the gate electrodes GE1 and GE2 can be reliably covered, so that the effect of dispersing the heat in the channel region of the pixel transistor SW can be further improved.

[0120] In addition, Fig.10 In the above description, a case where a floating metal FM is formed to overlap the gate electrode GE1 (corresponding channel region CHN1) and the gate electrode GE2 (corresponding channel region CHN2) is described. Fig.11 As shown, a structure in which a first floating metal FM1 overlapping with the gate electrode GE1 and a second floating metal FM2 overlapping with the gate electrode GE2 are formed may be adopted.

[0121] Even if there is Fig.11 The structure of the first floating metal FM1 and the second floating metal FM2 shown can also disperse the heat generated in the channel region CHN1 corresponding to the gate electrode GE1 through the first floating metal FM1, and disperse the heat generated in the channel region CHN2 corresponding to the gate electrode GE2 through the second floating metal FM2, thereby suppressing abnormalities caused by heat.

[0122] In this embodiment, the pixel transistor SW included in the pixel portion is mainly described. However, this embodiment can also be applied to a transistor included in the peripheral portion as described in the first embodiment.

[0123] In addition, in this embodiment, the case where the pixel transistor SW is a bottom-gate transistor is described, but this embodiment may also be Fig.12 The above-mentioned top-gate transistor is applied to the above-mentioned top-gate transistor except that a floating metal FM is arranged between the source electrode SE and the drain electrode DE. Figure 8 The same, so the detailed description is omitted here.

[0124] According to at least one of the embodiments described above, a display device and a transistor capable of suppressing abnormality caused by heat generation in a channel region are provided.

[0125] Although several embodiments of the present invention have been described, these embodiments are only presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the purpose of the invention. These embodiments and their variations are included in the scope and purpose of the invention, and are also included in the invention described in the claims and their equivalents.

[0126] Description of Reference Numerals

[0127] 1…display panel; 2…flexible wiring substrate; 3…IC chip; 11, 21…substrate; 12-16…insulating film; 22…electrophoretic element; 30…microcapsule; 31…dispersion medium; 32…black particles; 33…white particles; 100…capacitor electrode; 201…first gate electrode portion; 202…second gate electrode portion; DSP…display device; SUB1…first substrate; SUB2…second substrate; GD1, GD2…gate driver; SD…source driver; DA…display area (pixel portion); NDA…non-display area (peripheral portion); SC…semiconductor layer; GE1, GE2…gate electrode; SE…source electrode; DE…drain electrode; SW…pixel transistor; PX…pixel; PE…pixel electrode; FM…floating metal (metal component).

Claims

1. A display device comprising: A display panel having a pixel portion in which a plurality of pixels are arranged and a peripheral portion provided around the pixel portion; and A driving circuit is provided in the peripheral portion and drives the pixel. A transistor is provided in the pixel portion or the peripheral portion, the transistor comprising: a semiconductor layer having a first end and a second end; a first gate electrode overlapping the semiconductor layer at a position close to the first end; a second gate electrode overlapping the semiconductor layer between the first gate electrode and the second end; a source electrode connected to the first end; and a drain electrode connected to the second end. The first and second gate electrodes are arranged on the first layer, The source electrode and the drain electrode are arranged on a second layer different from the first layer, The source electrode is formed to cover at least the first channel region which is an overlapping region of the first gate electrode and the semiconductor layer in a plan view. The drain electrode is formed to cover at least the second channel region which is an overlapping region of the second gate electrode and the semiconductor layer in a plan view, The peripheral portion includes a protection circuit, The protection circuit is configured by alternately arranging a first gate electrode portion arranged in the order of the first gate electrode and the second gate electrode and a second gate electrode portion arranged in the order of the second gate electrode and the first gate electrode. The source electrode and the drain electrode are formed in a comb-teeth shape that mesh with each other, so that the source electrode is arranged at a position overlapping with the first gate electrode and the drain electrode is arranged at a position overlapping with the second gate electrode.

2. The display device according to claim 1, The first channel region and the second channel region have the same shape and area, An area of ​​a portion where the first channel region overlaps with the source electrode is the same as an area of ​​a portion where the second channel region overlaps with the drain electrode.

3. The display device according to claim 1, The source electrode includes a first extension portion extending beyond the first channel region, and the drain electrode includes a second extension portion extending beyond the second channel region. A first extension width of the first extension portion is smaller than a second extension width of the second extension portion.

4. The display device according to claim 1, The transistor is a bottom-gate transistor in which the first and second gate electrodes are arranged between a substrate and the semiconductor layer, and the semiconductor layer is located between the first gate electrode and a source electrode and between the second gate electrode and a drain electrode.

5. The display device according to claim 1, The transistor is a top-gate transistor in which the first and second gate electrodes are arranged between the semiconductor layer and the source electrode and the drain electrode. The first gate electrode is located between the semiconductor layer and the source electrode, and the second gate electrode is located between the semiconductor layer and the drain electrode.

6. The display device according to any one of claims 1 to 5, The first gate electrode includes a first end portion and a second end portion that intersect the semiconductor layer and define the first channel region, and the source electrode covers the first end portion and the second end portion.

7. The display device according to any one of claims 1 to 5, The second gate electrode includes a first end portion and a second end portion intersecting the semiconductor layer and defining the second channel region, and the drain electrode covers the first end portion and the second end portion.

8. The display device according to any one of claims 1 to 5, The first gate electrode includes a first end and a second end that intersect the semiconductor layer and define the first channel region, the source electrode covers the first end and the second end, and The second gate electrode includes a first end portion and a second end portion intersecting the semiconductor layer and defining the second channel region, and the drain electrode covers the first end portion and the second end portion.

9. The display device according to any one of claims 1 to 5, The drain electrode is connected to the pixel electrode.

10. The display device according to claim 9, The drain electrode is connected to the semiconductor layer via a first contact hole, and the pixel electrode is connected to the drain electrode via a second contact hole. The first contact hole is located between the first channel region and the second contact hole.

11. The display device according to claim 9, A signal line for supplying a video signal to the plurality of pixels is formed in the pixel portion, and the source electrode is formed integrally with the signal line.

12. The display device according to any one of claims 1 to 5, The source electrode has an end portion facing the drain electrode, and the drain electrode has an end portion facing the source electrode, and the two end portions are chamfered.

13. A display device comprising A display panel having a pixel portion in which a plurality of pixels are arranged and a peripheral portion provided around the pixel portion; and A driving circuit is provided in the peripheral portion and drives the pixel. A transistor is provided in the pixel portion or the peripheral portion, the transistor comprising: a semiconductor layer having a first end and a second end; a first gate electrode overlapping the semiconductor layer at a position close to the first end; a second gate electrode overlapping the semiconductor layer at a position close to the second end; a source electrode connected to the first end; a drain electrode connected to the second end; and a metal component. The first and second gate electrodes are arranged on the first layer, The source electrode, the drain electrode, and the metal component are arranged on a second layer different from the first layer, The metal component is formed to cover at least a first channel region which is an overlapping region of the first gate electrode and the semiconductor layer and a second channel region which is an overlapping region of the second gate electrode and the semiconductor layer when viewed from above, The peripheral portion includes a protection circuit, The protection circuit is configured by alternately arranging a first gate electrode portion arranged in the order of the first gate electrode and the second gate electrode and a second gate electrode portion arranged in the order of the second gate electrode and the first gate electrode. The source electrode and the drain electrode are formed in a comb-teeth shape that mesh with each other, so that the source electrode is arranged at a position overlapping with the first gate electrode and the drain electrode is arranged at a position overlapping with the second gate electrode.

14. The display device according to claim 13, The first channel region and the second channel region have the same shape and area, An area of ​​a portion where the first channel region overlaps with the source electrode is the same as an area of ​​a portion where the second channel region overlaps with the drain electrode.

15. The display device according to claim 13, The source electrode includes a first extension portion extending beyond the first channel region, and the drain electrode includes a second extension portion extending beyond the second channel region. A first extension width of the first extension portion is smaller than a second extension width of the second extension portion.

16. The display device according to claim 13, The transistor is a bottom-gate transistor in which the first and second gate electrodes are arranged between a substrate and the semiconductor layer, and the semiconductor layer is located between the first gate electrode and a source electrode and between the second gate electrode and a drain electrode.

17. The display device according to claim 13, The transistor is a top-gate transistor in which the first and second gate electrodes are arranged between the semiconductor layer and the source electrode and the drain electrode. The first gate electrode is located between the semiconductor layer and the source electrode, and the second gate electrode is located between the semiconductor layer and the drain electrode.

18. The display device according to any one of claims 13 to 17, The drain electrode is connected to the pixel electrode.

19. The display device according to claim 18, The drain electrode is connected to the semiconductor layer via a first contact hole, and the pixel electrode is connected to the drain electrode via a second contact hole. The first contact hole is located between the first channel region and the second contact hole.

20. The display device according to claim 18, A signal line for supplying a video signal to the plurality of pixels is formed in the pixel portion, and the source electrode is formed integrally with the signal line.

21. The display device according to any one of claims 13 to 17, The first gate electrode includes a first end portion and a second end portion intersecting the semiconductor layer and defining the first channel region. The second gate electrode includes a first end portion and a second end portion intersecting the semiconductor layer and defining the second channel region. The metal component is provided to cover the first end and the second end of the first gate electrode and the first end and the second end of the second gate electrode.

22. The display device according to any one of claims 13 to 17, The first gate electrode includes a first end portion and a second end portion intersecting the semiconductor layer and defining the first channel region. The second gate electrode includes a first end portion and a second end portion intersecting the semiconductor layer and defining the second channel region. The metal member includes a first metal member covering a first end portion and a second end portion of the first gate electrode and a second metal member covering a first end portion and a second end portion of the second gate electrode.

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