Method for forming a semiconductor device

Abstract

A process for forming gate structures with varying pitches is provided. An exemplary method includes providing a workpiece having a substrate and semiconductor fins spaced apart from each other by isolation features; depositing a gate material layer over the workpiece; forming a patterned hard mask over the gate material layer, the patterned hard mask comprising elongated features with varying pitches; performing a first etching process using the patterned hard mask as an etching mask to form trenches through the gate material layer; performing a second etching process using the patterned hard mask as an etching mask to extend the trenches to the top surfaces of the isolation features; and performing a third etching process using the patterned hard mask to extend the trenches into the isolation features. The first etching process includes using carbon tetrafluoride and does not use oxygen. Embodiments of the present application also relate to methods of forming semiconductor devices.

Description

Technical Field

[0001] Embodiments of the present application relate to methods of forming semiconductor devices. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, each with smaller and more complex circuits than the previous one. Over the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be produced using a manufacturing process) has decreased. This scaling process generally provides benefits by increasing production efficiency and reducing associated costs.

[0003] This scaling down has also increased the complexity of processing and manufacturing ICs, and similar developments in IC processing and manufacturing are needed to achieve these advances. For example, double patterning or multiple patterning has been used to form patterned features of uniform size. First, a mandrel is formed over a hard mask layer. Then a spacer layer is deposited over the mandrel, including over the sidewalls of the mandrel. After removing the spacer layer deposited over the mandrel to expose the mandrel, the mandrel is selectively removed, leaving behind a patterned spacer layer lining the sidewalls of the mandrel. The patterned spacer layer is used as an etch mask to pattern the underlying hard mask layer. However, when gate structures of varying pitch are desired in a semiconductor device, etch loading effects may prevent uniform etching throughout the depth of the gate material used for the gate structure. Several conventional methods have been proposed to address this challenge, but they are not satisfactory in all aspects. Therefore, an improved method is needed. Summary of the Invention

[0004] Some embodiments of the present application provide a method of forming a semiconductor device, comprising: providing a workpiece, the workpiece comprising a substrate and a plurality of semiconductor fins located above the substrate, each of the plurality of semiconductor fins being separated from another of the plurality of semiconductor fins by an isolation feature;

[0005] Depositing a gate material layer over the workpiece, the gate material layer comprising a first thickness over the top surfaces of the plurality of semiconductor fins; forming a patterned hard mask over the gate material layer, the patterned hard mask comprising a first plurality of elongated features and a second plurality of elongated features; performing a first etching process using the patterned hard mask as an etching mask through the gate material layer to form trenches extending through approximately 90% and approximately 95% of the first thickness toward the top surfaces of the plurality of semiconductor fins; performing a second etching process using the patterned hard mask as an etching mask to extend the trenches to the top surfaces of the isolation features; and performing a third etching process using the patterned hard mask to extend the trenches into the isolation features; wherein the first plurality of elongated features comprise a first spacing and the second plurality of elongated features comprise a second spacing greater than the first spacing; wherein the first etching process comprises using carbon tetrafluoride at a pressure between 40 mTorr and 100 mTorr; and wherein the first etching process does not use oxygen.

[0006] Some other embodiments of the present application provide a method for forming a semiconductor device, comprising: providing a workpiece, the workpiece comprising: a substrate; a plurality of semiconductor fins located above the substrate, each of the plurality of semiconductor fins being separated from another of the plurality of semiconductor fins by an isolation feature; and a dielectric layer conformally disposed above the plurality of semiconductor fins; depositing a gate material layer above the workpiece, the gate material layer comprising a first thickness above top surfaces of the plurality of semiconductor fins; forming a patterned hard mask above the gate material layer, the patterned hard mask comprising a first plurality of elongated features and a second plurality of elongated features; performing a first etching process performing an etching process using the patterned hard mask as an etching mask to form a trench extending through a majority of the first thickness; performing a second etching process using the patterned hard mask as an etching mask to extend the trench to a top surface of the isolation feature; and performing a third etching process using the patterned hard mask to extend the trench into the isolation feature; wherein the first plurality of elongated features include a first pitch and the second plurality of elongated features include a second pitch greater than the first pitch; wherein the first etching process and the third etching process do not use oxygen, and the second etching process includes the use of oxygen.

[0007] Some further embodiments of the present application provide a method for forming a semiconductor device, comprising: providing a workpiece, the workpiece comprising: a substrate; a plurality of semiconductor fins located above the substrate, each of the plurality of semiconductor fins being separated from another of the plurality of semiconductor fins by an isolation feature; and a silicon oxide layer being conformally disposed above the plurality of semiconductor fins; depositing a gate material layer above the workpiece, the gate material layer comprising a first thickness above top surfaces of the plurality of semiconductor fins; forming a patterned hard mask above the gate material layer, the patterned hard mask comprising a first plurality of elongated features and a second plurality of elongated features; performing a first etching process, using the patterned hard mask to form a first etch layer; and a second etching process using the patterned hard mask as an etching mask to form a trench extending through a majority of the first thickness; a second etching process using the patterned hard mask as an etching mask to extend the trench to a top surface of the isolation feature; and a third etching process using the patterned hard mask to extend the trench into the isolation feature; wherein the first plurality of elongated features include a first spacing, the second plurality of elongated features include a second spacing, the second spacing being 1.1 to 2 times the first spacing; wherein the first etching process includes carbon tetrafluoride and does not use oxygen; and wherein the third etching process does not use oxygen and hydrogen bromide and includes chlorine. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Various aspects of the present invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale and are used for illustrative purposes only. In fact, the dimensions of various components may be arbitrarily increased or decreased for clarity of discussion.

[0009] Figure 1 is a flow chart of a method for manufacturing a semiconductor device according to various aspects of the present invention;

[0010] Figure 2 is a schematic perspective view of a workpiece for a semiconductor device according to various aspects of the present invention;

[0011] Figure 3A According to various aspects of the present invention, in Figure 1 a schematic top view of a portion of a workpiece during one of those manufacturing stages associated with the method;

[0012] Figure 3B and Figure 4-11 According to various aspects of the present invention, in Figure 1 Schematic partial cross-sectional views of a workpiece at various manufacturing stages of those manufacturing stages that are relevant for the method. DETAILED DESCRIPTION

[0013] It should be understood that the following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various embodiments and / or structures discussed. In addition, for the sake of simplicity and clarity, the various components may be arbitrarily drawn in different proportions.

[0014] Moreover, for ease of description, spatially relative terms such as "under," "beneath," "lower," "above," and "upper" may be used herein to easily describe the relationship of one element or component to another (or other) elements or components as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations shown in the figures. For example, if the device in the figures is turned over, elements described as "under" or "beneath" other elements or features can be oriented "above" the other elements or features. Thus, the exemplary term "under" can include both above and below. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein can be interpreted accordingly.

[0015] Furthermore, when "about," "approximately," or the like is used to describe a number or range of numbers, the term is intended to encompass numbers that are included within a reasonable range of the described number, such as within + / - 10% of the described number or other values ​​understood by those skilled in the art. For example, the term "about 5 nm" encompasses a size range from 4.5 nm to 5.5 nm.

[0016] Advances in semiconductor conductor manufacturing have been made to accommodate the reduction in size of semiconductor device components. When the reduction in size exceeds the resolution of photolithography, multiple patterning techniques have been used. For example, a double patterning lithography (DPL) process (e.g., a lithography-etch-lithography-etch (LELE) process, a self-aligned double patterning (SADP) process, a spacer-dielectric patterning (SIDP) process, other double patterning processes, or a combination thereof) can be used to form a patterned etch mask. Further iterations of the process steps can be implemented to form components of even smaller sizes. For example, a triple patterning process (e.g., a lithography-etch-lithography-etch-lithography-etch (LELELE) process, a self-aligned triple patterning (SATP) process, other triple patterning processes, or a combination thereof), other multiple patterning processes (e.g., a self-aligned quadruple patterning (SAQP) process), or a combination thereof) can be implemented. Typically, a multiple patterning process combines a photolithography process with a self-aligned process, thereby allowing the created pattern to be, for example, having a pitch smaller than that obtainable using a single direct photolithography process. For example, in some embodiments, a patterned sacrificial layer is formed over a substrate using a photolithography process, and spacers are formed next to the patterned sacrificial layer using, for example, a self-aligned process. The patterned sacrificial layer is then removed, and the spacers can be used as an etch mask to pattern underlying layers, such as a hard mask layer.

[0017] A limitation of the aforementioned multiple patterning techniques is that the resulting etch mask includes features of substantially uniform width. This is so because these features are the result of a self-aligned process that occurs on a scale that exceeds the resolution of the photolithographic process. Although (some) photolithographic processes in the multiple patterning techniques can dictate the spacing and intervals between features, it is powerless to change the size of the self-aligned features. In the above example, as the photolithographic process patterns the sacrificial layer, the size of the sacrificial layer features in the patterned sacrificial layer can be controlled by the photolithographic process. However, the photolithographic process has no effect on how the spacers are deposited above the sacrificial layer. Instead, the thickness and uniformity of the spacer layer are largely controlled by the material properties of the spacer layer and the process parameters that are uniformly distributed throughout the spacer layer. As a result, the sizes of the features in the spacer layer are largely uniform.

[0018] This limitation presents a challenge when gate structures with varying spacing are required in semiconductor devices. It has been observed that densely packed components and loosely packed components experience different etching rates due to different etching loads. In one mode of non-uniform etching loading, byproducts of the etching process can be redeposited at different rates on the lateral surfaces of the isolation region (i.e., the loosely packed region) and on the lateral surfaces of the dense region (i.e., the densely packed region), resulting in non-uniform lateral etching in different regions. In some cases, the byproduct redeposition rate in the isolation region is greater than the byproduct redeposition rate in the dense region, and the etching rate of the isolation region is slower than the etching rate of the dense region. To compensate for non-uniform lateral etching, additional photolithography and etching processes can be used to trim the patterned hard mask. In an example where the isolation region is etched at a lower rate, the patterned hard mask components in the isolation region are trimmed to have smaller dimensions. However, such additional photolithography and trimming processes may involve increased costs and may reduce manufacturing yields. High-resolution photolithography techniques with smaller wavelengths can also be used to accurately form etching mask components with varying dimensions to compensate for non-uniform lateral etching. However, the use of such high-resolution photolithography also involves increased costs.

[0019] The present invention provides a process for uniformly etching through a gate material layer using etch mask features of varying spacing but similar size, thereby forming a gate structure with substantially straight sidewalls. An exemplary process includes: a first etch process for etching through the gate material layer above the top surface of an active area (e.g., a fin or semiconductor fin); a second etch process for etching the gate material layer to the top surface of an isolation feature; and a third etch process for etching into the isolation feature. The first etch process includes the use of carbon tetrafluoride and is oxygen (O2)-free. Additionally, the first etch process is performed under increased pressure to reduce lateral etching. The second etch process includes a nitridation process to nitride the dummy gate dielectric layer to protect the active area. The third etch process is oxygen (O2)-free and hydrogen bromide (HBr)-free. Instead, the third etch process includes the use of chlorine gas and is of very short duration. By avoiding the use of costly alternative processes, the process according to the present invention provides an economical alternative for forming gate structures of varying spacing with substantially vertical sidewalls. In other words, the process according to the present invention offers circuit designers a greater degree of design freedom without significantly increasing manufacturing costs.

[0020] Various aspects of the present invention will now be described in more detail with reference to the accompanying drawings. Figure 1is a flow chart of a method 100 for manufacturing a semiconductor device according to various aspects of the present invention. In some embodiments, the semiconductor device includes a multi-gate transistor in which a gate structure surrounds multiple sides of an active region in its channel region. Examples of multi-gate transistors include fin field effect transistors (FinFETs) or gate-all-around (GAA) transistors. Method 100 is only an example and is not intended to limit the present invention to what is explicitly described in method 100. Other steps may be provided before, during, and after method 100, and some of the steps described may be moved, replaced, or deleted for additional embodiments of method 100. For simplicity, not all steps are described in detail herein. Figure 2 、 Figure 3A 、 Figure 3B ,and Figure 4-11 Method 100 is described with reference to perspective, top, and partial cross-sectional views of a workpiece 200 shown in FIG. Since a semiconductor device will be formed from the workpiece 200 , the workpiece 200 may be referred to as a semiconductor device 200 as the context requires.

[0021] The semiconductor device 200 may be included in a microprocessor, memory, and / or other integrated circuit (IC) device. In some embodiments, the semiconductor device 200 may be part of an IC chip, a system on a chip (SoC), or a portion thereof, which includes various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high voltage transistors, high frequency transistors, other suitable components, or combinations thereof. For clarity, the following has been simplified. Figure 2 、 Figure 3A 、 Figure 3B ,and Figure 4-11 Other components may be added to the semiconductor device 200, and some components described below may be replaced, modified, or deleted in other embodiments of the semiconductor device 200.

[0022] refer to Figure 1 、 Figure 2 、 Figure 3A ,and Figure 3B The method 100 includes block 102 where a workpiece 200 including a plurality of fins 204 is received. Figure 2 、 Figure 3A ,and Figure 3BAs shown, the workpiece 200 includes a substrate 202. In the described embodiment, the substrate 202 is a bulk substrate including silicon. Alternatively, in some embodiments, the substrate 202 includes a bulk substrate (including, for example, silicon) and one or more material layers disposed above the bulk substrate. For example, the one or more material layers may include a semiconductor layer stack having various semiconductor layers (such as a heterostructure) disposed above the bulk substrate, wherein the semiconductor layer stack is subsequently patterned to form a fin. The semiconductor layer may include any suitable semiconductor material, such as silicon, germanium, silicon germanium, other suitable semiconductor materials, or a combination thereof. Depending on the design requirements of the semiconductor device 200, the semiconductor layers may include the same or different materials, etching rates, atomic percent compositions, weight percent compositions, thicknesses, and / or configurations. In some embodiments, the semiconductor layer stack includes alternating semiconductor layers, such as a semiconductor layer composed of a first material and a semiconductor layer composed of a second material. For example, the semiconductor layer stack alternates silicon layers and silicon germanium layers (e.g., Si / SiGe / Si from bottom to top). In some embodiments, the semiconductor layer stack includes semiconductor layers of the same material but with alternating atomic percentage compositions, such as a semiconductor layer with a first atomic percentage composition and a semiconductor layer with a second atomic percentage composition. For example, the semiconductor layer stack includes silicon germanium layers with alternating silicon atomic percentages and / or germanium atomic percentages (e.g., Si from bottom to top). a Ge b / Si c Ge d / Si a Ge b , where a and c are different atomic percentages of silicon, and b and d are different atomic percentages of germanium). Alternatively or additionally, bulk substrate 202 and / or one or more material layers include another elemental semiconductor, such as germanium; a compound semiconductor, such as silicon carbide, silicon phosphide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, zinc oxide, zinc selenide, zinc sulfide, zinc telluride, cadmium selenide, cadmium sulfide, and / or cadmium telluride; an alloy semiconductor, such as SiGe, SiPC, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; other III-V materials; other II-V materials; or combinations thereof. Alternatively, substrate 202 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The semiconductor-on-insulator substrate may be fabricated using separation by implantation of oxygen (SIMOX), wafer bonding, and / or other suitable methods.

[0023] In some embodiments, the plurality of fins 204 can be formed from the substrate 202 or by depositing a semiconductor layer over the substrate 202 using a multiple patterning process, such as a double patterning lithography (DPL) process (e.g., a lithography-etch-lithography-etch (LELE) process, a self-aligned double patterning (SADP) process, a spacer-dielectric patterning (SIDP) process, other double patterning processes, or combinations thereof), a triple patterning process (e.g., a lithography-etch-lithography-etch-lithography-etch (LELELE) process, a self-aligned triple patterning (SATP) process, other triple patterning processes, or combinations thereof), other multiple patterning processes (e.g., a self-aligned quadruple patterning (SAQP) process), or combinations thereof. Typically, a multiple patterning process combines a lithography process with a self-aligned process, thereby allowing the creation of patterns that can, for example, have a pitch smaller than that achievable using a single direct lithography process. For example, in some embodiments, a patterned sacrificial layer is formed over the substrate using a lithography process, and spacers are formed adjacent to the patterned sacrificial layer using, for example, a self-aligned process. The patterned sacrificial layer is then removed, and the spacers can be used to pattern the underlying layers. In some embodiments, a directed self-assembly (DSA) technique is implemented during the multiple patterning processes. Since each of the multiple fins 204 is formed from a semiconductor material that forms the substrate 202 or a semiconductor layer deposited above the substrate 202, it can also be referred to as a semiconductor fin or semiconductor fin structure. For the sake of brevity, a detailed description of the formation process of the multiple fins 204 is omitted.

[0024] refer to Figure 2 , Figure 2 FIG is a perspective view of a workpiece 200 including a plurality of fins 204. The fins 204 extend upward from the substrate 202 along the Z direction and extend parallel to each other along the X direction. Figure 2 Five fins are shown in FIG. The present invention is not limited thereto and fully contemplates workpieces including more or fewer fins 204. Isolation features 206 (i.e., shallow trench isolation (STI) features) are formed between adjacent fins 204 to provide electrical isolation and mechanical support. Thus, isolation features 206 include isolation materials such as silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation materials (e.g., including silicon, oxygen, nitrogen, carbon, and / or other suitable isolation components), or combinations thereof. Figure 2 As shown, the isolation feature 206 is pulled back to form the inter-fin groove 205, so that a portion of each of the plurality of fins rises above the top surface of the isolation feature 206. Figure 3A The top view also shows that the plurality of fins 204 extend along the X-direction, with each fin being separated from adjacent fins by isolation features 206 . Figure 3BA Y-direction view along the cross section II' is provided along one of the plurality of fins 204. Since the cross section passes through one of the plurality of fins 204, Figure 3B The isolation member 206 is not visible. To illustrate the various components of the present invention, the following figures, including Figure 4-11 ,like Figure 3B As such, it is a partial cross-sectional view of the fin 204 of the workpiece 200 through the cross section II′.

[0025] refer to Figure 1 and Figure 4 , the method 100 includes block 104, where a gate material layer 208 is deposited over the plurality of fins 204. Figure 4 As shown, a gate material layer 208 is deposited over the workpiece 200, including being deposited over the top surface of the isolation feature 206, being deposited over the top surface of each of the plurality of fins 204, and being deposited into the inter-fin recesses 205 (e.g., Figure 2 Shown, but not shown in Figure 4 In some embodiments employing a gate-last process or a gate replacement process, the gate material layer 208 is intended to form a dummy gate stack and may include polysilicon. The dummy gate structure serves as a placeholder for the functional gate structure throughout a portion of the manufacturing process and is replaced by the functional gate stack at a later point. The dummy gate dielectric layer 207 may be blanket deposited over the workpiece 200 before the gate material layer 208 is deposited. Figure 4 As shown, along section II', a dummy gate dielectric layer 207 is disposed between the top surface of the fin 204 and the gate material layer 208. The dummy gate dielectric layer 207 is also disposed over the sidewalls of the plurality of fins 204. In some embodiments, the dummy gate dielectric layer 207 may include silicon oxide deposited using thermal oxidation or a suitable process.

[0026] Still refer to Figure 1 and Figure 4 , the method 100 includes block 106, where a hard mask layer 210 is deposited over the gate material layer 208. In some embodiments, the hard mask layer 210 is patterned to form a patterned hard mask layer 210 to be used as an etch mask for patterning the gate material layer 208. In some embodiments not shown, the hard mask layer 210 can be a single layer formed of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon oxycarbonitride, or a suitable dielectric material. Figure 4 In some alternative embodiments shown, the hard mask layer 210 may be multiple layers. Figure 4As shown, the hard mask layer 210 includes a first hard mask layer 212 and a second hard mask layer 214. In some embodiments, the first hard mask layer 212 is formed of silicon oxide, and the second hard mask layer is formed of a nitrogen-containing dielectric material such as silicon nitride or silicon oxynitride. Each of the first hard mask layer 212 and the second hard mask layer 214 can be deposited using chemical vapor deposition (CVD), low pressure CVD (LPCVD), plasma enhanced CVD (PECVD), other suitable processes, or combinations thereof.

[0027] refer to Figure 1 and Figure 4 , method 100 includes box 108, in which mandrel parts 216 (including a first plurality of mandrel parts 2161, a second plurality of mandrel parts 2162, and a third plurality of mandrel parts 2163) are formed over the hard mask layer 210. Each of the first plurality of mandrel parts 2161 has a first width W1 along the X direction. Each of the second plurality of mandrel parts 2162 has a second width W2 along the X direction. Each of the third plurality of mandrel parts 2163 has a third width W3 along the X direction. The third width W3 is greater than the second width W2, and the second width W2 is greater than the first width W1. In some cases, the ratio of the second width W2 to the first width W1 is between about 1.1 and about 2.0, and the ratio of the third width W3 to the first width W1 is between about 1.1 and about 2.0. Note that although the first plurality of mandrel parts 2161, the second plurality of mandrel parts 2162, and the third plurality of mandrel parts 2163 are Figure 4 As shown in FIG. 1 , the two components are adjacent to each other on the workpiece 200, but the present invention is not limited thereto. Figure 4 It is merely a representative illustration of mandrel components that can be used to form varying widths in different areas of the same workpiece 200 .

[0028] The mandrel component 216 may be formed in the following example process. A sacrificial layer is deposited on the hard mask layer 210 by spin coating, chemical vapor deposition (CVD), or a suitable deposition process. The sacrificial layer may be formed by a layer having a thickness that is substantially the same as that of the hard mask layer 210 or the spacer layer ( Figure 5The sacrificial layer is formed of a material having a different etch selectivity than that of the hard mask layer 218 shown in FIG. 218 , so that the sacrificial layer can be patterned or removed without damaging the hard mask layer 210 and the spacer layer. In some embodiments, the sacrificial layer can be a suitable semiconductor material (e.g., silicon, germanium, or amorphous silicon), a dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide), other suitable materials, or a combination thereof. The sacrificial layer is then patterned to form the core shaft component 216. The sacrificial layer is patterned using a photolithography process. A photoresist layer is deposited over the sacrificial layer using spin coating, and then the photoresist layer is baked in a pre-exposure baking process. The photoresist layer can be a single layer or multiple layers, such as three layers. The pre-baked photoresist layer is then exposed to radiation, which is reflected by a patterned photomask or transmitted by a patterned photomask. The exposed photoresist layer is then baked in a post-exposure baking process and developed in a developing process. The radiation source can be an excimer laser source, an ultraviolet (UV) source, a deep ultraviolet (DUV) source, or an extreme ultraviolet (EUV) source. Since the photoresist layer is selected to be sensitive to radiation, during the development process, the exposed (or unexposed) portion of the photoresist layer undergoes chemical changes, thereby dissolving in the developer solution. The resulting patterned photoresist layer has a pattern corresponding to the pattern of the mask. Then, during the etching process, the patterned photoresist layer can be used as an etching mask to remove parts of the sacrificial layer below. The etching process can include a dry etching process (such as a reactive ion etching (RIE) process), a wet etching process, other suitable etching processes, or a combination thereof. After the etching process, the patterned photoresist layer can be removed by ashing or a suitable method. Alternatively, the exposure process can implement maskless lithography, electron beam writing, ion beam writing, and / or nano-printing technology. Figure 4 As shown, since the mandrel member 216 is formed by a photolithography process, the mandrel member may be allowed to have different widths along the X direction.

[0029] refer to Figure 1 、 Figure 5 ,and Figure 6 , the method 100 includes block 110, wherein a first plurality of spacer components 2181, a second plurality of spacer components 2182, and a third plurality of spacer components 2183 are formed over the hard mask layer 210. Figure 5In some embodiments, a spacer layer 218 is conformally deposited over the workpiece 200, including over the top surface and sidewalls of the mandrel features 216, using spin coating, chemical vapor deposition (CVD), or a suitable deposition process. The spacer layer 218 can be formed from a material having an etch selectivity different from that of the mandrel features 216, thereby allowing the mandrel features 216 to be selectively removed without damaging the spacer layer 218. Furthermore, the material of the spacer layer 218 can be selected to have an etch selectivity different from that of the hardmask layer 210, thereby allowing the spacer features formed from the spacer layer 218 to serve as an etch mask for the hardmask layer 210. In some embodiments, the spacer layer 218 can be a suitable semiconductor material (e.g., silicon, germanium, or amorphous silicon), a dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide), other suitable materials, or combinations thereof.

[0030] Now refer to Figure 6 After depositing the spacer layer 218, an anisotropic etch-back process may be performed to remove excess spacer layer 218 on the hard mask layer 210 and on the top surface of the mandrel features 216. The etch-back process is performed such that the mandrel features 216 are exposed from the spacer layer portions extending along the sidewalls of the mandrel features 216. The mandrel features 216 are then selectively removed, leaving a patterned spacer layer 218 comprising a first plurality of spacer features 2181, a second plurality of spacer features 2182, and a third plurality of spacer features 2183. Figure 6 In some embodiments represented, the first plurality of spacer components 2181 can be characterized by a first pitch P1, the second plurality of spacer components 2182 can be characterized by a second pitch P2, and the third plurality of spacer components 2183 can be characterized by a third pitch P3. Figure 4-Figure 6As can be seen, first pitch P1 substantially corresponds to first width W1, second pitch P2 substantially corresponds to second width W2, and third pitch P3 substantially corresponds to third width W3. In some cases, first pitch P1 is substantially equal to first width W1 and the thickness of spacer layer 218; second pitch P2 is substantially equal to second width W2 and the thickness of spacer layer 218; and third pitch P3 is substantially equal to third width W3 and the thickness of spacer layer 218. In some embodiments, the ratio of second pitch P2 to first pitch P1 is between approximately 1.1 and approximately 2.0, and the ratio of third pitch P3 to first pitch P1 is between approximately 1.1 and approximately 2.0. While second pitch P2 and third pitch P3 share the same range, in the illustrated embodiment, third pitch P3 is greater than second pitch P2. The difference between first pitch P1 and either second pitch P2 or third pitch P3 is at least approximately 10%, which is significant enough to allow the resulting device to exhibit different characteristics or functionality. Meanwhile, the second pitch P2 or the third pitch P3 is less than approximately twice the first pitch P1 , so that the device density is not affected by the increased pitch.

[0031] refer to Figure 1 and Figure 7 The method 100 includes block 112, wherein the hard mask layer 210 is patterned using the first plurality of spacer features 2181, the second plurality of spacer features 2182, and the third plurality of spacer features 2183 as an etch mask. In some embodiments, the hard mask layer 210, including the first hard mask layer 212 and the second hard mask layer 214, can be etched through the first plurality of spacer features 2181, the second plurality of spacer features 2182, and the third plurality of spacer features 2183 using a dry etch process, a wet etch process, or a suitable process. Exemplary dry etching processes can use a fluorine-containing precursor (e.g., CF4, SF6, NF3, CH2F2, CHF3, and / or C2F6), an oxygen-containing precursor, a chlorine-containing precursor (e.g., Cl2, CHCl3, CCl4, and / or BCl3), a bromine-containing precursor (e.g., HBr and / or CHBR3), an iodine-containing precursor, other suitable precursors (which can be used to generate an etchant gas and / or an etching plasma), or a combination thereof. The exemplary wet etching process implements an etching solution comprising TMAH, NH4OH, H2O2, H2SO4, HF, HCl, other suitable wet etching components, or combinations thereof. Figure 7As shown, the operation at block 112 transfers the pattern of the first plurality of spacer features 2181, the second plurality of spacer features 2182, and the third plurality of spacer features 2183 to the hard mask layer 210, resulting in a patterned hard mask 220 comprising a first plurality of hard mask features 2201, a second plurality of hard mask features 2202, and a third plurality of hard mask features 2203. Similar to the first plurality of spacer features 2181, the second plurality of spacer features 2182, and the third plurality of spacer features 2183, the first plurality of hard mask features 2201 comprises a first pitch P1, the second plurality of hard mask features 2202 comprises a second pitch P2, and the third plurality of hard mask features 2203 comprises a third pitch P3. Figure 7 As shown, the gate material layer 208 underlying the first plurality of hard mask features 2201 , the second plurality of hard mask features 2202 , and the third plurality of hard mask features 2203 includes a first thickness ( T1 ) measured from a top surface of the fin 204 .

[0032] refer to Figure 1 and Figure 8 , the method 100 includes a box 114, in which a first etching process 300 is performed using the patterned hard mask 220 as an etching mask. In some embodiments, the first etching process 300 is a main etching process that etches the second thickness T2 from the top surface height Z1 of the gate material layer 208 to the height Z2 in a top-down manner. In some cases, the second thickness T2 is about 90% and about 95% of the first thickness T1. That is, at the end of the first etching process 300, a limited or measurable amount of the gate material layer remains above the top surface of the plurality of fins 204. In order to easily remove the byproducts of the first etching process 300 of the gate material layer 208, the first etching process includes a dry etching process using carbon tetrafluoride (CF4) as an etchant. In conventional processes, it is not preferred to use carbon tetrafluoride (CF4) in the main etching process because it will cause strong lateral etching, which may prematurely destroy the gate structure ( Figure 11230 shown). In accordance with the present invention, the pressure of the first etch process 300 is increased from less than 20 mTorr in conventional processes to between about 40 mTorr and about 100 mTorr. It can be observed that the increased process pressure of the third etch process 500 reduces the mean free path of carbon tetrafluoride, thereby mitigating lateral etching associated with the use of carbon tetrafluoride. The disclosed pressure range (i.e., between about 40 mTorr and about 100 mTorr) is selected so that the pressure of the first etch process 300 is at least twice the conventional pressure range to ensure that there is a detectable difference in the etching characteristics. At the same time, the pressure range is selected so that the pressure of the first etch process 300 does not unduly reduce the mean free path and thereby excessively reduce the etch rate. The increased process pressure at block 114 requires increased energy to ignite the plasma. In some embodiments, the first etching process 300 and the third etching process 500 may include using an inductively coupled plasma (ICP) with a power in the range between about 400 W and about 3500 W, or using a capacitively coupled plasma (CCP) with a power in the range between about 500 W and about 5500 W. When the ICP or CCP power level drops below the disclosed range, the etching rate may be unduly reduced and the process time may increase. The increase in process time will result in an increase in production costs. When the ICP or CCP power level increases above the disclosed range, the etching rate may be unduly increased and the desired etching characteristics may be lost, resulting in an undesirable fin sidewall profile.

[0033] Although lateral etching may be a concern for the first etching process 300, the first etching process 300 does not use oxygen (O2), which is known to produce more byproducts that passivate the sidewalls of the gate structure 230 (e.g., Figure 11 As shown). In some embodiments, in addition to carbon tetrafluoride (CF4), the first etching process 300 can further include hydrogen bromide (HBr) and chlorine (Cl2). In some cases, the first etching process 300 includes 200 sccm (standard cubic centimeters per minute) of hydrogen bromide and about 20 sccm to 50 sccm of carbon tetrafluoride. Figure 8 As shown, the first etching process forms a first trench 241 defined between two of the first plurality of hard mask features 2201, a second trench 242 defined between two of the second plurality of hard mask features 2202, and a third trench 243 defined between two of the third plurality of hard mask features 2203 at block 114. Each of the first trench 241, the second trench 242, and the third trench 243 has a depth substantially equal to the second thickness T2. As described above, the second thickness T2 is about 90% to about 95% of the first thickness T1.

[0034] refer to Figure 1 、 Figure 9 ,and Figure 10 , the method 100 includes block 116, wherein a second etching process 400 is performed using the patterned hard mask 220 as an etching mask. Figure 9 . In some embodiments, the second etching process 400 is a soft landing etching process that etches from height Z2 to height Z3 at the top surface of the isolation feature 206 in a top-down manner. Unlike the first etching process 300, the second etching process 400 does not contain carbon tetrafluoride and includes oxygen (O2) to enhance lateral passivation. In some embodiments, the second etching process 400 can include the use of chlorine (Cl2), oxygen (O2), and hydrogen bromide (HBr). In some cases, the process pressure for the second etching process 400 is also between about 40 millitorr (mTorr) and about 100 mTorr for similar reasons as described above with respect to block 114. As Figure 9 As shown, the second etching process 400 extends the first trench 241 , the second trench 242 , and the third trench 243 to a height Z3 (ie, the top surface of the isolation feature 206 ).

[0035] Now refer to Figure 10 . In some embodiments, to prevent accidental damage to the plurality of fins 204, the second etching process 400 may optionally include a nitridation process 410, which includes introducing a nitrogen-containing reagent, such as nitrogen (N2) or ammonia (NH3), to nitride the dummy gate dielectric layer 207. In the case where the dummy gate dielectric layer 207 is formed of silicon oxide, the nitridation process 410 may introduce nitrogen into the dummy gate dielectric layer 207 so that at least the outer portion of the dummy gate dielectric layer 207 is formed of silicon oxynitride (SiON). Since silicon oxynitride is etched at an etch rate slower than that of silicon oxide during the second etching process 400, the nitridation process 410 may protect the fins 204 from damage caused by the second etching process 400. The nitridation process 410 may be incorporated into the second etching process 400. In this regard, the second etching process 400 may include an etching cycle (i.e., using the above-mentioned etchants, such as chlorine, hydrogen bromide, and oxygen) and a nitridation cycle (i.e., the nitridation process 410). In one example, the second etch process 400 can begin with an etch cycle, followed by a nitridation cycle, followed by another etch cycle.Other arrangements of etch cycles and nitridation cycles are fully contemplated.

[0036] refer to Figure 1 and Figure 11, the method 100 includes block 118, wherein a third etching process 500 is performed using the patterned hard mask 220 as an etching mask. In some embodiments, the third etching process 500 is an over-etching process that etches into the top surface of the isolation feature 206 in a top-down manner. That is, the third etching process 500 further extends the first trench 241, the second trench 242, and the third trench 243 to at least partially enter the isolation feature 206. At the end of the operation of block 118, the gate structure 230 is substantially formed. Figure 11 As shown, the gate structure 230 includes a first plurality of gate structures 2301 having a first pitch P1, a second plurality of gate structures 2302 having a second pitch P2, and a third plurality of gate structures 2303 having a third pitch P3. According to the present invention, the purpose of the third etching process 500 is to laterally etch the sidewalls toward the bottom of the first trench 241, the second trench 242, and the third trench 243. In some embodiments, the third etching process 500 includes the use of chlorine gas (Cl2) supplied between about 200 sccm and about 500 sccm. In order to prevent accidental damage to the portion of the gate structure 230 that has been formed in the first etching process 300 and the second etching process 400, the third etching process 500 can last between about 10 seconds and about 20 seconds. In some embodiments, the third etching process 500 does not include the use of hydrogen bromide (HBr) and oxygen gas (O2). The etching rate of the former is less than that of chlorine gas, and the role of the latter is to enhance lateral passivation. In some cases, the third etch process 500 may also be performed at a pressure between about 40 mTorr and about 100 mTorr for reasons similar to those described above with respect to block 114. As described above, this increased pressure range may reduce the mean free path of the etchant and may decrease the etch rate.

[0037] refer to Figure 1, method 100 includes block 120, in which additional processes are performed. The additional processes may include depositing gate spacers over gate structure 230, depositing an interlayer dielectric (ILD) layer over workpiece 200, forming source / drain trenches adjacent to gate structure 230, forming source / drain epitaxial features, depositing another interlayer dielectric (ILD) layer, replacing the gate stack with a functional gate structure, forming source / drain contacts to the source / drain epitaxial features, and forming a gate contact to the functional gate structure. Because the functional gate structure replaces gate structure 230, it substantially inherits the shape, size, and spacing of gate structure 230. At the end of method 100, the functional gate structures of semiconductor device 200 include a first plurality of functional gate structures replacing the first plurality of gate structures 2301, a second plurality of functional gate structures replacing the second plurality of gate structures 2302, and a third plurality of functional gate structures replacing the third plurality of gate structures 2303. As a result, the first plurality of functional gate structures may have a first pitch P1 , the second plurality of functional gate structures may have a second pitch P2 , and the third plurality of functional gate structures may have a third pitch P3 .

[0038] The process of the present invention provides benefits. Examples of the process of the present invention include a first etching process, a second etching process, and a third etching process. The first etching process is a main etching process that etches through most of the depth of the gate material layer above the fin to form a trench. The first etching process includes the use of carbon tetrachloride (CF4) for removing byproducts at any time and increasing the pressure to reduce lateral etching. The first etching process does not include the use of oxygen, which may cause more byproducts to be re-deposited. The second etching process is a soft landing etching process that extends the trench to the top surface of the isolation component. The second etching process includes the use of oxygen and may include a nitriding process to protect the fin from damage. The third etching process is an over-etching process that extends the trench partially into the isolation component. The third etching process includes the use of chlorine (Cl2) and a shorter etching time. The process of the present invention can be used to etch through the gate material layer to form gate structures of different spacings without the need for additional photolithography steps.

[0039] In one aspect, the present invention provides a method. The method includes providing a workpiece comprising a substrate and a plurality of semiconductor fins located above the substrate, wherein each of the plurality of semiconductor fins is separated from another of the plurality of semiconductor fins by an isolation feature; depositing a gate material layer above the workpiece, wherein the gate material layer comprises a first thickness above top surfaces of the plurality of semiconductor fins; forming a patterned hard mask above the gate material layer, wherein the patterned hard mask comprises a first plurality of elongated features and a second plurality of elongated features; performing a first etching process using the patterned hard mask as an etching mask through the gate material layer to form trenches extending through approximately 90% and approximately 95% of the first thickness toward the top surfaces of the plurality of semiconductor fins; performing a second etching process using the patterned hard mask as an etching mask to extend the trenches to the top surfaces of the isolation features; and performing a third etching process using the patterned hard mask to extend the trenches into the isolation features. The first plurality of elongated features comprise a first pitch, and the second plurality of elongated features comprise a second pitch greater than the first pitch. The first etching process includes using carbon tetrafluoride and a pressure between about 40 mTorr and about 100 mTorr, and the first etching process does not use oxygen.

[0040] In some embodiments, the first etching process further comprises using hydrogen bromide and chlorine. In some embodiments, the ratio of the second spacing to the first spacing is between about 1.1 and about 2.0. In some cases, the second etching process comprises a dry etching process using chlorine, hydrogen bromide, or oxygen. In some embodiments, the second etching process comprises a nitriding process using a nitrogen-containing reagent. In some embodiments, the nitrogen-containing reagent comprises nitrogen (N2). In some embodiments, the third etching process comprises chlorine. In some embodiments, the third etching process does not use oxygen and hydrogen bromide.

[0041] In another aspect, the present invention provides a method. The method includes providing a workpiece comprising: a substrate; a plurality of semiconductor fins located above the substrate, each of the plurality of semiconductor fins being separated from another of the plurality of semiconductor fins by an isolation feature; and a dielectric layer conformally disposed above the plurality of semiconductor fins; depositing a gate material layer over the workpiece, wherein the gate material layer comprises a first thickness above top surfaces of the plurality of semiconductor fins; forming a patterned hard mask over the gate material layer, wherein the patterned hard mask comprises a first plurality of elongated features and a second plurality of elongated features; performing a first etching process using the patterned hard mask as an etching mask to form a trench extending through a majority of the first thickness; performing a second etching process using the patterned hard mask as an etching mask to extend the trench to the top surface of the isolation feature; and performing a third etching process using the patterned hard mask to extend the trench into the isolation feature. The first plurality of elongated features comprise a first pitch, and the second plurality of elongated features comprise a second pitch greater than the first pitch. The first etching process and the third etching process do not utilize oxygen, and the second etching process utilizes oxygen.

[0042] In some embodiments, the first etching process includes using hydrogen bromide, carbon tetrafluoride and chlorine. In some embodiments, the first etching process includes a pressure between about 40mTorr and about 100mTorr. In some cases, the ratio of the second spacing to the first spacing is between about 1.1 and about 2.0. In some embodiments, the second etching process includes a dry etching process using chlorine, hydrogen bromide, or oxygen. In some embodiments, the third etching process includes chlorine. In some embodiments, the second etching process includes a nitriding process to introduce nitrogen into the dielectric layer. In some cases, the nitriding process includes using nitrogen (N2).

[0043] In another aspect, the present invention provides a method. The method includes providing a workpiece comprising: a substrate; a plurality of semiconductor fins located above the substrate, each of the plurality of semiconductor fins being separated from another of the plurality of semiconductor fins by an isolation feature; and a silicon oxide layer conformally disposed above the plurality of semiconductor fins; depositing a gate material layer over the workpiece, wherein the gate material layer comprises a first thickness above top surfaces of the plurality of semiconductor fins; forming a patterned hard mask over the gate material layer, wherein the patterned hard mask comprises a first plurality of elongated features and a second plurality of elongated features; performing a first etching process using the patterned hard mask as an etching mask to form a trench extending through a majority of the first thickness; performing a second etching process using the patterned hard mask as an etching mask to extend the trench to the top surface of the isolation feature; and performing a third etching process using the patterned hard mask to extend the trench into the isolation feature. The first plurality of elongated features comprises a first pitch, and the second plurality of elongated features comprises a second pitch, the second pitch being approximately 1.1 times to approximately 2 times the first pitch. The first etching process comprises carbon tetrafluoride and does not use oxygen. The third etching process does not use oxygen and hydrogen bromide, and includes chlorine.

[0044] In some embodiments, the first etching process further comprises using hydrogen bromide and chlorine. In some embodiments, the first etching process comprises a pressure between about 40 mTorr and about 100 mTorr. In some cases, the second etching process comprises a nitridation process to convert a portion of the silicon oxide layer into silicon oxynitride.

[0045] The features of several embodiments have been summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use this disclosure as a basis for designing or modifying other processes and structures for performing the same or similar purposes and / or achieving the same or similar advantages as the present disclosure. Those skilled in the art will also appreciate that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and modifications may be made without departing from the spirit and scope of the present disclosure.

Claims

1. A method for forming a semiconductor device, comprising: providing a workpiece comprising a substrate, a plurality of semiconductor fins over the substrate, and a dielectric layer conformally disposed over the plurality of semiconductor fins, each of the plurality of semiconductor fins being spaced apart from another of the plurality of semiconductor fins by an isolation feature; depositing a gate material layer over the workpiece, the gate material layer comprising a first thickness above top surfaces of the plurality of semiconductor fins; forming a patterned hard mask over the gate material layer, the patterned hard mask comprising a first plurality of elongated features and a second plurality of elongated features; performing a first etching process through the gate material layer to form trenches using the first and second plurality of elongated members as etching masks, the trenches extending through between about 90% and about 95% of the first thickness toward the top surfaces of the plurality of semiconductor fins; performing a second etching process using the first plurality of elongated members and the second plurality of elongated member patterns as etching masks to extend the trenches through the dielectric layer to the top surfaces of the isolation features; as well as performing a third etching process using the first and second pluralities of elongated features to extend the trench into the isolation feature; wherein the first plurality of elongated members comprises a first spacing, and the second plurality of elongated members comprises a second spacing greater than the first spacing; The first etching process includes using carbon tetrafluoride without using oxygen, and the pressure is between 40 mTorr and 100 mTorr; wherein the second etching process includes using oxygen; The second etching process includes a nitridation process to convert the outer portion of the dielectric layer into silicon oxynitride, and during the second etching process, the silicon oxynitride is etched at an etching rate slower than an etching rate of silicon oxide.

2. The method according to claim 1, wherein The first etching process further includes using hydrogen bromide and chlorine.

3. The method according to claim 1, wherein A ratio of the second spacing to the first spacing is between 1.1 and 2.

0.

4. The method according to claim 1, wherein The second etching process includes a dry etching process using chlorine or hydrogen bromide.

5. The method according to claim 1, wherein The second etching process includes an etching period and a nitriding period.

6. The method according to claim 1, wherein The nitridation process uses a nitrogen-containing reagent, which includes nitrogen (N2).

7. The method according to claim 1, wherein The third etching process includes chlorine.

8. The method according to claim 7, wherein: The third etching process does not use oxygen and hydrogen bromide.

9. A method of forming a semiconductor device, comprising: An artifact is provided, the artifact comprising: substrate; a plurality of semiconductor fins over the substrate, each of the plurality of semiconductor fins being spaced apart from another of the plurality of semiconductor fins by an isolation feature; and a dielectric layer conformally disposed over the plurality of semiconductor fins; depositing a gate material layer over the workpiece, the gate material layer comprising a first thickness above top surfaces of the plurality of semiconductor fins; forming a patterned hard mask over the gate material layer, the patterned hard mask comprising a first plurality of elongated features and a second plurality of elongated features; performing a first etching process using the first and second pluralities of elongated members as etch masks to form trenches extending through a majority of the first thickness; performing a second etching process using the first and second pluralities of elongated features as etching masks to extend the trenches through the dielectric layer to the top surfaces of the isolation features; and performing a third etching process using the first and second pluralities of elongated features to extend the trench into the isolation feature; wherein the first plurality of elongated members comprises a first spacing, and the second plurality of elongated members comprises a second spacing greater than the first spacing; wherein the first etching process and the third etching process do not use oxygen, and the second etching process includes using oxygen; The second etching process includes a nitridation process to convert the outer portion of the dielectric layer into silicon oxynitride, and during the second etching process, the silicon oxynitride is etched at an etching rate slower than an etching rate of silicon oxide.

10. The method according to claim 9, wherein: The first etching process includes using hydrogen bromide, carbon tetrafluoride and chlorine.

11. The method according to claim 9, wherein The first etching process includes a pressure between 40 mTorr and 100 mTorr.

12. The method according to claim 9, wherein A ratio of the second spacing to the first spacing is between 1.1 and 2.

0.

13. The method according to claim 9, wherein: The second etching process includes a dry etching process using chlorine, hydrogen bromide, or oxygen.

14. The method according to claim 9, wherein The third etching process includes chlorine.

15. The method according to claim 9, wherein The second etching process includes an etching period and a nitriding period.

16. The method according to claim 9, wherein The nitridation process includes using nitrogen (N2) gas.

17. A method of forming a semiconductor device, comprising: An artifact is provided, the artifact comprising: substrate; a plurality of semiconductor fins over the substrate, each of the plurality of semiconductor fins being spaced apart from another of the plurality of semiconductor fins by an isolation feature; and a silicon oxide layer conformally disposed over the plurality of semiconductor fins; depositing a gate material layer over the workpiece, the gate material layer comprising a first thickness above top surfaces of the plurality of semiconductor fins; forming a patterned hard mask over the gate material layer, the patterned hard mask comprising a first plurality of elongated features and a second plurality of elongated features; performing a first etching process using the first and second pluralities of elongated members as etch masks to form trenches extending through a majority of the first thickness; performing a second etching process using the first and second plurality of elongated features as etching masks to extend the trenches through the silicon oxide layer to top surfaces of the isolation features; and performing a third etching process using the first and second pluralities of elongated features to extend the trench into the isolation feature; wherein the first plurality of elongated members comprises a first spacing, the second plurality of elongated members comprises a second spacing, and the second spacing is 1.1 to 2 times the first spacing; wherein the first etching process includes carbon tetrafluoride and does not use oxygen, and the second etching process includes using oxygen; wherein the third etching process does not use oxygen and hydrogen bromide and includes chlorine; The second etching process includes a nitridation process to convert an outer portion of the silicon oxide layer into silicon oxynitride, and during the second etching process, the silicon oxynitride is etched at an etching rate slower than an etching rate of silicon oxide.

18. The method according to claim 17, wherein The first etching process further includes using hydrogen bromide and chlorine.

19. The method according to claim 18, wherein The first etching process includes a pressure between 40 mTorr and 100 mTorr.

20. The method according to claim 17, wherein The second etching process includes an etching period and a nitriding period.

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