Semiconductor device and structure and method for manufacturing the same

Abstract

A semiconductor device includes a redistribution structure, the redistribution structure including: a conductive component; a dielectric layer; and an internal support within a first dielectric layer of the dielectric layer, wherein the internal support is free of passive devices and active devices; a first interconnect structure attached to a first side of the redistribution structure; a second interconnect structure attached to the first side of the redistribution structure, wherein the second interconnect structure is laterally adjacent to the first interconnect structure, wherein the internal support laterally overlaps the first interconnect structure and the second interconnect structure. Embodiments of the present invention also relate to semiconductor structures and methods of manufacturing the same.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices and structures and methods of manufacturing the same. Background Art

[0002] The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, allowing more components and more functions to be integrated into a given area. Integrated circuits with high functionality require many input / output pads. However, for applications where miniaturization is important, small packages may be required.

[0003] As the demand for shrinking electronic devices grows, the need for smaller and more creative semiconductor die packaging technologies has also emerged. An example of such a packaging system is package-on-package (PoP) technology. In a PoP device, a top semiconductor package is stacked on top of a bottom semiconductor package to provide a high level of integration and component density. PoP technology is generally capable of producing semiconductor devices with enhanced functionality and a small footprint on a printed circuit board (PCB). Summary of the invention

[0004] According to one aspect of an embodiment of the present invention, a semiconductor device is provided, comprising: a redistribution structure, comprising: a plurality of conductive components; a plurality of dielectric layers; and an internal support within a first dielectric layer of the plurality of dielectric layers, wherein the internal support is free of passive devices and active devices; a first interconnect structure attached to a first side of the redistribution structure; a second interconnect structure attached to a first side of the redistribution structure, wherein the second interconnect structure is laterally adjacent to the first interconnect structure, and wherein the internal support laterally overlaps the first interconnect structure and the second interconnect structure.

[0005] According to another aspect of an embodiment of the present invention, a semiconductor structure is provided, comprising: a plurality of core substrates attached to a first side of a redistribution structure, wherein the redistribution structure comprises: a plurality of first redistribution layers; a plurality of internal supports attached to at least one of the plurality of first redistribution layers, wherein the plurality of internal supports are not electrically connected to the plurality of first redistribution layers; and a plurality of second redistribution layers located on the plurality of first redistribution layers and above the plurality of internal supports, wherein the plurality of internal supports are not electrically connected to the plurality of second redistribution layers; and an integrated device package attached to a second side of the redistribution structure.

[0006] According to another aspect of an embodiment of the present invention, a method for manufacturing a semiconductor structure is provided, comprising: forming a plurality of first redistribution layers above a carrier; attaching an internal support to the plurality of first redistribution layers, wherein the internal support is an electrically inert material; forming a plurality of second redistribution layers above the plurality of first redistribution layers and above the internal support; attaching a first interconnect substrate and a second interconnect substrate to the plurality of second redistribution layers, wherein the first interconnect substrate is laterally separated from the second interconnect substrate by a gap, wherein the gap is laterally aligned with the internal support; and attaching a plurality of integrated circuit dies to the plurality of first redistribution layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When the following detailed description is read in conjunction with the accompanying drawings, various aspects of the present invention will be better understood. It should be noted that, according to standard practice in the industry, various components are not drawn to scale. In fact, the size of each component may be arbitrarily enlarged or reduced for clarity of discussion.

[0008] Figure 1 A cross-sectional view illustrating an intermediate step of forming a first redistribution layer of a redistribution structure according to some embodiments.

[0009] Figure 2A A plan view illustrating an intermediate step of forming a first redistribution layer of a redistribution structure according to some embodiments.

[0010] Figure 2B and Figure 2C A cross-sectional view illustrating an intermediate step in forming a structure on a carrier substrate in accordance with some embodiments.

[0011] Figure 3 , Figure 4 and Figure 5 A cross-sectional view illustrating an intermediate step of forming a first redistribution layer of a redistribution structure according to some embodiments.

[0012] Figure 6 A cross-sectional view is shown of an intermediate step in forming internal supports in a redistribution structure according to some embodiments.

[0013] Figure 7 A plan cross-sectional view is shown of an intermediate step in forming internal supports in a redistribution structure according to some embodiments.

[0014] Figure 8 , Fig. 9 and Fig.10 A cross-sectional view illustrating an intermediate step of forming a second redistribution layer of a redistribution structure according to some embodiments.

[0015] Fig.11 A cross-sectional view of an interconnect structure according to some embodiments is shown.

[0016] Fig.12 , Fig.13 and Fig.14 A cross-sectional view illustrates an intermediate step of bonding an interconnect structure to a redistribution structure in accordance with some embodiments.

[0017] Fig.15 A plan view illustrating an intermediate step in bonding an interconnect structure to a redistribution structure in accordance with some embodiments.

[0018] Fig.16 , Fig.17 and Fig.18 Cross-sectional views are shown of intermediate steps in forming a package structure in accordance with some embodiments.

[0019] Fig.19 , Fig. 20 , Fig.21 , Fig. 22 , Fig.23 and Fig.24 A cross-sectional view illustrating an intermediate step of forming a first redistribution layer and a second redistribution layer of a redistribution structure according to some embodiments.

[0020] Fig.25 and Fig.26 Cross-sectional views are shown of intermediate steps in forming a package structure in accordance with some embodiments.

[0021] Fig. 27 , Fig.28 , Fig.29 , Fig. 30A , Fig. 30B and Fig. 30C Cross-sectional and plan views of a package structure with an internal support according to some embodiments are shown. DETAILED DESCRIPTION

[0022] The following disclosure provides many different embodiments or examples of different components for implementing the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may be formed by direct contact between the first component and the second component, and may also be formed by including an additional component between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or structures discussed.

[0023] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0024] In the present disclosure, various aspects of package structures and their formation are described. In some embodiments, one or more internal supports are incorporated within the redistribution structure of the package. The internal supports can be, for example, dummy die or body material. The internal supports can be placed to provide structural support to the package and reduce warping or cracking, especially when multiple interconnects or integrated circuit dies are attached to the redistribution structure. Reducing stress within the package in this way can improve performance and yield.

[0025] Figures 1 to 10 The formation of a redistribution structure 100 (see FIG. Fig.10 ) is an intermediate step. The redistribution structure 100 includes one or more internal support members 110 (see Figure 6-Figure 7 ), which increases structural stability and reduces warping. In subsequent steps, multiple interconnect structures 200 (see Figure 11-Figure 12 ) is attached to the redistribution structure 100. Figure 1-Figure 10 The interconnection regions 200' and 200' shown in FIG. 2 represent regions to which the interconnection structure 200 is subsequently attached (see FIG. 2 ). Fig.11 ), and each interconnect region 200 ′ has the same size as the corresponding interconnect structure 200 . Figure 2A and Figure 7 shows a plan view of the structure, Figure 1 , Figure 3-Figure 6 and Figure 8-Figure 10 Shown through Figure 2A and Figure 7 A cross-sectional view of the reference cross section shown in .

[0026] Figure 1-Figure 4 The formation of a first redistribution layer 108A of the redistribution structure 100 is shown, which includes a plurality of conductive lines 105A-105E, a plurality of dielectric layers 106A-106D, and a plurality of conductive vias 107A-107D. The first redistribution layer 108A is an illustrative example, and in other embodiments, more or fewer conductive lines, dielectric layers, and / or conductive vias may be used. The first redistribution layer 108A may be formed using materials and / or techniques different from those described below.

[0027] Go to Figure 1, shows a first carrier substrate 102 on which a release layer 103, a protective layer 104, and a conductive line 105A are formed, according to some embodiments. Figure 2A Shows Figure 1 A plan view of the structure shown, wherein Figure 1 The cross section passes through Figure 2A Reference section AA is shown. For clarity, Figure 1 Some of the components shown in FIG. 1 , such as conductive wire 105A, have been removed from Figure 2A Omitted in . Figure 2A Four interconnect regions 200' are shown, but in other embodiments, there may be more or fewer interconnect regions 200', the interconnect regions 200' may have a different size or shape than shown, or the interconnect regions 200' may have a different arrangement than shown. In some embodiments, adjacent interconnect regions 200' may be separated by a separation distance D1 in a range of about 40 μm to about 5000 μm, although other separation distances are possible.

[0028] The first carrier substrate 102 may include a silicon-based material, such as a silicon substrate (e.g., a silicon wafer), a glass material, other materials such as silicon oxide or aluminum oxide, or a combination thereof. In some embodiments, the first carrier substrate 102 may be a panel structure, which may be, for example, a support substrate formed of a suitable dielectric material, such as a glass material, a plastic material, or an organic material. The panel structure may be a rectangular panel.

[0029] As an illustrative example, Figure 2B and Figure 2C Different types of first carrier substrate 102 are shown in accordance with some embodiments. Figure 2B An embodiment in which the first carrier substrate 102 is a silicon wafer is shown. Figure 2C An embodiment is shown where the first carrier substrate 102 is a panel structure. Figure 2B-2C A plurality of redistribution structures 100 are shown formed on a first carrier substrate 102. In this manner, a plurality of structures may be formed simultaneously on the first carrier substrate 102. As part of the process of forming a single package structure 300, the structures formed on the first carrier substrate 102 may subsequently be singulated (see FIG. Fig.18 ).

[0030] Back to Figure 1, the release layer 103 can be formed on the top surface of the first carrier substrate 102 to facilitate the subsequent debonding of the first carrier substrate 102. The release layer 103 can be formed of a polymer-based material, which can be removed from the upper structure to be formed in a subsequent step together with the first carrier substrate 102. In some embodiments, the release layer 103 is a thermal release material based on epoxy resin (e.g., a light-to-heat conversion (LTHC) release coating) that loses its adhesiveness when heated. In other embodiments, the release layer 103 can be an ultraviolet (UV) glue that loses its adhesiveness when exposed to UV light. The release layer 103 can be dispensed and cured in the form of a liquid, can be a laminated film laminated to the first carrier substrate 102, or can be the like. The top surface of the release layer 103 can be horizontal and can have a high flatness. In some embodiments, a die attach film (DAF) (not shown) can be used instead of or in addition to the release layer 103.

[0031] In some embodiments, the protective layer 104 may be formed on the release layer 103. The bottom surface of the protective layer 104 may be in contact with the top surface of the release layer 103. In some embodiments, the protective layer 104 is formed of a polymer, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), etc. In other embodiments, the protective layer 104 is formed of: a nitride such as silicon nitride; an oxide such as silicon oxide, phosphosilicate glass, borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG); or the like. The protective layer 104 may be formed by any feasible deposition process, such as spin coating, CVD, lamination, etc., or a combination thereof.

[0032] Conductive wires 105A of the redistribution structure 100 are formed on the protective layer 104. Conductive wires 105A may include, for example, conductive wires, redistribution layers or redistribution lines, contact pads, or other conductive components extending above the main surface of the protective layer 104. As an example of forming conductive wires 105A, a seed layer is formed above the protective layer 104. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer including a plurality of sublayers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer above the titanium layer. The seed layer may be formed using, for example, physical vapor deposition (PVD) or the like. Then, a photoresist is formed on the seed layer and patterned. The photoresist may be formed by spin coating or the like, and may be exposed for patterning, wherein the pattern of the photoresist corresponds to the conductive wires 105A. Patterning forms an opening through the photoresist to expose the seed layer, and then forms a conductive material in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material may be formed by plating such as electroplating or chemical plating. The conductive material may include a metal such as copper, titanium, tungsten, aluminum, etc., or a combination thereof. Then, the photoresist and the portion of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by a feasible ashing or stripping process, such as using oxygen plasma, a chemical stripping process, etc. Once the photoresist is removed, for example by using a feasible etching process such as wet or dry etching, the exposed portion of the seed layer is removed. The remaining portion of the seed layer and the conductive material forms the conductive line 105A. Other techniques for forming the conductive line 105A are also possible.

[0033] exist Figure 3 In some embodiments, a conductive via 107A is formed above the conductive line 105A. The conductive via 107A extends over the conductive line 105A and electrically connects the conductive line 105A and the conductive line 105B of the subsequently formed redistribution structure 100. As an example of forming the conductive via 107A, a photoresist is formed over the protective layer 104 and the conductive line 105A and patterned. The photoresist can be formed by spin coating, etc., and can be exposed for patterning. The patterning of the photoresist forms an opening through the photoresist to expose a portion of the conductive line 105A below, so that the opening in the photoresist corresponds to the pattern of the conductive via 107A. A conductive material is then formed in the opening of the photoresist and on the exposed portion of the conductive line 105A. The conductive material can be formed by plating such as electroplating or chemical plating. The conductive material may include a metal such as copper, titanium, tungsten, aluminum, etc., or a combination thereof. The photoresist can be removed by a feasible ashing or stripping process. The conductive lines 105A and the conductive vias 107A together form a metallization pattern of the redistribution structure 100 .

[0034] According to some embodiments, after forming the conductive via 107A, a dielectric layer 106A is formed on and around the conductive via 107A and the conductive line 105A. After formation, the dielectric layer 106A surrounds the conductive via 107A and the conductive line 105A. The dielectric layer 106A and the metallization pattern (including the conductive via 107A and the conductive line 105A) form one of the first redistribution layers 108A of the redistribution structure 100. In some embodiments, the dielectric layer 106 is an encapsulant, such as a prepreg, a resin, a resin coated copper (RCC), a molding compound, a polyimide, a photo-imageable dielectric (PID), an epoxy resin, etc., and can be applied by a suitable technique such as compression molding, transfer molding, etc. The encapsulant can be applied in a liquid or semi-liquid form and then cured. In some embodiments, the dielectric layer 106A is formed so that the conductive line 105A and the conductive via 107A are buried or covered, and then a planarization process is performed on the dielectric layer 106A to expose the conductive via 107A. After the planarization process, within the process variation range, the topmost surface of the dielectric layer 106A and the conductive via 107A can be substantially horizontal (e.g., flat). The planarization process can include, for example, a grinding process and / or a chemical mechanical polishing (CMP) process. In some embodiments, the dielectric layer 106A can include other materials, such as silicon oxide, silicon nitride, etc. In some embodiments, the dielectric layer 106A is formed to have a thickness in the range of about 5 μm to about 50 μm, although other thicknesses are also possible.

[0035] exist Figure 4 In accordance with some embodiments, the above steps and processes are repeated to form additional redistribution layers of the first redistribution layer 108A. Figure 4 The first redistribution layer 108A shown includes: additional dielectric layers 106B, 106C, and 106D; additional conductive lines 105B, 105C, 105D, and 105E; and additional conductive vias 107B, 107C, and 107D. The first redistribution layer 108A is shown as an example of a redistribution layer including five layers of conductive lines, but more or fewer layers of dielectric layers, conductive lines, or conductive vias may be formed in the first redistribution layer 108A. If fewer redistribution layers are to be formed, some of the steps and processes discussed below may be omitted. If more redistribution layers are to be formed, some of the steps and processes discussed below may be repeated.

[0036] Additional redistribution layers of the first redistribution layer 108A may be formed using similar techniques as described for the dielectric layer 106A, the conductive wire 105A, and the conductive via 107A. For example, the conductive wire 105B may be formed on the dielectric layer 106A and the conductive via 107A. The conductive wire 105B makes physical and electrical contact with the conductive via 107A below. The conductive wire 105B may be formed in a similar manner and with similar materials as the conductive wire 105A. The conductive via 107B may then be formed on the conductive wire 105B and may be formed in a similar manner and with similar materials as the conductive via 107A. The dielectric layer 106B may then be formed over the dielectric layer 106A, the conductive wire 105B, and the conductive via 107B. The dielectric layer 106B may be formed in a similar manner and with similar materials as the dielectric layer 106A. A planarization process may be performed on the dielectric layer 106B to expose the conductive via 107B. Steps or processes similar to these may be performed to form conductive lines 105B, 105C, 105D, and 105E conductive vias 107C and 107D and dielectric layers 106C and 106D. In some embodiments, conductive lines and / or conductive vias having different sizes may be formed. For example, one or more conductive lines or conductive vias may have a different width, spacing, or thickness than other conductive lines or conductive vias. In some embodiments, one or more dielectric layers may be formed of different materials or have a different thickness than other dielectric layers.

[0037] Although one process for forming the conductive vias 107A-107D, the dielectric layers 106A-106D, and the conductive lines 105A-105E has been described, it should be understood that other processes may be used to form the first redistribution layer 108A. For example, the conductive vias and the conductive lines of the redistribution layer may be simultaneously formed by forming a single metallization pattern that includes via portions corresponding to the conductive vias and line portions corresponding to the conductive lines. In such an embodiment, the line portions of the metallization pattern extend on and along the major surface of the dielectric layer, and the via portions of the metallization pattern extend through the dielectric layer to physically and electrically couple the conductive lines to the underlying conductive features. In such an embodiment, no seed layer is formed between the conductive vias and the conductive lines of the same redistribution layer.

[0038] Figures 5 to 10 The second redistribution layer 108B of the redistribution structure 100 according to some embodiments is shown (see FIG. Fig.10 ) is an intermediate step in the formation process, including incorporating an internal support member 110 (see Figure 6 ).exist Figure 5, the conductive via 107E of the second redistribution layer 108B is formed on the conductive line 105E and may be formed in a similar manner and with similar materials as the conductive vias 107A-107D. The conductive via 107E is formed on the conductive line 105E to make physical and electrical contact with the conductive line 105E.

[0039] exist Figure 6 In the embodiment of the present invention, one or more internal supports 110 are attached to the first redistribution layer 108A. The internal supports 110 are passive structures incorporated into the redistribution structure 100 to provide additional structural support to the redistribution structure 100. The internal supports 110 may be free of passive devices and / or active devices. The stability provided by the internal supports 110 may reduce stress, warping, or cracking of the redistribution structure 100 during or after bonding to the plurality of interconnect structures 200 (see Fig.11 ). In some cases, the internal support 110 can be considered a "dummy structure" or "dummy die" within the redistribution structure 100. In some embodiments, the thickness of the internal support 110 is in a range from about 15 μm to about 100 μm, although other thicknesses are possible. In some cases, the thickness of the internal support 110 is selected to provide sufficient structural support while adding little or no thickness to the overall redistribution structure 100.

[0040] The internal support 110 can be formed of a material having suitable mechanical stiffness or rigidity. In some embodiments, the internal support 110 can be formed of a semiconductor material, such as silicon, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, etc., or a combination thereof. In some embodiments, the internal support 110 can be formed of a dielectric material, such as a ceramic material, quartz, another electrically inert material, etc., or a combination thereof. In some embodiments, the internal support 110 can be a metal or a metal alloy, such as a tin-nickel alloy (e.g., "alloy 42"), etc. In some embodiments, the internal support 110 is formed of two or more different materials, such as multiple layers of different materials. In some embodiments, the material of the internal support 110 is selected based on the mechanical stiffness or rigidity of the material. For example, in some embodiments, the material of the internal support 110 can be selected to have a Young's modulus in the range of about 10 GPa to about 160 GPa, although other values ​​are also possible. In some embodiments, the material of the internal support 110 is selected based on the coefficient of thermal expansion (CTE) of the redistribution structure 100. For example, a particular material for the internal support 110 can be selected to have a CTE similar to the redistribution structure 100 or a component thereof. In some embodiments, the material for the internal support can be selected to have a CTE in the range of about 2 ppm to about 10 ppm, although other values ​​are possible.

[0041] Figure 6 An internal support 110 is shown attached to an exposed conductive line (e.g., conductive line 105E) of the first redistribution layer 108A, but in other embodiments, the internal support 110 can be attached to an exposed dielectric layer (e.g., dielectric layer 106D) of the first redistribution layer 108A. An adhesive 109 on the internal support 110 adheres the internal support 110 to the first redistribution layer 108A (e.g., to the conductive line 105E or the dielectric layer 106D). The adhesive 109 can be any suitable adhesive, epoxy, adhesive film, die attach film (DAF), etc. The adhesive 109 can be applied to the internal support 110, or can be applied over the surface of the first redistribution layer 108A. In some embodiments, the thickness of the adhesive 109 is in the range of about 2 μm to about 20 μm, for example 3 μm, but other thicknesses are possible. The internal support 110 can be placed using pick and place techniques, etc.

[0042] In some embodiments, the internal support 110 is placed on the structure to laterally overlap two or more interconnected regions 200', the interconnected structure 200 (see Fig.11 ) is then attached at the interconnect area 200'. Figure 6 The internal support member 110 is shown to be approximately laterally centered between adjacent interconnect regions 200', such that the internal support member 110 laterally overlaps portions of two adjacent interconnect regions 200'. In some cases, positioning the internal support member 110 laterally between and / or overlapping multiple interconnect structures 200 can reduce stress within the redistribution structure 100 due to the attachment of multiple interconnect structures 200 to the redistribution structure 100, thereby reducing warping or cracking of the redistribution structure 100.

[0043] Steering Figure 7 , according to some embodiments, shows a diagram similar to Figure 6 Schematic plan view of the structure. Figure 7 The exemplary cross section AA shown corresponds to Figure 6 For example, Figure 7 The inner support member 110 shown may be similar to Figure 6 An internal support member 110 is shown. Figure 7 The floor plans are illustrative examples and are provided for the sake of clarity. Figure 7 Not shown Figure 6 Some components shown in (eg, conductive line 105E and conductive via 107E). Figure 7A first redistribution layer 108A having four interconnect regions 200' is shown. Four internal supports 110 are attached to the first redistribution layer 108A and laterally overlap adjacent pairs of interconnect regions 200'. In this way, each pair of adjacent interconnect regions 200' has a corresponding internal support 110 that can reduce stress in the redistribution structure 100 after the interconnect structure 200 is attached (see Fig.13 ). Figure 7 Four internal supports 110 are shown, but in other embodiments, more or fewer internal supports 110 may be used. In some embodiments, each pair of adjacent interconnect regions may have two or more corresponding internal supports 110 that overlap each interconnect region 200' in the adjacent pair. In some embodiments, different internal supports 110 attached to the first redistribution layer 108A may have different sizes or shapes. For some examples of structures with multiple internal supports 110, see the following reference to Figure 27-Figure 30B Described embodiments.

[0044] Still reference Figure 7 In some embodiments, the internal support member 110 may have a width W1 in the range of about 80 μm to about 6000 μm, but other widths are possible. In some embodiments, the overlap distance D2 between the edge of the internal support member 110 and the edge of the interconnection region 200' is in the range of about 20 μm to about 500 μm, but other overlap distances are possible. In some cases, a larger overlap distance D2 can provide more structural support for the redistribution structure 100. In some embodiments, the internal support member 110 may have a length L1 in the range of about 2 mm to about 60 mm, but other lengths are possible. In some embodiments, the interconnection region 200' may have a length L2 in the range of about 15 mm to about 70 mm, but other lengths are possible. The length L1 of the internal support member 110 may be in the range of about 2.5% to about 86% of the length L2 of the interconnection region 200'. In some cases, the internal support member 110 having a larger length L1 can provide more structural support for the redistribution structure 100. In some embodiments, the separation distance D3 between the end of the internal support 110 and the edge of the interconnect region 200' can be in the range of about 20 μm to about 500 μm, although other separation distances are possible. The internal support 110 can be approximately laterally centered with the interconnect region 200' so that the separation distance D3 at both ends of the internal support 110 is approximately the same, or the internal support 110 can be laterally offset so that the separation distance D3 at one end of the internal support 110 is different from the separation distance D3 at the other end of the internal support 110.

[0045] exist Figure 8In the embodiment of the present invention, dielectric layer 106E of second redistribution layer 108B is formed over inner support 110, dielectric layer 106D, conductive line 105E, and conductive via 107B. Dielectric layer 106E may be formed in a similar manner and with similar materials as dielectric layers 106A-106D, although dielectric layer 106E may be a different material than one or more dielectric layers 106A-106D. Fig. 9 In the process, a planarization process, such as a CMP process and / or a mechanical grinding process, is performed on the dielectric layer 106E, the conductive via 107E and / or the internal support 110. The planarization process exposes the conductive via 107E. In some embodiments, the planarization process exposes the dielectric layer 106E, the conductive via 107E and the internal support 110, and the top surfaces of the dielectric layer 106E, the conductive via 107E and the internal support 110 may be horizontal. In other embodiments, after the planarization process is performed, the dielectric layer 106E remains covering the internal support 110.

[0046] exist Fig.10 , the dielectric layer 106F, the conductive vias 107F, and the conductive lines 105F-105G of the second redistribution layer 108B are formed above the dielectric layer 106E. In this way, the redistribution structure 100 is formed by the first redistribution layer 108A and the second redistribution layer 108B, and one or more internal supports 110 are disposed between the first redistribution layer 108A and the second redistribution layer 108B. In other embodiments, the first redistribution layer 108A or the second redistribution layer 108B may have a different number of conductive lines, conductive vias, or dielectric layers than shown. In this way, the redistribution structure 100 may have any suitable number of redistribution layers (e.g., conductive vias, conductive lines, and / or dielectric layers), and the internal supports 110 may be located within any suitable dielectric layer of the redistribution structure 100. If fewer redistribution layers of the second redistribution layer 108B are to be formed, some of the steps and processes discussed below may be omitted. If more redistribution layers are to be formed, some of the steps and processes discussed below may be repeated.

[0047] The dielectric layer 106F, conductive vias 107F, and conductive wires 105F-105G of the second redistribution layer 108B can be formed using similar materials and similar techniques as described for the first redistribution layer 108A. For example, the conductive wire 105F can be formed on the dielectric layer 106E and the conductive via 107E. The conductive wire 105F makes physical and electrical contact with the conductive via 107E below. The conductive wire 105F can be formed in a similar manner and with similar materials as the conductive wires 105A-105E. The conductive via 107F can then be formed on the conductive wire 105F and can be formed in a similar manner and with similar materials as the conductive vias 107A-107E. The dielectric layer 106F can then be formed over the dielectric layer 106E, the conductive wire 105F, and the conductive via 107F. The dielectric layer 106F can be formed in a similar manner and with similar materials as the dielectric layers 106A-106E. A planarization process may be performed on dielectric layer 106F to expose conductive vias 107F. Steps or processes similar to these may be performed to form conductive wire 105G. In some embodiments, conductive wires and / or conductive vias having different sizes may be formed. For example, one or more conductive wires or conductive vias may have a width, spacing, or thickness different from other conductive wires or conductive vias. In some embodiments, one or more dielectric layers may be formed of different materials or have a different thickness from other dielectric layers.

[0048] In some embodiments, an under-bump metallization structure (UBM, not shown) is formed on the topmost conductive line (e.g., conductive line 105G) of the redistribution structure 100. For example, the UBM may include three layers of conductive material, such as a layer of titanium, a layer of copper, and a layer of nickel. However, other materials and layer arrangements suitable for forming the UBM may be used, such as an arrangement of chromium / chromium-copper alloy / copper / gold, an arrangement of titanium / titanium tungsten / copper, or an arrangement of copper / nickel / gold. Any suitable material or material layer that can be used for the UBM should be fully included within the scope of the present application. The UBM can be created by forming each layer of the UBM above the redistribution structure 100. Each layer can be formed using a plating process such as electroplating or chemical plating, but other formation processes such as sputtering, evaporation, or PECVD processes may optionally be used depending on the desired material. Once the desired layer is formed, a portion of the layer may be removed by a suitable photolithography mask and etching process to remove undesirable materials and keep the UBM in a desired shape, such as a circle, an octagon, a square, or a rectangle, although any desired shape may be optionally formed. In some embodiments, as part of the formation of the redistribution structure 100, a UBM is formed over the topmost redistribution layer, which may include using the same lithography steps as forming the topmost redistribution layer of the redistribution structure 100. For example, a layer of the UBM may be deposited over the topmost redistribution layer, and then excess material of the topmost redistribution layer and the UBM may be removed in the same process. In some embodiments, the UBM may be part of the topmost redistribution layer of the redistribution structure 100, and may, for example, extend through the topmost dielectric layer (e.g., dielectric layer 106F) of the redistribution structure 100.

[0049] Fig.11 2 shows an interconnect structure 200 according to some embodiments. The interconnect structure 200 is then bonded to the redistribution structure 100 to form a package structure 300 (see FIG. Fig.18 ), and provide additional routing and stability for the redistribution structure 100. For example, the interconnect structure 200 can reduce warping of the redistribution structure 100. In some embodiments, the interconnect structure 200 can be, for example, an interposer or a "semi-finished substrate" and can be free of active devices. The interconnect structure 200 can have a thickness between about 200 μm and about 3000 μm, although other thicknesses are possible.

[0050] In some embodiments, the interconnect structure 200 may include a wiring layer (e.g., wiring structures 212 and 213) formed on a core substrate 202. The core substrate 202 may include materials such as Ajinomoto built-up film (ABF), pre-impregnated composite fiber ("prepreg") materials, epoxy resins, molding compounds, epoxy molding compounds, glass fiber reinforced resin materials, printed circuit board (PCB) materials, silica fillers, polymer materials, polyimide materials, paper, glass fibers, non-woven glass fiber fabrics, glass, ceramics, other laminates, etc., or combinations thereof. In some embodiments, the core substrate may be a double-sided copper clad laminate (CCL) substrate, etc. The core substrate 202 may have a thickness between about 30 μm and about 2000 μm, although other thicknesses are also possible.

[0051] The interconnect structure 200 may have one or more wiring structures 212 / 213 formed on each side of the core substrate 202 and a through hole 210 extending through the core substrate 202. The wiring structure 212 / 213 and the through hole 210 provide additional electrical wiring and interconnection. The through hole 210 can interconnect the wiring structure 212 and the wiring structure 213. The wiring structure 212 / 213 may include one or more wiring layers 208 / 209 and one or more dielectric layers 218 / 219. In some embodiments, the wiring layer 208 / 209 and / or the through hole 210 may include one or more layers of copper, nickel, aluminum, other conductive materials, etc., or a combination thereof. In some embodiments, the dielectric layer 218 / 219 may include another material such as a build-up material, ABF, a prepreg material, a laminate material, a material similar to the above-mentioned material for the core substrate 202 or the dielectric layer 106A-106F, etc., or a combination thereof. Fig.11 The interconnect structure 200 shown shows two wiring structures 212 / 213 with a total of six wiring layers, but in other embodiments, the interconnect structure 200 can include only one wiring structure (e.g., 212 or 213), or the wiring structures 212 / 213 can include more or fewer wiring layers. Each wiring layer of the wiring structures 212 / 213 can have a thickness between about 5 μm and about 50 μm, and each of the wiring structures 212 / 213 can have a total thickness between about 2 μm and about 50 μm, although other thicknesses are also possible.

[0052] In some embodiments, the opening in the core substrate 202 for the through hole 210 can be filled with a filling material 211. The filling material 211 can provide structural support and protection for the conductive material of the through hole 210. In some embodiments, the filling material 211 can be a material such as a molding compound, an epoxy resin, an epoxy molding compound, a resin, a material including a monomer or an oligomer (e.g., an acrylated polyurethane, a rubber-modified acrylated epoxy resin, or a multifunctional monomer, etc.), or a combination thereof. In some embodiments, the filling material 211 can include a pigment or dye (e.g., for coloring) that changes rheology, improves adhesion, or affects other properties of the filling material 211, or other fillers and additives. In some embodiments, the conductive material of the through hole 210 can completely fill the through hole 210, and the filling material 211 is omitted.

[0053] In some embodiments, the interconnect structure 200 may include a passivation layer 207 formed over one or more sides of the interconnect structure 200. The passivation layer 207 may be a material such as a nitride, an oxide, a polyimide, a low temperature polyimide, a solder resist, a combination thereof, etc. Once formed, the passivation layer 207 may be patterned (e.g., using suitable photolithography and etching processes) to expose portions of the wiring layers 208 / 209 of the wiring structures 212 / 213.

[0054] According to some embodiments, Figures 12 to 18 The interconnect structures 200A-200B are bonded to the redistribution structure 100 to form the package structure 300 (see FIG. Fig.18 ). The interconnect structures 200A-200B may be similar to Fig.11 The interconnect structures 200 described in the figure are interconnect structures 200. The interconnect structures 200A-200B can be similar or different from each other. For example, the sizes of the interconnect structures 200A-200B can be the same or different. More or fewer interconnect structures 200 than shown in the figure can be attached. The interconnect structures 200A-200B are attached to the redistribution structure 100 in the corresponding interconnect area 200'.

[0055] refer to Fig.12According to some embodiments, the conductive connector 220 can be formed on the interconnect structure 200A-200B. The conductive connector 220 can be a ball grid array (BGA) connector, a solder ball, a metal column, a controlled collapse chip connection (C4) bump, a microbump, an electroless nickel plating, a bump formed by chemical nickel palladium immersion gold (ENEPIG), etc. The conductive connector 220 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or a combination thereof. In some embodiments, the conductive connector 220 is formed by first forming a solder layer by evaporation, electroplating, printing, solder transfer, and solder ball placement. Once the solder layer is formed on the structure, reflow can be performed to shape the material into a desired bump shape. In another embodiment, the conductive connector 220 includes a metal column (e.g., a copper column) formed by sputtering, printing, electroplating, chemical plating, CVD, etc. The metal column can be solder-free and have a substantially vertical sidewall. In some embodiments, a metal protective layer is formed on the top of the metal column. The metal protection layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, etc., or a combination thereof, and may be formed by a plating process. In other embodiments, the conductive connector 220 is formed on the redistribution structure 100 instead of the interconnect structures 200A-200B, or the interconnect structures 200A-200B and the conductive connector 220 are formed on the redistribution structure 100.

[0056] Fig.13 It is shown that the interconnect structures 200A-200B are placed in electrical connection with the redistribution structure 100 according to some embodiments. In one embodiment, the conductive connectors 220 of the interconnect structures 200A-200B are placed in physical contact with the conductive lines or UBMs of the redistribution structure 100 using, for example, a pick and place process. Once in physical contact, the conductive connectors 220 of the interconnect structures 200A-200B can be bonded to the redistribution structure 100 using a reflow process. In some embodiments, the conductive connectors 220 are not formed on the interconnect structures 200A-200B, and the interconnect structures 200A-200B are bonded to the redistribution structure 100 using a direct bonding technique such as a thermocompression bonding technique.

[0057] In some cases, joining multiple interconnect structures 200 to the same redistribution structure 100 may induce stress within the redistribution structure 100. By incorporating one or more internal supports 110 within the redistribution structure 100, this stress may be reduced. In some cases, stress within the redistribution structure 100 is substantially aligned with the gaps between adjacent interconnect structures 200, and such stress within the redistribution structure 100 may be reduced by using one or more internal supports 110 that are substantially aligned with the gaps between adjacent interconnect structures 200. Fig.14 , showing Fig.13 An enlarged cross section of the region 111 is shown. Figure 13-Figure 14 As shown, the internal support member 110 is generally aligned with the gap between the interconnect structure 200A and the interconnect structure 200B. Figure 7 As described for the interconnect region 200' in FIG. 1 , the interconnect structures 200A-200B have a gap separation distance D1, and the edge of the internal support 110 and the edge of the interconnect structure 200A / 200B have an overlap distance D2. In some embodiments, the distance D4 between the redistribution structure 100 and the interconnect structure 200 is in the range of about 10 μm to about 300 μm, and the distance D5 between the internal support 110 and the upper interconnect structure 200 is in the range of about 100 μm to about 15,000 μm. Other distances are also possible. In some embodiments, the ratio of D5:D2 is in the range of about 5:1 to about 30:1. In some cases, the internal support 110 having a ratio of D5:D2 within the range of this example can provide more structural support for the redistribution structure 100 and reduce more stress than the internal support 110 having a ratio within the range of this example. The ratio D5:D2 may also have other ranges.

[0058] Fig.15 According to some embodiments Fig.14 A plan view of the structure shown. Fig.15 The floor plan is similar to Figure 7 The floor plan shown, Fig.15 The exemplary cross section AA shown corresponds to Fig.14 The cross-sectional view shown. Fig.15 As shown, the interconnect structures 200A-200D are attached to the redistribution structure 100 in the interconnect region 200'. Each pair of adjacent interconnect structures 200A-200D has a corresponding internal support 110 that reduces stress in the redistribution structure 100 associated with the pair of adjacent interconnect structures 200A-200D. The interconnect structures 200A-200D may have a different size or shape than shown, and may have a different arrangement than shown. There may be more or fewer interconnect structures 200 than shown. In some embodiments, the distance D6 between the edge of the interconnect structure 200 and the edge of the redistribution structure 100 is in the range of 40 μm to about 5,000 μm, although other distances are possible.

[0059] exist Fig.16In the embodiment, the bottom filler 224 is deposited along the sidewalls of the interconnect structures 200A-200B and in the gaps between the interconnect structures 200A-200B and the redistribution structure 100. The bottom filler 224 can be a material such as a molding compound, a sealant, an epoxy resin, a bottom filler, a molded bottom filler (MUF), a resin, etc. The bottom filler 224 can protect the conductive connector 220 and provide structural support for the package structure 300 (see FIG. Fig.18 ). In some embodiments, the bottom filler 224 can be applied using a compression molding process, a transfer molding process, or the like. In some embodiments, the bottom filler 224 can be applied in a liquid or semi-liquid form and then cured. In some embodiments, the bottom filler 224 can be thinned after deposition. The thinning can be performed, for example, using a mechanical grinding or CMP process. In some embodiments, the bottom filler 224 can be deposited over the interconnect structures 200A-200B, and the thinning can expose the interconnect structures 200A-200B.

[0060] Go to Fig.17 , the first carrier substrate 102 is debonded to separate (or "debond") the first carrier substrate 102. According to some embodiments, the structure is then flipped over and bonded to the second carrier substrate 302. In some embodiments, debonding includes projecting light, such as laser or ultraviolet light, onto the release layer 103 of the first carrier substrate 102, so that the release layer 103 decomposes under the heat of the light, and the first carrier substrate 102 can be removed. The second carrier substrate 302 can be a carrier substrate similar to the first carrier substrate 102 described above. For example, the second carrier substrate 302 can be similar to Figure 2B Wafers shown or similar Figure 2C A release layer 304 may be formed on the second carrier substrate 302 to facilitate attachment of the structure to the second carrier substrate 302. Multiple structures may be formed on the second carrier substrate 302 and then separated to form individual package structures 300 (see Fig.18 ). The structure can be segmented, for example using one or more saw blades to divide the structure into discrete blocks, thereby forming one or more segmented structures. However, any suitable segmentation method can also be used, including laser ablation or one or more wet etching. The segmentation process can leave the bottom filler 224 on the sidewalls of the interconnect structure 200, or the segmentation process can remove the bottom filler 224 from the sidewalls of the interconnect structure 200. After the segmentation process, each redistribution structure 100 can have a sidewall that is coplanar with the sidewalls of the interconnect structure 200, or can have a sidewall that is coplanar with the bottom filler 224 remaining on the sidewalls of the interconnect structure 200.

[0061] Still reference Fig.17According to some embodiments, conductive connectors 312 are formed on the redistribution structure 100. The conductive connectors 312 allow for physical and electrical connection to a die or another packaging structure, such as an integrated circuit package 350 (see Fig.18 ). In some embodiments, openings may be formed in the protective layer 104 to expose the conductive lines (e.g., conductive lines 105A) of the redistribution structure 100. These openings expose portions of the conductive lines on which the conductive connectors 312 are subsequently formed. For example, a laser drilling process may be used to form the openings. In other embodiments, the openings may be formed by forming a photoresist over the protective layer 104, patterning the photoresist, and etching the protective layer 104 through the patterned photoresist using a suitable etching process (e.g., a wet etching process and / or a dry etching process).

[0062] Then, a conductive connector 312 can be formed on the conductive line 105A to electrically connect with the redistribution structure 100. The conductive connector 312 can be a ball grid array (BGA) connector, a solder ball, a metal column, a controlled collapse chip connection (C4) bump, a microbump, an electroless nickel plating, a bump formed by chemical nickel palladium immersion gold (ENEPIG), etc. The conductive connector 312 may include a conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or a combination thereof. In some embodiments, the conductive connector 312 is formed by first forming a solder layer by evaporation, electroplating, printing, solder transfer, and solder ball placement. Once the solder layer is formed on the structure, reflow can be performed to shape the material into a desired bump shape. In another embodiment, the conductive connector 312 includes a metal column (e.g., a copper column) formed by sputtering, printing, electroplating, chemical plating, CVD, etc. The metal column can be solder-free and have a substantially vertical sidewall. In some embodiments, a metal protective layer is formed on the top of the metal column. The metal protection layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, etc., or a combination thereof, and may be formed by a plating process. In some embodiments, before forming the conductive connector 312, a UBM (not shown) is formed on the conductive line 105A.

[0063] According to some embodiments, Fig.18 An integrated circuit package 350 is shown attached to the conductive connector 312 to form the package structure 300. The integrated circuit package 350 is physically and electrically connected to the conductive connector 312 to make an electrical connection between the integrated circuit package 350 and the redistribution structure 100. The integrated circuit package 350 can be placed on the conductive connector 312 using a suitable process (e.g., a pick and place process). Fig.18The attachment of one integrated circuit package 350 is shown, but in other embodiments, one, two, or more than three integrated circuit packages 350 may be attached to the conductive connector 312. In some embodiments, the integrated circuit packages 350 attached to the conductive connector 312 may include more than one integrated circuit package of the same type, or may include two or more integrated circuit packages of different types. Fig.18 Package structure 300 is shown after singulation, which may be performed at any suitable previous step during the formation process.In some embodiments, the lateral distance between opposite sides of package structure 300 is between about 30 mm and about 500 mm, although other distances are possible.

[0064] In some embodiments, integrated circuit package 350 may include one or more integrated circuit dies 352 . Fig.18 The cross-sectional view of shows three integrated circuit dies 352A-352C, but the integrated circuit package 350 may include more or fewer integrated circuit dies 352 than shown. The integrated circuit dies 352 may include, for example, logic dies (e.g., central processing unit (CPU), graphics processing unit (GPU), system on chip (SoC), component on wafer (CoW), application processor (AP), microcontroller, etc.), memory dies (e.g., dynamic random access memory (DRAM) die, static random access memory (SRAM) die, etc.), power management dies (e.g., power management integrated circuit (PMIC) die), radio frequency (RF) die, sensor die, micro-electromechanical system (MEMS) die, signal processing die (e.g., digital signal processing (DSP) die), front-end die (e.g., analog front end (AFE) die), input-output (I / O) die, etc., or a combination thereof. For example, in some embodiments, Fig.18 The integrated circuit package 350 shown includes a logic die 352B and multiple I / O dies 352A and 352C that interface with the logic die 352B, although other combinations of integrated circuit dies 352 are possible. The integrated circuit die 352 can be a memory device including multiple memory dies, such as a hybrid memory cube (HMC) module, a high bandwidth memory (HBM) module, etc. The integrated circuit die 352 can be formed in one or more wafers, which can include different device areas that are segmented in subsequent steps. The integrated circuit die 352 can be packaged with other similar or different integrated circuit dies 352 using known manufacturing techniques.

[0065] The integrated circuit package 350 may include a routing structure 354 that provides, for example, electrical routing and connections between the integrated circuit dies 352. The routing structure 354 may also provide connections from the integrated circuit package 350 to the conductive connector 312. The routing structure 354 may include one or more redistribution layers, an integrated fan-out structure (InFO), through substrate vias (TSVs), metallization patterns, electrical routing, conductive lines, conductive vias, etc., or a combination thereof.

[0066] The integrated circuit package 350 can be placed so that the conductive areas of the integrated circuit package 350 (e.g., contact pads, conductive connectors, solder bumps, etc., which can be part of the wiring structure 354) are aligned with the corresponding conductive connectors 312 on the redistribution structure 100. Once physically contacted, the conductive connectors 312 can be bonded to the semiconductor device 350 using a reflow process to form the package structure 300. Fig.18 As shown,

[0067] An underfill 314 may be deposited between the integrated circuit package 350 and the redistribution structure 100. The underfill 314 may also at least partially surround the conductive connector 312. The underfill 314 may be a material such as a molding compound, an epoxy, an underfill, a molded underfill (MUF), a resin, etc., and may be similar to the underfill 224 described previously.

[0068] In some cases, the multiple interconnect structures 200 of the package structure 300 may induce stress within the wiring structure 354. Incorporating one or more internal supports 110 within the redistribution structure 100 may also reduce such stress within the wiring structure 354. In this way, the risk of problems such as bending or cracking within the wiring structure 354 may be reduced. In some cases, the internal supports 110 may be incorporated within the redistribution structure 100 to reduce stress within the redistribution structure 100 and the wiring structure 354. In some embodiments, the internal supports 110 may be incorporated within a specific layer of the redistribution structure 100 to reduce stress within the wiring structure 354. In some embodiments, multiple internal supports 110 may be incorporated on different layers of the redistribution structure 100 to reduce stress within the redistribution structure 100 and the wiring structure 354. In some cases, the multiple integrated circuit dies 352 of the integrated circuit package 350 may induce stress within the redistribution structure 100 and / or the wiring structure 354. Internal supports 110 may also be incorporated into the redistribution structure 100 to reduce stress from the plurality of integrated circuit dies 352, as will be discussed below with reference to FIG. Figure 29-30B Describe in more detail.

[0069] Still reference Fig.18, an external connector 316 may be formed on the interconnect structure 200. In some embodiments, a UBM is first formed on the interconnect structure 200, and an external connector 316 is formed above the UBM. The external connector 316 may be, for example, a contact bump or a solder ball, although any suitable type of connector may be used. In an embodiment where the external connector 316 is a contact bump, the external connector 316 may include a material such as tin or other suitable materials such as silver, lead-free tin, or copper. In an embodiment where the external connector 316 is a solder bump, the external connector 316 may be formed by first forming a solder layer using techniques such as evaporation, electroplating, printing, solder transfer, solder ball placement, etc. Once the solder layer is formed on the structure, a reflow may be performed to shape the material into the bump shape required for the external connector 316. In some embodiments, the external connector 316 may have a pitch between about 100 μm and about 1,500 μm, although other distances are possible. In this way, a package structure 300 may be formed.

[0070] In some embodiments, an optional support ring 320 is attached to the package structure 300 to provide further mechanical support to reduce warping of the package structure 300. The support ring 320 can be attached to the package structure 300 by an adhesive, an adhesive film, etc. The support ring 320 can be a material such as a metal, although other materials can also be used. In some cases, the outer edge of the support ring 320 can be flush with the sidewalls of the package structure 300. The thickness of the support ring 320 can be between about 50 μm and about 1,500 μm, but other thicknesses are also possible.

[0071] Figures 19 to 26 A package structure 400 according to some embodiments is shown (see Fig.26 ) is an intermediate step in the formation process of the package structure 400. Fig.18 The package structure 300 shown in FIG. 1 is different in that the redistribution structure 402 includes a first redistribution layer 408A and a second redistribution layer 408B formed using different techniques. In some cases, using different techniques to form the second redistribution layer 408B can improve electrical performance, which will be described in more detail below. The package structure 400 includes one or more internal support members 110 (see FIG. 1 ) within the redistribution structure 402. Fig. 20 ), which increases structural stability and reduces warping. In subsequent steps, multiple interconnect structures 200 (see Fig.25 ) is attached to the redistribution structure 402. Figure 19-Figure 25 The interconnection regions 200' and 200' shown in FIG. 2 represent regions to which the interconnection structure 200 is subsequently attached (see FIG. 2 ). Fig.25 ), and each interconnect region 200 ′ has the same size as the corresponding interconnect structure 200 .

[0072] Fig.19 The formation of a first redistribution layer 408A formed over the first carrier substrate 102 is shown in accordance with some embodiments. Fig.19 The first redistribution layer 408A shown may be similar to Figure 4 The first redistribution layer 108A shown in the figure can be formed in a similar manner. For example, the first redistribution layer 408A includes a plurality of conductive lines 105A-105E, a plurality of dielectric layers 106A-106D, and a plurality of conductive vias 107A-107D. The first redistribution layer 408A is shown as an illustrative example, and more or fewer conductive lines, dielectric layers, and / or conductive vias can be used in other embodiments.

[0073] exist Fig. 20 In some embodiments, one or more internal supports 110 are attached to the first redistribution layer 408A. The internal supports 110 may be similar to Figure 6 and the internal support 110 described elsewhere herein. Adhesive 109 may be used to attach the internal support 110 to the first redistribution layer 408A. The internal support 110 may be placed using pick and place techniques or the like.

[0074] Figure 21 to Figure 24 The second redistribution layer 408B of the redistribution structure 402 according to some embodiments is shown (see Fig.24 ). The second redistribution layer 408B includes metallization patterns 405A-405B and dielectric layers 406A-406B. The second redistribution layer 408B may have a different number of metallization patterns or dielectric layers than shown. If fewer redistribution layers of the second redistribution layer 408B are to be formed, some of the steps and processes discussed below may be omitted. If more redistribution layers are to be formed, some of the steps and processes discussed below may be repeated.

[0075] exist Fig.21 In the embodiment, dielectric layer 406A is formed on dielectric layer 106D, conductive line 105E and internal support 110. In some embodiments, dielectric layer 406A is formed of a photosensitive material, such as PBO, polyimide, BCB, etc., which can be patterned using a photolithography process. Dielectric layer 406A can be formed by spin coating, lamination, CVD, etc., or a combination thereof. Fig. 22 In the embodiment of the present invention, dielectric layer 406A is then patterned to form openings that expose portions of conductive line 105E. Patterning can be performed by a feasible process, such as by exposing and developing dielectric layer 406A when dielectric layer 406A is a photosensitive material, or by etching using, for example, anisotropic etching when dielectric layer 406A is not a photosensitive material.

[0076] exist Fig.23In some embodiments, a metallization pattern 405A is formed above a dielectric layer 406A. The metallization pattern 405A includes a conductive element extending along the main surface of the dielectric layer 406A and extending through the dielectric layer 406A to physically couple and electrically couple to the conductive layer below (e.g., conductive line 105E). As an example of forming the metallization pattern 405A, a seed layer is formed above the dielectric layer 406A and extending through the dielectric layer 406A to the opening of the conductive line 105E. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer including multiple sublayers formed by different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer above the titanium layer. The seed layer can be formed using, for example, PVD. Then, a photoresist is formed on the seed layer and patterned. The photoresist can be formed by spin coating, etc., and can be exposed and developed for patterning. Patterning forms an opening through the photoresist to expose the seed layer, and the pattern of the opening corresponds to the metallization pattern 405A. Then, a conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material can be formed by plating such as electroplating or chemical plating. The conductive material can include metals, such as copper, titanium, tungsten, aluminum, etc. The combination of the conductive material and the lower portion of the seed layer forms a metallization pattern 405A. The photoresist and the portion of the seed layer where the conductive material is not formed are removed. The photoresist can be removed by a feasible ashing or stripping process, such as using oxygen plasma, etc. Once the photoresist is removed, for example by using a feasible etching process such as wet or dry etching, the exposed portion of the seed layer is removed. The combination of dielectric layer 406A and metallization pattern 405A forms a redistribution layer of the second redistribution layer 408B.

[0077] exist Fig.24 , dielectric layer 406B and metallization pattern 405B are formed. Dielectric layer 406B and metallization pattern 405B may be formed using materials and techniques similar to those of dielectric layer 406A and metallization pattern 405A. In some embodiments, some or all of the dielectric layers of second redistribution layer 408B may be thinner than the dielectric layers of first redistribution layer 408A. In some embodiments, one or more dielectric layers (e.g., dielectric layer 406A or 406B) of second redistribution layer 408B may have a different thickness than other dielectric layers of second redistribution layer 408B. For example, dielectric layer 406B may be thinner than dielectric layer 406A. In some embodiments, the dielectric layers of second redistribution layer 408B each have a thickness in the range of about 2 μm to about 15 μm, but other thicknesses are also possible.

[0078] In some embodiments, some metallization patterns of the second redistribution layer 408B may have different dimensions than metallization patterns below the second redistribution layer 408B. For example, the metallization pattern 405A may be wider or thicker than the metallization pattern 405B. In some embodiments, the metallization pattern of the second redistribution layer 408B may have different dimensions than the conductive lines of the first redistribution layer 408A. For example, the conductive lines and / or conductive vias of the first redistribution layer 408A may be wider or thicker than the conductive lines and / or vias of the metallization pattern of the second redistribution layer 408B, thereby allowing longer horizontal routing.

[0079] In some embodiments, thicker and / or wider metallization dimensions are used to form longer linear electrical paths in the first redistribution layer 408A, while the second redistribution layer 408B has an overall shorter linear electrical path. In some embodiments, the roughness of the planarization layer of the first redistribution layer 408A can be well controlled and more easily accumulated to a larger thickness. In this case, thicker and wider metallization dimensions can be used in the planarization layer to reduce the total impedance of the metallization path per unit length, thereby improving circuit efficiency and / or reducing heat and power consumption. For example, for the same linear length of a given metallization path, the circuit load can be reduced by increasing the thickness and / or width of the metallization pattern, thereby improving efficiency while reducing power consumption and heat. By horizontally extending the metallization path with thicker and / or wider metallization paths, a larger overall package size can be achieved with the same or similar circuit design.

[0080] Go to Fig.25 According to some embodiments, interconnect structures 200A-200B are attached to redistribution structure 100. Interconnect structures 200A-200B may be similar to those previously described with reference to Fig.11 The interconnect structures 200A-200B may be constructed similarly to those previously described with reference to Figure 12-16 The conductive connector 220 may be attached to the redistribution structure 402 in the interconnect region 200' in the manner described. The underfill 224 may be deposited along the sidewalls of the interconnect structures 200A-200B and in the gaps between the interconnect structures 200A-200B and the redistribution structure 402. The conductive connector 220 may be formed to physically and electrically connect the interconnect structures 200A-200B and the topmost metallization pattern (e.g., metallization pattern 405B) of the redistribution structure 402.

[0081] Fig.26 4 shows that the integrated circuit package 350 is attached to the redistribution structure 402 to form the package structure 400 according to some embodiments. The integrated circuit package 350 can be similar to the previous reference Fig.18The integrated circuit package 350 described above may be attached in a similar manner. For example, the conductive connector 312 may be formed on the redistribution structure 402, which may be similar to that described with reference to FIG. Fig.17 The integrated circuit package 350 is physically and electrically connected to the conductive connector 312 to make an electrical connection between the integrated circuit package 350 and the redistribution structure 402. In addition, the external connector 316 and / or the support ring 320 can be similar to the conductive connector 312 described above. Fig.18 Described in a manner that forms.

[0082] Figures 27 to 30B Cross-sectional views and plan views of various embodiments of package structures including an internal support 110 are shown. Figures 27 to 30B The package structure shown in is an illustrative example, and in other embodiments, components such as internal support member 110 may have different sizes, numbers, structures and / or arrangements. Fig. 27 A plan view of a package structure 500 is shown that includes a plurality of internal supports 110 that laterally overlap the same interconnect structure 200 . Fig. 27 The floor plan is similar to Fig.15 For example, in Fig. 27 , internal supports 110C and 110D are shown as each laterally overlapping interconnect structures 200E and 200F. Internal supports 110C and 110D are laterally separated by a distance D7, which can be in the range of 20 μm to 5000 μm, although other distances are possible. In other embodiments, more than two internal supports 110 can laterally overlap the same interconnect structure 200, or different pairs of interconnect structures 200 can have different numbers of associated internal supports 110.

[0083] The internal supports 110 may have the same size or different sizes, and the internal supports may be on different layers of the redistribution structure 100. Fig. 27As shown, the internal support members 110 may have different lengths or widths. For example, within the same redistribution structure 100, some internal support members may have a length L4 in the range of about 2 mm to about 30 mm, while other internal support members may have a length L5 in the range of about 2 mm to about 30 mm. In some embodiments, within the same redistribution structure 100, some internal support members may have a width W2 in the range of about 2 mm to about 4 mm, while other internal support members may have a width W3 in the range of about 3 mm to about 8 mm. In some embodiments, the ratio of the lengths L4:L5 of two internal support members 110 within the same redistribution structure 100 is in the range of about 1:15 to about 1:1, or the ratio of the widths W3:W2 is in the range of about 4:1 to about 3:4. However, other lengths, widths, or ratios are also possible. In some cases, using a ratio such as Fig. 27 The multiple internal supports 110 shown can allow electrical routing to be formed between the internal supports 110, thereby increasing design flexibility. In some cases, using multiple internal supports 110 in this manner can allow the internal supports 110 to be sized to more effectively reduce stress within the redistribution structure 100 (or routing structure 354), or to be placed in a location within the redistribution structure 100 that more effectively reduces stress.

[0084] Fig.28 1 shows a cross-sectional view of a package structure 600 including internal support members 110E-110F in different layers of a redistribution structure 100 according to some embodiments. Fig.18 The package structure 400 shown is similar, except that the internal support member 110 is located in a different layer of the redistribution structure 100. Fig.28 As shown, internal supports 110E are located within dielectric layer 106E and internal supports 110F are located within dielectric layer 106F. Internal supports 110 may be located within different layers of redistribution structure 100 than shown, or a different number of internal supports 110 may be located within a different number of layers than shown. Fig.28 The internal support members 110E and 110F shown in the figure overlap laterally, but in other embodiments, the internal support members 110 formed on different layers of the redistribution structure 100 can be separated laterally. By placing the internal support members 110 in multiple layers of the redistribution structure 100, the redistribution structure 100 (or the wiring structure 354) can have better stability and reduce stress.

[0085] As an example, Fig.28Also shown is package structure 600 attached to package substrate 650 according to some embodiments. In some embodiments, other package structures described herein can be attached to the package substrate in a similar manner. Package structure 600 is attached to package substrate 650 using external connectors 316. Package substrate 650 can be made of a semiconductor material (e.g., silicon or another semiconductor), a semiconductor on insulator (SOI) substrate, etc. In some embodiments, package substrate 650 is attached using a similar method to that described in reference to FIG. Fig.11 The package substrate 650 may be formed by a core substrate of the core substrate 202 of the interconnect structure 200 described above. For example, the package substrate 650 may be a printed circuit board, etc. The package substrate 650 may include active devices and / or passive devices (not shown). As will be appreciated by those skilled in the art, a variety of devices, such as transistors, capacitors, resistors, and combinations thereof, etc., may be used to generate the structural and functional requirements of the device stack design. Any suitable method may be used to form the device.

[0086] The package substrate 650 may also include a metallization layer and a through hole (not shown) and a bonding pad 652 above the metallization layer and the through hole. The metallization layer may be formed above the active and passive devices and is designed to connect various devices to form a functional circuit. In some embodiments, the metallization layer may be formed alternately of a dielectric layer (e.g., a low-k dielectric material) and a conductive material layer (e.g., copper), and has a through hole of the conductive material layer of the interconnect, and may be formed by any suitable process (e.g., deposition, inlay, dual inlay, etc.). In some embodiments, the package substrate 650 is substantially free of active and passive devices. In some embodiments, the external connector 316 is reflowed to attach the package structure 600 to the bonding pad 652. The external connector 316 electrically and / or physically couples the package substrate 650 (including the metallization layer in the package substrate 650) to the package structure 600. In some embodiments, an underfill (not shown) may be formed between the package structure 600 and the package substrate 650 and around the external connector 316. The underfill may be formed by a capillary flow process after the package structure 600 is attached, or may be formed by a suitable deposition method before the package structure 600 is attached.

[0087] Fig.29 FIG. 4 shows a cross-sectional view of a package structure 700 including internal supports 110G-110I to reduce stress caused by a plurality of integrated circuit dies 352A-352C within an integrated circuit package 350 in accordance with some embodiments. The package structure 700 is similar to Fig.18FIG. 4 is a package structure 400 shown in FIG. 4. In some cases, the plurality of integrated circuit dies 352 within the integrated circuit package 350 may induce stress within the redistribution structure 100 or the wiring structure 354. In some cases, the area of ​​maximum stress may be approximately laterally aligned with the gaps between adjacent integrated circuit dies 352. In this manner, stress may be reduced by laterally aligning the internal support members 110 with the gaps between adjacent integrated circuit dies 352 or aligning the internal support members 110 so that they laterally overlap adjacent pairs of integrated circuit dies 352. This may be achieved by: Fig.29 , where the internal support 110G is positioned such that it laterally overlaps the integrated circuit dies 352A and 352B and thus reduces stress caused by the integrated circuit dies 352A and 352B. Fig.29 Also shown are internal supports 1101 that are positioned so that they laterally overlap the integrated circuit dies 352B and 352C, thereby reducing stress caused by the integrated circuit dies 352B and 352C. The internal supports 110 may be located in a different layer of the redistribution structure 100 than shown, or a different number of internal supports 110 may be located in a different number of layers than shown. By positioning the internal supports 110 in alignment with the integrated circuit dies 352 as described above, the stability of the redistribution structure 100 (or wiring structure 354) may be improved and stress may be reduced. Fig.29 Also shown is an internal support 110H that is laterally aligned with the gap between the interconnect structures 200A and 200B, although in other embodiments the internal support 110 is not present.

[0088] In some embodiments, the maximum stress within the redistribution structure 100 or the wiring structure 354 can be located where the gaps between the interconnect structures 200 are approximately laterally aligned with the gaps between the integrated circuit dies 352. For example, the gaps between the interconnect structures 200 can laterally overlap the gaps between the integrated circuit dies 352. In this case, the internal support 110 can be positioned to be approximately laterally aligned with these gaps. Figure 30A-Figure 30C It is shown in Figure 30A-Figure 30C Plan views of package structures 800A, 800B, and 800C are shown in which gaps between interconnect structures 200 are approximately laterally aligned with gaps between integrated circuit dies 352 of integrated circuit package 350 . Figure 30A-Figure 30C The illustrated integrated circuit package 350 may include, for example, a logic die 352B and I / O dies 352A and 352C, although other combinations of integrated circuit dies 352 are possible. Figure 30A-Figure 30C The floor plan is similar to Fig.15 Floor plan shown.

[0089] exist Fig. 30A, the package structure 800A includes four interconnect structures 200 and an internal support 110 within the redistribution structure 100. Each interconnect structure 200 can have a size in the range of about 15 mm×15 mm to about 75 mm×75 mm, for example, about 55 mm×55 mm, although other sizes are possible. The internal support 110 is laterally aligned with the gaps between the interconnect structures 200 and the gaps between the integrated circuit dies 352B. Fig. 30B A package structure 800B is shown that includes nine interconnect structures 200 (one below the integrated circuit package 352) and two internal supports 110. Each interconnect structure 200 can have dimensions in the range of about 10 mm x 10 mm to about 50 mm x 50 mm, for example about 36 mm x 36 mm, although other dimensions are possible. Each internal support 110 is positioned to laterally align the gaps between the interconnect structures 200 and the gaps between the integrated circuit dies 352. Fig. 30C , the package structure 800C includes four interconnect structures 200G-200H of two different sizes and two internal supports 110 within the redistribution structure 100. The larger interconnect structures 200G and 200H can have a size in the range of about 10 mm×15 mm to about 75 mm×100 mm, for example, about 55 mm×76 mm, although other sizes are possible. The smaller interconnect structures 200I and 200J can have a size in the range of about 5 mm×15 mm to about 50 mm×75 mm, for example, about 34 mm×55 mm, although other sizes are possible. The internal supports 110 are each laterally aligned with the gaps between the interconnect structures 200 and the gaps between the integrated circuit dies 352. In some cases, aligning the internal supports 110 between the interconnect structures 200 and the gaps between the integrated circuit dies 352 in this manner can more effectively reduce stress and reduce the size or number of internal supports 110 used within the redistribution structure 100.

[0090] Other components and processes may also be included in the various embodiments described herein. For example, a test structure may be included to assist in verification testing of a 3D package or 3DIC device. The test structure may include test pads such as those formed in a redistribution layer or on a substrate, which allow testing of the 3D package or 3DIC, using probes and / or probe cards, etc. Verification testing may be performed on intermediate structures as well as final structures. In addition, the structures and techniques disclosed herein may be used in conjunction with test methods that incorporate intermediate verification of known good dies to increase yield and reduce costs.

[0091] By utilizing the embodiments described herein, the performance of the device package can be improved, and the reliability of the device package can be improved. The different components of the embodiments described herein can be combined to achieve these benefits and other benefits. In some cases, multiple interconnect structures or multiple integrated circuit dies within a package can cause internal stress within the package, which can cause warping and problems associated with warping, such as cracking or delamination. The technology described herein includes incorporating one or more internal supports within one or more layers of a redistribution structure of the package to provide structural support and reduce stress. The internal support can be placed in a suitable position within the redistribution structure to provide more effective stress reduction. For example, the internal support can be laterally aligned with the gap between adjacent interconnect structures or adjacent integrated circuit dies. This can allow multiple interconnect structures to be used within the package without increasing warping, thereby reducing the cost of the package. The technology described herein is also applicable to joining various structures to form different types of packages. In addition, the use of process technologies as described above can improve yield and connection reliability, especially for packages with larger areas. For example, the technology described herein can reduce stress in large packages with a size greater than 80mm×80mm (e.g., greater than 100mm×100mm), such as system on integrated substrate (SoIS) packages or other types of packages. The techniques described herein can also reduce fine line stress in redistribution structures having finer conductive features, such as conductive features having a line width or line spacing less than about 2 μm. For example, the process techniques described herein can reduce warpage and, therefore, also reduce problems such as cracking or delamination associated with warpage.

[0092] In some embodiments, a device includes a redistribution structure, the redistribution structure including: a conductive component; a dielectric layer; an internal support within a first dielectric layer of the dielectric layer, wherein the internal support is free of passive devices and actives; a first interconnect structure attached to a first side of the redistribution structure; a second interconnect structure attached to the first side of the redistribution structure, wherein the second interconnect structure is laterally adjacent to the first interconnect structure, wherein the internal support laterally overlaps the first interconnect structure and the second interconnect structure. In one embodiment, the internal support is a ceramic. In one embodiment, the internal support is between the second dielectric layer and the third dielectric layer of the dielectric layer. In one embodiment, the internal support is a first internal support of a plurality of first internal supports, wherein the plurality of first internal supports are within the first dielectric layer. In one embodiment, the device includes a plurality of second internal supports, wherein the plurality of second internal supports are within a fourth dielectric layer of the dielectric layer. In one embodiment, the device includes an integrated circuit package attached to a second side of the redistribution structure, wherein the integrated circuit package includes a first integrated circuit die and a second integrated circuit die laterally adjacent to the first integrated circuit die. In one embodiment, the internal support laterally overlaps the first integrated circuit die and the second integrated circuit die. In one embodiment, the device comprises a die attach film on the inner support. In one embodiment, the inner support has a thickness in the range of 15 μm to 100 μm. In one embodiment, the inner support laterally overlaps the first interconnect structure by a distance in the range of 20 μm to 500 μm.

[0093] In some embodiments, a structure includes: a plurality of core substrates attached to a first side of a redistribution structure, wherein the redistribution structure includes a plurality of first redistribution layers; a plurality of internal supports attached to at least one of the plurality of first redistribution layers, wherein the plurality of internal supports are not electrically connected to the plurality of first redistribution layers; a plurality of second redistribution layers on the plurality of first redistribution layers and above the plurality of internal supports, wherein the plurality of internal supports are not electrically connected to the plurality of second redistribution layers; and an integrated device package attached to a second side of the redistribution structure. In one embodiment, the plurality of internal supports are vertically separated from the multi-core substrate by a vertical distance in a range of 100 μm to 15,000 μm. In one embodiment, the first redistribution layer includes a first dielectric layer, wherein the second redistribution layer includes a second dielectric layer, the second dielectric layer being a different dielectric material than the first dielectric layer. In one embodiment, the internal supports are silicon. In one embodiment, the internal supports laterally overlap at least two corresponding core substrates. In one embodiment, the integrated device package includes a plurality of dies, and wherein the internal supports laterally overlap at least two corresponding dies.

[0094] In some embodiments, a method includes: forming a first redistribution layer over a carrier; attaching an internal support to the first redistribution layer, wherein the internal support is an electrically inert material; forming a second redistribution layer over the first redistribution layer and over the internal support; attaching a first interconnect substrate and a second interconnect substrate to the second redistribution layer, wherein the first interconnect substrate is laterally separated from the second interconnect substrate by a gap, wherein the gap is laterally aligned with the internal support; and attaching an integrated circuit die to the first redistribution layer. In one embodiment, the first redistribution layer is formed using a different technique than the second redistribution layer. In one embodiment, the method includes depositing an underfill on the first interconnect structure and the second interconnect structure. In one embodiment, the internal support is attached to the first redistribution layer using a die attach film.

[0095] The features of several embodiments are summarized above so that those skilled in the art can better understand various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent structures do not deviate from the spirit and scope of the present invention, and that various changes, substitutions and modifications can be made without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device, comprising: A redistribution structure, comprising: a plurality of conductive components; a plurality of dielectric layers; and an internal support within a first dielectric layer of the plurality of dielectric layers, wherein the internal support is free of passive devices and active devices; a first interconnect structure attached to a first side of the redistribution structure; A second interconnect structure is attached to the first side of the redistribution structure, wherein the second interconnect structure is laterally adjacent to the first interconnect structure, and wherein the internal support laterally overlaps the first interconnect structure and the second interconnect structure.

2. The semiconductor device according to claim 1, wherein The inner support comprises ceramic.

3. The semiconductor device according to claim 1, wherein The internal support is between a second dielectric layer and a third dielectric layer of the plurality of dielectric layers.

4. The semiconductor device according to claim 1, wherein The internal support is a first internal support of a first plurality of internal supports, wherein the first plurality of internal supports are within the first dielectric layer.

5. The semiconductor device according to claim 4, further comprising a plurality of second inner support members, wherein: The second plurality of internal supports are located within a fourth dielectric layer of the plurality of dielectric layers.

6. The semiconductor device of claim 1 , further comprising an integrated circuit package attached to the second side of the redistribution structure, wherein: The integrated circuit package includes a first integrated circuit die and a second integrated circuit die laterally adjacent to the first integrated circuit die.

7. The semiconductor device according to claim 6, wherein: The inner support laterally overlaps the first integrated circuit die and the second integrated circuit die. 8 . The semiconductor device according to claim 1 , further comprising a die attach film on the inner support.

9. The semiconductor device according to claim 1, wherein: The thickness of the inner support is in the range of 15 μm to 100 μm.

10. The semiconductor device according to claim 1, wherein The internal support laterally overlaps the first interconnect structure by a distance in the range of 20 μm to 500 μm.

11. A semiconductor structure comprising: A plurality of core substrates attached to a first side of a redistribution structure, wherein the redistribution structure comprises: a plurality of first redistribution layers; a plurality of internal supports attached to at least one of the plurality of first redistribution layers, wherein the plurality of internal supports are not electrically connected to the plurality of first redistribution layers; and a plurality of second redistribution layers on the plurality of first redistribution layers and above the plurality of internal support members, wherein the plurality of internal support members are not electrically connected to the plurality of second redistribution layers; and An integrated device package is attached to the second side of the redistribution structure, wherein an internal support of the plurality of internal supports laterally overlaps two core substrates of the plurality of core substrates.

12. The semiconductor structure according to claim 11, wherein: The plurality of internal supports are vertically spaced apart from the plurality of core substrates by a vertical distance in a range of 100 μm to 15,000 μm.

13. The semiconductor structure according to claim 11, wherein: The plurality of first redistribution layers include a plurality of first dielectric layers, wherein the plurality of second redistribution layers include a plurality of second dielectric layers, and the plurality of second dielectric layers are a dielectric material different from that of the plurality of first dielectric layers.

14. The semiconductor structure according to claim 11, wherein: The internal support of the plurality of internal supports is silicon.

15. The semiconductor structure according to claim 11, wherein: The inner supports of the plurality of inner supports laterally overlap at least two corresponding core substrates of the plurality of core substrates.

16. The semiconductor structure according to claim 11, wherein: The integrated device package includes a plurality of dies, and wherein the inner supports of the plurality of inner supports laterally overlap at least two respective dies of the plurality of dies.

17. A method of manufacturing a semiconductor structure, comprising: forming a plurality of first redistribution layers over the carrier; attaching an internal support to the plurality of first redistribution layers, wherein the internal support is an electrically inert material; forming a plurality of second redistribution layers over the plurality of first redistribution layers and over the internal support; attaching a first interconnect substrate and a second interconnect substrate to the plurality of second redistribution layers, wherein the first interconnect substrate is laterally separated from the second interconnect substrate by a gap, wherein the gap is laterally aligned with the internal support; and A plurality of integrated circuit dies are attached to the plurality of first redistribution layers.

18. The method according to claim 17, wherein: The plurality of first redistribution layers are formed using a different technique than the plurality of second redistribution layers.

19. The method of claim 17, further comprising depositing an underfill material on the first interconnect substrate and the second interconnect substrate.

20. The method according to claim 17, wherein: The inner support is attached to the plurality of first redistribution layers using a die attach film.

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