Semiconductor package device and method of manufacturing the same

Abstract

The present disclosure relates to a semiconductor packaging device and a manufacturing method thereof. The semiconductor packaging device comprises a first chip, a first surface of the first chip is provided with a first conductive pad; a second chip is arranged on the first surface of the first chip, the first chip and the second chip are connected through an adhesive layer, a first redistribution line is arranged on a side of the second chip facing the first chip, the first redistribution line is electrically connected with a second conductive pad on the surface of the second chip; an opening is arranged on the second chip and the adhesive layer, the opening penetrates through the second chip and the adhesive layer, and a conductive material is filled in the opening, the conductive material electrically connects the first conductive pad and the first redistribution line. The semiconductor packaging device shortens the electrical connection path between the first chip and the second chip, and is beneficial to realizing better electrical connection effect.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor packaging, and in particular, to a semiconductor packaging device and a manufacturing method thereof. BACKGROUND

[0002] A de-coupling capacitor is a capacitor arranged at a power supply end in a circuit, which functions to maintain stability of the power supply and reduce noise in the circuit. In order to better exert the function of the de-coupling capacitor, it has become a goal pursued in the field of semiconductor packaging to make the integrated passive device (IPD) chip where the de-coupling capacitor is located closer to a logic die.

[0003] In the prior art, there is a way of arranging the IPD chip on the surface of the logic die in a flip chip manner. However, this way has the following problems: in the case where the IPD chip faces away from the logic die, the two need to be electrically connected by a wire-bond manner. However, the conductive path in the wire-bond is relatively long, and the resistance is relatively large, which cannot fully realize the function of the de-coupling capacitor. In the case where the IPD chip faces the logic die, the two need to be electrically connected by using solder balls. However, the thickness of the solder balls is relatively large, and the resistance is relatively large, which also cannot fully realize the function of the de-coupling capacitor.

[0004] In addition, since the hybrid bond requires the size of the conductive pad to be small enough (for example, less than 0.5 nanometers), and the size of the conductive pad of the IPD chip is relatively large (for example, greater than 80 microns), the hybrid bond cannot be used to electrically connect the IPD chip and the logic die.

[0005] Therefore, it is necessary to propose a new technical scheme for improving the electrical connection effect between the IPD chip and the logic die. SUMMARY

[0006] The present disclosure provides a semiconductor packaging device and a manufacturing method thereof.

[0007] In a first aspect, the present disclosure provides a semiconductor packaging device, comprising:

[0008] a first chip, a first surface of the first chip being provided with a first conductive pad;

[0009] a second chip, arranged on the first surface of the first chip, the first chip and the second chip being connected through an adhesive layer, a side of the second chip facing the first chip being provided with a first rewiring line, the first rewiring line being electrically connected with a second conductive pad on the second chip;

[0010] The second chip and the adhesive layer are provided with an opening, the opening penetrates the second chip and the adhesive layer, the opening is filled with a conductive material, and the conductive material electrically connects the first conductive pad and the first redistribution line.

[0011] In some optional embodiments, an inner wall of the opening is provided with an inner lining.

[0012] In some optional embodiments, the opening is partially filled with the conductive material, or the opening is entirely filled with the conductive material.

[0013] In some optional embodiments, the semiconductor packaging device further comprises:

[0014] A molding material is located on the first surface of the first chip and covers the second chip and the adhesive layer.

[0015] In some optional embodiments, the first surface of the first chip is further provided with a third conductive pad; and

[0016] A second redistribution line is provided on a side of the molding material away from the first chip, and a conductive pillar is provided in the molding material, the conductive pillar electrically connecting the second redistribution line and the third conductive pad.

[0017] In some optional embodiments, a surface of the second redistribution line is provided with an electrical connector, and the electrical connector is electrically connected with the second redistribution line.

[0018] In some optional embodiments, the adhesive layer is bonded to the first chip and the second chip by a melting method.

[0019] In some optional embodiments, a portion of the second chip penetrated by the opening is a silicon material, a molding material, or a resin material.

[0020] In a second aspect, the disclosure provides a manufacturing method of a semiconductor packaging device, comprising:

[0021] forming a first redistribution line on a surface of a second chip;

[0022] connecting the second chip to a first surface of a first chip through an adhesive layer, wherein one side of the second chip with the first redistribution line faces the first chip, and the first surface of the first chip is provided with a first conductive pad;

[0023] forming an opening on the second chip and the adhesive layer, wherein the opening penetrates the second chip and the adhesive layer;

[0024] filling the opening with an electrically conductive material to electrically connect the first conductive pad and the first redistribution line.

[0025] In some optional embodiments, before forming the opening on the second chip and the adhesive layer, the method further comprises:

[0026] polishing a surface of the second chip away from the first redistribution line to reduce a thickness of the second chip.

[0027] In some optional embodiments, after filling the opening with the electrically conductive material, the method further comprises:

[0028] forming an electrically conductive pillar on the first surface of the first chip;

[0029] molding on the first surface of the first chip to form a molded material, wherein the molded material covers the second chip, the adhesive layer, and the electrically conductive pillar.

[0030] In some optional embodiments, after molding on the first surface of the first chip to form the molded material, the method further comprises:

[0031] forming a second redistribution line on a side of the molded material away from the first chip;

[0032] providing an electrical connector on a surface of the second redistribution line.

[0033] In some optional embodiments, before forming the opening on the second chip and the adhesive layer, the method further comprises:

[0034] forming an electrically conductive pillar on the first surface of the first chip;

[0035] molding on the first surface of the first chip to form a molded material, wherein the molded material covers the second chip, the adhesive layer, and the electrically conductive pillar.

[0036] polishing a side of the molded material away from the first chip to expose a surface of the second chip away from the first chip.

[0037] In some optional embodiments, after filling the opening with the electrically conductive material, the method further comprises:

[0038] forming a second redistribution line on a side of the molded material away from the first chip;

[0039] providing an electrical connector on a surface of the second redistribution line.

[0040] In the semiconductor packaging device and the manufacturing method thereof provided by the present disclosure, the first redistribution line is electrically connected with the second conductive pad on the second chip, and the conductive material in the opening electrically connects the first conductive pad and the first redistribution line, thereby realizing the electrical connection between the first chip and the second chip without the aid of a connecting line or solder, shortening the electrical connection path between the first chip and the second chip, and facilitating better electrical connection effect. BRIEF DESCRIPTION OF DRAWINGS

[0041] Other features, objects, and advantages of the present disclosure will become more apparent from the following detailed description of non-limiting embodiments made with reference to the drawings:

[0042] Figure 1 And Figure 2 are the first schematic view and the second schematic view of the semiconductor packaging device according to an embodiment of the present disclosure;

[0043] Figures 3-8 is a schematic view of the manufacturing method of the semiconductor packaging device according to an embodiment of the present disclosure.

[0044] SYMBOL DESCRIPTION

[0045] 100, first chip; 110, first conductive pad; 130, third conductive pad; 140, conductive pillar; 200, second chip; 210, first redistribution line; 220, second conductive pad; 300, adhesive layer; 400, opening; 410, conductive material; 420, inner liner; 500, molding material; 520, second redistribution line; 530, electrical connector; 901, wafer; 902, first photoresist; 903, first via; 904, first dielectric layer; 905, first seed layer; 906, second photoresist; 907, first electroplated layer; 908, second dielectric layer; 909, second seed layer; 910, third photoresist. DETAILED DESCRIPTION

[0046] The specific embodiments of the present disclosure will be described below in conjunction with the drawings and examples, and those skilled in the art can easily understand the technical problems solved by the present disclosure and the technical effects produced by the present disclosure through the content described in the present specification. It can be understood that the specific embodiments described herein are only used to explain the related invention, and not to limit the invention. In addition, only the parts related to the invention are shown in the drawings for ease of description.

[0047] It should be noted that the structure, proportion, size and the like shown in the drawings of the specification are only used in conjunction with the content described in the specification for the understanding and reading of those skilled in the art, and do not have technical significance to limit the conditions that can be implemented by the present application. Any modification of the structure, change of the proportion relationship or adjustment of the size, without affecting the effects and purposes that can be achieved by the present application, should still fall within the scope of the technical content disclosed by the present application. At the same time, the terms such as "upper", "first", "second" and "one" in the specification are only for the convenience of clear description, and are not used to limit the scope of the application that can be implemented. The change or adjustment of the relative relationship is also considered as the scope of the application that can be implemented without substantially changing the technical content.

[0048] It should also be noted that the longitudinal cross-section of the embodiments of the present disclosure can be a cross-section corresponding to the front view direction, the transverse cross-section can be a cross-section corresponding to the right view direction, and the horizontal cross-section can be a cross-section corresponding to the upper view direction.

[0049] In addition, the embodiments in the present disclosure and the features in the embodiments can be combined with each other without conflict. The present disclosure will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0050] Figure 1 And Figure 2 are the first and second schematic diagrams of the semiconductor packaging device according to the embodiments of the present application.

[0051] As Figure 1 shown, the semiconductor packaging device in the present embodiment includes a first chip 100 and a second chip 200. The first chip 100 is, for example, a logic chip, and the second chip 200 is, for example, an IPD chip.

[0052] In the present embodiment, the first surface (i.e. the upper surface in Figure 1 ) of the first chip 100 is provided with a first conductive pad 110. The second chip 200 is arranged on the first surface of the first chip 100. The first chip 100 and the second chip 200 are connected through an adhesive layer 300.

[0053] In the present embodiment, the side of the second chip 200 facing the first chip 100 (i.e. the lower side in Figure 1 ) is provided with a first redistribution line 210. The first redistribution line 210 is electrically connected with a second conductive pad 220 on the second chip 200.

[0054] In this embodiment, the second chip 200 and the adhesive layer 300 are provided with an opening 400. The opening 400 penetrates the second chip 200 and the adhesive layer 300. The opening 400 is filled with a conductive material 410. The conductive material 410 electrically connects the first conductive pad 110 and the first redistribution line 210.

[0055] In this embodiment, the first conductive pad 110 is electrically connected to the second conductive pad 220 through the first redistribution line 210 and the conductive material 410, thereby realizing the electrical connection between the first chip 100 and the second chip 200.

[0056] In this embodiment, the inner wall of the opening 400 is provided with an inner liner 420. The inner liner 420 covers the inner wall of the opening 400, and can include one or more metal layers.

[0057] In one example, the opening 400 is partially filled with the conductive material 410. For example, in Figure 1 , the lower part of the opening 400 is filled with the conductive material 410, while the upper part of the opening 400 is not filled with the conductive material 410. In other examples, the opening 400 can be entirely filled with the conductive material 410. In the case that the opening 400 is entirely filled with the conductive material 410, the conductive material 410 can be used for electrical conduction or thermal conduction between the second chip 200 and the structure above.

[0058] In this embodiment, the semiconductor packaging device further includes a molding material 500. The molding material 500 is located on the first surface of the first chip 100 and covers the second chip 200 and the adhesive layer 300. The molding material 500 can protect the internal components and enhance the overall structural strength, etc.

[0059] In this embodiment, the first surface of the first chip 100 is further provided with a third conductive pad 130. The side of the molding material 500 away from the first chip 100 (i.e. the upper side in Figure 1 , the molding material 500 is provided with a second redistribution line 520. The molding material 500 is provided with a conductive pillar 140. The conductive pillar 140 electrically connects the second redistribution line 520 and the third conductive pad 130. Through the conductive pillar 140 and the second redistribution line 520, the electrical signal in the first chip 100 can be guided to the outside.

[0060] In this embodiment, the surface of the second redistribution line 520 is provided with an electrical connector 530, which is electrically connected to the second redistribution line 520. The electrical connector 530 can realize the electrical connection between the semiconductor packaging device and other external components.

[0061] In one example, the adhesive layer 300 is a metal material, which is bonded to the first chip 100 and the second chip 200 by melting. In this way, the thickness of the semiconductor package device can be reduced. In another example, the adhesive layer 300 is a non-metal material, which can be directly bonded to the first chip 100 and the second chip 200.

[0062] In the present embodiment, the portion of the second chip 200 that is penetrated by the opening 400 can be a silicon material (Si), a molding material 500, or a resin material. For example, the opening 400 can be formed in the silicon material portion of the second chip 200 itself. For another example, a molding material 500 or a resin material can be provided around the second chip 200, and the opening 400 can be formed in the molding material 500 or the resin material portion. In the case where the molding material 500 is provided around the second chip 200, the first redistribution line 210 can adopt a redistribution scheme such as eWLB (embedded wafer level ball grid array) or M-series (a kind of fan-out packaging method).

[0063] In the present embodiment, the opening 400 can be a small opening, a medium opening, or a large opening. In the case where the opening 400 is a small opening, the opening 400 and the inner liner 420 can be formed first, and then the molding material 500 is formed. The finally formed opening 400 is shown in the left part of FIG. 4. Figure 2 In the case where the opening 400 is a medium opening, the molding material 500 can be formed first, and then the opening 400 and the inner liner 420 are formed. In this case, the upper surface of the molding material 500 is higher than the top of the opening 400. The finally formed opening 400 is shown in the middle part of FIG. 4. Figure 2 In the case where the opening 400 is a large opening, the molding material 500 can be formed first, and then the opening 400 and the inner liner 420 are formed. In this case, the upper surface of the molding material 500 is flush with the top of the opening 400. The finally formed opening 400 is shown in the right part of FIG. 4. Figure 2

[0064] In the semiconductor package device of the present embodiment, the first redistribution line 210 is electrically connected to the second conductive pad 220 on the second chip 200, and the conductive material 410 in the opening 400 electrically connects the first conductive pad 110 and the first redistribution line 210, thereby achieving electrical connection between the first chip 100 and the second chip 200 without the aid of a connecting wire or solder, shortening the electrical connection path between the first chip 100 and the second chip 200, and facilitating better electrical connection.

[0065] The present embodiment also provides a manufacturing method of a semiconductor package device. The method further includes at least two implementation manners.

[0066] Figures 3-6 ​A first embodiment of a method for manufacturing the semiconductor package device in the present embodiment is shown. The embodiment includes the following steps:

[0067] In a first step, a first redistribution line 210 is formed on a surface of the second chip 200. As shown in FIG. 9A, a first photoresist 902 can be disposed on a wafer 901, and a first via 903 can be formed by dry etching. After the first via 903 is formed, the first photoresist 902 can be removed and a first dielectric layer 904 can be formed on the surface of the wafer 901. On the basis of the first dielectric layer 904, a first seed layer 905 can be formed by physical vapor deposition (PVD). Thereafter, a second photoresist 906 can be formed on the surface of the first seed layer 905. On this basis, as shown in FIG. 9B, a first plating layer 907 can be formed by electroplating. Part of the metal in the first plating layer 907 constitutes the first redistribution line 210. Thereafter, the second photoresist 906 can be removed, and part of the first seed layer 905 can be removed by dry etching, so that the first dielectric layer 904 below the first seed layer 905 is exposed. Next, a second dielectric layer 908 can be formed on the surface of the wafer 901, and an adhesive layer 300 can be formed on the second dielectric layer 908. Figure 3 Figure 4

[0068] In a second step, the second chip 200 is connected to the first surface of the first chip 100 by the adhesive layer 300, wherein the side of the second chip 200 on which the first redistribution line 210 is disposed faces the first chip 100, and the first surface of the first chip 100 is provided with the first conductive pad 110. As shown in FIG. 10A, the wafer 901 can be singulated to obtain a plurality of individual second chips 200. Thereafter, the first chip 100 can be bonded to the second chip 200 by the adhesive layer 300 on the surface of the second chip 200. Figure 5

[0069] In a third step, the surface of the second chip 200 away from the first redistribution line 210 is polished to reduce the thickness of the second chip 200. As shown in FIG. 11A, after the first chip 100 and the second chip 200 are bonded, the second chip 200 can be polished from above to reduce the thickness of the second chip 200. Figure 5

[0070] In a fourth step, an opening 400 is formed on the second chip 200 and the adhesive layer 300, wherein the opening 400 penetrates the second chip 200 and the adhesive layer 300. As shown in FIG. 12A, the opening 400 can be formed by dry etching to penetrate the second chip 200 and the adhesive layer 300. Figure 5

[0071] ​​​​​Fifth step, fill the conductive material 410 in the opening 400 to electrically connect the first conductive pad 110 and the first redistribution line 210. As shown in Figure 6 the second chip 200. After that, the third photoresist 910 can be disposed above the first chip 100, and the conductive material 410 can be formed in the opening 400 by electroplating.

[0072] Sixth step, form the conductive pillar 140 on the first surface of the first chip 100, and mold on the first surface of the first chip 100 to form the molding material 500, wherein the molding material 500 covers the second chip 200, the adhesive layer 300 and the conductive pillar 140, and the second redistribution line 520 is formed on the side of the molding material 500 away from the first chip 100, and the electrical connector 530 is disposed on the surface of the second redistribution line 520. The finally formed semiconductor packaging device is shown in Figure 6 the lowermost.

[0073] Figure 7 and Figure 8 A second embodiment of the manufacturing method of the semiconductor packaging device in the present embodiment is shown. The embodiment includes the following steps:

[0074] The first step is the same as the first step in the first embodiment, which can be referred to the description above.

[0075] The second step is the same as the second step in the first embodiment, which can be referred to the description above.

[0076] The third step, form the conductive pillar 140 on the first surface of the first chip 100, and mold on the first surface of the first chip 100 to form the molding material 500, wherein the molding material 500 covers the second chip 200, the adhesive layer 300 and the conductive pillar 140, and the side of the molding material 500 away from the first chip 100 is polished to expose the surface of the second chip 200 away from the first chip 100. As shown in Figure 7 the conductive pillar 140 can be formed on the upper surface of the first chip 100 by electroplating. After that, the molding material 500 can be formed above the first chip 100 by molding. Next, the semiconductor packaging device can be polished from above as a whole to expose the upper surface of the second chip 200.

[0077] The fourth step, form the opening 400 on the second chip 200 and the adhesive layer 300. As shown in Figure 7 the opening 400 can be formed through the second chip 200 and the adhesive layer 300 by dry etching or laser drilling (Laser Grill).

[0078] In the fifth step, the conductive material 410 is filled in the opening 400 to electrically connect the first conductive pad 110 and the first redistribution line 210. As shown in Figure 8 The conductive material 410 can be formed in the opening 400 by electroplating.

[0079] In the sixth step, the second redistribution line 520 is formed on the side of the molding material 500 away from the first chip 100, and the electrical connector 530 is disposed on the surface of the second redistribution line 520. The finally formed semiconductor package device is shown in Figure 8 the lowermost.

[0080] The first embodiment described above can be applied to the case where the second chip 200 is thin, and the second embodiment described above can be applied to the case where the second chip 200 is thick.

[0081] The method in the present embodiment can achieve similar technical effects as the semiconductor package device in the foregoing embodiments, which will not be repeated here.

[0082] Although the present disclosure has been described and illustrated with reference to specific embodiments, the description and illustrations have been made by way of example only. It is not intended that the present disclosure be limited by the examples and illustrations. Numerous variations, changes, and substitutions will now occur to those skilled in the art without departing from the true spirit and scope of the present disclosure as set forth in the appended claims. The drawings are not necessarily to scale. There can be differences between the technology in the present disclosure and the actual equipment due to variables in the manufacturing process, etc. There can be other embodiments of the present disclosure that are not specifically illustrated. The specification and drawings should be considered illustrative only and not restrictive of the disclosure. Modifications can be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. While the method disclosed herein has been described with reference to particular operations performed in a particular order, it will be understood that these operations can be combined, sub-divided, or re-ordered to form equivalent methods without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of operations are not a limitation of the present disclosure.

Claims

1. A semiconductor package device, comprising: a first chip, a first surface of the first chip being provided with a first conductive pad; a second chip, disposed on the first surface of the first chip, the first chip and the second chip being connected by an adhesive layer, a side of the second chip facing the first chip being provided with a first redistribution line, the first redistribution line being electrically connected with a second conductive pad on the second chip; an opening being formed on the second chip and the adhesive layer, the opening penetrating through the second chip and the adhesive layer, the opening being filled with a conductive material, the conductive material electrically connecting the first conductive pad and the first redistribution line, so that the first conductive pad is electrically connected with the second conductive pad through the first redistribution line and the conductive material; the first conductive pad and the second conductive pad not overlapping in a vertical direction; an inner wall of the opening being provided with an inner liner, the inner liner comprising one or more metal layers; the semiconductor package device further comprising: a molding material, located on the first surface of the first chip and covering the second chip and the adhesive layer; the first surface of the first chip being further provided with a third conductive pad; and a side of the molding material away from the first chip being provided with a second redistribution line, the molding material being provided with a conductive pillar, the conductive pillar electrically connecting the second redistribution line and the third conductive pad.

2. The semiconductor package device of claim 1, wherein, the adhesive layer being bonded to the first chip and the second chip by a melting method. 3.A method for manufacturing a semiconductor package device, comprising: forming a first redistribution line on a surface of a second chip, the first redistribution line being electrically connected with a second conductive pad on the second chip; connecting the second chip to a first surface of a first chip by an adhesive layer, wherein the second chip has a side of the first redistribution line facing the first chip, the first surface of the first chip being provided with a first conductive pad, the first conductive pad and the second conductive pad not overlapping in a vertical direction; forming an opening on the second chip and the adhesive layer, wherein the opening penetrates through the second chip and the adhesive layer; an inner wall of the opening being provided with an inner liner, the inner liner comprising one or more metal layers; filling a conductive material in the opening to electrically connect the first conductive pad and the first redistribution line, so that the first conductive pad is electrically connected with the second conductive pad through the first redistribution line and the conductive material; wherein, after filling the conductive material in the opening, or before forming the opening on the second chip and the adhesive layer, the method further comprises: forming a conductive pillar on the first surface of the first chip; and molding on the first surface of the first chip to form a molding material, wherein the molding material covers the second chip, the adhesive layer and the conductive pillar; the method further comprising: forming a second redistribution line on a side of the molding material away from the first chip; providing an electrical connector on a surface of the second redistribution line.

4. The method of claim 3, wherein, before forming the opening on the second chip and the adhesive layer, the method further comprising: polishing a surface of the second chip distal from the first rewiring line to reduce a thickness of the second chip.

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