Semiconductor device and method of manufacturing a semiconductor structure

Abstract

A semiconductor device includes: a first S / D arrangement including: a silicide-clamped portion having a silicide-clamped structure corresponding to an active region; a first portion corresponding to a metal-to-drain / source (MD) contact structure; a first via-to-MD (VD) structure; and a first buried via-to-source / drain (BVD) structure; a gate structure located over a channel portion of the corresponding active region; and a second S / D arrangement including: a first doped portion of the corresponding active region; and at least one of each of the following: an upper contact arrangement including: a first silicide layer located over the first doped portion, a second portion of the corresponding MD contact structure; and a second VD structure; or a lower contact arrangement including: a second silicide layer located under the first doped portion, and a second BVD structure. Embodiments of the present application also relate to a method of manufacturing a semiconductor structure.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor devices and methods of fabricating semiconductor structures. Background Art

[0002] An integrated circuit (“IC”) includes one or more semiconductor devices. One way to represent a semiconductor device is by means of a planar layout diagram. The layout diagram is generated in the context of design rules. The set of design rules imposes constraints on the placement of corresponding patterns in the layout diagram, such as geographical / spatial constraints, connectivity constraints, etc. Typically, the set of design rules includes a subset of design rules related to the spacing and other interactions between patterns in adjacent or neighboring cells, where the patterns represent conductors in a metallization layer.

[0003] Typically, the set of design rules is specific to a process / technology node through which a semiconductor device will be fabricated based on the layout diagram. The set of design rules compensates for the variability of the corresponding process / technology node. This compensation increases the likelihood that the actual semiconductor device generated from the layout diagram will be an acceptable counterpart of the pseudo-device on which the layout diagram is based. Summary of the Invention

[0004] According to one aspect of an embodiment of the present invention, there is provided a semiconductor device, comprising: a first source / drain (S / D) arrangement, comprising: a silicide-clamped portion having a silicide-clamped structure corresponding to an active region; a first portion located above and electrically coupled to the silicide-clamped portion corresponding to a metal-to-drain / source (MD) contact structure; a first via-to-MD (VD) structure located above and electrically coupled to the first MD contact structure; and a first buried via-to-source / drain (BVD) structure located below and electrically coupled to the silicide-clamped portion; a gate structure located above a channel portion corresponding to the active region and field-coupled to the channel portion corresponding to the active region; and a second S / D arrangement, comprising: a first doped portion corresponding to the active region, with a channel portion located between the first doped portion and the silicide-clamped portion; and at least one of the following: an upper contact arrangement, comprising: a first silicide layer located above and electrically coupled to the first doped portion; and a second portion corresponding to the MD contact structure, located above and electrically coupled to the first silicide layer; and a second VD structure located above and electrically coupled to the second portion corresponding to the MD contact structure; or a lower contact arrangement, comprising: a second silicide layer located below and electrically coupled to the first doped portion; and a second BVD structure located below and electrically coupled to the second silicide layer.

[0005] According to another aspect of an embodiment of the present invention, a semiconductor device is provided, including: a first source / drain (S / D) arrangement corresponding to an active region, the first S / D arrangement including: a first silicide sandwich portion corresponding to the active region, having a silicide sandwich structure; a first portion corresponding to a metal-to-drain / source (MD) contact structure, located above the silicide sandwich portion and electrically coupled to the silicide sandwich portion; and a first buried via to source / drain (BVD) structure, located below the silicide sandwich portion and electrically coupled to the silicide sandwich portion; a second S / D arrangement corresponding to the active region, the second S / D arrangement including: a second silicide sandwich portion corresponding to the active region, having a silicide sandwich structure; a second portion corresponding to the MD contact structure, located above the second silicide sandwich portion and electrically coupled to the second silicide sandwich portion; and a second BVD structure, located below the second silicide sandwich portion and electrically coupled to the second silicide sandwich portion; a third S / D arrangement corresponding to the active region, the third S / D arrangement including: a third silicide sandwich portion corresponding to the active region, having a silicide sandwich structure; a third portion corresponding to the MD contact structure, located above the third silicide sandwich portion and electrically coupled to the third silicide sandwich portion; and a third BVD structure, located below the third silicide sandwich portion and electrically coupled to the third silicide sandwich portion; a first via to MD (VD) structure, located above the third portion corresponding to the MD contact structure and electrically coupled to the third portion; and a buried conductive segment, located in a buried metallization layer, and located below each of the second BVD structure and the third BVD structure and electrically coupled to each of the second BVD structure and the third BVD structure.

[0006] According to yet another aspect of an embodiment of the present invention, a method of manufacturing a semiconductor structure is provided, including: forming an active region having a doped first portion; forming a first silicide layer located above the first portion of the active region and electrically coupled to the first portion; forming a second silicide layer located below the first portion of the active region and electrically coupled to the first portion; forming a first metal-to-drain / source (MD) contact structure located above the first silicide layer and electrically coupled to the first silicide layer; forming a first via to MD (VD) structure located above the MD contact structure and electrically coupled to the MD contact structure; and forming a buried via to source / drain (BVD) structure located below the second silicide layer and electrically coupled to the second silicide layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying Figure 1 The aspects of the present invention may be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of various components may be arbitrarily increased or decreased.

[0008] Figure 1Is a block diagram of a semiconductor device according to some embodiments.

[0009] Figure 2A Is a block diagram of a system according to some embodiments.

[0010] FIG. 2B to FIG. 2E Is a corresponding cross-section according to some embodiments.

[0011] Figure 2F Is a layout diagram according to some embodiments.

[0012] Figure 2G Is a circuit diagram according to some embodiments.

[0013] Figure 3A Is a layout diagram according to some embodiments.

[0014] Figure 3B Is a cross-section according to some embodiments.

[0015] Figure 3C Is a circuit diagram according to some embodiments.

[0016] Figure 4A Is a layout diagram according to some embodiments.

[0017] FIG. 4B to FIG. 4C Is a corresponding cross-section according to some embodiments.

[0018] FIG. 4D to FIG. 4E Is a corresponding circuit diagram according to some embodiments.

[0019] Figure 5A Is a layout diagram according to some embodiments.

[0020] Figure 5B Is a cross-section according to some embodiments.

[0021] Figure 5C Is a circuit diagram according to some embodiments.

[0022] FIG. 6A to FIG. 6E Is a corresponding circuit diagram according to some embodiments.

[0023] FIG. 7A to FIG. 7B And Figures 8 to 9 Is a corresponding flowchart according to some embodiments.

[0024] Fig.10 Is a block diagram of an electronic design automation (EDA) system according to some embodiments.

[0025] Fig.11 Is a block diagram of an integrated circuit (IC) manufacturing system and an IC manufacturing process associated therewith according to some embodiments. Detailed Description

[0026] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components, values, operations, materials, arrangements, etc. are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. Other components, values, operations, materials, arrangements, etc. are contemplated. For example, in the following description, forming a first component above or on a second component may include embodiments in which the first component is in direct contact with the second component, and may also include embodiments in which additional components are formed between the first component and the second component such that the first component and the second component are not in direct contact. Additionally, the present invention may repeat reference numerals and / or characters in various instances. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0027] Moreover, for ease of description, spatially relative terms such as "beneath", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another (or other) element or component as illustrated. In addition to the orientation shown in the figures, spatially relative terms are intended to include different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0028] In some embodiments, a semiconductor device, such as an active transistor, includes: a first source / drain (S / D) region including a silicide sandwich portion corresponding to an active region; a gate structure above a channel portion corresponding to the active region; and a second S / D arrangement including a first doped portion corresponding to the active region, wherein the channel portion is located between the first doped portion and the silicide sandwich portion; and at least one of an upper contact arrangement and a lower contact arrangement. In some embodiments, the silicide sandwich portion corresponding to the active region includes: an active region having a first doped portion; a first silicide layer above the first doped portion; a first metal-to-drain / source (MD) contact structure above the first silicide layer; a first via-to-MD (VD) structure above the MD contact structure; a second silicide layer below the first doped portion; and a first buried via-to-source / drain (BVD) structure below the second silicide layer. In some embodiments, the silicide sandwich S / D region functions as a heater for heating the active transistor. In some embodiments, the silicide sandwich S / D region functions as a temperature sensor for sensing the temperature of the active transistor.

[0029] According to another method, an active transistor is formed by an instance of a channel portion between two instances of an upper contact region, and an instance of a gate structure covers the instance of the channel portion. Additionally according to another method, a thermistor (also known as a temperature-sensitive resistor) (not shown) is formed in one of the metallization layers (not shown) covering the transistor (e.g., in the third metallization layer), and the thermistor serves as a heater for heating the active transistor or as a temperature sensor for sensing the temperature of the active transistor. However, according to another method, the thermal distance of the thermistor is too far to effectively and / or efficiently heat the active transistor, and the temperature of the thermistor is too far to accurately sense the temperature of the active transistor. In some embodiments where the silicide-sandwiched S / D region serves as a heater for heating the active transistor, the silicide-sandwiched S / D region is hot enough adjacent to the active transistor such that, compared to the effectiveness and efficiency of another method, the silicide-sandwiched S / D region heats the active transistor more effectively and efficiently. In some embodiments where the silicide-sandwiched S / D region serves as a temperature sensor for sensing the temperature of the active transistor, the silicide-sandwiched S / D region is hot enough adjacent to the active transistor such that, compared to the accuracy of another method, the silicide-sandwiched S / D region senses the temperature of the active transistor more accurately.

[0030] Figure 1 is a block diagram of a semiconductor device 100 according to some embodiments.

[0031] The semiconductor device 100 includes one or more cell regions 102. Each cell region 102 includes one or more active regions 103. Each active region 103 includes one or more silicide-sandwiched source / drain (S / D) regions 104. In addition to serving as the S / D region of the corresponding transistor itself, each silicide-sandwiched S / D region can also serve as a heater or a temperature sensor.

[0032] Figure 2A is a block diagram of a temperature monitoring system 200 according to some embodiments.

[0033] The temperature monitoring system 200 includes one or more cell regions 202 and temperature measurement circuitry 208 (see Figure 4E , Figure 5B , FIG. 6A to FIG. 6E etc.). The cell regions 202 include silicide-sandwiched source / drain (S / D) regions 204 (not all regions are labeled for ease of illustration) (see Figure 2B , Figure 2F etc.). Depending on the function of the cell region 202, each silicide-sandwiched S / D region 204 is differently and correspondingly used as a heater, a temperature sensor, or the S / D region of the corresponding transistor itself.

[0034] In some embodiments, the cell region 202 is Figure 1An example of the semiconductor device 100. In some embodiments, the temperature monitoring system 200 is Figure 1 An example of the semiconductor device 100.

[0035] FIG. 2B to FIG. 2E Are corresponding cross-sections of the semiconductor structure 205B, the active transistor 224C, the active transistor 224D, and the active transistor 224E according to some embodiments.

[0036] In Figure 2B , the semiconductor structure 205B is a source / drain (S / D) region, including the active region / layer 203 and the silicide-clamped source / drain (S / D) region 204(1). The silicide-clamped S / D region 204(1) is differently and correspondingly used as a heater, a temperature sensor, or the S / D region of the corresponding transistor itself.

[0037] The active layer 203 includes portions 210 and 212. The portion 210 of the active layer 203 is formed of a first semiconductor material, and the portions 210 and 212 are each formed of a different second semiconductor material. In some embodiments, the base material for each of the first and second semiconductor materials is silicon. In some embodiments, the portion 210 is a more heavily doped semiconductor material, and each of the portions 212 is a more lightly doped semiconductor material. In some embodiments, the portion 210 is a doped semiconductor material, and each of the portions 212 is an undoped semiconductor material. For simplicity of discussion, the portion 212 will be referred to as the undoped portion, and the portion 210 will be referred to as the doped portion. In some embodiments, the doped portion 210 is based on epitaxially grown silicon. Details of epitaxial growth of a portion of the active region can be found, for example, in U.S. Pre-Grant Publication No. 10,510,850, published Dec. 17, 2019, and U.S. Pre-Grant Publication No. 10,700,208, published Jun. 30, 2020. Each of the entire contents of these publications 1 is incorporated herein by reference.

[0038] In Figure 2B , the silicide-clamped S / D region 204(1) includes: the doped portion 210; the top silicide layer 214, located above and electrically coupled to the doped portion 210; the metal-to-drain / source (MD) contact structure 218, located above and electrically coupled to the top silicide layer 214; the via-to-MD (VD) structure 220, located above and electrically coupled to the MD contact structure 218; the bottom silicide layer 216, located below and electrically coupled to the doped portion 210; the buried via-to-source / drain (BVD) structure 222, located below the second silicide layer and electrically coupled to it.

[0039] In some embodiments, the top silicide layer 214 is formed by a self-aligned type of silicidation process and is thus referred to as the top silicide layer 214. In some embodiments, the bottom silicide layer 216 is formed by a self-aligned type of silicidation process and is thus referred to as the bottom silicide layer 216. In some embodiments, the top silicide layer 214 and / or the bottom silicide layer 216 include titanium, nickel, cobalt, etc. in order to reduce the Schottky barrier height between the doped portion 210 and the corresponding MD contact structure 218 and BVD structure 222. However, in some embodiments, other metals such as platinum, palladium, etc. are used. In some embodiments, silicidation is performed by blanket depositing an appropriate metal layer and then an annealing step is carried out, which causes the metal to react with the underlying exposed doped portion 210. Then unreacted metal is removed, for example, by using a selective etching process. In some embodiments, the thickness of the top silicide layer 214 and / or the bottom silicide correspondingly ranges from about to about . Details regarding the formation of the silicide layer can be found, for example, in U.S. Patent Nos. 10,510,850 and 10,700,208 mentioned above.

[0040] In Figure 2B , generally, each of the MD contact structure 218, the top silicide layer 214, the doped portion 210, and the bottom silicide layer 216 has a corresponding resistance curve that varies to some extent with temperature. As a result, a unit including the MD contact structure 218 and the silicide-clamped S / D region 204(1) has an overall resistance distribution. Based on the main purpose of a specific instance of the silicide-clamped S / D region 204(1), the overall resistance curve of the unit including the MD contact structure 218 and the silicide-clamped S / D region 204(1) is adjusted accordingly.

[0041] In some embodiments where the main purpose of the silicide-clamped S / D region 204(1) is to be used as a heater, the doped portion 210 is configured to have a resistance that varies relatively little with temperature. In some embodiments where the main purpose of the silicide-clamped S / D region 204(1) is to be used as a heater, the unit including the MD contact structure 218 and the silicide-clamped S / D region 204(1) is configured to have a total resistance that varies relatively little with temperature.

[0042] In some embodiments where the main purpose of the silicide-clamped S / D region 204(1) is to be used as an S / D region itself, the doped portion 210 is configured to have a resistance that varies relatively little with temperature. In some embodiments where the main purpose of the silicide-clamped S / D region 204(1) is to be used as an S / D region itself, the unit including the MD contact structure 218 and the silicide-clamped S / D region 204(1) is configured to have an overall resistance that varies relatively little with temperature.

[0043] In some embodiments where the silicide - sandwiched S / D region 204(1) is used as a temperature sensor, the doped portion 210 is configured to have a resistance that varies significantly with temperature, even for a small temperature change, such that the doped portion 210 behaves similarly to a thermistor (also known as a thermal resistor). In some embodiments where the main purpose of the silicide - sandwiched S / D region 204(1) is to be used as a temperature sensor, the unit including the MD contact structure 218 and the silicide - sandwiched S / D region 204(1) is configured such that the overall resistance varies significantly (if not significantly) with temperature. In some embodiments where the silicide - sandwiched S / D region 204(1) is used as a temperature sensor, the doped portion 210 is configured as a thermistor. In some embodiments where the main purpose of the silicide - sandwiched S / D region 204(1) is to be used as a temperature sensor, the doped portion 210 and one or more of the MD contact structure 218, the top silicide layer 214, or the bottom silicide layer 216 are configured as thermistors. In some embodiments, the thermistor has a positive temperature coefficient (TcR). In some embodiments, the thermistor has a negative TcR.

[0044] In Figure 2C this, the semiconductor device 205C includes: a silicide - sandwiched S / D region 204(1); a silicide - sandwiched S / D region 204(2); an undoped portion 212'; and a gate structure 226. Note that the undoped portion 212' is located between the silicide - sandwiched S / D regions 204(1) and 204(2) and below the gate structure 226. The silicide - sandwiched S / D regions 204(1) and 204(2), the undoped portion 212', and the gate structure 226 together form an active transistor 224C.

[0045] The gate structure 226 is configured to selectively induce a channel in the undoped portion 212'. Thus, the undoped portion 212 is an undoped portion that is referred to herein as a channel portion. The gate structure 226 is referred to herein as being field - coupled to the channel portion 212'. In some embodiments, one or more insulating layers (not shown) are formed between the gate structure 226 and the channel portion 212'.

[0046] In Figure 2C this, each of the silicide - sandwiched S / D regions 204(1) and 204(2) is used as the S / D region of the active transistor 224C itself. However, each of the silicide - sandwiched S / D regions 204(1) and 204(2) may also be used differently and correspondingly as a heater or a temperature sensor.

[0047] In some embodiments where each of the silicide - sandwiched S / D regions 204(1) and 204(2) itself serves as an S / D region, one of the regions 204(1) in the VD structure 220 and the BVD structure 222 in the silicide - sandwiched S / D is coupled to facilitate current flow, while the other remains floating to substantially restrict current flow, and one of the VD structure 220 and the BVD structure 222 in the silicide - sandwiched S / D region 204(2) is coupled to facilitate current flow, while the other remains floating to substantially restrict current flow.

[0048] In Figure 2D a semiconductor device 205D includes a silicide - sandwiched S / D region 204(1) and an upper contact region 228. Regarding Figure 2C a semiconductor device 205C, the silicide - sandwiched S / D region 204(2) has been replaced by the upper contact region 228 in Figure 2D the semiconductor device 205D. The silicide - sandwiched S / D region 204(1), the upper contact region 228, the undoped portion 212', and the gate structure 226 together form an active transistor 224D.

[0049] The upper contact region 228 includes: a doped portion 210; a top silicide layer 214; an MD contact structure 218; and a VD structure 220. The upper contact region 228 is different from the silicide - sandwiched region 204(2) in that it does not include a bottom silicide layer 216 or a BVD structure 222.

[0050] In Figure 2D a semiconductor device, the silicide - sandwiched S / D region 204(1) serves as the S / D region of the active transistor 224D itself. However, the silicide - sandwiched S / D region 204(1) can also be used as a heater or a temperature sensor in various ways.

[0051] In some embodiments where the silicide - sandwiched S / D region 204(1) is used as a heater, the doped portion 210 in the silicide - sandwiched S / D region 204(1) is configured to have a resistance significantly different from that of the doped portion 210 in the upper contact region 228.

[0052] According to another method, an active transistor is formed by an instance of a channel portion 212' between two instances of an upper contact region 228, and an instance of a gate structure 226 covers the instance of the channel portion 212'. Additionally according to another method, a thermistor (also known as a thermistor) (not shown) is formed in one of the metallization layers (not shown) covering the transistor (e.g., in the third metallization layer (at a distance greater than about 2 - 3 μm)), and the thermistor serves as a heater for heating the active transistor or as a temperature sensor for sensing the temperature of the active transistor. However, according to another method, the thermistor is thermally too far away to effectively and / or efficiently heat the active transistor, and the temperature of the thermistor is too far away to accurately sense the temperature of the active transistor. In some embodiments where the silicide sandwiched S / D region 204(1) serves as a heater for heating the active transistor 224D, the silicide sandwiched S / D region 204(1) is thermally close enough to the active transistor 224D such that, compared to the effectiveness and efficiency of another method, the silicide sandwiched S / D region 204(1) heats the active transistor 224D more effectively and efficiently. In some embodiments where the silicide sandwiched S / D region 204(1) serves as a heater for heating the active transistor 224D, the silicide sandwiched S / D region 204(1) is thermally close enough to the active transistor 224D such that, compared to another method, the S / D region 204(1) increases the efficiency of heating the active transistor 224D by about 10 times to about 105 times. In some embodiments where the silicide sandwiched S / D region 204(1) serves as a temperature sensor for sensing the temperature of the active transistor 224D, the silicide sandwiched S / D region 204(1) is thermally close enough to the active transistor 224D such that, compared to the accuracy of another method, the silicide sandwiched S / D region 204(1) more accurately senses the temperature of the active transistor 224D.

[0053] In Figure 2E a semiconductor device 205E includes a silicide sandwiched S / D region 204(1) and a lower contact region 230. Regarding Figure 2C a semiconductor device 205C, the silicide sandwiched S / D region 204(2) in Figure 2E the semiconductor device 205E has been replaced by the lower contact region 230. The silicide sandwiched S / D region 204(1), the lower contact region 230, the undoped portion 212', and the gate structure 226 together form an active transistor 224E.

[0054] The lower contact region 230 includes: a doped portion 210; a bottom silicide layer 216; and a BVD structure 222. The lower contact region 230 is different from the silicide sandwiched region 204(2) in that it does not include a top silicide layer 214, an MD contact structure 218, or a VD structure 220.

[0055] In Figure 2EIn this case, the silicide-clamped S / D region 204(1) serves as the S / D region of the active transistor 224E itself. However, the silicide-clamped S / D region 204(1) can also be used as a heater or a temperature sensor in various ways. In some embodiments where the silicide-clamped S / D region 204(1) is used as a heater, the doped portion 210 in the silicide-clamped S / D region 204(1) is configured to have a resistance significantly different from that of the doped portion 210 in the lower contact region 230.

[0056] Figure 2F is a layout diagram 205F according to some embodiments.

[0057] The layout diagram 205F represents a semiconductor device. More specifically, the layout diagram 205F represents two instances of the active transistor 224C formed side by side, as reflected by the intermediate silicide-clamped S / D regions numbered 204(2) / 204(1). Figure 2C The cross-sectional line IIC-IIC' in shows Figure 2F how it is related to Figure 2F Figure 2C

[0058] Thus, the individual shapes (also called patterns) in the layout diagram 205F represent individual structures in the semiconductor device represented by the layout diagram 205F. For simplicity of discussion, the elements in the layout diagram 205F (and other layout diagrams included herein) are referred to as structures rather than the shapes themselves. For example, each instance of the shape 226 in the layout diagram 205F is a gate shape representing an instance of the gate structure 226. In the following discussion, each instance of the element 226 in the layout diagram 205F is referred to as the gate structure 226 rather than the gate shape 226. For example, each instance of the element 210 in the layout diagram 205F is a doped shape that is designated for doping and represents an instance of the doped portion 210. In the following discussion, each instance of the element 210 of the layout diagram 205F is referred to as the doped portion 210, rather than the doped shape 210. Figure 2C Figure 2C

[0059] The layout diagram 205F is organized according to the trace lines T1, T2, T3, T4, and T5 parallel to the first direction, which is the Y-axis direction in Figure 2F Figure 2F The instances of the non-doped portion 212, the doped portion 210, and the channel portion 212' are grouped into a set representing the active region, which has a long symmetry axis extending in a second direction substantially perpendicular to the first direction, and the second direction is the X-axis in

[0060] ​​​​​Relative to the X-axis, examples of the gate structure 226 and the MD contact structure 218 are scattered and do not overlap with each other. The long symmetry axes of the silicides sandwiching the S / D regions 204(1), 204(2) / 204(1), and 204(2) are substantially aligned with the corresponding tracks T1, T3, and T5. The long symmetry axis of the first example of the gate structure 226 is substantially aligned with the track T2. The long symmetry axis of the second example of the gate structure 226 is substantially aligned with the track T4. In some embodiments, the silicide sandwiching the S / D region 204(1) aligned with T1 is configured to act as a heater, the silicide sandwiching the S / D regions 204(2) / 204(1) aligned with T3 is configured to act as a heat sensor (e.g., a thermistor), and the silicide sandwiching the S / D region 204(2) aligned with T5 is configured to act as a heater.

[0061] In some embodiments, relative to the X-axis, adjacent track lines are separated by a half unit of contact polycrystalline pitch (CPP). Generally, the unit of CPP is specific to the corresponding process node through which the semiconductor device will be fabricated based on the corresponding layout. For example, the track lines T3 and T4 are separated by CPP / 2, and the track lines T3 and T5 are separated by 1*CPP.

[0062] Examples of the MD contact structure 218 are aligned with the corresponding tracks T1, T3, and T5 and are located above the corresponding examples of the doped portion 210. Examples of the top silicide layer 214 corresponding to the examples of the doped portion 210 are aligned with the tracks T1, T3, and T5 correspondingly, but are not shown in Figure 2F (or other layouts disclosed herein) for simplicity of illustration. Examples of the VD structure 220 are aligned with the corresponding tracks T1, T3, and T5 and are located above the corresponding examples of the MD contact structure 218. Examples of the BVD structure 222 are aligned with the corresponding tracks T1, T3, and T5 and are located below the corresponding examples of the doped portion 210. Examples of the bottom silicide layer 216 corresponding to the examples of the doped portion 210 are aligned with the tracks T1, T3, and T5 correspondingly, but are not shown in Figure 2F (or other layouts disclosed herein) for simplicity of illustration.

[0063] Figure 2G is a circuit diagram 205G representing Figure 2F according to some embodiments.

[0064] In circuit diagram 205G, the silicide sandwiches S / D regions 204(1), 204(2) / 204(1) and 204(2) are represented by resistors R_A, R_B, and R_C respectively. More specifically, the voltage VD_a at the instance of T1 alignment of the VD structure 220 is coupled through resistor R_A to the voltage BVD_a at the instance of T1 alignment of the BVD structure 222. The voltage VD_b at the instance of T3 alignment of the VD structure 220 is coupled through resistor R_B to the voltage BVD_b at the instance of T3 alignment of the BVD structure 222. The voltage VD_c at the instance of alignment with T5 of the VD structure 220 is coupled through resistor R_C to the voltage BVD_c at the instance of alignment with T5 of the BVD structure 222.

[0065] Resistor R_A is the series connection of the resistance R_ts_a of the instance of T1 alignment of the top silicide layer 214 ( Figure 2F not shown, but see Figure 2B ), the resistance R_epi_a of the instance of T1 alignment of the doped portion 210, and the resistance R_Bs_a of the instance of T1 alignment of the bottom silicide layer 216 ( Figure 2F not shown, but see Figure 2B ). Resistor R_B is the series connection of the resistance R_ts_b of the instance of T3 alignment of the top silicide layer 214 ( Figure 2F not shown, but see Figure 2B ), the resistance R_epi_b of the instance of T3 alignment of the doped portion 210, and the resistance R_Bs_b of the instance of T3 alignment of the bottom silicide layer 216 (in Figure 2F not shown, but see Figure 2B ). Resistor R_C is the series connection of the resistance R_ts_c of the instance of T5 alignment of the top silicide layer 214 ( Figure 2F not shown, but see Figure 2B ), the resistance R_epi_c of the instance of T5 alignment of the doped portion 210, and the resistance R_Bs_c of the instance of T5 alignment of the bottom silicide layer 216 ( Figure 2F not shown, but see Figure 2B ).

[0066] Figure 3A is the layout diagram 305A according to some embodiments. Figure 3B is the cross-section 305B of a semiconductor device according to some embodiments. According to some embodiments, Figure 3C is for representing Figure 3B circuit diagram 305C.

[0067] FIG. 3A to FIG. 3C follows a numbering scheme similar to FIG. 2A to FIG. 2E Although corresponding, some components are also different. To assist in identifying corresponding but still different components, the numbering convention for FIG. 3A to FIG. 3C Use the 3-series numbering, while FIG. 2A to FIG. 2E use the 2-series numbering for the numbering convention. For example, Figure 3A item 304(1) in row W_205F(1) of Figure 2F is a silicide sandwich region, and the corresponding item 204(1) aligned with T1 in Figure 3A is a silicide sandwich region, and where: the similarities are reflected in the common root _04(1); and the differences are reflected in Figure 2F the corresponding leading digit 3 in FIG. 3A to FIG. 3C and FIG. 2A to FIG. 2E the corresponding leading digit 2 in . Additionally, for example: 310 is a doped portion; R_bs_304(1), R_bs_304(2), and R_bs_304(3) are corresponding resistors; R_epi_304(1), R_epi_304(2), and R_epi_304(3) are corresponding resistors; R_ts_304(1), R_ts_304(2), and R_ts_304(3) are corresponding resistors; 314(1)-314(3) are corresponding top silicide layers; 316(1)-314(3) are corresponding bottom silicide layers; 322(2)-322(3) are corresponding BVD structures; and 326 is a gate structure. For the sake of brevity, the discussion will focus more on

[0068] the differences between Figure 3A and Figure 3B rather than the similarities. Figure 3A The semiconductor device represented by cross-section 305B is an example of the semiconductor device based on layout diagram 305A. Conversely, layout diagram 305A represents cross-section 305B.

[0069] The cross-section line IIIB-IIIB' in Figure 2F shows the relationship between Figure 3AIn [the figure], the active regions corresponding to rows W_205F(1) and W_205F(3) are configured for P-type conductivity, e.g., PMOS transistors, and the active region corresponding to row W_205F(2) is configured for N-type conductivity, e.g., NMOS transistors. In some embodiments, the active regions corresponding to rows W_205F(1) and W_205F(3) are configured for N-type conductivity, and the active region corresponding to row W_205F(2) is configured for P-type conductivity.

[0070] In Figure 3A [the figure], the T1-aligned MD contact structure 318 extends in the Y-axis direction from the silicide sandwich region 304(1) of row W_205F(1) to the silicide sandwich region 304(2) of row W_205F(2), and further extends through the silicide sandwich region 304(3) of row W_205F(3), which is why each of rows W_205F(1), W_205F(2), and W_205F(3) is referred to as Figure 2F an example of the layout pattern of layout diagram 205F. As another example, the T2-aligned gate structure 326(1) extends in the Y-axis direction from the silicide sandwich region 304(1) of row W_205F(1) through the silicide sandwich region 304(2) of row W_205F(2), and further extends through the silicide sandwich region 304(3) of row W_205F(3). As another example, compared with the layout diagram 205F of Figure 2F [the figure], an example of omitting the VD structure 220 from each of rows W_205F(1) and W_205F(2). In some embodiments, the VD structure 220 is included in row W_205F(1) and / or row W_205F(2).

[0071] In Figure 3A [the figure], the layout diagram 305A further includes a cut MD (CMD) shape 332, which indicates that the example of the MD contact structure 318 will be cut into two parts, and these two parts correspond to Figure 3B the MD contact structures 318' and 318” in

[0072] Similarly, in Figure 3A [the figure], rows W_205F(1), W_205F(2), and W_205(3) extend in the X-axis direction. Regarding Figure 3B [the figure], rows W_205F(1), W_205F(2), and W_205(3) extend in the Z-axis direction ( Figure 3B not shown).

[0073] Similarly, Figure 3C [the figure] is the circuit diagram 305C representing Figure 3B [the figure]. Figure 3C [the figure] is also the one representing Figure 3ACircuit diagram of components aligned with T1.

[0074] In circuit diagram 305C, the silicide sandwiches S / D regions 304(1), 304(2), and 304(3) are represented by resistors R_T1 correspondingly. In some embodiments, R_T1 is configured as a heater, R_T3 is configured as a thermal sensor (e.g., a thermistor), and R_T5 is configured as a heater.

[0075] Through resistor R_T1, the voltage V_BVD_304(1) on the BVD structure 322(1) aligned with row W_205F(1) is coupled to the voltage V_MD_304(3) on the VD structure 320 aligned with row W_205F(3).

[0076] In Figure 3C the enlarged view R_T1' shows resistor R_T1 in more detail. In the enlarged view R_T1', the silicide sandwiches S / D regions 304(1), 304(2), and 304(3) are represented by resistors R_304(1), R_304(2), and R_304(3) respectively. More specifically, through resistor R_304(1), the voltage V_BVD_304(1) on the BVD structure 322(1) aligned with row W_205F(1) is coupled to the voltage V_MD_304(1) on a portion of the MD contact structure 318' aligned with row W_205F(1). The voltage V_MD_304(1) on the portion of the MD contact structure 318' aligned with row W_205F(1) is the same as the voltage V_MD_304(2) on the portion of the MD contact structure 318' aligned with row W_205F(2). Through resistor R_304(2), the voltage V_MD_304(2) on the portion of the MD contact structure 318' aligned with row W_205F(2) is coupled to the voltage V_BM0_304(2) on a portion of the buried conductive (BM0) segment 336 aligned with row W_205F(2).

[0077] The BM0 segment 336 is located in the first buried layer (BM_1st) of metallization. In Figure 3A the BM_1 layer is BM0. Figure 3A Adopting such a numbering convention, where the BM_1 layer and the corresponding first buried interconnect layer (BVIA_1st layer) (not shown) are referred to as BM0 and BVIA0 respectively. In some embodiments, the numbering convention assumes that the BM_1 layer is BM1 and the BVIA_1 layer is BVIA1.

[0078] Return Figure 3C, the voltage V_BM0_304(2) on the portion of the BM0 segment 336 aligned with the row W_205F(2) is the same as the voltage V_BM0_304(3) on the portion of the BM0 segment 336 aligned with the row W_205F(3). Through the resistor R_304(3), the voltage V_BM0_304(3) on the portion of the BM0 segment 336 aligned with the row W_205F(3) is coupled to the voltage V_MD_304(3) on the VD structure 320 aligned with the row W_205F(3).

[0079] Figure 4A is the layout diagram 405A according to some embodiments. FIG. 4B to FIG. 4C are the corresponding cross-sections 405B and 405C of the semiconductor device 405B according to some embodiments. According to some embodiments, Figure 4D and Figure 4E are the corresponding circuit diagrams 405D and 405E representing the FIG. 4B to FIG. 4C corresponding first and second aspects.

[0080] FIG. 4A to FIG. 4E follows a numbering scheme similar to that of FIG. 3A to FIG. 3C . Although corresponding, some components are also different. To help identify the corresponding but still different components, the numbering convention uses a 4-series numbering for FIG. 4A to FIG. 4C , while the numbering convention for FIG. 3A to FIG. 3C uses a 3-series numbering. For example, Figure 4A the item 404(1) in the row W_205F(1) of Figure 3A is a silicide sandwiched region, and the corresponding item 304(1) in Figure 4A is a silicide sandwiched region, and wherein: the similarities are reflected in the common root _04(1); and the differences are reflected in the Figure 3A corresponding leading digit 4 in FIG. 4A to FIG. 4E and the corresponding leading digit 3 in FIG. 3A to FIG. 3C . Additionally, for example: 404(1) is a silicide sandwiched S / D region; R_ts_404(1), R_ts_404(2), and R_ts_404(3) are the corresponding resistors; 410(1), 410(2), and 410(3) are the corresponding doped portions; 414(1), 414(2), and 414(3) are the corresponding top silicide layers; 418(3) is an MD contact structure; 422(3) is a BVD structure; 426(1) and 426(2) are the corresponding gate structures; and 420 is a VD structure. For the sake of brevity, the discussion will focus more on the

[0081] differences between Figure 4AThe cross-sectional line IIIB-IIIB' in Figure 4B shows the relationship with Figure 4A . Thus, a single shape (also called a pattern) in layout diagram 405A represents a single structure in cross-section 405B. For simplicity of discussion, the elements in layout diagram 405A (and other layout diagrams included herein as well) are referred to as structures rather than the shapes themselves. To simplify the illustration, not all elements in layout diagram 405A are labeled with item numbers.

[0082] Layout diagram 405A is arranged in three rows W_205F(1), W_205F(2), and W_205F(3) that extend in the X-axis direction. Each of the rows W_205F(1), W_205F(2), and W_205F(3) is Figure 2F a version of layout diagram 205F. Each of the rows W_205F(1), W_205F(2), and W_205F(3) also includes: a BM0 segment, where only the BM0 segment 436 in row W_205F(1) is called out with a reference number; a non-buried conductive (M0) segment 438, where only the M0 segment 438 in row W_205F(1) is labeled with a reference number; a cut M0 (CM0) shape, where only the CM0 shape 440 is labeled with a reference numeral. The M0 segment 438 is located in the first non-buried layer BM_1st of metallization.

[0083] In Figure 4A , the M_1 layer is M0. Figure 4A Such a numbering convention is adopted, where the M_1 layer and the corresponding first non-buried interconnect layer (VIA_1st layer) (not shown) are referred to as M0 and VIA0, respectively. In some embodiments, the numbering convention assumes that the M_1 layer is M1 and the VI_1 layer is BVIA1.

[0084] In layout diagram 405A, the CM0 shape 440 indicates that the M0 segment 438 will be cut into two parts, which are the Figure 4C corresponding M0 segment 438' and M0 segment 438” in

[0085] Similarly, Figure 4D is a circuit diagram 405D that represents the first aspect of Figure 4B and Figure 4C . Figure 4D is also a circuit diagram of some of the components aligned with row W_205F(1) that represents Figure 4A .

[0086] In circuit diagram 405D, the silicide sandwich of row W_205F(1) clamps S / D regions 404(1), 404(2), and 404(3) together to represent resistor R_205F(1). The silicide sandwich of row W_205F(2) clamps the S / D regions together to represent resistor R_205F(2). The silicide sandwich of row W_205F(3) clamps the S / D regions together to represent resistor R_205F(3). In some embodiments, R_205F(1) is configured as a heater, R_205F(2) is configured as a thermal sensor (e.g., a thermistor), and R_205F(3) is configured as a heater.

[0087] Through resistor R_404(1), the voltage V_BVD_404(1) on BVD structure 422(1) aligned with row W_205F(1) is coupled to the voltage V_M0_404(3) on VD structure 420(3) aligned with row W_205F(1).

[0088] In Figure 4D the enlarged view R_205F(1)' shows resistor R_205F(1) in more detail. In enlarged view R_205F(1)', the silicide sandwich S / D regions 404(1), 404(2), and 404(3) are represented by resistors R_404(1), R_404(2), and R_404(3), respectively.

[0089] More specifically, through resistor R_404(1), the voltage V_BVD_404(1) on BVD structure 422(1) is coupled to the voltage V_M0_404(1) on a portion of the M0 segment 438' aligned with track T1.

[0090] In Figure 4A the metallized first non-buried layer (M_1st layer) is M0. Figure 4A Adopting such a numbering convention, where the M_1 layer and the corresponding first non-buried interconnect layer (VIA_1st layer) (not shown) are referred to as M0 and VIA0, respectively. In some embodiments, the numbering convention assumes that the M_1 layer is M1 and the VI_1 layer is VIA1.

[0091] Return Figure 4D, the voltage V_M0_404(2) on the portion of the track T1 of M0 segment 438 that is aligned is the same as the voltage V_M0_404(2) on the portion of the track T3 of M0 segment 438' that is aligned. Through resistor R_404(2), the voltage V_M0_404(2) on the portion of the track T3 of M0 segment 438' that is aligned is coupled to the voltage V_BM0_404(2) on the portion of the track T3 of BM0 segment 436 that is aligned. BM0 segment 436 is located in the buried metallization layer BM0. The voltage V_BM0_404(2) on the portion of the track T3 of BM0 segment 436 that is aligned is the same as the voltage V_BM0_404(3) on the portion of the track T5 of BM0 segment 436 that is aligned. Through resistor R_404(3), the voltage V_BM0_404(3) on the portion of the track T5 of BM0 segment 436 that is aligned is coupled to the voltage V_M0_404(3) on the portion of the track T5 of M0 segment 438'' that is aligned.

[0092] Similarly, Figure 4E represents Figure 4B and Figure 4C the circuit diagram 405E of the second aspect. Figure 4E also represents Figure 4A some of the components aligned with row W_205F(1).

[0093] The circuit diagram 405E represents a temperature calibration circuit including the active transistor 424C(1). In Figure 4E , the influence of the circuit diagram 405E on the active transistor 424C(1) is modeled as the series coupling of the switch 442 and the resistor R_412'(1), and the latter corresponds to the resistance of the channel portion 412'(1). The silicide sandwiching the S / D regions 404(1) and 404(2) is represented by the resistors R_404(1) and R_404(2) respectively. The circuit diagram 405E assumes that at least one of the doped portions of the silicide sandwiching the S / D region 404(1) and the doped portion of the silicide sandwiching the S / D region 404(2) is configured as a thermistor.

[0094] In Figure 4E , when the active transistor 424C(1) is turned off, that is, when the switch 442 is open, the voltage V_BVD_404(1) on the BVD structure 422(1) aligned with row W_205F(1) is coupled to the voltage V_BM0_404(2) on the BVD structure 422(2) aligned with row W_205F(1) through the first signal path, and the first signal path includes the series coupling of the resistors R_404(1) and 404(2).

[0095] More specifically, the first signal path includes the following. The BVD structure 422(1) is coupled to the first terminal of the resistor R_404(1). Through the MD contact structure 418(1) and the VD structure 420(1), the second terminal of the resistor R_404(1) is coupled to a portion of the M0 segment 438' aligned with the track T1. The voltage V_M0_404(1) is shown on the portion of the M0 segment 438' aligned with the track T1. The voltage V_M0_404(1) on the portion of the M0 segment 438' aligned with the track T1 is the same as the voltage V_M0_404(2) on the portion of the M0 segment 438' aligned with the track T3. Through the VD structure 420(2) and the MD contact structure 418(2), the portion of the M0 segment 438' aligned with the track T3 is coupled to the first terminal of the resistor R_404(2). Through the BVD structure 422(2), the second terminal of the resistor R_404(2) is coupled to a portion of the BM0 segment 436 aligned with the track T3. The voltage V_BM0_404(2) is shown on the portion of the BM0 segment 436 aligned with the track T3.

[0096] In Figure 4E , when the active transistor 424C(1) is turned on, i.e., when the switch 442 is closed, current flows through the first signal path (as described above) and the second signal path.

[0097] More specifically, the second signal path includes the following. The BVD structure 422(1) is coupled to the first terminal of the resistor R_Bs_404(1), which represents the resistance of the bottom silicide layer of the silicide sandwich region 404(1).

[0098] The second terminal of R_Bs_404(1) is coupled to the first terminal of the resistor R_epi_404(1), which represents the resistance of the doped portion of the silicide sandwich region 404(1). The third terminal of the resistor R_epi_404(1) is coupled to the first terminal of the switch 442. The second terminal of the switch 442 is coupled to the first terminal of R_412'(1), which (similarly) corresponds to the resistance of the channel portion 412'(1). The second terminal of the resistor R_412'(1) is coupled to the first terminal of the resistor R_epi_404(2), which represents the resistance of the doped portion of the silicide sandwich region 404(2).

[0099] The second terminal of the resistor R_epi_404(2) is coupled to the first terminal of the resistor R_Bs_404(2), which represents the resistance of the bottom silicide layer of the silicide sandwich region 404(2). Through the BVD structure 422(2), the second terminal of the resistor R_Bs_404(2) is coupled to the portion of the BM0 segment 436 aligned with the track T3.

[0100] Using circuit 405E, temperature calibration is achieved by comparing a first voltage difference between V_BVD_401(1) and V_BM0_404(2) when switch 442 is open (i.e., when active transistor 424C(1) is off) with a second voltage difference between V_BVD_401(1) and V_BM0_404(2) when switch 442 is closed (i.e., when active transistor 424C(1) is on).

[0101] According to some embodiments, Figure 5A and Figure 5C are corresponding layout diagrams 505A and 505C. Figure 5B is a representation according to some embodiments Figure 5A and Figure 5C of circuit diagram 505B.

[0102] FIG. 5A to FIG. 5C Follow a numbering scheme similar to FIG. 3A to FIG. 3C Although corresponding, some components are also different. To help identify components that are corresponding but still have differences, the numbering convention uses a 5-series numbering for FIG. 5A to FIG. 5C while FIG. 3A to FIG. 3C uses a 3-series numbering for its numbering convention. For example, Figure 5A the item 504(1) aligned with T1 in row W_205F(1) of Figure 3A is a silicide sandwiched region, and Figure 5A the corresponding item 304(1) in Figure 3A is a silicide sandwiched region, and wherein: the similarities are reflected in the common root _04(1); and the differences are reflected in FIG. 5A to FIG. 5C and FIG. 3A to FIG. 3C the corresponding leading digits 5 and

[0103] Layout diagram 505A represents a semiconductor device based on layout diagram 505A. Thus, the individual shapes (also called patterns) in layout diagram 505A represent individual structures in the semiconductor device represented by layout diagram 505A. For simplicity of discussion, the elements in layout diagram 505A (and also other layout diagrams included herein) are referred to as structures rather than the shapes themselves. Additionally, for example: 504(3), 504(4), 504(5), 504(6), 504(9), 504(10), 504(11), 504(12), 504(13), and 504(14) are corresponding silicide sandwiched S / D regions. For simplicity of illustration, not all elements in layout diagram 505A are labeled with item numbers.

[0104] Organize layout diagram 505A according to trace lines T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, and T13. Layout diagram 505A is arranged as row W_505, which is Figure 2F a version of layout diagram 205F. Row W_505 includes active transistor 524 and a set 544 of pseudo (non-active) transistors.

[0105] In Figure 5A , the T1-aligned BVD structure 522(1) is coupled to the T13-aligned BVD structure 522(7) through BM0 segment 536. BM0 segment 536 corresponds to Figure 3B node 546 in. The T2-aligned silicide sandwich portion 504(2) is thermally adjacent to the T1-aligned silicide sandwich portion 504(1). In some embodiments, if the second structure is less than or equal to about 100 nm from the first structure, the first structure and the second structure are thermally adjacent to each other. In some embodiments where the left edge of the T2-aligned silicide sandwich portion 504(2) is separated from the right edge of the T1-aligned silicide sandwich portion 504(1) by a distance less than or equal to about 100 nm, the T2-aligned silicide sandwich portion 504(2) is thermally adjacent to the T1-aligned silicide sandwich portion 504(1).

[0106] The T13-aligned silicide sandwich portion 504(7) is thermally remote from the T1-aligned silicide sandwich portion 504(1). In some embodiments, if the second structure is about 1 μm or more away from the first structure, the first structure and the second structure are thermally remote from each other. In some embodiments where the left edge of the T13-aligned silicide sandwich portion 504(7) is separated from the right edge of the T1-aligned silicide sandwich portion 504(1) by a distance equal to or greater than about 1 μm, the T13-aligned silicide sandwich portion 504(7) is thermally remote from the T1-aligned silicide sandwich portion 504(1).

[0107] In some embodiments, if the distance G from the first structure to the second structure is in the range of (≈1 μm) ≤ G ≤ (≈1 mm), the first structure and the second structure are thermally remote from each other. In some embodiments where the left edge of the T13-aligned silicide sandwich portion 504(7) is separated from the right edge of the T1-aligned silicide sandwich portion 504(1) by a distance G having a range of (≈1 μm) ≤ G ≤ (≈1 mm), the T13-aligned silicide sandwich portion 504(7) is thermally remote from the T1-aligned silicide sandwich portion 504(1).

[0108] Through resistor R_504(1) corresponding to silicide sandwich portion 504(1) ( Figure 5B) The voltage V_high on the VD structure 520(1) aligned with T1 is coupled to the voltage V_div on the BM0 segment 536. Through the BVD structure 522(7) aligned with T13 and the resistor R_504(7) corresponding to the BVD structure 522(7) aligned with T13, the voltage V_div on the BM0 segment 536 is coupled to the voltage V_low on the VD structure 520(7) aligned with T13.

[0109] Circuit diagram 505B represents a temperature sensing circuit as a voltage divider. The signal path through the voltage divider 505B is as follows. The voltage V_high is coupled to node 546 through the resistor R_504(1) corresponding to the BVD structure 522(1) aligned with T1. Node 546 is coupled to the voltage V_low through the resistor R_504(7) corresponding to the BVD structure 522(7) aligned with T13. The voltage divider 505B generates a divided voltage V_div at node 546.

[0110] In Figure 5B the voltage divider 505B assumes that the resistor R_504(1) (i.e., the doped portion of the silicide-clamped S / D region 504(1)) is configured as a thermistor. Thus, the divided voltage V_div indicates the temperature difference between the resistor R_504(1) (i.e., the doped portion of the silicide-clamped S / D region 504(1)) and the resistor R_504(7) (i.e., the doped portion of the silicide-clamped S / D region 504(7)). In some embodiments, the resistor R_504(7) (i.e., the doped portion of the silicide-clamped S / D region 504(7)) is configured as a thermistor instead of the resistor R_504(1). In some embodiments, the voltage V_high is VDD. In some embodiments, the voltage V_low is VSS. In some embodiments, the voltage V_high and V_low are voltages other than the corresponding VDD and VSS.

[0111] The layout diagram 505A is organized according to the trace lines T1, T2, and T3. The layout diagram 305A is arranged as row W_505, which is Figure 2F a version of the row of the layout diagram 205F that is

[0112] In Figure 5A the active region is configured for P-type conductivity (e.g., PMOS transistors) or for N-type conductivity (e.g., NMOS transistors).

[0113] In Figure 5CIn [reference], the layout diagram 505C is organized according to the trace lines T1, T2, and T3. The layout diagram 505C is arranged in rows W_205F(1), W_205F(2), W_205F(3), W_205F(4), W_205F(5), W_205F(6), and W_205F(7). Each of the rows W_205F(1) to W_205F(7) is Figure 3A a version of row W_205F(3) of the layout diagram 305A of [reference]. Row W_205F(1) includes the active transistor 524. Rows W_205F(2) to W_205F(6) include a set of pseudo (passive) transistors 544.

[0114] In Figure 5C [reference], the active regions corresponding to the odd rows W_205F(1), W_205F(3), W_205F(5), and W_205F(7) are configured for P-type conductivity (e.g., PMOS transistors), and the even rows W_205F(2), W_205F(4), and W_205F(6) are configured for N-type conductivity (e.g., NMOS transistors). In some embodiments, the active regions corresponding to the odd rows are configured for N-type conductivity, and the active regions corresponding to the even rows are configured for P-type conductivity.

[0115] In Figure 5C [reference], the BVD structure 522(1) aligned with row W_205(1) is coupled to the BVD structure 522(7) aligned with row W_205F(7) through the MD contact structure 518(1). The MD contact structure 518(1) corresponds to Figure 3B the node 546 in [reference]. The silicide sandwich portion 504(2) aligned with row W_205F(2) is thermally adjacent to the silicide sandwich portion 504(1) aligned with row W_205F(1). In some embodiments, if the second structure is less than or equal to about 100 nm away from the first structure, the first structure and the second structure are thermally adjacent to each other.

[0116] In some embodiments where the top edge of the silicide sandwich portion 504(2) aligned with row W_205F(2) is separated from the bottom edge of the silicide sandwich portion 504(1) aligned with row W_205F(1) by a distance less than or equal to about 100 nm, the silicide sandwich portion 504(2) aligned with row W_205F(2) is thermally adjacent to the silicide sandwich portion 504(1) aligned with row W_205F(1).

[0117] In some embodiments, for a first structure and a second structure aligned with the same track, where the first structure is also aligned with a first row, if the second structure is aligned with a second row, the second structure is thermally proximate to the first structure, and there are zero or one intermediate rows between the second row and the first row.

[0118] The silicide sandwich portion 504(7) aligned with row W_205F(7) is thermally distant from the silicide sandwich portion 504(1) aligned with row W_205F(1). If the distance G from the first structure to the second structure is within the range of (≈1μm) ≤ G ≤ (≈1mm), the first structure and the second structure are thermally distant from each other. In some embodiments where the top edge of the silicide sandwich portion 504(7) aligned with row W_205F(7) is separated from the bottom edge of the silicide sandwich portion 504(1) aligned with row W_205F(1) by a distance G within the range of (≈1μm) ≤ G ≤ (≈1mm), the silicide sandwich portion 504(7) aligned with row W_205F(7) is thermally distant from the silicide sandwich portion 504(1) aligned with row W_205F(1). In some embodiments, for a first structure and a second structure aligned with the same track, where the first structure is also aligned with a first row, if the second structure is aligned with a second row, the second structure is thermally distant from the first structure. There are M rows between the second row and the first row, where M is a positive integer and 2 ≤ M ≤ (≈1000).

[0119] Through the resistor R_504(1) corresponding to the silicide sandwich portion 504(1)( Figure 5B ), the voltage V_high on the VD structure 520(1) aligned with row W_205F(1) is coupled to the voltage V_div on the MD contact structure 518(1). Through the resistor R_504(7) corresponding to the silicide sandwich portion 504(7) aligned with row W_205F(7), the voltage V_div on the MD contact structure 518(1) is coupled to the voltage V_low on the BVD structure 522(7) aligned with row W-205F(7).

[0120] According to some embodiments, Fig. 6A 、 Figure 6B and Figure 6C are corresponding type 1, type 2, and type 3 Wheatstone bridge structures.

[0121] FIG. 6A to FIG. 6C Each of the Figure 5B is a variant of the voltage divider 505B of FIG. 6A to FIG. 6C . More specifically, each of the Fig. 6A includes a voltage divider 505B and a second voltage divider. Figure 5C The node Nde_P in the

[0122] corresponds to the MD contact structure 518(1) in the Figure 5BThe signal path of the second voltage divider in Fig. 6A is aligned with the node Nde_N in

[0123] In Fig. 6A , the node Nde_P represents the P-type side of the Wheatstone bridge type 1. The node Nde_N represents the N-type side of the Wheatstone bridge type 1. Fig. 6A Assume that each of the resistors R_504(1) and R_504(13) is a thermistor with a positive TcR.

[0124] Figure 6B Assume that: the resistor R_504(1) is a thermistor with a positive TcR; and the resistor R_504(7) is a thermistor with a negative TcR. Figure 6C Assume that: each of the resistors R_504(1) and R_504(13) is a thermistor with a positive TcR; and each of the resistors R_504(7) and R_504(8) is a thermistor with a negative TcR. In some embodiments, the combination of thermistors and resistors is different from the corresponding FIG. 6A to FIG. 6C combination shown.

[0125] In Fig. 6A , the voltage V_Nde_P on the node Nde_P is

[0126]

[0127] where TcR_doped is the temperature coefficient of the doped portion of the corresponding resistor's doped portion.

[0128] Fig.6D is a circuit diagram according to some embodiments.

[0129] Fig.6D The circuit diagram of FIG. 6A to FIG. 6C is a single-ended differential amplifier used with any Wheatstone bridge of Fig. 6A . The non-inverting input of the single-ended differential amplifier receives the voltage V_Nde_P from the node Nde_P of Fig. 6A for example. The inverting input of the single-ended differential amplifier receives the voltage V_Nde_N from the node Nde_N of

[0130]

[0131] To simplify V_out, let (V_Nde_P - V_Nde_N) = ΔV. From FIG. 6A to FIG. 6C V_high and V_low are called, and ΔV can be expressed as follows.

[0132]

[0133] Substituting ΔV into the equation for V_out gives the following result.

[0134]

[0135] Assume that during the operation of the operational amplifier (OPAMP), due to a pseudo-short circuit, V'≈(V+)≈(V-). If V_Nde_P≈V_Nde_N, then ΔV = 0, and V_out can be expressed as follows.

[0136]

[0137] Fig. 6E is a circuit diagram according to some embodiments.

[0138] Fig. 6E The circuit diagram of FIG. 6A to FIG. 6C is a differential amplifier with two inputs used with any Wheatstone bridge of Fig. 6A The non-inverting input of the differential amplifier with two inputs receives the voltage V_Nde_P from the node Nde_P of, for example, Fig. 6A The inverting input of the differential amplifier with two inputs receives the voltage V_Nde_N from the node Nde_N of, for example,

[0139]

[0140] Note that ΔV is as explained above with respect to Fig.6D

[0141] Fig. 7A is a flowchart of a method for manufacturing a semiconductor shape of 700A according to some embodiments.

[0142] The flowchart 700A includes blocks 702 to 712. At block 702, an active region having a first doped portion is formed. An example of the active region is Figure 2B the active region 203 of Figure 2B ​The doped portion 210. In some embodiments, block 702 includes: forming an active region (not shown corresponding to the flowchart block) from a first semiconductor material; and doping the first semiconductor material in a first portion (not shown corresponding to the flowchart block) to become a second semiconductor material different from the first semiconductor material. From block 702, the process proceeds to block 704.

[0143] At block 704, a first silicide layer is formed over the first doped portion of the active region. An example of the first silicide layer is Figure 2B the top silicide layer 214. From block 704, the process proceeds to block 706.

[0144] At block 706, a second silicide layer is formed under the first doped portion of the active region. An example of the second silicide layer is Figure 2B the bottom silicide layer 216. From block 706, the process proceeds to block 708.

[0145] At block 708, an MD contact shape is formed over the first silicide layer. An example of the MD contact shape is Figure 2B the MD contact shape 218. From block 708, the process proceeds to block 710.

[0146] At block 710, a VD shape is formed over the MD contact shape. An example of the VD shape is Figure 2B the VD shape 220. From block 710, the process proceeds to block 712.

[0147] At block 712, a first BVD structure is formed under the second silicide layer and electrically coupled to the second silicide layer. An example of the BVD structure is Figure 2B the BVD structure 222. In some embodiments, flowchart 700A further includes: configuring the semiconductor structure as a heater (not shown corresponding to the flowchart block); or configuring the semiconductor structure as a temperature sensor (not shown corresponding to the flowchart block).

[0148] Figure 7B is a flowchart 700B of a method of fabricating a semiconductor shape according to some embodiments.

[0149] Flowchart 720B includes blocks 722 to 732. At block 722, an active area (AA) shape having a first portion designated for doping is formed. The layout represents a semiconductor device. Thus, a single shape (also referred to as a pattern) in the layout represents a single structure in the semiconductor device represented by the layout. For simplicity of discussion, an example of an element in the layout generated by flowchart 700B is a structure corresponding to the shape, rather than the shape itself. An example of the AA shape is Figure 2B the active region 203. An example of the doped first portion is Figure 2BThe doped portion 210. In some embodiments, block 722 includes: designating the active region as being formed of a first semiconductor material; and designating the active region as being formed of a first semiconductor material (corresponding flowchart block not shown); and designating the first semiconductor material in the first portion as being formed of a second semiconductor material different from the first semiconductor material (corresponding flowchart block not shown). From block 722, the process proceeds to block 724.

[0150] At block 724, a first silicide shape is formed over the first doped portion in the shape of AA. An example of the first silicide shape is Figure 2B the top silicide layer 214. From block 724, the process proceeds to block 726.

[0151] At block 726, a second silicide shape is formed under the first doped portion in the shape of AA. An example of the second silicide shape is Figure 2B the bottom silicide layer 216. From block 726, the process proceeds to block 728.

[0152] At block 728, an MD contact shape is formed over the first silicide shape. An example of the MD contact shape is Figure 2B the MD contact shape 218. From block 728, the process proceeds to block 730.

[0153] At block 730, a VD shape is formed over the MD contact shape. An example of the VD shape is Figure 2B the VD shape 220. From block 730, the process proceeds to block 732.

[0154] At block 732, a first BVD shape is formed under the second silicide shape. An example of the BVD shape is Figure 2B the BVD shape 222.

[0155] Figure 8 is a flowchart of a method 800 for manufacturing a semiconductor device according to some embodiments.

[0156] According to some embodiments, method 800 can be implemented, for example, using an EDA system 1000 (discussed below Fig.10 ) and an integrated circuit (IC) manufacturing system 1100 (discussed below Fig.11 ). Examples of semiconductor devices that can be manufactured according to method 800 include Figure 1 the semiconductor device 100.

[0157] In Figure 8 method 800 includes blocks 802 to 804. At block 802, a layout diagram is generated, which particularly includes one or more of the layout diagrams disclosed herein, etc. According to some embodiments, block 802 can be implemented, for example, using an EDA system 1000 ( Fig.10, (discussed below) to implement. From block 802, the process proceeds to block 804.

[0158] At block 804, based on the layout, (A) perform one or more photolithographic exposures; or (B) fabricate one or more semiconductor masks; or (C) fabricate one or more elements in a layer of a semiconductor device. See Fig.11 the following discussion.

[0159] Fig. 9 is a flowchart of a method for generating a layout according to some embodiments.

[0160] More specifically, according to one or more embodiments, Fig. 9 the flowchart of Figure 8 shows additional blocks in block 802 including

[0161] In Fig. 9 , the flowchart includes blocks 902 to 930. At block 902, a first source / drain (S / D) arrangement is formed. The layout represents a semiconductor device. Thus, a single shape (also referred to as a pattern) in the layout represents a single structure in the semiconductor device represented by the layout. For simplicity of discussion, some examples of elements in the layout generated by flowchart 700B are structures corresponding to the shapes, rather than the shapes themselves. An example of the first S / D arrangement is Figure 2B the S / D region 205B in

[0162] At block 904, a silicide sandwich arrangement is generated. Examples of the silicide sandwich arrangement are Figure 2B the silicide sandwich arrangement 204(1) of Figure 5A the silicide sandwich arrangement 504(1) of Figure 5A and Figure 5C the silicide sandwich arrangement 504(1) of

[0163] At block 906, a first MD contact shape is generated above the silicide sandwich arrangement. Examples of the first MD contact shape are Figure 2B the MD contact structure 218 of Figure 5A and Figure 5C the MD contact shape 522(1) of

[0164] At block 908, a first VD shape is generated above the first MD contact shape. Examples of the first VD shape are Figure 2B the VD structure 220 of Figure 5A and Figure 5C the VD structure 520(1) of

[0165] At block 910, a first BVD shape is generated below the first silicide sandwich arrangement. Examples of the first BVD shape are Figure 2B the BVD structure 222 of Figure 5A and Figure 5C the BVD structure 522(1) of

[0166] At block 912, a channel shape is generated. Examples of the channel shape are Figure 2B the channel portion 212' of Figure 5A the channel portion between the silicide sandwich portions 504(1) and 504(2) of Figure 5C the channel portion between the silicide sandwich portions 504(1) and 504(8) of

[0167] At block 914, a gate shape is generated above the channel shape. Examples of the gate shape are Figure 2B the gate structure 226 of Figure 5A and Figure 5C the gate structures aligned with the track T2 in each of

[0168] At block 915, a second S / D arrangement is generated. Block 916 includes blocks 916 through 920. At block 916, a first doping shape is generated such that the channel shape is located between the first doping shape and the silicide sandwich arrangement. Examples of the first doping shape are Figure 2C the doped portion 210 in the silicide sandwich arrangement 204(2) of Figure 2D the doped portion 210 in the upper contact region 228 of Figure 2E the doped portion 210 in the lower contact region 230 of

[0169] At block 917, the process transfers to block 918 or block 920. In some embodiments, the process proceeds to each of blocks 918 and 920.

[0170] At block 918, an upper contact is generated. Examples of the upper contact arrangement are Figure 2D the upper contact region 228 of Figure 2E the doped portion 210 in the lower contact region 230 of

[0171] At block 922, a first silicide shape is formed above the first doping shape. Examples of the first silicide shape are Figure 2D the top silicide layer 214 of the upper contact region 228 of

[0172] At block 924, a second MD contact shape is formed over the first silicide shape. An example of the second MD contact shape is Figure 2D the MD contact shape 218 of the upper contact region 228 of

[0173] At block 926, a second VD shape is formed over the second MD contact shape. An example of the second VD shape is the VD shape 220 over the Figure 2B upper contact region 228 of

[0174] Now, the discussion returns to block 920. At block 920, a lower contact arrangement is generated. An example of the lower contact arrangement is the Figure 2B lower contact region 230 of

[0175] At block 928, a second silicide shape is formed under the first doping shape. An example of the second silicide shape is the Figure 2E bottom silicide layer 216 of the lower contact region 230 of

[0176] At block 930, a second BVD shape is formed under the second silicide shape. An example of the second BVD shape is the Figure 2B BVD shape 222 of the lower contact region 230 of

[0177] Fig.10 is a block diagram of an electronic design automation (EDA) system 1000 according to some embodiments.

[0178] In some embodiments, the EDA system 1000 includes an autorouting and placement (APR) system. According to one or more embodiments, the design layout diagrams described herein can be implemented, for example, using the EDA system 1000 according to some embodiments.

[0179] In some embodiments, the EDA system 1000 is a general-purpose computing device that includes a hardware processor 1002 and a non-volatile computer-readable storage medium 1004. Among other things, the storage medium 1004 is encoded with computer program code 1006 (i.e., an executable instruction set), that is, stores the computer program code. Executing the instructions 1006 by the hardware processor 1002 represents (at least in part) an EDA tool that implements part or all of the methods described herein according to one or more embodiments (hereinafter, the processes and / or methods mentioned).

[0180] Processor 1002 is electrically coupled to computer-readable storage medium 1004 via bus 1008. Processor 1002 is also electrically coupled to input / output (I / O) interface 1010 via bus 1008. Network interface 1012 is also electrically connected to processor 1002 via bus 1008. Network interface 1012 is connected to network 1014 such that processor 1002 and computer-readable storage medium 1004 can be connected to external components via network 1014. Processor 1002 is configured to execute computer program code 1006 encoded in computer-readable storage medium 1004 such that system 1000 can be used to perform part or all of the processes and / or methods mentioned. In one or more embodiments, processor 1002 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application specific integrated circuit (ASIC), and / or a suitable processing unit.

[0181] In one or more embodiments, computer-readable storage medium 1004 is an electronic, magnetic, optical fiber, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, computer-readable storage medium 1004 includes semiconductor or solid state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), hard disk, and / or optical disk. In one or more embodiments using optical disks, computer-readable storage medium 1004 includes compact disk read-only memory (CD-ROM), compact disk read / write (CD-R / W), and / or digital video disk (DVD).

[0182] In one or more embodiments, storage medium 1004 stores computer program code 1006 that is configured to make system 1000 (where such execution (at least in part) represents an EDA tool) available to perform part or all of the processes and / or methods mentioned. In one or more embodiments, storage medium 1004 also stores information that facilitates the performance of part or all of the processes and / or methods mentioned. In one or more embodiments, storage medium 1004 stores standard cell library 1007, including standard cells such as those disclosed herein. In one or more embodiments, storage medium 1004 stores one or more layout diagrams 1009 corresponding to one or more layouts disclosed herein.

[0183] EDA system 1000 includes I / O interface 1010. I / O interface 1010 is coupled to external circuitry. In one or more embodiments, I / O interface 1010 includes a keyboard, keypad, mouse, trackball, trackpad, touch screen, and / or cursor direction keys for communicating information and commands to processor 1002.

[0184] The EDA system 1000 also includes a network interface 1012 coupled to the processor 1002. The network interface 1012 allows the system 1000 to communicate with a network 1014 that is connected to one or more other computer systems. The network interface 1012 includes a wireless network interface, such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA, or a wired network interface, such as ETHERNET, USB, or IEEE-1364. In one or more embodiments, part or all of the described processes and / or methods are implemented in two or more systems 1000.

[0185] The system 1000 is configured to receive information through the I / O interface 1010. The information received through the I / O interface 1010 includes one or more instructions, data, design rules, a standard cell library, and / or other parameters for processing by the processor 1002. The information is transmitted to the processor 1002 through the bus 1008. The EDA system 1000 is configured to receive UI-related information through the I / O interface 1010. The information is stored in the computer-readable medium 1004 as a user interface (UI) 1042.

[0186] In some embodiments, part or all of the mentioned processes and / or methods are implemented as a stand-alone software application for execution by a processor. In some embodiments, part or all of the mentioned processes and / or methods are implemented as a software application that is part of an additional software application. In some embodiments, part or all of the mentioned processes and / or methods are implemented as a plug-in of a software application. In some embodiments, part or all of the described processes and / or methods are executed as a software application that is part of an EDA tool. In some embodiments, part or all of the mentioned processes and / or methods are implemented as a software application used by the EDA system 1000. In some embodiments, a layout diagram including standard cells is generated using a tool such as VIRTUOSO available from CADENCE DESIGN SYSTEMS, Inc. or another suitable layout generation tool.

[0187] In some embodiments, the process is implemented as the function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage devices or memory units, such as one or more of optical discs such as DVDs, magnetic disks such as hard disks, and semiconductor memories such as ROM, RAM, and memory cards.

[0188] Fig.11FIG. 1100 is a block diagram of an integrated circuit (IC) manufacturing system 1100 and an IC manufacturing process associated therewith, according to some embodiments. In some embodiments, based on a layout, the manufacturing system 1100 is used to manufacture at least one of the following: (A) one or more semiconductor masks or (B) at least one element in a layer of a semiconductor integrated circuit.

[0189] In Fig.11 , the IC manufacturing system 1100 includes entities that interact with each other during a design, development, and manufacturing cycle, such as a design house 1120, a mask house 1130, and an IC manufacturer / fabricator (“fab”) 1150 and / or services related to manufacturing the IC device 1160. The entities in the system 1100 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of the design house 1120, the mask house 1130, and the IC fabrication plant 1150 are owned by a single larger company. In some embodiments, two or more of the design house 1120, the mask house 1130, and the IC fabrication plant 1150 coexist in a common facility and use common resources.

[0190] A design house (or design team) 1120 generates an IC design layout 1122. The IC design layout 1122 includes various geometric patterns designed for the IC device 1160. The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that make up the various elements of the IC device 1160 to be manufactured. The individual layers combine to form various IC components. For example, a portion of the IC design layout 1122 includes various IC features, such as source regions, gate electrodes, source and drain electrodes, metal lines or vias for interlayer interconnects, and openings for bonding pads, formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. The design house 1120 implements appropriate design procedures to form the IC design layout 1122. The design process includes one or more of logic design, physical design, or placement and routing. The IC design layout 1122 is presented in one or more data files having information of the geometric patterns. For example, the IC design layout 1122 can be represented in a GDSII file format or a DFII file format.

[0191] The mask chamber 1130 includes data preparation 1132 and mask fabrication 1144. The mask chamber 1130 uses the IC design layout 1122 to fabricate one or more masks 1145 for fabricating the respective layers of the IC device 1160 according to the IC design layout 1122. The mask chamber 1130 performs mask data preparation 1132, in which the IC design layout 1122 is translated into a representation data file ("RDF"). The mask data preparation 1132 provides the RDF to the mask fabrication 1144. The mask fabrication 1144 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (intermediate mask) 1145 or a semiconductor wafer 1153. The design layout 1122 is manipulated by the mask data preparation 1132 to conform to the specific characteristics of the mask writer and / or the requirements of the IC fabrication plant 1150. In Fig.11 it, the mask data preparation 1132 and the mask fabrication 1144 are shown as separate elements. In some embodiments, the mask data preparation 1132 and the mask fabrication 1144 can be collectively referred to as mask data preparation.

[0192] In some embodiments, the mask data preparation 1132 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other processing effects, etc. The OPC adjusts the IC design layout 1122. In some embodiments, the mask data preparation 1132 includes additional resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shifting masks, other suitable techniques, etc. or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

[0193] In some embodiments, the mask data preparation 1132 includes a mask rule checker (MRC), which checks the IC design layout 1122 that has been processed in the OPC with a set of mask creation rules that contain certain geometric and / or connectivity restrictions to ensure sufficient margins to address issues such as variability in the semiconductor manufacturing process. In some embodiments, the MRC modifies the IC design layout 1122 to compensate for the limitations during mask fabrication 1144, which may undo some of the modifications performed by the OPC to meet the mask creation rules.

[0194] In some embodiments, mask data preparation 1132 includes lithography process check (LPC), and the LPC simulation processes that will be implemented by IC fabricator 1150 to fabricate IC device 1160. The LPC simulates this process based on IC design layout 1122 to create a simulated fabricated device, such as IC device 1160. The process parameters in the LPC simulation may include parameters related to various processes of the IC manufacturing cycle, parameters related to the tools used for manufacturing the IC, and / or other aspects of the manufacturing process. The LPC check takes into account various factors, such as aerial image contrast, depth of focus ("DOF"), mask error enhancement factor ("MEEF"), and other suitable factors, etc. or combinations thereof. In some embodiments, after the simulated fabricated device created by the LPC, if the shape of the simulated device is not close enough to meet the design rules, OPC and / or MRC are repeated to further refine IC design layout 1122.

[0195] It should be understood that the above description of mask data preparation 1132 has been simplified for clarity. In some embodiments, data preparation 1132 includes additional features such as logic operation (LOP) to modify IC design layout 1122 according to manufacturing rules. In addition, the processes applied to IC design layout 1122 during data preparation 1132 can be performed in various different orders.

[0196] After mask data preparation 1132 and during mask manufacturing 1144, a mask 1145 or a set of masks 1145 is manufactured based on the modified IC design layout 1122. In some embodiments, mask manufacturing 1144 includes performing one or more lithographic exposures based on the IC design layout 1122. In some embodiments, an electron beam (e-beam) or a mechanism of multiple electron beams is used to form a pattern on the mask (photomask or intermediate mask) 1145 according to the modified IC design layout 1122. The mask 1145 can be formed by various techniques. In some embodiments, the binary technique is used to form the mask 1145. In some embodiments, the mask pattern includes opaque regions and transparent regions. A radiation beam, such as an ultraviolet (UV) beam, for exposing an image-sensitive material layer (e.g., photoresist) that has been coated on a wafer is blocked by the opaque regions and transmitted through the transparent regions. In one example, the binary intermediate mask of the mask 1145 includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, the phase-shift technique is used to form the mask 1145. In the phase-shift mask (PSM) version of the mask 1145, various features in the pattern formed on the phase-shift mask are configured to have an appropriate phase difference to enhance resolution and imaging quality. In various examples, the phase-shift mask can be an attenuated PSM or an alternating PSM. The one or more masks generated by mask manufacturing 1144 are used in various processes. For example, such masks are used in an ion implantation process to form various doped regions in the semiconductor wafer 1153, in an etching process to form various etched regions in the semiconductor wafer 1153, and / or in other suitable processes.

[0197] IC fabrication facility 1150 includes fabrication tools 1152 that are configured to perform various fabrication operations on the semiconductor wafer 1153 such that an IC device 1160 is fabricated according to one or more masks (e.g., mask 1145). In various embodiments, the fabrication tools 1152 include one or more of the following: a wafer stepper, an ion implanter, a photoresist coater, a processing chamber (e.g., a CVD chamber or an LPCVD furnace), a CMP system, a plasma etching system, a wafer cleaning system, or other fabrication devices capable of performing one or more suitable fabrication processes as discussed herein.

[0198] IC fabricator 1150 uses mask 1145 fabricated by provided mask chamber 1130 to fabricate IC device 1160. Thus, IC fabricator 1150 uses IC design layout 1122 at least indirectly to fabricate IC device 1160. In some embodiments, IC fabricator 1150 uses mask 1145 to fabricate semiconductor wafer 1153 to form IC device 1160. In some embodiments, IC fabrication includes performing one or more lithographic exposures at least indirectly based on IC design layout 1122. Semiconductor wafer 1153 includes a silicon substrate or other suitable substrate having a plurality of material layers formed thereon. Semiconductor wafer 1153 also includes one or more of various doped regions, dielectric components, and multi-level interconnects (formed in subsequent fabrication steps).

[0199] Regarding integrated circuit (IC) fabrication systems (e.g., Fig.11 system 1100) and details of the associated IC fabrication processes are found, for example, in the following: U.S. Patent No. 9,256,709, issued February 9, 2016; U.S. Patent Publication No. 20150278429, published October 1, 2015; U.S. Patent Publication No. 20140040838, published February 6, 2014; and U.S. Patent No. 7,260,442, issued August 21, 2007, the entire contents of each of which are incorporated herein by reference.

[0200] For example, in U.S. Patent No. 9,256,709, an IC design layout is generated in a design house (or design team). The IC design layout includes various geometric patterns designed for IC devices. The geometric patterns correspond to the patterns of metal, oxide, or semiconductor layers that make up the various components of the IC device to be fabricated. The individual layers are combined to form various IC functions. For example, parts of the IC design layout include various IC components such as active regions, gate electrodes, source and drain electrodes, metal lines or vias for interlayer interconnects, and openings for pads formed in the semiconductor, which will be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. The design house performs appropriate design processes to form the IC design layout. The design processes may include logic design, physical design, and / or layout and routing. The IC design layout is presented in one or more data files with geometric pattern information. The mask house uses the IC design layout to fabricate one or more masks, which are used to fabricate the individual layers of the IC device according to the IC design layout. The mask house performs mask data preparation, in which the IC design layout is converted into a form that can be physically written by a mask writer, and the design layout prepared by the mask data preparation is modified to comply with a specific mask manufacturer and / or mask vendor, and then manufacturing is carried out. In this embodiment, mask data preparation and mask manufacturing are illustrated as separate elements; however, mask data preparation and mask manufacturing may be collectively referred to as mask data preparation. Mask data preparation generally includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors such as those that may be caused by diffraction, interference, or other processing effects. Mask data preparation may include other resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shift masks, other suitable techniques, or combinations thereof. Mask data preparation 132 also includes a mask rule checker (MRC), which uses a set of mask creation rules to check the IC design layout that has already been processed in the OPC. The mask creation rules may include some geometric and connectivity restrictions to ensure sufficient margins.

[0201] For example, in U.S. Publication No. 20150278429 before authorization, in one embodiment, an IC manufacturing system may employ maskless lithography techniques, such as electron beam lithography or optical maskless lithography. In such a system, mask manufacturing is bypassed, and the IC design layout is modified through data preparation suitable for wafer processing using a specific maskless lithography technique. The data preparation modifies the design layout suitable for subsequent operations in the IC manufacturing system. The result of the data preparation is represented by one or more data files, such as files in GDSII file format or DFII file format. One or more data files include information on geometric patterns, such as polygons representing main design patterns and / or auxiliary components. In this embodiment, one or more data files also include auxiliary data generated by the data preparation. The auxiliary data will be used to enhance various operations of the IC manufacturing system, such as mask manufacturing performed by the mask chamber and wafer exposure performed by the IC manufacturer.

[0202] For example, in Publication No. 20140040838 before authorization, the IC design layout is presented in one or more data files having geometric pattern information. In one example, the IC design layout is represented in the "GDS" format known in the art. In an alternative embodiment, the IC design layout may be transferred between components in the IC manufacturing system in an alternative file format such as DFII, CIF, OASIS, or any other suitable file type. The IC design layout 300 includes various geometric patterns representing components of the integrated circuit. For example, the IC design layout may include main IC components, such as active regions, gate electrodes, source and drain electrodes, metal lines, interlayer vias, and openings for pads formed in the semiconductor, which will be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. The IC design layout may also include some auxiliary components, such as those for imaging effects, process enhancement, and / or mask identification information.

[0203] For example, in U.S. Patent No. 7,260,442, a mask manufacturing system includes: a processing tool for processing a mask; a metrology tool connected to the processing tool for inspecting the mask and obtaining inspection results; a controller coupled to the processing tool and the metrology tool for generating a manufacturing model of the processing tool and calibrating the manufacturing model based on equipment data, material data, and inspection results of the mask. The mask manufacturing system may include at least one processing tool, metrology tool, controller, database, and manufacturing execution system. The processing tool may be an exposure tool, developer, etcher, or photoresist stripper. The metrology tool performs post-etch inspection or post-stripping inspection and obtains post-etch inspection results or post-stripping inspection results, respectively. The controller is used for run-to-run control of the processing tool, including feedforward control and feedback control. The controller receives post-etch or post-stripping inspection results from the metrology tool and retrieves device and material data from the database. The controller connected to the manufacturing execution system generates a manufacturing model of the processing tool and calibrates the manufacturing model based on equipment data, material data, and inspection results of the mask. The controller also monitors the operating conditions of the processing tool and adjusts the manufacturing model of the processing tool during processing.

[0204] In an embodiment, a semiconductor structure includes: an active region having a doped first portion; a first silicide layer located over and electrically coupled to the first portion of the active region; a first metal-to-drain / source (MD) contact structure located over and electrically coupled to the first silicide layer; a first via-to-MD (VD) structure located over and electrically coupled to the MD contact structure; a second silicide layer located under and electrically coupled to the first portion of the active region; a first buried via-to-source / drain (BVD) structure located under and electrically coupled to the first silicide layer. In an embodiment, the first portion of the active region is a first material, the first material is an epitaxially grown semiconductor that has been doped; and a portion of the active region that is substantially adjacent to the first portion of the active region is a second material, the second material being a semiconductor material of a different type than the first material. In an embodiment, the semiconductor structure is a heater; or the semiconductor structure is a temperature sensor.

[0205] In an embodiment, a semiconductor device includes: a first source / drain (S / D) arrangement including: a silicide sandwich portion having a silicide sandwich structure corresponding to an active region; a first portion located above and electrically coupled to the silicide sandwich portion corresponding to a metal-to-drain / source (MD) contact structure; a first via-to-MD (VD) structure located above and electrically coupled to the first MD contact structure; and a first buried via-to-source / drain (BVD) structure located below and electrically coupled to the silicide sandwich portion; a gate structure located above and field-coupled to a channel portion of the corresponding active region; and a second S / D arrangement including: a first doped portion of the corresponding active region, the channel portion being located between the first doped portion and the silicide sandwich portion; and at least one of each of the following: an upper contact arrangement including: a first silicide layer located above and electrically coupled to the first doped portion; and a second portion of the corresponding MD contact structure located above and electrically coupled to the first silicide layer; and a second VD structure located above and electrically coupled to the second portion of the corresponding MD contact structure; or a lower contact arrangement including: a second silicide layer located below and electrically coupled to the first doped portion; and a second BVD structure located below and electrically coupled to the second silicide layer.

[0206] In an embodiment, the silicide sandwich portion includes: a second doped portion corresponding to the active region; a third silicide layer located above and electrically coupled to the second doped portion and electrically coupled to the first portion of the first MD contact structure; and a fourth silicide layer located below and electrically coupled to the second doped portion and electrically coupled to the first BVD structure. In an embodiment, the first and second doped portions are a first material, the first material is a doped epitaxially grown semiconductor; and the channel portion is a second material, the second material is a semiconductor different from the first material. In an embodiment, the first S / D arrangement, the channel portion, the gate structure, and the second S / D arrangement together serve as a transistor; the first S / D arrangement is also a temperature sensor; the silicide sandwich portion is a first silicide sandwich portion; the first silicide sandwich portion corresponding to the active region and the first doped portion corresponding to the active region are corresponding portions of the same first active region; the first portion of the corresponding MD contact structure is a part of the first MD contact structure; and the semiconductor device further includes: a third S / D arrangement including: a second silicide sandwich portion having a silicide sandwich structure of a second active region, the second active region being separate from the first active region; a third portion of the first MD contact structure located above and electrically coupled to the second silicide sandwich portion; a third VD structure located above and electrically coupled to the third portion of the first MD contact structure; and a third BVD structure located below and electrically coupled to the second silicide sandwich portion; and the third S / D arrangement represents a calibration device related to the first S / D arrangement.

[0207] In an embodiment, the second silicide sandwich portion includes: a second doped portion of the second active region; a third silicide layer located above and electrically coupled to the second doped portion and electrically coupled to the third portion of the first MD contact structure; and a sixth silicide layer located below and electrically coupled to the second doped portion and electrically coupled to the third BVD structure; and the conduction type of the first active region is the same as the conduction type of the second active region. In an embodiment, the semiconductor device further includes: at least a third active region located between the first active region and the second active region. In an embodiment, the second S / D is thermally adjacent to the first S / D, and the third S / D is thermally remote from the first S / D. In an embodiment, the semiconductor device further includes: a buried conductive segment located in a buried metallization layer and located below and electrically coupled to each of the first BVD structure and the third BVD structure; and an operational amplifier (op-amp); and wherein: the first S / D and the third S / D form a voltage divider circuit configured to provide a voltage division; the first S / D is electrically coupled to a node represented by the first MD contact structure; the third S / D is electrically coupled to the node; a third voltage on the node represents the voltage division with respect to a first voltage on the first BVD structure of the first S / D and a second voltage on the third BVD structure of the third S / D; and a first input of the op-amp is configured to receive the voltage division. In an embodiment, the second S / D includes the upper contact arrangement and the lower contact arrangement.

[0208] In an embodiment, the first S / D arrangement is a heater. In an embodiment, the first S / D arrangement, the channel portion, the gate structure, and the second S / D arrangement together act as a transistor; the first S / D arrangement is also a temperature sensor; the silicide sandwich portion is a first silicide sandwich portion; the first silicide sandwich portion of the corresponding active region and the first doped portion of the corresponding active region are corresponding portions of the same first active region; the semiconductor device further includes: a third S / D arrangement including: a second silicide sandwich portion of the first active region having the silicide sandwich structure; a third MD contact structure located above and electrically coupled to the second silicide sandwich portion; a third VD structure located above and electrically coupled to the third MD contact structure; and a third BVD structure located below and electrically coupled to the second silicide sandwich portion; and the third S / D arrangement represents a calibration device related to the first S / D arrangement. In an embodiment, the gate structure is a first gate structure: and the semiconductor device further includes at least a second gate structure between the second S / D arrangement and the third S / D arrangement. In an embodiment, the second S / D arrangement is in thermal proximity to the first S / D arrangement, and the third S / D arrangement is thermally remote from the first S / D arrangement. In an embodiment, the semiconductor device further includes: a buried conductive segment located in a buried metallization layer and located below and electrically coupled to each of the first BVD structure and the third BVD structure; and an operational amplifier; and wherein: the first S / D arrangement and the third S / D arrangement form a voltage divider circuit configured to provide a voltage division; the first S / D arrangement is electrically coupled to a node represented by the buried conductive segment; the third S / D arrangement is electrically coupled to the node; and with respect to a first voltage on the first MD contact of the first S / D arrangement and a second voltage on the third portion of the first MD contact structure of the third S / D arrangement, a third voltage on the node represents the voltage division; and a first input of the operational amplifier is configured to receive the voltage division.

[0209] In an embodiment, a semiconductor device includes: a first source / drain (S / D) arrangement corresponding to an active region, the first S / D arrangement including: a first silicide sandwich portion of the corresponding active region having a silicide sandwich structure; a first portion of a corresponding metal-to-drain / source (MD) contact structure located above and electrically coupled to the silicide sandwich portion; and a first buried via to source / drain (BVD) structure located below and electrically coupled to the silicide sandwich portion; a second S / D arrangement corresponding to the active region, the second S / D arrangement including: a second silicide sandwich portion of the corresponding active region having a silicide sandwich structure; a second portion of the corresponding MD contact structure located above and electrically coupled to the second silicide sandwich portion; and a second BVD structure located below and electrically coupled to the second silicide sandwich portion; a third S / D arrangement corresponding to the active region, the third S / D arrangement including: a third silicide sandwich portion of the corresponding active region having a silicide sandwich structure; a third portion of the corresponding MD contact structure located above and electrically coupled to the third silicide sandwich portion; and a third BVD structure located below and electrically coupled to the third silicide sandwich portion; a first via to MD (VD) structure located above and electrically coupled to the third portion of the corresponding MD contact structure; and a buried conductive segment located in a buried metallization layer and located below and electrically coupled to each of the second BVD structure and the third BVD structure.

[0210] In an embodiment, the active regions corresponding to the first silicide sandwich portion, the active regions corresponding to the second silicide sandwich portion, and the active regions corresponding to the third silicide sandwich portion are separate first, second, and third active regions; the first portion of the corresponding MD contact structure and the second portion of the corresponding MD contact structure are corresponding portions of the same first MD contact structure; and the third portion of the corresponding MD contact structure is a portion of the second MD contact structure that is separate from the first MD contact structure. In an embodiment, each of the first, second, and third active regions extends in a first direction; and each of the first and second MD contact structures extends in a second direction that is substantially perpendicular to the first direction; and the buried conductive segment extends in the second direction. In an embodiment, the active regions corresponding to the first silicide sandwich portion, the active regions corresponding to the second silicide sandwich portion, and the active regions corresponding to the third silicide sandwich portion are corresponding portions of the same active region; and the first portion of the corresponding MD contact structure, the second portion of the corresponding MD contact structure, and the third portion of the corresponding MD contact structure are portions of separate first, second, and third MD contact structures, respectively. In an embodiment, the semiconductor device further includes: a second VD structure located above and electrically coupled to the first MD contact structure; a third VD structure located above and electrically coupled to the second MD contact structure; a first non-buried conductive segment located in a first metallization layer and above and electrically coupled to each of the second and third VD structures; and a second non-buried conductive segment located in the first metallization layer and above and electrically coupled to the first VD structure. In an embodiment, each of the first, second, and third active regions extends in a first direction; and each of the first and second MD contact structures extends in a second direction that is substantially perpendicular to the first direction; the buried conductive segment extends in the first direction, and each of the first and second non-buried conductive segments extends in the first direction.In an embodiment, the first silicide sandwich portion includes: a first doped portion of the corresponding active region; a first top silicide layer located above and electrically coupled to the first doped portion and electrically coupled to the first portion of the first MD contact structure; and a first bottom silicide layer located below and electrically coupled to the first doped portion and electrically coupled to the first BVD structure; the second silicide sandwich portion includes: a second doped portion of the corresponding active region; a second top silicide layer located above and electrically coupled to the second doped portion and electrically coupled to the second portion of the first MD contact structure; and a second bottom silicide layer located below and electrically coupled to the second doped portion and electrically coupled to the second BVD structure; and the third silicide sandwich portion includes: a third doped portion of the corresponding active region; a third top silicide layer located above and electrically coupled to the third doped portion and electrically coupled to the second MD contact structure; and a third bottom silicide layer located below and electrically coupled to the third doped portion and electrically coupled to the third BVD structure.

[0211] In an embodiment, a method of manufacturing a semiconductor structure includes: forming an active region having a first doped portion; forming a first silicide layer located above and electrically coupled to the first portion of the active region; forming a second silicide layer located below and electrically coupled to the first portion of the active region; forming a first metal-to-drain / source (MD) contact structure located above and electrically coupled to the first silicide layer; forming a first via-to-MD (VD) structure located above and electrically coupled to the MD contact structure; and forming a buried via-to-source / drain (BVD) structure located below and electrically coupled to the second silicide layer. In an embodiment, the step of forming an active region having a first doped portion includes: forming the active region from a first semiconductor material; doping the first semiconductor material in the first portion to become a second semiconductor material different from the first semiconductor material. In an embodiment, the method further includes: configuring the semiconductor structure as a heater; or configuring the semiconductor structure as a temperature sensor.

[0212] In an embodiment, a method of manufacturing a semiconductor device (the corresponding layout is stored on a non-transitory computer-readable medium), the method comprising generating a layout that includes: generating a first source / drain (S / D) arrangement, including: generating a silicide sandwich arrangement and including the arrangement in a set representing a corresponding active region, the silicide sandwich arrangement being designated for a silicide sandwich structure; generating a first metal-to-drain / source (MD) contact shape above the silicide sandwich arrangement; generating a first via-to-MD (VD) shape above the first MD contact shape; generating a first buried via-to-source / drain shape below the silicide sandwich arrangement; generating a channel shape and including it in the set representing the corresponding active region; generating a gate shape on the channel shape; and generating a second S / D arrangement, including: generating a first doping shape and including it in the set representing the corresponding active region, the channel shape being located between the first doping shape and the silicide sandwich arrangement; and generating an upper contact arrangement or a lower contact arrangement; generating the upper contact arrangement, including: generating a first silicide shape above the first doping shape; and generating a second MD contact shape above the first silicide shape; and generating a second VD shape above the second MD contact shape; and generating the lower contact arrangement, including: generating a second silicide shape below the first doping shape; and generating a second BVD shape below the second silicide shape.

[0213] In an embodiment, the method further includes: performing at least one of the following operations based on the layout diagram: (A) performing one or more photolithographic exposures; (B) fabricating one or more semiconductor masks; or (C) fabricating at least one element in a layer of a semiconductor integrated circuit. In an embodiment, wherein generating the silicide sandwich arrangement includes: generating a second doped shape and including it in a set representing the corresponding active region; generating a third silicide shape above the second doped shape and below the first MD contact shape; and generating a fourth silicide shape below the second doped shape and above the first BVD shape. In an embodiment, the first S / D arrangement, the channel shape, the gate shape, and the second S / D arrangement together represent a transistor; the first S / D arrangement also represents a temperature sensor; the silicide sandwich arrangement is a first silicide sandwich arrangement; the first silicide sandwich arrangement and the first doped shape are corresponding components in the same first set representing the same first active region; the first MD contact shape is a first part of a larger MD contact shape; and generating the layout diagram further includes: generating a third S / D arrangement, including: generating a second silicide sandwich arrangement and including it in a second set representing a second active region, the second silicide sandwich arrangement being designated for a silicide sandwich structure, the second set being discrete from the first set; generating a third MD contact shape above the second silicide sandwich arrangement, the third MD contact shape being a second part of the larger MD contact shape; generating a third VD shape above the third MD contact shape; generating a third BVD shape below the second silicide sandwich arrangement; and the third S / D arrangement represents a calibration device relative to the first S / D arrangement.

[0214] In an embodiment, generating the second silicide sandwich arrangement includes: generating a second doped shape of the second S / D arrangement and including it in the second set; generating a third silicide layer above the second doped shape and below the third MD contact shape; and generating a fourth silicide layer above the third doped shape and the third BVD shape; and designating the conduction type of the first active region to be the same as the conduction type of the second active region. In an embodiment, generating the layout further includes: generating a third set of one or more shapes representing a third active region; and arranging the third set between the first and second active sets. In an embodiment, the second S / D arrangement is thermally adjacent to the first S / D arrangement, and the third S / D arrangement is thermally remote from the first S / D arrangement. In an embodiment, generating the layout further includes: generating a buried conductive shape below and overlapping each of the first and third BVD shapes, the buried conductive shape representing a buried conductive segment in a buried metallization layer; and wherein: the first S / D arrangement and the third S / D arrangement represent a voltage divider circuit configured to provide voltage division; the first S / D arrangement represents an electrical coupling to a node represented by the first MD contact shape; in an embodiment, the third S / D arrangement represents an electrical coupling to a node; and a third voltage designated for the node represents the voltage division with respect to a first voltage designated for the first BVD shape of the first S / D arrangement and a second voltage designated for the third BVD shape of the third S / D arrangement. In an embodiment, generating the second S / D arrangement includes generating the upper contact arrangement and generating the lower contact arrangement. In an embodiment, the first S / D arrangement is represented as a heater. In an embodiment, the first S / D arrangement, the channel shape, the gate shape, and the second S / D arrangement together represent a transistor; the first S / D arrangement further represents a temperature sensor; the silicide sandwich arrangement is a first silicide sandwich arrangement; the first silicide sandwich arrangement and the first doped shape are corresponding members of the same first set representing the same first active region; generating the layout further includes: generating a third S / D arrangement, including: generating a second silicide sandwich arrangement and including it in the first set, the second silicide sandwich arrangement being designated for a silicide sandwich structure; generating a third MD contact shape above the second silicide sandwich arrangement; generating a third VD shape above the third MD contact shape; and generating a third BVD shape below the second silicide sandwich arrangement; and the third S / D arrangement represents a calibration device with respect to the first S / D arrangement. In an embodiment, the gate shape is a first gate shape; and generating the layout further includes: generating at least a second gate shape between the second S / D arrangement and the third S / D arrangement.In an embodiment, generating the layout further includes: positioning the second S / D arrangement thermally proximate to the first S / D arrangement; and positioning the third S / D arrangement thermally remote from the first S / D arrangement. In an embodiment, generating the layout further includes: generating, beneath and overlapping each of the first and third BVD shapes, a buried conductive shape representing a buried conductive segment in a buried metallization layer; and wherein: the first S / D arrangement and the third S / D arrangement represent a voltage divider circuit configured to provide a voltage division; the first S / D arrangement represents an electrical coupling to a node represented by the buried conductive segment; the third S / D arrangement represents an electrical coupling to the node; and a third voltage assigned to the node represents the voltage division relative to a first voltage assigned to the first MD shape of the first S / D arrangement and a second voltage assigned to the third MD shape of the third S / D arrangement.

[0215] In an embodiment, a method of manufacturing a semiconductor device, the corresponding layout of which is stored on a non-transitory computer-readable medium, the method includes generating a layout that includes: generating an active area (AA) shape having a first portion designated for doping; generating a first silicide shape over the first portion of the AA shape; generating a second silicide shape beneath the first portion of the AA shape; generating a first metal-to-drain / source (MD) contact shape over the first silicide layer; generating a first via-to-MD (VD) shape over the MD contact shape; and generating a buried via-to-source / drain (BVD) shape beneath the second silicide shape. In an embodiment, generating the AA shape having a doped first portion includes: designating the AA shape to be formed of a first semiconductor material; designating the first portion to be formed of a second semiconductor material different from the first semiconductor material.

[0216] The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present invention as a basis to design or modify other processes and structures for carrying out the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present invention and that various changes, substitutions, and alterations may be made herein without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device, comprising: A first source / drain arrangement, comprising: A silicide sandwich portion having a silicide sandwich structure corresponding to an active region; A first portion located above the silicide sandwich portion corresponding to a metal-to-drain / source contact structure and electrically coupled to the silicide sandwich portion; A first via to a metal-to-drain / source structure, located above the first portion of the corresponding metal-to-drain / source contact structure and electrically coupled to the corresponding metal-to-drain / source contact structure; and A first buried via to a source / drain structure, located below the silicide sandwich portion and electrically coupled to the silicide sandwich portion; A gate structure, located above a channel portion of the corresponding active region and field-coupled to the channel portion of the corresponding active region; and A second source / drain arrangement, comprising: A first doped portion of the corresponding active region, with the channel portion located between the first doped portion and the silicide sandwich portion; and At least one of each of the following: An upper contact arrangement, comprising: A first silicide layer, located above the first doped portion and electrically coupled to the first doped portion; and A second portion corresponding to a metal-to-drain / source contact structure, located above the first silicide layer and electrically coupled to the first silicide layer; and A second via to a metal-to-drain / source structure, located above the second portion of the corresponding metal-to-drain / source contact structure and electrically coupled to the second portion; or A lower contact arrangement, comprising: A second silicide layer, located below the first doped portion and electrically coupled to the first doped portion; and A second buried via to a source / drain structure, located below the second silicide layer and electrically coupled to the second silicide layer.

2. The semiconductor device according to claim 1, wherein The silicide sandwich portion comprises: A second doped portion of the corresponding active region; A third silicide layer, located above the second doped portion and electrically coupled to the second doped portion, and electrically coupled to the first portion of the corresponding metal-to-drain / source contact structure; and A fourth silicide layer, located below the second doped portion and electrically coupled to the second doped portion, and electrically coupled to the first buried via to a source / drain structure.

3. The semiconductor device according to claim 2, wherein: The first doped portion and the second doped portion are a first material, and the first material is an epitaxially grown semiconductor that has been doped; and The channel portion is a second material, and the second material is a semiconductor different from the first material.

4. The semiconductor device according to claim 1, wherein: The first source / drain arrangement, the channel portion, the gate structure, and the second source / drain arrangement together act as a transistor; The first source / drain arrangement is also a temperature sensor; The silicide sandwich portion is a first silicide sandwich portion; The first silicide sandwich portion of the corresponding active region and the first doped portion of the corresponding active region are corresponding portions of the same first active region; The first portion of the corresponding metal-to-drain / source contact structure is a part of a first metal-to-drain / source contact structure; And The semiconductor device further comprises: A third source / drain arrangement, comprising: A second silicide sandwich portion of the second active region, having a silicide sandwich structure, the second active region being discrete from the first active region; A third portion of the first metal-to-drain / source contact structure, located above the second silicide sandwich portion and electrically coupled to the second silicide sandwich portion; A third via-to-metal-to-drain / source structure, located above the third portion of the first metal-to-drain / source contact structure and electrically coupled to the third portion; and A third buried via-to-source / drain structure, located below the second silicide sandwich portion and electrically coupled to the second silicide sandwich portion; and The third source / drain arrangement represents a calibration device related to the first source / drain arrangement.

5. The semiconductor device according to claim 4, wherein: The second silicide sandwich portion comprises: A second doped portion of the second active region; A third silicide layer, located above the second doped portion and electrically coupled to the second doped portion, and electrically coupled to the third portion of the first metal-to-drain / source contact structure; and A sixth silicide layer, located below the second doped portion and electrically coupled to the second doped portion, and electrically coupled to the third buried via-to-source / drain structure; and The conductivity type of the first active region is the same as the conductivity type of the second active region.

6. The semiconductor device according to claim 4, further comprising: At least a third active region, located between the first active region and the second active region.

7. The semiconductor device according to claim 4, further comprising: A buried conductive segment, the buried conductive segment being located in a buried metallization layer and located below each of the first buried via-to-source / drain structure and the third buried via-to-source / drain structure and electrically coupled to each of the first buried via-to-source / drain structure and the third buried via-to-source / drain structure; And An operational amplifier; And Wherein: The first source / drain arrangement and the third source / drain arrangement form a voltage divider circuit configured to provide a voltage division; The first source / drain arrangement is electrically coupled to a node represented by the first metal-to-drain / source contact structure; The third source / drain arrangement is electrically coupled to the node; With respect to a first voltage on the first buried via-to-source / drain structure of the first source / drain arrangement and a second voltage on the third buried via-to-source / drain structure of the third source / drain arrangement, a third voltage on the node represents the voltage division; and A first input of the operational amplifier is configured to receive the voltage division.

8. The semiconductor device according to claim 1, wherein: The second source / drain arrangement comprises the upper contact arrangement and the lower contact arrangement.

9. The semiconductor device according to claim 1, wherein: The first source / drain arrangement is a heater.

10. The semiconductor device according to claim 1, wherein: The first source / drain arrangement, the channel portion, the gate structure, and the second source / drain arrangement together form a transistor; The first source / drain arrangement is also a temperature sensor; The silicide sandwich portion is the first silicide sandwich portion; The first silicide sandwich portion of the corresponding active region and the first doped portion of the corresponding active region are corresponding portions of the same first active region; The semiconductor device further includes: A third source / drain arrangement, including: A second silicide sandwich portion of the first active region having the silicide sandwich structure; A third metal-to-drain / source contact structure located above the second silicide sandwich portion and electrically coupled to the second silicide sandwich portion; A third via-to-metal-to-drain / source structure located above the third metal-to-drain / source contact structure and electrically coupled to the third metal-to-drain / source contact structure; and A third buried via-to-source / drain structure located below the second silicide sandwich portion and electrically coupled to the second silicide sandwich portion; and The third source / drain arrangement represents a calibration device related to the first source / drain arrangement.

11. The semiconductor device according to claim 10, further including: A buried conductive segment located in a buried metallization layer and below each of the first buried via-to-source / drain structure and the third buried via-to-source / drain structure and electrically coupled to each of the first buried via-to-source / drain structure and the third buried via-to-source / drain structure; And An operational amplifier; And Wherein: The first source / drain arrangement and the third source / drain arrangement form a voltage divider circuit configured to provide a voltage division; The first source / drain arrangement is electrically coupled to a node represented by the buried conductive segment; The third source / drain arrangement is electrically coupled to the node; The first portion of the corresponding metal-to-drain / source contact structure is a part of the first metal-to-drain / source contact structure; Relative to a first voltage on the first metal-to-drain / source contact structure of the first source / drain arrangement and a second voltage on a third portion of the first metal-to-drain / source contact structure of the third source / drain arrangement, a third voltage on the node represents the voltage division, and the third portion of the first metal-to-drain / source contact structure of the third source / drain arrangement is located above the second silicide sandwich portion and electrically coupled to the second silicide sandwich portion; and A first input of the operational amplifier is configured to receive the voltage division.

12. A semiconductor device, including: A first source / drain arrangement in a corresponding active region, the first source / drain arrangement including: A first silicide sandwich portion of the corresponding active region having a silicide sandwich structure; A first portion of a corresponding metal-to-drain / source contact structure located above the silicide sandwich portion and electrically coupled to the silicide sandwich portion; and A first buried via to source / drain structure, located below the silicide sandwich portion and electrically coupled to the silicide sandwich portion; A second source / drain arrangement in the corresponding active region, the second source / drain arrangement comprising: A second silicide sandwich portion of the corresponding active region, having a silicide sandwich structure; A second portion of the corresponding metal to drain / source contact structure, located above the second silicide sandwich portion and electrically coupled to the second silicide sandwich portion; and A second buried via to source / drain structure, located below the second silicide sandwich portion and electrically coupled to the second silicide sandwich portion; A third source / drain arrangement in the corresponding active region, the third source / drain arrangement comprising: A third silicide sandwich portion of the corresponding active region, having a silicide sandwich structure; A third portion of the corresponding metal to drain / source contact structure, located above the third silicide sandwich portion and electrically coupled to the third silicide sandwich portion; and A third buried via to source / drain structure, located below the third silicide sandwich portion and electrically coupled to the third silicide sandwich portion; A first via to metal to drain / source structure, located above the third portion of the corresponding metal to drain / source contact structure and electrically coupled to the third portion of the corresponding metal to drain / source contact structure; and A buried conductive segment, which is located in a buried metallization layer, and is located below each of the second buried via to source / drain structure and the third buried via to source / drain structure and is electrically coupled to each of the second buried via to source / drain structure and the third buried via to source / drain structure.

13. The semiconductor device according to claim 12, wherein: The active region corresponding to the first silicide sandwich portion, the active region corresponding to the second silicide sandwich portion, and the active region corresponding to the third silicide sandwich portion are discrete first, second, and third active regions; The first portion of the corresponding metal to drain / source contact structure and the second portion of the corresponding metal to drain / source contact structure are corresponding portions of the same first metal to drain / source contact structure; And The third portion of the corresponding metal to drain / source contact structure is a portion of a second metal to drain / source contact structure that is discrete from the first metal to drain / source contact structure.

14. The semiconductor device according to claim 13, wherein: Each of the first active region, the second active region, and the third active region extends in a first direction; And Each of the first metal to drain / source contact structure and the second metal to drain / source contact structure extends in a second direction, the second direction being perpendicular to the first direction; and The buried conductive segment extends in the second direction.

15. The semiconductor device according to claim 12, wherein: The active region corresponding to the first silicide sandwich portion, the active region corresponding to the second silicide sandwich portion, and the active region corresponding to the third silicide sandwich portion are corresponding portions of the same active region; and the first portion of the corresponding metal-to-drain / source contact structure, the second portion of the corresponding metal-to-drain / source contact structure, and the third portion of the corresponding metal-to-drain / source contact structure are correspondingly portions of a discrete first metal-to-drain / source contact structure, a second metal-to-drain / source contact structure, and a third metal-to-drain / source contact structure.

16. The semiconductor device according to claim 15, further comprising: a second via-to-metal-to-drain / source structure located above the first metal-to-drain / source contact structure and electrically coupled to the first metal-to-drain / source contact structure; a third via-to-metal-to-drain / source structure located above the second metal-to-drain / source contact structure and electrically coupled to the second metal-to-drain / source contact structure; a first non-buried conductive segment located in a first metallization layer and above each of the second via-to-metal-to-drain / source structure and the third via-to-metal-to-drain / source structure and electrically coupled to each of the second via-to-metal-to-drain / source structure and the third via-to-metal-to-drain / source structure; and a second non-buried conductive segment located in the first metallization layer and above the first via-to-metal-to-drain / source structure and electrically coupled to the first via-to-metal-to-drain / source structure.

17. The semiconductor device according to claim 12, wherein: the first silicide sandwich portion includes: a first doped portion of the corresponding active region; a first top silicide layer located above the first doped portion and electrically coupled to the first doped portion and electrically coupled to the first portion of the corresponding metal-to-drain / source contact structure; and a first bottom silicide layer located below the first doped portion and electrically coupled to the first doped portion and electrically coupled to the first buried via-to-source / drain structure; the second silicide sandwich portion includes: a second doped portion of the corresponding active region; a second top silicide layer located above the second doped portion and electrically coupled to the second doped portion and electrically coupled to the second portion of the corresponding metal-to-drain / source contact structure; and a second bottom silicide layer located below the first doped portion and electrically coupled to the first doped portion and electrically coupled to the second buried via-to-source / drain structure; and the third silicide sandwich portion includes: a third doped portion of the corresponding active region; a third top silicide layer located above the third doped portion and electrically coupled to the third doped portion and electrically coupled to the third portion of the corresponding metal-to-drain / source contact structure; and a third bottom silicide layer located below the third doped portion and electrically coupled to the third doped portion and electrically coupled to the third buried via-to-source / drain structure.

18. A method of fabricating a semiconductor structure, comprising: forming an active region having a doped first portion; forming a first silicide layer over and electrically coupled to the first portion of the active region; forming a second silicide layer under and electrically coupled to the first portion of the active region; forming a first metal-to-drain / source contact structure over and electrically coupled to the first silicide layer; forming a first via-to-metal-to-drain / source (VD) structure over and electrically coupled to the first metal-to-drain / source contact structure; and forming a buried via-to-source / drain structure under and electrically coupled to the second silicide layer.

19. The method according to claim 18, wherein The step of forming an active region having a doped first portion comprises: forming the active region from a first semiconductor material; doping the first semiconductor material in the first portion to be a second semiconductor material different from the first semiconductor material.

20. The method according to claim 18, further comprising: configuring the semiconductor structure as a heater; or configuring the semiconductor structure as a temperature sensor.

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