Master-slave D flip-flop and integrated circuit including master-slave D flip-flop

Abstract

A master-slave D flip-flop and an integrated circuit comprising the master-slave D flip-flop are disclosed. The master-slave D flip-flop comprises a master circuit configured to receive an input signal and to generate two first intermediate signals from the input signal, a transmission circuit connected to the master circuit and comprising at least two logic gates and a clock connection for applying a clock signal to one input of each gate, wherein the gates are configured to provide two second intermediate signals from the first intermediate signals and the clock signal, and a slave circuit connected to the transmission circuit to form at least one output signal of the flip-flop from the second intermediate signals. The slave circuit is configured to maintain the at least one output signal given by a preceding pair of states in case the second intermediate signals have a predetermined pair of states following the preceding pair of states, and the transmission circuit has a control input and is configured to generate the second intermediate signals with the predetermined pair of states in response to a predetermined control signal state at the control input.

Description

Technical Field

[0001] This disclosure pertains to master-slave D triggers. Background Technology

[0002] Flip-flop-based registers are used in various circuits to store state. To reduce current consumption in such circuits, the circuits may include a data processing mode in which they perform their intended function. Furthermore, such devices or circuits may include so-called data retention modes or sleep / standby modes, in which data processing is interrupted. In data retention mode, only low quiescent leakage current should generally be allowed. Additionally, it is desirable to ensure that the device (e.g., IC (integrated circuit)) can immediately resume data processing after changing from data retention mode to data processing mode. Moreover, for flip-flops used in such devices, the state stored in the flip-flops should be preserved even in data retention mode.

[0003] Such functionality can be achieved using additional circuitry, for example, to store the flip-flop's data during data retention mode. However, it is desirable to provide such functionality with the smallest possible additional cost (e.g., in terms of additional circuitry and chip area). Summary of the Invention

[0004] According to an embodiment, a master-slave D flip-flop is provided, comprising: a master circuit configured to receive an input signal and generate two first intermediate signals based on the input signal; a transmission circuit connected to the master circuit and including at least two logic gates and a clock connection for applying a clock signal to an input of each of the plurality of gates, wherein the plurality of gates are configured to provide two second intermediate signals based on the first intermediate signals and the clock signal; and a slave circuit connected to the transmission circuit to form at least one output signal of the flip-flop from the second intermediate signals. The slave circuit is configured to maintain at least one output signal given by a previous state pair if the second intermediate signal has a predetermined state pair following a previous state pair, and the transmission circuit has a control input and is configured to generate a second intermediate signal having a predetermined state pair in response to a predetermined control signal state at the control input. Attached Figure Description

[0005] In the accompanying drawings, similar reference numerals generally refer to the same parts throughout the different views. The drawings are not necessarily drawn to scale, but generally focus on illustrating the principles of the invention. In the following description, various aspects will be described with reference to the following drawings, in which:

[0006] Figure 1 A data processing device including circuitry with multiple registers is shown.

[0007] Figure 2 The master-slave D flip-flop is shown.

[0008] Figure 3 A master-slave D trigger according to an implementation is shown.

[0009] Figure 4 A timing diagram illustrating how the relevant signal changes over time is shown.

[0010] Figure 5 A master-slave D trigger according to an implementation is shown. Detailed Implementation

[0011] The following detailed description is taken with reference to the accompanying drawings, which illustrate, by way of explanation, specific details and aspects of this disclosure in which the invention may be practiced. Other aspects may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the invention. The various aspects of this disclosure are not necessarily mutually exclusive, as some aspects of this disclosure may be combined with one or more other aspects of this disclosure to form new aspects.

[0012] Figure 1 A data processing device 100 is shown, which includes an integrated circuit 101 having multiple registers 102.

[0013] Circuit 101 (i.e., integrated circuit) may include, for example, register 102, as a register for a data processing element (e.g., a microprocessor or any kind of microcontroller), as a control or configuration register of any kind, a register for storing the state of the data processing device 100 (state machine), etc. Therefore, circuit 101 may also include logic for implementing circuit 105, such as sequential circuits and combinational circuits.

[0014] The data processing device 100 includes a working mode controller 106, which can switch a portion of the data processing device 100 (e.g., circuitry 101) between a data processing mode (normal mode) and a data retention mode or a sleep or standby mode. In the data retention mode or sleep or standby mode, data processing by the data processing device 100 is interrupted to save power. For this purpose, the working mode controller 106 has a signaling connection 103 to register 102 and logic circuitry 105 (and possible other components of circuitry 101 and / or device 100). The working mode controller 106 can use this signaling connection 103 to transmit (working mode) control signals to set the working mode of register 102 and logic circuitry 105.

[0015] In many applications, it is expected that the data processing device can immediately resume data processing after changing from data retention mode to data processing mode, and it is expected that registers will retain the data stored therein during the data retention mode.

[0016] Therefore, each register 102 is formed by a plurality of flip-flops 104, and each flip-flop 104 is configured to maintain its state (i.e., the logical state stored in the flip-flop) during the data retention mode, meaning that the state should not be lost during the data retention mode.

[0017] Register 102 is formed, for example, by a flip-flop 104 having an isolated input interface (e.g., an isolated data input, clock input, and reset input) and a clock edge controlled for data retention in a data retention mode, sleep mode, or standby mode, or by means of said mode, the normal mode (data processing mode) can be interrupted, so that in the data retention mode, integrated circuit 101 absorbs only a very low static leakage current.

[0018] As mentioned above, it may also be necessary for integrated circuit 101 to be able to immediately resume data processing after transitioning from data holding mode to data processing mode. It is also desirable that such a register 102 with an isolable input interface can be seamlessly integrated into the existing design process and implementation of the IC, or with minimal effort. This is particularly relevant to the timing characteristics of the interface signals of the relevant registers to be observed during the transition between data processing mode and data holding mode.

[0019] To meet the requirements of the data retention mode, it is generally desirable to first separate as much of the sequential and combinational circuitry 105 (i.e., combinational and sequential logic) integrated on IC 101 as possible from the power supply voltage (from the high (positive) power supply potential VDD or from the low power supply potential (ground) VSS) in a high-impedance switchable manner. However, since at least a portion of the information stored in registers 102 should remain in registers 102 (i.e., retained in these registers), a certain number of these registers 102 must remain connected to the power supply voltage in data retention mode. In data retention mode, these registers 102 are electrically isolated from those parts of IC 101 that are disconnected from the power supply voltage, otherwise unwanted and uncontrollable cross currents would flow through the input interfaces of these registers 102.

[0020] Another expected condition is that, for the transition between data processing mode and data retention mode, the register clock signal should have a Boolean (logic) value of 0 immediately before changing to data retention mode and immediately after reverting to data processing mode, or the register clock signal should be physically connected to a lower power supply potential VSS.

[0021] One approach to address the aforementioned requirements is to save the information stored in registers 102 before changing from data processing mode to data retention mode by transferring the data contents of all these registers 102 to other memory circuitry (e.g., SRAM (Static Random Access Memory) integrated on the IC) that can be assumed to remain connected to the power supply voltage. When data processing mode is restored, these data contents are then transferred back to their respective circuit registers. However, this approach requires additional circuitry and significantly increases time and complexity.

[0022] Another approach is to provide a specially constructed "data retention trigger" that includes an additional "low-leakage latch (LLL)" for each memory bit; the information stored in the trigger is transferred to this specially constructed "data retention trigger" before entering data retention mode; and the trigger receives the information back from the specially constructed "data retention trigger" before re-entering data processing mode. In this way, even in data retention mode, the trigger can be disconnected from the power supply voltage, and only the LLL connected to the power supply voltage can be left, thus ensuring that the LLL has only a very small leakage current. This is possible because the LLL associated only with data retention mode does not need to meet any speed requirements. However, this approach leads to a significant increase in area, and therefore a significant increase in the cost of implementing the LLL.

[0023] According to various embodiments, a master-slave D flip-flop is provided that enables the above requirements to be met in an efficient manner. The master-slave D flip-flop described below can be used as a flip-flop 104 for forming register 102.

[0024] As a starting point, refer to Figure 2 Describe a master-slave D flip-flop controlled by clock edge (e.g., for implementation in CMOS (Complementary Metal-Oxide-Semiconductor)).

[0025] Figure 2 The master-slave D trigger 200 is displayed.

[0026] The AND-OR-NOT gate ANRDN 201 at the data input is used as an inverting multiplexer for the data input D and the test input TI, with a test enable signal TE, such that in the (SCAN) test mode, i.e., for TE=1, the test input TI is forwarded to the internal node DN of the flip-flop 200, and in the data processing mode, i.e., for TE=0, the data input D is forwarded to the internal node DN of the flip-flop 200. The case of TE=1 will not be considered further in the following text, as data retention mode or sleep mode is generally not involved in the scan test mode.

[0027] First, consider the case R = 0, i.e., the reset function is not activated (the case R = 1, i.e., the activated reset function will be considered further below). Furthermore, as explained above, TE = 0, i.e., DN = NOT(D).

[0028] The clock input CK is initially at a low supply potential VSS, which is logically 0. When CK = 0, RQ = SQ = 1, that is, the set-reset (SR) flip-flop formed by two NAND gates NDQN 202 and NDS 203, i.e., the so-called slave latch of flip-flop 200 (whose output is inverted by the output inverter 209 to form the output of the flip-flop), retains the value previously written on the rising edge of CK (symbolically Q = Q(t-1)) or the value set in the case of a valid reset (RESET) R = 1, QN = 1, S = 0 (since SQ = 1) and Q = 0.

[0029] Since the feedback RQ = SQ = 1, the two NAND gates NDDM 205 and NDMN 204 are used as inverters for nodes DN and DM. That is, the data inputs D and DN are passed to the inside of flip-flop 200 via NDDM 205 and NDMN 204, such that the inputs MN and M of gates ANRRQ 206 and NDSQ 207 have the values ​​MN = NOT(D) and M = D. When CK = 0, input D and its inverted NOT(D) are thus placed before the set and reset inputs of the slave latch. With the next rising edge of CK, these are then shifted into the slave latch.

[0030] In the subsequent state CK=1, if D=0 was previously written, then RQ=0 (and SQ=1) is assumed, causing the latch formed by NDMN 204 and ANRRQ 206 to hold this value, since NDMN 204 provides the value 1 for MN due to RQ=0. However, if D=1 was previously written, then SQ=0 (and RQ=1) is assumed when CK=1, causing the latch formed by NDDM 205, NDMN 204, inverter IVM 208, and NDSQ 207 to hold this value, since NDDM 205 provides the value 1 for DM due to SQ=0, and NDMN 204 acts as the inverter for DM due to RQ=1. Therefore, as long as CK=1, the states of internal nodes DM, MN, M, SQ, RQ, S, and QN, as well as the state of Q, are maintained, and data input DN has no effect on these nodes.

[0031] Furthermore, it is assumed that the clock stops before entering standby or data retention mode. This means that in a typical IC implementation, the clock input CK of all affected registers remains 0, and may only show a rising edge or the value CK=1 again after resuming data processing mode. This means that before entering data retention mode, the slave latch formed by NDS 203 and NDQN 202 is isolated from the master latch because CK=0 and therefore RQ=SQ=1, and retains the data previously used when CK=1, while ANRDN 201 and (because RQ=SQ=1) NDDM 205, NDMN 204, IVM 208, NDSQ 207, and ANRRQ 206 react to possible changes in data input D. Therefore, if the (combinatorial) logic gates providing data input D are disconnected from the power supply voltage as expected in data retention mode, all these data inputs D will exhibit undefined values ​​for at least a longer period of time, which will cause cross currents in gates ANRDN201, NDDM 205, NDMN 204, IVM 208, NDSQ 207, and ANRRQ 206.

[0032] According to various embodiments, this problem is also solved by isolating gates ANRDN 201, NDDM 205, NDMN 204, and IVM 208 from the power supply voltage and introducing additional control signal ISN and additional transistor functions for the input signals CK, R, MN, and M of isolation gates ANRRQ 206 and NDSQ 207. See below for further details. Figure 3 This will be described.

[0033] Figure 3 A master-slave D trigger 300 according to an embodiment is shown.

[0034] Similar to Figure 2 The master-slave D flip-flop 200 and master-slave D flip-flop 300 include gates ANRDN 301, NDQN 302, NDS 303, NDMN 304, NDDM 305, AONDRQ 306 (corresponding to ANRRQ 206), NDSQ 307, IVM 308 and IVQ 309.

[0035] The only difference between the master-slave D flip-flop 300 and the master-slave D flip-flop 200 is related to the gates NDSQ207 and ANRRQ206: the NAND2 gate (i.e., a NAND gate with two inputs) NDSQ207 is extended to a NAND3 gate NDSQ307 (i.e., a NAND gate with three inputs) with an additional input for the control signal ISN, and the ANDNOR gate ANRRQ206 is extended to an ANDORNAND gate AONDRQ306 with an additional NAND input for the control signal ISN.

[0036] When ISN = 0, it is assumed that the outputs SQ and RQ of gates NDSQ 307 and AONDRQ 306 are set to 1, regardless of the values ​​of MN, M, CK, and R. With ISN = 0, nodes SQ and RQ are isolated from the perspective that the values ​​of MN, M, CK, and R have no effect on the current through gates NDSQ 307 and AONDRQ 306 of flip-flop 300.

[0037] This means (as mentioned above) Figure 2 (As described in the context) For R = CK = 0, in the case of RQ = SQ = 1, it is known that the SR flip-flop formed by the two NAND gates NDQN 302 and NDS 303, namely the so-called slave latch of the register, holds the value previously written by CK with a rising edge (symbolically: Q = Q(t-1)) or the value set by the valid reset signal R = 1, QN = 1, S = 0 (since SQ = 1) and Q = 0.

[0038] Therefore, for data retention, gates NDSQ 307 and AONDRQ 306 need to remain connected to the higher supply voltage VDD, while the lower supply voltage VSS can be disconnected. Gates NDS303 and NDQN 302 need to remain connected to both supply voltages VDD and VSS to retain data in the latch. On the other hand, output inverter IVQ 309 can be disconnected from VSS and / or VDD, as well as AONDRN 301, NDDM 305, NDMN 304, and IVM 308.

[0039] This means that when the value of ISN is 0 (which remains stable throughout the data retention mode), both the clock tree that generates the clock signal CK and the (combinatorial) logic gates that provide data inputs D, TI, and TE can be disconnected from the power supply voltage as expected, in order to minimize leakage current in the data retention mode without losing the information stored in the slave latch of flip-flop 300.

[0040] Figure 4A timing diagram 400 illustrating the behavior of the relevant signals over time is shown. First, at the system level (e.g., at the level of device 100 or circuit 101), (e.g., via the operating mode controller 106) it is ensured that all triggers 104 (assuming they have...) are activated before entering data retention mode. Figure 3 The clock input CK (in the form of) is stopped at zero (which can be considered an invalid level). Furthermore, (e.g., via the operating mode controller 106) it is ensured that R is invalid before entering data hold mode (i.e., in the form of) Figure 3 The implementation example shown is equal to 0).

[0041] Therefore, as long as the latch remains "online" on one hand and the internal values ​​RQ and SQ retain their values ​​on the other, each of the involved flip-flops 104 can be isolated from its input interface without losing the information stored in the flip-flop. The retention of the internal values ​​RQ and SQ is achieved by a working mode controller 106, which activates the ISN signal at the system level, utilizing the falling edge of ISN (and maintaining a stable value of 0 throughout the data retention mode). Therefore, RQ = SQ = 1, which ensures that the latch cannot change to a reset state and ensures that the latch retains the stored data.

[0042] Following the falling edge of ISN, all parts of IC 101 not needed in data retention mode are disconnected from the power supply. The operating mode controller 106 performs this operation at the system level by deactivating the signal PW (i.e., utilizing the falling edge of PW and maintaining a stable value of 0 throughout data retention mode). This means that all input signals to the registers (except ISN) can take undefined values ​​(indicated by the crosshairs in timing diagram 400) without causing a malfunction in IC 101.

[0043] To re-enter data processing mode, the operating mode controller 106 first activates the power supply (PW) at the system level, i.e., by triggering the rising edge of the PW. This means that all circuitry previously disconnected from the power supply voltage is now back online. As a result, after re-entering data processing mode, the values ​​at the data inputs D, TI, and TE of all flip-flops 104 are again those values ​​that existed at the data inputs before (i.e., just before leaving data processing mode). This is because the value at data input D is generated by a Boolean combination of the register output values ​​Q. However, all Qs still have their old values ​​(because it is assumed that all relevant registers are not disconnected from the power supply). After reaching a stable value D, the "isolation" of flip-flops 104 can then be canceled using the rising edge of ISN, since the register inputs CK and R have now recovered their values ​​that they had before leaving data processing mode (both returning to 0). Therefore, all registers are ready to operate again, and the entire IC is ready to operate again through all registers.

[0044] Therefore, the master-slave D flip-flop 300 effectively allows the external clock and reset tree to be completely disabled in data retention mode. Since these driver stages (which consist primarily of fast inverters) absorb a particularly large amount of leakage current, turning them off achieves a significant reduction in leakage current. In contrast, the (few) drivers in the ISN (and PW) stages do not need to be very strong, resulting in low leakage current.

[0045] Figure 3 An example is a flip-flop with scan and reset functions. It should be noted that the implementation is not limited to this, and the principle of isolating input signals can also be applied to flip-flops with set inputs, no reset inputs, and no scan functions.

[0046] In summary, according to various implementation methods, such as Figure 5 As shown, a master-slave D flip-flop is provided.

[0047] Figure 5 A master-slave D flip-flop 500 according to an embodiment is shown.

[0048] The master-slave D flip-flop 500 includes a master circuit 501 (e.g., a master latch), which is configured to receive an input signal 502 and generate two first intermediate signals 503 and 504 based on the input signal 502.

[0049] The master-slave D flip-flop 500 also includes a transmission circuit 505 connected to the master circuit 501 and including at least two logic gates 506, 507 and a clock connection 508 for applying a clock signal 509 to one input of each of the gates 506, 507, wherein the gates 506, 507 are configured to provide two second intermediate signals 510, 511 based on the first intermediate signals 503, 504 and the clock signal 509.

[0050] In addition, the master-slave D flip-flop 500 includes a slave circuit (e.g., a slave latch) 512, which is connected to the transmission circuit 505 to form at least one output signal 513 of the flip-flop 500 from the second intermediate signals 510, 511.

[0051] The circuit 512 is configured to maintain at least one output signal 513 given by the previous state pair (i.e. formed by the previous state pair) when the second intermediate signals 510, 511 have a predetermined state pair following the previous state pair.

[0052] The transmission circuit 505 has a control input 514 and is configured to generate a second intermediate signal 510, 511 having a predetermined state pair in response to a predetermined control signal state (of control signal 515) at the control input 514.

[0053] According to various embodiments, in other words, the master-slave flip-flop is provided with a control input that, when active, switches the input of the slave latch to a state that maintains the slave latch in its current state (i.e., the state given by the previous state pair of the slave latch's previous input, i.e., the predetermined state pair of the second intermediate signal). For the case where the slave latch is an RS flip-flop, this input of the RS flip-flop can be used to disable both its set and reset inputs. Figure 3 In the example, this corresponds to both RQ and SQ being equal to 1, which is the case where ISN = 0.

[0054] The main circuit, transmission circuit, and slave circuit are each formed by one or more gates, such as NAND gates, NOR gates, composite gates (as in the example above, ANDORNAND), and inverters.

[0055] For example, the slave circuit 512 is formed by NDQN 302 and NDS 303, the master circuit is formed by NDMN 304, NDDM 305 and IVM 308, and the transmission circuit is formed by AONDRQ 306 and NDSQ 307. Therefore, in Figure 3 In the example, the first intermediate signals are M and MN, and the second intermediate signals are RQ and SQ. The control signal corresponds to ISN, and the predetermined control signal state corresponds to ISN = 0.

[0056] D flip-flops are also known as "data" or "delay" flip-flops. A D flip-flop captures the value of its D input at a defined portion of the clock cycle (e.g., the rising edge of the clock). This captured value becomes the Q output. A D flip-flop can be viewed as a memory cell, a zero-order hold, or a delay line.

[0057] The following describes various examples:

[0058] Example 1 is a reference Figure 5 The master-slave D trigger is described.

[0059] Example 2 is a master-slave D flip-flop based on Example 1, wherein the second intermediate signal is fed back to the input of the master circuit.

[0060] Example 3 is a master-slave D flip-flop according to Example 1 or 2, wherein another input of the first gate of the transmission circuit is connected to the master circuit to directly receive a first intermediate signal from the first intermediate signal provided by the master circuit, and another input of the second gate of the transmission circuit is connected to the master circuit to receive the complement of the first intermediate signal.

[0061] Example 4 is a master-slave D flip-flop according to any one of Examples 1 to 3, wherein none of the gates of the transmission circuit have an output that is connected to the input of any other gate in the transmission circuit.

[0062] Example 5 is a master-slave D flip-flop according to any one of Examples 1 to 4, wherein the transmission circuit is connected to the master circuit such that a second intermediate signal is fed to the master circuit, and the master circuit is configured to generate a first intermediate signal based on the second intermediate signal.

[0063] Example 6 is a master-slave D flip-flop according to any one of Examples 1 to 5, wherein the slave circuit is formed by an SR latch.

[0064] Example 7 is a master-slave D flip-flop according to any one of Examples 1 to 6, wherein the slave circuit is formed by a cross-coupled NAND gate SR latch or a cross-coupled NOR gate SR latch.

[0065] Example 8 is a master-slave D flip-flop based on Example 6 or 7, wherein two second intermediate signals are provided to the R input and S input of the slave latch, respectively.

[0066] Example 9 is a master-slave D flip-flop according to any one of Examples 6 to 8, wherein the predetermined state pair is set to invalid for both the set input and reset input of the slave latch.

[0067] Example 10 is a master-slave D flip-flop according to any one of Examples 1 to 9, wherein each gate of the transmission circuit is configured to generate a corresponding second intermediate signal in the second intermediate signal by combining the state at the control input with the state at one or more other inputs of the gate.

[0068] Example 11 is a master-slave D flip-flop according to any one of Examples 1 to 10, wherein the predetermined control signal state is the active state of the data retention mode.

[0069] Example 12 is a master-slave D flip-flop according to any one of Examples 1 to 11, wherein the first intermediate signal is a complementary signal pair and the second intermediate signal is a complementary signal pair.

[0070] Example 13 is an integrated circuit that includes multiple registers, each register including multiple flip-flops according to any one of Examples 1 to 12.

[0071] Example 14 is an integrated circuit of Example 13, including a working mode controller configured to set the control input of a trigger to a predetermined control signal state to enter a data retention mode.

[0072] Example 15 is an integrated circuit of Example 13 or 14, wherein each flip-flop includes a reset input and / or a set input providing a reset signal and / or a set signal, and a clock input providing a clock signal, and an operating mode controller is configured to set the control input of the flip-flop to a predetermined control signal state to enter a data retention mode after the reset signal and / or set signal and the clock signal have been set to an invalid level.

[0073] While specific embodiments have been illustrated and described herein, those skilled in the art will understand that various alternative and / or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the invention. This application is intended to cover any changes or variations to the specific embodiments discussed herein. Therefore, the invention is intended to be limited only by its claims and their equivalents.

[0074] Figure Labels

[0075] 100 Data Processing Equipment

[0076] 101 Integrated Circuits

[0077] Register 102

[0078] 103 Signaling Connection

[0079] 104 triggers

[0080] 105 Logic Circuit System

[0081] 106 Operating Mode Controller

[0082] 201 ANRDN gate

[0083] 202 NDQN Gate

[0084] 203 NDS Gate

[0085] 204 NDMN gate

[0086] 205 NDDM Gate

[0087] 206 ANRRQ Gate

[0088] 207 NDSQ Gate

[0089] 208 IVM Gate

[0090] 209 IVQ Gate

[0091] 301 ANRDN gate

[0092] 302 NDQN Gate

[0093] 303 NDS Gate

[0094] 304 NDMN gate

[0095] 305 NDDM Gate

[0096] 306 AONDRQ Gate

[0097] 307 NDSQ Gate

[0098] 308 IVM Gate

[0099] 309 IVQ Gate

[0100] 400 timing diagram

[0101] 500 Master-Slave D Flip-Flop

[0102] 501 Main Circuit

[0103] 502 Input Signal

[0104] 503, 504 First intermediate signal

[0105] 505 Transmission Circuit

[0106] 506 and 507 logic gates

[0107] 508 Clock Connection

[0108] 509 Clock Signal

[0109] 510, 511 Second intermediate signal

[0110] 512 from the circuit

[0111] 513 Output Signal

[0112] 514 Control Input

[0113] 515 Control Signal

Claims

1. A master-slave D flip-flop, comprising: The main circuit is configured to receive an input signal and generate two first intermediate signals based on the input signal. A transmission circuit, connected to the main circuit, includes at least two logic gates and a clock connection for applying a clock signal to an input of each of the at least two logic gates, wherein the at least two logic gates are configured to provide two second intermediate signals based on the first intermediate signal and the clock signal. The circuit, connected to the transmission circuit, forms at least one output signal of the master-slave D flip-flop from the second intermediate signal. The slave circuit is configured to maintain at least one output signal given by the previous state pair when the second intermediate signal has a predetermined state pair following the previous state pair. The transmission circuit has a control input and is configured to generate a second intermediate signal having the predetermined state pair in response to a predetermined control signal state at the control input.

2. The master-slave D flip-flop according to claim 1, wherein, The second intermediate signal is fed back to the input of the main circuit.

3. The master-slave D flip-flop according to claim 1, wherein, Another input of the first logic gate of the at least two logic gates is connected to the main circuit to directly receive a first intermediate signal from the first intermediate signal provided by the main circuit, and another input of the second logic gate of the at least two logic gates is connected to the main circuit to receive a complementary signal to the first intermediate signal.

4. The master-slave D flip-flop according to any one of claims 1 to 3, wherein, Each of the at least two logic gates has no output connected to the input of the other of the at least two logic gates.

5. The master-slave D flip-flop according to any one of claims 1 to 3, wherein, The transmission circuit is connected to the main circuit such that the second intermediate signal is fed to the input of the main circuit, and the main circuit is configured to generate the first intermediate signal based on the second intermediate signal.

6. The master-slave D flip-flop according to claim 1, wherein, The slave circuit is formed by an SR latch.

7. The master-slave D flip-flop according to claim 1, wherein, The slave circuit is formed by a cross-coupled NAND gate SR latch or a cross-coupled NOR gate SR latch.

8. The master-slave D flip-flop according to claim 6 or 7, wherein, The two second intermediate signals are respectively provided to the R input and S input of the SR latch.

9. The master-slave D flip-flop according to claim 6 or 7, wherein, The predetermined state is that both the set input and the reset input of the SR latch are set to invalid.

10. The master-slave D flip-flop according to any one of claims 1 to 3, wherein, Each of the at least two logic gates is configured to generate a corresponding second intermediate signal from the two second intermediate signals by performing an AND operation on the state at the control input and the state at one or more other inputs of the logic gate.

11. The master-slave D flip-flop according to any one of claims 1 to 3, wherein, The predetermined control signal state is the active state of the data retention mode.

12. The master-slave D flip-flop according to any one of claims 1 to 3, wherein, The first intermediate signal is a complementary signal pair, and the second intermediate signal is a complementary signal pair.

13. An integrated circuit comprising a plurality of registers, each register comprising a plurality of master-slave D flip-flops according to any one of claims 1 to 12.

14. The integrated circuit of claim 13, further comprising a mode controller configured to set the control input of the master-slave D flip-flop to the predetermined control signal state to enter a data retention mode.

15. The integrated circuit according to claim 14, wherein, Each master-slave D flip-flop includes at least one of a reset input providing a reset signal and a set input providing a set signal; and a clock input providing a clock signal, wherein the operating mode controller is configured to set the control input of the master-slave D flip-flop to the predetermined control signal state to enter the data retention mode after at least one of the reset signal and the set signal and the clock signal have been set to an invalid level.

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