System and method for interleaved Hamming encoding and decoding

Abstract

The present invention relates to systems and methods for interleaved Hamming encoding and decoding. More specifically, embodiments of the present invention provide a communication device for aligning a data stream with a RS symbol. An interleaver interleaves the RS symbols to generate an interleaved RS symbol data stream. A Hamming parity block is generated for a corresponding RS symbol group and inserted into the interleaved RS symbol data stream. Other embodiments also exist.

Description

Technical Field

[0001] The present invention relates to a data communication system and technology thereof. Background Art

[0002] The rate of data communication can be increased in a variety of ways, such as via error correction. For example, Reed-Solomon codes have been used in conventional communication systems. Unfortunately, the prior art is inadequate, and improved systems and methods are desired. Summary of the invention

[0003] The present invention relates to data communication and coding techniques. More specifically, an embodiment of the present invention provides a communication device for aligning a data stream with a RS symbol. An interleaver interleaves the RS symbols to generate an interleaved RS symbol data stream. A Hamming parity check block is generated for a corresponding RS symbol group and inserted into the interleaved RS symbol data stream. Other embodiments also exist.

[0004] According to an embodiment, the present invention provides a communication device, which includes m communication channels, and the m communication channels include a first communication channel configured to receive a first coded data stream. The device further includes a first alignment module, which is configured to align the first coded data stream to output aligned Reed-Solomon (RS) symbols. The device also includes a convolution interleaver, which is configured to interleave the aligned RS symbols into RS symbol parts. Each of the RS symbol parts consists of n RS symbols. The device also includes an encoder, which is configured to generate a Hamming parity block corresponding to the RS symbol part and output a first Hamming coded data stream. The device further includes a distribution block for distributing m Hamming coded data streams to k physical channels. The m Hamming coded data streams include a first Hamming coded data stream.

[0005] It should be understood that embodiments of the present invention provide many benefits over conventional techniques. In addition, encoder and decoder modules according to embodiments of the present invention can be easily applied to existing systems. For example, in a high-speed data communication system based on PAM4, an interleaver and a Hamming encoder and decoder module are added to an existing communication chip through an RS encoding scheme. The addition of a Hamming parity block for interleaved RS symbols according to an embodiment of the present invention adds very little transmission overhead (8 / 128) and can achieve a low-power implementation. Through the interleaving mechanism, the interleaved Hamming parity block can be used for different data transmission modes, including but not limited to 50G, 100G, 200G and 400G modes.

[0006] Embodiments of the present invention can be implemented in conjunction with existing systems and processes. For example, error checking and correction based on Hamming codes can be easily applied to existing communication systems. Encoding and decoding modules according to embodiments of the present invention can be easily manufactured using existing manufacturing processes and systems. There are other benefits as well. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a block diagram illustrating an FEC encoding scheme according to an embodiment of the present invention.

[0008] Figure 2A is a simplified diagram illustrating a communication device according to an embodiment of the present invention.

[0009] Figure 2B is a table showing encoding performance according to an embodiment of the present invention.

[0010] Figure 3 is a block diagram illustrating the combination of encoded data streams according to an embodiment of the present invention.

[0011] Figure 4 is a block diagram illustrating suboptimal interleaving at boundaries between combined Hamming codewords from encoded data streams in accordance with an embodiment of the present invention.

[0012] Figure 5 is a block diagram illustrating an interleaved FEC encoding scheme according to an embodiment of the present invention.

[0013] Fig. 6A is a block diagram showing a communication device according to an embodiment of the present invention.

[0014] Figure 6B is a block diagram showing a decoding device according to an embodiment of the present invention.

[0015] Figure 7 is a simplified diagram showing an interleaving mechanism for a 400G communication interface according to an embodiment of the present invention.

[0016] Figure 8 is a simplified diagram illustrating an interleaving mechanism for a 200G communication interface according to an embodiment of the present invention.

[0017] Fig. 9 is a simplified diagram illustrating a bidirectional interleaving mechanism for a 100G communication interface according to an embodiment of the present invention.

[0018] Fig.10 is a simplified diagram illustrating a unidirectional interleaving mechanism for a 100G communication interface according to an embodiment of the present invention. DETAILED DESCRIPTION

[0019] The present invention relates to data communication and coding techniques. More specifically, an embodiment of the present invention provides a communication device for aligning a data stream with a RS symbol. An interleaver interleaves the RS symbols to generate an interleaved RS symbol data stream. A Hamming parity check block is generated for a corresponding RS symbol group and inserted into the interleaved RS symbol data stream. Other embodiments also exist.

[0020] Figure 1 1 is a block diagram illustrating an FEC encoding scheme according to an embodiment of the present invention. The diagram is merely an example, which should not unduly limit the scope of the claims. A person of ordinary skill in the art will recognize various changes, substitutions, and modifications. The encoded data stream 100 includes a data portion 101 and a Hamming parity block 102. In a specific embodiment, the data portion 101 includes 12 Reed-Solomon (RS) symbols 103 to 114. Each of the RS symbols (i.e., boxes 103 to 114) contains 10 bits of data. For example, each of the RS symbols comes from a different codeword (e.g., as generated in the FEC encoding process and the codeword interleaver). The Hamming parity block 102 includes 8 bits of Hamming data corresponding to the RS symbols 103 to 114. For example, a "Hamming parity block" refers to a parity block generated by Hamming encoding, and a "Hamming codeword" refers to a codeword having a data portion (e.g., box 101) and a Hamming parity block (e.g., box 102) of an RS symbol. For example, the 8-bit parity data contained in the Hamming parity block 102 corresponds to a parity block of an 8-bit extended Hamming error correction code. As part of the data stream 100, the Hamming codeword includes a data portion 101 and a Hamming parity block 102. It should be understood that the Hamming parity bits stored in the Hamming parity block 102 provide a significant improvement in overall coding gain (e.g., an overall coding gain approaching 10 dB in some implementations) and allow for a simple soft decision decoding algorithm. For example, the data stream 100 includes repeated Hamming codewords that form a pattern of 12 RS symbols (10 bits each) followed by a Hamming parity block (8 bits). In various applications, a Hamming decoding failure will only result in at most one RS symbol error per RS ​​codeword. In some communication systems and applications, in addition to the process of generating the Hamming parity block 102, a different and separate forward error correction (FEC) process (e.g., hard FEC) is performed.

[0021] As an example, Figure 1 The coding scheme shown is implemented into a communication system. Figure 2AIt is a simplified diagram showing a communication device according to an embodiment of the present invention. This diagram is only an example, which should not overly limit the scope of the claims. A person of ordinary skill in the art will recognize various changes, substitutions and modifications. The communication device 200 includes functional blocks 202 to 206 as shown. For example, functional blocks 202 to 206 are configured to process data from a single 25G FEC channel. Data received from the host 201 is processed at the AM lock block 202. For example, the communication device can be connected to the host 201 via more than one physical communication link. In various embodiments, the host 201 sends the RS symbol received by the AM lock block 202 to the communication system via the FEC channel as shown in the figure (i.e., RS encoding is performed on the host side). In some embodiments, the host 201 periodically inserts an alignment mark (AM) into the 25G FEC channel between RS symbol blocks. In some embodiments, the RS symbol received by the AM lock block 202 has been bidirectionally interleaved. The AM lock block 202 detects and locks to the AM, and aligns the received data with the boundary of the RS symbol. Block 203 uses a convolutional interleaving (CI) process to interleave the aligned data, where the frame data may be 6-way interleaved (the received RS symbols have been bidirectionally interleaved) or 12-way interleaved. Hamming encoder 204 performs encoding to insert Hamming parity data (e.g., 8-bit Hamming parity blocks) into the RS data stream. For example, Hamming encoder 204 generates Figure 1 The data stream 100 shown in FIG. 1 is a block diagram of a block diagram of a plurality of interleaved RS symbols, wherein an 8-bit Hamming parity block is generated for 12 interleaved RS symbols. The RS symbol data stream, now embedded with the Hamming parity block, is then processed at box 205, where Gray mapping is performed. The mapped data is transmitted by transmitter 206 via pulse amplitude modulation (PAM) channel 207. For example, in 100G communication, four 25G FEC data streams are received from host 201 and later combined (e.g., at transmission channel 207) for 100G communication. It should be understood that the communication device may include multiple communication channels. For example, there may be multiple data streams processed in parallel by multiple AM ​​locking blocks, convolution interleavers, RS encoders, and Hamming encoders. In various embodiments, BCH (n, k, t) coding is used instead of Hamming coding to encode RS symbols. For example, when t=1, BCH coding is equivalent to Hamming coding. In various embodiments, BCH encoding is performed on the interleaved RS symbols (e.g., similar to the above-described Hamming encoding process), where the BCH payload is n*10 bits for n RS symbols originating from different RS codewords. As an example, both BCH encoding and Hamming encoding may be referred to as "inner FEC" processing to distinguish them from FEC encoding of RS symbols.

[0022] Figure 2BIt is a table showing the coding performance according to an embodiment of the present invention. This diagram is only an example, which should not overly limit the scope of the claims. Those of ordinary skill in the art will recognize various changes, substitutions and modifications. Depending on the implementation, various types of Hamming coding schemes can be used. For example, the scheme Ham (128, 120) involves a relatively small coding overhead (i.e., 8-bit error correction information corresponding to a 120-bit data payload), but because the inner code is relatively long to 128 bits, the scheme involves a maximum waiting time of 137ns, as shown in the figure. In contrast, the scheme Ham (68, 60) involves a relatively large overhead (i.e., 8-bit error correction information corresponding to a 60-bit data payload) that is approximately twice that of the Ham (128, 120) scheme, which has a lower waiting time and a greater coding gain. In a specific embodiment, the coding scheme according to the present invention provides an 8-bit Hamming block for 6 RS symbols (e.g., each RS symbol is a 10-bit codeword), and the data rate characteristics will follow the Ham (68, 60) scheme. Depending on the implementation, different coding schemes can be used.

[0023] Figure 3 3 is a block diagram illustrating a combination of coded data streams according to an embodiment of the present invention. The diagram is merely an example and should not unduly limit the scope of the claims. A person of ordinary skill in the art will recognize various changes, substitutions, and modifications. Data stream 300 includes an RS symbol portion 301 generated from a first processed FEC channel followed by a Hamming parity block 302. RS symbol portion 301 includes 12 RS symbols. For example, these 12 RS symbols are generated by a 12-way RS codeword interleaving structure. Hamming parity block 302 includes 8-bit Hamming parity, which may correspond to 12 RS symbols in a Ham (128, 120) scheme. Hamming parity block 302 is followed by RS symbol portion 303, which includes 12 RS symbols. It should be noted that the RS symbols in RS symbol portion 303 are interleaved in the same order as the RS symbols in RS symbol portion 301. Similarly, Hamming parity block 304 contains 8-bit Hamming parity for the 12 RS symbols in RS symbol portion 303 generated from the second processed FEC channel. The data stream 300 shown includes two Hamming codewords: a first Hamming codeword consisting of a data portion 301 and a Hamming parity block 302, and a second Hamming codeword consisting of a data portion 303 and a Hamming parity block 304. The data stream 300 shows an ideal situation, where RS symbols from different processed FEC channels are kept 12-way interleaved at the Hamming codeword boundary.

[0024] Figure 44 is a block diagram illustrating suboptimal interleaving at the boundary between Hamming codewords from a combination of coded data streams according to an embodiment of the present invention. The diagram is merely an example, which should not unduly limit the scope of the claims. A person of ordinary skill in the art will recognize various variations, substitutions, and modifications. Data stream 400 includes a block of RS symbols followed by a corresponding Hamming parity block. For example, RS symbol portion 401 includes 12 RS symbols (e.g., according to a predetermined interleaving scheme). Two RS symbols in portion 402 are part of 12-symbol portion 401. For example, due to a bidirectional interleaving process performed by a host, the two RS symbols are adjacent to each other. Hamming parity block 403 contains an 8-bit Hamming code and corresponds to 12 RS symbols in portion 401. Portion 401 and Hamming parity block 403 form a first Hamming codeword. In various cases, due to skew introduced during data transmission (e.g., data transmitted at high speeds is misaligned between 25G FEC channels), the 12-way interleaving of RS symbols is not maintained at the boundary between RS symbol portions 401 and 406 originating from different FEC channels. besides, Figure 4 The situation shown reduces the burst tolerance of the system. In various embodiments, a de-skew mechanism is used to solve Figure 4 Misalignment problem shown.

[0025] Figure 5 is a block diagram illustrating an interleaved FEC coding scheme according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. A person of ordinary skill in the art will recognize various changes, substitutions, and modifications. Figure 5 In the bidirectional Hamming codeword interleaving scheme, the Hamming codewords are interleaved. In the absence of bidirectional interleaving (i.e., an interleaving process separate from the 12-way interleaving of RS symbols), the Hamming parity block 502 includes 8-bit Hamming code information of the previous 12 RS symbols (wherein part 501 is the first two RS symbols), and the Hamming parity block 504 similarly includes 8-bit Hamming code information of the previous 12 RS symbols (wherein part 503 is the first two RS symbols). In the bidirectional Hamming codeword interleaving scheme, two RS symbol parts (each containing 12 RS symbols) are interleaved two RS symbols at a time. RS part 501 and RS part 503 are interleaved to become the first four RS symbols of the long RS symbol part formed by the bidirectional interleaving process (parts 505 and 506 as shown in the figure). Hamming parity block 502 is interleaved to position 507. Hamming parity block 504 is interleaved to position 508. The two Hamming parity blocks 507 and 508 are adjacent to each other after interleaving. It should be understood that Figure 5 The bidirectional interleaving in is used as an example only. The Hamming codewords may also be interleaved in other ways before transmission over the physical data channel. One of the benefits of using a bidirectional interleaving scheme is that the system is more tolerant to correlated erroneous bit pairs, as they will tend to be distributed over multiple Hamming codewords.

[0026] In practice, there are various limitations and constraints, such as latency and power. To address different situations, the implementation of a soft decoder for Hamming codes can be based on modeling of the communication model. For example, the Hamming code is decoded using soft information such as log-likelihood ratios (LLRs) using an additive white Gaussian noise (AWGN) model that simulates the effects of many random processes occurring in nature, where the decoding algorithm assumes independent and identically distributed (IID) bit errors.

[0027] In some cases, correlated pairs of errors can be a problem. For example, if a large fraction of the errors occur in pairs, such as in cases involving Maximum Likelihood Sequence Estimation (MLSE) or Decision Feedback Equalization (DFE) coding, the performance of Hamming decoding may be degraded. Interleaving multiple Hamming codewords on the line side reduces the probability that two errors hit the same Hamming codeword.

[0028] Fig. 6A 6 is a block diagram showing a communication device 600 according to an embodiment of the present invention. This diagram is only an example, which should not unduly limit the scope of the claims. A person of ordinary skill in the art will recognize various changes, substitutions and modifications. For the purpose of illustration, the communication device 600 assumes that de-skew of the 25G FEC channel is not performed, and the meaning of this assumption is that in order to ensure 12-way RS symbol interleaving inside the Hamming payload, interleaving and encoding processing are performed separately for each FEC channel. The communication device 600 includes multiple (m channel) data paths, each data path includes its own functional blocks 601 to 603, and the data outputs of the functional blocks 601 to 603 are processed and distributed at block 604. For example, in a 100G communication mode, data from four (m=4) 25G FEC channels are processed in parallel for the purpose of AM locking, interleaving and Hamming encoding, and four data streams (each data stream's own Hamming parity block is inserted into the corresponding data stream) are distributed at block 604 for 100G communication. For the purpose of interleaving and Hamming coding, the four 25G FEC lanes are independent and no de-skew processing is required between the four lanes. If the communication device 600 is configured to perform 400G communication, there will be 16 lanes (each 25G) from the input side.

[0029] like Fig. 6AAs shown, data from a 25G FEC channel is first processed by an AM locking block 601. In various embodiments, the AM locking block 601 uses embedded alignment marks to align the data stream received from the FEC channel. For example, alignment marks in the FEC channel are detected and used to determine and align with RS symbol boundaries. For a bidirectional KP4 interleaved FEC channel, RS symbols are aligned based on 20-bit boundaries. For a KP4 FEC channel without interleaving, RS symbols are aligned on 10-bit boundaries because the convolutional interleaver can be designed to perform 12-way interleaving of 10-bit symbols.

[0030] At block 602, aligned RS symbols are interleaved. In a specific embodiment, block 602 includes a convolutional interleaver that interleaves RS symbols 12-way to generate Figure 1 RS symbol portion shown. Block 602 minimizes latency in the interleaving process, which for a 120-bit payload (i.e., 12 10-bit symbol blocks) of the Hamming encoder, the payload of 12 RS symbols comes from 12 different RS codewords. For example, it should be understood that each FEC channel arrangement (e.g., 100G unidirectional, 100G bidirectional, 200G, and 400G) has a different number of RS symbols per FEC channel. In various embodiments, the Hamming encoding scheme according to the present invention will generate an 8-bit Hamming parity block for 12 different RS symbols, and when the data received from the host is already bidirectionally interleaved, block 602 only needs to perform 6-way interleaving instead of 12-way interleaving. As explained below, the interleaving scheme of block 602 depends largely on the input data stream (e.g., Figure 7 shows 6-way interleaving, while Fig.10 12-way interleaving is shown).

[0031] Box 603 performs Hamming encoding. For example, an 8-bit Hamming parity block is generated for an RS symbol portion containing 12 RS symbols. The interleaved RS symbols with embedded Hamming parity blocks now form a data stream of Hamming codewords (i.e., each Hamming codeword consists of interleaved RS symbols and a corresponding Hamming parity block) processed at box 604. As described above, the device 600 includes multiple 25G FEC channels processed by their corresponding boxes 601 to 603. For example, in an arrangement for PAM4 communications with 50G / 100G outputs, box 604 receives data from four 25G FEC channels (already interleaved and Hamming encoded) and performs data allocation and mapping as shown. The device 600 does not perform de-skew as described above.

[0032] As an example, for a 100G channel, four processed 25G FEC channels are combined, and the Hamming codewords from the four FEC channels are allocated in a round-robin manner. For example, block 604 sequentially sends 128 bits of data from the first FEC channel and its corresponding Hamming encoder, 128 bits of data from the second FEC channel and its corresponding Hamming encoder, 128 bits of data from the third FEC channel and its corresponding Hamming encoder, and 128 bits of data from the fourth FEC channel and its corresponding Hamming encoder. Similarly, for a 50G channel output, two FEC channels are combined and allocated in a round-robin manner.

[0033] Block 604 additionally maps bit pairs for PAM4 communication. Depending on the implementation, an optional 1 / (1+D) modulo-4 precoder is used after PAM4 mapping.

[0034] It should be understood that the device 600 is flexible and can operate in various modes. For example, the device 600 can operate in 100G PCS mode (e.g., with or without bidirectional KP4 interleaving), 200G PCS mode, and 400G PCS mode. Each of these four data communication modes is implemented by a specific convolution interleaver. For example, there may be different hardware chips to perform different types of convolution interleaving processes. In a digital implementation, different types of convolution interleaving processes are performed by the same hardware chip, but using different software algorithms. The same Hamming encoding scheme can be used for these four modes. In the implementation of a 50G or 100G PAM4 channel, different numbers of FEC channels can be combined, wherein each FEC channel interleaves an optional Hamming parity block. For example, for 100G communications (with a 100G output from box 604), four 25G FEC lanes at the input are processed and combined; for 400G communications, at box 604, 16 (m=16) FEC lanes (25G per FEC lane) at the input are combined and distributed (i.e., if each output physical channel is 100G, it is combined into four output channels, or if the output physical channel is 400G, it is combined into a single output channel).

[0035] Figure 6B610 is a block diagram illustrating a decoding device 610 according to an embodiment of the present invention. The diagram is merely an example and should not unduly limit the scope of the claims. A person of ordinary skill in the art will recognize various changes, substitutions and modifications. The decoding device 601 includes a Hamming soft decoder 611 and a KP4 decoder 612. As shown, the input of the block 611 includes a DSP output related to the reliability of the communication link and the hard decision, and the block 611 additionally uses the output of the KP4 decoder 612 to generate a bit flip. For example, the block 611 uses the bit flip from the RS KP4 hard decoding provided by the KP4 decoder 612 to determine the bit flip. In various embodiments, the KP4 decoder 612 includes a conventional hard decision algebraic decoder, and it outputs the decoded bit. For example, the decoding device 610 performs an iterative decoding process. For example, if the process for decoding the RS codeword fails, a decoding iteration is performed. The bit flip from the successfully decoded RS codeword is transmitted back to the Hamming code soft decoder 611. For example, the reliability of the bit corrected by the RS decoder is set to "INF", but no other updates to the soft reliability are performed. The Hamming soft decoding process is repeated, and the failed RS symbols are decoded again.

[0036] Figure 7 is a simplified diagram illustrating an interleaving mechanism for a 400G communication interface according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art will recognize various variations, substitutions, and modifications. The interleaver 700 performs convolutional interleaving processing through 6 data channels with varying delays, and the delay is predetermined based on the data rate of the 400G communication. As an example, the input switch 701 is synchronized with respect to the input data stream and is also synchronized with respect to the output switch 702. Depending on the implementation, the input switch 701 can be synchronized with respect to the AM position. In various embodiments, synchronization at the output switch 702 is implied by the boundaries of the Hamming parity blocks. Figure 7In the embodiment of the present invention, the RS code symbol is interleaved into a 20-bit data block, which is two RS symbols from two different RS code words. Block A[m] represents a block of two 10-bit RS symbols. For example, block A[6k] corresponds to the first group of bidirectionally interleaved RS symbols, and block A[6k+1] represents the next two RS symbols after the first group of two RS symbols, and so on. For the purpose of 6-way interleaving as shown in the figure, the interleaved delay channel 703 has different delay amounts (for example, 30 units for A[6k] and no delay for A[6k+5]). For example, each delay channel includes a plurality of serially cascaded 20-bit buffers, one buffer for each delay unit, for temporarily storing a set of two RS symbols. Delay channel 703 includes 6 branches with a 6-way interleaved variable delay (including zero delay) corresponding to the RS symbol of bidirectional interleaving, and the output of interleaver 700 is a 12-way RS interleaved data stream forming the payload of the Hamming code word. For example, the output payload for generating a Hamming parity block is (A[6k-180], A[6k-143], A[6k-106], A[6k-69], A[6k-32], A[6k+5]).

[0037] Figure 8 It is a simplified diagram showing an interleaving mechanism for a 200G communication interface according to an embodiment of the present invention. This diagram is only an example, which should not overly limit the scope of the claims. Those of ordinary skill in the art will recognize various changes, substitutions and modifications. Interleaver 800 performs convolution interleaving processing through 6 data channels with variable delays, and the delay is predetermined based on the data rate of 200G communication. A data stream with bidirectionally interleaved RS symbols is received at input 801, which distributes the received data stream 6-way to the delay channel. In various embodiments, input 801 distributes the bidirectionally interleaved RS symbols (one RS symbol for each interleaved RS codeword) in a 20-bit block to 6 delay channels, as shown in the figure. For example, a 20-bit block of RS symbols is represented by A[M]. For example, block A[6k] corresponds to the first group of bidirectionally interleaved RS symbols, and block A[6k+1] represents the next group of bidirectionally interleaved RS symbols after the first group. For the purpose of 6-way interleaving as shown, the interleaving delay path 803 has different delay amounts (e.g., 60 units for A[6k] and zero delay for A[6k+5]). Note that there is a 60-unit delay for A[6k] and zero delay for A[6k+5]. Figure 7There is a 30 unit delay for A[6k], and the difference is due to the different data communication modes (i.e., 200G vs. 400G). Output 803 provides the subsequent interleaved data stream ready for Hamming encoding, and the payload for Hamming encoding is (A[6k-360], A[6k-287], A[6k-214], A[6k-141], A[6k-68], A[6k+5]).

[0038] Fig. 9 It is a simplified diagram showing a bidirectional interleaving mechanism for a 100G communication interface according to an embodiment of the present invention. This diagram is only an example, and it should not overly limit the scope of the claims. Those of ordinary skill in the art will recognize various changes, substitutions and modifications. Interleaver 900 performs convolution interleaving processing through 6 data channels with variable delays, and the delay is predetermined based on the data rate of 100G communication (through a bidirectionally interleaved KP4 FEC channel). A data stream with bidirectionally interleaved RS symbols is received at input 901, which distributes the received data stream 6-way to the delay channel. In various embodiments, input 901 distributes the RS symbols in a 20-bit block to 6 delay channels, as shown in the figure. For example, a 20-bit block of bidirectionally interleaved RS symbols is represented by A[M]. For example, block A[6k] corresponds to a first group of bidirectionally interleaved RS symbols, and block A[6k+1] represents the next bidirectionally interleaved RS symbol after the first group of bidirectionally interleaved RS symbols. For the purpose of 6-way interleaving as shown, the interleaving delay path 903 has different amounts of delay (e.g., 120 units for A[6k] and no delay for A[6k+5]). Note that there is a 120 unit delay for A[6k] and no delay for A[6k+5]. Figure 7 There is a 30 unit delay for A[6k], and the difference is due to the different data communication modes (i.e., bidirectional 100G vs. 400G). Output 903 provides the subsequent interleaved data stream ready for Hamming encoding, and the payload for Hamming encoding is (A[6k-720], A[6k-575], A[6k-430], A[6k-285], A[6k-140], A[6k+5]).

[0039] Fig.10It is a simplified diagram showing a unidirectional interleaving mechanism for a 100G communication interface according to an embodiment of the present invention. This diagram is only an example, which should not overly limit the scope of the claims. Those of ordinary skill in the art will recognize various changes, substitutions and modifications. Interleaver 1000 performs convolution interleaving processing through 12 data channels with variable delays, and the delay is predetermined based on the data rate of 100G communication (through a unidirectional interleaved KP4 FEC channel). A single data stream with RS symbols is received at input 901, which distributes the received data stream 12 ways to delay channels 1002. In various embodiments, input 1001 distributes RS symbols in 10-bit blocks (each RS symbol is 10 bits) to 12 delay channels, as shown in the figure. For example, a 10-bit block of RS symbols is represented by A[M]. For example, block A[12k] corresponds to the first RS symbol, and block A[12k+1] represents the next RS symbol after the first RS symbol. For the purpose of 12-way interleaving as shown, the interleaving delay path 12 has different amounts of delay (e.g., 132 units for A[12k] and no delay for A[12k+11]). Note that there is a 132 unit delay for A[12k] and no delay for A[12k+11]. Figure 7 In , A[6k] has a delay of 30 units, and the difference is due to the different data communication modes (ie, unidirectional 100G vs. 400G). Output 1003 provides the interleaved data stream that is subsequently ready for Hamming encoding.

[0040] Hamming codewords can be decoded in various ways. On the transmitting side, encoding (e.g., Hamming encoding) is performed on the interleaved RS encoded data stream with the Hamming codeword. For example, the decoded input includes a syndrome value, an overall parity check, and an LLR. For example, the LLR indicates reliability information associated with each bit of the decoded input. In various embodiments, the input and output permutations are embedded in the Hamming decoder. The decoding process depends on the calculated syndrome value and the overall parity check bit. In a specific encoding scheme, the syndrome value "0" plus the overall parity check bit zero indicates that the decoding process is complete and no additional steps are required. After checking the syndrome value, the decoding process determines whether to terminate early based on the reliability of the bit flip indicated by the non-zero syndrome; otherwise, the decoder proceeds to error mapping (e.g., selecting between an odd number of errors and an even number of errors), and the selection of the error mapping is based on the parity check bit. The selected error mapping and syndrome value are used to flip one or more bits from the hard decoded input, and select a candidate codeword (which can be based on the minimum LLR amplitude in the position of the inversion relative to the hard decoded input). For example, the positions for bit flips correspond to different combinations of received bits that are least reliable.

[0041] As described above, interleaving of Hamming-encoded FEC channels can be performed in various ways. In an example, interleaving involves cyclically allocating 128-bit Hamming codewords (e.g., on m×25G FEC channels, m=2 or m=4) to the Gray mapper, where 64 consecutive PAM4 UIs originate from a single Hamming-encoded 25G FEC channel. In different interleaving schemes, each FEC channel (i.e., before line allocation) performs a block interleaving process of P consecutive Hamming parity blocks. The process involves writing P Hamming parity blocks row by row to a p×128 memory. For example, the process divides the 128-bit row into 8 20-bit columns and 1 8-bit column. When accessed, the data is read out column by column. For line allocation, a cyclic allocation is performed on the "cells" of the P 128-bit Hamming parity blocks of each FEC channel. For example, 64×P consecutive PAM4 UIs originate from P-way interleaved Hamming parity blocks from a single FEC channel. It will be appreciated that other variations are possible. For example, the RS symbol interleaving depth may be improved (on-line) by cyclically shifting the Hamming payload on 20-bit boundaries (eg, performed after Hamming encoding).

[0042] At the receiving end, an important aspect is data synchronization. In various embodiments, the synchronization process is equivalent to determining the boundaries of the Hamming parity blocks. Depending on the implementation, various types of line distributors can be used. For a cyclic line distribution implementation, the alignment with the 64 UI Hamming parity block boundaries can be determined by searching at 64 positions in the received PAM4 signal. For each candidate position, a Hamming syndrome calculator is used to try to "lock" the code block boundary. In an exemplary embodiment, the FEC block synchronization state machine searches for a programmable number of T zero syndrome received codewords in a window of N codewords. If misaligned, the probability of a zero syndrome is 1 / 256. If aligned correctly and the input bit error rate (BER) is 3E-2 (e.g., SNR=11.85dB; about 3dB less than the SFEC threshold), the probability of a zero error is about 1 / 50. In the case of an SNR of 13.9dB, the probability of a zero error is about 1 / 4; when the SNR is 12.9dB, the probability of a zero error is about 1 / 14. Once Hamming lock is obtained, the convolutional deinterleaver (CDi) is implicitly locked.The latency characteristics of the convolutional interleaver and convolutional deinterleaver are the main contributors to end-to-end latency, with the Hamming encoding and decoding processes contributing a relatively small amount of latency.

[0043] While the above is a complete description of specific embodiments, various modifications, alternative constructions, and equivalents may be used. Therefore, the above descriptions and illustrations should not be taken as limiting the scope of the invention, which is defined by the appended claims.

Claims

1. A communication device for interleaving a first encoded data stream received from a host device, the communication device comprising: a first alignment circuit configured to (i) receive the first coded data stream from the host device, wherein the first coded data stream includes a plurality of Reed-Solomon (RS) symbols encoded using a forward error correction (FEC) code, and (ii) output an aligned first coded data stream, wherein the aligned first coded data stream is aligned with a boundary between the plurality of RS symbols encoded using the FEC code; a convolutional interleaver configured to interleave the plurality of RS symbols of the aligned first coded data stream into RS symbol portions, the RS symbol portions each comprising a predetermined number of RS symbols encoded using the FEC error correction code; an encoder configured to generate, for each of the RS symbol portions, a parity block corresponding to the RS symbol in the RS symbol portion, and output a second encoded data stream, the second encoded data stream comprising the aligned first encoded data stream and the parity block; as well as The allocation block is configured to allocate a plurality of the second encoded data streams to corresponding pulse amplitude modulation (PAM) physical channels.

2. The device according to claim 1, wherein: The first encoded data stream includes alignment marks between blocks of the plurality of RS symbols.

3. The apparatus according to claim 1, further comprising a mapper for mapping the second coded data stream to a PAM4 format, wherein Each of the second encoded data streams corresponds to a different 25G FEC data stream.

4. The device according to claim 1, wherein: A corresponding RS symbol among the plurality of RS symbols has 10 bits.

5. The device according to claim 4, wherein: The corresponding RS symbol part includes 12 RS symbols.

6. The device according to claim 5, wherein: The RS symbols of the first encoded data stream are bidirectionally interleaved, the convolutional interleaver is configured to perform 6-way interleaving, the 12 RS symbols are from 12 different RS code words, and the second encoded data stream includes the 12 RS symbols and a Hamming parity block.

7. The device according to claim 1, wherein: The plurality of second encoded data streams are associated with independent alignments.

8. The device according to claim 1, wherein: The coded data streams defining the plurality of second coded data streams are allocated to the PAM physical channels according to a round-robin scheme.

9. The device according to claim 1, wherein: The convolution interleaver includes n or n / 2 delay lines, where n is an integer.

10. The apparatus of claim 1, further comprising m alignment circuits, the m alignment circuits comprising the first alignment module, wherein: m is an integer.

11. The device according to claim 1, wherein: The convolutional interleaver is configured to perform 12-way interleaving to interleave 12 of the RS symbols into blocks.

12. A method for encoding a data stream, the method comprising: Receiving a first coded data stream, the first coded data stream comprising a plurality of coded Reed-Solomon (RS) symbols, each of the plurality of coded RS symbols having a boundary relative to other coded RS symbols of the plurality of coded RS symbols, the coded RS symbols being encoded using a forward error correction (FEC) error correction code; aligning the first coded data stream with the boundary of the coded RS symbols to generate a first aligned symbol stream; interleaving the first aligned symbol stream into RS symbol portions, each of the RS symbol portions comprising n of the coded RS symbols coded using the FEC error correction code; performing a first type of FEC encoding on the first aligned symbol stream to generate a first FEC encoded stream, the first FEC encoded stream including a first FEC block corresponding to each of the RS symbol portions; as well as allocating m FEC coded streams to k physical channels, the m FEC coded streams including the first FEC coded stream, Wherein n, m and k are integers.

13. The method according to claim 12, wherein: The first type of FEC encoding comprises a Hamming encoding of the first aligned symbol stream.

14. The method according to claim 12, wherein: The first type of FEC encoding comprises BCH encoding of the first aligned symbol stream.

15. The method according to claim 14, wherein: The BCH encoding is characterized by a payload of n*10 bits.

16. The method of claim 12, further comprising mapping the m inner FEC coded streams to a PAM4 format.

17. The method according to claim 12, wherein: The interleaving includes convolutional interleaving configured to interleave the first aligned symbol stream into RS symbol portions.

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