Data processing method and data processing device

Abstract

The present application discloses a data processing method. First data processing is performed on a plurality of first data streams obtained through first FEC encoding to obtain m second data streams. Second FEC encoding is performed on each of the second data streams, and each codeword obtained through the second FEC encoding includes N bits, where N=K+S. Second data processing is performed separately on m second data streams to obtain m third data streams. Each of the third data streams includes at least one bit sequence, each bit sequence including P+W bits, where P bits in each bit sequence are from the second data stream and W bits in each bit sequence are added alignment markers, where P=N×b. Third data processing is performed on the m third data streams to obtain Y modulated symbol streams, and modulation is performed on each modulated symbol stream.

Description

[Technical Field]

[0001] This application claims priority to Chinese Patent Application No. 202211307290.5, filed with the State Intellectual Property Office of China on October 24, 2022, entitled "Data Processing Method and Data Processing Device," Chinese Patent Application No. 202211559068.4, filed with the State Intellectual Property Office of China on December 6, 2022, entitled "Data Processing Method and Data Processing Device," and Chinese Patent Application No. 202310631032.0, filed with the State Intellectual Property Office of China on May 30, 2023, entitled "Data Processing Method and Data Processing Device," all of which are incorporated herein by reference in their entireties.

[0002] The present application relates to the field of communications, and in particular to a data processing method and device. [Background technology]

[0003] Continually driven by 5G, cloud computing, big data, artificial intelligence, etc., Ethernet networks are evolving towards ever larger capacities, higher speeds, and lower latency. Forward error correction (FEC) coding is used to correct transmitted data, resolve transmission bit errors, and recover the original data sent by the transmitter from the received data.

[0004] Currently, a transmission strategy based on concatenated FEC is provided, in which a transmitter device is connected to a transmitter processing module through an attachment unit interface (AUI). The transmitter device performs a first FEC encoding on data to be transmitted and transmits the data obtained through the first FEC encoding to the transmitter processing module. The transmitter processing module performs a second FEC encoding on the data obtained through the first FEC encoding, performs modulation and mapping on the bit sequence obtained through the second FEC encoding to generate a corresponding modulated symbol sequence, and finally transmits the generated modulated symbol sequence to a receiver through an optical fiber. The data stream received by the receiver is asynchronous and contains noise. Generally, clock and data recovery (CDR) based on a phase-locked loop (PLL) is performed. Specifically, the clock is extracted from the data, and "retiming" is performed on the data to remove jitter generated during transmission. Demodulation and decoding are then performed to restore the original data transmitted by the transmitter. However, in existing solutions, the PLL circuit used for the CDR implemented by the receiver is complex to implement and has large PLL jitter. Summary of the Invention [Means for solving the problem]

[0005] The embodiments of the present application provide a data processing method and a data processing device for simplifying a receiver's clock extraction and synchronization scheme, realizing high-speed phase locking, achieving low PLL complexity and small jitter, and for simplifying operations such as receiver frame synchronization and inner codeword synchronization, and achieving low implementation complexity.

[0006] According to a first aspect, an embodiment of the present application provides a data processing method. This method is applied to a transmitter and includes the following steps: first data processing is performed on a plurality of first data streams obtained through first FEC encoding to obtain m second data streams, where m is an integer greater than 1; second FEC encoding is performed on each of the second data streams, where each codeword obtained through the second FEC encoding includes N bits, where N=K+S, where K represents the number of information bits and S represents the number of parity bits, and K is an integer greater than or equal to 1; second data processing is performed separately on the m second data streams to obtain m third data streams, where each third data stream includes at least one bit sequence, where each bit sequence includes P+W bits, where P bits in each bit sequence are from the second data stream, and W bits in each bit sequence are added alignment markers, where P=N×b, where b is an integer greater than or equal to 1. Further, third data processing is performed on the m third data streams to obtain Y modulated symbol streams, where Y is an integer greater than or equal to 1, and modulation is performed on each of the modulated symbol streams, and a baud rate value of each of the modulated symbol streams is an integer multiple of the reference clock frequency value.

[0007] In this implementation, P bits are periodically obtained from the data stream obtained through concatenated FEC encoding, and a W-bit alignment marker is inserted, resulting in a W-bit alignment marker every P+W bits in the data stream. Positive integers P and W are selected so that the baud rate of the modulated symbol data stream is an integer multiple of the Ethernet common reference clock frequency. This simplifies the receiver's clock extraction and synchronization scheme, realizes fast phase locking, and achieves low PLL complexity and jitter. Additionally, P must be a multiple of the code length N of the inner code, i.e., P = N × b, so that inner codeword synchronization can be guaranteed after the receiver performs frame synchronization on the received data (i.e., frame synchronization of P+W bits, also called alignment marker lock operation). This simplifies operations such as receiver frame synchronization and inner codeword synchronization, achieving low implementation complexity.

[0008] In some possible implementations, the baud rate value of each of the modulated symbol streams is an integer multiple of 156.25M.

[0009] In some possible implementations, convolutional interleaving is performed on each of the second data streams before the second FEC encoding. The convolutional interleaving includes delaying the input data stream based on r delay lines, where r is an integer greater than 1, the delay lines include different numbers of storage units, the delay line with the smallest number of storage units includes 0 storage units, the difference between the numbers of storage units in every two adjacent delay lines is Q, and each storage unit is for storing d bits. Bits in the input data stream are input sequentially to the r delay lines based on the order numbers of the r delay lines, d bits are input to each delay line only once, and d bits are output from each delay line only once, and the r*d consecutive bits in the data stream output through the convolutional interleaving include d bits output from each delay line, where Q is an integer greater than or equal to 1 and d is an integer greater than or equal to 1.

[0010] In some possible implementations, the input / output switches corresponding to the convolutional interleaver are at the 0th delay line every time f bits are output through the convolutional interleaver, where K×b is divisible by f. The starting position of each frame (W+P bits) should correspond to the starting positions of the input and output switches of the convolutional deinterleaver, which are usually at the topmost positions. More specifically, the input / output switches of the convolutional interleaver are at the topmost positions every time the convolutional interleaver outputs f bits, and the input / output switches of the convolutional deinterleaver are at the topmost positions every time the convolutional deinterleaver outputs f bits, so that synchronization performed by the convolutional deinterleaver can be guaranteed during frame synchronization.

[0011] In some possible implementations, r×d×c=K×b, where c is an integer greater than or equal to 1. Specifically, the convolutional interleaver and the convolutional deinterleaver may output K×b bits for each c round robin. In this case, the input and output switches of the convolutional interleaver and the convolutional deinterleaver are at the start position of the switch, so that the synchronization performed by the convolutional deinterleaver can be guaranteed during frame synchronization.

[0012] In some possible implementations, the rate of the first data stream is 850 Gbps;

number

[0013] In some possible implementations, N=128, K=120,

number

[0014] In some possible implementations, W=48, P=13056, a=728, b=102, baud rate=113.75 Gbaud, W=48, P=52224, a=726, b=408, baud rate=113.4375Gbaud, W=56, P=15232, a=728, b=119, baud rate=113.75Gbaud, W=56, P=60928, a=726, b=476, baud rate=113.4375Gbaud, W=64, P=13056, a=728, b=102, baud rate=113.75Gbaud, W=64, P=69632, a=726, b=544, baud rate=113.4375Gbaud, W=120, P=32640, a=728, b=255, baud rate=113.75Gbaud, W=120, P=52224, a=727, b=408, baud rate=113.5938Gbaud, W=120, P=130560, a=726, b=1020, baud rate=113.4375Gbaud, W=128, P=34816, a=728, b=272, baud rate=113.75 Gbaud, or W=128, P=139264, a=726, b=1088, baud rate=113.4375Gbaud.

[0015] In some possible implementations, N=170, K=160,

number

[0016] In some possible implementations, W=48, P=23120, a=724, b=136, baud rate=113.125 Gbaud, W=48, P=69360, a=723, b=408, baud rate=112.9688Gbaud, W=56, P=11560, a=726, b=68, baud rate=113.4375Gbaud, W=56, P=80920, a=723, b=476, baud rate=112.9688Gbaud, W=64, P=92480, a=723, b=544, baud rate=112.9688Gbaud, W=120, P=34680, a=725, b=204, baud rate=113.2813Gbaud, W=120, P=57800, a=724, b=340, baud rate=113.125Gbaud, W=120, P=173400, a=723, b=1020, baud rate=112.9688Gbaud, W=170, P=49130, a=725, b=289, baud rate=113.2813 Gbaud, or W=170, P=245650, a=723, b=1445, baud rate=112.9688Gbaud.

[0017] In some possible implementations, N=144, K=136,

number

[0018] In some possible implementations, W=48, P=5760, a=726, b=40, baud rate=113.4375 Gbaud, W=48, P=8640, a=724, b=60, baud rate=113.125Gbaud, W=48, P=11520, a=723, b=80, baud rate=112.9688Gbaud, W=48, P=17280, a=722, b=120, baud rate=112.8125Gbaud, W=48, P=34560, a=721, b=240, baud rate=112.6563Gbaud, W=56, P=5760, a=727, b=40, baud rate=113.5938Gbaud, W=56, P=20160, a=722, b=140, baud rate=112.8125Gbaud, W=56, P=40320, a=721, b=280, baud rate=112.6563Gbaud, W=64, P=5760, a=728, b=40, baud rate=113.75Gbaud, W=64, P=11520, a=724, b=80, baud rate=113.125Gbaud, W=64, P=23040, a=722, b=160, baud rate=112.8125Gbaud, W=64, P=46080, a=721, b=320, baud rate=112.6563Gbaud, W=120, P=14400, a=726, b=100, baud rate=113.4375Gbaud, W=120, P=17280, a=725, b=120, baud rate=113.2813Gbaud, W=120, P=28800, a=723, b=200, baud rate=112.9688Gbaud, W=120, P=43200, a=722, b=300, baud rate=112.8125Gbaud, W=120, P=86400, a=721, b=600, baud rate=112.6563Gbaud, W=144, P=11520, a=729, b=80, baud rate=113.9063Gbaud, W=144, P=17280, a=726, b=120, baud rate=113.4375Gbaud, W=144, P=25920, a=724, b=180, baud rate=113.125Gbaud, W=144, P=34560, a=723, b=240, baud rate=112.9688Gbaud, W=144, P=51840, a=723, b=360, baud rate=112.8125 Gbaud, or W=144, P=103680, a=721, b=720, baud rate=112.6563Gbaud.

[0019] In some possible implementations, W=56, P=5040, a=728, b=35, baud rate=113.75 Gbaud, W=56, P=10080, a=724, b=70, baud rate=113.125Gbaud, W=56, P=20160, a=722, b=140, baud rate=112.8125 Gbaud, or W=56, P=40320, a=721, b=280, baud rate=112.6563Gbaud.

[0020] In some possible implementations, N=148, K=140, W is a multiple of 4, and b is a multiple of 17.

[0021] In some possible implementations, N=128, K=120, and the baud rate of the modulated symbol stream is 113.4375 Gbaud.

[0022] In some possible implementations, P=1088×W.

[0023] In some possible implementations, the alignment marker includes at least one frame synchronization sequence that is 48 bits in length.

[0024] In some possible implementations, the 48 bits of the frame synchronization sequence are contiguous within the alignment marker.

[0025] In some possible implementations, the 48-bit values ​​of the frame synchronization sequence include 0x9A, 0x4A, 0x26, 0x65, 0xB5, and 0xD9.

[0026] In some possible implementations, the frame synchronization sequence includes two frame synchronization subsequences, each of which is 24 bits long, and the two frame synchronization subsequences are separated by 8 bits within the alignment marker.

[0027] In some possible implementations, the 24-bit values ​​of one of the two frame synchronization subsequences include 0x9A, 0x4A, and 0x26, and the 24-bit values ​​of the other of the two frame synchronization subsequences include 0x65, 0xB5, and 0xD9.

[0028] In some possible implementations, the alignment marker includes padding bits and / or a status field.

[0029] In some possible implementations, W is divisible by N.

[0030] In some possible implementations, at least one of the following operations is performed on each of the second data streams before the second FEC encoding: alignment marker lock, lane deskew, and lane reordering; and / or at least one of the following operations is further performed on each of the second data streams after the second FEC encoding: channel interleaving and scrambling.

[0031] In some possible implementations, performing first data processing on the plurality of first data streams to obtain m second data streams includes separately performing second FEC encoding on each group of eight first data streams among the plurality of first data streams to obtain each group of eight encoded data streams, and performing channel interleaving on each group of eight encoded data streams to obtain m second data streams to obtain one second data stream.

[0032] In some possible implementations, N=128, K=120, and performing channel interleaving on each group of eight coded data streams to obtain one second data stream includes obtaining one inner codeword of length 128 bits from each coded data stream in each group of eight coded data streams to obtain eight total inner codewords, and obtaining two bits from each of the eight inner codewords in a round-robin manner to obtain 1024 consecutive bits in the second data stream.

[0033] In some possible implementations, a cyclic shift is performed on each of the second data streams before the second FEC encoding.

[0034] In some possible implementations, performing the first data processing on the multiple first data streams includes separately performing convolutional interleaving on the 8×m first data streams, separately performing cyclic shifting on the 8×m convolutionally interleaved first data streams, and separately performing second FEC encoding on the 8×m cyclically shifted first data streams.

[0035] In some possible implementations, performing the first data processing on the multiple first data streams includes separately performing convolutional interleaving on 2×m first data streams, dispersing each convolutionally interleaved first data stream to obtain four dispersed first data streams to obtain a total of 8×m dispersed first data streams, separately performing cyclic shifting on the 8×m dispersed first data streams, and separately performing second FEC encoding on the 8×m cyclically shifted first data streams.

[0036] In some possible implementations, performing the first data processing on the multiple first data streams includes separately performing convolutional interleaving on m first data streams, dispersing each convolutionally interleaved first data stream to obtain eight distributed first data streams, to obtain a total of 8×m distributed first data streams, separately performing cyclic shifting on the 8×m distributed first data streams, and separately performing second FEC encoding on the 8×m cyclically shifted first data streams.

[0037] In some possible implementations, to achieve further lower delay, lower complexity, and lower power consumption, the cyclic shift operation and / or the channel interleaving operation may alternatively be bypassed. Specifically, performing the first data processing on the multiple first data streams to obtain m second data streams includes first distributing each of the m first data streams to obtain eight distributed first data streams to obtain a total of 8×m distributed first data streams, then separately performing second FEC encoding on the 8×m distributed first data streams to obtain 8×m coded data streams, and performing codeword merging on each of the eight coded data streams among the 8×m coded data streams to obtain one second data stream to obtain m second data streams in total. It should be understood that performing codeword merging on the eight coded data streams is equivalent to performing one-way Hamming codeword interleaving on the eight coded data streams.

[0038] In some possible implementations, the alignment marker includes at least one target codeword, the target codeword including N bits.

[0039] In some possible implementations, the target codeword is obtained by performing a second FEC encoding on the K-bit alignment marker information. The target codeword may also be referred to as an inner codeword, and it should be understood that selecting one or more inner codewords as a specific pattern of alignment markers helps the receiver to perform low-complexity frame synchronization and codeword synchronization.

[0040] In some possible implementations, the alignment markers are obtained by performing codeword interleaving on multiple target codewords. For example, each alignment marker is obtained by performing eight-way codeword interleaving on eight target codewords. Herein, codeword interleaving may also be referred to as channel interleaving. It should be understood that alignment markers obtained by performing codeword interleaving on multiple target codewords should also be considered to include multiple target codewords. Alternatively, each alignment marker is obtained by performing codeword integration on multiple target codewords. For example, each alignment marker is obtained by performing codeword integration on eight target codewords. Herein, codeword integration may also be referred to as one-way codeword interleaving.

[0041] According to a second aspect, an embodiment of the present application provides a data processing method. The method is applied to a receiver and includes the following steps: first, fourth data processing is performed on received Y modulated symbol streams to obtain m fourth data streams; demodulation is performed on each of the fourth data streams, and the Y modulated symbol streams are obtained by performing third data processing on m third data streams; modulation is performed on each of the modulated symbol streams, and the m third data streams are obtained by separately performing second data processing on m second data streams; and the m second data streams are obtained by performing first data processing on a plurality of first data streams obtained through first FEC encoding, where Y is an integer greater than or equal to 1 and m is an integer greater than 1; second FEC encoding is performed on each of the second data streams, and each codeword obtained through the second FEC encoding includes N bits, where N=K+S, K represents the number of information bits, S represents the number of parity bits, K is an integer greater than or equal to 1, and S is an integer greater than or equal to 1; Each of the third data streams includes at least one bit sequence, each bit sequence including P+W bits, where P bits in each bit sequence are from the second data stream and W bits in each bit sequence are added alignment markers, where P=N×b, where b is an integer greater than or equal to 1, and the baud rate value of each of the modulated symbol streams is an integer multiple of the reference clock frequency value. Further, frame synchronization is performed for each of the fourth data streams based on the alignment markers in each of the fourth data streams.

[0042] In some possible implementations, the baud rate value of each of the modulated symbol streams is an integer multiple of 156.25M.

[0043] In some possible implementations, convolutional interleaving is performed on each of the second data streams before the second FEC encoding. The convolutional interleaving includes delaying the input data stream based on r delay lines, where r is an integer greater than 1, the delay lines include different numbers of storage units, the delay line with the smallest number of storage units includes 0 storage units, the difference between the numbers of storage units in every two adjacent delay lines is Q, and each storage unit is for storing d bits. Bits in the input data stream are input sequentially to the r delay lines based on the order numbers of the r delay lines, d bits are input to each delay line only once, and d bits are output from each delay line only once, and the r*d consecutive bits in the data stream output through the convolutional interleaving include d bits output from each delay line, where Q is an integer greater than or equal to 1 and d is an integer greater than or equal to 1.

[0044] In some possible implementations, the input / output switches corresponding to the convolutional interleaver are at the 0th delay line every time f bits are output through the convolutional interleaver, where K×b is divisible by f. The starting position of each frame (W+P bits) should correspond to the starting positions of the input and output switches of the convolutional deinterleaver, which are usually at the topmost positions. More specifically, the input / output switches of the convolutional interleaver are at the topmost positions every time the convolutional interleaver outputs f bits, and the input / output switches of the convolutional deinterleaver are at the topmost positions every time the convolutional deinterleaver outputs f bits, so that synchronization performed by the convolutional deinterleaver can be guaranteed during frame synchronization.

[0045] In some possible implementations, r×d×c=K×b, where c is an integer greater than or equal to 1. Specifically, the convolutional interleaver and the convolutional deinterleaver may output K×b bits for each c round robin. In this case, the input and output switches of the convolutional interleaver and the convolutional deinterleaver are at the start position of the switch, so that the synchronization performed by the convolutional deinterleaver can be guaranteed during frame synchronization.

[0046] In some possible implementations, the rate of the first data stream is 850 Gbps;

number

[0047] In some possible implementations, N=128, K=120,

number

[0048] In some possible implementations, W=48, P=13056, a=728, b=102, baud rate=113.75 Gbaud, W=48, P=52224, a=726, b=408, baud rate=113.4375Gbaud, W=56, P=15232, a=728, b=119, baud rate=113.75Gbaud, W=56, P=60928, a=726, b=476, baud rate=113.4375Gbaud, W=64, P=13056, a=728, b=102, baud rate=113.75Gbaud, W=64, P=69632, a=726, b=544, baud rate=113.4375Gbaud, W=120, P=32640, a=728, b=255, baud rate=113.75Gbaud, W=120, P=52224, a=727, b=408, baud rate=113.5938Gbaud, W=120, P=130560, a=726, b=1020, baud rate=113.4375Gbaud, W=128, P=34816, a=728, b=272, baud rate=113.75 Gbaud, or W=128, P=139264, a=726, b=1088, baud rate=113.4375Gbaud.

[0049] In some possible implementations, N=170, K=160,

number

[0050] In some possible implementations, W=48, P=23120, a=724, b=136, baud rate=113.125 Gbaud, W=48, P=69360, a=723, b=408, baud rate=112.9688Gbaud, W=56, P=11560, a=726, b=68, baud rate=113.4375Gbaud, W=56, P=80920, a=723, b=476, baud rate=112.9688Gbaud, W=64, P=92480, a=723, b=544, baud rate=112.9688Gbaud, W=120, P=34680, a=725, b=204, baud rate=113.2813Gbaud, W=120, P=57800, a=724, b=340, baud rate=113.125Gbaud, W=120, P=173400, a=723, b=1020, baud rate=112.9688Gbaud, W=170, P=49130, a=725, b=289, baud rate=113.2813 Gbaud, or W=170, P=245650, a=723, b=1445, baud rate=112.9688Gbaud.

[0051] In some possible implementations, N=144, K=136,

number

[0052] In some possible implementations, W=48, P=5760, a=726, b=40, baud rate=113.4375 Gbaud, W=48, P=8640, a=724, b=60, baud rate=113.125Gbaud, W=48, P=11520, a=723, b=80, baud rate=112.9688Gbaud, W=48, P=17280, a=722, b=120, baud rate=112.8125Gbaud, W=48, P=34560, a=721, b=240, baud rate=112.6563Gbaud, W=56, P=5760, a=727, b=40, baud rate=113.5938Gbaud, W=56, P=20160, a=722, b=140, baud rate=112.8125Gbaud, W=56, P=40320, a=721, b=280, baud rate=112.6563Gbaud, W=64, P=5760, a=728, b=40, baud rate=113.75Gbaud, W=64, P=11520, a=724, b=80, baud rate=113.125Gbaud, W=64, P=23040, a=722, b=160, baud rate=112.8125Gbaud, W=64, P=46080, a=721, b=320, baud rate=112.6563Gbaud, W=120, P=14400, a=726, b=100, baud rate=113.4375Gbaud, W=120, P=17280, a=725, b=120, baud rate=113.2813Gbaud, W=120, P=28800, a=723, b=200, baud rate=112.9688Gbaud, W=120, P=43200, a=722, b=300, baud rate=112.8125Gbaud, W=120, P=86400, a=721, b=600, baud rate=112.6563Gbaud, W=144, P=11520, a=729, b=80, baud rate=113.9063Gbaud, W=144, P=17280, a=726, b=120, baud rate=113.4375Gbaud, W=144, P=25920, a=724, b=180, baud rate=113.125Gbaud, W=144, P=34560, a=723, b=240, baud rate=112.9688Gbaud, W=144, P=51840, a=723, b=360, baud rate=112.8125 Gbaud, or W=144, P=103680, a=721, b=720, baud rate=112.6563Gbaud.

[0053] In some possible implementations, W=56, P=5040, a=728, b=35, baud rate=113.75 Gbaud, W=56, P=10080, a=724, b=70, baud rate=113.125Gbaud, W=56, P=20160, a=722, b=140, baud rate=112.8125 Gbaud, or W=56, P=40320, a=721, b=280, baud rate=112.6563Gbaud.

[0054] In some possible implementations, N=148, K=140, W is a multiple of 4, and b is a multiple of 17.

[0055] In some possible implementations, the alignment marker includes padding bits and / or a status field.

[0056] In some possible implementations, W is divisible by N.

[0057] In some possible implementations, the alignment marker includes at least one target codeword, the target codeword including N bits.

[0058] In some possible implementations, the target codeword is obtained by performing a second FEC encoding on the K-bit alignment marker information. The target codeword may also be called an inner codeword, and selecting one or more inner codewords as a specific pattern of alignment markers helps the receiver to perform low-complexity frame synchronization and codeword synchronization.

[0059] In some possible implementations, the alignment markers are obtained by performing codeword interleaving on multiple target codewords. For example, each alignment marker is obtained by performing eight-way codeword interleaving on eight target codewords. Herein, codeword interleaving may also be referred to as channel interleaving. It should be understood that alignment markers obtained by performing codeword interleaving on multiple target codewords should also be considered to include multiple target codewords. Alternatively, each alignment marker is obtained by performing codeword integration on multiple target codewords. For example, each alignment marker is obtained by performing codeword integration on eight target codewords. Herein, codeword integration may also be referred to as one-way codeword interleaving.

[0060] According to a third aspect, an embodiment of the present application provides a data processing device for use in a transmitter, the data processing device including a first data processing unit, a second data processing unit, and a third data processing unit, the first data processing unit being configured to perform first data processing on a plurality of first data streams obtained through first forward error correction (FEC) encoding to obtain m second data streams, where m is an integer greater than 1, and second FEC encoding is performed on each of the second data streams, and each codeword obtained through the second FEC encoding includes N bits, where N=K+S, K represents the number of information bits, S represents the number of parity bits, K is an integer greater than or equal to 1, and S is an integer greater than or equal to 1. The second data processing unit is configured to separately perform second data processing on the m second data streams to obtain m third data streams, each of the third data streams including at least one bit sequence, each bit sequence including P+W bits, where P bits in each bit sequence are from the second data stream and W bits in each bit sequence are added alignment markers, and P=N×b, where b is an integer greater than or equal to 1. The third data processing unit is configured to perform third data processing on the m third data streams to obtain Y modulated symbol streams, where Y is an integer greater than or equal to 1, modulation is performed on each modulated symbol stream, and a baud rate value of each modulated symbol stream is an integer multiple of the reference clock frequency value.

[0061] In some possible implementations, the baud rate value of each of the modulated symbol streams is an integer multiple of 156.25M.

[0062] In some possible implementations, convolutional interleaving is performed on each of the second data streams before the second FEC encoding. The convolutional interleaving includes delaying the input data stream based on r delay lines, where r is an integer greater than 1, the delay lines include different numbers of storage units, the delay line with the smallest number of storage units includes 0 storage units, the difference between the numbers of storage units in every two adjacent delay lines is Q, and each storage unit is for storing d bits. Bits in the input data stream are input sequentially to the r delay lines based on the order numbers of the r delay lines, d bits are input to each delay line only once, and d bits are output from each delay line only once, and the r*d consecutive bits in the data stream output through the convolutional interleaving include d bits output from each delay line, where Q is an integer greater than or equal to 1 and d is an integer greater than or equal to 1.

[0063] In some possible implementations, the input / output switches corresponding to the convolutional interleaver are at the 0th delay line every time f bits are output through the convolutional interleaver, where K×b is divisible by f. The starting position of each frame (W+P bits) should correspond to the starting positions of the input and output switches of the convolutional deinterleaver, which are usually at the topmost positions. More specifically, the input / output switches of the convolutional interleaver are at the topmost positions every time the convolutional interleaver outputs f bits, and the input / output switches of the convolutional deinterleaver are at the topmost positions every time the convolutional deinterleaver outputs f bits, so that synchronization performed by the convolutional deinterleaver can be guaranteed during frame synchronization.

[0064] In some possible implementations, r×d×c=K×b, where c is an integer greater than or equal to 1. Specifically, the convolutional interleaver and the convolutional deinterleaver may output K×b bits for each c round robin. In this case, the input and output switches of the convolutional interleaver and the convolutional deinterleaver are at the start position of the switch, so that the synchronization performed by the convolutional deinterleaver can be guaranteed during frame synchronization.

[0065] In some possible implementations, the rate of the first data stream is 850 Gbps;

number

[0066] In some possible implementations, N=128, K=120,

number

[0067] In some possible implementations, W=48, P=13056, a=728, b=102, baud rate=113.75 Gbaud, W=48, P=52224, a=726, b=408, baud rate=113.4375Gbaud, W=56, P=15232, a=728, b=119, baud rate=113.75Gbaud, W=56, P=60928, a=726, b=476, baud rate=113.4375Gbaud, W=64, P=13056, a=728, b=102, baud rate=113.75Gbaud, W=64, P=69632, a=726, b=544, baud rate=113.4375Gbaud, W=120, P=32640, a=728, b=255, baud rate=113.75Gbaud, W=120, P=52224, a=727, b=408, baud rate=113.5938Gbaud, W=120, P=130560, a=726, b=1020, baud rate=113.4375Gbaud, W=128, P=34816, a=728, b=272, baud rate=113.75 Gbaud, or W=128, P=139264, a=726, b=1088, baud rate=113.4375Gbaud.

[0068] In some possible implementations, N=170, K=160,

number

[0069] In some possible implementations, W=48, P=23120, a=724, b=136, baud rate=113.125 Gbaud, W=48, P=69360, a=723, b=408, baud rate=112.9688Gbaud, W=56, P=11560, a=726, b=68, baud rate=113.4375Gbaud, W=56, P=80920, a=723, b=476, baud rate=112.9688Gbaud, W=64, P=92480, a=723, b=544, baud rate=112.9688Gbaud, W=120, P=34680, a=725, b=204, baud rate=113.2813Gbaud, W=120, P=57800, a=724, b=340, baud rate=113.125Gbaud, W=120, P=173400, a=723, b=1020, baud rate=112.9688Gbaud, W=170, P=49130, a=725, b=289, baud rate=113.2813 Gbaud, or W=170, P=245650, a=723, b=1445, baud rate=112.9688Gbaud.

[0070] In some possible implementations, N=144, K=136,

number

[0071] In some possible implementations, W=48, P=5760, a=726, b=40, baud rate=113.4375 Gbaud, W=48, P=8640, a=724, b=60, baud rate=113.125Gbaud, W=48, P=11520, a=723, b=80, baud rate=112.9688Gbaud, W=48, P=17280, a=722, b=120, baud rate=112.8125Gbaud, W=48, P=34560, a=721, b=240, baud rate=112.6563Gbaud, W=56, P=5760, a=727, b=40, baud rate=113.5938Gbaud, W=56, P=20160, a=722, b=140, baud rate=112.8125Gbaud, W=56, P=40320, a=721, b=280, baud rate=112.6563Gbaud, W=64, P=5760, a=728, b=40, baud rate=113.75Gbaud, W=64, P=11520, a=724, b=80, baud rate=113.125Gbaud, W=64, P=23040, a=722, b=160, baud rate=112.8125Gbaud, W=64, P=46080, a=721, b=320, baud rate=112.6563Gbaud, W=120, P=14400, a=726, b=100, baud rate=113.4375Gbaud, W=120, P=17280, a=725, b=120, baud rate=113.2813Gbaud, W=120, P=28800, a=723, b=200, baud rate=112.9688Gbaud, W=120, P=43200, a=722, b=300, baud rate=112.8125Gbaud, W=120, P=86400, a=721, b=600, baud rate=112.6563Gbaud, W=144, P=11520, a=729, b=80, baud rate=113.9063Gbaud, W=144, P=17280, a=726, b=120, baud rate=113.4375Gbaud, W=144, P=25920, a=724, b=180, baud rate=113.125Gbaud, W=144, P=34560, a=723, b=240, baud rate=112.9688Gbaud, W=144, P=51840, a=723, b=360, baud rate=112.8125 Gbaud, or W=144, P=103680, a=721, b=720, baud rate=112.6563Gbaud.

[0072] In some possible implementations, W=56, P=5040, a=728, b=35, baud rate=113.75 Gbaud, W=56, P=10080, a=724, b=70, baud rate=113.125Gbaud, W=56, P=20160, a=722, b=140, baud rate=112.8125 Gbaud, or W=56, P=40320, a=721, b=280, baud rate=112.6563Gbaud.

[0073] In some possible implementations, N=148, K=140, W is a multiple of 4, and b is a multiple of 17.

[0074] In some possible implementations, N=128, K=120, and the baud rate of the modulated symbol stream is 113.4375 Gbaud.

[0075] In some possible implementations, P=1088×W.

[0076] In some possible implementations, the alignment marker includes at least one frame synchronization sequence that is 48 bits in length.

[0077] In some possible implementations, the 48 bits of the frame synchronization sequence are contiguous within the alignment marker.

[0078] In some possible implementations, the 48-bit values ​​of the frame synchronization sequence include 0x9A, 0x4A, 0x26, 0x65, 0xB5, and 0xD9.

[0079] In some possible implementations, the frame synchronization sequence includes two frame synchronization subsequences, each of which is 24 bits long, and the two frame synchronization subsequences are separated by 8 bits within the alignment marker.

[0080] In some possible implementations, the 24-bit values ​​of one of the two frame synchronization subsequences include 0x9A, 0x4A, and 0x26, and the 24-bit values ​​of the other of the two frame synchronization subsequences include 0x65, 0xB5, and 0xD9.

[0081] In some possible implementations, the alignment marker includes padding bits and / or a status field.

[0082] In some possible implementations, W is divisible by N. In some possible implementations, at least one of the following operations is performed on each of the second data streams before the second FEC encoding: alignment marker locking, lane deskewing, and lane reordering; and / or at least one of the following operations is further performed on each of the second data streams after the second FEC encoding: channel interleaving and scrambling.

[0083] In some possible implementation forms, the first data processing unit is specifically configured to separately perform second FEC encoding on each group of eight first data streams among the plurality of first data streams to obtain each group of eight encoded data streams, and to perform channel interleaving on each group of eight encoded data streams to obtain one second data stream, in order to obtain m second data streams.

[0084] In some possible implementations, N=128 and K=120, and the first data processing unit is specifically configured to obtain one inner codeword of length 128 bits from each coded data stream in each group of eight coded data streams to obtain a total of eight inner codewords, and to obtain two bits from each of the eight inner codewords in a round-robin manner to obtain 1024 consecutive bits in the second data stream.

[0085] In some possible implementations, a cyclic shift is performed on each of the second data streams before the second FEC encoding.

[0086] In some possible implementations, the first data processing unit is specifically configured to separately perform convolutional interleaving on the 8×m first data streams, separately perform cyclic shifting on the 8×m convolutionally interleaved first data streams, and separately perform second FEC encoding on the 8×m cyclically shifted first data streams.

[0087] In some possible implementations, the first data processing unit is specifically configured to: separately perform convolutional interleaving on the 2×m first data streams; disperse each convolutionally interleaved first data stream to obtain four dispersed first data streams, to obtain a total of 8×m dispersed first data streams; separately perform cyclic shifting on the 8×m dispersed first data streams; and separately perform second FEC encoding on the 8×m cyclically shifted first data streams.

[0088] In some possible implementations, the first data processing unit is specifically configured to: separately perform convolutional interleaving on the m first data streams; disperse each convolutionally interleaved first data stream to obtain eight distributed first data streams, to obtain a total of 8×m distributed first data streams; separately perform cyclic shifting on the 8×m distributed first data streams; and separately perform second FEC encoding on the 8×m cyclically shifted first data streams.

[0089] In some possible implementations, the first data processing unit is specifically configured to: distribute each of the m first data streams to obtain eight distributed first data streams, so as to obtain a total of 8×m distributed first data streams; separately perform second FEC encoding on the 8×m distributed first data streams to obtain 8×m coded data streams; and perform codeword merging on each of the eight coded data streams among the 8×m coded data streams to obtain one second data stream, so as to obtain a total of m second data streams. It should be understood that performing codeword merging on the eight coded data streams is equivalent to performing one-way Hamming codeword interleaving on the eight coded data streams.

[0090] In some possible implementations, the alignment marker includes at least one target codeword, the target codeword including N bits.

[0091] In some possible implementations, the target codeword is obtained by performing a second FEC encoding on the K-bit alignment marker information. It should be understood that the target codeword may also be referred to as an inner codeword, and selecting one or more inner codewords as a particular pattern of alignment markers helps the receiver to perform low-complexity frame synchronization and codeword synchronization.

[0092] In some possible implementations, the alignment markers are obtained by performing codeword interleaving on multiple target codewords. For example, each alignment marker is obtained by performing eight-way codeword interleaving on eight target codewords. Herein, codeword interleaving may also be referred to as channel interleaving. It should be understood that alignment markers obtained by performing codeword interleaving on multiple target codewords should also be considered to include multiple target codewords. Alternatively, each alignment marker is obtained by performing codeword integration on multiple target codewords. For example, each alignment marker is obtained by performing codeword integration on eight target codewords. Herein, codeword integration may also be referred to as one-way codeword interleaving.

[0093] According to a fourth aspect, an embodiment of the present application provides a data processing device, which is used in a receiver and includes a data processing unit and a synchronization unit, wherein the data processing unit is configured to perform fourth data processing on received Y modulated symbol streams to obtain m fourth data streams, where demodulation is performed on each of the fourth data streams, the Y modulated symbol streams are obtained by performing third data processing on m third data streams, where modulation is performed on each of the modulated symbol streams, the m third data streams are obtained by separately performing second data processing on m second data streams, and the m second data streams are obtained by performing first data processing on a plurality of first data streams obtained through first forward error correction (FEC) encoding, where Y is an integer greater than or equal to 1, and m is an integer greater than 1. A second FEC encoding is performed on each of the second data streams, and each codeword obtained through the second FEC encoding includes N bits, where N=K+S, where K represents the number of information bits and S represents the number of parity bits, and K is an integer greater than or equal to 1. Each of the third data streams includes at least one bit sequence, where each bit sequence includes P+W bits, where P bits in each bit sequence are from the second data stream and W bits in each bit sequence are added alignment markers, where P=N×b, where b is an integer greater than or equal to 1, and the baud rate value of each of the modulated symbol streams is an integer multiple of the reference clock frequency. The synchronization unit is configured to perform frame synchronization for each of the fourth data streams based on the alignment markers in each of the fourth data streams.

[0094] In some possible implementations, the baud rate value of each of the modulated symbol streams is an integer multiple of 156.25M.

[0095] In some possible implementations, convolutional interleaving is performed on each of the second data streams before the second FEC encoding. The convolutional interleaving includes delaying the input data stream based on r delay lines, where r is an integer greater than 1, the delay lines include different numbers of storage units, the delay line with the smallest number of storage units includes 0 storage units, the difference between the numbers of storage units in every two adjacent delay lines is Q, and each storage unit is for storing d bits. Bits in the input data stream are input sequentially to the r delay lines based on the order numbers of the r delay lines, d bits are input to each delay line only once, and d bits are output from each delay line only once, and the r*d consecutive bits in the data stream output through the convolutional interleaving include d bits output from each delay line, where Q is an integer greater than or equal to 1 and d is an integer greater than or equal to 1.

[0096] In some possible implementations, the input / output switches corresponding to the convolutional interleaver are at the 0th delay line every time f bits are output through the convolutional interleaver, where K×b is divisible by f. The starting position of each frame (W+P bits) should correspond to the starting positions of the input and output switches of the convolutional deinterleaver, which are usually at the topmost positions. More specifically, the input / output switches of the convolutional interleaver are at the topmost positions every time the convolutional interleaver outputs f bits, and the input / output switches of the convolutional deinterleaver are at the topmost positions every time the convolutional deinterleaver outputs f bits, so that synchronization performed by the convolutional deinterleaver can be guaranteed during frame synchronization.

[0097] In some possible implementations, r×d×c=K×b, where c is an integer greater than or equal to 1. Specifically, the convolutional interleaver and the convolutional deinterleaver may output K×b bits for each c round robin. In this case, the input and output switches of the convolutional interleaver and the convolutional deinterleaver are at the start position of the switch, so that the synchronization performed by the convolutional deinterleaver can be guaranteed during frame synchronization.

[0098] In some possible implementations, the rate of the first data stream is 850 Gbps;

number

[0099] In some possible implementations, N=128, K=120,

number

[0100] In some possible implementations, W=48, P=13056, a=728, b=102, baud rate=113.75 Gbaud, W=48, P=52224, a=726, b=408, baud rate=113.4375Gbaud, W=56, P=15232, a=728, b=119, baud rate=113.75Gbaud, W=56, P=60928, a=726, b=476, baud rate=113.4375Gbaud, W=64, P=13056, a=728, b=102, baud rate=113.75Gbaud, W=64, P=69632, a=726, b=544, baud rate=113.4375Gbaud, W=120, P=32640, a=728, b=255, baud rate=113.75Gbaud, W=120, P=52224, a=727, b=408, baud rate=113.5938Gbaud, W=120, P=130560, a=726, b=1020, baud rate=113.4375Gbaud, W=128, P=34816, a=728, b=272, baud rate=113.75 Gbaud, or W=128, P=139264, a=726, b=1088, baud rate=113.4375Gbaud.

[0101] In some possible implementations, N=170, K=160,

number

[0102] In some possible implementations, W=48, P=23120, a=724, b=136, baud rate=113.125 Gbaud, W=48, P=69360, a=723, b=408, baud rate=112.9688Gbaud, W=56, P=11560, a=726, b=68, baud rate=113.4375Gbaud, W=56, P=80920, a=723, b=476, baud rate=112.9688Gbaud, W=64, P=92480, a=723, b=544, baud rate=112.9688Gbaud, W=120, P=34680, a=725, b=204, baud rate=113.2813Gbaud, W=120, P=57800, a=724, b=340, baud rate=113.125Gbaud, W=120, P=173400, a=723, b=1020, baud rate=112.9688Gbaud, W=170, P=49130, a=725, b=289, baud rate=113.2813 Gbaud, or W=170, P=245650, a=723, b=1445, baud rate=112.9688Gbaud.

[0103] In some possible implementations, N=144, K=136,

number

[0104] In some possible implementations, W=48, P=5760, a=726, b=40, baud rate=113.4375 Gbaud, W=48, P=8640, a=724, b=60, baud rate=113.125Gbaud, W=48, P=11520, a=723, b=80, baud rate=112.9688Gbaud, W=48, P=17280, a=722, b=120, baud rate=112.8125Gbaud, W=48, P=34560, a=721, b=240, baud rate=112.6563Gbaud, W=56, P=5760, a=727, b=40, baud rate=113.5938Gbaud, W=56, P=20160, a=722, b=140, baud rate=112.8125Gbaud, W=56, P=40320, a=721, b=280, baud rate=112.6563Gbaud, W=64, P=5760, a=728, b=40, baud rate=113.75Gbaud, W=64, P=11520, a=724, b=80, baud rate=113.125Gbaud, W=64, P=23040, a=722, b=160, baud rate=112.8125Gbaud, W=64, P=46080, a=721, b=320, baud rate=112.6563Gbaud, W=120, P=14400, a=726, b=100, baud rate=113.4375Gbaud, W=120, P=17280, a=725, b=120, baud rate=113.2813Gbaud, W=120, P=28800, a=723, b=200, baud rate=112.9688Gbaud, W=120, P=43200, a=722, b=300, baud rate=112.8125Gbaud, W=120, P=86400, a=721, b=600, baud rate=112.6563Gbaud, W=144, P=11520, a=729, b=80, baud rate=113.9063Gbaud, W=144, P=17280, a=726, b=120, baud rate=113.4375Gbaud, W=144, P=25920, a=724, b=180, baud rate=113.125Gbaud, W=144, P=34560, a=723, b=240, baud rate=112.9688Gbaud, W=144, P=51840, a=723, b=360, baud rate=112.8125 Gbaud, or W=144, P=103680, a=721, b=720, baud rate=112.6563Gbaud.

[0105] In some possible implementations, W=56, P=5040, a=728, b=35, baud rate=113.75 Gbaud, W=56, P=10080, a=724, b=70, baud rate=113.125Gbaud, W=56, P=20160, a=722, b=140, baud rate=112.8125 Gbaud, or W=56, P=40320, a=721, b=280, baud rate=112.6563Gbaud.

[0106] In some possible implementations, N=148, K=140, W is a multiple of 4, and b is a multiple of 17.

[0107] In some possible implementations, the alignment marker includes padding bits and / or a status field.

[0108] In some possible implementations, W is divisible by N.

[0109] In some possible implementations, the alignment marker includes at least one target codeword, the target codeword including N bits.

[0110] In some possible implementations, the target codeword is obtained by performing a second FEC encoding on the K-bit alignment marker information. The target codeword may also be called an inner codeword, and selecting one or more inner codewords as a specific pattern of alignment markers helps the receiver to perform low-complexity frame synchronization and codeword synchronization.

[0111] In some possible implementations, the alignment markers are obtained by performing codeword interleaving on multiple target codewords. For example, each alignment marker is obtained by performing eight-way codeword interleaving on eight target codewords. Herein, codeword interleaving may also be referred to as channel interleaving. It should be understood that alignment markers obtained by performing codeword interleaving on multiple target codewords should also be considered to include multiple target codewords. Alternatively, each alignment marker is obtained by performing codeword integration on multiple target codewords. For example, each alignment marker is obtained by performing codeword integration on eight target codewords. Herein, codeword integration may also be referred to as one-way codeword interleaving.

[0112] According to a fifth aspect, an embodiment of the present application provides a data processing method, which is applied to a transmitter and includes the following steps: first, performing first data processing on m first data streams obtained through first forward error correction (FEC) encoding to obtain m second data streams, where m is an integer greater than 1, and each of the second data streams includes at least one first bit sequence, and each of the first bit sequences is

number

number

number

number

number

[0113] In this embodiment of the present application, a first marker is periodically inserted into the outer-code encoded data stream before inner-code encoding is performed.

number

number

number

number

number

number

number

number

number

[0114] In some possible implementations, each of the third data streams includes at least one second bit sequence, each second bit sequence includes P+W bits, and P bits in each second bit sequence are

number

[0115] In some possible implementations, the baud rate value of each of the modulated symbol streams is an integer multiple of 156.25M.

[0116] In some possible implementations, the first marker includes padding bits and / or a status field.

[0117] In some possible implementations, convolutional interleaving is further performed on each first data stream, the convolutional interleaving including delaying the input data stream based on r delay lines, where r is an integer greater than 1, the delay lines include different numbers of storage units, the delay line with the smallest number of storage units includes 0 storage units, the difference between the numbers of storage units in every two adjacent delay lines is Q, and each storage unit is for storing d bits. Bits in the input data stream are input sequentially to the r delay lines based on the order numbers of the r delay lines, where d bits are input to each delay line only once and d bits are output from each delay line only once, and r*d consecutive bits in the data stream output through the convolutional interleaving include d bits output from each delay line, where Q is an integer greater than or equal to 1 and d is an integer greater than or equal to 1.

[0118] In some possible implementations, the input / output switch corresponding to the convolutional interleave is in the 0th delay line whenever f bits are output through the convolutional interleave, where K×b is divisible by f.

[0119] In some possible implementations, r×d×c=K×b, where c is an integer greater than or equal to 1.

[0120] In some possible implementations,

number

[0121] In some possible implementations, N=148, K=140, 5032×e is divisible by b, and

number

[0122] In some possible implementations, b=629×e.

[0123] In some possible implementations, KP4 encoding is used for the first FEC encoding, and Hamming(148,140) is used for the second FEC encoding. Alternatively, KP4 encoding is used for the first FEC encoding, and the second FEC encoding is to perform a bitwise exclusive OR on every two consecutive information bits among the K=140 information bits to obtain 70 bits, and perform Hamming(78,70) encoding on the 70 bits to obtain S=8 parity bits, and the codeword of length 148 bits obtained through the second FEC encoding includes K=140 information bits and S=8 parity bits.

[0124] In some possible implementations, N=127, K=120, 2159×e is divisible by b, and

number

[0125] In some possible implementations, b=2159×e.

[0126] In some possible implementations, KP4 encoding is used for the first FEC encoding, and Hamming(127,120) is used for the second FEC encoding. Alternatively, KP4 encoding is used for the first FEC encoding, and the second FEC encoding is to perform a bitwise exclusive OR on every two consecutive information bits among the K=120 information bits to obtain 60 bits, and perform Hamming(67,60) encoding on the 60 bits to obtain S=7 parity bits, and the 127-bit codeword obtained through the second FEC encoding includes K=120 information bits and S=7 parity bits.

[0127] In some possible implementations, the first data processing further includes scrambling.

[0128] In some possible implementations, the third data processing further includes codeword interleaving, where the codeword interleaving is performed on t codewords to obtain an interleaved sequence including t×N bits, and the ith codeword among the t codewords is a K-bit information sequence B i and the S-bit parity sequence P i , where 0≦i≦t−1, and the interleaved sequence includes a first subsequence of t×K consecutive bits and a second subsequence of t×S consecutive bits, the first subsequence being B0, B1, B2, ..., B t-1 The second subsequence contains t information sequences in total, P0, P1, P2, ..., P t-1 It contains a total of t parity sequences where

[0129] In some possible implementations, the baud rate of the modulated symbol stream is

number

number

[0130] In some possible implementations, N=128, K=120, and the baud rate of the modulated symbol stream is 113.4375 Gbaud.

[0131] In some possible implementations,

number

[0132] In some possible implementations, performing third data processing on the m third data streams to obtain Y modulated symbol streams includes: performing channel interleaving on each group of eight third data streams among the m third data streams to obtain one fourth data stream, and separately modulating the Y fourth data streams to obtain Y modulated symbol streams, to obtain a total of Y fourth data streams.

[0133] In some possible implementations, the first marker in each of the second data streams has a length

number

number

[0134] In some possible implementations,

number

[0135] In some possible implementations, the 48-bit values ​​of the synchronization sequence include 0x9A, 0x4A, 0x26, 0x65, 0xB5, and 0xD9.

[0136] In some possible implementations, the synchronization subsequence 0 included in the 0th secondary data stream in the group of 8 secondary data streams is 010110.

[0137] The synchronization subsequence 1 contained in the first secondary data stream in the group of eight secondary data streams is 011010.

[0138] The synchronization subsequence 2 contained in the second secondary data stream in the group of eight secondary data streams is 100111.

[0139] The synchronization subsequence 3 contained in the third secondary data stream in the group of eight secondary data streams is 010001.

[0140] The synchronization subsequence 4 contained in the fourth secondary data stream in the group of eight secondary data streams is 011010.

[0141] The synchronization subsequence 5 contained in the fifth secondary data stream in the group of eight secondary data streams is 011001.

[0142] The synchronization subsequence 6 contained in the sixth secondary data stream in the group of eight secondary data streams is 000110.

[0143] The synchronization subsequence 7 contained in the seventh secondary data stream in the group of eight secondary data streams is 101011.

[0144] In some possible implementations, one group of eight third data streams among the m third data streams is obtained by performing second FEC encoding on one group of eight second data streams among the m second data streams. The zeroth, first, second, and third second data streams among the group of eight second data streams each include an eight-bit synchronization subsequence. The fourth, fifth, sixth, and seventh second data streams among the group of eight second data streams each include a four-bit synchronization subsequence, and the first two bits and the last two bits in the four-bit synchronization subsequence are two bits apart.

[0145] In some possible implementations, one fourth data stream obtained by performing channel interleaving on the group of eight third data streams includes a 48-bit synchronization sequence, which includes a total of eight synchronization subsequences respectively included in the group of eight second data streams, and the first 24 bits and the last 24 bits in the 48-bit synchronization sequence are separated by 8 bits.

[0146] In some possible implementations, the values ​​of the first 24 bits in the 48-bit long synchronization sequence include 0x9A, 0x4A, and 0x26, and the values ​​of the last 24 bits in the 48-bit long synchronization sequence include 0x65, 0xB5, and 0xD9.

[0147] In some possible implementations, the synchronization subsequence 0 included in the 0th second data stream in the group of 8 second data streams is 01011010.

[0148] The synchronization subsequence 1 contained in the first secondary data stream in the group of eight secondary data streams is 01101001.

[0149] The synchronization subsequence 2 contained in the second secondary data stream in the group of eight secondary data streams is 10010110.

[0150] The synchronization subsequence 3 contained in the third secondary data stream in the group of eight secondary data streams is 01001011.

[0151] The synchronization subsequence 4 contained in the fourth secondary data stream in the group of eight secondary data streams is 0110.

[0152] The synchronization subsequence 5 contained in the fifth secondary data stream in the group of eight secondary data streams is 0110.

[0153] The synchronization subsequence 6 contained in the sixth secondary data stream in the group of eight secondary data streams is 0011.

[0154] The synchronization subsequence 7 contained in the seventh secondary data stream in the group of eight secondary data streams is 1001.

[0155] In some possible implementations, the first marker in each of the second data streams includes a synchronization subsequence that is 48 bits long, and the first 24 bits and the last 24 bits in the synchronization subsequence are separated by 8 bits.

[0156] In some possible implementations, the values ​​of the first 24 bits in the 48-bit long synchronization subsequence include 0x9A, 0x4A, and 0x26, and the values ​​of the last 24 bits in the 48-bit long synchronization subsequence include 0x65, 0xB5, and 0xD9.

[0157] In some possible implementations, N=128 and K=120, and performing channel interleaving on each group of eight third data streams to obtain one fourth data stream includes obtaining one inner codeword of length 128 bits from each of the third data streams in each group of eight third data streams to obtain eight total inner codewords, and obtaining two bits from each of the eight inner codewords in a round-robin manner to obtain 1024 consecutive bits in the fourth data stream.

[0158] In some possible implementations, performing the first data processing on the m first data streams includes separately performing a cyclic shift on the m first data streams.

[0159] In some possible implementations, performing the first data processing on the m first data streams before separately performing cyclic shifts on the m first data streams includes separately performing convolutional interleaving on the m first data streams.

[0160] In some possible implementations, before separately performing cyclic shifts on the m first data streams, the method further includes separately performing convolutional interleaving on the m / 4 input data streams, and dispersing each input convolutionally interleaved data stream to obtain four first data streams, to obtain a total of m first data streams.

[0161] In some possible implementations, before separately performing cyclic shifts on the m first data streams, the method further includes separately performing convolutional interleaving on the m / 8 input data streams, and dispersing each input convolutionally interleaved data stream to obtain 8 first data streams, to obtain a total of m first data streams.

[0162] According to a sixth aspect, an embodiment of the present application provides a data processing method, which is applied to a receiver and includes the following steps: first, fourth data processing is performed on received Y modulated symbol streams to obtain m fourth data streams, where Y is an integer greater than or equal to 1, demodulation is performed on each of the fourth data streams, and a baud rate value of each modulated symbol stream is an integer multiple of a reference clock frequency value; third data processing is performed on m third data streams to obtain Y modulated symbol streams, modulation is performed on each of the modulated symbol streams; second data processing is performed on m second data streams to obtain m third data streams; and first data processing is performed on m first data streams obtained through first forward error correction (FEC) encoding to obtain m second data streams, where m is an integer greater than 1, each of the second data streams includes at least one first bit sequence, and each first bit sequence is

number

number

number

number

number

[0163] In some possible implementations, each of the third data streams includes at least one second bit sequence, each second bit sequence includes P+W bits, and P bits in each second bit sequence are

number

[0164] In some possible implementations, the baud rate value of each of the modulated symbol streams is an integer multiple of 156.25M.

[0165] In some possible implementations, the first marker includes padding bits and / or a status field.

[0166] In some possible implementations, convolutional interleaving is further performed on each first data stream, the convolutional interleaving including delaying the input data stream based on r delay lines, where r is an integer greater than 1, the delay lines include different numbers of storage units, the delay line with the smallest number of storage units includes 0 storage units, the difference between the numbers of storage units in every two adjacent delay lines is Q, and each storage unit is for storing d bits. Bits in the input data stream are input sequentially to the r delay lines based on the order numbers of the r delay lines, where d bits are input to each delay line only once and d bits are output from each delay line only once, and r*d consecutive bits in the data stream output through the convolutional interleaving include d bits output from each delay line, where Q is an integer greater than or equal to 1 and d is an integer greater than or equal to 1.

[0167] In some possible implementations, the input / output switch corresponding to the convolutional interleave is in the 0th delay line whenever f bits are output through the convolutional interleave, where K×b is divisible by f.

[0168] In some possible implementations, r×d×c=K×b, where c is an integer greater than or equal to 1.

[0169] In some possible implementations,

number

[0170] In some possible implementations, N=148, K=140, 5032×e is divisible by b, and

number

[0171] In some possible implementations, b=629×e.

[0172] In some possible implementations, KP4 encoding is used for the first FEC encoding, and Hamming(148,140) is used for the second FEC encoding. Alternatively, KP4 encoding is used for the first FEC encoding, and the second FEC encoding is to perform a bitwise exclusive OR on every two consecutive information bits among the K=140 information bits to obtain 70 bits, and perform Hamming(78,70) encoding on the 70 bits to obtain S=8 parity bits, and the codeword of length 148 bits obtained through the second FEC encoding includes K=140 information bits and S=8 parity bits.

[0173] In some possible implementations, N=127, K=120, 2159×e is divisible by b, and

number

[0174] In some possible implementations, b=2159×e.

[0175] In some possible implementations, KP4 encoding is used for the first FEC encoding, and Hamming(127,120) is used for the second FEC encoding. Alternatively, KP4 encoding is used for the first FEC encoding, and the second FEC encoding is to perform a bitwise exclusive OR on every two consecutive information bits among the K=120 information bits to obtain 60 bits, and perform Hamming(67,60) encoding on the 60 bits to obtain S=7 parity bits, and the 127-bit codeword obtained through the second FEC encoding includes K=120 information bits and S=7 parity bits.

[0176] In some possible implementations, the first data processing further includes scrambling.

[0177] In some possible implementations, the third data processing further includes codeword interleaving, where the codeword interleaving is performed on t codewords to obtain an interleaved sequence including t×N bits, and the ith codeword among the t codewords is a K-bit information sequence B i and the S-bit parity sequence P i , where 0≦i≦t−1, and the interleaved sequence includes a first subsequence of t×K consecutive bits and a second subsequence of t×S consecutive bits, the first subsequence being B0, B1, B2, ..., B t-1 The second subsequence contains t information sequences in total, P0, P1, P2, ..., P t-1 It contains a total of t parity sequences where

[0178] According to a seventh aspect, an embodiment of the present application provides a data processing device, the data processing device including a first data processing unit, a second data processing unit, and a third data processing unit, the first data processing unit configured to perform first data processing on m first data streams obtained through a first forward error correction (FEC) encoding to obtain m second data streams, where m is an integer greater than 1, each of the second data streams including at least one first bit sequence, and each of the first bit sequences is

number

number

number

number

number

[0179] In some possible implementations, each of the third data streams includes at least one second bit sequence, each second bit sequence includes P+W bits, and P bits in each second bit sequence are

number

[0180] In some possible implementations, the baud rate value of each of the modulated symbol streams is an integer multiple of 156.25M.

[0181] In some possible implementations, the first marker includes padding bits and / or a status field.

[0182] In some possible implementations, convolutional interleaving is further performed on each first data stream, the convolutional interleaving including delaying the input data stream based on r delay lines, where r is an integer greater than 1, the delay lines include different numbers of storage units, the delay line with the smallest number of storage units includes 0 storage units, the difference between the numbers of storage units in every two adjacent delay lines is Q, and each storage unit is for storing d bits. Bits in the input data stream are input sequentially to the r delay lines based on the order numbers of the r delay lines, where d bits are input to each delay line only once and d bits are output from each delay line only once, and r*d consecutive bits in the data stream output through the convolutional interleaving include d bits output from each delay line, where Q is an integer greater than or equal to 1 and d is an integer greater than or equal to 1.

[0183] In some possible implementations, the input / output switch corresponding to the convolutional interleave is in the 0th delay line whenever f bits are output through the convolutional interleave, where K×b is divisible by f.

[0184] In some possible implementations, r×d×c=K×b, where c is an integer greater than or equal to 1.

[0185] In some possible implementations,

number

[0186] In some possible implementations, N=148, K=140, 5032×e is divisible by b, and

number

[0187] In some possible implementations, b=629×e.

[0188] In some possible implementations, KP4 encoding is used for the first FEC encoding, and Hamming(148,140) is used for the second FEC encoding. Alternatively, KP4 encoding is used for the first FEC encoding, and the second FEC encoding is to perform a bitwise exclusive OR on every two consecutive information bits among the K=140 information bits to obtain 70 bits, and perform Hamming(78,70) encoding on the 70 bits to obtain S=8 parity bits, and the codeword of length 148 bits obtained through the second FEC encoding includes K=140 information bits and S=8 parity bits.

[0189] In some possible implementations, N=127, K=120, 2159×e is divisible by b, and

number

[0190] In some possible implementations, b=2159×e.

[0191] In some possible implementations, KP4 encoding is used for the first FEC encoding, and Hamming(127,120) is used for the second FEC encoding. Alternatively, KP4 encoding is used for the first FEC encoding, and the second FEC encoding is to perform a bitwise exclusive OR on every two consecutive information bits among the K=120 information bits to obtain 60 bits, and perform Hamming(67,60) encoding on the 60 bits to obtain S=7 parity bits, and the 127-bit codeword obtained through the second FEC encoding includes K=120 information bits and S=7 parity bits.

[0192] In some possible implementations, the first data processing further includes scrambling.

[0193] In some possible implementations, the third data processing further includes codeword interleaving, where the codeword interleaving is performed on t codewords to obtain an interleaved sequence including t×N bits, and the ith codeword among the t codewords is a K-bit information sequence B i and the S-bit parity sequence P i , where 0≦i≦t−1, and the interleaved sequence includes a first subsequence of t×K consecutive bits and a second subsequence of t×S consecutive bits, the first subsequence being B0, B1, B2, ..., B t-1 The second subsequence contains t information sequences in total, P0, P1, P2, ..., P t-1 It contains a total of t parity sequences where

[0194] In some possible implementations, the baud rate of the modulated symbol stream is

number

number

[0195] In some possible implementations, N=128, K=120, and the baud rate of the modulated symbol stream is 113.4375 Gbaud.

[0196] In some possible implementations,

number

[0197] In some possible implementations, the third data processing unit is specifically configured to perform channel interleaving on each group of eight third data streams among the m third data streams to obtain one fourth data stream, and separately modulate the Y fourth data streams to obtain Y modulated symbol streams, to obtain a total of Y fourth data streams.

[0198] In some possible implementations, the first marker in each of the second data streams has a length

number

number

[0199] In some possible implementations,

number

[0200] In some possible implementations, the 48-bit values ​​of the synchronization sequence include 0x9A, 0x4A, 0x26, 0x65, 0xB5, and 0xD9.

[0201] In some possible implementations, the synchronization subsequence 0 included in the 0th secondary data stream in the group of 8 secondary data streams is 010110.

[0202] The synchronization subsequence 1 contained in the first secondary data stream in the group of eight secondary data streams is 011010.

[0203] The synchronization subsequence 2 contained in the second secondary data stream in the group of eight secondary data streams is 100111.

[0204] The synchronization subsequence 3 contained in the third secondary data stream in the group of eight secondary data streams is 010001.

[0205] The synchronization subsequence 4 contained in the fourth secondary data stream in the group of eight secondary data streams is 011010.

[0206] The synchronization subsequence 5 contained in the fifth secondary data stream in the group of eight secondary data streams is 011001.

[0207] The synchronization subsequence 6 contained in the sixth secondary data stream in the group of eight secondary data streams is 000110.

[0208] The synchronization subsequence 7 contained in the seventh secondary data stream in the group of eight secondary data streams is 101011.

[0209] In some possible implementations, one group of eight third data streams among the m third data streams is obtained by performing second FEC encoding on one group of eight second data streams among the m second data streams. The zeroth, first, second, and third second data streams among the group of eight second data streams each include an eight-bit synchronization subsequence. The fourth, fifth, sixth, and seventh second data streams among the group of eight second data streams each include a four-bit synchronization subsequence, and the first two bits and the last two bits in the four-bit synchronization subsequence are two bits apart.

[0210] In some possible implementations, one fourth data stream obtained by performing channel interleaving on one group of eight third data streams includes a 48-bit synchronization sequence, which includes a total of eight synchronization subsequences respectively included in the group of eight second data streams, and the first 24 bits and the last 24 bits in the 48-bit synchronization sequence are separated by 8 bits.

[0211] In some possible implementations, the values ​​of the first 24 bits in the 48-bit long synchronization sequence include 0x9A, 0x4A, and 0x26, and the values ​​of the last 24 bits in the 48-bit long synchronization sequence include 0x65, 0xB5, and 0xD9.

[0212] In some possible implementations, the synchronization subsequence 0 included in the 0th second data stream in the group of 8 second data streams is 01011010.

[0213] The synchronization subsequence 1 contained in the first secondary data stream in the group of eight secondary data streams is 01101001.

[0214] The synchronization subsequence 2 contained in the second secondary data stream in the group of eight secondary data streams is 10010110.

[0215] The synchronization subsequence 3 contained in the third secondary data stream in the group of eight secondary data streams is 01001011.

[0216] The synchronization subsequence 4 contained in the fourth secondary data stream in the group of eight secondary data streams is 0110.

[0217] The synchronization subsequence 5 contained in the fifth secondary data stream in the group of eight secondary data streams is 0110.

[0218] The synchronization subsequence 6 contained in the sixth secondary data stream in the group of eight secondary data streams is 0011.

[0219] The synchronization subsequence 7 contained in the seventh secondary data stream in the group of eight secondary data streams is 1001.

[0220] In some possible implementations, the first marker in each of the second data streams includes a synchronization subsequence that is 48 bits long, and the first 24 bits and the last 24 bits in the synchronization subsequence are separated by 8 bits.

[0221] In some possible implementations, the values ​​of the first 24 bits in the 48-bit long synchronization subsequence include 0x9A, 0x4A, and 0x26, and the values ​​of the last 24 bits in the 48-bit long synchronization subsequence include 0x65, 0xB5, and 0xD9.

[0222] In some possible implementations, N=128 and K=120, and the third data processing unit is specifically configured to obtain one inner code word of length 128 bits from each of the third data streams in each group of eight third data streams to obtain a total of eight inner code words, and to obtain two bits from each of the eight inner code words in a round-robin manner to obtain 1024 consecutive bits in the fourth data stream.

[0223] In some possible implementation forms, the first data processing unit is specifically configured to perform cyclic shifts on the m first data streams separately.

[0224] In some possible implementation forms, before the cyclic shift is performed separately on the m first data streams, the first data processing unit is specifically configured to perform convolutional interleaving separately on the m first data streams.

[0225] In some possible implementations, the data processing apparatus further includes a convolutional interleaving unit and a scattering unit. The convolutional interleaving unit is configured to separately perform convolutional interleaving on the m / 4 input data streams before separately performing cyclic shifts on the m first data streams. The scattering unit is configured to scatter each input convolutionally interleaved data stream to obtain four first data streams, to obtain a total of m first data streams.

[0226] In some possible implementations, the data processing apparatus further includes a convolutional interleaving unit and a scattering unit. The convolutional interleaving unit is configured to separately perform convolutional interleaving on the m / 8 input data streams before separately performing cyclic shifts on the m first data streams. The scattering unit is configured to scatter each input convolutionally interleaved data stream to obtain eight first data streams, to obtain a total of m first data streams.

[0227] According to an eighth aspect, an embodiment of the present application provides a data processing device, the data processing device including a data processing unit and a synchronization unit.

[0228] the data processing unit is configured to perform fourth data processing on the received Y modulated symbol streams to obtain m fourth data streams, where Y is an integer greater than or equal to 1, demodulation is performed on each of the fourth data streams, and a baud rate value of each of the modulated symbol streams is an integer multiple of a reference clock frequency value; perform third data processing on m third data streams to obtain Y modulated symbol streams, where modulation is performed on each of the modulated symbol streams; perform second data processing on m second data streams to obtain m third data streams; and perform first data processing on m first data streams obtained through first forward error correction (FEC) encoding to obtain m second data streams, where m is an integer greater than 1, each of the second data streams including at least one first bit sequence, and each first bit sequence is

number

number

number

number

number

[0229] In some possible implementations, each of the third data streams includes at least one second bit sequence, each second bit sequence includes P+W bits, and P bits in each second bit sequence are

number

[0230] In some possible implementations, the baud rate value of each of the modulated symbol streams is an integer multiple of 156.25M.

[0231] In some possible implementations, the first marker includes padding bits and / or a status field.

[0232] In some possible implementations, convolutional interleaving is further performed on each first data stream, the convolutional interleaving including delaying the input data stream based on r delay lines, where r is an integer greater than 1, the delay lines include different numbers of storage units, the delay line with the smallest number of storage units includes 0 storage units, the difference between the numbers of storage units in every two adjacent delay lines is Q, and each storage unit is for storing d bits. Bits in the input data stream are input sequentially to the r delay lines based on the order numbers of the r delay lines, where d bits are input to each delay line only once and d bits are output from each delay line only once, and r*d consecutive bits in the data stream output through the convolutional interleaving include d bits output from each delay line, where Q is an integer greater than or equal to 1 and d is an integer greater than or equal to 1.

[0233] In some possible implementations, the input / output switch corresponding to the convolutional interleave is in the 0th delay line whenever f bits are output through the convolutional interleave, where K×b is divisible by f.

[0234] In some possible implementations, r×d×c=K×b, where c is an integer greater than or equal to 1.

[0235] In some possible implementations,

number

[0236] In some possible implementations, N=148, K=140, 5032×e is divisible by b, and

number

[0237] In some possible implementations, b=629×e.

[0238] In some possible implementations, KP4 encoding is used for the first FEC encoding, and Hamming(148,140) is used for the second FEC encoding. Alternatively, KP4 encoding is used for the first FEC encoding, and the second FEC encoding is to perform a bitwise exclusive OR on every two consecutive information bits among the K=140 information bits to obtain 70 bits, and perform Hamming(78,70) encoding on the 70 bits to obtain S=8 parity bits, and the codeword of length 148 bits obtained through the second FEC encoding includes K=140 information bits and S=8 parity bits.

[0239] In some possible implementations, N=127, K=120, 2159×e is divisible by b, and

number

[0240] In some possible implementations, b=2159×e.

[0241] In some possible implementations, KP4 encoding is used for the first FEC encoding, and Hamming(127,120) is used for the second FEC encoding. Alternatively, KP4 encoding is used for the first FEC encoding, and the second FEC encoding is to perform a bitwise exclusive OR on every two consecutive information bits among the K=120 information bits to obtain 60 bits, and perform Hamming(67,60) encoding on the 60 bits to obtain S=7 parity bits, and the 127-bit codeword obtained through the second FEC encoding includes K=120 information bits and S=7 parity bits.

[0242] In some possible implementations, the first data processing further includes scrambling.

[0243] In some possible implementations, the third data processing further includes codeword interleaving, where the codeword interleaving is performed on t codewords to obtain an interleaved sequence including t×N bits, and the ith codeword among the t codewords is a K-bit information sequence B i and the S-bit parity sequence P i , where 0≦i≦t−1, and the interleaved sequence includes a first subsequence of t×K consecutive bits and a second subsequence of t×S consecutive bits, the first subsequence being B0, B1, B2, ..., B t-1 The second subsequence contains t information sequences in total, P0, P1, P2, ..., P t-1 It contains a total of t parity sequences where

[0244] In an embodiment of the present application, alignment markers are periodically inserted into the data stream obtained through concatenated FEC encoding. Specifically, P bits are periodically obtained from the data stream obtained through concatenated FEC encoding, and alignment markers of length W bits are inserted therein, so that an alignment marker of length W bits is present every P+W bits in the data stream. Positive integers P and W are selected so that the baud rate value of the modulated symbol data stream is an integer multiple of the Ethernet common reference clock frequency. This simplifies the receiver's clock extraction and synchronization scheme, realizes fast phase locking, and achieves low PLL complexity and small jitter. In addition, P must be a multiple of the code length N of the inner code, in other words, P=N×b, so that synchronization of the inner codeword can be guaranteed after the receiver performs frame synchronization on the received data (i.e., frame synchronization of P+W bits, also called alignment marker lock operation). This simplifies operations such as receiver frame synchronization and inner codeword synchronization, and achieves low implementation complexity. In addition, the input / output switches of the convolutional interleaver and the convolutional deinterleaver are in the top position every time the convolutional interleaver and the convolutional deinterleaver output f bits, and K×b is divisible by f, so that the synchronization performed by the convolutional deinterleaver can be guaranteed during frame synchronization.

[0245] The present application further provides another embodiment for performing inner code encoding after a first marker is periodically inserted into the outer code encoded data stream.

number

number

number

number

number

number

number

number

number

[0246] [Figure 1] 1 is a diagram of a communication system to which an embodiment of the present application may be applied; [Figure 2(a)] FIG. 2 is a diagram of a data transmission process in the communication system shown in FIG. [Figure 2(b)] FIG. 2 is a diagram of another communication system to which an embodiment of the present application may be applied. [Figure 3] 1 is a schematic flowchart of a data processing method according to an embodiment of the present application; [Figure 4(a)] FIG. 2 is a first diagram of a structure of a convolutional interleaver according to an embodiment of the present application; [Figure 4(b)] FIG. 2 is a second diagram of the structure of a convolutional interleaver according to an embodiment of the present application. [Figure 5(a)] FIG. 10 is a diagram of the structure of a third data stream according to an embodiment of the present application. [Figure 5(b)] FIG. 10 is another diagram of the structure of the third data stream according to an embodiment of the present application. [Figure 6] 4 is another schematic flowchart of a data processing method according to an embodiment of the present application; [Figure 7] 4 is yet another schematic flowchart of a data processing method according to an embodiment of the present application; [Figure 8] FIG. 2 is a diagram of the structure of a second data stream according to an embodiment of the present application. [Figure 9] FIG. 10 is a diagram of the structure of a third data stream according to an embodiment of the present application. [Figure 10] FIG. 2 is a diagram of an implementation of inner code encoding according to an embodiment of the present application. [Figure 11] FIG. 10 is a diagram of another implementation of inner code encoding according to an embodiment of the present application. [Figure 12] FIG. 1 is a diagram of the structure of a code word. [Figure 13] FIG. 10 is another diagram of the structure of a codeword. [Figure 14] FIG. 2 is a diagram of an implementation of data processing according to an embodiment of the present application. [Figure 15] 1 is a diagram of an alignment marker structure according to an embodiment of the present application. [Figure 16] FIG. 1 is a diagram of a computer architecture for synchronization. [Figure 17] FIG. 10 is another view of the structure of an alignment marker according to an embodiment of the present application. [Figure 18] FIG. 2 is a diagram of another implementation of data processing according to an embodiment of the present application. [Figure 19] FIG. 2 is a diagram of another implementation of data processing according to an embodiment of the present application. [Figure 20] FIG. 2 is a diagram of another implementation of data processing according to an embodiment of the present application. [Figure 21] FIG. 2 is a diagram of another implementation of data processing according to an embodiment of the present application. [Figure 22(a)] FIG. 2 is a diagram of another implementation of data processing according to an embodiment of the present application. [Figure 22(b)] FIG. 2 is a diagram of another implementation of data processing according to an embodiment of the present application. [Figure 22(c)] FIG. 2 is a diagram of another implementation of data processing according to an embodiment of the present application. [Figure 22(d)] FIG. 1 is a diagram of an implementation of generating alignment markers according to an embodiment of the present application. [Figure 23] FIG. 2 is a diagram of another implementation of data processing according to an embodiment of the present application. [Figure 24] 1 is a diagram of a structure of a first marker according to an embodiment of the present application. [Figure 25] FIG. 2 is a diagram of a structure of a channel interleaved synchronization sequence according to an embodiment of the present application. [Figure 26] FIG. 2 is another view of the structure of the first marker according to an embodiment of the present application. [Figure 27] FIG. 2 is another diagram of the structure of a channel interleaved synchronization sequence according to an embodiment of the present application. [Figure 28] FIG. 2 is a diagram of another implementation of data processing according to an embodiment of the present application. [Figure 29] FIG. 2 is another view of the structure of the first marker according to an embodiment of the present application. [Figure 30] FIG. 2 is a diagram of another implementation of data processing according to an embodiment of the present application. [Figure 31] FIG. 2 is a diagram of another implementation of data processing according to an embodiment of the present application. [Figure 32] FIG. 2 is a diagram of another implementation of data processing according to an embodiment of the present application. [Figure 33] FIG. 2 is a diagram of another implementation of data processing according to an embodiment of the present application. [Figure 34] 2 is a diagram of the structure of a data processing device used in a transmitter according to an embodiment of the present application; [Figure 35] 2 is a diagram of the structure of a data processing device used in a receiver according to an embodiment of the present application; [Figure 36] FIG. 2 is another diagram of the structure of a data processing device according to an embodiment of the present application; DETAILED DESCRIPTION OF THE INVENTION

[0247] Embodiments of the present application provide a data processing method and a data processing device for simplifying a receiver's clock extraction and synchronization scheme, realizing fast phase locking, achieving low PLL complexity and small jitter, and simplifying operations including receiver frame synchronization and inner codeword synchronization, achieving low implementation complexity. It should be noted that in the description, claims, and accompanying drawings of this application, terms such as "first" and "second" are intended to distinguish between similar objects but do not limit a specific order or permutation. It should be understood that the above terms may be interchanged where appropriate, and that the embodiments described in this application may be performed in an order other than that described in this application. In addition, the terms "comprise," "have," and any other variations thereof are intended to cover a non-exclusive inclusion. For example, a process, method, system, product, or device that includes a list of steps or units is not necessarily limited to the explicitly listed steps or units and may include other steps or units not explicitly listed or inherent to the process, method, product, or device.

[0248] FIG. 1 is a diagram of a communication system to which an embodiment of the present application is applied. As shown in FIG. 1, the communication system includes a transmitter device 01, a transmitter processing module 02, a channel transmission medium 03, a receiver processing module 04, and a receiver device 05. For example, the communication system is a data center network. The transmitter device 01 and the receiver device 05 may be devices such as a switch or a router. The transmitter device 01 is also called a host chip located in the transmitter, and the receiver device 05 is also called a host chip located in the receiver, and the channel transmission medium 03 may be an optical fiber. The host chip is sometimes also called a host device. The transmitter device 01 may be connected to the transmitter processing module 02 through an attachment unit interface (AUI), and the receiver device 05 may be connected to the receiver processing module 04 through the AUI. The transmitter processing module 02 and the receiver processing module 04 may each be an optical module, an electronic module, a connector, or another module that processes data in the data transmission process. For example, the processing module may be an 800LR module (an 800LR module, which is a coherent optical module). In addition, the transmitter device 01, the transmitter processing module 02, the channel transmission medium 03, the receiver processing module 04, and the receiver device 05 in the communication system may all support bidirectional or unidirectional transmission, which is not specifically limited herein.

[0249] 2(a) is a diagram of a data transmission process in the communication system shown in FIG. 1. As shown in FIG. 2(a), in the process of transmitting data from a transmitter device 01 to a receiver device 05, the transmitter device 01 is configured to perform outer-code encoding on the data and then transmit the outer-code-encoded data to a transmitter processing module 02. The transmitter processing module 02 is configured to perform inner-code encoding on the outer-code-encoded data to obtain outer-code-encoded and inner-code-encoded data, and transmit the outer-code-encoded and inner-code-encoded data to a channel transmission medium 03. The channel transmission medium 03 is configured to transmit the outer-code-encoded and inner-code-encoded data to a receiver processing module 04. The receiver processing module 04 is configured to perform inner-code decoding on the outer-code-encoded and inner-code-encoded data, and transmit the inner-code-decoded data to a receiver device 05. The receiver device 05 is configured to perform outer-code decoding on the inner-code-decoded data.

[0250] It should be understood that the distinction between the "inside" of the inner code and the "outside" of the outer code is based solely on the distance between the actor performing the operation on the data and the channel transmission medium 03. The actor performing the operation on the inner code is closer to the channel transmission medium, and the actor performing the operation on the outer code is farther from the channel transmission medium. In an embodiment of the present application, data is transmitted from the transmitter device 01 to the channel transmission medium 03 via the transmitter processing module 02, and then transmitted from the channel transmission medium 03 to the receiver device 05 via the receiver processing module 04. The distance traveled by data encoded by the transmitter device 01 to the channel transmission medium 03 is longer than the distance traveled by data encoded by the transmitter processing module 02, and the distance traveled by data decoded by the receiver device 05 to the channel transmission medium 03 is longer than the distance traveled by data decoded by the receiver processing module 04. Thus, data encoded by the transmitter device 01 is referred to as outer-code encoded data, data encoded by the transmitter processing module 02 is referred to as inner-code encoded data, data decoded by the receiver device 05 is referred to as outer-code decoded data, and data decoded by the receiver processing module 04 is referred to as inner-code decoded data. In one possible implementation, both the inner and outer code encodings use FEC encoding schemes to form a concatenated FEC transmission strategy. For example, the transmitter device 01 may perform outer code encoding by using an RS code, and the transmitter processing module 02 may perform inner code encoding by using a Hamming code. In another example, the transmitter device 01 may perform outer code encoding by using an RS code, and the transmitter processing module 02 may perform inner code encoding by using a Bose-Chaudhuri-Hocquenghem (BCH) code. A BCH code for correcting a single error is equivalent to a Hamming code.In another example, the transmitter device 01 may perform outer code encoding by using an RS code, and the transmitter processing module 02 may perform inner code encoding by using a polar code.

[0251] FIG. 2(b) is a diagram of another communication system to which an embodiment of the present application is applied. As shown in FIG. 2(b), the communication system includes a transmitter device 01, a channel transmission medium 03, and a receiver device 05. The transmitter device 01 performs outer code encoding and inner code encoding and transmits the outer code-encoded and inner code-encoded data to the transmission medium 03, and the receiver device 05 performs inner code decoding and outer code decoding on the data received from the transmission medium 03. For example, the communication system is a data center network. The transmitter device 01 and the receiver device 05 may each be a switch, a router, or another device. The transmitter device 01 is also called a host chip in the transmitter, and the receiver device 05 is also called a host chip in the receiver, and the channel transmission medium 03 may be an optical fiber. The host chip is sometimes also called a host device. All the transmitter devices 01, the channel transmission medium 03, and the receiver devices 05 in the communication system can support bidirectional transmission and can also support unidirectional transmission. This is not specifically limited herein.

[0252] It should be noted that the above content is an exemplary description of the application scenario of the data processing method provided in the embodiment of the present application, and does not constitute any limitation on the application scenario of the data processing method. As service requirements change, those skilled in the art can know that the application scenario of the data processing method can be adjusted based on application requirements. This is not listed one by one in the embodiment of the present application.

[0253] 3 is a schematic flowchart of a data processing method according to an embodiment of the present application. It should be understood that this data processing method is applied to a transmitter. For example, the data processing method can be specifically implemented by the transmitter processing module 02 shown in FIG. 2(a).

[0254] 301: Perform first data processing on a plurality of first data streams to obtain m second data streams.

[0255] In this embodiment, all of the multiple first data streams are data streams obtained through the first FEC encoding, i.e., the outer-code-encoded data streams described above. The RS code may be for outer-code encoding, and the outer-code-encoded data stream may include multiple RS codewords. In practical applications, the outer-code encoding may alternatively be performed using a different coding scheme. For simplicity, the RS codeword will be used collectively below to represent the codeword generated through outer-code encoding. Note that in this application, the code length of the outer code is measured in outer-code symbols, and the outer-code symbol may contain one or more bits. For example, the outer code is a KP4 RS(544,514) code, with a code length of 544 symbols, and one RS symbol of the outer code contains 10 bits.

[0256] It should be understood that the first data processing operation includes, but is not limited to, performing second FEC encoding on each first data stream. The second FEC encoding can be understood as the inner code encoding described above. In other words, the second FEC encoding is performed on all m second data streams, where m is an integer greater than 1. Typically, the value of m is 4, 8, 16, 32, or 64. In one example, the inner code encoder performs inner code encoding on every K information bits in each first data stream, specifically adding S parity bits to obtain a total of N-bit inner codewords, i.e., N=K+S, where K≧1 and S≧1. In some scenarios, K is a multiple of 10, and K bits correspond to K / 10 outer code symbols, and the corresponding K / 10 outer code symbols are from K / 10 different outer codewords.

[0257] In some possible implementations, the first data processing operation may further include at least one of operations such as alignment marker lock, lane de-skew, lane reorder, concatenated interleaving, channel interleaving, and scrambling. For example, at least one of operations such as alignment marker lock, lane de-skew, lane reorder, and concatenated interleaving is performed on each of the second data streams before the second FEC encoding. In another example, at least one of operations such as channel interleaving and scrambling is further performed on each of the second data streams after the second FEC encoding.

[0258] It should be noted that after the second FEC encoding, channel interleaving is further performed for each of the second data streams. HM ×N bits in total HM n inner code words obtained through the second FEC encoding (inner code encoding) HM From each of the input data streams, one inner codeword of length N bits is obtained through channel interleaving, and n consecutive inner codewords in the second data stream are HM In order to obtain ×N bits, two bits are obtained as bits in the second data stream from each inner codeword in a round-robin manner. In other words, to obtain one second data stream, the data stream obtained through the second FEC encoding (inner code encoding) is n HM Each channel is processed through channel interleaving. HM Inner codeword interleaving in the direction (n HM It is also called multi-way inner codeword interleaving or inner codeword interleaving.

[0259] It should be noted that in an AWGN channel, the error bits input to the inner code decoder follow a random distribution, but the error bits output from the decoder do not. Therefore, adding a concatenated interleaver between the inner code and the outer code can improve the performance of the overall concatenated FEC solution. The concatenated interleaving operation usually includes convolutional interleaving to achieve low delay. Specific implementations of concatenated interleaving include lane permutation and convolutional interleaving. In lane permutation, data permutation is performed on g input data streams to obtain g data streams obtained through data permutation. Then, convolutional interleaving is performed separately to obtain convolutionally interleaved data streams. Another specific implementation of concatenated interleaving includes lane multiplexing and convolutional interleaving. In lane multiplexing, symbol multiplexing is performed on g input data streams to obtain g symbol-multiplexed data streams, where g is divisible by g. Then, convolutional interleaving is separately performed on the g data streams to obtain g convolutionally interleaved data streams. In this case, g is not equal to g. In other words, the number of first data streams may be the same as or different from the number of second data streams obtained by performing the first data processing on the first data streams. This specifically depends on the actual application scenario and is not limited herein.

[0260] The following describes a possible implementation of the above-mentioned convolutional interleaving.

[0261] A convolutional interleaver that implements convolutional interleaving includes r delay lines, each including a different number of storage units, with the delay line with the smallest number of storage units including 0 storage units, and the difference between the number of storage units in every two adjacent delay lines is Q, where r is an integer greater than 1. Each storage unit is for storing d bits. Bits in each lane data stream are input sequentially to the r delay lines based on the sequence numbers of the r delay lines, with d bits input to each delay line only once and d bits output from each delay line only once. Consecutive r*d bits in the data stream output through convolutional interleaving include d bits output from each delay line. Q is an integer greater than or equal to 1, and d is an integer greater than or equal to 1. For example, the r delay lines each include 0 storage unit, Q storage units, 2Q storage units, ..., (r-1)Q storage units, with each storage unit for storing d bits. In this case, r delay lines correspond to r delay values, respectively, and the delay values ​​include 0 bit, Q×d bits, 2Q×d bits, ..., (r-1)Q×d bits. The more bits included in the delay line delay value, the greater the delay (also called latency) of the delay line relative to the data stream. It should be understood that when the delay line does not include a storage unit, the delay of the delay line is 0 bit, in other words, transparent transmission without delay is implemented.

[0262] The following describes a specific structure of a convolutional interleaver with reference to the accompanying drawings. Figure 4(a) is a first diagram of the structure of a convolutional interleaver according to an embodiment of the present application. As shown in Figure 4(a), the number of storage units in r delay lines is in descending order of the sequence numbers of the r delay lines. Specifically, delay line 0 has (r-1)Q storage units, and Q storage units sequentially decrease for each delay line, and delay line r-1 has 0 storage units. Figure 4(b) is a second diagram of the structure of a convolutional interleaver according to an embodiment of the present application. As shown in Figure 4(b), the number of storage units in r delay lines is in ascending order of the sequence numbers of the r delay lines. Specifically, delay line 0 has 0 storage units, and Q storage units sequentially increase for each delay line, and delay line r-1 has (r-1)Q storage units.

[0263] It should be noted that at the same moment, the input switch and the output switch of the convolutional interleaver are located on the same delay line. After d bits are input to the current delay line only once and d bits are output from the current delay line only once, the switch position is updated to the next delay line to ensure that the bits in each lane data stream are input to the r delay lines sequentially based on the sequence numbers of the r delay lines, and the consecutive r*d bits in the first data stream include d bits output from each delay line. The specific data read / write operations performed by the convolutional interleaver are as follows: d bits are read from the storage unit in the current delay line that is closest to the output port; the d bits stored in each storage unit in the current delay line are transferred to the next storage unit; and then d bits are written to the storage unit in the current delay line that is closest to the input port; then, switching to the next delay line is performed, and the above operations are repeated. The rest can be deduced by analogy.

[0264] It should be understood that when the same parameters r, Q, and d are used, the convolutional interleaving process in Figure 4(a) and the convolutional interleaving process in Figure 4(b) are inverse operations to each other. In other words, when a transmitter processing module uses the convolutional interleaving structure shown in Figure 4(a), the convolutional deinterleaving corresponding to the receiver processing module corresponding to the transmitter processing module uses the structure shown in Figure 4(b). Similarly, when a transmitter processing module uses the convolutional interleaving structure shown in Figure 4(b), the convolutional deinterleaving corresponding to the receiver processing module corresponding to the transmitter processing module uses the structure shown in Figure 4(a).

[0265] It should be noted that in some specific applications, before the inner code encoder performs inner code encoding on every K information bits in each first data stream, a cyclic shift operation is performed, in which a left cyclic shift or a right cyclic shift is performed on every K information bits in order to improve the anti-burst performance of the entire concatenated code.

[0266] 302: Perform second data processing on the m second data streams separately to obtain m third data streams.

[0267] In this embodiment, to obtain a third data stream, an alignment marker is periodically inserted into each of the second data streams. Specifically, P bits are periodically obtained from each of the second data streams, and a W-bit alignment marker is inserted therein, so that a W-bit alignment marker is present every P+W bits in each of the third data streams. It should be understood that the specific form of the alignment marker is not limited herein. For example, the alignment marker added herein may be the same as the alignment marker used in the above-mentioned alignment marker lock. As another example, the alignment marker added herein may be a portion of the alignment marker used in the above-mentioned alignment marker lock. It should be noted that if the alignment marker added herein includes a portion of the alignment marker used in the above-mentioned alignment marker lock, the first data processing operation generally includes scrambling.

[0268] 5(a) is a diagram of a structure of a third data stream according to an embodiment of the present application. As shown in FIG. 5(a), the third data stream includes at least one bit sequence, each bit sequence including P+W bits, where P bits in each bit sequence are from the second data stream and W bits in each bit sequence are added alignment markers. Note that each P+W bit may be referred to as a frame, and the W-bit alignment marker is usually the first W consecutive bits of the frame. In some specific application scenarios, the W-bit alignment marker may also be referred to as a frame header, or a frame alignment signal (FAS), or by another name. Note that the alignment marker may include bits with multiple functions, and specifically, only a portion of the W bits is for a receiver to perform synchronization.

[0269] Note that in the P+W bits of each frame, the W-bit alignment marker may be the first W consecutive bits of the frame, or the W-bit alignment marker may be the last W consecutive bits of the frame.

[0270] 5(b) is another diagram of the structure of a third data stream according to an embodiment of the present application. As shown in FIG. 5(b), the alignment marker includes padding bits and / or a status field. For example, in the W bits, the W0 bit is for the receiver to perform synchronization, and the W1 bit is a padding bit. The padding bits may be preset bits. For example, the W1 bit is all 0. Alternatively, the W1 bit is a random bit. W0+W1≦W. In another example, in the W bits, the W0 bit is for the receiver to perform synchronization, the W1 bit is a padding bit reserved for future development or innovation, and the W2 bit is a status field indicating the FEC status, where W0+W1+W2≦W.

[0271] In some other scenarios, the W-bit alignment marker may not be arranged contiguously. For example, the alignment marker may be divided into multiple marker sub-blocks distributed among the P+W bits. Specifically, the W-bit alignment marker may be divided into h marker sub-blocks distributed among the P+W bits, with the lengths of the h marker sub-blocks being W0, W1, ..., and W2, respectively. h-1 In this case, W0+W1++W h-1 = W. The location of the alignment marker of W bits in one frame of P+W bits is not specifically limited herein.

[0272] 303: Perform third data processing on the m third data streams to obtain Y modulated symbol streams.

[0273] In this embodiment, third data processing including modulation is performed on the m third data streams to obtain Y modulated symbol streams, where Y is an integer greater than or equal to 1.

[0274] It should be noted that in this application, the positive integers P and W are selected so that the baud rate value of the modulated symbol data stream is an integer multiple of the reference clock frequency. This simplifies the implementation of clock extraction and clock synchronization performed by the receiver, realizes fast phase locking, and achieves low PLL complexity and small jitter. It should be understood that the specific value of the reference clock frequency is not limited herein. For example, this value may be the Ethernet common reference clock frequency. In one example, the baud rate value of the modulated symbol data stream is an integer multiple of 156.25M. It should be further understood that in practical applications, a certain error range may be accepted. For example, the baud rate value of the modulated symbol data stream is an integer multiple of 156.25M ± V (ppm), where V may be 20, 50, or 100.

[0275] Furthermore, the positive integer P is selected so that the receiver processing module performs frame synchronization on the received data (i.e., frame synchronization of P+W bits, also called alignment marker lock operation), and based on performing this frame synchronization, inner codeword synchronization and concatenated deinterleaving synchronization can be guaranteed. Specifically, according to the data processing method provided in this application, after the receiver processing module performs the frame synchronization operation, inner codeword synchronization and concatenated deinterleaving synchronization can still be performed without needing to design separate operations for inner codeword synchronization and concatenated deinterleaving synchronization. This is simple to implement. The following describes in detail the value requirements for P and W.

[0276] Considering an 800GbE scenario, the transmitter device performs outer code encoding on the 800GbE service data stream to be transmitted by using KP4 RS (544,514) code to obtain a data stream with an overall rate of 850Gbps, and transmits the data stream to the transmitter processing module through the attachment unit interface 800GAUI after PMA processing. The transmitter processing module performs first data processing including inner code encoding on a plurality of first data streams to obtain m second data streams, and the overall rate of the m second data streams is

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[0277] It should be noted that in a 1.6TbE scenario, the transmitter device performs outer code encoding on the 1.6TbE service data stream to be transmitted by using KP4 RS (544,514) code to obtain a data stream with a rate of 1.7 Tbps overall, and transmits the data stream to the transmitter processing module through the attachment unit interface AUI after PMA processing. The transmitter processing module obtains eight PAM4 modulated symbol streams through the first data processing, the second data processing, and the third data processing, and the baud rate of the PAM4 modulated symbol streams is

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[0278] The reference clock frequency is

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[0279] It should be noted that the parameter combinations N, K, P, and W used in the 800 GbE scenario described above can be used in higher speed scenarios, such as 1.6 TbE. For example, when PAM4 modulation is for 1.6 TbE,

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[0280] Furthermore, when P is a multiple of the code length N of the inner code, in other words, P=N×b, where b is a positive integer, synchronization of the inner codeword can be guaranteed after the receiver processing module performs frame synchronization on the received data (i.e., frame synchronization of P+W bits, also called alignment marker lock operation). Specifically, the receiver processing module can determine the frame boundary based on the alignment marker to complete frame synchronization. Furthermore, since P is a multiple of the code length N of the inner code, the boundary of the inner codeword can be obtained after frame synchronization is completed to complete inner codeword synchronization. In some 800GbE scenarios with PAM4 modulation and a baud rate of 112.5G and 1.6TbE scenarios with PAM4 modulation and a baud rate of 225G,

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[0281] Furthermore, since the transmitter processing module uses concatenated interleaving including convolutional interleaving to ensure convolutional deinterleave synchronization during frame synchronization, the receiver processing module should satisfy the condition that the starting position of each frame (W+P bits) corresponds to the starting positions of the input and output switches of the convolutional deinterleaver, which are usually the topmost positions, for example, the position of delay line 0 shown in Figures 4(a) and 4(b). More specifically, the input and output switches of the convolutional interleaver are in the topmost position every time the convolutional interleaver outputs f bits, and the input and output switches of the convolutional deinterleaver are in the topmost position every time the convolutional deinterleaver outputs f bits, and since K × b is divisible by f, the synchronization performed by the convolutional deinterleaver can be guaranteed during frame synchronization. In one particular scheme, r*d*c=K×b, where r is the number of delay lines in each of the convolutional interleavers and convolutional deinterleavers, d is the number of bits stored in the storage units in each of the convolutional interleavers and convolutional deinterleavers, and c is a positive integer.

[0282] In this way, based on the improvement of the transmitter processing module in this application, as long as the receiver processing module performs frame synchronization of the received data based on the alignment markers added by the transmitter processing module, inner codeword synchronization and convolutional deinterleaving synchronization are also performed, which simplifies operations such as frame synchronization, inner codeword synchronization, and concatenated interleaving synchronization in the receiver and achieves low implementation complexity.

[0283] 6 is another schematic flowchart of a data processing method according to an embodiment of the present application. It should be understood that this data processing method is applied to a receiver. For example, the data processing method can be specifically implemented by the receiver processing module 04 shown in FIG. 2(a).

[0284] 601: Perform fourth data processing on the received Y modulated symbol streams to obtain m fourth data streams.

[0285] It should be understood that the Y modulated symbol streams are from the transmitter processing module 02. For characteristics of the modulated symbol streams and the manner of generating the modulated symbol streams, please refer to the relevant description of the embodiment shown in Figure 3. The details will not be described again here. The receiver processing module 04 performs fourth data processing, including demodulation, on the Y modulated symbol streams to obtain m fourth data streams, and the fourth data processing performed by the receiver processing module 04 is the inverse operation of the third data processing performed by the transmitter processing module 02.

[0286] 602: Perform frame synchronization for each of the fourth data streams based on the alignment markers in each of the fourth data streams.

[0287] To perform frame synchronization, the receiver processing module 04 may perform alignment marker lock for each of the fourth data streams based on the alignment markers added by the transmitter processing module 02 to determine the boundaries of each frame (P+W bits) in the fourth data stream.

[0288] It should be understood that after completing frame synchronization, the receiver processing module 04 further performs fifth data processing on the m fourth data streams. The fifth data processing can be understood as the inverse operation of the first data processing performed by the transmitter processing module 02. For example, the fifth data processing module includes, but is not limited to, inner code decoding and concatenated deinterleaving, and concatenated deinterleaving includes convolutional deinterleaving. The details will not be described one by one again here.

[0289] The following uses a specific application scenario as an example to explain the operations performed by the transmitter processing module 02 and the receiver processing module 04.

[0290] The transmitter processing module 02 performs first data processing, including concatenated interleaving and inner code encoding, on the outer-code-encoded first data stream to obtain m second data streams, where the concatenated interleaving includes convolutional interleaving. Then, W-bit alignment markers are inserted separately into the m second data streams by using P bits as a period to obtain P+W bits, in other words, to obtain m third data streams. Third data processing, including PAM4 modulation, is performed on the third data stream to obtain Y modulated symbol streams, where Y is a positive integer. In an 800 GbE service scenario, Y=4. In a 1.6 TbE service scenario, Y=8. In this application, an 800 GbE service scenario is used as an example to describe the data processing method, and the 800 GbE service scenario can be easily extended to a 1.6 TbE service scenario. The specific implementation of the data processing method in the 1.6TbE service scenario is known to those skilled in the art, and the details will not be described here.

[0291] The receiver processing module 04 performs fourth data processing on the received Y modulated symbol streams to obtain m fourth data streams, where the fourth data processing is the inverse operation of the third data processing and includes PAM4 demodulation. The receiver processing module 04 then performs alignment marker lock on each of the fourth data streams based on the W-bit alignment marker inserted by the transmitter processing module 02 to obtain P+W-bit frame boundaries within the fourth data streams, in other words, to perform frame synchronization. The receiver processing module 04 then performs fifth data processing on the m fourth data streams, where the fifth data processing includes inner code decoding and concatenated deinterleaving, where concatenated deinterleaving includes convolutional deinterleaving. It should be understood that the receiver processing module 04 may further perform alignment marker lock on each received modulated symbol stream based on the W-bit alignment marker inserted by the transmitter processing module 02 and the characteristics of the third data processing to further perform frame synchronization.

[0292] It should be noted that before performing inner code decoding, the receiver processing module 04 needs to determine the boundaries of the inner codeword, in other words, needs to perform inner codeword synchronization. It should further be noted that before performing convolutional deinterleaving, the receiver processing module 04 needs to determine the positions of the input / output switches in the convolutional deinterleaving, in other words, needs to perform convolutional deinterleaving synchronization. Based on the above description, as long as the receiver processing module 04 performs frame synchronization of the received data based on the alignment markers added by the transmitter processing module 02, the inner codeword synchronization and convolutional deinterleaving synchronization are also performed, and no other operations need to be designed for the inner codeword synchronization and concatenated deinterleaving synchronization. This simplifies operations such as frame synchronization, inner codeword synchronization, and convolutional deinterleaving in the receiver, achieving low implementation complexity.

[0293] The following provides several embodiments based on different inner code encoding schemes to illustrate possible values ​​of P and W.

[0294] Embodiment 1: Hamming(128,120) is used for inner code encoding.

[0295] The inner code is a block code, e.g., Hamming(128,120), with information length K=120 bits, codeword length N=128 bits, and the baud rate of the PAM4 modulated symbol stream is

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[0296] When P is a multiple of the code length N of the inner code, i.e., P=128×b, inner codeword synchronization can be guaranteed when the receiver processing module performs frame synchronization on the received data (i.e., frame synchronization of P+W bits, also called alignment marker lock operation), in other words, the boundary of the inner codeword can be obtained, and b is a positive integer. In this case,

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[0297] Given that some typical alignment marker bit lengths W are 48, 56, 64, and 120, and N=128, optional combinations of positive integers a, b, and P corresponding to W and the corresponding baud rates are listed in Table 1 below.

[0298] [Table 1A] [Table 1B]

[0299] At high baud rates, the power consumption of the optical module is usually high. Considering baud rates lower than 114 Gbaud, the preferred combinations of positive integers a, b, and P and the corresponding baud rates are listed in Table 2 below.

[0300] [Table 2]

[0301] The length of the inner codeword information is K=120 bits, and one RS symbol of the outer KP4 code contains 10 bits. For the convolutional interleaver between the inner code encoding and the outer code encoding, there is a convolutional interleaver whose input / output switch is in the top position whenever the convolutional interleaver outputs 120 bits. For example, the number r of delay lines of the convolutional interleaver is 3, and each storage unit of the convolutional interleaver stores d=40 bits. In another example, the number r of delay lines of the convolutional interleaver is 6, and each storage unit of the convolutional interleaver stores d=20 bits. In this case, when the receiver processing module performs frame synchronization on the received data (i.e., frame synchronization of P+W bits, also called alignment marker lock operation), inner codeword synchronization can be guaranteed; in other words, the boundary of the inner codeword can be obtained. In addition, convolutional deinterleaving synchronization can be further ensured, specifically the positions of the input and output switches of the convolutional deinterleaving are obtained, which simplifies the implementation of the receiver processing module.

[0302] It should be noted that the 800GbE scenario is considered in the above embodiment, and the 800GbE service scenario can be easily extended to the 1.6TbE scenario. For example, the parameter combinations of W, P, and b in Table 1 can be directly used in the 1.6TbE scenario. For example, PAM4 modulation is also applied to the 1.6TbE scenario, and the baud rate used in the 1.6TbE scenario is twice that in the 800GbE scenario.

[0303] Embodiment 2: Hamming(170,160) is used for inner code encoding.

[0304] The inner code is a block code, e.g., Hamming(170,160), with information length K=160 bits, codeword length N=170 bits, and the baud rate of the PAM4 modulated symbol stream is

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[0305] When P is a multiple of the code length N of the inner code, in other words, when P=170×b, inner codeword synchronization can be guaranteed when the receiver processing module performs frame synchronization on the received data (i.e., frame synchronization of P+W bits, also called alignment marker lock operation), in other words, the boundary of the inner codeword can be obtained, and b is a positive integer. In this case,

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[0306] Given that some typical alignment marker bit lengths W are 48, 56, 64, and 120, and N=170, optional combinations of positive integers a, b, and P corresponding to W and the corresponding baud rates are listed in Table 3 below.

[0307] [Table 3]

[0308] At high baud rates, the power consumption of the optical module is usually high. Considering baud rates lower than 114 Gbaud, the preferred combinations of positive integers a, b, and P and the corresponding baud rates are listed in Table 4 below.

[0309] [Table 4]

[0310] The length of the inner codeword information is K=160 bits, and one RS symbol of the outer KP4 code contains 10 bits. For the convolutional interleaver between the inner code and the outer code, there is a convolutional interleaver whose input / output switch is in the top position whenever the convolutional interleaver outputs 160 bits. For example, the number r of delay lines of the convolutional interleaver is 4, and each storage unit of the convolutional interleaver stores d=40 bits. In another example, the number r of delay lines of the convolutional interleaver is 8, and each storage unit of the convolutional interleaver stores d=20 bits. In this case, when the receiver processing module performs frame synchronization on the received data (i.e., frame synchronization of P+W bits, also called alignment marker lock operation), inner codeword synchronization can be guaranteed; in other words, the boundary of the inner codeword can be obtained. In addition, convolutional deinterleaving synchronization can be further ensured, specifically the positions of the input and output switches of the convolutional deinterleaving are obtained, which simplifies the implementation of the receiver processing module.

[0311] It should be noted that the 800GbE scenario is considered in the above embodiment, and the 800GbE service scenario can be easily extended to the 1.6TbE scenario. For example, the parameter combinations of W, P, and b in Table 3 can be directly used in the 1.6TbE scenario. For example, PAM4 modulation is also applied to the 1.6TbE scenario, and the baud rate used in the 1.6TbE scenario is twice that in the 800GbE scenario.

[0312] Embodiment 3: Hamming(144,136) is used for inner code encoding.

[0313] The inner code is a block code, e.g., Hamming(144,136), with information length K=136 bits, codeword length N=144 bits, and the baud rate of the PAM4 modulated symbol stream is

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[0314] When P is a multiple of the code length N of the inner code, in other words, when P=144×b, inner codeword synchronization can be guaranteed when the receiver processing module performs frame synchronization on the received data (i.e., frame synchronization of P+W bits, also called alignment marker lock operation), in other words, the boundary of the inner codeword can be obtained, and b is a positive integer.

number

[0315] Given that some typical alignment marker bit lengths W are 48, 56, 64, and 120, and N=144, optional combinations of positive integers a, b, and P corresponding to W and the corresponding baud rates are listed in Table 5 below.

[0316] [Table 5A] [Table 5B] [Table 5C] [Table 5D]

[0317] At high baud rates, the power consumption of the optical module is usually high. Considering baud rates lower than 114 Gbaud, the preferred combinations of positive integers a, b, and P and the corresponding baud rates are listed in Table 6 below.

[0318] [Table 6A] [Table 6B]

[0319] Note that the length of the inner codeword information is K = 136 bits, and one RS symbol of the outer KP4 code contains 10 bits. For the convolutional interleaver between the inner and outer codes, there is a convolutional interleaver whose input / output switches are in the top position whenever the convolutional interleaver outputs r*d = 160 bits. For example, the number of delay lines r of the convolutional interleaver is 4, and each storage unit of the convolutional interleaver stores d = 40 bits. In another example, the number of delay lines r of the convolutional interleaver is 8, and each storage unit of the convolutional interleaver stores d = 20 bits. Considering that the least common multiple of the inner code information lengths K = 136 and 160 is 2720 = 136 × 20, the input / output switches of the convolutional interleaver are in the top position whenever the convolutional interleaver outputs 2720 = 17 × 160 bits, and the output 2720 bits are used as the information bits of the 20 inner codes. In other words, when b is a multiple of 20, 2720 = r*d*c = K*b, where c is a positive integer. In this case, when the receiver processing module performs frame synchronization (i.e., P+W bit frame synchronization, also called alignment marker lock operation) on the received data, inner codeword synchronization can be guaranteed, in other words, the boundary of the inner codeword can be obtained. In addition, convolutional deinterleaving synchronization can be further guaranteed, specifically, the positions of the input and output switches of the convolutional deinterleaving can be obtained. The corresponding combinations of positive integers a, b, and P and the corresponding baud rates for each combination are listed in Table 7 below.

[0320] [Table 7]

[0321] Note that the length of the inner codeword information is K = 136 bits, and one RS symbol of the outer KP4 code contains 10 bits. For the convolutional interleaver between the inner code and the outer code, there is a convolutional interleaver whose input / output switches are in the top position whenever the convolutional interleaver outputs r*d = 140 bits. For example, the number of delay lines r of the convolutional interleaver is 7, and each storage unit of the convolutional interleaver stores d = 20 bits. Considering that the least common multiple of the inner code information lengths K = 136 and 140 is 4760 = 136 × 35, the input / output switches of the convolutional interleaver are in the top position whenever the convolutional interleaver outputs 4760 = 34 × 140 bits, and the output 4760 bits are used as 35 inner code information bits. Specifically, when b is a multiple of 35, inner codeword synchronization can be guaranteed when the receiver processing module performs frame synchronization on the received data (i.e., frame synchronization of P+W bits, also called alignment marker lock operation), in other words, the boundary of the inner codeword can be obtained. In addition, convolutional deinterleaving synchronization can be further guaranteed, specifically, the positions of the input and output switches of the convolutional deinterleaving can be obtained. The corresponding combinations of positive integers a, b, and P and the corresponding baud rates for the combinations are listed in Table 8 below.

[0322] [Table 8]

[0323] It should be noted that the 800GbE scenario is considered in the above embodiments, and the 800GbE service scenario can be easily extended to the 1.6TbE scenario. For example, the parameter combinations of W, P, and b in Table 5 can be directly used in the 1.6TbE scenario. For example, PAM4 modulation is also applied to the 1.6TbE scenario, and the baud rate used in the 1.6TbE scenario is twice that in the 800GbE scenario.

[0324] Embodiment 4: An FEC code with information length K=140 bits and codeword length N=148 bits is used for inner code encoding.

[0325] The inner code is an FEC code, for example, a Hamming (148,140) code, where the information length is K=140 bits and the codeword length is N=148 bits. In another example, the encoding method shown in Figure 10 is used, where 140 bits of data to be encoded are represented by B[139:0], and a bitwise exclusive OR is performed on every two consecutive bits in the 140 bits of data to obtain 1 bit of data C[i], resulting in 70 bits of data in total, represented by C[69:0], where C[i]=B[2*i]^B[2*i+1], where 0≦i≦69. Then, Hamming (78,70) encoding is performed on C[69:0] as information data to obtain 8 bits of parity data represented by P[7:0]. Finally, the total 148 bits of B[139:0] and P[7:0] are concatenated to form the output of the inner code encoding, represented by D[147:0], where D[139:0] comes from B[139:0] and D[147:140] comes from P[7:0].

[0326] The baud rate of the PAM4 modulated symbol stream is

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[0327] When P is a multiple of the code length N of the inner code, in other words, when P=148×b, inner codeword synchronization can be guaranteed when the receiver processing module performs frame synchronization on the received data (i.e., frame synchronization of P+W bits, also called alignment marker lock operation), in other words, the boundary of the inner codeword can be obtained, and b is a positive integer.

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[0328] Given that some typical alignment marker bit lengths W are 48, 56, 64, and 120, and N=148, optional combinations of positive integers a, b, and P corresponding to W and the corresponding baud rates are listed in Table 9 below.

[0329] [Table 9]

[0330] At high baud rates, the power consumption of the optical module is usually high. Considering baud rates lower than 114 Gbaud, the preferred combinations of positive integers a, b, and P and the corresponding baud rates are listed in Table 10 below.

[0331] [Table 10]

[0332] The length of the inner codeword information is K=140 bits, and one RS symbol of the outer KP4 code contains 10 bits. For the convolutional interleaver between the inner code and the outer code, there is a convolutional interleaver whose input / output switches are in the top position whenever the convolutional interleaver outputs 140 bits. For example, the number of delay lines r of the convolutional interleaver is 7, and each storage unit of the convolutional interleaver stores d=20 bits. In this case, when the receiver processing module performs frame synchronization on the received data (i.e., frame synchronization of P+W bits, also known as alignment marker lock operation), inner codeword synchronization can be guaranteed; in other words, the boundary of the inner codeword can be obtained. In addition, convolutional deinterleaving synchronization can be further guaranteed; specifically, the positions of the input and output switches of the convolutional deinterleaving can be obtained, simplifying the implementation of the receiver processing module.

[0333] It should be noted that the 800GbE scenario is considered in the above embodiments, and the 800GbE service scenario can be easily extended to the 1.6TbE scenario. For example, the parameter combinations of W, P, and b in Table 9 can be directly used in the 1.6TbE scenario. For example, PAM4 modulation is also applied to the 1.6TbE scenario, and the baud rate used in the 1.6TbE scenario is twice that in the 800GbE scenario.

[0334] In some 800GbE scenarios with PAM4 modulation and 112.5G baud rate, and in 1.6TbE scenarios with PAM4 modulation and 225G baud rate,

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[0335] Embodiment 5: An FEC code with information length K=120 bits and codeword length N=128 bits is used for inner code encoding.

[0336] The inner code is an FEC code, for example, a Hamming (128,120) code, where the information length is K=120 bits and the codeword length is N=128 bits. In another example, 120 bits of data to be encoded are represented by B[119:0]. To obtain 1 bit of data C[i], a bitwise exclusive OR is performed on every two consecutive bits of the 120 bits of data, resulting in a total of 60 bits of data, represented by C[59:0]. C[i]=B[2*i]^B[2*i+1], where 0≦i≦59. Then, Hamming (68,60) encoding is performed on C[59:0] as information data to obtain 8 bits of parity data represented by P[7:0]. Finally, the 128 bits of B[119:0] and P[7:0] are concatenated together to form the output of the inner code encoding, which is represented by D[127:0]. D[119:0] comes from B[119:0] and D[127:120] comes from P[7:0].

[0337] Considering the 800GE scenario and PAM4 modulation is applied, four PAM-modulated symbol streams are obtained through data processing. When the periodically inserted alignment markers of length W bits are not considered, the baud rate of the PAM4-modulated symbol stream is

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[0338] In embodiment 1

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[0339] [Table 11]

[0340] 14 is a diagram of an implementation form of data processing according to an embodiment of the present application. Referring to FIG. 14, the following describes a specific data processing procedure.

[0341] The 32 data streams obtained through the first FEC encoding are subjected to inner code encoding to obtain 32 inner code-encoded data streams, specifically, inner code encoding is performed on every K=120 information bits in each data stream, specifically, S=8 parity bits are added to obtain a total of N=128-bit inner codewords.

[0342] To obtain one second data stream, channel interleaving is performed on every eight coded data streams among the 32 inner code coded data streams, resulting in m=4 second data streams in total. See Figure 14. In the 800GE scenario, the data processing includes four data partial processes, namely, data partial process 0, data partial process 1, data partial process 2, and data partial process 3 in Figure 14. Each data partial process includes one channel interleaving operation. To obtain eight inner code words in total, n input data streams are interleaved. HM From each of the 8 coded data streams, one inner codeword of length 128 bits is obtained through channel interleaving, and 2 bits are obtained from each inner codeword as bits in the second data stream in a round-robin manner to obtain 1024 consecutive bits in the second data stream. Channel interleaving is also called eight-way Hamming codeword interleaving or inner codeword interleaving.

[0343] Alignment markers are periodically inserted into each of the m=4 second data streams to obtain m=4 third data streams. Specifically, P bits are periodically obtained from each of the second data streams and alignment markers of length W bits are inserted, so that an alignment marker of length W bits is present every P+W bits in each of the third data streams.

[0344] Third data processing including PAM4 modulation is performed on the m=4 third data streams to obtain Y=4 modulated symbol streams.

[0345] FIG. 15 is a diagram of the structure of an alignment marker according to an embodiment of the present application. In this embodiment, a specific structure of a periodically inserted alignment marker with a length of W=384 bits is described by using W=3×128=384 and P=1088×W=417792 as an example. As shown in FIG. 15(a), the 384-bit alignment marker includes at least one group of frame synchronization sequences for a receiver to perform synchronization. The group of frame synchronization sequences includes a total of 48 bits and is distributed into two frame synchronization subsequences, namely, frame synchronization subsequence 1 and frame synchronization subsequence 2 in FIG. 15(b). Each frame synchronization subsequence includes 24 bits, and the two frame synchronization subsequences are not consecutive within the 1024-bit alignment marker and are separated by 8 bits (1 byte). The specific structure of the frame synchronization subsequence is shown in FIG. 15(b). In this specification, the interval between two consecutive bits is defined as 0 bits.

[0346] In some specific applications, specific values ​​of the 24-bit frame synchronization subsequence 1 are 0x9A, 0x4A, and 0x26, and specific values ​​of the 24-bit frame synchronization subsequence 2 are 0x65, 0xB5, and 0xD9. Note that frame synchronization subsequence 1 (or frame synchronization subsequence 2) is transmitted in the sequence 0x9A, 0x4A, and 0x26 (or 0x65, 0xB5, and 0xD9). More specifically, for frame synchronization subsequence 1, 0x9A is the first byte transmitted, and 0x26 is the next byte transmitted. In addition, for the 8 bits of a byte, the LSB is transmitted first, and the MSB is transmitted last. For example, the 8 bits corresponding to 0x9A are transmitted from left to right in the bit sequence 01011100.

[0347] FIG. 16 is a diagram of a computer architecture for synchronization. It should be noted that, since two frame synchronization subsequences in a group of frame synchronization sequences are separated by 8 bits (1 byte) in the 1024-bit alignment marker, when performing frame synchronization, the receiver can reuse the implementation architecture of the synchronization hardware in the existing 100GE 802.3bj standard and the 400GE 802.3bs standard. (a) of FIG. 16 shows the relevant computer architecture for alignment marker synchronization in the 100GE 802.3bj standard. (b) of FIG. 16 shows the relevant computer architecture for alignment marker synchronization in the 400GE 802.3bs standard. (c) of FIG. 16 shows the relevant computer architecture for frame synchronization in the present invention. It can be seen that the implementation architecture of the synchronization hardware in the existing 100GE 802.3bj standard and the 400GE 802.3bs standard can be reused for the structure of the frame synchronization sequence, which facilitates implementation.

[0348] Embodiment 6 17 is another diagram of the structure of an alignment marker according to an embodiment of the present application. Based on embodiment 5, it is assumed that W=8×128=1024 and P=1088×W=1114112. In a data processing operation, P bits are periodically obtained from each of the second data streams, and an alignment marker of length W bits is inserted. The alignment marker includes multiple groups of frame synchronization sequences for the receiver to perform synchronization. As shown in (a) and (b) of FIG. 17, the alignment marker includes three groups of frame synchronization sequences for the receiver to perform synchronization. As shown in (c) of FIG. 17, the alignment marker includes two groups of frame synchronization sequences for the receiver to perform synchronization.

[0349] Note that groups of frame synchronization sequences may or may not be spaced apart. As shown in (a) of Figure 17, within an alignment marker of length W = 1024 bits, three groups of frame synchronization sequences are not spaced apart. As shown in (b) of Figure 17, within an alignment marker of length W = 1024 bits, two adjacent frame synchronization sequences within a group of three frame synchronization sequences are spaced apart by 8 bits. Note that the number of bits by which two adjacent frame synchronization sequences within a group of three frame synchronization sequences are spaced apart within an alignment marker of length W = 1024 bits can be another positive integer that is an integer multiple of 8.

[0350] Note that the specific values ​​of multiple groups of the frame synchronization sequence may be the same or different. As shown in (a) of Figure 17, the values ​​of the three groups of the frame synchronization sequence are the same, and the values ​​of the 48 bits in each group of the frame synchronization sequence are 0x9A, 0x4A, 0x26, 0x65, 0xB5, and 0xD9. As shown in (b) of Figure 17, in the three groups of the frame synchronization sequence, the values ​​of the first group of the frame synchronization sequence and the values ​​of the second group of the frame synchronization sequence are the same, and the values ​​of the 48 bits in each group of the frame synchronization sequence are 0x9A, 0x4A, 0x26, 0x65, 0xB5, and 0xD9. The values ​​of the third group of the frame synchronization sequence are different from the values ​​of the first and second groups of the frame synchronization sequence, and the values ​​of the 48 bits in the third group of the frame synchronization sequence are 0x01, 0x71, 0xF3, 0xFE, 0x8E, and 0x0C. As shown in Figure 17(c), the values ​​of the two groups of frame synchronization sequences are different: the values ​​of the 48 bits in the first frame synchronization sequence are 0x9A, 0x4A, 0x26, 0x65, 0xB5, and 0xD9, and the values ​​of the 48 bits in the second frame synchronization sequence are 0x01, 0x71, 0xF3, 0xFE, 0x8E, and 0x0C.

[0351] Embodiment 7 18 is a diagram of another implementation of data processing according to an embodiment of the present application. Based on embodiment 5, considering a 1.6TE scenario and PAM4 modulation is applied, 8 PAM-modulated symbol streams are obtained through data processing. When the periodically inserted alignment markers of length W bits are not considered, the baud rate of the PAM4-modulated symbol stream is

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[0352] In embodiment 1

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[0353] Embodiment 8 19 is a diagram of another implementation form of data processing according to an embodiment of the present application. According to embodiment 5, before the inner code encoder performs inner code encoding on every K=120 information bits in each first data stream, a cyclic shift operation is further performed. As shown in FIG. 19, in the cyclic shift operation, a right cyclic shift is performed on every K=120 information bits to improve the anti-burst performance of the entire concatenated code.

[0354] Embodiment 9 20 is a diagram of another implementation of data processing according to an embodiment of the present application. Based on embodiment 5, before the inner code encoder performs inner code encoding on every K=120 information bits in each first data stream, a convolutional interleaving operation is further performed. As shown in FIG. 20, first, convolutional interleaving is performed on every 8 first data streams among the 32 first data streams, and then cyclic shifting is performed on every K=120 bits, and inner code encoding and channel interleaving (inner codeword interleaving) are sequentially performed to obtain one second data stream in total. Since convolutional interleaving is further performed before inner code encoding, the performance of concatenated codes in AWGN is improved.

[0355] Embodiment 10 21 is a diagram of another implementation of data processing according to an embodiment of the present application. Based on embodiment 9, every two first data streams among eight first data streams are grouped as two input data streams for data partial processing. In each data partial processing, convolutional interleaving is performed separately on the two first data streams to obtain two convolutionally interleaved data streams. Data distribution is performed on each convolutionally interleaved data stream to obtain four distributed data streams, resulting in a total of eight distributed data streams. Data distribution is performed with a granularity of α0 bits. As shown in Figure 21, when α0 bits in the convolutionally interleaved data stream are grouped together, for a total of four groups of 4 x α0 consecutive bits, the 0th group of α0 bits is transmitted to the 0th data stream of the four distributed data streams, the 1st group of α0 bits is transmitted to the 1st data stream of the four distributed data streams, the 2nd group of α0 bits is transmitted to the 2nd data stream of the four distributed data streams, and the 3rd group of α0 bits is transmitted to the 3rd data stream of the four distributed data streams. Typically, the granularity of the distributed bits is α0 = 120.

[0356] In the 800GE scenario, it should be noted that the data processing includes four data partial processes, as shown in Figure 21. The data stream inputs of each data partial process are two first data streams. The two first data streams correspond to a rate of approximately 200 Gbits per second, in other words, each first data stream corresponds to a rate of approximately 100 Gbits per second. Correspondingly, the distributed data stream corresponds to a rate of approximately 25 Gbits per second.

[0357] It should be further noted that when the granularity of the scattering bits is α0=120, the data processing shown in FIG. 21 can be described as follows: Convolutional interleaving is performed separately on the two first data streams to obtain two total convolutionally interleaved data streams; A group of 4 bits is obtained from each convolutionally interleaved data stream, and the length of each bit group is 120 bits; Cyclic shifting and inner code encoding are performed separately on each bit group to obtain four inner codewords; A group of 8 bits is obtained from the two convolutionally interleaved data streams, and a total of 8 inner codewords are obtained separately through cyclic shifting and inner code encoding; and then channel interleaving is performed to obtain 1024 bits in the second data stream.

[0358] It should be noted that in some specific application scenarios with low latency requirements, the convolutional interleaving in FIG. 21 may be removed and the convolutional interleaving operation is bypassed.

[0359] It should be noted that in the 1.6TE scenario, the data process includes eight data sub-processes, and the data stream input of each data sub-process is two first data streams. The two first data streams correspond to a rate of approximately 200 Gbits per second, or in other words, each first data stream corresponds to a rate of approximately 100 Gbits per second. Correspondingly, the distributed data stream corresponds to a rate of approximately 25 Gbits per second.

[0360] Embodiment 11 FIG. 22(a) is a diagram of another implementation of data processing according to an embodiment of the present application. Based on embodiment 9, four first data streams are each used as an input data stream for data partial processing. In each data partial processing, convolutional interleaving is performed on the first data stream to obtain one convolutionally interleaved data stream. Data distribution is performed on the convolutionally interleaved data stream to obtain eight distributed data streams. The data distribution is performed with a granularity of α0 bits. As shown in FIG. 22(a), when α0 bits in the convolutionally interleaved data stream are grouped together, for a total of eight groups of 8×α0 consecutive bits, the 0th group of α0 bits is transmitted to the 0th data stream among the eight distributed data streams, the first group of α0 bits is transmitted to the first data stream among the eight distributed data streams, ..., the seventh group of α0 bits is transmitted to the seventh data stream among the eight distributed data streams. Typically, the granularity of the distributed bits is α0=120.

[0361] In the 800GE scenario, as shown in Fig. 22(a), it should be noted that the data processing includes four data sub-processes. The data stream input of each data sub-process is one first data stream, and the first data stream corresponds to a rate of about 200 Gbit / s. Correspondingly, the distributed data stream corresponds to a rate of about 25 Gbit / s.

[0362] It should be further noted that when the granularity of the dispersion bits is α0=120, the data processing shown in FIG. 22(a) can be described as follows: convolutional interleaving is performed on each first data stream to obtain one convolutionally interleaved data stream; 8-bit groups are obtained from the convolutionally interleaved data stream, and the length of each bit group is 120 bits; cyclic shifting and inner code encoding are performed separately on each bit group to obtain 8 inner code words, and then channel interleaving is performed to obtain 1024 bits in the second data stream.

[0363] It should be noted that in some specific application scenarios with low-delay requirements, the convolutional interleaving in Figure 22 may be removed, and the convolutional interleaving operation may be bypassed. Furthermore, to achieve even lower delay, lower complexity, and lower power consumption, in some possible scenarios, the cyclic shift operation and / or the channel interleaving (inner codeword interleaving) operation may also be bypassed. When the channel interleaving (inner codeword interleaving) operation is bypassed, one-way Hamming codeword interleaving may be performed on the eight coded data streams. This is equivalent to performing codeword merging on the eight coded data streams.

[0364] FIG. 22(b) is a diagram of another implementation of data processing according to an embodiment of the present application. Each of four first data streams is an input data stream for data partial processing. The difference from the implementation shown in FIG. 22(a) lies in the following: As shown in FIG. 22(b), in each data partial processing, convolutional interleaving is not performed on the first data stream, and data distribution is directly performed to obtain eight distributed data streams. Data distribution is performed with a granularity of α0 bits. Specifically, when α0 bits in the first data stream without data distribution are grouped together, for a total of eight groups of 8×α0 consecutive bits, the 0th group of α0 bits is sent to the 0th distributed data stream, the first group of α0 bits is sent to the first distributed data stream, ..., the seventh group of α0 bits is sent to the seventh distributed data stream. Typically, the granularity of distribution bits is α0=120.

[0365] 22(c) is a diagram of another implementation of data processing according to an embodiment of the present application. In one possible implementation, the implementation of FIG. 22(b) is simplified to obtain the implementation shown in FIG. 22(c), which is equivalent to the implementation of FIG. 22(b). Specifically, as shown in FIG. 22(c), in each data partial processing, inner code encoding is performed on the first data stream to obtain a second data stream, alignment markers are periodically inserted into the second data stream to obtain a third data stream, and PAM4 modulation is performed to obtain a modulated symbol stream.

[0366] It should be noted that after the modulated symbol stream obtained through the data processing shown in Figure 22(b) or Figure 22(c) is transmitted through an actual channel, the received symbol stream is obtained at the receiver, and PAM4 demodulation is performed to obtain a demodulated data stream. In one example, in a data processing method of the receiver, frame synchronization is performed by using a frame synchronization sequence in the alignment marker to obtain the start position and inner code boundary of each frame, and then inner code soft decision decoding is performed to obtain an inner code decoded data stream, and the data stream is sent to the host device for outer code KP4 decoding. The uncorrected bit error rate of the entire concatenated system can reach approximately 3.3E-3.

[0367] In another example, in a data processing method of a receiver, frame synchronization is performed by using a frame synchronization sequence in an alignment marker to obtain the start position and inner code boundary of each frame, and then inner code hard-decision decoding is performed to obtain an inner code decoded data stream, and the data stream is sent to a host device for outer code KP4 decoding. The uncorrected bit error rate of the entire concatenated system can reach approximately 6E-4. It should be understood that applying hard-decision decoding as inner code decoding achieves low decoding complexity.

[0368] In yet another example, in some scenarios with good link quality, the receiver may perform frame synchronization by using the frame synchronization sequence in the alignment marker to obtain the starting position of each frame and the inner code boundary, and then bypass inner code decoding. Specifically, the receiver directly removes the parity bits in each received inner codeword in the data stream and keeps only the information bits, then performs frame synchronization by using the frame synchronization sequence in the alignment marker to obtain the starting position of each frame, removes the alignment marker, and sends the processed data stream to the host device for outer code KP4 decoding. In this case, the receiver has advantages such as low delay and low complexity.

[0369] In some possible implementations, the length W of the alignment marker is an integer multiple of the length N of the inner codeword, and a specific pattern of the alignment marker is one or more inner codewords. In one example, the inner codeword included in the alignment marker is obtained by performing inner code encoding on the alignment marker information, and the inner code encoding is the above-mentioned second FEC encoding. The length of the inner codeword obtained by performing inner code encoding on the alignment marker information is the same as the length of the inner codeword obtained through the second FEC encoding in the second data stream. For ease of explanation, the inner codeword included in the alignment marker may also be referred to as a target codeword, and specifically, the length of the target codeword is the same as the length of the inner codeword in the above-mentioned second data stream. Specifically, each target codeword is obtained by performing inner code encoding on alignment marker information including K target bits, and the target codeword includes N bits, and the N bits include the K target bits and S parity bits obtained through encoding.

[0370] 22(d) is a diagram of an implementation of generating alignment markers according to an embodiment of the present application. As shown in FIG. 22(d), two possible ways of generating alignment markers are provided.

[0371] Using the alignment marker generating method 0 as an example, the length W of the alignment marker is an integer multiple of the length N of the target codeword, in other words, W = b0 × N. b0 is an integer multiple of 8. For example, W = 8 × 128 = 1024. In this case, one or more target codewords may be selected as specific patterns of the alignment marker. Optionally, each alignment marker is obtained by performing codeword interleaving on multiple target codewords. Specifically, inner-code encoding is performed on alignment marker information including b0 × K target bits to obtain b0 target codewords, and eight-way codeword interleaving is performed on the b0 target codewords to obtain the alignment markers. It should be understood that the alignment markers obtained by performing codeword interleaving on multiple target codewords should also be considered to include multiple target codewords.

[0372] Using the method 1 for generating alignment markers as an example, the length W of the alignment marker is an integer multiple of the length N of the target codeword, in other words, W = b1 × N. W = 3 × 128 = 384. In another example, W = 8 × 128 = 1024. In this case, one or more target codewords may be selected as specific patterns of the alignment marker. Optionally, each alignment marker is obtained by performing codeword consolidation on multiple target codewords. Specifically, inner-code encoding is performed on alignment marker information including b1 × K target bits to obtain b1 target codewords, and codeword consolidation is performed on the b1 target codewords to obtain the alignment markers.

[0373] It should be noted that in the implementation shown in FIG. 22(a), Scheme 0 for generating alignment markers in FIG. 22(d) or Scheme 1 for generating alignment markers in FIG. 22(d) may be applied. In this case, the corresponding data processing scheme of the receiver is as follows: Inner code word self-synchronization is performed on the demodulated data stream obtained through demodulation to obtain inner code word boundaries. Next, the data stream obtained through 8-way inner code word deinterleaving is obtained, and inner code decoding is performed. Frame synchronization is performed by using the frame synchronization sequence in the inner code decoded alignment marker information to obtain the start position of each frame. It should be understood that the reliability of the frame synchronization sequence and the status field included in the inner code decoded alignment marker information is further improved, so the period for frame synchronization can be shortened.

[0374] It should be noted that in the implementation shown in Figure 22(b) or Figure 22(c), Scheme 0 for generating alignment markers in Figure 22(d) or Scheme 1 for generating alignment markers in Figure 22(d) may be applied. In this case, the corresponding data processing scheme of the receiver is as follows: Inner code word self-synchronization is performed on the demodulated data stream obtained through demodulation to obtain inner code word boundaries. Then, inner code decoding is performed, and frame synchronization is performed by using the frame synchronization sequence in the inner code decoded alignment marker information to obtain the start position of each frame. It should be understood that the period for frame synchronization can be shortened because the reliability of the frame synchronization sequence or status field included in the inner code decoded alignment marker information is further improved.

[0375] It should be noted that in the data processing methods shown in Figures 22(a), 22(b), and 22(c), the third data stream obtained by inserting alignment markers includes a W-bit alignment marker for every P+W bits, and the synchronization sequence in the alignment marker is at a fixed position. Therefore, in the data processing schemes shown in Figures 22(a), 22(b), and 22(c), one set of hardware is suitable for data processing at the receiver corresponding to the data processing at the transmitter in Figures 22(a), 22(b), and 22(c), since the same operation can be performed for frame synchronization in the corresponding data processing at the receiver to obtain the starting position of the frame.

[0376] It should be noted that in the 1.6TE scenario, the data process includes eight data sub-processes, each of which has a data stream input of one first data stream, and the first data stream corresponds to a rate of approximately 200 Gbits per second. Correspondingly, the distributed data stream corresponds to a rate of approximately 25 Gbits per second.

[0377] It should be noted that in some specific applications, the length W of the alignment marker is an integer multiple of the length N of the codeword obtained through the second FEC encoding (also called inner code encoding), and P is an integer multiple of N. In this case, the alignment marker may be protected by inner code encoding. Specifically, a W-bit alignment marker includes W / N inner codewords, W / N×K bits correspond to information bits in the inner codewords, and W / N×(NK) bits correspond to parity bits in the W / N inner codewords. Usually,

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[0378] In some specific applications, the frame sync sequence includes 48 bits distributed among two frame sync subsequences, which are separated by 8 bits, as shown in Figure 15. In this case, the 8 separating bits can be used as 8 bits for a CRC8 check, 8 bits indicating the type of link information and / or the type of control information, or 8 bits for a multi-frame sync signal.

[0379] Based on the above description, in this embodiment of the present application, alignment markers are periodically inserted into the data stream obtained through concatenated FEC encoding. Specifically, P bits are periodically obtained from the data stream obtained through concatenated FEC encoding, and a W-bit alignment marker (also called a frame header, which may include padding bits or a status field) is inserted, so that a W-bit alignment marker is present every P+W bits (called a frame) in the data stream. Positive integers P and W are selected so that the baud rate value of the modulated symbol data stream is an integer multiple of the Ethernet common reference clock frequency. This simplifies the receiver's clock extraction and synchronization scheme, realizes fast phase locking, and achieves low PLL complexity and small jitter. In addition, P needs to be a multiple of the code length N of the inner code, in other words, P=N×b, and synchronization of the inner codeword can be guaranteed after the receiver performs frame synchronization on the received data (i.e., frame synchronization of P+W bits, also called alignment marker lock operation). This simplifies operations such as frame synchronization and inner codeword synchronization at the receiver, achieving low implementation complexity. In addition, since the input / output switches of the convolutional interleaver are in the top position every time the convolutional interleaver outputs f bits, and the input / output switches of the convolutional deinterleaver are in the top position every time the convolutional deinterleaver outputs f bits, and K×b is divisible by f, the synchronization performed by the convolutional deinterleaver can be guaranteed during frame synchronization.

[0380] When frame synchronization is performed by using a W-bit alignment marker (also called a frame header, which may include padding bits or a status field), the receiver needs to identify the marker bit by bit. Given that the value of the integer P is usually large, the complexity of the frame synchronization operation for identifying the marker bit by bit is higher than the complexity of the inner codeword synchronization operation. In some application scenarios, the length W of the alignment marker may be selected as an integer multiple of the length N of the codeword obtained through the second FEC encoding (also called inner code encoding), and one or more inner codewords may be selected as a specific pattern of alignment markers, so that the receiver can perform frame synchronization and codeword synchronization with low complexity. The above-mentioned operation method of first performing inner code encoding and then periodically inserting alignment markers may be equivalent to the following operation method of first periodically inserting markers and then performing inner code encoding. In other words, the inner code encoding method applied to “first performing inner code encoding and then periodically inserting alignment markers” in the above embodiment may also be applied as the inner code encoding method for “first periodically inserting markers and then performing inner code encoding” in the following implementation. For example, the block code with information length K=120 bits and codeword length N=128 bits in embodiment 1 can also be used in the following specific implementation form. The following describes a specific implementation strategy for "first inserting markers periodically and then performing inner code encoding."

[0381] 7 is a schematic flowchart of another data processing method according to an embodiment of the present application. It should be understood that this data processing method is applied to a transmitter and includes the following steps:

[0382] 401: Perform first data processing on m first data streams to obtain m second data streams.

[0383] In this embodiment, all m first data streams are data streams obtained through first FEC encoding, i.e., outer-code encoded data streams as described above. Typically, the value of m is 4, 8, 16, 32, or 64.

[0384] Specifically, a first marker is periodically inserted into each of the m first data streams to obtain a total of m second data streams.

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[0385] 8 is a diagram of a structure of a second data stream according to an embodiment of the present application. As shown in FIG. 8, the second data stream includes at least one first bit sequence, and each first bit sequence is

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[0386] In some possible implementations, a concatenated interleaver is added between the inner code and the outer code to improve the performance of the overall concatenated FEC strategy. The concatenated interleaving operation usually includes convolutional interleaving to achieve low delay. In other words, all m first data streams are data streams obtained through concatenated interleaving. Specific implementations of concatenated interleaving include lane permutation and convolutional interleaving. In lane permutation, data permutation is performed on g input data streams to obtain g data streams obtained through data permutation. Then, convolutional interleaving is performed separately to obtain convolutionally interleaved data streams. Another specific implementation of concatenated interleaving includes lane multiplexing and convolutional interleaving. In lane multiplexing, symbol multiplexing is performed on g input data streams to obtain g symbol-multiplexed data streams, where g is divisible by g. Then, convolutional interleaving is separately performed on the g data streams to obtain g convolutionally interleaved data streams. In this case, g is not equal to g. In other words, the number of first data streams may be the same as or different from the number of second data streams obtained by performing the first data processing on the first data streams. This specifically depends on the actual application scenario and is not limited in this specification. For possible implementation forms of convolutional interleaving, please refer to step 301 for understanding.

[0387] In some possible implementations, at least one of operations such as alignment marker lock, lane de-skew, and lane reorder may be further performed before the first data processing.

[0388] In some possible implementations, the first data processing operation may further include scrambling. For example, each first data stream is first scrambled, and then a first marker is periodically inserted. In this way, when the receiver performs synchronization, the synchronization quality is improved.

[0389] 402: Perform second data processing on the m second data streams to obtain m third data streams.

[0390] In this embodiment, the second data processing operation includes, but is not limited to, performing second FEC encoding on each of the second data streams. The second FEC encoding can be understood as the inner code encoding described above. In other words, the second FEC encoding is performed on all m third data streams, where m is an integer greater than 1. Typically, the value of m is 4, 8, 16, 32, or 64. In one example, the inner code encoder performs inner code encoding on every K information bits in each of the second data streams, specifically adding S parity bits to obtain a total of N-bit inner codewords, in other words, N=K+S, where K≧1 and S≧1.

[0391] 9 is a diagram of a structure of a third data stream according to an embodiment of the present application. As shown in FIG. 9, each of the third data streams includes at least one second bit sequence, and each second bit sequence includes P+W bits, and P bits in each second bit sequence are

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[0392] The length of the first marker inserted into each first data stream in step 401

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[0393] In some possible implementations, the second data processing operation may further include at least one of operations such as channel interleaving and scrambling, for example, at least one of operations such as channel interleaving and scrambling is further performed on each of the second data streams after the second FEC encoding.

[0394] Note that the second marker shown in Figure 9 is a structure in the inner-code encoded data stream. Another operation, for example, channel interleaving for randomization, may be further performed on the inner-code encoded data stream. In this case, the second marker in the channel-interleaved data stream is randomized. However, the channel interleaving mode is fixed and preset, and the receiver can restore the specific position of the second marker in the data stream when performing inner-code synchronization based on the channel interleaving mode.

[0395] 403: Perform third data processing on the m third data streams to obtain Y modulated symbol streams.

[0396] In this embodiment, third data processing including modulation is performed on the m third data streams to obtain Y modulated symbol streams, where Y is an integer greater than or equal to 1.

[0397] In some possible implementations, the third data processing operation may further include at least one of codeword interleaving and symbol interleaving. For example, codeword interleaving is performed first, and then modulation is performed on each of the third data streams. In another example, modulation is performed first, and then symbol interleaving is performed on each of the third data streams, where symbol interleaving is also called channel interleaving. Colored noise in channel transmission can be interleaved through symbol interleaving for randomization, so that the quality of the signal recovered by the receiver is good.

[0398] In some specific applications, to obtain one channel-interleaved data stream, first, n of the m third data streams are interleaved. HM Channel interleaving is performed for every third data stream, resulting in a total of m / n HM Note that there are m / n channel-interleaved data streams. HM To obtain m / n modulated symbol data streams, HM The channel-interleaved data streams are modulated to m / n HM = Y. In total, n HM Through channel interleaving, n inner codewords are obtained. HM Each of the third data streams yields one inner codeword of length N bits. HM The inner code words are n HM ×N bits in a channel-interleaved data stream. HM To obtain ×N bits, two bits are obtained from each inner codeword in a round-robin fashion as bits in the second data stream. HM Hamming codeword interleaving in the direction (n HM It is also called multi-way Hamming codeword interleaving, or inner codeword interleaving.

[0399] Channel interleaving is performed first, then m / n overall HM n modulated symbol data streams for m third data streams HM Considering that modulation is performed for each third data stream, the total

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[0400]

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[0401] Note that in some other specific applications, each of the m second data streams includes one periodically inserted synchronization subsequence, and there are m synchronization subsequences in total, and the m synchronization subsequences are not all the same length.

[0402] In some specific applications, to further improve the anti-burst performance of the overall concatenated code,

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[0403] In this application, a positive integer is used so that the baud rate value of the modulated symbol data stream is an integer multiple of the reference clock frequency.

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[0404] Additionally, a selected positive integer

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[0405] It should be noted that the receiver may first perform codeword synchronization and then perform frame synchronization, or may directly perform frame synchronization bit by bit using the first marker or the second marker, which can ensure codeword synchronization and concatenated deinterleaving synchronization, which is not specifically limited in this specification.

[0406] Below is

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[0407] Considering an 800GbE scenario, the transmitter device performs outer code encoding on the 800GbE service data stream to be transmitted by using KP4 RS (544,514) code to obtain a data stream with an overall rate of 850Gbps, and transmits the data stream to the transmitter processing module through the attachment unit interface 800GAUI after PMA processing. The transmitter processing module periodically inserts first markers into m first data streams separately, in other words, performs first data processing to obtain m second data streams, and the overall rate of the m second data streams is

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[0408] moreover,

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[0409] Channel interleaving is performed first, then m / n overall HM n in the m third data streams to obtain m modulated symbol data streams. HM Considering that modulation is performed for every third data stream,

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[0410] Furthermore, since the transmitter processing module applies concatenated interleaving including convolutional interleaving, the receiver processing module must perform the following steps to ensure convolutional deinterleaving synchronization during frame synchronization:

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[0411] In this embodiment, the data processing operation is

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[0412] Below is

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[0413] Implementation 1: An FEC code with information length K=140 bits and codeword length N=148 bits is used for inner code encoding.

[0414] The inner code is considered to be an FEC code, for example Hamming(148,140), with information length K=140 bits and codeword length N=148 bits.

[0415] 10 is a diagram of an implementation form of inner code encoding according to an embodiment of the present application. In another example, the encoding method shown in FIG. 10 is used, where 140 bits of data to be encoded are represented by B[139:0]. To obtain 1 bit of data C[i], a bitwise exclusive OR is performed on every two consecutive bits in the 140 bits of data, obtaining 70 bits of data in total, represented by C[69:0], where C[i]=B[2*i]^B[2*i+1], and 0≦i≦69. Then, Hamming (78,70) encoding is performed on C[69:0] as information data to obtain 8 bits of parity data represented by P[7:0]. Finally, the 148 bits of B[139:0] and P[7:0] are concatenated together to become the output of the inner code encoding, and the output is represented by D[147:0]. D[139:0] comes from B[139:0] and D[147:140] comes from P[7:0].

[0416] Considering the 800GbE scenario, the baud rate of the PAM4 modulated symbol stream is

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[0417]

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[0418] [Table 12]

[0419] Parameter combinations in Table 11 (Table 12)

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[0420] The length of the inner codeword information is K=140 bits, and one RS symbol of the outer KP4 code contains 10 bits. For the convolutional interleaver between the inner code and the outer code, there is a convolutional interleaver whose input / output switch is in the top position whenever the convolutional interleaver outputs 140 bits. For example, the number of delay lines r of the convolutional interleaver is 7, and each storage unit of the convolutional interleaver stores d=20 bits. In this case, the receiver processing module can perform frame synchronization and codeword synchronization with low complexity. In addition, convolutional deinterleaving synchronization can be further ensured through frame synchronization of the received data; in other words, the positions of the input and output switches of the convolutional deinterleaving can be obtained. This simplifies operations such as frame synchronization, inner codeword synchronization, and concatenated interleaving synchronization in the receiver, achieving low implementation complexity.

[0421] Implementation 2: An FEC code with information length K=120 bits and codeword length N=127 bits is used for inner code encoding.

[0422] The inner code is considered to be an FEC code, for example Hamming(127,120), with information length K=120 bits and codeword length N=127 bits.

[0423] 11 is a diagram of another implementation of inner code encoding according to an embodiment of the present application. In another example, the encoding method shown in FIG. 11 is used, where 120 bits of data to be encoded are represented by B[119:0]. To obtain 1 bit of data C[i], a bitwise exclusive OR is performed on every two consecutive bits in the 120 bits of data, resulting in 60 bits of data in total, represented by C[59:0], where C[i]=B[2*i]^B[2*i+1], and 0≦i≦59. Then, Hamming (67,60) encoding is performed on C[59:0] as information data to obtain 7 bits of parity data represented by P[6:0]. Finally, the 127 bits of B[119:0] and P[6:0] are concatenated together to become the output of inner code encoding, and the output is represented by D[126:0]. D[119:0] comes from B[119:0] and D[126:120] comes from P[6:0].

[0424] Considering the 800GbE scenario, the baud rate of the PAM4 modulated symbol stream is

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[0425]

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[0426] [Table 13]

[0427] In some 800GbE scenarios with PAM4 modulation and 112.5G baud rate, and in 1.6TbE scenarios with PAM4 modulation and 225G baud rate,

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[0428] The length of the inner codeword information is K=120 bits, and one RS symbol of the outer KP4 code contains 10 bits. For the convolutional interleaver between the inner code encoding and the outer code encoding, there is a convolutional interleaver whose input / output switches are in the top position whenever the convolutional interleaver outputs 120 bits. For example, the number of delay lines r of the convolutional interleaver is 3, and each storage unit of the convolutional interleaver stores d=40 bits. In another example, the number of delay lines r of the convolutional interleaver is 6, and each storage unit of the convolutional interleaver stores d=20 bits. In this case, the receiver processing module can perform frame synchronization and codeword synchronization with low complexity. In addition, convolutional deinterleaving synchronization can be further ensured through frame synchronization of the received data; in other words, the positions of the input and output switches of the convolutional deinterleaving are obtained. This simplifies operations such as frame synchronization, inner codeword synchronization, and concatenated interleaving synchronization in the receiver, achieving low implementation complexity.

[0429] It should be noted that when PAM4 modulation is applied, each PAM4 symbol corresponds to two bits, and the bit error rate of the most significant bit (MSB) is different from the bit error rate of the least significant bit (LSB). When the bit length N of a codeword (e.g., the FEC code with a code length of 127 bits used in Implementation 2) is odd, two inner codewords are consecutive. Figure 12 is a diagram of the structure of a codeword. As shown in Figure 12, the first bit in the K-bit information sequence (also referred to as K information bits for short) of one codeword is the MSB, and the first bit in the K-bit information sequence of the other codeword is the LSB. This is not conducive to a hardware implementation of inner code decoding performed by a receiver.

[0430] To solve the above-mentioned problem, in some possible application scenarios, an inner codeword interleaving process may be performed on t inner codewords encoded with an inner code, where t is an even number, such as 2, 4, 8, or 16. The following describes the inner codeword interleaving process in detail.

[0431] 13 is another diagram of the codeword structure. As shown in FIG. 13, there are t inner codewords, namely, D0, D1, D2, ..., D t-1 is considered, and the codeword D i (0≦i≦t-1) is a K-bit information sequence B i and the S-bit parity sequence P i More specifically, t information sequences, namely B0, B1, B2, ..., B t-1 There are t parity sequences, namely, P0, P1, P2, ..., P t-1 A total of t×N bits in the t inner codewords are interleaved through an inner code interleaver to obtain an interleaved sequence of length t×N bits, and the interleaved sequence includes two consecutive subsequences of its bits, namely, a first subsequence of length t×K bits and a second subsequence of length t×S bits. The first consecutive subsequence of its bits is divided into t information sequences, namely, B0, B1, B2, ..., B t-1 The second subsequence, whose bits are consecutive, is a set of t parity sequences, namely, P0, P1, P2, ..., P t-1 For understanding, please refer to Figure 13. The above codeword interleaving is also a specific implementation strategy for channel interleaving.

[0432] t inner codewords of t × N bits, namely D0, D1, D2, ..., D t-1 To obtain the information sequence, we use t information sequences of t × K bits, namely, B0, B1, B2, ..., B t-1The inner code word is then performed on t×N bits, i.e., B0, B1, B2, ..., B t-1 , P0, P1, P2, ..., P t-1 It should be noted that inner codeword interleaving is performed to obtain t×N,t×K. In some possible scenarios, the above-mentioned inner code (N,K) encoding and interleaving of t inner codewords are referred to together as inner code (t×N,t×K) codewords. Those skilled in the art can distinguish between (N,K) encoding and (t×N,t×K) encoding based on context, and the details will not be described again here.

[0433] The t codewords mentioned above, i.e., D0, D1, D2, ..., D, are interleaved. t-1 It should be noted that t / 2 inner codewords may be obtained by performing inner code encoding on t×K bits in the same second data stream, or may be obtained by performing inner code encoding on t×K bits in multiple second data streams. For example, t / 2 inner codewords are obtained by performing inner code encoding on t / 2×K bits in one second data stream, and the other t / 2 inner codewords are obtained by performing inner code encoding on t / 2×K bits in another second data stream. Specific implementation forms are known to those skilled in the art, and will not be described in detail here.

[0434] Implementation 3: An FEC code with information length K=120 bits and codeword length N=128 bits is used for inner code encoding.

[0435] The inner code is an FEC code, for example, a Hamming (128,120) code, where the information length is K=120 bits and the codeword length is N=128 bits. In another example, 120 bits of data to be encoded are represented by B[119:0]. To obtain 1 bit of data C[i], a bitwise exclusive OR is performed on every two consecutive bits of the 120 bits of data, resulting in a total of 60 bits of data, represented by C[59:0]. C[i]=B[2*i]^B[2*i+1], where 0≦i≦59. Then, Hamming (68,60) encoding is performed on C[59:0] as information data to obtain 8 bits of parity data represented by P[7:0]. Finally, the 128 bits of B[119:0] and P[7:0] are concatenated together to form the output of the inner code encoding, which is represented by D[127:0]. D[119:0] comes from B[119:0] and D[127:120] comes from P[7:0].

[0436] Considering an 800GE scenario and PAM4 modulation being applied, four PAM-modulated symbol streams are obtained through data processing.

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[0437] Considering the 800GbE scenario, the baud rate of the PAM4 modulated symbol stream is

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[0438] 23 is a diagram of another implementation of data processing according to an embodiment of the present application. Referring to FIG. 23, the following describes a specific data processing procedure.

[0439] To obtain a total of m=32 second data streams, first markers are periodically inserted into each of the m=32 data streams obtained through the first FEC code.

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[0440] An inner code is encoded on each of the m=32 second data streams to obtain m=32 third data streams, specifically, K=120 information bits in each of the second data streams, and S=8 parity bits are added to obtain a total of N=128-bit inner codewords.

[0441] Overall, Y=m / n HM n out of m=32 third data streams to obtain m=4 modulated symbol streams HMThird data processing including PAM4 modulation is performed on each of the 32 third data streams. More specifically, to obtain a total of four channel-interleaved data streams, channel interleaving is first performed on each of eight of the 32 third data streams to obtain one channel-interleaved data stream. See FIG. 23. In the 800GE scenario, the data processing includes four data partial processes, namely, data partial process 0, data partial process 1, data partial process 2, and data partial process 3 in FIG. 23. Each data partial process includes one channel interleaving operation. To obtain a total of eight inner codewords, one inner codeword having a length of 128 bits is obtained from each of the eight input third data streams through channel interleaving. Two bits are obtained from each inner codeword in a round-robin manner as bits in the channel-interleaved data stream to obtain 1024 consecutive bits in the channel-interleaved data stream. The channel interleaving is also called eight-way Hamming codeword interleaving, or inner codeword interleaving. PAM4 modulation is then performed on the four channel-interleaved data streams to obtain Y=4 modulated symbol streams.

[0442] 24 is a diagram of the structure of a first marker according to an embodiment of the present application.

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[0443] In some specific applications,

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[0444] [Table 14]

[0445] Figure 25 is a diagram of the structure of a channel-interleaved synchronization sequence according to an embodiment of the present application. It should be noted that the specific bit patterns of the eight synchronization subsequences are not completely the same. Please refer to Figure 25. Through inner code encoding and inner codeword interleaving, the total number of bits in the eight synchronization subsequences is

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[0446] Implementation form 4 26 is another diagram of the structure of the first marker according to an embodiment of the present application.

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[0447] The specific bit patterns of the eight synchronization subsequences are listed in Table 15. The lengths of the eight synchronization subsequences are not exactly the same. The bit length of synchronization subsequence 0, synchronization subsequence 1, synchronization subsequence 2, and synchronization subsequence 3 is 8, and the bit length of synchronization subsequence 4, synchronization subsequence 5, synchronization subsequence 6, and synchronization subsequence 7 is 4.

[0448] [Table 15]

[0449] FIG. 27 is another diagram of the structure of a channel-interleaved synchronization sequence according to an embodiment of the present application. Please refer to FIG. 27. Through inner code encoding and inner codeword interleaving, a total of 48 bits in the eight synchronization subsequences correspond to 48 bits in the corresponding channel-interleaved data stream. These 48 bits may be used by a receiver to perform frame synchronization, and are also called a frame synchronization sequence, or synchronization sequence for short. The 48-bit synchronization sequence is not completely contiguous in the channel-interleaved data stream, but includes two bit sequence parts, the first bit sequence part including 24 bits, and the second bit sequence part including 24 bits. The first bit sequence part and the second bit sequence part are separated by 8 bits (i.e., 1 byte). In this specification, the interval between two consecutive bits is defined as 0 bits.

[0450] In some specific applications, the specific value of the 24-bit first bit sequence is 01011001 01010010 01100100 (transmitted from left to right), and the specific value of the 24-bit second bit sequence portion is 10100110 10101101 10011011 (transmitted from left to right). The leftmost bit in this bit pattern is transmitted first in the actual transmission. Both the first bit sequence portion and the second bit sequence portion can be expressed in hexadecimal notation. The first bit sequence portion is 0x9A, 0x4A, and 0x26, and the second bit sequence portion is 0x65, 0xB5, and 0xD9. Note that the specific bit patterns of the four synchronization sequences corresponding to the four channel-interleaved data streams are all the same: 0x9A, 0x4A, 0x26, 0x65, 0xB5, and 0xD9.

[0451] It should be noted that in the 48-bit synchronization sequence, the first bit sequence portion includes 24 bits, the second bit sequence portion includes 24 bits, and the first bit sequence portion and the second bit sequence portion are separated by 8 bits (1 byte). See Figure 16. According to the data processing method in this embodiment, for ease of implementation, it can be seen that the synchronization hardware implementation architecture in the existing 100GE 802.3bj and 400GE 802.3bs standards can be reused for the related computer architecture for performing synchronization by the receiver.

[0452] Implementation form 5 28 is a diagram of another implementation of data processing according to an embodiment of the present application. Based on embodiment 3, considering a 1.6TE scenario and PAM4 modulation is applied, 8 PAM-modulated symbol streams are obtained through data processing.

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[0453] Considering the 1.6TE scenario, the baud rate of the PAM4 modulated symbol stream is

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[0454] Implementation form 6 29 is another diagram of the structure of the first marker according to an embodiment of the present application.

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[0455] More specifically, the bit length of each synchronization subsequence is

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[0456] In some specific applications, specific values ​​for the first bit sequence portion of 24 bits in length are 0x9A, 0x4A, and 0x26, and specific values ​​for the second bit sequence portion of 24 bits in length are 0x65, 0xB5, and 0xD9.

[0457] In some specific applications, according to a specific data processing strategy of the present invention, the receiver may perform frame synchronization based on the total 384 bits of the eight synchronization subsequences. In other words, the receiver performs frame synchronization based on a data stream received at a rate of approximately 200G per second. In some other specific applications, the receiver may first perform channel deinterleaving on the data stream received at a rate of approximately 200G according to a channel interleaving rule to obtain eight channel-deinterleaved data streams, each with a rate of approximately 25G. Then, the receiver performs synchronization on each channel-deinterleaved data stream based on the known synchronization subsequence. It should be noted that when the receiver applies the above synchronization strategy based on the 25G rate, the eight channel-deinterleaved data streams are not perfectly aligned, and the order of each channel-deinterleaved data stream among the eight channel-deinterleaved data streams can be determined based on the position of the synchronized synchronous subsequence of each channel-deinterleaved data stream to correctly restore the order of the data streams and implement synchronous alignment.

[0458] Implementation form 7 30 is a diagram of another implementation of data processing according to an embodiment of the present application.

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[0459] Implementation form 8 31 is a diagram of another implementation of data processing according to an embodiment of the present application.

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[0460] Implementation 9 32 is a diagram of another implementation of data processing according to an embodiment of the present application. Based on implementation form 8, in each data partial processing, convolutional interleaving is performed separately on two input data streams to obtain two convolutionally interleaved data streams. Data distribution is performed on each convolutionally interleaved data stream to obtain four distributed first data streams, resulting in a total of eight distributed first data streams. Data distribution is performed with a granularity of α0 bits. As shown in Figure 32, when α0 bits in the convolutionally interleaved data stream are grouped together, for a total of four groups of 4 x α0 consecutive bits, the 0th group of α0 bits is transmitted to the 0th data stream of the four distributed first data streams, the first group of α0 bits is transmitted to the first data stream of the four distributed first data streams, the second group of α0 bits is transmitted to the second data stream of the four distributed first data streams, and the third group of α0 bits is transmitted to the third data stream of the four distributed first data streams. Typically, the granularity of the distributed bits is α0 = 120.

[0461] Note that in the 800GE scenario, as shown in Figure 32, the data processing includes four data sub-processes. Each data sub-process corresponds to two input data streams. The two input data streams correspond to a rate of approximately 200 Gbits per second, or in other words, each input data stream corresponds to a rate of approximately 100 Gbits per second. Correspondingly, the distributed first data stream corresponds to a rate of approximately 25 Gbits per second.

[0462] It is further noted that when the granularity of the scattering bits is α0=120, the data processing shown in FIG. 32 can be described as follows: Convolutional interleaving is performed separately on the two input data streams to obtain two total convolutionally interleaved data streams; A group of 4 bits is obtained from each convolutionally interleaved data stream, and the length of each bit group is 120 bits; Cyclic shifting and inner code encoding are performed separately on each bit group to obtain four inner codewords; A group of 8 bits is obtained from the two convolutionally interleaved data streams, and a total of 8 inner codewords are obtained separately through cyclic shifting and inner code encoding; and then channel interleaving is performed to obtain 1024 bits in the channel interleaved data stream.

[0463] Note that in the 1.6TE scenario, the data process includes eight data sub-processes, each corresponding to two first data streams. The two input data streams correspond to a rate of approximately 200 Gbits per second, or in other words, each input data stream corresponds to a rate of approximately 100 Gbits per second. Correspondingly, the distributed first data streams correspond to a rate of approximately 25 Gbits per second.

[0464] Implementation 10 FIG. 33 is a diagram of another implementation of data processing according to an embodiment of the present application. Based on implementation form 8, the data processing includes four input data streams, and each data sub-process includes one input data stream. Convolutional interleaving is performed on each input data stream to obtain one convolutionally interleaved data stream. Data distribution is performed on the convolutionally interleaved data stream to obtain eight distributed first data streams. The data distribution is performed with a granularity of α bits. As shown in FIG. 33, when α bits in the convolutionally interleaved first data stream are grouped together, for a total of eight groups of 8×α consecutive bits, the 0th group of α bits is transmitted to the 0th data stream among the eight distributed first data streams, the 1st group of α bits is transmitted to the 1st data stream among the eight distributed first data streams, ..., the 7th group of α bits is transmitted to the 7th data stream among the eight distributed first data streams. Typically, the granularity of the distributed bits is α0=120.

[0465] In the 800GE scenario, it should be noted that the data processing includes four data sub-processes, as shown in Figure 33. The data stream input of each data sub-process is one data stream, and the data stream corresponds to a rate of about 200 Gbits per second. Correspondingly, the distributed first data stream corresponds to a rate of about 25 Gbits per second.

[0466] It should be noted that in the 1.6TE scenario, the data process includes eight data sub-processes, each of which has a data stream input corresponding to one data stream, and the data stream corresponds to a rate of approximately 200G / s. Correspondingly, the distributed first data stream corresponds to a rate of approximately 25Gbit / s.

[0467] It should be noted that convolutional interleaving and dispersion are performed on the input data stream to obtain four first data streams as shown in Figure 32, and convolutional interleaving and dispersion are performed on the input data stream to obtain eight first data streams as shown in Figure 33. Both of these can be understood as each first data stream being obtained through convolutional interleaving.

[0468] In implementations 3 to 10, each of the eight second data streams is inserted periodically.

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[0469] In some specific applications, as shown in Figure 26, a total of 48 bits of the eight synchronization subsequences are used as frame synchronization sequences and distributed among eight secondary data streams, with four of the secondary data streams each including eight bits of the frame synchronization sequence (i.e., synchronization subsequences 0 to 3), and the other four secondary data streams each including four bits of the frame synchronization sequence (i.e., synchronization subsequences 4 to 7). The four bits of each synchronization subsequence among synchronization subsequences 4 to 7 are:

number

[0470] It should be noted that according to the data processing method applied to the transmitter shown in FIG. 7, the data processing method applied to the receiver correspondingly includes the following steps: First, fourth data processing is performed on the received Y modulated symbol streams to obtain m fourth data streams. For characteristics of the modulated symbol streams and the manner of generating the modulated symbol streams, please refer to the relevant description of the embodiment shown in FIG. 7. Details will not be described again here. To obtain m fourth data streams, fourth data processing including demodulation is performed on the Y modulated symbol streams, and the fourth data processing performed by the receiver is the inverse operation of the third data processing performed by the transmitter. Then, frame synchronization is performed for each of the fourth data streams. It should be understood that, so that codeword synchronization and / or frame synchronization can be performed, the receiver performs alignment marker lock based on markers added to the data streams by the transmitter to determine the boundary of each frame (P+W bits) in the fourth data stream.

[0471] It should be understood that after completing codeword synchronization and / or frame synchronization, the receiver further performs fifth data processing on the m fourth data streams. The fifth data processing can be understood as the inverse operation of the second data processing performed by the transmitter. For example, the fifth data processing module includes, but is not limited to, inner code decoding and concatenated deinterleaving, and concatenated deinterleaving includes convolutional deinterleaving. Details will not be described one by one again here.

[0472] The following describes a data processing device provided in an embodiment of the present application.

[0473] 34 is a diagram of the structure of a data processing device used in a transmitter according to an embodiment of the present application. As shown in FIG. 34, the data processing device includes a first data processing unit 701, a second data processing unit 702, and a third data processing unit 703. The first data processing unit 701 is configured to perform the operation of step 301 in the embodiment shown in FIG. 3 or the operation of step 401 in the embodiment shown in FIG. 7. The second data processing unit 702 is configured to perform the operation of step 302 in the embodiment shown in FIG. 3 or the operation of step 402 in the embodiment shown in FIG. 7. The third data processing unit 703 is configured to perform the operation of step 303 in the embodiment shown in FIG. 3 or the operation of step 403 in the embodiment shown in FIG. 7. For specific operations, please refer to the relevant descriptions in the embodiments shown in FIG. 3 and FIG. 7. The details will not be described again here.

[0474] Figure 35 is a structural diagram of a data processing device used in a receiver according to an embodiment of the present application. As shown in Figure 35, the data processing device includes a data processing unit 801 and a synchronization unit 802. The data processing unit 801 is configured to perform the operation of step 601 in the embodiment shown in Figure 6. The synchronization unit 802 is configured to perform the operation of step 602 in the embodiment shown in Figure 6. For specific operations, please refer to the related description in the embodiment shown in Figure 6. The details will not be described again here.

[0475] It should be understood that the devices provided in the present application may alternatively be implemented in other ways. For example, the division into units in the above-described devices is merely a logical division of functions, and other divisions may be used in actual implementation. For example, multiple units or components may be combined or integrated into another system. In addition, the functional units in the embodiments of the present application may be integrated into one processing unit or may be independent physical units, or two or more functional units may be integrated into one processing unit. The integrated unit may be implemented in the form of hardware or in the form of a software functional unit.

[0476] FIG. 36 is another diagram of the structure of a data processing device according to an embodiment of the present application. As shown in FIG. 36, the data processing device includes a processor 901, a memory 902, and a transceiver 903. The processor 901, the memory 902, and the transceiver 903 are interconnected through lines. The memory 902 is configured to store program instructions and data. Specifically, the processor 901 is configured to perform data processing operations, and the transceiver 903 is configured to perform data receiving and transmitting operations. In one possible implementation, the processor 901 may include the first data processing unit 701, the second data processing unit 702, and the third data processing unit 703 shown in FIG. 34. In another possible implementation, the processor 901 may include the data processing unit 801 and the synchronization unit 802 shown in FIG. 35.

[0477] It should be noted that the processor shown in FIG. 36 may be a general-purpose central processing unit (CPU), a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, a transistor logic device, a hardware component, or any combination thereof. The memory shown in FIG. 36 may store an operating system and other application programs. When the technical solutions provided in the embodiments of the present application are implemented through software or firmware, the program code used to implement the technical solutions provided in the embodiments of the present application is stored in the memory and executed by the processor. In some embodiments, the processor may include a memory therein. In another embodiment, the processor and the memory are two independent structures.

[0478] For convenience and ease of explanation, the detailed working processes of the above-mentioned systems, devices, and units can be clearly understood by those skilled in the art by referring to the corresponding processes in the above-mentioned method embodiments, and therefore, the details will not be described again here.

[0479] Those skilled in the art may understand that all or part of the steps in the above-described embodiments may be implemented through hardware or a program instructing related hardware. The program may be stored in a computer-readable storage medium. The storage medium may be a read-only memory, a random-access memory, etc. Whether the functions are implemented through hardware or software depends on the specific application and the design constraints of the technical solution. Those skilled in the art may use various methods to implement the described functions for each specific application, but the implementation should not be considered as going beyond the scope of this application.

[0480] When software is used to implement functions, all or part of the method steps described in the above embodiments may be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded into a computer and executed, all or part of the procedures or functions according to the embodiments of the present application are generated. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from a computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from a website, computer, server, or data center to another website, computer, server, or data center via wire (e.g., coaxial cable, optical fiber, or digital subscriber line (DSL)) or wireless (e.g., infrared, radio, or microwave). The computer-readable storage medium may be any available medium accessible by a computer or a data storage device, such as a server or data center, that integrates one or more available media. The usable medium may be a magnetic medium (e.g., a floppy disk, a hard disk, or a magnetic tape), an optical medium (e.g., a DVD), a semiconductor medium (e.g., a solid-state drive (SSD)), or the like. [Explanation of symbols]

[0481] 01 Transmitter Device 02 Transmitter Processing Module 03 Channel Transmission Medium 04 Receiver processing module 05 Receiver Device 701 first data processing unit 702 second data processing unit 703 Third Data Processing Unit 801 Data Processing Unit 802 Synchronous Unit 901 processor 902 memory 903 Transceiver

Claims

1. 1. A data processing method comprising: performing first data processing on a plurality of first data streams obtained through first forward error correction (FEC) encoding to obtain m second data streams, where m is an integer greater than 1, second FEC encoding is performed on each of the second data streams, and each codeword obtained through the second FEC encoding includes N bits, where N=K+S, K represents the number of information bits, S represents the number of parity bits, K is an integer greater than or equal to 1, and S is an integer greater than or equal to 1; separately performing second data processing on the m second data streams to obtain m third data streams, each of the third data streams including at least one bit sequence, each bit sequence including P+W bits, P bits in each bit sequence being from the second data stream, and W bits in each bit sequence being an added alignment marker, where P=N×b, and b is an integer greater than or equal to 1; performing third data processing on the m third data streams to obtain Y modulated symbol streams, where Y is an integer greater than or equal to 1, modulation is performed on each of the modulated symbol streams, and a baud rate value of each of the modulated symbol streams is an integer multiple of a reference clock frequency value.

2. 2. The method of claim 1, wherein the value of the baud rate of each of the modulated symbol streams is an integer multiple of 156.25M.

3. 3. The method of claim 1, wherein before the second FEC encoding, convolutional interleaving is performed on each of the second data streams, the convolutional interleaving includes delaying the input data stream based on r delay lines, r is an integer greater than 1, the delay lines include different numbers of storage units, the delay line with the smallest number of storage units includes 0 storage units, the difference between the number of storage units in every two adjacent delay lines is Q, each storage unit is for storing d bits, bits in the input data stream are input sequentially to the r delay lines based on their order numbers, d bits are input to each delay line only once, and d bits are output from each delay line only once, and r*d consecutive bits in the data stream output through the convolutional interleaving include d bits output from each delay line, Q is an integer greater than or equal to 1, and d is an integer greater than or equal to 1.

4. 4. The method of claim 3, wherein the input / output switch corresponding to the convolutional interleave is in a 0th delay line every time f bits are output through the convolutional interleave, and K×b is divisible by f.

5. 5. The method of claim 3, wherein r×d×c=K×b, and c is an integer of 1 or greater.

6. the rate of the first data stream is 850 Gbps; [Equation 1] 6. The method of claim 1, wherein a is an integer greater than or equal to 1, G represents 10^9, and M represents 10^6.

7. N=128, K=120, and [Equation 2] The method of claim 6, wherein

8. W=48, P=13056, a=728, b=102, and the baud rate=113.75 Gbaud; W=48, P=52224, a=726, b=408, and the baud rate=113.4375 Gbaud; W=56, P=15232, a=728, b=119, and the baud rate=113.75 Gbaud; W=56, P=60928, a=726, b=476, and the baud rate=113.4375 Gbaud; W=64, P=13056, a=728, b=102, and the baud rate=113.75 Gbaud; W=64, P=69632, a=726, b=544, and the baud rate=113.4375 Gbaud; W=120, P=32640, a=728, b=255, and the baud rate=113.75 Gbaud; W=120, P=52224, a=727, b=408, and the baud rate=113.5938 Gbaud; W=120, P=130560, a=726, b=1020, and the baud rate=113.4375 Gbaud; W=128, P=34816, a=728, b=272, and the baud rate=113.75 Gbaud, or 8. The method of claim 7, wherein W=128, P=139264, a=726, b=1088, and the baud rate=113.4375 Gbaud.

9. N=170, K=160, and [Equation 3] The method of claim 6, wherein

10. W=48, P=23120, a=724, b=136, and the baud rate=113.125 Gbaud; W=48, P=69360, a=723, b=408, and the baud rate=112.9688 Gbaud; W=56, P=11560, a=726, b=68, and the baud rate=113.4375 Gbaud; W=56, P=80920, a=723, b=476, and the baud rate=112.9688 Gbaud; W=64, P=92480, a=723, b=544, and the baud rate=112.9688 Gbaud; W=120, P=34680, a=725, b=204, and the baud rate=113.2813 Gbaud; W=120, P=57800, a=724, b=340, and the baud rate=113.125 Gbaud; W=120, P=173400, a=723, b=1020, and the baud rate=112.9688 Gbaud; W=170, P=49130, a=725, b=289, and the baud rate=113.2813 Gbaud, or 10. The method of claim 9, wherein W=170, P=245650, a=723, b=1445, and the baud rate=112.9688 Gbaud.

11. N=144, K=136, and [Equation 4] The method of claim 6, wherein

12. W=48, P=5760, a=726, b=40, and the baud rate=113.4375 Gbaud; W=48, P=8640, a=724, b=60, and the baud rate=113.125 Gbaud; W=48, P=11520, a=723, b=80, and the baud rate=112.9688 Gbaud; W=48, P=17280, a=722, b=120, and the baud rate=112.8125 Gbaud; W=48, P=34560, a=721, b=240, and the baud rate=112.6563 Gbaud; W=56, P=5760, a=727, b=40, and the baud rate=113.5938 Gbaud; W=56, P=20160, a=722, b=140, and the baud rate=112.8125 Gbaud; W=56, P=40320, a=721, b=280, and the baud rate=112.6563 Gbaud; W=64, P=5760, a=728, b=40, and the baud rate=113.75 Gbaud; W=64, P=11520, a=724, b=80, and the baud rate=113.125 Gbaud; W=64, P=23040, a=722, b=160, and the baud rate=112.8125 Gbaud; W=64, P=46080, a=721, b=320, and the baud rate=112.6563 Gbaud, W=120, P=14400, a=726, b=100, and the baud rate=113.4375 Gbaud; W=120, P=17280, a=725, b=120, and the baud rate=113.2813 Gbaud; W=120, P=28800, a=723, b=200, and the baud rate=112.9688 Gbaud; W=120, P=43200, a=722, b=300, and the baud rate=112.8125 Gbaud; W=120, P=86400, a=721, b=600, and the baud rate=112.6563 Gbaud; W=144, P=11520, a=729, b=80, and the baud rate=113.9063 Gbaud; W=144, P=17280, a=726, b=120, and the baud rate=113.4375 Gbaud; W=144, P=25920, a=724, b=180, and the baud rate=113.125 Gbaud; W=144, P=34560, a=723, b=240, and the baud rate=112.9688 Gbaud; W=144, P=51840, a=723, b=360, and the baud rate=112.8125 Gbaud, or 12. The method of claim 11, wherein W=144, P=103680, a=721, b=720, and the baud rate=112.6563 Gbaud.

13. W=56, P=5040, a=728, b=35, and the baud rate=113.75 Gbaud; W=56, P=10080, a=724, b=70, and the baud rate=113.125 Gbaud; W=56, P=20160, a=722, b=140, and the baud rate=112.8125 Gbaud, or 12. The method of claim 11, wherein W=56, P=40320, a=721, b=280, and the baud rate=112.6563 Gbaud.

14. 6. The method according to claim 1, wherein N=148, K=140, W is a multiple of 4, and b is a multiple of 17.

15. 6. The method of claim 1, wherein N=128, K=120, and the baud rate of the modulated symbol stream is 113.4375 Gbaud.

16. 16. The method of claim 15, wherein P=1088×W.

17. 17. The method of claim 1, 2, 3, 4, 5, 15, or 16, wherein the alignment marker comprises at least one frame synchronization sequence having a length of 48 bits.

18. 18. The method of claim 17, wherein the 48 bits of the frame synchronization sequence are contiguous within the alignment marker.

19. 20. The method of claim 18, wherein the 48-bit values ​​of the frame synchronization sequence include 0x9A, 0x4A, 0x26, 0x65, 0xB5, and 0xD9.

20. 18. The method of claim 17, wherein the frame synchronization sequence includes two frame synchronization subsequences, each of which is 24 bits long, and the two frame synchronization subsequences are separated by 8 bits within the alignment marker.

21. 21. The method of claim 20, wherein the 24-bit values ​​of one of the two frame synchronization subsequences include 0x9A, 0x4A, and 0x26, and the 24-bit values ​​of the other of the two frame synchronization subsequences include 0x65, 0xB5, and 0xD9.

22. 22. The method of claim 1, wherein the alignment marker comprises padding bits and / or a status field.

23. 23. The method of any one of claims 1 to 22, wherein W is divisible by N.

24. At least one of the following operations is performed on each of the second data streams prior to the second FEC encoding: alignment marker locking, lane deskewing, and lane reordering; and / or 24. The method of claim 1, wherein at least one of the following operations is further performed on each of the second data streams after the second FEC encoding: channel interleaving and scrambling.

25. performing first data processing on a plurality of first data streams to obtain m second data streams; separately performing second FEC encoding on each group of eight first data streams among the plurality of first data streams to obtain each group of eight encoded data streams; and performing channel interleaving on each group of eight coded data streams to obtain one second data stream to obtain the m second data streams.

26. N=128, K=120, and performing channel interleaving on each group of eight coded data streams to obtain one second data stream, obtaining one inner codeword having a length of 128 bits from each coded data stream in each group of eight coded data streams to obtain a total of eight inner codewords; and taking two bits from each of the eight inner codewords in a round-robin manner to obtain 1024 consecutive bits in the second data stream.

27. 27. The method of claim 1, wherein a cyclic shift is performed on each of the second data streams before the second FEC encoding.

28. performing a first data processing on a plurality of first data streams; separately performing convolutional interleaving on the 8×m first data streams; separately performing cyclic shifts on the 8×m convolutionally interleaved first data streams; and separately performing second FEC encoding on the 8×m cyclically shifted first data streams.

29. performing a first data processing on a plurality of first data streams; separately performing convolutional interleaving on the 2×m first data streams; dispersing each convolutionally interleaved first data stream to obtain four dispersed first data streams, for a total of 8×m dispersed first data streams; separately performing cyclic shifts on the 8×m distributed first data streams; and separately performing second FEC encoding on the 8×m cyclically shifted first data streams.

30. performing a first data processing on a plurality of first data streams; separately performing convolutional interleaving on the m first data streams; distributing each convolutionally interleaved first data stream to obtain eight distributed first data streams, for a total of 8×m distributed first data streams; separately performing cyclic shifts on the 8×m distributed first data streams; and separately performing second FEC encoding on the 8×m cyclically shifted first data streams.

31. performing first data processing on a plurality of first data streams to obtain m second data streams; distributing each of the m first data streams to obtain 8 distributed first data streams in total, for a total of 8×m distributed first data streams; separately performing second FEC encoding on the 8×m distributed first data streams to obtain 8×m encoded data streams; and performing codeword combination on every eight coded data streams among the 8×m coded data streams to obtain one second data stream, for a total of m second data streams.

32. 32. The method of claim 1, wherein the alignment marker comprises at least one target code word, the target code word comprising N bits.

33. 33. The method of claim 32, wherein the target codeword is obtained by performing a second FEC encoding on K-bit alignment marker information.

34. 34. The method of claim 32 or 33, wherein the alignment markers are obtained by performing codeword interleaving on a plurality of target codewords or by performing codeword merging on a plurality of target codewords.

35. 1. A data processing method comprising: performing fourth data processing on the received Y modulated symbol streams to obtain m fourth data streams, wherein demodulation is performed on each of the fourth data streams, the Y modulated symbol streams being obtained by performing third data processing on m third data streams, modulation is performed on each of the modulated symbol streams, the m third data streams being obtained by separately performing second data processing on m second data streams, and the m second data streams being obtained by performing first data processing on a plurality of first data streams obtained through first forward error correction (FEC) encoding, wherein Y is an integer greater than or equal to 1; wherein m is an integer greater than 1, a second FEC encoding is performed on each of the second data streams, and each codeword obtained through the second FEC encoding includes N bits, where N=K+S, K represents the number of information bits, S represents the number of parity bits, K is an integer greater than or equal to 1, and S is an integer greater than or equal to 1, each of the third data streams includes at least one bit sequence, each bit sequence includes P+W bits, P bits in each bit sequence are from the second data stream, and W bits in each bit sequence are added alignment markers, where P=N×b, b is an integer greater than or equal to 1, and a baud rate value of each of the modulated symbol streams is an integer multiple of a reference clock frequency value; performing frame synchronization for each of the fourth data streams based on alignment markers in each of the fourth data streams.

36. 1. A data processing device, comprising: a first data processing unit, a second data processing unit, and a third data processing unit; the first data processing unit is configured to perform first data processing on a plurality of first data streams obtained through first forward error correction (FEC) encoding to obtain m second data streams, where m is an integer greater than 1; second FEC encoding is performed on each of the second data streams; each code word obtained through the second FEC encoding includes N bits, where N=K+S, K represents the number of information bits, S represents the number of parity bits, K is an integer greater than or equal to 1, and S is an integer greater than or equal to 1; the second data processing unit is configured to separately perform second data processing on the m second data streams to obtain m third data streams, each of the third data streams including at least one bit sequence, each bit sequence including P+W bits, P bits in each bit sequence being from the second data stream, and W bits in each bit sequence being an added alignment marker, where P=N×b, b being an integer greater than or equal to 1; the third data processing unit is configured to perform third data processing on the m third data streams to obtain Y modulated symbol streams, where Y is an integer greater than or equal to 1, modulation is performed on each of the modulated symbol streams, and a baud rate value of each of the modulated symbol streams is an integer multiple of a reference clock frequency value.

37. 37. A data processing apparatus as claimed in claim 36, wherein said value of said baud rate of each of said modulated symbol streams is an integer multiple of 156.25M.

38. 38. The data processing apparatus of claim 36 or 37, wherein before the second FEC encoding, convolutional interleaving is performed on each of the second data streams, the convolutional interleaving comprises delaying the input data stream based on r delay lines, r is an integer greater than 1, the delay lines comprise different numbers of storage units, the delay line with the smallest number of storage units comprises zero storage units, the difference between the number of storage units in every two adjacent delay lines is Q, each storage unit is for storing d bits, bits in the input data stream are input sequentially to the r delay lines based on their order numbers, d bits are input to each delay line only once and d bits are output from each delay line only once, r*d consecutive bits in the data stream output through the convolutional interleaving comprise d bits output from each delay line, Q is an integer greater than or equal to 1, and d is an integer greater than or equal to 1.

39. 39. The data processing apparatus of claim 38, wherein the input / output switch corresponding to the convolutional interleave is in a 0th delay line every time f bits are output through the convolutional interleave, and K*b is divisible by f.

40. 40. The data processing device of claim 38 or 39, wherein r×d×c=K×b, and c is an integer greater than or equal to 1.

41. the rate of the first data stream is 850 Gbps; [Equation 5] 41. The data processing device according to any one of claims 36 to 40, wherein a is an integer greater than or equal to 1, G represents 10^9, and M represents 10^6.

42. N=128, K=120, and [Equation 6] 42. The data processing device of claim 41, wherein:

43. W=48, P=13056, a=728, b=102, and the baud rate=113.75 Gbaud; W=48, P=52224, a=726, b=408, and the baud rate=113.4375 Gbaud; W=56, P=15232, a=728, b=119, and the baud rate=113.75 Gbaud; W=56, P=60928, a=726, b=476, and the baud rate=113.4375 Gbaud; W=64, P=13056, a=728, b=102, and the baud rate=113.75 Gbaud; W=64, P=69632, a=726, b=544, and the baud rate=113.4375 Gbaud; W=120, P=32640, a=728, b=255, and the baud rate=113.75 Gbaud; W=120, P=52224, a=727, b=408, and the baud rate=113.5938 Gbaud; W=120, P=130560, a=726, b=1020, and the baud rate=113.4375 Gbaud; W=128, P=34816, a=728, b=272, and the baud rate=113.75 Gbaud, or 43. A data processing apparatus as claimed in claim 42, wherein W=128, P=139264, a=726, b=1088, and the baud rate=113.4375 Gbaud.

44. N=170, K=160, and [Equation 7] 42. The data processing device of claim 41, wherein:

45. W=48, P=23120, a=724, b=136, and the baud rate=113.125 Gbaud; W=48, P=69360, a=723, b=408, and the baud rate=112.9688 Gbaud; W=56, P=11560, a=726, b=68, and the baud rate=113.4375 Gbaud; W=56, P=80920, a=723, b=476, and the baud rate=112.9688 Gbaud; W=64, P=92480, a=723, b=544, and the baud rate=112.9688 Gbaud; W=120, P=34680, a=725, b=204, and the baud rate=113.2813 Gbaud; W=120, P=57800, a=724, b=340, and the baud rate=113.125 Gbaud; W=120, P=173400, a=723, b=1020, and the baud rate=112.9688 Gbaud; W=170, P=49130, a=725, b=289, and the baud rate=113.2813 Gbaud, or 45. The data processing apparatus of claim 44, wherein W=170, P=245650, a=723, b=1445, and the baud rate=112.9688 Gbaud.

46. N=144, K=136, and [Equation 8] 42. The data processing device of claim 41, wherein:

47. W=48, P=5760, a=726, b=40, and the baud rate=113.4375 Gbaud; W=48, P=8640, a=724, b=60, and the baud rate=113.125 Gbaud; W=48, P=11520, a=723, b=80, and the baud rate=112.9688 Gbaud; W=48, P=17280, a=722, b=120, and the baud rate=112.8125 Gbaud; W=48, P=34560, a=721, b=240, and the baud rate=112.6563 Gbaud; W=56, P=5760, a=727, b=40, and the baud rate=113.5938 Gbaud; W=56, P=20160, a=722, b=140, and the baud rate=112.8125 Gbaud; W=56, P=40320, a=721, b=280, and the baud rate=112.6563 Gbaud; W=64, P=5760, a=728, b=40, and the baud rate=113.75 Gbaud; W=64, P=11520, a=724, b=80, and the baud rate=113.125 Gbaud; W=64, P=23040, a=722, b=160, and the baud rate=112.8125 Gbaud; W=64, P=46080, a=721, b=320, and the baud rate=112.6563 Gbaud, W=120, P=14400, a=726, b=100, and the baud rate=113.4375 Gbaud; W=120, P=17280, a=725, b=120, and the baud rate=113.2813 Gbaud; W=120, P=28800, a=723, b=200, and the baud rate=112.9688 Gbaud; W=120, P=43200, a=722, b=300, and the baud rate=112.8125 Gbaud; W=120, P=86400, a=721, b=600, and the baud rate=112.6563 Gbaud; W=144, P=11520, a=729, b=80, and the baud rate=113.9063 Gbaud; W=144, P=17280, a=726, b=120, and the baud rate=113.4375 Gbaud; W=144, P=25920, a=724, b=180, and the baud rate=113.125 Gbaud; W=144, P=34560, a=723, b=240, and the baud rate=112.9688 Gbaud; W=144, P=51840, a=723, b=360, and the baud rate=112.8125 Gbaud, or 47. A data processing apparatus according to claim 46, wherein W=144, P=103680, a=721, b=720, and the baud rate=112.6563 Gbaud.

48. W=56, P=5040, a=728, b=35, and the baud rate=113.75 Gbaud; W=56, P=10080, a=724, b=70, and the baud rate=113.125 Gbaud; W=56, P=20160, a=722, b=140, and the baud rate=112.8125 Gbaud, or 47. A data processing apparatus according to claim 46, wherein W=56, P=40320, a=721, b=280, and the baud rate=112.6563 Gbaud.

49. 41. A data processing apparatus according to any one of claims 36 to 40, wherein N=148, K=140, W is a multiple of 4, and b is a multiple of 17.

50. 41. A data processing apparatus according to any one of claims 36 to 40, wherein N=128, K=120 and the baud rate of the modulated symbol stream is 113.4375 Gbaud.

51. 51. A data processing apparatus according to claim 50, wherein P=1088×W.

52. 52. A data processing apparatus as claimed in claim 36, 37, 38, 39, 40, 50 or 51, wherein said alignment marker comprises at least one frame synchronization sequence having a length of 48 bits.

53. 53. A data processing apparatus as claimed in claim 52, wherein said 48 bits of said frame synchronization sequence are contiguous within said alignment marker.

54. 54. A data processing apparatus as claimed in claim 53, wherein the 48-bit values ​​of the frame synchronization sequence include 0x9A, 0x4A, 0x26, 0x65, 0xB5 and 0xD9.

55. 53. The data processing apparatus of claim 52, wherein the frame synchronization sequence includes two frame synchronization subsequences, each of which is 24 bits in length, and wherein the two frame synchronization subsequences are separated by 8 bits within the alignment marker.

56. 56. A data processing apparatus as claimed in claim 55, wherein the 24-bit values ​​of one of the two frame synchronization subsequences include 0x9A, 0x4A, and 0x26, and the 24-bit values ​​of the other of the two frame synchronization subsequences include 0x65, 0xB5, and 0xD9.

57. 57. A data processing apparatus according to any one of claims 36 to 56, wherein the alignment marker comprises padding bits and / or a status field.

58. 58. A data processing apparatus according to any one of claims 36 to 57, wherein W is divisible by N.

59. At least one of the following operations is performed on each of the second data streams prior to the second FEC encoding: alignment marker locking, lane deskewing, and lane reordering; and / or 59. A data processing apparatus according to any one of claims 36 to 58, wherein at least one of the following operations is further performed on each of said second data streams after said second FEC encoding: channel interleaving and scrambling.

60. Specifically, the first data processing unit: separately performing second FEC encoding on each group of eight first data streams among the plurality of first data streams to obtain each group of eight encoded data streams; 59. A data processing apparatus according to any one of claims 36 to 58, configured to perform channel interleaving on each group of eight coded data streams to obtain one second data stream, in order to obtain the m second data streams.

61. N=128, K=120, and the first data processing unit specifically: obtaining one inner codeword having a length of 128 bits from each coded data stream in each group of eight coded data streams to obtain a total of eight inner codewords; 61. A data processing apparatus according to claim 60, configured to obtain two bits from each of the eight inner codewords in a round robin manner to obtain 1024 consecutive bits in the second data stream.

62. 62. A data processing apparatus according to any one of claims 36 to 61, wherein a cyclic shift is performed on each of said second data streams before said second FEC encoding.

63. Specifically, the first data processing unit: separately performing convolutional interleaving on the 8×m first data streams; separately performing cyclic shifts on the 8×m convolutionally interleaved first data streams; 63. A data processing apparatus according to claim 62, configured to perform the second FEC encoding separately on the 8xm cyclically shifted first data streams.

64. Specifically, the first data processing unit: separately performing convolutional interleaving on the 2×m first data streams; dispersing each convolutionally interleaved first data stream to obtain four distributed first data streams, for a total of 8×m distributed first data streams; separately performing cyclic shifts on the 8×m distributed first data streams; 63. A data processing apparatus according to claim 62, configured to perform the second FEC encoding separately on the 8xm cyclically shifted first data streams.

65. Specifically, the first data processing unit: separately performing convolutional interleaving on the m first data streams; distributing each convolutionally interleaved first data stream to obtain 8 distributed first data streams, for a total of 8×m distributed first data streams; separately performing cyclic shifts on the 8×m distributed first data streams; 63. A data processing apparatus according to claim 62, configured to perform the second FEC encoding separately on the 8xm cyclically shifted first data streams.

66. Specifically, the first data processing unit: distributing each of the m first data streams to obtain 8 distributed first data streams in total, to obtain 8×m distributed first data streams; separately performing second FEC encoding on the 8×m distributed first data streams to obtain 8×m encoded data streams; 59. The data processing apparatus of claim 36, 37, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, or 58, configured to perform codeword combination on every eight coded data streams among the 8×m coded data streams to obtain one second data stream, for a total of m second data streams.

67. 67. A data processing apparatus as claimed in any one of claims 36 to 66, wherein said alignment marker comprises at least one target code word, said target code word comprising N bits.

68. 68. A data processing apparatus according to claim 67, wherein said target codeword is obtained by performing a second FEC encoding on K-bit alignment marker information.

69. 69. A data processing apparatus according to claim 67 or 68, wherein the alignment markers are obtained by performing codeword interleaving on a plurality of target codewords or by performing codeword merging on a plurality of target codewords.

70. A data processing apparatus, comprising: a data processing unit and a synchronization unit; The data processing unit is configured to perform fourth data processing on the received Y modulated symbol streams to obtain m fourth data streams, demodulation is performed on each of the fourth data streams, the Y modulated symbol streams are obtained by performing third data processing on m third data streams, modulation is performed on each of the modulated symbol streams, the m third data streams are obtained by separately performing second data processing on m second data streams, the m second data streams are obtained by performing first data processing on a plurality of first data streams obtained through first forward error correction (FEC) encoding, and Y is 1. m is an integer greater than or equal to 1, a second FEC encoding is performed on each of the second data streams, and each codeword obtained through the second FEC encoding contains N bits, N=K+S, where K represents the number of information bits and S represents the number of parity bits, K is an integer greater than or equal to 1, and S is an integer greater than or equal to 1, each of the third data streams contains at least one bit sequence, each bit sequence containing P+W bits, P bits in each bit sequence are from the second data stream, and W bits in each bit sequence are added alignment markers, P=N×b, where b is an integer greater than or equal to 1, and a baud rate value of each of the modulated symbol streams is an integer multiple of a reference clock frequency value; 20. A data processing apparatus, wherein the synchronization unit is configured to perform frame synchronization for each of the fourth data streams based on an alignment marker in each of the fourth data streams.

71. 1. A data processing method comprising: performing first data processing on m first data streams obtained through first forward error correction (FEC) encoding to obtain m second data streams, where m is an integer greater than 1, each of the second data streams includes at least one first bit sequence, and each of the first bit sequences is [Equation 9] bits, and in each first bit sequence [Equation 10] The bits are from the first data stream, and in each first bit sequence [0011] the bit is the first marker added; performing second data processing on the m second data streams to obtain m third data streams, wherein the second data processing includes second FEC encoding, and each codeword obtained through the second FEC encoding includes N bits, where N=K+S, K represents the number of information bits, S represents the number of parity bits, K is an integer greater than or equal to 1, and S is an integer greater than or equal to 1; [0012] 、 [0013] where b is an integer greater than or equal to 1 and e is an integer greater than or equal to 1; performing third data processing on the m third data streams to obtain Y modulated symbol streams, where Y is an integer greater than or equal to 1, modulation is performed on each of the modulated symbol streams, and a baud rate value of each of the modulated symbol streams is an integer multiple of a reference clock frequency value.

72. Each of the third data streams includes at least one second bit sequence, each second bit sequence includes P+W bits, and P bits in each second bit sequence are [0014] 72. The method of claim 71, wherein W bits in each second bit sequence are second markers, and the second markers are obtained by performing second FEC encoding on the first markers, where P=N×b and W=N×e.

73. 73. The method of claim 71 or 72, wherein the value of the baud rate of each of the modulated symbol streams is an integer multiple of 156.25M.

74. 74. A method according to any one of claims 71 to 73, wherein the first marker comprises padding bits and / or a status field.

75. 75. The method of claim 71, further comprising: performing convolutional interleaving on each of the first data streams, the convolutional interleaving comprising delaying the input data stream based on r delay lines, r being an integer greater than 1, the delay lines comprising different numbers of storage units, the delay line with the smallest number of storage units comprising zero storage units, the difference between the number of storage units in every two adjacent delay lines being Q, each storage unit being for storing d bits, bits in the input data stream being input sequentially to the r delay lines based on their order numbers, d bits being input to each delay line only once, and d bits being output from each delay line only once, and r*d consecutive bits in the data stream output through the convolutional interleaving comprising d bits being output from each delay line, Q being an integer greater than or equal to 1, and d being an integer greater than or equal to 1.

76. 76. The method of claim 75, wherein the input / output switch corresponding to the convolutional interleave is in a 0th delay line whenever f bits are output through the convolutional interleave, and K×b is divisible by f.

77. 77. The method of claim 75 or 76, wherein r×d×c=K×b, and c is an integer greater than or equal to 1. [Request Item 78] [Number 15] 78. The method of any one of claims 71 to 77, wherein

79. N=148, K=140, and 5032×e is divisible by b. [0016] 79. The method of any one of claims 71 to 78, wherein is divisible by 7.

80. 80. The method of claim 79, wherein b = 629 × e.

81. KP4 encoding is used for the first FEC encoding and Hamming(148,140) is used for the second FEC encoding, or 81. The method of claim 80, wherein KP4 encoding is used for the first FEC encoding, and the second FEC encoding is performing a bitwise exclusive OR on every two consecutive information bits among the K=140 information bits to obtain 70 bits, and performing Hamming (78,70) encoding on the 70 bits to obtain S=8 parity bits, and the codeword having a length of 148 bits obtained through the second FEC encoding includes K=140 information bits and S=8 parity bits.

82. N=127, K=120, and 2159×e is divisible by b. [Equation 17] 79. The method of any one of claims 71 to 78, wherein is divisible by 3.

83. 83. The method of claim 82, wherein b = 2159 × e.

84. KP4 encoding is used for the first FEC encoding and Hamming(127,120) is used for the second FEC encoding, or 84. The method of claim 83, wherein KP4 encoding is used for the first FEC encoding, and the second FEC encoding is performing a bitwise exclusive OR on every two consecutive information bits among K=120 information bits to obtain 60 bits, and performing Hamming (67,60) encoding on the 60 bits to obtain S=7 parity bits, and the codeword having a length of 127 bits obtained through the second FEC encoding includes the K=120 information bits and the S=7 parity bits.

85. 85. The method of any one of claims 71 to 84, wherein the first data processing further comprises scrambling.

86. The third data processing further includes codeword interleaving, wherein the codeword interleaving is performed on t codewords to obtain an interleaved sequence including t×N bits, and an ith codeword among the t codewords is interleaved with a K-bit information sequence B i and the S-bit parity sequence P i where 0≦i≦t−1, and the interleaved sequence includes a first subsequence having t×K consecutive bits and a second subsequence having t×S consecutive bits, and the first subsequence is 0 , B 1 , B 2 , ..., B t-1 and the second sub-sequence comprises a total of t information sequences, P 0 , P 1 , P 2 , ..., P t-1 86. A method according to any one of claims 71 to 85, comprising a total of t parity sequences where

87. The baud rate of the modulated symbol stream is [Equation 18] Gbaud, and said value of said baud rate is [Equation 19] 87. The method of any one of claims 71 to 86, wherein a is an integer greater than or equal to 1, G represents 10^9, and M represents 10^6.

88. 88. The method of claim 71, 72, 73, 74, 75, 76, 77, 85, 86, or 87, wherein N=128, K=120, and the baud rate of the modulated symbol stream is 113.4375 Gbaud. [Request Item 89] [Number 20] 89. The method of claim 88, wherein:

90. performing third data processing on the m third data streams to obtain Y modulated symbol streams; performing channel interleaving on each group of eight third data streams among the m third data streams to obtain one fourth data stream, for a total of Y fourth data streams; and separately modulating the Y fourth data streams to obtain the Y modulated symbol streams.

91. The first marker in each of the second data streams: [Equation 21] a synchronization subsequence having a length of 128 bits, the synchronization subsequence starting at a start position within the first marker, [Equation 22] 91. The method of claim 90, wherein the bit is a bit. [Request Item 92] [Number 23] 92. The method of claim 91, wherein one group of eight third data streams among the m third data streams is obtained by performing second FEC encoding on one group of eight second data streams among the m second data streams, one fourth data stream obtained by performing channel interleaving on the group of eight third data streams includes a synchronization sequence having a length of 48 bits, the synchronization sequence having a length of 48 bits is continuous in the fourth data stream, and the synchronization sequence having a length of 48 bits includes a total of eight synchronization subsequences included in the group of eight second data streams, respectively.

93. 93. The method of claim 92, wherein the 48-bit values ​​of the synchronization sequence include 0x9A, 0x4A, 0x26, 0x65, 0xB5, and 0xD9.

94. the synchronization subsequence 0 included in the 0th second data stream in the group of 8 second data streams is 010110; the synchronization subsequence 1 included in a first second data stream in the group of eight second data streams is 011010; the synchronization subsequence 2 included in a second second data stream in the group of eight second data streams is 100111; a synchronization subsequence 3 included in a third second data stream in the group of eight second data streams is 010001; the synchronization subsequence 4 included in a fourth second data stream in the group of eight second data streams is 011010; a synchronization subsequence 5 included in a fifth second data stream in the group of eight second data streams is 011001; a synchronization subsequence 6 included in a sixth second data stream in the group of eight second data streams is 000110; 94. The method of claim 92 or 93, wherein the synchronization subsequence 7 included in the seventh second data stream in the group of eight second data streams is 101011.

95. a group of eight third data pieces among the m third data streams is obtained by performing second FEC encoding on a group of eight second data streams among the m second data streams; a 0th second data stream, a 1st second data stream, a 2nd second data stream, and a 3rd second data stream in the group of 8 second data streams each include a synchronization subsequence having a length of 8 bits; 91. The method of claim 90, wherein a fourth second data stream, a fifth second data stream, a sixth second data stream, and a seventh second data stream in the group of eight second data streams each include a synchronization subsequence having a length of four bits, and wherein the first two bits and the last two bits in the synchronization subsequence having a length of four bits are separated by two bits.

96. 96. The method of claim 95, wherein one fourth data stream obtained by performing channel interleaving on the group of eight third data streams includes a synchronization sequence having a length of 48 bits, the synchronization sequence having a length of 48 bits includes a total of eight synchronization subsequences respectively included in the group of eight second data streams, and the first 24 bits and the last 24 bits in the synchronization sequence having a length of 48 bits are separated by 8 bits.

97. 97. The method of claim 96, wherein the first 24-bit values ​​in the synchronization sequence having a length of 48 bits include 0x9A, 0x4A, and 0x26, and the last 24-bit values ​​in the synchronization sequence having a length of 48 bits include 0x65, 0xB5, and 0xD9.

98. a synchronization subsequence 0 included in the 0th second data stream in the group of 8 second data streams is 01011010; a synchronization subsequence 1 included in the first second data stream in the group of eight second data streams is 01101001; a synchronization subsequence 2 included in the second second data stream in the group of eight second data streams is 10010110; a synchronization subsequence 3 included in the third second data stream in the group of eight second data streams is 01001011; a synchronization subsequence 4 included in the fourth second data stream in the group of eight second data streams is 0110; a synchronization subsequence 5 included in the fifth second data stream in the group of eight second data streams is 0110; a synchronization subsequence 6 included in the sixth second data stream in the group of eight second data streams is 0011; 98. The method of any one of claims 95 to 97, wherein the synchronization subsequence 7 included in the seventh second data stream in the group of eight second data streams is 1001.

99. 91. The method of claim 71, wherein the first marker in each of the second data streams includes a synchronization subsequence having a length of 48 bits, the first 24 bits and the last 24 bits in the synchronization subsequence being separated by 8 bits.

100. 100. The method of claim 99, wherein the first 24-bit values ​​in the synchronization subsequence having a length of 48 bits include 0x9A, 0x4A, and 0x26, and the last 24-bit values ​​in the synchronization subsequence having a length of 48 bits include 0x65, 0xB5, and 0xD9.

101. N=128, K=120, and performing channel interleaving on each group of eight third data streams to obtain one fourth data stream; obtaining one inner codeword having a length of 128 bits from each of the third data streams in each group of eight third data streams to obtain a total of eight inner codewords; and taking two bits from each of the eight inner codewords in a round robin manner to obtain 1024 consecutive bits in the fourth data stream.

102. performing a first data processing on the m first data streams; 102. The method of any one of claims 71 to 101, comprising performing a cyclic shift on the m first data streams separately.

103. performing a first data processing on the m first data streams before separately performing a cyclic shift on the m first data streams; 103. The method of claim 102, comprising performing convolutional interleaving on the m first data streams separately.

104. Before separately performing cyclic shifts on the m first data streams, the method further comprises: performing convolutional interleaving separately on the m / 4 input data streams; 103. The method of claim 102, further comprising: dispersing each input convolutionally interleaved data stream to obtain four first data streams to obtain a total of the m first data streams.

105. Before separately performing cyclic shifts on the m first data streams, the method further comprises: performing convolutional interleaving separately on the m / 8 input data streams; 103. The method of claim 102, further comprising: dispersing each input convolutionally interleaved data stream to obtain eight first data streams in total to obtain the m first data streams.

106. 1. A data processing method comprising: performing fourth data processing on the received Y modulated symbol streams to obtain m fourth data streams, where Y is an integer greater than or equal to 1, demodulation is performed on each of the fourth data streams, and a baud rate value of each of the modulated symbol streams is an integer multiple of a reference clock frequency value; performing third data processing on m third data streams to obtain the Y modulated symbol streams, modulation is performed on each of the modulated symbol streams, and performing second data processing on m second data streams to obtain the m third data streams; and performing first data processing on m first data streams obtained through first forward error correction (FEC) encoding to obtain the m second data streams, where m is an integer greater than 1, and each of the second data streams includes at least one first bit sequence, and each first bit sequence is [0000] bits, and in each first bit sequence [Equation 25] The bits are from the first data stream, and in each first bit sequence [Equation 26] bits are added as a first marker, the second data processing includes a second FEC encoding, and each codeword obtained through the second FEC encoding includes N bits, where N=K+S, K represents the number of information bits, S represents the number of parity bits, K is an integer greater than or equal to 1, and S is an integer greater than or equal to 1; [0000] 、 [0000] where b is an integer greater than or equal to 1 and e is an integer greater than or equal to 1; and performing codeword synchronization and / or frame synchronization for each of said fourth data streams.

107. 1. A data processing device, comprising: a first data processing unit, a second data processing unit, and a third data processing unit; The first data processing unit is configured to perform first data processing on m first data streams obtained through first forward error correction (FEC) encoding to obtain m second data streams, where m is an integer greater than 1, and each of the second data streams includes at least one first bit sequence, and each of the first bit sequences is [0000] bits, and in each first bit sequence [Equation 30] The bits are from the first data stream, and in each first bit sequence [Equation 31] The bit is the first marker added, the second data processing unit is configured to perform second data processing on the m second data streams to obtain m third data streams, the second data processing including second FEC encoding, each codeword obtained through the second FEC encoding including N bits, N=K+S, K represents the number of information bits, S represents the number of parity bits, K is an integer greater than or equal to 1, and S is an integer greater than or equal to 1; [Equation 32] 、 [Equation 33] where b is an integer of 1 or greater, and e is an integer of 1 or greater, the third data processing unit is configured to perform third data processing on the m third data streams to obtain Y modulated symbol streams, where Y is an integer greater than or equal to 1, modulation is performed on each of the modulated symbol streams, and a baud rate value of each of the modulated symbol streams is an integer multiple of a reference clock frequency value.

108. Each of the third data streams includes at least one second bit sequence, each second bit sequence includes P+W bits, and the P bits in each second bit sequence are [Equation 34] 108. The data processing apparatus of claim 107, wherein the W bits in each second bit sequence are obtained by performing a second FEC encoding on the first markers, and wherein the W bits in each second bit sequence are second markers, and the second markers are obtained by performing a second FEC encoding on the first markers, and P=N×b and W=N×e.

109. 109. A data processing apparatus as claimed in claim 107 or 108, wherein said value of said baud rate of each of said modulated symbol streams is an integer multiple of 156.25M.

110. 110. A data processing apparatus according to any one of claims 107 to 109, wherein the first marker comprises padding bits and / or a status field.

111. 111. The data processing apparatus of claim 107, further comprising: convolutional interleaving performed on each of the first data streams, the convolutional interleaving comprising delaying the input data stream based on r delay lines, r being an integer greater than 1, the delay lines comprising different numbers of storage units, the delay line having the smallest number of storage units comprising zero storage units, the difference between the number of storage units in every two adjacent delay lines being Q, each storage unit being for storing d bits, bits in the input data stream being input sequentially to the r delay lines based on their order numbers, d bits being input to each delay line only once and d bits being output from each delay line only once, r*d consecutive bits in the data stream output through the convolutional interleaving comprising d bits being output from each delay line, Q being an integer greater than or equal to 1, and d being an integer greater than or equal to 1.

112. 112. A data processing apparatus as claimed in claim 111, wherein the input / output switch corresponding to said convolutional interleave is in a 0th delay line whenever f bits are output through said convolutional interleave, and K×b is divisible by f.

113. 113. A data processing device according to claim 111 or 112, wherein r×d×c=K×b, and c is an integer greater than or equal to 1. [Request Item 114] [Number 35] 114. A data processing device according to any one of claims 111 to 113, wherein:

115. N=148, K=140, and 5032×e is divisible by b. [Equation 36] 115. A data processing apparatus according to any one of claims 107 to 114, wherein is divisible by seven.

116. 116. A data processing device according to claim 115, wherein b = 629 x e.

117. KP4 encoding is used for the first FEC encoding and Hamming(148,140) is used for the second FEC encoding, or 117. The data processing apparatus of claim 116, wherein KP4 encoding is used for the first FEC encoding, and the second FEC encoding involves performing a bitwise exclusive OR on every two consecutive information bits among the K=140 information bits to obtain 70 bits, and performing Hamming (78,70) encoding on the 70 bits to obtain S=8 parity bits, and the codeword having a length of 148 bits obtained through the second FEC encoding includes the K=140 information bits and the S=8 parity bits.

118. N=127, K=120, and 2159×e is divisible by b. [Equation 37] 115. A data processing apparatus according to any one of claims 107 to 114, wherein is divisible by three.

119. 119. A data processing device according to claim 118, wherein b=2159×e.

120. KP4 encoding is used for the first FEC encoding and Hamming(127,120) is used for the second FEC encoding, or 120. The data processing apparatus of claim 119, wherein KP4 encoding is used for the first FEC encoding, and the second FEC encoding is performing a bitwise exclusive OR on every two consecutive information bits among the K=120 information bits to obtain 60 bits, and performing Hamming (67,60) encoding on the 60 bits to obtain S=7 parity bits, and the codeword having a length of 127 bits obtained through the second FEC encoding includes the K=120 information bits and the S=7 parity bits.

121. 121. A data processing apparatus according to any one of claims 107 to 120, wherein the first data processing further comprises scrambling.

122. The third data processing further includes codeword interleaving, wherein the codeword interleaving is performed on t codewords to obtain an interleaved sequence including t×N bits, and an ith codeword among the t codewords is interleaved with a K-bit information sequence B i and the S-bit parity sequence P i where 0≦i≦t−1, and the interleaved sequence includes a first subsequence having t×K consecutive bits and a second subsequence having t×S consecutive bits, and the first subsequence is 0 , B 1 , B 2 , ..., B t-1 and the second sub-sequence comprises a total of t information sequences, P 0 , P 1 , P 2 , ..., P t-1 122. A data processing apparatus as claimed in any one of claims 107 to 121, comprising a total of t parity sequences where

123. The baud rate of the modulated symbol stream is [Number 38] Gbaud, and said value of said baud rate is [0.39] 123. A data processing device according to any one of claims 107 to 122, wherein a is an integer greater than or equal to 1, G represents 10^9, and M represents 10^6.

124. 124. The data processing apparatus of claim 107, 108, 109, 110, 111, 112, 113, 121, 122, or 123, wherein N=128, K=120, and the baud rate of the modulated symbol stream is 113.4375 Gbaud. [Request Item 125] [Number 40] 125. The data processing device of claim 124,

126. The third data processing unit specifically comprises: performing channel interleaving on each group of eight third data streams among the m third data streams to obtain one fourth data stream, to obtain a total of Y fourth data streams; 126. A data processing apparatus according to any one of claims 107 to 125, configured to separately modulate the Y fourth data streams to obtain the Y modulated symbol streams.

127. The first marker in each of the second data streams: [Equation 41] a synchronization subsequence having a length of 128 bits, the synchronization subsequence starting at a start position within the first marker, [0.001] 127. A data processing device according to claim 126, wherein the data processing device is a bit. [Request Item 128] [Number 43] 128. The data processing apparatus of claim 127, wherein one group of eight third data streams among the m third data streams is obtained by performing second FEC encoding on one group of eight second data streams among the m second data streams, one fourth data stream obtained by performing channel interleaving on the group of eight third data streams includes a synchronization sequence having a length of 48 bits, the synchronization sequence having a length of 48 bits is continuous in the fourth data stream, and the synchronization sequence having a length of 48 bits includes a total of eight synchronization subsequences included in each of the groups of eight second data streams.

129. 129. A data processing apparatus as claimed in claim 128, wherein the 48-bit values ​​of the synchronization sequence include 0x9A, 0x4A, 0x26, 0x65, 0xB5 and 0xD9.

130. the synchronization subsequence 0 included in the 0th second data stream in the group of 8 second data streams is 010110; the synchronization subsequence 1 included in a first second data stream in the group of eight second data streams is 011010; the synchronization subsequence 2 included in a second second data stream in the group of eight second data streams is 100111; a synchronization subsequence 3 included in a third second data stream in the group of eight second data streams is 010001; the synchronization subsequence 4 included in a fourth second data stream in the group of eight second data streams is 011010; a synchronization subsequence 5 included in a fifth second data stream in the group of eight second data streams is 011001; a synchronization subsequence 6 included in a sixth second data stream in the group of eight second data streams is 000110; 130. A data processing apparatus as claimed in claim 128 or 129, wherein the synchronization subsequence 7 contained in a seventh second data stream in said group of eight second data streams is 101011.

131. a group of eight third data streams among the m third data streams is obtained by performing second FEC encoding on a group of eight second data streams among the m second data streams; a 0th second data stream, a 1st second data stream, a 2nd second data stream, and a 3rd second data stream in the group of 8 second data streams each include a synchronization subsequence having a length of 8 bits; 127. The data processing apparatus of claim 126, wherein a fourth second data stream, a fifth second data stream, a sixth second data stream, and a seventh second data stream in said group of eight second data streams each include a synchronization subsequence having a length of four bits, and the first two bits and the last two bits in said synchronization subsequence having a length of four bits are separated by two bits.

132. 132. A data processing device as described in claim 131, wherein one fourth data stream obtained by performing channel interleaving on said group of eight third data streams includes a synchronization sequence having a length of 48 bits, said synchronization sequence having a length of 48 bits includes a total of eight synchronization subsequences respectively included in said group of eight second data streams, and the first 24 bits and the last 24 bits in said synchronization sequence having a length of 48 bits are separated by 8 bits.

133. 133. The data processing apparatus of claim 132, wherein the first 24-bit values ​​in the synchronization sequence having a length of 48 bits include 0x9A, 0x4A, and 0x26, and the last 24-bit values ​​in the synchronization sequence having a length of 48 bits include 0x65, 0xB5, and 0xD9.

134. a synchronization subsequence 0 included in the 0th second data stream in the group of 8 second data streams is 01011010; a synchronization subsequence 1 included in the first second data stream in the group of eight second data streams is 01101001; a synchronization subsequence 2 included in the second second data stream in the group of eight second data streams is 10010110; a synchronization subsequence 3 included in the third second data stream in the group of eight second data streams is 01001011; a synchronization subsequence 4 included in the fourth second data stream in the group of eight second data streams is 0110; a synchronization subsequence 5 included in the fifth second data stream in the group of eight second data streams is 0110; a synchronization subsequence 6 included in the sixth second data stream in the group of eight second data streams is 0011; 134. A data processing apparatus according to any one of claims 131 to 133, wherein the synchronization subsequence 7 contained in the seventh second data stream in the group of eight second data streams is 1001.

135. 127. A data processing apparatus as claimed in any one of claims 107 to 126, wherein the first marker in each of the second data streams includes a synchronization subsequence having a length of 48 bits, the first 24 bits and the last 24 bits in the synchronization subsequence being separated by 8 bits.

136. 136. A data processing apparatus as claimed in claim 135, wherein the first 24-bit values ​​in the synchronization subsequence having a length of 48 bits include 0x9A, 0x4A, and 0x26, and the last 24-bit values ​​in the synchronization subsequence having a length of 48 bits include 0x65, 0xB5, and 0xD9.

137. N=128, K=120, and the third data processing unit specifically: obtaining one inner code word having a length of 128 bits from each of the third data streams in each group of eight third data streams to obtain a total of eight inner code words; 137. A data processing device according to any one of claims 126 to 136, configured to obtain 2 bits from each of the eight inner codewords in a round robin manner to obtain 1024 consecutive bits in the fourth data stream.

138. Specifically, the first data processing unit:

138. A data processing apparatus according to any one of claims 107 to 137, configured to perform cyclic shifting on said m first data streams separately.

139. Before the cyclic shift is separately performed on the m first data streams, the first data processing unit specifically:

139. A data processing apparatus according to claim 138, configured to perform convolutional interleaving on said m first data streams separately.

140. the data processing apparatus further includes a convolutional interleaving unit and a distributing unit, wherein the convolutional interleaving unit is configured to separately perform convolutional interleaving on the m / 4 input data streams before the cyclic shift is separately performed on the m first data streams; 139. The data processing apparatus of claim 138, wherein the distributing unit is configured to distribute each input convolutionally interleaved data stream to obtain four first data streams, to obtain the m first data streams in total.

141. the data processing apparatus further includes a convolutional interleaving unit and a distributing unit, wherein the convolutional interleaving unit is configured to separately perform convolutional interleaving on the m / 8 input data streams before the cyclic shift is separately performed on the m first data streams; 139. The data processing apparatus of claim 138, wherein the distributing unit is configured to distribute each input convolutionally interleaved data stream to obtain eight first data streams, to obtain the m first data streams in total.

142. 1. A data processing device, comprising: a data processing unit and a synchronization unit, the data processing unit is configured to perform fourth data processing on the received Y modulated symbol streams to obtain m fourth data streams, where Y is an integer greater than or equal to 1, demodulation is performed on each of the fourth data streams, and a baud rate value of each of the modulated symbol streams is an integer multiple of a reference clock frequency value; the Y modulated symbol streams are obtained by performing third data processing on m third data streams, where modulation is performed on each of the modulated symbol streams; the m third data streams are obtained by performing second data processing on m second data streams; and the m second data streams are obtained by performing first data processing on m first data streams obtained through first forward error correction (FEC) encoding, where m is an integer greater than 1, each of the second data streams includes at least one first bit sequence, and each first bit sequence is [0.0000] bits, and in each first bit sequence [Equation 45] The bits are from the first data stream, and in each first bit sequence [Equation 46] bits are added as a first marker, the second data processing includes a second FEC encoding, and each codeword obtained through the second FEC encoding includes N bits, where N=K+S, K represents the number of information bits, S represents the number of parity bits, K is an integer greater than or equal to 1, and S is an integer greater than or equal to 1; [Equation 47] 、 [Number 48] where b is an integer of 1 or greater, and e is an integer of 1 or greater, A data processing apparatus, wherein said synchronization unit is configured to perform codeword synchronization and / or frame synchronization for each of said fourth data streams.

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