Light emitting device, optical device and information processing device

Abstract

The light-emitting device comprises: a wiring substrate; a substrate mounted on the wiring substrate; a light source mounted on the substrate; a driving unit mounted on the wiring substrate and used to drive the light source; a wiring pattern on the wiring substrate, which is connected to the light source and extends from the back side of the substrate toward the driving unit; and a circuit element, which is arranged in an area on the substrate between the light source and the driving unit and overlaps with the wiring pattern when viewed from above.

Description

Technical Field

[0001] The present invention relates to a light emitting device, an optical device and an information processing device. Background Art

[0002] Patent document 1 describes an imaging device comprising: a light source; a light diffusion component having a plurality of lenses arranged adjacent to each other on a predetermined plane and diffusing light emitted by the light source; and an imaging element receiving reflected light from a subject after the light diffused by the light diffusion component, wherein the plurality of lenses are arranged so that the period of interference fringes in the diffused light is less than three pixels.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2018-54769 Summary of the invention

[0006] Problems to be solved by the invention

[0007] However, when it is desired to reduce the inductance of the circuit driving the light source, wiring such as bonding wires is provided on multiple side surfaces instead of only one side surface of the light source. In addition, circuit elements such as light receiving elements that detect the amount of light emitted from the light source are arranged close to the side surfaces of the light source.

[0008] In the above case, a structure is considered in which a circuit element is arranged on the driving part side of the light source, and wiring such as bonding wires are arranged on other side sides. However, when the circuit element is arranged between the light source and the driving part, the path of the wiring pattern connecting the light source and the driving part is limited, and the inductance of the circuit may increase.

[0009] At least one embodiment of the present invention provides a light-emitting device having a structure in which a circuit element is arranged between a light source and a driving unit, and compared with a structure in which a wiring pattern connecting the light source and the driving unit and the circuit element are both arranged on a wiring substrate, a path of the wiring pattern is not easily restricted by the circuit element.

[0010] Means for solving problems

[0011] The first embodiment of the present invention is a light-emitting device, comprising: a wiring substrate; a substrate mounted on the wiring substrate; a light source mounted on the substrate; a driving unit mounted on the wiring substrate and used to drive the light source; a wiring pattern on the wiring substrate, which is connected to the light source and extends from the back side of the substrate toward the driving unit; and a circuit element, which is arranged in an area on the substrate between the light source and the driving unit and overlaps with the wiring pattern when viewed from above.

[0012] A second aspect of the present invention is the light emitting device according to the first aspect, wherein the circuit element is connected to the wiring substrate outside the wiring pattern.

[0013] A third aspect of the present invention is the light emitting device according to the first or second aspect, wherein the circuit element is electrically connected to the wiring substrate, and the wiring pattern is wired so as not to avoid a connection portion between the circuit element and the wiring substrate.

[0014] The fourth embodiment of the present invention is a light-emitting device according to any one of the first to third embodiments, wherein the circuit element has a first electrode and a second electrode, the first electrode is connected to the wiring substrate on one side of the width direction of the wiring pattern, and the second electrode is connected to the wiring substrate on the other side of the width direction of the wiring pattern.

[0015] The fifth aspect of the present invention is a light-emitting device according to any one of the first to fourth aspects, wherein the light source is a light-emitting element array having a first side surface and a second side surface opposite to each other, and a third side surface and a fourth side surface connecting the first side surface and the second side surface and opposite to each other, the wiring extending from the upper surface electrode of the light-emitting element array toward the outside of the light-emitting element array is arranged at least on the first side surface and the second side surface, the circuit element is arranged on the substrate on the fourth side surface, and the wiring pattern extends from the fourth side surface toward the driving unit.

[0016] A sixth aspect of the present invention is the light emitting device according to the fifth aspect, wherein a wiring extending from an upper surface electrode of the light emitting element array toward an outside of the light emitting element array is provided on the third side surface.

[0017] A seventh aspect of the present invention is the light emitting device according to the fifth aspect, wherein another circuit element is provided on the substrate on the third side surface.

[0018] An eighth aspect of the present invention is the light emitting device according to the seventh aspect, wherein at least one of the circuit element and the other circuit element is a light receiving element.

[0019] A ninth aspect of the present invention is the light emitting device according to any one of the first to eighth aspects, wherein the base material is a member having a higher thermal conductivity than the wiring substrate.

[0020] A tenth aspect of the present invention is the light emitting device according to the ninth aspect, wherein the base material on the wiring substrate is made of ceramic.

[0021] The eleventh aspect of the present invention is a light emitting device according to any one of the fifth to eighth aspects, wherein a light diffusion member for diffusing light emitted from the light source toward the outside is provided on an emission path of the light emitting element array in the light source.

[0022] A twelfth aspect of the present invention is the light emitting device according to any one of the fifth to eighth aspects, wherein the light emitting element array includes a plurality of light emitting elements connected in parallel to each other.

[0023] The thirteenth embodiment of the present invention is a light-emitting device, which comprises: a wiring substrate; a light source and a driving unit for driving the light source, which are mounted on the wiring substrate; a wiring pattern on the wiring substrate, which connects the light source and the driving unit; a substrate, which is arranged between the light source and the driving unit so as to cross the wiring pattern; and a circuit element, which is arranged in an area on the substrate that overlaps with the wiring pattern when viewed from above.

[0024] The fourteenth aspect of the present invention is an optical device comprising: a light-emitting device of any one of the first to thirteenth aspects; and a light-receiving unit, which receives reflected light emitted from a light source possessed by the light-emitting device and reflected by an object to be measured, wherein the light-receiving unit outputs a signal corresponding to the time from when the light is emitted from the light source to when the light is received by the light-receiving unit.

[0025] The fifteenth embodiment of the present invention is an information processing device comprising: the optical device of the fourteenth embodiment; and a shape determination unit, which determines the three-dimensional shape of the object to be measured based on reflected light emitted from a light source possessed by the optical device, reflected by the object to be measured, and received by a light receiving unit possessed by the optical device.

[0026] A sixteenth aspect of the present invention is an information processing device according to the fifteenth aspect, comprising: an authentication processing unit that performs authentication processing related to the use of the device based on the determination result of the shape determination unit.

[0027] Effects of the Invention

[0028] According to the first and thirteenth aspects of the invention, compared with a structure in which both the wiring pattern connecting the light source and the driving unit and the circuit element are provided on a wiring substrate, the path of the wiring pattern is less likely to be restricted by the circuit element.

[0029] According to the second aspect of the invention, compared with the case where the connection is made to the wiring substrate inside the wiring pattern, the path of the wiring pattern is not affected.

[0030] According to the third aspect of the invention, the path of the wiring pattern is not affected by the connection portion between the circuit element and the wiring substrate.

[0031] According to the fourth aspect of the invention, the light emitting device can be easily miniaturized compared to a case where the first electrode and the second electrode are connected to the wiring substrate at one side in the width direction of the wiring pattern.

[0032] According to the fifth aspect of the invention, the inductance of the circuit is reduced compared to a case where the wiring extending outward from the upper surface electrode is provided only on one side surface of the light emitting element array.

[0033] According to the sixth aspect of the invention, the inductance of the circuit is reduced compared to a case where wiring extending outward from the upper surface electrode is provided only on both side surfaces of the light emitting element array.

[0034] According to the seventh aspect of the invention, the heat dissipation effect is better than in the case where no other circuit elements are provided.

[0035] According to the eighth aspect of the invention, the light emitted from the light source is detected.

[0036] According to the ninth aspect of the invention, the heat dissipation effect is better than when the thermal conductivity is the same as that of the wiring substrate.

[0037] According to the tenth aspect of the invention, the heat dissipation effect is better than when the structure is made of resin.

[0038] According to the eleventh aspect of the invention, compared with a configuration without a light diffusion member, light emitted from the light source is irradiated to a wider range.

[0039] According to the twelfth aspect of the invention, the intensity of light emitted simultaneously is higher than that of a structure in which the light emitting elements are driven individually.

[0040] According to the invention of a fourteenth aspect, an optical device capable of three-dimensional measurement is provided.

[0041] According to a fifteenth aspect of the invention, there is provided an information processing device capable of measuring a three-dimensional shape.

[0042] According to a sixteenth aspect of the invention, there is provided an information processing device equipped with an authentication process based on a three-dimensional shape. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 It is a diagram showing an example of an information processing device.

[0044] Figure 2 It is a block diagram illustrating the structure of an information processing device.

[0045] Figure 3 This is a top view of the light source.

[0046] Figure 4 This is a diagram illustrating a cross-sectional structure of one VCSEL in a light source.

[0047] Figure 5 is a diagram illustrating an example of a light diffusion component. Figure 5 The included (a) is a top view, Figure 5 (b) included is a cross-sectional view taken along the VB-VB line of (a).

[0048] Figure 6 This is a diagram showing an example of an equivalent circuit for driving a light source by low-side driving.

[0049] Figure 7 is a diagram for explaining a light emitting device to which the first embodiment is applied, Figure 7 The included (a) is a top view, Figure 7 (b) included is a cross-sectional view taken along line VIIB-VIIB of (a), Figure 7 (c) included is a cross-sectional view taken along line VIIC-VIIC of (a).

[0050] Figure 8 is a diagram for explaining a wiring pattern provided on a wiring substrate and a base material, Figure 8 (a) included is the surface of the wiring substrate, Figure 8 (b) included is the surface of the substrate, Figure 8 Included (c) is the back side of the substrate.

[0051] Fig. 9 1 is a diagram for explaining the relationship in which the PD is arranged outside the cathode wiring pattern for the light source in the wiring substrate. Fig. 9 (a) included is Example 1, Fig. 9 (b) included is Example 2.

[0052] Fig.10 is a diagram illustrating a light emitting device of Comparative Example 1, Fig.10 The included (a) is a top view, Fig.10 (b) included is a cross-sectional view taken along the XB-XB line of (a).

[0053] Fig.11 is a diagram illustrating a light emitting device of Comparative Example 2, Fig.11 The included (a) is a top view, Fig.11 (b) included is a cross-sectional view taken along the XIB-XIB line of (a).

[0054] Fig.12 FIG. 2 is a diagram for explaining a light emitting device to which the second embodiment is applied. Fig.12 The included (a) is a top view, Fig.12 (b) included is a cross-sectional view taken along the line XIIB-XIIB of (a), Fig.12 (c) included is a cross-sectional view taken along the XIIC-XIIC line of (a).

[0055] Fig.13 is a diagram for explaining a wiring pattern provided on a wiring substrate and a base material, Fig.13 (a) included is the surface of the wiring substrate, Fig.13 (b) included is the surface of the substrate, Fig.13 Included (c) is the back side of the substrate. DETAILED DESCRIPTION

[0056] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0057] Usually, an information processing device identifies whether a user who has accessed the information processing device is allowed to access, and allows the user to use the device, i.e., the information processing device, only if the user is authenticated as being allowed to access. So far, methods of authenticating users through passwords, fingerprints, irises, etc. have been used. Recently, a more secure authentication method is being sought. This method performs authentication based on a three-dimensional image such as the shape of the user's face.

[0058] Here, the information processing device is described by taking a portable information processing terminal as an example, and describes authenticating a user by recognizing the shape of a face captured as a three-dimensional image. It should be noted that the information processing device can be applied to information processing devices such as personal computers (PCs) other than portable information processing terminals.

[0059] Furthermore, the structure, function, method, etc. described in this embodiment can also be applied to the recognition of three-dimensional shapes other than the recognition of the face shape. In other words, it can also be applied to the recognition of the shape of objects other than the face. In addition, the distance to the object to be measured is not limited.

[0060] [First embodiment]

[0061] (Information Processing Device 1)

[0062] Figure 1 1 is a diagram showing an example of the information processing device 1. As described above, the information processing device 1 is a portable information processing terminal as an example.

[0063] The information processing device 1 includes a user interface unit (hereinafter referred to as a UI unit) 2 and an optical device 3 for acquiring a three-dimensional image. The UI unit 2 is, for example, an integrated structure of a display device that displays information to a user and an input device that inputs instructions for information processing through user operations. The display device is, for example, a liquid crystal display or an organic EL display, and the input device is, for example, a touch panel.

[0064] The optical device 3 includes a light emitting device 4 and a three-dimensional sensor (hereinafter, marked as a 3D sensor) 5. The light emitting device 4 irradiates light toward the object to be measured for obtaining a three-dimensional image, which is a face in the example described here. The 3D sensor 5 obtains the light irradiated by the light emitting device 4 and reflected by the face and returned. Here, it is assumed that a three-dimensional image of the face is obtained based on the so-called ToF (Time of Flight) method based on the flight time of light. In the following, even in the case of obtaining a three-dimensional image of the face, the face will be marked as the object to be measured. It should be noted that a three-dimensional image other than the face can also be obtained. Sometimes the acquisition of a three-dimensional image is marked as 3D sensing. The 3D sensor 5 is an example of a light receiving unit.

[0065] It should be noted that the information processing device 1 is configured as a computer including a CPU, ROM, RAM, etc. It should be noted that the ROM includes a non-volatile rewritable memory, such as a flash memory. In addition, the application program and constants stored in the ROM are loaded into the RAM and executed by the CPU, so that the information processing device 1 operates and performs various information processing.

[0066] Figure 2 It is a block diagram illustrating the structure of the information processing device 1.

[0067] The information processing device 1 includes the above-mentioned optical device 3, an optical device control unit 8, and a system control unit 9. The optical device control unit 8 controls the optical device 3. In addition, the optical device control unit 8 includes a shape determination unit 81. The system control unit 9 controls the information processing device 1 as a system. In addition, the system control unit 9 includes an authentication processing unit 91. In addition, the system control unit 9 is connected to the UI unit 2, the speaker 92, and the two-dimensional camera (in Figure 2 Marked as 2D camera) 93 and other connections.

[0068] The following will explain them one by one.

[0069] The light emitting device 4 provided in the optical device 3 includes a wiring substrate 10, a substrate 100, a light source 20, a light diffusion member 30, and a light receiving element for monitoring light quantity (in Figure 2 The light emitting device 4 is provided with passive components such as a resistor 6 and a capacitor 7 to operate the driver 50. It should be noted that although two capacitors 70 are shown, the number of the capacitors 70 may be one or more than two. In addition, the resistor 6 and the capacitor 7 may be multiple. Here, the light source 20, the PD 40, and the capacitor 70 other than the driver 50, the 3D sensor 5, the resistor 6, the capacitor 7, etc. may be marked as circuit components without distinction.

[0070] The light source 20 and the PD 40 are provided on a substrate 100 . The substrate 100 is made of an electrically insulating member. The substrate 100 , the drive unit 50 , the capacitor 70 , the resistor 6 , and the capacitor 7 are provided on a wiring board 10 .

[0071] The light source 20 is configured as a light emitting element array in which a plurality of light emitting elements are arranged two-dimensionally (see the following description). Figure 3 ). As an example, the light emitting element is a vertical cavity surface emitting laser element VCSEL (Vertical Cavity Surface Emitting Laser). In the following, the light emitting element is a vertical cavity surface emitting laser element VCSEL for example. And, the vertical cavity surface emitting laser element VCSEL is marked as VCSEL. The light source 20 emits light in a direction perpendicular to the surface of the wiring substrate 10 or the substrate 100. In the case of three-dimensional sensing by the ToF method, the light source 20 is required to emit a pulse light (hereinafter marked as an emitted light pulse) of, for example, more than 100 MHz and a rise time of less than 1ns through the driving unit 50. In addition, in the case of facial authentication as an example, the distance of light irradiation is about 10 cm to about 1 m. And, the range for measuring the 3D shape of the object to be measured is about 1 m square. Therefore, the light source 20 is required to have a large output and to efficiently dissipate the heat generated by the light source 20. It should be noted that the distance of light irradiation is marked as the measurement distance, and the range for measuring the 3D shape of the object to be measured is marked as the measurement range or the irradiation range. In addition, a surface virtually set within the measurement range or the irradiation range is marked as an irradiation surface.

[0072] PD40 is a photodiode of a pin type or the like, which outputs an electrical signal corresponding to the amount of light received (hereinafter referred to as the amount of light received), and is composed of a p-type Si region that serves as an anode, an i (intrinsic) type Si region, and an n-type Si region that serves as a cathode. Furthermore, an anode electrode is provided in the p-type Si region, and a cathode electrode is provided in the n-type Si region. It should be noted that PD40 is an example of a circuit element, and the anode electrode is an example of a first electrode, and the cathode electrode is an example of a second electrode.

[0073] The light diffuser 30 is arranged to cover the light source 20 and the PD40. That is, the light diffuser 30 is arranged at a predetermined distance from the light source 20 and the PD40 on the substrate 100 through the retaining portion 60 arranged on the substrate 100. It should be noted that the light diffuser 30 covering the light source 20 means that the light diffuser 30 is arranged on the emission path of the light emitted by the light source 20, and the light emitted by the light source 20 passes through the light diffuser 30. As described later, it refers to a state in which the light source 20 and the PD40 overlap with the light diffuser 30 when viewed from above. Here, the view from above refers to the state described later. Figure 3 , Figure 7 The PD 40 is arranged at a position covered by the light diffuser 30 so as to receive a part of the light emitted from the light source 20 and reflected by the light diffuser 30 .

[0074] The holding portion 60 includes walls 61A, 61B, 62A, and 62B that are provided to surround the light source 20 and the PD 40. Here, it is assumed that the outer shape of the substrate 100, the outer shape of the light diffusion component 30, and the outer shape of the holding portion 60 are the same. Therefore, the outer edges of the substrate 100, the light diffusion component 30, and the holding portion 60 overlap. It should be noted that the outer shape of the substrate 100 may also be larger than the outer shape of the light diffusion component 30 and the outer shape of the holding portion 60.

[0075] The wiring substrate 10 , the base material 100 , the light source 20 , the light diffusion member 30 , the drive unit 50 , and the holding unit 60 in the light emitting device 4 will be described in detail later.

[0076] The 3D sensor 5 has a plurality of light receiving units. For example, each light receiving unit is configured to receive a pulsed reflected light (hereinafter, referred to as a light receiving pulse) formed by the object to be measured reflecting the outgoing light pulse from the light source 20, and to store a charge corresponding to the time until the light is received in each light receiving unit. The 3D sensor 5 is a device of CMOS structure, wherein each light receiving unit has two gates and a charge storage unit corresponding to the two gates. Furthermore, by alternately applying pulses to the two gates, the generated photoelectrons are transmitted to either of the two charge storage units at a high speed. Charges corresponding to the phase difference between the outgoing light pulse and the light receiving pulse are stored in the two charge storage units. Furthermore, the 3D sensor 5 outputs a digital value corresponding to the phase difference between the outgoing light pulse and the light receiving pulse as a signal for each light receiving unit via an AD converter. That is, the 3D sensor 5 outputs a signal corresponding to the time from the light being emitted from the light source 20 to the light being received by the 3D sensor 5. It should be noted that the AD converter can be provided with the 3D sensor 5 or can be provided outside the 3D sensor 5.

[0077] As described above, in the case of facial authentication, the light source 20 is required to irradiate light within an irradiation range of about 10 cm to about 1 m and about 1 m square. In addition, the 3D sensor 5 receives reflected light from the object to be measured, thereby measuring the 3D shape of the object to be measured. Therefore, the light source 20 is required to have a large output. Therefore, the heat is required to be efficiently dissipated from the light source 20.

[0078] The shape specifying unit 81 of the optical device control unit 8 acquires the digital value obtained for each light receiving unit from the 3D sensor 5, calculates the distance to the object to be measured for each light receiving unit, and specifies the 3D shape of the object to be measured based on the calculated distance.

[0079] When the determination result determined by the shape determination unit 81, i.e., the 3D shape of the object to be measured, is a 3D shape pre-stored in a ROM or the like, the authentication processing unit 91 of the system control unit 9 performs authentication processing related to the use of the information processing device 1. It should be noted that, as an example, the authentication processing related to the use of the information processing device 1 refers to processing to determine whether to allow the use of the present device, i.e., the information processing device 1. For example, when it is determined that the 3D shape of the face of the object to be measured is consistent with the face shape stored in a storage unit such as a ROM, the use of the information processing device 1 including various applications provided by the information processing device 1 is permitted.

[0080] As an example, the shape identification unit 81 and the authentication processing unit 91 are constituted by a program. Alternatively, they may be constituted by an integrated circuit such as an ASIC or FPGA. Furthermore, they may be constituted by software such as a program and an integrated circuit such as an ASIC.

[0081] exist Figure 2 , the optical device 3, the optical device control unit 8, and the system control unit 9 are shown separately, but the system control unit 9 may include the optical device control unit 8. In addition, the optical device control unit 8 may be included in the optical device 3. Furthermore, the optical device 3, the optical device control unit 8, and the system control unit 9 may be integrally configured.

[0082] Next, before describing the light emitting device 4 , the light source 20 , the light diffusion member 30 , the drive unit 50 , and the capacitor 70 constituting the light emitting device 4 will be described.

[0083] (Structure of Light Source 20)

[0084] Figure 3 It is a top view of the light source 20. The light source 20 is composed of a plurality of VCSELs arranged in a two-dimensional array. That is, the light source 20 is configured as a light-emitting element array with VCSELs as light-emitting elements. The right direction of the paper is set as the x direction, and the upper direction of the paper is set as the y direction. The direction orthogonal to the x direction and the y direction counterclockwise is set as the z direction. It should be noted that the x, y, and z directions in each of the accompanying drawings are the same. It should be noted that the surface refers to the surface on the +z direction side, and the back surface refers to the surface on the -z direction side. The same applies to other situations.

[0085] VCSEL is a light emitting element which is stacked on a semiconductor substrate 200 (see below). Figure 4) is provided with an active area serving as a light emitting area between the lower multilayer film reflector and the upper multilayer film reflector, and the laser is emitted in a direction perpendicular to the semiconductor substrate 200. Thus, two-dimensional arraying is easily performed. As an example, the number of VCSELs possessed by the light source 20 is 100 to 1000. It should be noted that a plurality of VCSELs are connected in parallel to each other and driven in parallel. It should be noted that the number of VCSELs mentioned above is an example, and the number of VCSELs can be set according to the measurement distance and the measurement range.

[0086] On the surface of the light source 20, an anode electrode 218 common to a plurality of VCSELs is provided (see the following description). Figure 4 A cathode electrode 214 is provided on the back side of the light source 20 (see Figure 4 ). That is, a plurality of VCSELs are connected in parallel. Compared with the case where a VCSEL is driven individually, by driving a plurality of VCSELs connected in parallel, high-intensity light is emitted at the same time and irradiates the object to be measured.

[0087] Here, the shape of the light source 20 when viewed from above, that is, the planar shape is a quadrilateral. And, the side on the +y direction side is marked as side 21A, the side on the -y direction side is marked as side 21B, the side on the -x direction side is marked as side 22A, and the side on the +x direction side is marked as side 22B. Side 21A is opposite to side 21B. Side 22A and side 22B are connected to side 21A and side 21B, respectively, and are opposite to each other. Here, side 21A is an example of a first side, side 21B is an example of a second side, side 22A is an example of a third side, and side 22B is an example of a fourth side.

[0088] (VCSEL structure)

[0089] Figure 4 1 is a diagram for explaining a cross-sectional structure of one VCSEL in the light source 20. The VCSEL is a VCSEL having a λ resonator structure. The upward direction on the paper is defined as the z direction.

[0090] The VCSEL is composed of the following structures stacked in sequence on a semiconductor substrate 200 such as n-type GaAs: n-type lower distributed Bragg reflector (DBR: Distributed Bragg Reflector) 202, which is composed of AlGaAs layers with different Al compositions alternately overlapped; an active region 206, which includes a quantum well layer sandwiched by an upper spacer layer and a lower spacer layer; and a p-type upper distributed Bragg reflector 208, which is composed of AlGaAs layers with different Al compositions alternately overlapped. Hereinafter, the distributed Bragg reflector is marked as DBR.

[0091] The n-type lower DBR 202 is a stacked body of Al0.9Ga0.1As layers and GaAs layers in pairs, each layer has a thickness of λ / 4nr (where λ is the oscillation wavelength and nr is the refractive index of the medium), and these layers are alternately stacked for 40 cycles. The carrier concentration after doping with n-type impurities, i.e., silicon, is, for example, 3×10 18 cm -3 .

[0092] The active region 206 is formed by stacking a lower spacer layer, a quantum well active layer and an upper spacer layer. For example, the lower spacer layer is an undoped Al0.6Ga0.4As layer, the quantum well active layer is an undoped InGaAs quantum well layer and an undoped GaAs barrier layer, and the upper spacer layer is an undoped Al0.6Ga0.4As layer.

[0093] The p-type upper DBR 208 is a stacked body of Al0.9Ga0.1As layers and GaAs layers in pairs, each layer has a thickness of λ / 4nr, and these layers are alternately stacked in 29 cycles. The carrier concentration after doping with p-type impurities, i.e., carbon, is, for example, 3×10 18 cm -3 Preferably, a contact layer composed of p-type GaAs is formed at the uppermost layer of the upper DBR 208 , and a current confinement layer 210 of p-type AlAs is formed at the lowermost layer of the upper DBR 208 or inside thereof.

[0094] A cylindrical mesa M is formed on the semiconductor substrate 200 by etching the semiconductor layers stacked from the upper DBR 208 to the lower DBR 202. As a result, the current limiting layer 210 is exposed to the side of the mesa M. Through the oxidation process, an oxidized region 210A oxidized from the side of the mesa M and a conductive region 210B surrounded by the oxidized region 210A are formed in the current limiting layer 210. It should be noted that in the oxidation process, the oxidation rate of the AlAs layer is faster than that of the AlGaAs layer, and the oxidized region 210A is oxidized from the side of the mesa M toward the inside at a substantially constant rate, so the planar shape of the conductive region 210B becomes a shape reflecting the outer shape of the mesa M, that is, a circle, and its center is roughly consistent with the axial direction (single-point dashed line) of the mesa M. In the present embodiment, the mesa M forms a columnar structure.

[0095] A ring-shaped p-side electrode 212 made of a stacked metal such as Ti / Au is formed on the top layer of the mesa M. The p-side electrode 212 is in ohmic contact with a contact layer provided on the upper DBR 208. The inner side of the ring-shaped p-side electrode 212 becomes a light emission port 212A for emitting laser light to the outside. That is, in the VCSEL, light is emitted in a direction perpendicular to the semiconductor substrate 200, and the axial direction of the mesa M becomes the optical axis. Furthermore, on the back side of the semiconductor substrate 200, a cathode electrode 214 is formed as an n-side electrode. It should be noted that the surface of the upper DBR 208 located on the inner side of the p-side electrode 212 is the light emission surface. That is, the optical axis direction of the VCSEL is the light emission direction.

[0096] Furthermore, an insulating layer 216 is provided to cover the surface of the mesa M except for the portion of the p-side electrode 212 connected to the anode electrode (the anode electrode 218 described later) and the light emission port 212A. Furthermore, except for the light emission port 212A, the anode electrode 218 is provided to be in ohmic contact with the p-side electrode 212. It should be noted that the anode electrode 218 is provided to be shared by a plurality of VCSELs. That is, the p-side electrodes 212 of the plurality of VCSELs constituting the light source 20 are connected in parallel through the anode electrode 218. It should be noted that the anode electrode 218 is an example of an upper surface electrode of the light emitting element array.

[0097] It should be noted that the VCSEL can oscillate in a single transverse mode or in multiple transverse modes. As an example, the light output of a VCSEL is 4 mW to 8 mW. Therefore, for example, when the light source 20 is composed of 500 VCSELs, the light output of the light source 20 is 2 W to 4 W. In such a high-output light source 20, the heat generated by the light source 20 is large.

[0098] (Structure of the light diffusion member 30)

[0099] Figure 5 It is a diagram for explaining an example of the light diffusion member 30 . Figure 5 (a) is a top view, Figure 5 (b) is Figure 5 (a) is a cross-sectional view of the VB-VB line. Figure 5 In (a), the right direction of the paper is set as the x direction, and the upward direction of the paper is set as the y direction. The direction that is counterclockwise orthogonal to the x direction and the y direction is set as the z direction. Figure 5 In (b), the right direction of the paper is the x direction, and the upper direction of the paper is the z direction.

[0100] like Figure 5As shown in (b), the light diffusion component 30 has a resin layer 32 formed with concave and convex portions for diffusing light on the back side of a glass substrate 31 having two parallel and flat surfaces. The light diffusion component 30 further expands the diffusion angle of light incident from the VCSEL of the light source 20 and emits the light. That is, the concave and convex portions formed on the resin layer 32 of the light diffusion component 30 refract or scatter the light so that the diffusion angle β of the emitted light is greater than the diffusion angle α of the incident light. That is, as Figure 5 As shown, the diffusion angle β of the light emitted from the light diffuser 30 through the light diffuser 30 is greater than the diffusion angle α of the light emitted from the VCSEL (α<β). Therefore, when the light diffuser 30 is used, the area of ​​the irradiated surface irradiated by the light emitted by the light source 20 is expanded compared to the case where the light diffuser 30 is not used. In addition, the light density of the irradiated surface is reduced. It should be noted that light density refers to the radiant illuminance per unit area, and the spread angles α and β are the full width at half maximum (FWHM).

[0101] Furthermore, the light diffuser 30 has a plane shape of, for example, a quadrilateral, a width Wx in the x direction and a longitudinal width Wy in the y direction of 1 mm to 10 mm, and a thickness td in the z direction of 0.1 mm to 1 mm. Furthermore, if the light diffuser 30 has the above size and shape, a light diffuser particularly suitable for facial authentication of a portable information processing terminal and measurement at a relatively close distance of about several meters is provided. It should be noted that the plane shape of the light diffuser 30 may also be other shapes such as a polygon or a circle.

[0102] (Driver 50 and Capacitor 70)

[0103] When it is desired to drive the light source 20 at a higher speed, low-side driving can be performed. Low-side driving refers to a structure in which a driving element such as a MOS transistor is located on the downstream side of a current path relative to a driving object such as a VCSEL. Conversely, a structure in which a driving element is located on the upstream side is called high-side driving.

[0104] Figure 6 is a diagram showing an example of an equivalent circuit for driving the light source 20 by low-side driving. Figure 6 , a VCSEL of the light source 20 , a driving unit 50 , a capacitor 70 , a power source 82 , a PD 40 , and a detection resistor 41 for detecting a current flowing through the PD 40 are shown.

[0105] The power supply 82 is provided at Figure 2 The optical device control unit 8 is shown. The power supply 82 generates a DC voltage with a + side as a power supply potential and a - side as a ground potential. The power supply potential is supplied to a power supply line 83, and the ground potential is supplied to a ground line 84.

[0106] As described above, the light source 20 is composed of a plurality of VCSELs connected in parallel. Figure 4 ) is connected to the power line 83.

[0107] The driving unit 50 includes an n-channel MOS transistor 51 and a signal generating circuit 52 for turning the MOS transistor 51 on and off. The drain of the MOS transistor 51 is connected to the cathode electrode 214 (see Figure 4 ) is connected. The source of the MOS transistor 51 is connected to the ground line 84. In addition, the gate of the MOS transistor 51 is connected to the signal generating circuit 52. That is, the MOS transistor 51 of the VCSEL and driving unit 50 is connected in series between the power supply line 83 and the ground line 84. The signal generating circuit 52 generates an "H level" signal that turns the MOS transistor 51 on and an "L level" signal that turns the MOS transistor 51 off under the control of the optical device control unit 8.

[0108] One terminal of the capacitor 70 is connected to the power supply line 83, and the other terminal is connected to the ground line 84. When there are a plurality of capacitors 70, the plurality of capacitors 70 are connected in parallel. It should be noted that the capacitor 70 is, for example, an electrolytic capacitor, a ceramic capacitor, or the like.

[0109] The cathode electrode of the PD 40 is connected to the power line 83, and the anode electrode is connected to one terminal of the detection resistor element 41. In addition, the other terminal of the detection resistor element 41 is connected to the ground line 84. That is, the PD 40 and the detection resistor element 41 are connected in series between the power line 83 and the ground line 84. In addition, the connection point between the PD 40 and the detection resistor element 41, that is, the output terminal 42, is connected to the optical device control unit 8.

[0110] Next, a low-side drive method, that is, a method of driving the light source 20 will be described.

[0111] First, assume that the signal generated by the signal generating circuit 52 in the driving unit 50 is at an "L level". In this case, the MOS transistor 51 is in an off state. That is, no current flows between the source and the drain of the MOS transistor 51. Therefore, no current flows in the VCSELs connected in series. The VCSELs do not emit light.

[0112] At this time, capacitor 70 is charged by power supply 82. That is, one terminal of capacitor 70 connected to power supply line 83 is at power supply potential, and the other terminal connected to ground line 84 is at ground potential. Capacitor 70 accumulates charge determined by capacitance, power supply voltage (=power supply potential - ground potential) and time.

[0113] Next, when the signal generated by the signal generating circuit 52 in the driving unit 50 becomes "H level", the MOS transistor 51 changes from the off state to the on state. Then, the charge accumulated in the capacitor 70 is discharged, and current flows through the MOS transistor 51 and the VCSEL connected in series, causing the VCSEL to emit light.

[0114] When the signal generated by the signal generating circuit 52 in the driving unit 50 becomes "L level", the MOS transistor 51 changes from the on state to the off state. As a result, the VCSEL stops emitting light. Then, the power supply 82 resumes accumulating charge in the capacitor 70.

[0115] As described above, whenever the signal output from the signal generating circuit 52 changes to the "L level" and the "H level", the MOS transistor 51 is repeatedly turned off and on, and the VCSEL repeatedly performs non-light emission and light emission in the light emission stopping state. That is, light pulses are emitted from the VCSEL. The repeated on and off of the MOS transistor 51 is sometimes referred to as a switch. Here, Figure 6 The current path shown in the equivalent circuit of , which is composed of the light source 20 , the MOS transistor 51 , the capacitor 70 , etc. and leads to the light source 20 , is marked as a circuit or circuit for driving the light source 20 .

[0116] It should be noted that the capacitor 70 may be omitted and charge (current) may be directly supplied from the power supply 82 to the VCSEL. However, by accumulating charge in the capacitor 70, the accumulated charge is discharged when the MOS transistor 51 changes from off to on, and current is quickly supplied to the VCSEL, thereby shortening the rise time of the light emission of the VCSEL.

[0117] PD40 is reversely connected between the power line 83 and the ground line 84 via the detection resistor element 41. Therefore, no current flows in the state where no light is irradiated. As described above, when PD40 receives a part of the light reflected by the light diffusion component 30 in the light emitted by the VCSEL, a current corresponding to the amount of light received flows through PD40. Therefore, the current flowing through PD40 is measured as the voltage of the output terminal 42, and the light intensity of the light source 20 is detected. Therefore, the optical device control unit 8 controls according to the amount of light received by PD40 so that the light intensity of the light source 20 is a predetermined light intensity. For example, when the light intensity of the light source 20 is less than the predetermined light intensity, the optical device control unit 8 increases the amount of charge accumulated in the capacitor 70 by increasing the power supply potential of the power supply 82, and increases the current flowing through the VCSEL. On the other hand, when the light intensity of the light source 20 is greater than the predetermined light intensity, the power supply potential of the power supply 82 is reduced, the amount of charge accumulated in the capacitor 70 is reduced, and the current flowing through the VCSEL is reduced. In this way, the light intensity of the light source 20 is controlled.

[0118] In addition, when the amount of light received by the PD 40 is extremely low, the light diffusion component 30 may fall off or be damaged, and the light emitted by the light source 20 may directly irradiate the outside. In such a case, the light intensity of the light source 20 can be suppressed by the optical device control unit 8. For example, the light emission from the light source 20 is stopped, that is, the light irradiation to the object to be measured is stopped.

[0119] As described above, PD40 is provided to detect the light intensity of the light source 20. Therefore, the farther PD40 is arranged from the light source 20, the smaller the amount of light received, and the lower the detection sensitivity of the light intensity of the light source 20. Therefore, PD40 can be arranged close to the light source 20. That is, PD40 is an example of a circuit element that is expected to be arranged close to the light source 20. In addition, if PD40 is arranged close to the light source 20, the area of ​​the light diffusion component 30 can be smaller. That is, the expensive light diffusion component 30 is miniaturized, and the light emitting device 4 becomes cheap.

[0120] (Light emitting device 4)

[0121] Next, the light emitting device 4 will be described in detail.

[0122] Figure 7 It is a diagram for explaining a light emitting device 4 to which the first embodiment is applied. Figure 7 (a) is a top view, Figure 7 (b) is Figure 7 (a) is a cross-sectional view taken along line VIIB-VIIB, Figure 7 (c) is Figure 7 (a) is a cross-sectional view of the VIIC-VIIC line. Figure 7 In (a), the right direction of the paper is set as the x direction, and the upward direction of the paper is set as the y direction. The direction that is counterclockwise orthogonal to the x direction and the y direction is set as the z direction. Figure 7 In (b) and (c), the right direction of the paper is the x direction, and the upper direction of the paper is the z direction. This is also the same in similar drawings shown below.

[0123] like Figure 7 As shown in (b) and (c) of FIG. 1 , the light emitting device 4 includes a substrate 100 and a driving unit 50 on a wiring substrate 10. In addition, a light source 20, a PD 40, and a holding unit 60 are provided on the substrate 100. A light diffusion component 30 is provided on the holding unit 60. Figure 7 As shown in (a) and (c), the light source 20 and the PD 40 are covered by the light diffusion member 30. Therefore, the PD 40 receives a portion of the light emitted by the light source 20 that is reflected by the back surface of the light diffusion member 30. It should be noted that the holding portion 60 may also be provided on the wiring substrate 10.

[0124] And, if Figure 7As shown in (a), in the light emitting device 4, the light source 20, the PD 40, and the driving unit 50 are arranged linearly in the x direction. Furthermore, in the light emitting device 4, even if the PD 40 is arranged between the light source 20 and the driving unit 50 and the PD 40 is close to the light source 20, the path of the wiring pattern (the cathode wiring pattern 12 for the light source described later) connecting the light source 20 and the driving unit 50 is not restricted by the PD 40.

[0125] That is, in the light-emitting device 4, the light source 20 and the PD 40 are mounted on a substrate 100 provided with a wiring pattern, and the substrate 100 is mounted on a wiring substrate 10 provided with a wiring pattern connected to the driving unit 50, so that the wiring patterns are three-dimensionally crossed, thereby making the path of the wiring pattern connecting the light source 20 and the driving unit 50 not restricted by the PD 40.

[0126] The details are described below.

[0127] The wiring substrate 10 is, for example, a three-layer multilayer substrate. That is, the wiring substrate 10 has a first conductive layer, a second conductive layer, and a third conductive layer from the side on which the substrate, the driving unit 50, etc. are mounted. Furthermore, an insulating layer is provided between the first conductive layer and the second conductive layer, and between the second conductive layer and the third conductive layer. For example, the third conductive layer is set as a power line 83, and the second conductive layer is set as a ground line 84. In addition, through the first conductive layer, a light source anode wiring pattern 11 and a light source cathode wiring pattern 12 are formed, which constitute a part of the current path to the light source 20, and a PD anode wiring pattern 13 and a PD cathode wiring pattern 14 are formed, which constitute a part of the current path to the PD 40. Furthermore, a wiring pattern for connecting circuit components such as the capacitor 70, the resistor 6, and the capacitor 7 is formed by the first conductive layer, but the illustration of these circuit components is omitted. In this way, by configuring the wiring substrate 10 as a multilayer substrate, configuring the power line 83 as the third conductive layer, and configuring the ground line 84 as the second conductive layer, it is easy to suppress the variation of the power supply potential and the ground potential. It should be noted that the paths through which current flows, such as the anode wiring pattern 11 for light source, the cathode wiring pattern 12 for light source, the anode wiring pattern 13 for PD, and the cathode wiring pattern 14 for PD, are marked as wiring patterns. In addition, the wiring pattern composed of the first conductive layer is electrically connected to the second conductive layer or the third conductive layer via a through hole. The through hole is, for example, a conductive portion formed by embedding a conductive material in a hole provided to penetrate the wiring substrate 10 in the thickness direction.

[0128] The first conductive layer, the second conductive layer, and the third conductive layer are made of conductive materials such as metals such as copper (Cu) and silver (Ag) or conductive pastes containing these metals, etc. The insulating layer is made of epoxy resin, ceramics, etc., for example.

[0129] The substrate 100 is made of an electrically insulating material. It should be noted that, since the light source 20 is provided on the substrate 100, the substrate 100 can be made of an electrically insulating component having a higher thermal conductivity than the wiring substrate 10, i.e., a heat dissipation component. The electrically insulating heat dissipation component includes ceramics such as silicon nitride and aluminum nitride. If the substrate 100 is a heat dissipation component, the heat generated by the light source 20 is easily conducted to the holding portion 60 and the light diffusion component 30 via the substrate 100 and dissipated, thereby improving the heat dissipation efficiency.

[0130] On the surface of the substrate 100, there are provided a light source anode wiring pattern 111F and a light source cathode wiring pattern 112F, which constitute a part of the current path to the light source 20, and a PD anode wiring pattern 113F and a PD cathode wiring pattern 114F, which constitute a part of the current path to the PD 40. On the back side of the substrate 100, there are also provided a light source anode wiring pattern 111B and a light source cathode wiring pattern 112B, which constitute a part of the current path to the light source 20, and a PD anode wiring pattern 113B and a PD cathode wiring pattern 114B, which constitute a part of the current path to the PD 40 (see the following). Figure 8 ). In addition, on the front and back sides of the substrate 100, wiring patterns with the same number are connected through through holes. Figure 7 As shown in (b), the anode wiring pattern 111F for the light source provided on the surface is connected to the anode wiring pattern 111B for the light source provided on the back through a through hole 111V. The through hole is marked by marking the number of the wiring pattern with "V". The through hole here is, for example, a conductive portion formed by embedding a conductive material in a hole provided through the substrate 100, and electrically connects the wiring pattern on the surface with the wiring pattern on the back. By connecting the wiring patterns using multiple through holes, the inductance of the circuit is reduced.

[0131] Furthermore, the cathode wiring pattern 112F for light source of the substrate 100 and the cathode electrode 214 of the light source 20 (see Figure 4 ) are connected by a conductive adhesive or the like. Also, the light source anode wiring pattern 111F of the substrate 100 is connected to the anode electrode 218 of the light source 20 (see Figure 4 ) are connected by bonding wires 23A, 23B, 23C on the side surfaces 21A, 21B, 22A of the light source 20. Here, the anode wiring pattern 111F for the light source is arranged on the side surfaces 21A, 21B, 22A of the light source 20, and is not arranged on the side surface 22B of the light source 20. In this way, a bonding wire connecting the anode electrode 218 and the anode wiring pattern 111F for the light source is not arranged on the side surface 22B of the light source 20. Therefore, PD40, which is an example of a circuit element that is expected to be arranged close to the light source 20, is arranged close to the light source 20.

[0132] In the above, the anode electrode 218 of the light source 20 is connected to the anode wiring pattern 111F for the light source by bonding wires (bonding wires 23A, 23B, 23C) on the three side surfaces (side surfaces 21A, 21B, 22A) of the light source 20. Alternatively, the anode electrode 218 of the light source 20 is connected to the anode wiring pattern 111F for the light source by bonding wires on at least two side surfaces of the light source 20. It should be noted that, compared with the case where the anode electrode 218 of the light source 20 is connected to the anode wiring pattern 111F for the light source by bonding wires on two side surfaces, the inductance of the circuit is reduced when the three side surfaces are connected. It should be noted that, it is also possible to connect the anode electrode 218 of the light source 20 to the anode wiring pattern 111F for the light source by bonding wires on two side surfaces, and to set other circuit elements on the substrate 100 on the other side surface (side surface 22A). As an example, the other circuit element is a temperature sensor. By setting other circuit elements, the inductance of the circuit can be reduced.

[0133] Note that in the PD 40 , the cathode electrode of the PD 40 is bonded to the PD cathode wiring pattern 114F of the substrate 100 by a conductive adhesive, and the anode electrode of the PD 40 is connected to the PD anode wiring pattern 113F of the substrate 100 by a bonding wire 23D.

[0134] Furthermore, the light source anode wiring pattern 11 and the light source cathode wiring pattern 12 provided on the wiring substrate 10 are respectively connected to the light source anode wiring pattern 111B and the light source cathode wiring pattern 112B on the back side of the substrate 100. Similarly, the PD anode wiring pattern 13 and the PD cathode wiring pattern 14 provided on the wiring substrate 10 are respectively connected to the PD anode wiring pattern 113B and the PD cathode wiring pattern 114B on the back side of the substrate 100. It should be noted that the connection between the wiring pattern of the wiring substrate 10 and the wiring pattern of the substrate 100 is performed by a conductive adhesive or the like.

[0135] And, if Figure 7 As shown in (b), in the cross-sectional view at the line VIIB-VIIB offset from the center in the y direction to the -y direction, the anode wiring pattern 11 for the light source of the wiring substrate 10 is connected to the anode wiring pattern 111B for the light source on the back side of the substrate 100. The anode wiring pattern 111B for the light source of the substrate 100 is connected to the anode wiring pattern 111F for the light source on the surface of the substrate 100 via the through hole 111V. Furthermore, the anode wiring pattern 111F for the light source of the substrate 100 is connected to the anode electrode 218 of the light source 20 (see FIG. 21) via the bonding wires 23A, 23B, and 23C. Figure 4 )connect.

[0136] Similarly, the PD cathode wiring pattern 14 of the wiring substrate 10 is connected to the PD cathode wiring pattern 114B on the back surface of the substrate 100. The PD cathode wiring pattern 114B of the substrate 100 is connected to the PD cathode wiring pattern 114F on the surface of the substrate 100 via the through hole 114V. Furthermore, the PD cathode wiring pattern 114F of the substrate 100 is connected to the cathode electrode of the PD 40.

[0137] That is, in the cross section of line VIIB-VIIB, the anode wiring pattern 11 for light source of the wiring substrate 10, the anode wiring pattern 111B for light source on the back side of the substrate 100, and the anode wiring pattern 111F for light source on the surface of the substrate 100 are arranged in a mutually opposed manner. Similarly, the cathode wiring pattern 14 for PD of the wiring substrate 10, the cathode wiring pattern 114B for PD on the back side of the substrate 100, and the cathode wiring pattern 114F for PD on the surface of the substrate 100 are arranged in a mutually opposed manner.

[0138] On the other hand, Figure 7 As shown in (c), in the cross-sectional view along the line VIIC-VIIC in the center of the y direction, the cathode wiring pattern 12 for light source of the wiring substrate 10 is arranged to extend from the bottom of the light source 20 to the driving unit 50. The anode wiring pattern 11 for light source of the wiring substrate 10 is connected to the anode wiring pattern 111B for light source on the back side of the substrate 100, and the cathode wiring pattern 12 for light source is connected to the cathode wiring pattern 112B for light source on the back side of the substrate 100. Furthermore, the anode wiring pattern 111B for light source of the substrate 100 is connected to the anode wiring pattern 111F for light source on the surface of the substrate 100 via the through hole 111V, and the cathode wiring pattern 112B for light source is connected to the cathode wiring pattern 112F for light source on the surface of the substrate 100 via the through hole 112V. Furthermore, the cathode wiring pattern 112F for light source is connected to the cathode electrode 214 of the light source 20.

[0139] However, in Figure 7 In the VIIC-VIIC cross section shown in FIG. 2 ( c ), the PD cathode wiring pattern 114F on the base material 100 is not connected to the light source cathode wiring pattern 12 provided on the wiring substrate 10 .

[0140] That is, in the cross section of line VIIC-VIIC, the anode wiring pattern 11 for light source of the wiring substrate 10, the anode wiring pattern 111B for light source on the back side of the substrate 100, and the anode wiring pattern 111F for light source on the surface of the substrate 100 are arranged in a mutually opposed manner. However, the cathode wiring pattern 112B for light source on the back side of the substrate 100 and the cathode wiring pattern 112F for light source on the surface of the substrate 100 are arranged in a mutually opposed manner, but the cathode wiring pattern 12 for light source of the wiring substrate 10 is arranged to extend from the portion opposite to the cathode wiring pattern 112B for light source to the driving unit 50. In addition, no wiring pattern is arranged on the back side of the substrate 100 to be opposite to the cathode wiring pattern 114F for PD on the substrate 100. That is, the cathode wiring pattern 114F for PD on the substrate 100 is three-dimensionally crossed with the cathode wiring pattern 12 for light source provided on the wiring substrate 10 without being electrically connected. That is, the substrate 100 is arranged to straddle the cathode wiring pattern 12 for light source. Thus, the cathode wiring pattern 12 for light source of the wiring substrate 10 is arranged to extend from the light source 20 to the driving unit 50 on the back side of the substrate 100, and the PD 40 is arranged in an area on the substrate 100 that overlaps with the cathode wiring pattern 12 for light source when viewed from above. It should be noted that if the substrate 100 is not arranged to straddle the cathode wiring pattern 12 for light source, but is arranged on one side in the width direction of the cathode wiring pattern 12 for light source, the light emitting device 4 will be enlarged.

[0141] Therefore, if Figure 7 As shown in (a), in the light emitting device 4 to which the first embodiment is applied, even in a structure in which the PD 40 and the light source 20 are arranged close to each other and the PD 40 is arranged between the light source 20 and the driving unit 50, the wiring pattern connecting the light source 20 and the driving unit 50 (here, the cathode wiring pattern 12 for the light source) is also arranged in a straight line. As a result, the wiring pattern connecting the light source 20 and the driving unit 50 (here, the cathode wiring pattern 12 for the light source) becomes shorter, thereby suppressing the increase in the inductance of the circuit. That is, the path of the wiring pattern connecting the light source 20 and the driving unit 50 is not restricted by the PD 40.

[0142] Next, the wiring patterns provided on the wiring substrate 10 and the base material 100 will be described in detail.

[0143] Figure 8 The diagrams are for explaining wiring patterns provided on the wiring board 10 and the base material 100 . Figure 8 (a) is the surface of the wiring substrate 10, Figure 8 (b) is the surface of the substrate 100, Figure 8 (c) is the back side of the substrate 100. Figure 8In (a), the wiring pattern of the first conductive layer of the wiring substrate 10 is shown, and the wiring pattern of the second conductive layer, i.e., the ground line 84, and the wiring pattern of the third conductive layer, i.e., the power line 83, are not shown. The second conductive layer and the third conductive layer are patternless films except for the portion where the through hole for connecting to the wiring pattern composed of the first conductive layer is provided.

[0144] exist Figure 8 An anode wiring pattern 11 for a light source and a cathode wiring pattern 12 for a light source are provided on the surface of the wiring substrate 10 shown in (a). The planar shape of the cathode wiring pattern 12 for the light source is a quadrilateral. The anode wiring pattern 11 for the light source is provided adjacent to the short side of the cathode wiring pattern 12 for the light source on the -x direction side, and extends along the two long sides connected to the short side. Furthermore, an anode wiring pattern 13 for PD and a cathode wiring pattern 14 for PD are provided on the surface of the wiring substrate 10. The anode wiring pattern 13 for PD and the cathode wiring pattern 14 for PD are provided so as to sandwich the cathode wiring pattern 12 for the light source from the ±y direction.

[0145] exist Figure 8 The surface of the substrate 100 shown in (b) is provided with an anode wiring pattern 111F for light source and a cathode wiring pattern 112F for light source. The cathode wiring pattern 112F for light source is in the same Figure 3 The plane shape of the light source 20 shown in FIG. 1 corresponds to the plane shape of a quadrilateral. In addition, the light source anode wiring pattern 111F and the light source cathode wiring pattern 112F are provided adjacent to three sides. Furthermore, a PD anode wiring pattern 113F and a PD cathode wiring pattern 114F are provided on the surface of the substrate 100 .

[0146] exist Figure 8 On the back side of the substrate 100 shown in (c), there are provided an anode wiring pattern 111B for light source connected to the anode wiring pattern 111F for light source via a through hole 111V, a cathode wiring pattern 112B for light source connected to the cathode wiring pattern 112F for light source via a through hole 112V, an anode wiring pattern 113B for PD connected to the anode wiring pattern 113F for PD via a through hole 113V, and a cathode wiring pattern 114B for PD connected to the cathode wiring pattern 114F for PD via a through hole 114V. It should be noted that in the substrate 100, Figure 8 (b) shows the surface wiring pattern and Figure 8The wiring pattern on the back side shown in (c) is a mirror inversion except for the PD anode wiring pattern 113F and the PD anode wiring pattern 113B. That is, in a top view, the wiring pattern on the surface of the substrate 100 and the wiring pattern on the back side are arranged in an overlapping manner. It should be noted that the cathode wiring pattern 12 for light source is a wiring pattern on the wiring substrate 10 that is connected to the light source 20 and extends from the back side of the substrate 100 toward the drive unit 50.

[0147] On the other hand, of the PD anode wiring pattern 113F and the PD anode wiring pattern 113B, the PD anode wiring pattern 113F on the front surface is longer in the y direction than the PD anode wiring pattern 113B on the back surface and extends to the center of the substrate 100 in the y direction.

[0148] And, if in Figure 8 In (a), the substrate 100 is arranged at the position shown by the dotted line of the wiring substrate 10, then the anode wiring pattern 11 for light source of the wiring substrate 10 is connected to the anode wiring pattern 111B for light source of the substrate 100, and the cathode wiring pattern 12 for light source of the wiring substrate 10 is connected to the cathode wiring pattern 112B for light source of the substrate 100. Similarly, the anode wiring pattern 13 for PD of the wiring substrate 10 is connected to the anode wiring pattern 113B for PD of the substrate 100, and the cathode wiring pattern 14 for PD of the wiring substrate 10 is connected to the cathode wiring pattern 114B for PD of the substrate 100.

[0149] At this time, in the substrate 100, if the PD cathode wiring pattern 114B on the back side is the same shape as the PD cathode wiring pattern 114F on the front side, the PD cathode wiring pattern 114B will short-circuit the light source cathode wiring pattern 12 and the PD cathode wiring pattern 14 of the wiring substrate 10. Therefore, in the substrate 100, the length of the PD cathode wiring pattern 114B on the back side in the +y direction is made shorter than the length of the PD cathode wiring pattern 114F on the front side in the +y direction, and the PD cathode wiring pattern 114B will not short-circuit the light source cathode wiring pattern 12 and the PD cathode wiring pattern 14 of the wiring substrate 10. That is, in order to arrange the PD 40 between the light source 20 and the driving unit 50, the PD cathode wiring pattern 114F connected to the cathode electrode of the PD 40 is provided on the substrate 100, so that it is three-dimensionally crossed and not short-circuited with the light source cathode wiring pattern 12 provided on the wiring substrate 10.

[0150] It should be noted that before the substrate 100 is arranged on the wiring board 10, the light source 20 and the PD 40 are mounted on the substrate 100. That is, the cathode electrode 214 of the light source 20 is bonded to the cathode wiring pattern 112F for the light source of the substrate 100 by a conductive adhesive or the like (see Figure 4). In addition, the anode electrode 218 of the light source 20 (see Figure 4 ) is connected to the anode wiring pattern 111F for the light source through bonding wires 23A, 23B, and 23C.

[0151] Furthermore, the cathode electrode of the PD 40 is bonded to the cathode wiring pattern 114F for PD of the substrate 100 by a conductive adhesive, and the anode electrode of the PD 40 is connected to the anode wiring pattern 113F for PD of the substrate 100 by a bonding wire 23D.

[0152] As described above, in the light emitting device 4 of the first embodiment, by using the substrate 100, even in a structure where the PD 40 is disposed between the light source 20 and the driving unit 50, the path of the wiring pattern connecting the light source 20 and the driving unit 50 is not restricted by the PD 40. Thus, an increase in the inductance of the circuit can be suppressed.

[0153] As described above, the anode electrode and cathode electrode of PD40 are separated on both sides with the cathode wiring pattern 12 for light source provided on wiring substrate 10, and connected to PD anode wiring pattern 13 and PD cathode wiring pattern 14. That is, PD40 is connected to wiring substrate 10 on the outside with cathode wiring pattern 12 for light source sandwiched therebetween.

[0154] Fig. 9 This is a diagram for explaining the relationship in which the PD 40 is provided outside the cathode wiring pattern 12 for light sources in the wiring substrate 10 . Fig. 9 (a) is Example 1, Fig. 9 (b) is Example 2.

[0155] Fig. 9 Example 1 shown in (a) and Figure 8 The embodiment shown is the same. In embodiment 1, the cathode wiring pattern 12 for light source connects the light source 20 and the driving unit 50 in a straight line. And, the cathode wiring pattern 12 for light source is formed into a quadrilateral in planar shape. That is, even if there are an anode wiring pattern 13 for PD and a cathode wiring pattern 14 for PD for connecting PD40, the cathode wiring pattern 12 for light source is not affected by the two and is set with the same line width. Therefore, in the cathode wiring pattern 12 for light source, the light source 20 and the driving unit 50 are set in a straight line with the shortest distance, thereby suppressing the increase in the inductance of the circuit. And, the resistance of the cathode wiring pattern 12 for light source is smaller than that in embodiment 2 described below.

[0156] exist Fig. 9In the second embodiment shown in (b), in order to set PD40, the portion of the cathode wiring pattern 12 for light source where the anode wiring pattern 13 for PD and the cathode wiring pattern 14 for PD are set narrower. Therefore, the resistance of the cathode wiring pattern 12 for light source is larger than that in the above-mentioned first embodiment. However, in the second embodiment, the light source 20 and the driving unit 50 are also set in a straight line with the shortest distance. That is, the cathode wiring pattern 12 for light source is not easily affected by the setting of PD40. The cathode wiring pattern 12 for light source can be constructed in this way.

[0157] As described above, compared with the case where PD40 is provided inside the cathode wiring pattern 12' for the light source as shown in the light emitting device 4-2 of the comparative example 2 described later, PD40 is connected to the wiring substrate 10 on the outside in a manner of sandwiching the cathode wiring pattern 12 for the light source from both sides, so that the path of the cathode wiring pattern 12 for the light source is not affected. Therefore, the increase in the inductance of the circuit can be suppressed. It should be noted that the anode wiring pattern 13 for PD and the cathode wiring pattern 14 for PD are an example of a circuit element, that is, an example of a connection portion between PD40 and the wiring substrate 10, the anode electrode of PD40 is an example of a first electrode, and the cathode electrode is an example of a second electrode.

[0158] In the light emitting device 4 of the first embodiment, the substrate 100 is used. Hereinafter, a light emitting device in which the substrate 100 is not used will be described as a comparative example.

[0159] (Light Emitting Device of Comparative Example)

[0160] Fig.10 It is a diagram for explaining a light emitting device 4-1 of Comparative Example 1. Fig.10 (a) is a top view, Fig.10 (b) is Fig.10 The light emitting device 4-1 does not use the substrate 100 used in the light emitting device 4. That is, the light emitting device 4-1 is provided with the light source 20, the PD 40, the driving unit 50, and other circuit components on the wiring substrate 10.

[0161] In the light emitting device 4-1 of Comparative Example 1, Fig.10 As shown in (a), the PD 40, the light source 20, and the driving unit 50 are arranged in the x direction toward the wiring substrate 10. Therefore, on the side 22B side of the light source 20, the light source 20 and the driving unit 50 are connected through the cathode wiring pattern 12 for the light source. Fig.10 As shown in (a) and (b) of FIG. 1 , the light source cathode wiring pattern 12 is set between the light source 20 and the driving unit 50 without being affected by the PD 40 .

[0162] On the other hand, the PD40 must be arranged on the side of the light source 20 other than the side 22B on which the cathode wiring pattern 12 for light source is provided, that is, on the side of the side 21A, 21B, 22A. However, the anode wiring pattern 11 for light source is provided on the side of the side 21A, 21B, 22A. And the anode wiring pattern 11 for light source is connected to the anode electrode 218 of the light source 20 by the bonding wires 23A, 23B, 23C. Therefore, the PD40 must be arranged on the -x side, that is, on the outside, of the anode wiring pattern 11 for light source, and the light source 20 and the PD40 cannot be arranged close to each other.

[0163] Fig.11 It is a diagram for explaining a light emitting device 4-2 of Comparative Example 2. Fig.11 (a) is a top view, Fig.11 (b) is Fig.11 The light emitting device 4-2 does not use the substrate 100 used in the light emitting device 4. That is, the light emitting device 4-2 is provided with the light source 20, the PD 40, the driving unit 50, and other circuit components on the wiring substrate 10.

[0164] In the light emitting device 4-2 of Comparative Example 2, as Fig.11 As shown in (b), the light source 20, the PD40 and the driving unit 50 are arranged linearly in the x direction of the wiring substrate 10. That is, the PD40 is arranged between the light source 20 and the driving unit 50. In addition, similar to the light emitting device 4-1, the light source 20 is provided with a light source anode wiring pattern 11 on the side surfaces 21A, 21B, and 22A, and the light source anode wiring pattern 11 is connected to the anode electrode 218 of the light source 20 by bonding wires 23A, 23B, and 23C. In addition, the PD40 is provided on the side surface 22B where the light source anode wiring pattern 11 is not provided. Therefore, it is desirable that the PD40 provided close to the light source 20 is provided close to the light source 20.

[0165] On the other hand, the cathode wiring pattern 12' for light source is branched and arranged so as to include the PD 40 inside. That is, the cathode wiring pattern 12' for light source must be arranged so as to bypass the PD 40. Thus, in the light emitting device 4-2, the cathode wiring pattern 12' for light source connecting the light source 20 and the driving unit 50 is affected by the arrangement of the PD 40, and the inductance of the circuit increases.

[0166] As described above, as in the light-emitting device 4 of the first embodiment, the substrate 100 is set, so that even in a structure in which a circuit element (here, PD40 as an example) that is desired to be set close to the light source 20 is arranged between the light source 20 and the driving unit 50, the path of the wiring pattern (here, the cathode wiring pattern 12 for the light source) connecting the light source 20 and the driving unit 50 will not be restricted by PD40.

[0167] [Second Embodiment]

[0168] The light emitting device 4 according to the first embodiment includes the light source 20 and the PD 40 preferably disposed close thereto on the substrate 100. In the light emitting device 4A according to the second embodiment, the light source 20 is not disposed on the substrate 150 as described later.

[0169] Fig.12 It is a diagram for explaining a light emitting device 4A to which the second embodiment is applied. Fig.12 (a) is a top view, Fig.12 (b) is Fig.12 (a) is a cross-sectional view taken along the XIIB-XIIB line, Fig.12 (c) is Fig.12 1 and 2. A cross-sectional view taken along line XIIC-XIIC of (a). The same parts as those of the light emitting device 4 are denoted by the same reference numerals and their description is omitted.

[0170] like Fig.12 As shown in (b) and (c), the light emitting device 4A is provided with a light source 20, a substrate 150, a driving unit 50 and a holding unit 60 on a wiring substrate 10. In addition, a PD 40 is provided on the substrate 150. In the light emitting device 4A, a holding unit 60 is provided on the wiring substrate 10, and the light diffusion component 30 is held by the holding unit 60. Here, the substrate 150 may be made of an electrically insulating material. It should be noted that the wiring substrate 10 provided with the light source 20 may also be a heat dissipation substrate having a higher thermal conductivity than the substrate 150.

[0171] like Fig.12 As shown in (a), in the light emitting device 4A, the light source 20, the PD 40, and the driving unit 50 are arranged linearly in the x direction. Furthermore, in the light emitting device 4A, even in a structure in which the PD 40 is arranged between the light source 20 and the driving unit 50 and the PD 40 is close to the light source 20, the path of the wiring pattern (the cathode wiring pattern 12 for the light source described later) connecting the light source 20 and the driving unit 50 is not restricted by the PD 40.

[0172] The first conductive layer of the wiring substrate 10 forms a light source anode wiring pattern 11A and a light source cathode wiring pattern 12 that form a part of the current path to the light source 20, and a PD anode wiring pattern 15 and a PD cathode wiring pattern 16 that form a part of the current path to the PD 40. Fig.12 In (a), the PD anode wiring pattern 15 and the PD cathode wiring pattern 16 are located on the back side of the substrate 150 and are not shown in the figure. Figure 8 The anode wiring pattern 11 for the light source shown in (a) is small.

[0173] On the surface of the substrate 150, a PD anode wiring pattern 115F and a PD cathode wiring pattern 116F are provided, which constitute a part of the current path leading to the PD 40. On the back side of the substrate 150, a PD anode wiring pattern 115B and a PD cathode wiring pattern 116B (see below) are also provided, which constitute a part of the current path leading to the PD 40. Fig.13 ). Moreover, on the front and back surfaces of the substrate 150, wiring patterns with the same number are connected through through holes.

[0174] Furthermore, the cathode wiring pattern 12 for light source of the wiring substrate 10 and the cathode electrode 214 of the light source 20 (see Figure 4 ) are bonded by a conductive adhesive or the like. Also, the light source anode wiring pattern 11A of the wiring substrate 10 and the anode electrode 218 of the light source 20 (see Figure 4 ) are connected by bonding wires 23A, 23B, 23C on the side 21A, 21B, 22A of the light source 20. Here, the anode wiring pattern 11A for the light source is arranged on the side 21A, 21B, 22A of the light source 20, and is not arranged on the side 22B of the light source 20. In this way, a bonding wire connecting the anode electrode 218 and the anode wiring pattern 11A for the light source is not arranged on the side 22B of the light source 20. Therefore, it is desired that an example of a circuit element arranged close to the light source 20, that is, PD40, is arranged close to the light source 20.

[0175] In the PD 40 , the cathode electrode of the PD 40 is bonded to the PD cathode wiring pattern 116F of the substrate 100 by a conductive adhesive, and the anode electrode of the PD 40 is connected to the PD anode wiring pattern 115F of the substrate 100 by a bonding wire 23D.

[0176] Furthermore, the PD anode wiring pattern 15 and the PD cathode wiring pattern 16 provided on the wiring substrate 10 are connected to the PD anode wiring pattern 115B and the PD cathode wiring pattern 116B on the back surface of the base material 100 , respectively.

[0177] And, if Fig.12 As shown in (b), in the cross-sectional view at the XIIB-XIIB line offset from the center of the y direction to the -y direction side, the PD cathode wiring pattern 16 of the wiring substrate 10 is connected to the PD cathode wiring pattern 116B on the back side of the substrate 150. The PD cathode wiring pattern 116B of the substrate 150 is connected to the PD cathode wiring pattern 116F on the surface of the substrate 150 via the through hole 116V. In addition, the PD cathode wiring pattern 116F of the substrate 150 is connected to the cathode electrode of the PD40.

[0178] That is, in the cross section along line XIIB-XIIB, the PD cathode wiring pattern 16 of the wiring substrate 10, the PD cathode wiring pattern 116B on the back side of the substrate 150, and the PD cathode wiring pattern 116F on the surface of the substrate 150 are arranged opposite to each other.

[0179] On the other hand, Fig.12 As shown in (c) , in the cross-sectional view taken along line XIIC-XIIC in the center in the y direction, the PD cathode wiring pattern 116F on the base material 150 is not connected to the light source cathode wiring pattern 12 provided on the wiring substrate 10 .

[0180] That is, in the cross section of the XIIC-XIIC line, the cathode wiring pattern 12 for light source of the wiring substrate 10 is provided to extend from the light source 20 to the driving unit 50. In addition, no wiring pattern is provided on the wiring substrate 10 to oppose the cathode wiring pattern 116F for PD on the substrate 150. Thus, the cathode wiring pattern 116F for PD on the substrate 150 and the cathode wiring pattern 12 for light source provided on the wiring substrate 10 are three-dimensionally intersected without being electrically connected.

[0181] Next, the wiring patterns provided on the wiring substrate 10 and the base material 150 will be described.

[0182] Fig.13 The diagram is for explaining wiring patterns provided on the wiring substrate 10 and the base material 150 . Fig.13 (a) is the surface of the wiring substrate 10, Fig.13 (b) is the surface of the substrate 100, Fig.13 (c) is the back side of the substrate 100. Fig.13 (a) shows a wiring pattern of the first conductive layer of the wiring substrate 10.

[0183] exist Fig.13 On the surface of the wiring substrate 10 shown in (a), an anode wiring pattern 11A for light source and a cathode wiring pattern 12 for light source are provided. Figure 8 The light source cathode wiring pattern 12 shown in (a) is the same as that of the wiring substrate 10, and therefore the same reference numerals are given. A PD anode wiring pattern 15 and a PD cathode wiring pattern 16 are provided on the surface of the wiring substrate 10. The length ratio of the PD anode wiring pattern 15 to the PD cathode wiring pattern 16 in the y direction is Figure 8 The lengths of the PD anode wiring pattern 13 and the PD cathode wiring pattern 14 in the y direction shown in (a) are short.

[0184] exist Fig.13 In the substrate 150 shown in (b) and (c), Figure 8The substrate 100 shown in (b) and (c) is the same as the PD anode wiring pattern 113F, 113B and the PD cathode wiring pattern 114F, 114B, with a PD anode wiring pattern 115F and a PD cathode wiring pattern 116F provided on the surface, and a PD anode wiring pattern 115B and a PD cathode wiring pattern 116B provided on the back. It should be noted that the PD anode wiring pattern 115F on the surface and the PD anode wiring pattern 115B on the back are the same planar shape, and are mirror-inverted shapes on the surface and back of the substrate 150. On the other hand, the PD cathode wiring pattern 116F on the surface is longer in the y direction than the PD cathode wiring pattern 116B on the back, and extends to the center of the y direction of the substrate 150. Furthermore, the PD anode wiring pattern 115F on the front surface and the PD anode wiring pattern 115B on the back surface, and the PD cathode wiring pattern 116F on the front surface and the PD cathode wiring pattern 116B on the back surface are connected via through holes provided through the base material 150 .

[0185] And, if in Fig.13 In (a), the substrate 150 is configured at the position shown by the dotted line of the wiring substrate 10, and the PD anode wiring pattern 15 of the wiring substrate 10 is connected to the PD anode wiring pattern 115B of the substrate 150, and the PD cathode wiring pattern 16 of the wiring substrate 10 is connected to the PD cathode wiring pattern 116B of the substrate 150.

[0186] At this time, in the substrate 150, the cathode wiring pattern 116B for PD on the back side is made to have a shape different from the cathode wiring pattern 116F for PD on the front side, and the cathode wiring pattern 12 for light source and the cathode wiring pattern 16 for PD of the wiring substrate 10 are prevented from being short-circuited. That is, in order to arrange the PD40 in the central part of the y direction of the wiring substrate 10, the cathode wiring pattern 116F for PD connected to the cathode electrode of the PD40 is provided on the substrate 150, so that it is three-dimensionally crossed without being short-circuited with the cathode wiring pattern 12 for light source provided on the wiring substrate 10. That is, the substrate 150 is provided so as to cross the cathode wiring pattern 12 for light source. Thus, the cathode wiring pattern 12 for light source of the wiring substrate 10 is provided to extend from the light source 20 to the driving unit 50 on the back side of the substrate 150, and the PD40 is provided in the area on the substrate 100 that overlaps with the cathode wiring pattern 12 for light source when viewed from above. It should be noted that the light source cathode wiring pattern 12 is a wiring pattern on the wiring substrate 10 that is connected to the light source 20 and extends from the back side of the base material 150 toward the driving unit 50 .

[0187] It should be noted that before the substrate 150 is arranged on the wiring substrate 10, the PD 40 is mounted on the substrate 150. On the other hand, on the wiring substrate 10, the cathode electrode 214 of the light source 20 is bonded to the cathode wiring pattern 12 for the light source by a conductive adhesive. And the substrate 150 on which the PD 40 is mounted is mounted on the wiring substrate 10. Next, the anode electrode 218 of the light source 20 is connected to the anode wiring pattern 11 for the light source by bonding wires 23A, 23B, and 23C, and the anode electrode of the PD 40 is connected to the anode wiring pattern 115F for the PD on the substrate 150 by bonding wires 23D.

[0188] As described above, in the light emitting device 4A of the second embodiment, the substrate 150 is provided, so that even in a structure where a circuit element (here, as an example, PD40) that is desired to be provided close to the light source 20 is arranged between the light source 20 and the driving unit 50, the path of the wiring pattern (here, the cathode wiring pattern 12 for the light source) connecting the light source 20 and the driving unit 50 is not restricted by the PD40. Thus, an increase in the inductance of the circuit can be suppressed.

[0189] It should be noted that in the above-mentioned first and second embodiments, the light amount monitoring light receiving element (PD40) is described as an example of a circuit element, but the circuit element may also be other circuit components such as a capacitor (capacitor 70) that supplies current to the light source 20.

[0190] In the first and second embodiments described above, the light diffuser 30 is used. However, an optical component having a light-transmitting component such as a protective cover and a transparent base material, such as a condenser lens or a microlens array, may be used instead of the light diffuser 30 .

[0191] While the present invention has been described in detail and with reference to specific embodiments thereof, it will be apparent to one skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the present invention.

[0192] This application is based on the Japanese patent application (patent application 2019-053386) filed on March 20, 2019, the contents of which are incorporated herein by reference.

[0193] Description of reference numerals:

[0194] 1: information processing device; 2: UI unit; 3: optical device; 4, 4-1, 4-2, 4A: light emitting device; 5: 3D sensor; 6: resistor; 7, 70: capacitor; 8: optical device control unit; 9: system control unit; 10: wiring substrate; 11, 11A, 111F, 111B: anode wiring pattern for light source; 12, 12', 112F, 112B: cathode wiring pattern for light source; 13, 15, 113F, 113B, 115F, 115B: anode wiring pattern for PD; 14, 16, 114F, 114B, 116F, 116B: cathode wiring pattern for PD; 20: light source; 21A, 21B, 22A, 22B: side; 23A, 23B, 23C, 23D: bonding wire; 30: light diffusion component; 40: PD (light receiving element for monitoring light quantity); 50: driving unit; 51: MOS transistor; 52: signal generating circuit; 60: holding unit; 61A, 61B, 62A, 62B: wall; 81: shape determining unit; 82: power supply; 83: power supply line; 84: ground line; 91: authentication processing unit; 100, 150: substrate; 200: semiconductor substrate; 202: lower DBR; 206: active area; 208: upper DBR; 210: current limiting layer; 210A: oxidation area; 210B: conductive area; 214: cathode electrode; 218: anode electrode; M: table; VCSEL: vertical cavity surface emitting laser element.

Claims

1. A light emitting device comprising: Wiring substrate; a substrate mounted on the wiring substrate; a light source mounted on the substrate; a driving unit mounted on the wiring substrate and configured to drive the light source; a cathode wiring pattern for light source on the wiring substrate, which is connected to the light source and extends from the back side of the substrate toward the driving unit; as well as a circuit element provided between the light source and the driving unit in a region on the substrate that overlaps with the cathode wiring pattern for the light source when viewed from above, The circuit element is connected to the wiring substrate on the outside so as to sandwich the cathode wiring pattern for the light source from both sides.

2. The light emitting device according to claim 1, wherein: The circuit element is electrically connected to the wiring substrate on the outside so as to sandwich the cathode wiring pattern for light source from both sides, and the cathode wiring pattern for light source is wired so as not to avoid the connection portion between the circuit element and the wiring substrate.

3. The light emitting device according to claim 1, wherein: The circuit element includes a first electrode connected to the wiring substrate at one side in the width direction of the light source cathode wiring pattern and a second electrode connected to the wiring substrate at the other side in the width direction of the light source cathode wiring pattern.

4. The light emitting device according to claim 1, wherein: The light source is a light emitting element array having a first side surface and a second side surface facing each other, and a third side surface and a fourth side surface connecting the first side surface and facing each other. The wiring extending from the upper surface electrode of the light-emitting element array toward the outside of the light-emitting element array is arranged at least on the first side and the second side, the circuit element is arranged on the substrate on the fourth side, and the cathode wiring pattern for the light source extends from the fourth side toward the driving unit.

5. The light emitting device according to claim 4, wherein: A wiring extending from an upper surface electrode of the light emitting element array toward an outer side of the light emitting element array is provided on the third side surface.

6. The light emitting device according to claim 4, wherein: Other circuit elements are arranged on the substrate on the third side surface.

7. The light emitting device according to claim 6, wherein: At least one of the circuit element and the other circuit element is a light receiving element.

8. The light emitting device according to claim 1, wherein: The base material is a member having a higher thermal conductivity than the wiring substrate.

9. The light emitting device according to claim 8, wherein: The base material on the wiring substrate is made of ceramic.

10. The light emitting device according to any one of claims 4 to 7, wherein: A light diffusion member for diffusing light emitted from the light source toward the outside is provided on an emission path of the light emitting element array in the light source.

11. The light emitting device according to any one of claims 4 to 7, wherein: The light emitting element array includes a plurality of light emitting elements connected in parallel to each other.

12. A light emitting device comprising: Wiring substrate; A light source and a driving unit for driving the light source, which are mounted on the wiring substrate; a cathode wiring pattern for the light source on the wiring substrate, which connects the light source and the driving unit; a substrate disposed between the light source and the driving unit so as to cross the cathode wiring pattern for the light source; as well as a circuit element provided on the substrate in a region overlapping with the cathode wiring pattern for the light source when viewed from above, The circuit element is connected to the wiring substrate on the outside so as to sandwich the cathode wiring pattern for the light source from both sides.

13. An optical device comprising: The light emitting device according to any one of claims 1 to 12; and A light receiving unit receives reflected light emitted from a light source provided in the light emitting device and reflected by the object to be measured, wherein: The light receiving unit outputs a signal corresponding to the time from when light is emitted from the light source to when the light is received by the light receiving unit.

14. An information processing device comprising: The optical device according to claim 13; and The shape specifying unit specifies the three-dimensional shape of the object to be measured based on the reflected light emitted from the light source provided in the optical device, reflected by the object to be measured, and received by the light receiving unit provided in the optical device.

15. The information processing device according to claim 14, comprising: An authentication processing unit performs authentication processing related to the use of the device based on the determination result of the shape determination unit.

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