Computing device, method, board, and computer-readable storage medium

Abstract

The present disclosure discloses a computing device, an integrated circuit board, a method, and a computer-readable storage medium for processing multi-bit width values. The computing device may be included in a combined processing device, which may further include a general-purpose interconnection interface and other processing devices. The computing device interacts with other processing devices to jointly complete a calculation operation specified by a user. The combined processing device may further include a storage device, which is respectively connected to the device and other processing devices and is used for storing data of the device and other processing devices. The solution of the present disclosure can split multi-bit width values so that the processing capacity of the processor is not affected by the bit width.

Description

Technical Field

[0001] This disclosure generally relates to data processing. More specifically, this disclosure relates to a computing device, method, integrated circuit board, and computer-readable storage medium for processing multi-bit-width values. Background Art

[0002] Currently, the data bit widths processed by different types of processors may vary. For a processor that performs operations on a specific data type, the data bit width it processes is often limited. For example, for a fixed-point arithmetic unit, the data bit width it can usually process does not exceed 16 bits, such as 16-bit integer data. However, in order to save computing costs and overheads and improve computing efficiency, how to enable a processor with a limited bit width to process more bit-width data has become a technical problem to be solved. Summary of the Invention

[0003] To at least solve the above-mentioned technical problems, this disclosure proposes a solution for splitting multi-bit-width data in multiple aspects. Through the splitting solution of this disclosure, multi-bit-width data can be split into at least two data with smaller bit widths for representation, so that in a scenario where the processing bit width of the processor is limited, two data with smaller bit widths can be used to participate in the calculation.

[0004] In a first aspect, this disclosure provides a computing device for processing multi-bit-width values, where the multi-bit-width values include a high-bit part and a low-bit part, and the computing device includes:

[0005] An input circuit configured to receive the multi-bit-width value and configuration information, where the configuration information at least includes bit width information of the high-bit part or the low-bit part;

[0006] A first component calculation circuit configured to calculate the multi-bit-width value according to the bit width information of the low-bit part to obtain a first component representing the high-bit part in the multi-bit-width value;

[0007] A second component calculation circuit configured to calculate based on the multi-bit-width value and at least the value of the first component to obtain a second component representing the low-bit part in the multi-bit-width value; and

[0008] An output circuit configured to output at least one of the first component and the second component.

[0009] In a second aspect, this disclosure provides an integrated circuit chip including the aforementioned computing device.

[0010] In a third aspect, the present disclosure provides an integrated circuit board card, which includes the aforementioned integrated circuit chip.

[0011] In a fourth aspect, the present disclosure provides a method for processing a multi-bit-width value, where the multi-bit-width value includes a high-bit part and a low-bit part, and the method includes:

[0012] Receiving the multi-bit-width value and configuration information, where the configuration information at least includes bit-width information of the high-bit part or the low-bit part;

[0013] Calculating the multi-bit-width value according to the bit-width information of the low-bit part to obtain a first component representing the high-bit part in the multi-bit-width value;

[0014] Calculating based on the multi-bit-width value and at least the value of the first component to obtain a second component representing the low-bit part in the multi-bit-width value; and

[0015] Outputting at least one of the first component and the second component.

[0016] In a fifth aspect, the present disclosure provides a computing device for processing a multi-bit-width value, including:

[0017] A processor;

[0018] A memory for storing program instructions, which when executed by the at least one processor, cause the computing device to execute the aforementioned method.

[0019] In a sixth aspect, the present disclosure provides a computer-readable storage medium, on which program instructions for processing a multi-bit-width value for neural network operations are stored, and when the program instructions are run by a processor, the aforementioned method is executed.

[0020] Through the computing device, integrated circuit board card, method, and computer-readable storage medium provided as above, the solution of the present disclosure can split a multi- (or high-) bit-width value into multiple less- (or low-) bit-width values for expression, so as to be unrestricted by the processing bit-width of the processor in artificial intelligence application scenarios such as neural network operations or other general scenarios, and give full play to the computing power of the processor. Further, in some neural network operation scenarios that require low-bit-width values, the solution of the present disclosure can also simplify the calculation of the neural network by splitting the multi-bit-width value into multiple low-bit-width expressions, thereby improving the calculation efficiency. Description of the Drawings

[0021] The above features of the present disclosure can be better understood by combining the accompanying drawings, and its numerous objects, features, and advantages will be apparent to those skilled in the art. The drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts, where:

[0022] Figure 1 is a simplified block diagram showing a computing device according to an embodiment of the present disclosure;

[0023] Figure 2 is a detailed block diagram showing a computing device according to an embodiment of the present disclosure;

[0024] Figure 3 is a flowchart showing the processing of multi-bit width values according to an embodiment of the present disclosure;

[0025] Figure 4 is a structural diagram showing a combined processing device according to an embodiment of the present disclosure; and

[0026] Figure 5 is a schematic structural diagram showing a board card according to an embodiment of the present disclosure. Detailed Embodiments

[0027] The solution of the present disclosure overcomes the obstacle of limited processor bit width by expressing a multi-bit width (e.g., 24-bit) value with at least two low-bit (e.g., 16-bit and 8-bit) width components, simplifies the computational complexity, and thus improves the computational efficiency of, for example, neural network computations. In one or more embodiments, the source or initial value can be divided into a high-bit part and a low-bit part according to the bit distribution and configuration information of the input multi-bit width value, and split computations are performed on the high-bit part and the low-bit part to obtain a first component and a second component corresponding to the high-bit part and the low-bit part. Thus, in actual computations, at least one of the first component and the second component can be used to replace the source data for computations. In additional embodiments, the solution of the present disclosure can also decompose the aforementioned source value into a required number of components according to the configuration information, for example, repeatedly performing similar split computations on at least one of the aforementioned first component and the second component to obtain more than three components.

[0028] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0029] Figure 1is a simplified block diagram showing a computing device 100 according to an embodiment of the present disclosure. In one or more embodiments, the computing device 100 may process multi-bit width values for various application scenarios, such as artificial intelligence applications including neural network operations or general scenarios that require splitting values for calculations. Here, the multi-bit width value may include a high-bit part and a low-bit part for subsequent splitting into two or more components. Additionally, the aforementioned neural network operations may include various operations in training a neural network, such as weight update or gradient calculation in the backpropagation direction.

[0030] As Figure 1 shown, the computing device 100 includes an input circuit 102 configured to receive a multi-bit width value and configuration information, where the configuration information at least includes the bit width information of the high-bit part or the low-bit part. For example, when the multi-bit width is a 24-bit integer, it can be divided into an 8-bit high-bit part and a 16-bit low-bit part, that is, an 8-bit bit width component and a 16-bit bit width component to be obtained by splitting. In one or more embodiments, the configuration information may further include information indicating whether the low-bit part includes a sign bit. For example, when represented in bits, "1" indicates that the low-bit part includes a sign bit, and "0" indicates that the low-bit part does not include a sign bit. Additionally, the configuration information may further include valid bit information, such as forcibly specifying which bits in the multi-bit width value are valid bits for subsequent calculations on the valid bits during splitting calculations.

[0031] Connected to the input circuit 102 are a first component calculation circuit 104 and a second component calculation circuit 106. In one or more embodiments, the first component calculation circuit may be configured to calculate the multi-bit width value according to the bit width information of the low-bit part to obtain a first component representing the high-bit part in the multi-bit width value. In one scenario, the first component calculation circuit may determine a scaling factor according to the bit width information of the low-bit part and use the scaling factor to calculate the multi-bit width value to obtain the first component. For example, when the bit width of the high-bit part is n1 and the bit width of the low-bit part is n2, when not considering that n2 includes a sign bit, the scaling factor may be 2 n2 . In contrast, when considering that n2 includes a sign bit, the scaling factor may be 2 n2 -1 .

[0032] In one or more embodiments, the second component calculation circuit may be configured to perform calculations based on a multi-bit width value and at least a value regarding a first component to obtain a second component representing the low-bit portion in the multi-bit width value. In one scenario, when the configuration information indicates that the sign bit is not considered for the low-bit width portion, the second component can be simply obtained by subtracting the value of the first component from the multi-bit width value. Here, the value of the first component may be the product value of the first component and the aforementioned scaling coefficient. In another scenario, when the configuration information indicates that the sign bit is considered for the low-bit width portion, the second component calculation circuit may be configured to determine an adjustment value based on the bit width information of the low-bit portion, and perform calculations based on the multi-bit width value, the value regarding the first component, and the adjustment value to obtain the second component. It can be understood that in some scenarios, the aforementioned configuration information may not include sign bit information either. In this case, through, for example, an initial default setting, the computing device of the present disclosure may be configured to directly perform a split operation considering the sign bit or a split operation not considering the sign bit, rather than making a determination on whether to consider the sign bit based on the configuration information.

[0033] After obtaining the first and second components that can represent the multi-bit width value, the computing device of the present disclosure further includes an output circuit 108, which may be configured to output at least one of the first and second components. As previously described, the first and second components output by the output circuit can be applied to various calculations in the neural network that require the use of data with a low-bit width, such as weight update and gradient calculation for backpropagation in neural network training. In some application scenarios, the obtained first and second components can also be directly stored to replace the multi-bit width value for later use. In a scenario where the neural network uses a fixed-point processor that supports a low-bit width to perform fixed-point operations, by using the low-bit width first and second components output by the output circuit for the fixed-point operations of the fixed-point processor, the fixed-point processor will be freed from the limitation of being unable to process data with a multi- or high-bit width, expanding the calculation scenario of the fixed-point processor and simplifying the calculation, thereby also improving the calculation efficiency and reducing the calculation overhead.

[0034] Figure 2 is a detailed block diagram showing the computing device 200 according to an embodiment of the present disclosure. As can be seen from Figure 2 it, the computing device 200 not only includes Figure 1 the input circuit 102, the first component circuit 104, the second component circuit 106, and the output circuit 108 of the computing device 100 in Figure 1The functions of the input circuit, the first component and second component calculation circuits, and the output circuit have been described in detail and will not be elaborated further below.

[0035] As Figure 2 shown, the first component calculation circuit 104 may include a scaling circuit 1041 and a rounding circuit 1042. In one embodiment, the scaling circuit may be implemented by a shift circuit, which may be configured to perform a shift operation on a multi-bit width value according to the aforementioned scaling coefficient to complete the scaling. For example, when the scaling coefficient is 2 n2 , performing a shift operation using the shift circuit is to shift the multi-bit width value n2 bits to the higher bits. When the higher bits are on the left side of the multi-bit width value and the lower bits are on the right side thereof, shifting n2 bits to the higher bits is shifting n2 bits to the left. In terms of specific implementation, the shift circuit here may be constructed by a multiplier. After performing the corresponding shift operation on the multi-bit width value, in one embodiment, the first component calculation circuit further includes a rounding circuit 1042, which may be configured to perform a rounding operation on the multi-bit width value after the shift operation to obtain the first component. According to different application scenarios, the rounding operation here may include various forms of rounding operations, such as rounding up, rounding down, rounding towards zero, etc. After such a rounding operation, the first component related to the higher bit part in the multi-bit width value can be obtained.

[0036] In one or more embodiments, the second component calculation circuit 106 may include a subtraction circuit 1061, which is configured to subtract the value of the first component and the adjustment value from the multi-bit width value to obtain the second component. In one scenario, the value of the first component here may be the product value of the first component and the scaling coefficient, and the adjustment value is the value after considering the sign bit of the lower bit part as described above. By using the subtraction circuit to subtract the product value and the adjustment value from the multi-bit width value, the second component related to the lower bit part in the multi-bit width value can be obtained.

[0037] Further, the type converter 110 shown connected to the input circuit 102 in Figure 2 may be configured to convert the input data into the same data type as the multi-bit width value, that is, the data type supported by the first component calculation circuit and the second component calculation circuit. By providing the type converter, the computing device of the present disclosure can perform splitting on data of a type different from the data type supported by the splitting operation. For example, when the computing device of the present disclosure supports splitting of fixed-point integer values, when the input circuit receives a floating-point value, the type converter can convert the floating-point data into fixed-point integer data so that the first component calculation circuit and the second component calculation circuit can perform splitting.

[0038] To achieve flexible output, the computing device 200 of the present disclosure further includes a selector 112, which can be configured to output at least one of the first component and the second component to the output circuit 108 for output. In one embodiment, the selector 112 can select to output the first component, the second component, or both according to the information about the input item included in the configuration information. Such selective output has technical advantages in some application scenarios. For example, when only the first component or the second component is required to participate in subsequent operations, the output circuit does not need to output both of them, thus saving overhead in output. Additionally, when only the first component needs to be output, the computing device of the present disclosure can also calculate and output only the first component, thereby further saving computing overhead.

[0039] In one or more embodiments, the computing device of the present disclosure can also be used to decompose a multi-bit width value into multiple components specified by the user or required by the algorithm. To this end, the aforementioned configuration information can include information about the number of components. When the number of components is a positive integer greater than 2, the computing device of the present disclosure repeatedly executes the first component calculation circuit and the second component calculation circuit according to the configuration information until the components of the number of components are obtained. For example, for a 24-bit width value, when the configuration information indicates that it is split into 3 components and all three components are 8-bit width, the 24-bit width value can be split into an 8-bit width first component and a 16-bit width intermediate second component by the first component calculation circuit and the second component calculation circuit. Then, the value of the obtained 16-bit width intermediate second component is re-input to the first component calculation circuit and the second component calculation circuit to further split it into an 8-bit width second component and an 8-bit width third component.

[0040] Figure 3 It is a flowchart showing a method 300 for processing a multi-bit width value according to an embodiment of the present disclosure. As mentioned above, according to the configuration information, the multi-bit width value here includes a high-bit part and a low-bit part. Through the processing of method 300, at least the multi-bit width value can be split into a first component and a second component representing it.

[0041] As Figure 3As shown in [figure], at step 302, method 300 receives the multi-bit width value and configuration information, where the configuration information at least includes the bit width information of the high-bit part or the low-bit part. With such configuration information, method 300 can at least determine the bit width value corresponding to the first component or the second component to be split. Then, at step 304, the multi-bit width value is calculated according to the bit width information of the low-bit part to obtain the first component representing the high-bit part in the multi-bit width value. In one embodiment, method 300 can determine a scaling factor according to the bit width information of the low-bit part; and use the scaling factor to calculate the multi-bit width value to obtain the first component. In one scenario, the scaling factor is determined according to the sign information included in the configuration information regarding whether the low-bit part contains a sign bit.

[0042] After calculating and obtaining the first component representing the high-bit part, method 300 proceeds to step 306. At this step 306, method 300 calculates according to the multi-bit width value and at least the value of the first component to obtain the second component representing the low-bit part in the multi-bit width value. In one embodiment, when the sign information in the foregoing configuration information indicates that the low-bit part contains a sign bit, method 300 may further include determining an adjustment value according to the bit width of the low-bit part; and calculating according to the multi-bit width value, the value of the first component, and the adjustment value to obtain the second component.

[0043] After obtaining the first component and the second component, method 300 proceeds to step 308. Here, method 300 outputs at least one of the first component and the second component. In one embodiment, the configuration information can be used to selectively output the first component, the second component, or both. In some embodiments, when the configuration information includes information on the number of split components, method 300 can repeatedly perform the splitting operation according to the number of components in the configuration information until the multi-bit width value is split into the required number. For example, in one scenario, when the required number of split components is a positive integer greater than 2, method 300 may further include determining at least one of the first component and the second component as the new multi-bit width value to be processed next according to the configuration information. Then, method 300 can perform calculation steps according to the high-bit part and the low-bit part of the foregoing new multi-bit width value to obtain the first component and the second component of the new multi-bit width value. To reach the predetermined number of components, method 300 can repeatedly perform the foregoing determination steps and calculation steps until the predetermined number of components is obtained.

[0044] The splitting operation performed by the aforementioned computing device or method of the present disclosure will be described from a mathematical calculation perspective. Through the following series of exemplary formula expressions and the splitting results of specific numerical values, those skilled in the art can further understand the solution of the present disclosure and its implementation. For the sake of simplicity of description, hereinafter, I0 represents a multi-bit width value with a bit width of n0, I1 is the first component obtained after splitting, and I2 is the second component obtained after splitting. The high-bit part of I0 is n1 bit wide and is represented by the first component I1, and the low-bit part of I0 is n2 bit wide and is represented by I2, where n0 = n1 + n2.

[0045] First, the first component I1 can be calculated by the following formula:

[0046] I1 = floor(I0 / 2 n2 ) (1)

[0047] where floor is the floor function, and 2 n2 represents the aforementioned scaling factor. As mentioned above, this scaling factor is also related to whether the low-bit part includes a sign bit. When the low-bit part does not include a sign bit, the expression of this scaling factor will be different (to be described later).

[0048] Next, the second component I2 can be calculated by the following formula:

[0049] I2 = I0 - I1 × 2 n2 -2 n2-1 (2)

[0050] It can be seen that the term "I1 × 2 n2 " in the above formula (2) is the value of the aforementioned first component. When I1 is multiplied by the scaling factor 2 n2 , it is equivalent to shifting it n2 bits towards the high-bit direction, and the term "2 n2-1 " in the formula is the aforementioned adjustment value. As mentioned above, when the configuration information indicates that the low-bit part includes a sign bit, by subtracting this adjustment value, the representation range of the I2 value can be expanded. In different splitting scenarios, n0, n1, and n2 in the formula can take different positive integer values. For example, n0 = 24, n1 = 8, n2 = 16, or n0 = 32, n1 = 16, n2 = 16. Since the formula here considers the sign bit, the first component and the second component obtained through the above formula are more accurate in representing the multi-bit width value before splitting and have less loss.

[0051] The case where the low-bit part contains a sign bit is given above. Below, the calculation formula for the case where the low-bit part does not contain a sign bit will be given, and the meanings of the symbols are the same as above.

[0052] First, the first component I1 can be calculated by the following formula:

[0053] I1 = floor(I0 / 2 n2-1 ) (3)

[0054] As mentioned above, since the sign bit of the low - bit part is not considered in this case, 2 n2-1 is used here to represent the aforementioned scaling factor, rather than "2 n2 " in Equation (1).

[0055] Next, the second component I2 can be calculated by the following formula:

[0056] I2 = I0 - I1 × 2 n2-1 (4)

[0057] It can be seen that, since the sign bit is not considered, Equation (4) does not have the adjustment value "2 n2-1 " in Equation (2). Further, the term "I1 × 2 n2-1 " here is the value of the first component.

[0058] In different splitting scenarios, n0, n1, and n2 in the above formula can take different positive integer values. For example, n0 = 24, n1 = 8, n2 = 16, or n0 = 32, n1 = 16, n2 = 16, or n0 = 25, n1 = 9, n2 = 16. In some splitting scenarios, n0, n1, and n2 can also satisfy n0 <= n1 + n2. For example, n0 = 25, n1 = 16, n2 = 16, that is, splitting a 25 - bit bit - width value into two 16 - bit bit - width components. For the first component and the second component calculated using Equation (1) and Equation (2), as mentioned above, since the sign bit is considered, the first component and the second component obtained have less loss in expressing the multi - bit - width value before splitting.

[0059] The splitting results of specific values are listed in Table (1) and Table (2) below, where Table (1) lists the splitting results considering the sign bit, and Table (2) lists the splitting results without considering the sign bit.

[0060] Table 1

[0061]

[0062] Table 2

[0063]

[0064] Figure 4It is a structural diagram showing a combined processing device 400 according to an embodiment of the present disclosure. As shown in the figure, the combined processing device 400 includes the aforementioned computing device 402, which can be configured to execute the splitting method described above in conjunction with the accompanying drawings. Additionally, the combined processing device further includes a general interconnect interface 404 and other processing devices 406. The computing device 402 according to the present disclosure can interact with other processing devices 406 through the general interconnect interface 404 to jointly complete operations specified by the user, such as splitting a multi-bit width value to obtain at least a first component and a second component.

[0065] According to the solution of the present disclosure, the other processing device may include one or more types of processors such as a central processing unit ("CPU"), a graphics processing unit ("GPU"), an artificial intelligence processor, etc., and the number thereof may not be limited but determined according to actual needs. In one or more embodiments, the other processing device may serve as an interface between the computing device of the present disclosure (which may be specifically embodied as an operation device related to artificial intelligence such as neural network operations) and external data and control, and perform operations including but not limited to data transfer, and complete basic control such as starting and stopping the computing device; the other processing device may also cooperate with the computing device to jointly complete computing tasks.

[0066] According to the solution of the present disclosure, the general interconnect interface can be used to transfer data and control instructions between the computing device and other processing devices. For example, the computing device can obtain input data to be split from other processing devices via the general interconnect interface and write it into the storage device (or memory) on the chip of the computing device. Further, the computing device can obtain control instructions from other processing devices via the general interconnect interface and write them into the control cache on the chip of the computing device. Alternatively or optionally, the general interconnect interface can also read data from the storage module of the computing device and transfer it to other processing devices.

[0067] Optionally, the combined processing device may further include a storage device 408, which can be respectively connected to the computing device and the other processing devices. In one or more embodiments, the storage device can be used to store data of the computing device and the other processing devices, especially those data that cannot be fully stored in the internal or on-chip storage devices of the computing device or other processing devices.

[0068] According to different application scenarios, the combined processing device of the present disclosure can be used as a system-on-chip (SOC) of devices such as mobile phones, robots, drones, video surveillance devices, etc., effectively reducing the core area of the control part, improving the processing speed, and reducing the overall power consumption. In this case, the general interconnect interface of the combined processing device is connected to certain components of the device. Certain components such as cameras, displays, mice, keyboards, network cards, or wifi interfaces.

[0069] In some embodiments, the present disclosure also discloses a chip, which includes the above-mentioned test device or combined processing device. In other embodiments, the present disclosure also discloses a chip package structure, which includes the above-mentioned chip.

[0070] In some embodiments, the present disclosure also discloses a board, which includes the above-mentioned chip package structure. Refer to Figure 5 , which provides the aforementioned exemplary board. In addition to including the above-mentioned chip 502, the above-mentioned board may further include other supporting components, and the supporting components include but are not limited to: a storage device 504, an interface device 506, and a control device 508.

[0071] The storage device is connected to the chip in the chip package structure through a bus and is used for storing data. The storage device may include multiple groups of storage units 510. Each group of the storage units is connected to the chip through a bus. It can be understood that each group of the storage units may be a DDR SDRAM ("Double Data Rate SDRAM").

[0072] DDR can double the speed of SDRAM without increasing the clock frequency. DDR allows data to be read out on both the rising edge and the falling edge of the clock pulse. The speed of DDR is twice that of standard SDRAM. In one embodiment, the storage device may include 4 groups of the storage units. Each group of the storage units may include multiple DDR4 dies (chips). In one embodiment, the chip may internally include 4 72-bit DDR4 controllers, and 64 bits of the 72-bit DDR4 controllers are used for data transmission and 8 bits are used for ECC check.

[0073] In one embodiment, each group of the storage units includes multiple double data rate synchronous dynamic random access memories arranged in parallel. DDR can transfer data twice within one clock cycle. A controller for controlling DDR is provided in the chip for controlling the data transmission and data storage of each of the storage units.

[0074] The interface device is electrically connected to the chip within the chip packaging structure. The interface device is used to implement data transmission between the chip and an external device 512 (such as a server or a computer). For example, in one embodiment, the interface device may be a standard PCIE interface. For instance, the data to be processed is transferred from the server to the chip through the standard PCIE interface to achieve data transfer. In another embodiment, the interface device may also be other interfaces. The present disclosure does not limit the specific forms of the above-mentioned other interfaces, as long as the interface unit can achieve the transfer function. Additionally, the calculation result of the chip is still transmitted back to the external device (such as a server) by the interface device.

[0075] The control device is electrically connected to the chip. The control device is used to monitor the state of the chip. Specifically, the chip and the control device may be electrically connected through an SPI interface. The control device may include a microcontroller unit (MCU). In one or more embodiments, the chip may include multiple processing chips, multiple processing cores, or multiple processing circuits, and can drive multiple loads. Therefore, the chip may be in different working states such as multi-load and light-load. Through the control device, the working states of multiple processing chips, multiple processes, and / or multiple processing circuits in the chip can be regulated.

[0076] In some embodiments, the present disclosure also discloses an electronic device or apparatus, which includes the above-mentioned board. According to different application scenarios, the electronic device or apparatus may include a data processing device, a robot, a computer, a printer, a scanner, a tablet computer, a smart terminal, a mobile phone, a driving recorder, a navigator, a sensor, a camera, a server, a cloud server, a camera, a video camera, a projector, a watch, headphones, a mobile storage device, a wearable device, a vehicle, a household appliance, and / or a medical device. The vehicle includes an airplane, a ship, and / or a vehicle; the household appliance includes a television, an air conditioner, a microwave oven, a refrigerator, a rice cooker, a humidifier, a washing machine, a light, a gas stove, an oil fume extractor; the medical device includes a nuclear magnetic resonance instrument, a B-ultrasound instrument, and / or an electrocardiogram instrument.

[0077] It should be noted that for the foregoing method embodiments, for the sake of simple description, they are all expressed as a series of action combinations. However, those skilled in the art should know that the present disclosure is not limited by the described action sequence, because according to the present disclosure, certain steps may be performed in other sequences or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily essential to the present disclosure.

[0078] In the above embodiments, the descriptions of the various embodiments have their own focuses. For parts not detailed in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

[0079] In several embodiments provided in this disclosure, it should be understood that the disclosed device can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other can be through some interfaces. The indirect couplings or communication connections of the devices or units can be in electrical, optical, acoustic, magnetic or other forms.

[0080] The units described as separate components may or may not be physically separated. The components displayed as units may or may not be physical units, that is, they can be located in one place, or they can be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0081] In addition, in each embodiment of this disclosure, the functional units can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit. The above integrated units can be implemented in the form of hardware or in the form of software program modules.

[0082] If the above integrated unit is implemented in the form of a software program module and sold or used as an independent product, it can be stored in a computer-readable memory. Based on this understanding, when the technical solution of this disclosure can be embodied in the form of a software product (such as a computer-readable storage medium), the computer software product is stored in a memory and includes several instructions for causing a computer device (which can be a personal computer, a server or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this disclosure. And the aforementioned memory includes: various media such as USB flash drives, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), mobile hard disks, magnetic disks or optical discs that can store program codes.

[0083] In the above embodiments of the present disclosure, the descriptions of the respective embodiments have their own focuses. For parts not detailed in a certain embodiment, reference may be made to the relevant descriptions of other embodiments. The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as within the scope described in this specification.

[0084] The foregoing can be better understood in accordance with the following clauses:

[0085] Clause 1. A computing device for processing a multi-bit width value, wherein the multi-bit width value includes a high-bit part and a low-bit part, and the computing device includes:

[0086] An input circuit configured to receive the multi-bit width value and configuration information, wherein the configuration information includes at least the bit width information of the high-bit part or the low-bit part;

[0087] A first component calculation circuit configured to calculate the multi-bit width value according to the bit width information of the low-bit part to obtain a first component representing the high-bit part in the multi-bit width value;

[0088] A second component calculation circuit configured to calculate according to the multi-bit width value and at least the value of the first component to obtain a second component representing the low-bit part in the multi-bit width value; and

[0089] An output circuit configured to output at least one of the first component and the second component.

[0090] Clause 2. The computing device according to Clause 1, wherein in calculating the multi-bit width value according to the bit width information of the low-bit part, the first component calculation circuit is configured to:

[0091] Determine a scaling factor according to the bit width information of the low-bit part; and

[0092] Calculate the multi-bit width value using the scaling factor to obtain the first component.

[0093] Clause 3. The computing device according to Clause 2, wherein the configuration information further includes sign information regarding whether the low-bit part includes a sign bit, and the first component calculation circuit is configured to determine the scaling factor according to the sign information.

[0094] Clause 4. The computing device according to any one of Clauses 1-3, wherein the first component calculation circuit further includes a scaling circuit and a rounding circuit, wherein the scaling circuit is configured to perform a shift operation on the multi-bit width value according to the scaling factor, and the rounding circuit is configured to perform a rounding operation on the multi-bit width value after the shift operation to obtain the first component.

[0095] Clause 5. The computing device according to Clause 3, wherein the symbol information indicates that the low-bit part includes a sign bit, and the second component calculation circuit is configured to:

[0096] Determine an adjustment value according to the bit width information of the low-bit part; and

[0097] Perform a calculation according to the multi-bit width value, the value of the first component, and the adjustment value to obtain the second component.

[0098] Clause 6. The computing device according to Clause 5, wherein the second component calculation circuit includes a subtraction circuit configured to subtract the value of the first component and the adjustment value from the multi-bit width value to obtain the second component.

[0099] Clause 7. The computing device according to Clause 1, further including a type converter configured to convert the input data into the same data type as the multi-bit width value.

[0100] Clause 8. The computing device according to Clause 1, further including a selector configured to select at least one of the first component and the second component to the output circuit according to the configuration information.

[0101] Clause 9. The computing device according to any one of Clauses 5-8, wherein the configuration information further includes information on the number of components, and when the number of components is a positive integer greater than 2, the computing device repeatedly executes the first component calculation circuit and the second component calculation circuit according to the configuration information until the components of the number of components are obtained.

[0102] Clause 10. An integrated circuit chip including the computing device according to any one of Clauses 1-9.

[0103] Clause 11. An integrated circuit board including the integrated circuit chip according to Clause 10.

[0104] Clause 12. A method for processing a multi-bit width value, wherein the multi-bit width value includes a high-bit part and a low-bit part, and the method includes:

[0105] Receive the multi-bit width value and configuration information, where the configuration information at least includes the bit width information of the high bit part or the low bit part;

[0106] Calculate the multi-bit width value according to the bit width information of the low bit part to obtain a first component representing the high bit part in the multi-bit width value;

[0107] Calculate according to the multi-bit width value and at least the value of the first component to obtain a second component representing the low bit part in the multi-bit width value; and

[0108] Output at least one of the first component and the second component.

[0109] Clause 13. The method according to clause 12, wherein in calculating the multi-bit width value according to the bit width information of the low bit part, the method further includes:

[0110] Determine a scaling factor according to the bit width information of the low bit part; and

[0111] Calculate the multi-bit width value using the scaling factor to obtain the first component.

[0112] Clause 14. The method according to clause 13, wherein the configuration information further includes sign information on whether the low bit part includes a sign bit, and the method further includes determining the scaling factor according to the sign information.

[0113] Clause 15. The method according to clause 14, wherein the sign information indicates that the low bit part includes a sign bit, and the method further includes:

[0114] Determine an adjustment value according to the bit width information of the low bit part; and

[0115] Calculate according to the multi-bit width value, the value of the first component, and the adjustment value to obtain the second component.

[0116] Clause 16. The method according to any one of clauses 12-15, wherein the configuration information further includes information on the number of components, and when the number of components is a positive integer greater than 2, the method further includes:

[0117] Determine at least one of the first component and the second component as a new multi-bit width value to be processed next according to the configuration information;

[0118] Execute calculation steps according to the high bit part and the low bit part of the new multi-bit width value to obtain the first component and the second component of the new multi-bit width value; and

[0119] Repeat the above determination step and calculation step until the components of the said number of components are obtained.

[0120] Clause 17. A computing device for processing multi-bit width values, comprising:

[0121] A processor;

[0122] A memory for storing program instructions, which when executed by the at least one processor cause the computing device to perform the method according to any one of Clauses 12-16.

[0123] Clause 18. A computer-readable storage medium having stored thereon program instructions for processing multi-bit width values, which when run by a processor, perform the method according to Clauses 12-16. The above embodiments of the present disclosure have been described in detail. Specific examples are used herein to elaborate on the principles and implementation manners of the present disclosure. The description of the above embodiments is only used to help understand the method and its core idea of the present disclosure; at the same time, for those of ordinary skill in the art, according to the idea of the present disclosure, there will be changes in the specific implementation manners and application scopes. In summary, the content of this specification should not be construed as a limitation on the present disclosure.

[0124] It should be understood that the terms "first", "second", "third", "fourth", etc. in the claims, specification and drawings of the present disclosure are used to distinguish different objects, rather than to describe a specific order. The terms "comprising" and "including" used in the specification and claims of the present disclosure indicate the presence of the described features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or their combinations.

[0125] It should also be understood that the terms used in this specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used in the specification and claims of the present disclosure, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include the plural forms. It should be further understood that the term "and / or" used in the specification and claims of the present disclosure refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0126] As used in this specification and the claims, the term "if" can be construed contextually as "when" or "once" or "in response to determining" or "in response to detecting". Similarly, the phrase "if determined" or "if [described condition or event] is detected" can be construed contextually to mean "once determined" or "in response to determining" or "once [described condition or event] is detected" or "in response to detecting [described condition or event]".

[0127] The embodiments of the present disclosure have been described in detail above. Specific examples are used herein to illustrate the principles and implementation manners of the present disclosure. The description of the above embodiments is only for helping to understand the method and its core idea of the present disclosure. At the same time, any changes or deformations made by those skilled in the art based on the idea of the present disclosure within the specific implementation manners and application scope of the present disclosure fall within the protection scope of the present disclosure. In summary, the content of this specification should not be construed as a limitation to the present disclosure.

Claims

1. A computing device for processing multi-bit width values, wherein the multi-bit width values include a high-bit part and a low-bit part, and the computing device includes: An input circuit configured to receive the multi-bit width value and configuration information, wherein the configuration information includes at least the bit width information of the high-bit part or the low-bit part; A first component calculation circuit configured to calculate the multi-bit width value according to the bit width information of the low-bit part to obtain a first component representing the high-bit part in the multi-bit width value; A second component calculation circuit configured to calculate according to the multi-bit width value and at least the value of the first component to obtain a second component representing the low-bit part in the multi-bit width value; And An output circuit configured to output at least one of the first component and the second component.

2. The computing device according to claim 1, wherein in calculating the multi-bit width value according to the bit width information of the low-bit part, the first component calculation circuit is configured to: Determine a scaling factor according to the bit width information of the low-bit part; and Calculate the multi-bit width value using the scaling factor to obtain the first component.

3. The computing device according to claim 2, wherein the configuration information further includes sign information on whether the low-bit part includes a sign bit, and the first component calculation circuit is configured to determine the scaling factor according to the sign information.

4. The computing device according to any one of claims 1-3, wherein the first component calculation circuit further includes a scaling circuit and a rounding circuit, wherein the scaling circuit is configured to perform a shift operation on the multi-bit width value according to the scaling factor, and the rounding circuit is configured to perform a rounding operation on the multi-bit width value after the shift operation to obtain the first component.

5. The computing device according to claim 3, wherein the sign information indicates that the low-bit part includes a sign bit, and the second component calculation circuit is configured to: Determine an adjustment value according to the bit width information of the low-bit part; and Calculate according to the multi-bit width value, the value of the first component, and the adjustment value to obtain the second component.

6. The computing device according to claim 5, wherein the second component calculation circuit includes a subtraction circuit configured to subtract the value of the first component and the adjustment value from the multi-bit width value to obtain the second component.

7. The computing device according to claim 1, further including a type converter configured to convert the input data into the same data type as the multi-bit width value.

8. The computing device according to claim 1, further including a selector configured to select at least one of the first component and the second component to the output circuit according to the configuration information.

9. The computing device according to any one of claims 5-8, wherein the configuration information further includes information on the number of components, and when the number of components is a positive integer greater than 2, the computing device repeatedly executes the first component calculation circuit and the second component calculation circuit according to the configuration information until components of the number of components are obtained.

10. An integrated circuit chip, comprising the computing device according to any one of claims 1-9.

11. An integrated circuit board, comprising the integrated circuit chip according to claim 10.

12. A method for processing a multi-bit width value, wherein the multi-bit width value includes a high-bit part and a low-bit part, the method comprising: Receiving the multi-bit width value and configuration information, wherein the configuration information at least includes bit width information of the high-bit part or the low-bit part; Calculating the multi-bit width value according to the bit width information of the low-bit part to obtain a first component representing the high-bit part in the multi-bit width value; Calculating according to the multi-bit width value and at least the value of the first component to obtain a second component representing the low-bit part in the multi-bit width value; And Outputting at least one of the first component and the second component.

13. The method according to claim 12, wherein in calculating the multi-bit width value according to the bit width information of the low-bit part, the method further comprises: Determining a scaling factor according to the bit width information of the low-bit part; And Calculating the multi-bit width value by using the scaling factor to obtain the first component.

14. The method according to claim 13, wherein the configuration information further includes sign information on whether the low-bit part includes a sign bit, and the method further comprises determining the scaling factor according to the sign information.

15. The method according to claim 14, wherein the sign information indicates that the low-bit part includes a sign bit, the method further comprising: Determining an adjustment value according to the bit width information of the low-bit part; And Calculating according to the multi-bit width value, the value of the first component, and the adjustment value to obtain the second component.

16. The method according to any one of claims 12-15, wherein the configuration information further includes information on the number of components, and when the number of components is a positive integer greater than 2, the method further comprises: Determining at least one of the first component and the second component as a new multi-bit width value to be processed next according to the configuration information; Performing calculation steps according to the high-bit part and the low-bit part of the new multi-bit width value to obtain a first component and a second component of the new multi-bit width value; And Repeatedly performing the above determination step and calculation step until components of the number of components are obtained.

17. A computing device for processing a multi-bit width value, comprising: A processor; A memory for storing program instructions which, when executed by the at least one processor, cause the computing device to perform the method according to any one of claims 12 - 16.

18. A computer-readable storage medium having stored thereon program instructions for processing multi-bit width values which, when run by a processor, perform the method according to any one of claims 12 - 16.

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