Computing device, method, board and computer readable storage medium

Abstract

The present disclosure discloses a computing device, an integrated circuit board, a method, and a computer-readable storage medium for processing multi-bit width values, wherein the computing device may be included in a combined processing device, and the combined processing device may also include a universal interconnection interface and other processing devices. The computing device interacts with other processing devices to jointly complete the computing operations specified by the user. The combined processing device may also include a storage device, which is respectively connected to the device and the other processing devices to store data of the device and the other processing devices. The solution disclosed herein can split multi-bit width values ​​so that the processing power of the processor is not affected by the bit width.

Description

Technical Field

[0001] The present disclosure generally relates to data processing and, more particularly, to a computing device, method, integrated circuit board, and computer-readable storage medium for processing multi-bit width values. Background Art

[0002] Currently, different types of processors may process different data bit widths. Processors that perform operations on specific data types often have limited bit widths. For example, fixed-point arithmetic units (APUs) typically can only process data with a bit width of no more than 16 bits, such as 16-bit integer data. However, in order to save computing costs and overhead and improve computing efficiency, enabling processors with limited bit widths to process data with wider bit widths has become a technical problem that needs to be solved. Summary of the Invention

[0003] To at least address the technical issues mentioned above, the present disclosure proposes, in various aspects, a solution for splitting multi-bit-width data. This splitting solution allows multi-bit-width data to be split into at least two smaller-bit-width data for representation. This allows the use of the two smaller-bit-width data for computation in scenarios where the processor's processing bit width is limited.

[0004] In a first aspect, the present disclosure provides a computing device for processing multi-bit width values ​​for neural network operations, comprising:

[0005] an input circuit configured to receive the multi-bit width value and configuration information, wherein the configuration information includes at least width information of a first component and width information of a second component representing the multi-bit width value;

[0006] a first component calculation circuit configured to calculate the adjusted multi-bit bit-width value according to a scaling factor associated with the bit-width information of the second component to obtain a first component representing the multi-bit bit-width value;

[0007] a second component calculation circuit configured to perform calculation based on at least the adjusted multi-bit width value and the value of the first component to obtain a second component representing the multi-bit width value; and

[0008] An output circuit is configured to output at least one of the first component and the second component.

[0009] In a second aspect, the present disclosure provides an integrated circuit chip comprising the aforementioned computing device.

[0010] In a third aspect, the present disclosure provides an integrated circuit board comprising the aforementioned integrated circuit chip.

[0011] In a fourth aspect, the present disclosure provides a method for processing multi-bit width values ​​for neural network operations, comprising:

[0012] receiving the multi-bit width value and configuration information, wherein the configuration information includes at least width information of a first component and width information of a second component representing the multi-bit width value;

[0013] calculating the adjusted multi-bit width value according to a scaling factor associated with the bit width information of the second component to obtain a first component representing the multi-bit width value;

[0014] performing a calculation based on at least the adjusted multi-bit width value and the value of the first component to obtain a second component representing the multi-bit width value; and

[0015] At least one of the first component and the second component is output.

[0016] In a fifth aspect, the present disclosure provides a computing device for processing multi-bit width values, comprising:

[0017] processor;

[0018] The memory is used to store program instructions, and when the program instructions are executed by the at least one processor, the computing device executes the aforementioned method.

[0019] In a sixth aspect, the present disclosure provides a computer-readable storage medium having stored thereon program instructions for processing multi-bit width values ​​for neural network operations, wherein when the program instructions are executed by a processor, the aforementioned method is performed.

[0020] Through the computing device, integrated circuit board, method, and computer-readable storage medium provided above, the disclosed solution can split a multi-bit (or high-bit width) value into multiple small (or low-bit width) values ​​for expression, thereby fully utilizing the processor's computing power in artificial intelligence application scenarios including, for example, neural network operations or other general scenarios without being limited by the processor's processing bit width. Furthermore, in some neural network operation scenarios requiring low-bit width values, the disclosed solution can also simplify neural network calculations by splitting multi-bit width values ​​into multiple low-bit width expressions, thereby improving computational efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The above features of the present disclosure can be better understood by referring to the accompanying drawings, and its numerous purposes, features, and advantages will be apparent to those skilled in the art. The drawings described below are merely some embodiments of the present disclosure. Those skilled in the art can derive other drawings based on these drawings without inventive effort, including:

[0022] Figure 1 is a simplified block diagram illustrating a computing device according to an embodiment of the present disclosure;

[0023] Figure 2 is a detailed block diagram illustrating a computing device according to an embodiment of the present disclosure;

[0024] Figure 3 is a flow chart illustrating processing of multi-bit width values ​​according to an embodiment of the present disclosure;

[0025] Figure 4 is a structural diagram illustrating a combined processing device according to an embodiment of the present disclosure; and

[0026] Figure 5 2 is a schematic diagram showing the structure of a board according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0027] The scheme disclosed herein overcomes the obstacle of processor bit width limitation by allowing a multi-bit width (e.g., 24-bit) value to be expressed by at least two low-bit (e.g., 16-bit and 8-bit) width components, simplifies the computational complexity, and thereby improves the computational efficiency of, for example, neural network computations. In one or more embodiments, the source or initial value can be divided into a high-bit portion and a low-bit portion based on the bit distribution and configuration information of the input multi-bit width value, and a split calculation is performed on the high-bit portion and the low-bit portion to obtain a first component and a second component corresponding to the high-bit portion and the low-bit portion. Thus, in actual calculations, at least one of the first component and the second component can be used to replace the source value in the calculation. In another embodiment, the scheme disclosed herein can also decompose the aforementioned source value into multiple required components based on the configuration information, for example, repeatedly performing a similar split calculation on at least one of the aforementioned first component and the second component to obtain more than three components.

[0028] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0029] Figure 1is a simplified block diagram of a computing device 100 according to an embodiment of the present disclosure. In one or more embodiments, the computing device 100 can process multi-bit width values ​​for use in various application scenarios, such as artificial intelligence applications including neural network operations or general scenarios where values ​​need to be split for calculation. Here, the multi-bit width value can include a high-bit part and a low-bit part for subsequent splitting into two or more components. In addition, the aforementioned neural network operations can include various operations in training neural networks, such as weight updates or gradient calculations in the backpropagation direction.

[0030] like Figure 1 As shown in , the computing device 100 includes an input circuit 102, which is configured to receive a multi-bit width value and configuration information, wherein the configuration information includes at least the width information of the first component representing the multi-bit width value and the width information of the second component. For example, when the multi-bit width value is 24 bits wide, it can be divided into an 8-bit high bit part and a 16-bit low bit part, that is, an 8-bit width component and a 16-bit width component to be split. In one or more embodiments, the configuration information may further include sign information indicating whether the width information of the second component includes a sign bit. For example, when expressed in bits, "1" indicates that the second component includes a sign bit, and "0" indicates that the low bit part does not include a sign bit. Additionally, the configuration information may further include valid bit information, such as forcibly specifying which bits in the multi-bit width value are valid bits, so that calculations are performed on the valid bits in subsequent split calculations.

[0031] Connected to the input circuit 102 is a first component calculation circuit 104 and a second component calculation circuit 106. In one or more embodiments, the first component calculation circuit can be configured to calculate the adjusted multi-bit width value according to a scaling factor associated with the bit width information of the second component to obtain a first component representing the multi-bit width value. In one scenario, the first component calculation circuit can determine the scaling factor according to the bit width information of the second component and calculate the multi-bit width value using the scaling factor to obtain the first component. For example, when the bit width of the first component is n1 and the bit width of the second component is n2, when the sign bit is not considered in n2, the scaling factor can be 2 n2-1 In contrast, when considering n2 including the sign bit, the scaling factor can be 2 n2 .

[0032] Before calculating the multi-bit width value, in one or more embodiments, the computing device of the present disclosure may further determine the size of the multi-bit width value and the specified data to perform corresponding numerical adjustments. For example, when the specified data is zero, when the multi-bit width value is greater than or equal to zero, it is added to a given constant to obtain the adjusted multi-bit width value. In contrast, when the multi-bit width value is less than zero, the multi-bit width value is subtracted from the given constant to obtain the adjusted multi-bit width value.

[0033] In one or more embodiments, the second component calculation circuit can be configured to perform a calculation based on at least the adjusted multi-bit width value and the value of the first component to obtain a second component representing the multi-bit width value. In one scenario, when the sign information indicates that the bit width information of the second component does not include a sign bit, for example, the highest bit of the second component bit width is not a sign bit, the second component calculation circuit can be configured to subtract the value of the first component from the adjusted multi-bit width value to obtain the second component. Here, the value of the first component can be the product value of the first component and the aforementioned scaling factor. In another scenario, when the sign information in the configuration information indicates that the bit width information of the second component includes a sign bit, for example, when the highest bit of the second component bit width is a sign bit, the second component calculation circuit can be configured to determine an adjustment value based on the bit width information of the second component, and to perform a calculation based on the multi-bit width value, the value of the first component and the adjustment value to obtain the second component. It can be understood that in some scenarios, the aforementioned configuration information may not include sign information. In this case, through, for example, an initial default setting, the computing device of the present disclosure can be configured to directly perform a split operation considering the sign bit or perform a split operation without considering the sign bit, without making a judgment on whether to consider the sign bit based on configuration information.

[0034] The above describes how to obtain the first component and the second component described in the present disclosure, but it should be understood that the above description is merely exemplary and not restrictive, and those skilled in the art can also think of other optional or alternative solutions based on the above description. For example, in some scenarios, according to different adjustment methods for the aforementioned multi-bit width values, various corresponding rounding operations can be performed on the intermediate values ​​before obtaining the first component and the second component. These rounding operations may include rounding to zero, rounding up, rounding down, etc., respectively. For example, after calculating the adjusted multi-bit width value using the scaling factor, the obtained value can be rounded to zero to obtain the first component. Similarly, after subtracting the value of the first component and the adjustment value from the adjusted multi-bit width value, the obtained value can also be rounded to zero to obtain the second component.

[0035] After obtaining the first component and the second component that can represent the multi-bit width value, the computing device disclosed herein also includes an output circuit 108, which can be configured to output at least one of the first component and the second component. As mentioned above, the first component and the second component output by the output circuit can be applied to various types of calculations in neural networks that require the use of low-bit width data, such as weight updates and gradient calculations for back propagation in neural network training. In some application scenarios, the obtained first component and the second component can also be directly stored to replace the multi-bit width value for later use. In a scenario where the neural network uses a fixed-point processor that supports low bit width to perform fixed-point operations, by using the first component and the second component of the low bit width output by the output circuit for the fixed-point operations of the fixed-point processor, the fixed-point processor will get rid of the limitation of not being able to process multi- or high-bit width data, expand the computing scenarios of the fixed-point processor and simplify the calculation, thereby also improving the computing efficiency and reducing the computing overhead.

[0036] Figure 2 is a detailed block diagram showing a computing device 200 according to an embodiment of the present disclosure. Figure 2 As can be seen from the figure, the computing device 200 not only includes Figure 1 The input circuit 102, the first component circuit 104, the second component circuit 106 and the output circuit 108 of the computing device 100 are further shown, and multiple circuits included in the first and second component circuits, as well as multiple other devices are additionally shown. Figure 1 The functions of the input circuit, the first component and second component calculation circuit, and the output circuit have been described in detail and will not be repeated hereafter.

[0037] like Figure 2 As shown in , the computing device 200 may further include a type converter 110, which may be configured to convert the input data into the same data type as the multi-bit width numerical value, that is, the data type supported by the first component calculation circuit and the second component calculation circuit. By setting the type converter, the computing device of the present disclosure can perform splitting on data of a different type than the data type supported by the splitting operation. For example, when the computing device of the present disclosure supports the splitting of fixed-point values, when the input circuit receives a floating-point value, the floating-point value can be converted into a fixed-point integer value by the type converter, so that it can be split by the first component calculation circuit and the second component calculation circuit. Similarly, when the computing device of the present disclosure supports the splitting of floating-point values, when the input circuit receives a fixed-point value, the fixed-point value can be converted into a floating-point value by the type converter, so that it can be split by the first component calculation circuit and the second component calculation circuit.

[0038] Furthermore, the computing device may further include a determination circuit 112, which may be configured to determine the size of the multi-bit width value and the specified data, and send the determination result to the addition circuit 114. In one embodiment, the addition circuit may be configured to perform an addition or subtraction operation on the multi-bit width value and a given constant based on the determination result to obtain the adjusted multi-bit width value. In one implementation scenario, the addition circuit here may include a negation circuit, so that the subtraction operation can be converted into an addition operation. In another implementation scenario, the aforementioned addition circuit may be an adder that supports subtraction operations. In addition, the adder here is merely exemplary, and those skilled in the art may also arrange adders and subtractors separately according to the teachings of this disclosure, so as to respectively complete the corresponding addition and subtraction operations.

[0039] The first component calculation circuit 104 further shown may include a scaling circuit 1041 and a rounding circuit 1042. In one embodiment, the scaling circuit is configured to perform a shift operation on the adjusted multi-bit width value according to the aforementioned scaling factor. For example, when the scaling factor is 2 n2 When performing a shift operation using a shift circuit, the multi-bit width value is shifted n2 bits toward the upper bit. When the upper bit is on the left side of the multi-bit width value and the lower bit is on its right side, shifting n2 bits toward the upper bit is equivalent to shifting n2 bits to the left. In terms of specific implementation, the shift circuit here can be constructed using a multiplier. After performing the corresponding shift operation on the multi-bit width value, in one embodiment, the first component calculation circuit also includes a rounding circuit 1042, which can be configured to round the multi-bit width value after the shift operation to obtain the first component. Depending on different application scenarios, the rounding operation here can include various forms of rounding operations, such as rounding up, rounding down, rounding toward zero, and other rounding operations. After such rounding operations, the first component related to the upper bit portion of the multi-bit width value can be obtained.

[0040] In one or more embodiments, the second component calculation circuit 106 may include a subtraction circuit 1061 configured to subtract the value of the first component and the adjustment value from the multi-bit width value to obtain the second component. In one scenario, the value of the first component may be the product of the first component and the scaling factor, and the adjustment value is the aforementioned value after taking into account the sign bit of the low-bit portion. By using the subtraction circuit to subtract the product value and the adjustment value from the multi-bit width value, the second component associated with the low-bit portion of the multi-bit width value can be obtained.

[0041] In order to achieve flexible output, the computing device 200 disclosed herein additionally includes a selector 116, which can be configured to output at least one of the first component and the second component to the output circuit 108 for output. In one embodiment, the selector 116 can choose to output the first component, the second component, or both according to the information about the input item included in the configuration information. Such selective output has technical advantages in some application scenarios. For example, when only the first component or the second component is required to participate in subsequent operations, the output circuit does not need to output both, thereby saving overhead in terms of output. In addition, when only the first component needs to be output, the computing device disclosed herein can also only calculate the first component and output it, thereby further saving computing overhead.

[0042] In one or more embodiments, the computing device disclosed herein can also be used to decompose a multi-bit width value into multiple components specified by the user or required by the algorithm for expression. To this end, the aforementioned configuration information can include information on the number of components. When the number of components is a positive integer greater than 2, the computing device disclosed herein repeatedly executes the first component calculation circuit and the second component calculation circuit according to the configuration information until the components of the number of components are obtained. For example, for a 24-bit width value, when the configuration information indicates that it is to be split into 3 components, and all three components are 8 bits wide, the 24-bit width value can be split into an 8-bit first component and a 16-bit middle second component by the first component calculation circuit and the second component calculation circuit. Then, the value of the 16-bit middle second component obtained is re-input into the first component calculation circuit and the second component calculation circuit to further split it into an 8-bit second component and an 8-bit third component.

[0043] Figure 3 3 is a flow chart illustrating a method 300 for processing a multi-bit width value according to an embodiment of the present disclosure. Through the processing of the method 300, the multi-bit width value can be split into at least a first component and a second component representing the multi-bit width value.

[0044] like Figure 3 As shown in , at step 302, the method 300 receives the multi-bit width value and configuration information, wherein the configuration information at least includes the width information of the first component and the width information of the second component representing the multi-bit width value. Through such configuration information, the method 300 can at least determine the bit width value corresponding to the first component or the second component to be split. Then, at step 304, the method 300 calculates the adjusted multi-bit width value according to the scaling factor associated with the width information of the second component to obtain the first component representing the multi-bit width value. As previously described in conjunction with Figure 1 and Figure 2As described above, the adjustment here can be to compare the multi-bit width value with the specified data, and perform an addition or subtraction operation on the multi-bit width value and a given constant based on the comparison result, thereby completing the corresponding adjustment. In one embodiment, method 300 can determine a scaling factor based on the bit width information of the second component, and use the scaling factor to calculate the adjusted multi-bit width value to obtain the first component. In one scenario, method 300 can determine the scaling factor based on the sign information included in the configuration information regarding whether the second component includes a sign bit.

[0045] After calculating and obtaining the first component representing the multi-bit width value, the method 300 proceeds to step 306. At this step 306, the method 300 performs calculations based on at least the adjusted multi-bit width value and the value of the aforementioned first component to obtain a second component representing the multi-bit width value. In one embodiment, when the sign information in the aforementioned configuration information indicates that the bit width information of the second component includes a sign bit, the method 300 may further include determining an adjustment value based on the bit width information of the second component, and performing calculations based on the adjusted multi-bit width value, the value of the first component and the adjustment value to obtain the second component. In one implementation scenario, the value of the first component and the adjustment value may be subtracted from the adjusted multi-bit width value to obtain the second component. Furthermore, after subtracting the value of the first component and the adjustment value from the multi-bit width value, a rounding operation corresponding to the operation of adjusting the multi-bit width value may be performed on the obtained value to obtain the second component.

[0046] After obtaining the first component and the second component, method 300 proceeds to step 308. Here, method 300 outputs at least one of the first component and the second component. In one embodiment, the first component, the second component, or both can be selectively output based on configuration information. In some embodiments, when the configuration information includes information about the number of components after splitting, method 300 can repeatedly perform the splitting operation based on the number of components in the configuration information until the multi-bit bit-width value is split to the required number. For example, in one scenario, when the number of components required to be split is a positive integer greater than 2, method 300 can also include determining at least one of the first component and the second component as the next new multi-bit bit-width value to be processed based on the configuration information. Next, method 300 can perform an adjustment operation on the new multi-bit bit-width data to obtain an adjusted new multi-bit bit-width value, and then perform calculations based on the bit-width information in the configuration information to obtain the first component and the second component representing the new multi-bit bit-width value. It can be seen that in order to reach the predetermined number of components, method 300 can repeatedly perform the aforementioned calculation steps of the first component and the second component until the predetermined number of components is obtained.

[0047] The splitting operation performed by the aforementioned computing device or method of the present disclosure will be described below from a mathematical calculation perspective. Through the following series of exemplary formula expressions and the splitting results of specific numerical values, those skilled in the art can further understand the scheme of the present disclosure and its implementation. For the sake of simplicity of description, f is used below to represent a multi-bit width value, which has a bit width of n0, I1 is the first component obtained after splitting and has a bit width of n1 length, and I2 is the second component obtained after splitting and has a bit width of n2 length, where n0=n1+n2.

[0048] First, f can be adjusted using the following formulas (1) and (2):

[0049] if f>=0: f=f+0.5 (1)

[0050] if f<0: f=f-0.5 (2)

[0051] The "0.5" in the above formula is the given constant mentioned above. By calculating the above formula (1) or (2), the adjusted multi-bit width value can be obtained.

[0052] Then, the first component I1 can be calculated by the following formula (3):

[0053]

[0054] Among them, to_zero is the rounding function, 2 n2-1 represents the aforementioned scaling factor, in which case the second component does not include a sign bit. As mentioned above, the scaling factor is also related to whether the second component includes a sign bit. When the second component includes a sign bit, the scaling factor here can be 2 n2 (described below)

[0055] Then, the second component I2 can be calculated by the following formula:

[0056] I2=to_zero(f-I1×2 n2-1 ) (4)

[0057] It can be seen that the “I1×2 n2-1 "The term is the value of the first component mentioned above. When I1 is multiplied by the scaling factor 2 n2-1 By the above calculation, the first component and the second component representing the multi-bit width value are obtained.

[0058] The above describes the splitting operation when the second component does not include the sign bit. The following describes the splitting operation when the second component includes the sign bit, wherein the meanings of the symbols in the formula are the same as above.

[0059] First, f can be adjusted using the following formulas (5) and (6):

[0060] iff>=0: f=f+0.5 (5)

[0061] if f<0: f=f-0.5 (6)

[0062] The "0.5" in the above formula is the given constant mentioned above. By calculating the above formula (5) or (6), the adjusted multi-bit width value can be obtained.

[0063] Then, the first component I1 can be calculated by the following formula (7):

[0064]

[0065] Since the second component includes a sign bit in this case, 2 is used here. n2 represents the aforementioned scaling factor, rather than the “2 n2-1 ”.

[0066] Then, the second component I2 can be calculated by the following equations (8) and (9):

[0067] If f<=0, then I2=to_zero(f-I1×2 n2 -2 n2-1 ) (8)

[0068] If f>0, then I2=floor(f-I1×2 n2 -2 n2-1 ) (9)

[0069] It can be seen that due to the consideration of the sign bit, equations (8) and (9) have an adjustment value "2" that is not present in equation (4). n2 -1 ”. Furthermore, “I1×2 n2 "The item is the value of the first component. In addition, after subtracting the value of the first component and the adjustment value from the multi-bit width value, the disclosed solution can also perform corresponding rounding operations on the obtained value, such as the rounding function "to_zero()" used in formula (8) and the rounding function "floor()" used in formula 9, so as to obtain the final first component and second component. Since formulas (8) and (9) take the sign bit into account, the obtained first component and second component have less loss in expressing the multi-bit width value before splitting.

[0070] In some application scenarios, when the multi-bit width value is a floating point number, it can be rounded (e.g., rounded to the nearest integer) to obtain a fixed point number, and then the first component and the second component obtained by the splitting operation of the above formula (1)-(4) or the above formula (5)-(9) can also represent the fixed point number to participate in the operation, which is particularly beneficial for fixed-point number operations in artificial intelligence applications. In addition, in different splitting scenarios, n0, n1, and n2 in the above formula can take different positive integer values, such as n0=24, n1=8, n2=16, or n0=32, n1=16, n2=16, or n0=25, n1=9, n2=16. In some splitting scenarios, n0, n1, and n2 can also satisfy n0<=n1+n2, such as n0=25, n1=16, n2=16, that is, the 25-bit width value is split into two 16-bit width components.

[0071] The following tables list the splitting results of specific numerical values ​​(taking floating-point numbers as an example), where Tables (1) and (2) list the splitting results considering the sign bit, while Tables (3) and (4) list the splitting results without considering the sign bit.

[0072] Table 1

[0073]

[0074] Table 2

[0075]

[0076] Table 3

[0077]

[0078] Table 4

[0079]

[0080] Figure 4 is a block diagram illustrating a combined processing device 400 according to an embodiment of the present disclosure. As shown, the combined processing device 400 includes the aforementioned computing device 402, which can be configured to execute the splitting method described above in conjunction with the accompanying figures. Furthermore, the combined processing device also includes a universal interconnect interface 404 and other processing devices 406. The computing device 402 according to the present disclosure can interact with the other processing devices 406 via the universal interconnect interface 404 to jointly perform user-specified operations, such as splitting a multi-bit value to obtain at least a first component and a second component.

[0081] According to the solution disclosed herein, the other processing devices may include one or more types of processors such as a central processing unit ("CPU"), a graphics processing unit ("GPU"), an artificial intelligence processor, and general-purpose and / or special-purpose processors. The number of such processors is not limited but determined according to actual needs. In one or more embodiments, the other processing devices may serve as an interface between the computing device disclosed herein (which may be embodied as an artificial intelligence computing device such as a neural network computing device) and external data and control, performing functions including but not limited to data transfer and completing basic control of the computing device, such as starting and stopping the computing device; the other processing devices may also collaborate with the computing device to jointly complete computing tasks.

[0082] According to the solution disclosed herein, the universal interconnect interface can be used to transmit data and control instructions between the computing device and other processing devices. For example, the computing device can obtain input data to be split from other processing devices via the universal interconnect interface and write it to the storage device (or memory) on the computing device chip. Furthermore, the computing device can obtain control instructions from other processing devices via the universal interconnect interface and write them to the control cache on the computing device chip. Alternatively or optionally, the universal interconnect interface can also read data from the storage module of the computing device and transmit it to other processing devices.

[0083] Optionally, the combined processing device may further include a storage device 408, which may be connected to the computing device and the other processing device, respectively. In one or more embodiments, the storage device may be used to store data of the computing device and the other processing device, especially data that cannot be fully stored in the internal or on-chip storage device of the computing device or other processing device.

[0084] Depending on the application scenario, the combined processing device disclosed herein can serve as a system-on-chip (SoC) for devices such as mobile phones, robots, drones, and video surveillance equipment, effectively reducing the core area of ​​the control unit, increasing processing speed, and lowering overall power consumption. In this case, the universal interconnect interface of the combined processing device connects to certain components of the device, such as a camera, display, mouse, keyboard, network card, or Wi-Fi interface.

[0085] In some embodiments, the present disclosure further discloses a chip, which includes the above-mentioned testing device or combined processing device. In other embodiments, the present disclosure further discloses a chip packaging structure, which includes the above-mentioned chip.

[0086] In some embodiments, the present disclosure further discloses a board card, which includes the above chip packaging structure. Figure 5, which provides the aforementioned exemplary board card. In addition to the aforementioned chip 502 , the aforementioned board card may also include other supporting components, including but not limited to: a storage device 504 , an interface device 506 and a control device 508 .

[0087] The memory device is connected to the chip within the chip package structure via a bus for storing data. The memory device may include multiple groups of memory cells 510. Each group of memory cells is connected to the chip via a bus. It is understood that each group of memory cells may be DDR SDRAM ("Double Data Rate SDRAM").

[0088] The above-mentioned DDR can double the speed of SDRAM without increasing the clock frequency. DDR allows data to be read out on the rising and falling edges of the clock pulse. The speed of DDR is twice that of standard SDRAM. In one embodiment, the memory device may include four groups of memory cells. Each group of memory cells may include multiple DDR4 particles (chips). In one embodiment, the chip may include four 72-bit DDR4 controllers, of which 64 bits are used for data transmission and 8 bits are used for ECC verification.

[0089] In one embodiment, each group of the memory cells includes a plurality of double data rate synchronous dynamic random access memories (DDRs) connected in parallel. DDRs can transmit data twice within one clock cycle. A controller for controlling the DDRs is provided in the chip to control data transmission and data storage in each of the memory cells.

[0090] The interface device is electrically connected to the chip in the chip packaging structure. The interface device is used to realize data transmission between the chip and an external device 512 (such as a server or a computer). For example, in one embodiment, the interface device can be a standard PCIE interface. For example, the data to be processed is transferred from the server to the chip through the standard PCIE interface to realize data transfer. In another embodiment, the interface device can also be other interfaces. This disclosure does not limit the specific form of expression of the above-mentioned other interfaces. The interface unit can realize the switching function. In addition, the calculation results of the chip are still transmitted back to the external device (such as a server) by the interface device.

[0091] The control device is electrically connected to the chip. The control device is used to monitor the state of the chip. Specifically, the chip and the control device can be electrically connected via an SPI interface. The control device may include a single-chip microcomputer (MCU). In one or more embodiments, the chip may include multiple processing chips, multiple processing cores or multiple processing circuits, which can drive multiple loads. Therefore, the chip can be in different working states such as multi-load and light load. The control device can realize the regulation of the working state of multiple processing chips, multiple processing and / or multiple processing circuits in the chip.

[0092] In some embodiments, the present disclosure further discloses an electronic device or apparatus, which includes the above-mentioned board. Depending on different application scenarios, the electronic device or apparatus may include a data processing device, a robot, a computer, a printer, a scanner, a tablet computer, a smart terminal, a mobile phone, a driving recorder, a navigator, a sensor, a camera, a server, a cloud server, a camera, a video camera, a projector, a watch, a headset, a mobile storage, a wearable device, a vehicle, a household appliance, and / or a medical device. The vehicle includes an airplane, a ship, and / or a vehicle; the household appliance includes a television, an air conditioner, a microwave oven, a refrigerator, an electric rice cooker, a humidifier, a washing machine, an electric light, a gas stove, and a range hood; the medical device includes an MRI machine, an ultrasound machine, and / or an electrocardiograph.

[0093] It should be noted that for the aforementioned method embodiments, for simplicity of description, they are all expressed as a series of action combinations, but those skilled in the art should be aware that this disclosure is not limited by the order of the actions described, because according to this disclosure, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in this specification are all optional embodiments, and the actions and modules involved are not necessarily required for this disclosure.

[0094] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0095] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, and the indirect coupling or communication connection of devices or units can be electrical, optical, acoustic, magnetic or other forms.

[0096] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0097] In addition, the functional units in the various embodiments of the present disclosure may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software program modules.

[0098] If the integrated unit is implemented in the form of a software program module and sold or used as an independent product, it can be stored in a computer-readable memory. Based on this understanding, when the technical solution of the present disclosure can be embodied in the form of a software product (such as a computer-readable storage medium), the computer software product is stored in a memory, including a number of instructions for enabling a computer device (which can be a personal computer, a server or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present disclosure. The aforementioned memory includes: various media that can store program codes, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0099] In the above embodiments of the present disclosure, the description of each embodiment has its own emphasis. For parts not described in detail in a particular embodiment, please refer to the relevant description of other embodiments. The technical features of the above embodiments can be combined in any way. To keep the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0100] The foregoing content can be better understood in accordance with the following terms:

[0101] Clause 1. A computing device for processing multi-bit wide values, comprising:

[0102] an input circuit configured to receive the multi-bit width value and configuration information, wherein the configuration information includes at least width information of a first component and width information of a second component representing the multi-bit width value;

[0103] a first component calculation circuit configured to calculate the adjusted multi-bit bit-width value according to a scaling factor associated with the bit-width information of the second component to obtain a first component representing the multi-bit bit-width value;

[0104] a second component calculation circuit configured to perform calculation based on at least the adjusted multi-bit width value and the value of the first component to obtain a second component representing the multi-bit width value; and

[0105] An output circuit is configured to output at least one of the first component and the second component.

[0106] Clause 2. The computing device according to clause 1, further comprising a decision circuit and an adding circuit, wherein:

[0107] The determination circuit is configured to determine the size of the multi-bit width value and the designated data, and send the determination result to the addition circuit; and

[0108] The adding circuit is configured to perform an addition or subtraction operation on the multi-bit width value and a given constant based on the determination result to obtain the adjusted multi-bit width value.

[0109] Clause 3. The computing device according to clause 2, wherein the configuration information further includes sign information regarding whether the bit width information of the second component includes a sign bit, and the first component calculation circuit is configured to determine the scaling factor according to the sign information.

[0110] Clause 4. The computing device of clause 1, wherein the first component computing circuit comprises:

[0111] A scaling circuit and a rounding circuit, wherein the scaling circuit is configured to perform a shift operation on the adjusted multi-bit width value according to the scaling factor, and the rounding circuit is configured to perform a rounding operation on the multi-bit width value after the shift operation to obtain the first component.

[0112] Clause 5. The computing device according to clause 3, wherein the sign information indicates that the bit width information of the second component includes a sign bit, and the second component computing circuit is configured to:

[0113] determining an adjustment value according to the bit width information of the second component; and

[0114] Calculation is performed based on the adjusted multi-bit width value, the value of the first component, and the adjustment value to obtain the second component.

[0115] Item 6. A computing device according to Item 5, wherein the second component calculation circuit includes a subtraction circuit configured to subtract the value of the first component and the adjustment value from the adjusted multi-bit width value to obtain the second component.

[0116] Clause 7. The computing device according to clause 1, further comprising a type converter configured to convert input data into a data type that is the same as the multi-bit width value.

[0117] Clause 8. The computing device of clause 1, further comprising a selector configured to select at least one of the first component and the second component to the output circuit according to the configuration information.

[0118] Clause 9. A computing device according to any one of clauses 1-8, wherein the first component and the second component are used to represent rounded values ​​of the multi-bit wide value.

[0119] Clause 10. A computing device according to any one of clauses 1-8, wherein the configuration information also includes information on the number of components, and when the number of components is a positive integer greater than 2, the computing device repeatedly executes the first component calculation circuit and the second component calculation circuit according to the configuration information until the number of components is obtained.

[0120] Clause 11. An integrated circuit chip comprising the computing device according to any one of clauses 1-10.

[0121] Clause 12. An integrated circuit board comprising the computing device according to clause 11.

[0122] Clause 13. A method for processing multi-bit wide values ​​for use in neural network operations, comprising:

[0123] receiving the multi-bit width value and configuration information, wherein the configuration information includes at least width information of a first component and width information of a second component representing the multi-bit width value;

[0124] calculating the adjusted multi-bit width value according to a scaling factor associated with the bit width information of the second component to obtain a first component representing the multi-bit width value;

[0125] performing a calculation based on at least the adjusted multi-bit width value and the value of the first component to obtain a second component representing the multi-bit width value; and

[0126] At least one of the first component and the second component is output.

[0127] Clause 14. The method according to clause 13, further comprising:

[0128] Determining the size of the multi-bit width value and the specified data; and

[0129] Based on the determination result, the multi-bit width value is added to a given constant to obtain the adjusted multi-bit width value.

[0130] Clause 15. The method of clause 14, wherein the configuration information further includes sign information regarding whether the bit width information of the second component includes a sign bit, the method further comprising determining the scaling factor based on the sign information.

[0131] Clause 16. The method of clause 13, wherein in obtaining the first component representing the multi-bit wide value, the method comprises:

[0132] performing a shift operation on the adjusted multi-bit width value according to the scaling factor; and

[0133] The multi-bit width value after the shift operation is performed is subjected to a rounding operation to obtain the first component.

[0134] Clause 17. The method of clause 15, wherein the sign information indicates that the bit width information of the second component includes a sign bit, the method further comprising:

[0135] determining an adjustment value according to the bit width information of the second component; and

[0136] Calculation is performed based on the adjusted multi-bit width value, the value of the first component, and the adjustment value to obtain the second component.

[0137] Clause 18. The method according to clause 13, further comprising:

[0138] Convert the input data to the same data type as the multi-bit width value.

[0139] Clause 19. The method according to clause 13, further comprising:

[0140] At least one of the first component and the second component is selected for output according to the configuration information.

[0141] Clause 20. The method of any one of clauses 13-19, wherein the first component and the second component are used to represent rounded values ​​of the multi-bit wide value.

[0142] Clause 21. The method according to clause 13, wherein the configuration information further includes information on the number of components, and when the number of components is a positive integer greater than 2, the method further comprises:

[0143] determining, according to the configuration information, at least one of the first component and the second component as a next new multi-bit width value to be processed;

[0144] calculating the adjusted new multi-bit width value according to the scaling system associated with the width information of the second component of the new multi-bit width value in the configuration information to obtain a first component representing the new multi-bit width value;

[0145] performing a calculation based on the adjusted new multi-bit width value and the value of the first component of the new multi-bit width value to obtain a second component representing the new multi-bit width value; and

[0146] The above-mentioned determining step and calculating step are repeatedly performed until the components of the number of components are obtained.

[0147] Clause 22. A computing device for processing multi-bit wide values ​​for use in neural network operations, comprising:

[0148] processor;

[0149] A memory for storing program instructions, which, when executed by the at least one processor, causes the computing device to perform the method according to any one of clauses 13-21.

[0150] Item 23. A computer-readable storage medium having stored thereon program instructions for processing multi-bit width values ​​for neural network operations, wherein when the program instructions are executed by a processor, the method according to any one of items 13-21 is performed.

[0151] The above is a detailed introduction to the embodiments of the present disclosure. Specific examples are used herein to illustrate the principles and implementation methods of the present disclosure. The description of the above embodiments is only used to help understand the method and core ideas of the present disclosure. At the same time, for those skilled in the art, based on the ideas of the present disclosure, there may be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as a limitation on the present disclosure.

[0152] It should be understood that the terms "first," "second," "third," and "fourth," etc. in the claims, specification, and drawings of the present disclosure are used to distinguish different objects rather than to describe a specific order. The terms "include" and "comprising" used in the specification and claims of the present disclosure indicate the presence of the described features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof.

[0153] It should also be understood that the terminology used in this disclosure is for the purpose of describing specific embodiments only and is not intended to limit the disclosure. As used in this disclosure and the claims, the singular forms "a," "an," and "the" are intended to include the plural forms unless the context clearly indicates otherwise. It should be further understood that the term "and / or" as used in this disclosure and the claims refers to any and all possible combinations of one or more of the associated listed items, including and including these combinations.

[0154] As used in this specification and claims, the term "if" can be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "upon determination" or "in response to determining" or "upon detection of [described condition or event]" or "in response to detecting [described condition or event]," depending on the context.

[0155] The above is a detailed introduction to the embodiments of the present disclosure. Specific examples are used herein to illustrate the principles and implementation methods of the present disclosure. The description of the above embodiments is only used to help understand the method and core ideas of the present disclosure. At the same time, changes or modifications made by those skilled in the art based on the ideas of the present disclosure, on the specific implementation methods and application scope of the present disclosure, all fall within the scope of protection of the present disclosure. In summary, the contents of this specification should not be understood as limiting the present disclosure.

Claims

1. A computing device for processing multi-bit width values, comprising: an input circuit configured to receive the multi-bit width value and configuration information, wherein the configuration information includes at least width information of a first component and width information of a second component representing the multi-bit width value; a first component calculation circuit configured to calculate an adjusted multi-bit bit-width value according to a scaling factor associated with the bit-width information of the second component to obtain a first component representing the multi-bit bit-width value, the calculation device further comprising a determination circuit and an addition circuit, wherein the determination circuit is configured to determine a size between the multi-bit bit-width value and designated data and send a determination result to the addition circuit, and the addition circuit is configured to perform an addition or subtraction operation on the multi-bit bit-width value and a given constant based on the determination result to obtain the adjusted multi-bit bit-width value, wherein the configuration information further comprises sign information regarding whether the bit-width information of the second component includes a sign bit, and the first component calculation circuit is configured to determine the scaling factor according to the sign information; a second component calculation circuit configured to perform calculation based on at least the adjusted multi-bit width value and the value of the first component to obtain a second component representing the multi-bit width value; as well as An output circuit is configured to output at least one of the first component and the second component.

2. The computing device according to claim 1, wherein the first component computing circuit comprises: A scaling circuit and a rounding circuit, wherein the scaling circuit is configured to perform a shift operation on the adjusted multi-bit width value according to the scaling factor, and the rounding circuit is configured to perform a rounding operation on the multi-bit width value after the shift operation to obtain the first component.

3. The computing device according to claim 1 , wherein the sign information indicates that the bit width information of the second component includes a sign bit, and the second component computing circuit is configured to: determining an adjustment value according to the bit width information of the second component; and Calculation is performed based on the adjusted multi-bit width value, the value of the first component, and the adjustment value to obtain the second component. 4 . The computing device of claim 3 , wherein the second component calculation circuit comprises a subtraction circuit configured to subtract the value of the first component and the adjustment value from the adjusted multi-bit width value to obtain the second component. 5 . The computing device according to claim 1 , further comprising a type converter configured to convert input data into a data type that is the same as the multi-bit width value. 6 . The computing device according to claim 1 , further comprising a selector configured to select at least one of the first component and the second component to the output circuit according to the configuration information.

7. The computing device according to any one of claims 1 to 6, wherein the first component and the second component are used to represent rounding values ​​of the multi-bit width value.

8. A computing device according to any one of claims 1-6, wherein the configuration information also includes information on the number of components, and when the number of components is a positive integer greater than 2, the computing device repeatedly executes the first component calculation circuit and the second component calculation circuit according to the configuration information until the components of the number of components are obtained.

9. An integrated circuit chip comprising the computing device according to any one of claims 1 to 8.

10. An integrated circuit board comprising the integrated circuit chip according to claim 9.

11. A method for processing a multi-bit width value, comprising: receiving the multi-bit width value and configuration information, wherein the configuration information includes at least width information of a first component and width information of a second component representing the multi-bit width value; calculating the adjusted multi-bit bitwidth value according to a scaling factor associated with the bitwidth information of the second component to obtain a first component representing the multi-bit bitwidth value, wherein a size of the multi-bit bitwidth value and the specified data is determined; and based on the determination result, adding the multi-bit bitwidth value to a given constant to obtain the adjusted multi-bit bitwidth value, wherein the configuration information further includes sign information regarding whether the bitwidth information of the second component includes a sign bit, and the method further includes determining the scaling factor according to the sign information; performing a calculation based on at least the adjusted multi-bit width value and the value of the first component to obtain a second component representing the multi-bit width value; as well as At least one of the first component and the second component is output.

12. The method of claim 11 , wherein in obtaining the first component representing the multi-bit width value, the method comprises: performing a shift operation on the adjusted multi-bit width value according to the scaling factor; as well as The multi-bit width value after the shift operation is performed is subjected to a rounding operation to obtain the first component.

13. The method according to claim 11, wherein the sign information indicates that the bit width information of the second component includes a sign bit, the method further comprising: determining an adjustment value according to the bit width information of the second component; as well as Calculation is performed based on the adjusted multi-bit width value, the value of the first component, and the adjustment value to obtain the second component.

14. The method according to claim 11, further comprising: Convert the input data to the same data type as the multi-bit width value.

15. The method according to claim 11, further comprising: At least one of the first component and the second component is selected for output according to the configuration information.

16. The method according to any one of claims 11 to 15, wherein the first component and the second component are used to represent rounding values ​​of the multi-bit width value.

17. The method according to claim 11, wherein the configuration information further includes information on the number of components, and when the number of components is a positive integer greater than 2, the method further comprises: determining, according to the configuration information, at least one of the first component and the second component as a next new multi-bit width value to be processed; calculating the adjusted new multi-bit width value according to the scaling system associated with the width information of the second component of the new multi-bit width value in the configuration information to obtain a first component representing the new multi-bit width value; Calculating based on the adjusted new multi-bit width value and the value of the first component of the new multi-bit width value to obtain a second component representing the new multi-bit width value; as well as The above-mentioned determining step and calculating step are repeatedly performed until the components of the number of components are obtained.

18. A computing device for processing multi-bit width values, comprising: processor; A memory for storing program instructions, which, when executed by the at least one processor, causes the computing device to perform the method according to any one of claims 11 to 17.

19. A computer-readable storage medium having stored thereon program instructions for processing multi-bit width values ​​for neural network operations, wherein when the program instructions are executed by a processor, the method according to any one of claims 11 to 17 is executed.

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