Flexible bus protocol negotiation and enable sequence

Abstract

Systems, methods, and devices may involve a host device including a root complex, a link, and an interconnect protocol stack coupled to the bus link. The interconnect protocol stack may include multiplexing logic and physical layer logic, the multiplexing logic being used to select one of a Peripheral Component Interconnect Express (PCIe) upper layer mode or an accelerator link protocol upper layer mode for communicating over the link, and the physical layer logic being used to determine one or more low latency features associated with one or both of the PCIe upper layer mode or the accelerator link protocol upper layer mode.

Description

[0001] This application is a divisional application of the patent application with the same name with application number 201910271412.1 filed on April 4, 2019.

[0002] Citation to Related Applications

[0003] This application claims the benefit of U.S. Provisional Patent Application No. 62 / 667,324, filed May 4, 2018, the entire contents of which are incorporated herein by reference. Background Art

[0004] Computing systems typically include multiple interconnects to facilitate communication between system components (e.g., processors and memory). In addition, the interconnects may also be used to support plug-in devices, such as input / output (IO) devices and expansion cards. Furthermore, different market segments require different interconnect architectures to meet market demands and different interconnect connections. Non-limiting examples of typical interconnects may include Peripheral Component Interconnect Express (PCIe), Intra-Device Interconnect (IDI), and Ultra-path interconnect (UPI or UPI). BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 is a schematic diagram of a simplified block diagram of a system including a serial point-to-point interconnect for connecting I / O devices in a computer system according to one embodiment.

[0006] Figure 2 is a schematic diagram of a simplified block diagram of a layered protocol stack according to one embodiment.

[0007] Figure 3 is a schematic diagram of an embodiment of a transaction descriptor.

[0008] Figure 4 is a schematic diagram of an embodiment of a serial point-to-point link.

[0009] Figure 5 is a schematic diagram of a processing system including a connected accelerator according to an embodiment of the present disclosure.

[0010] Figure 6 is a schematic diagram of an example computing system according to an embodiment of the present disclosure.

[0011] Figure 7 is a schematic diagram of an example flexible bus stack according to an embodiment of the present disclosure.

[0012] Fig. 8A is a process flow diagram for determining one or more characteristics to enable use of PCIe alternate protocol negotiation according to an embodiment of the present disclosure.

[0013] Figure 8B is a diagram illustrating sub-states in an example link training state machine.

[0014] Fig. 9 is a block diagram of a processor that may have more than one core, may have an integrated memory controller, and may have integrated graphics, according to various embodiments.

[0015] Fig.10 A block diagram of a system according to one embodiment of the present disclosure is depicted.

[0016] Fig.11 A block diagram of a more specific first exemplary system according to an embodiment of the present disclosure is depicted.

[0017] Fig.12 A block diagram of a more specific second exemplary system 1300 is depicted according to an embodiment of the present disclosure.

[0018] Fig.13 A block diagram of a SoC according to an embodiment of the present disclosure is depicted.

[0019] Fig.14 is a block diagram of using a software instruction converter to convert binary instructions in a source instruction set into binary instructions in a target instruction set according to an embodiment of the disclosure. DETAILED DESCRIPTION

[0020] Many specific details are set forth in the following description, such as examples of specific types of processors and system configurations, specific hardware structures, specific architectures and microarchitecture details, specific register configurations, specific instruction types, specific system components, specific processor pipeline stages, specific interconnect layers, specific grouping / transaction configurations, specific transaction names, specific protocol exchanges, specific link widths, specific implementations and operations, etc., in order to provide a thorough understanding of the present disclosure. However, it may be apparent to those skilled in the art that these specific details are not necessarily required to practice the subject matter of the present disclosure. In other instances, detailed descriptions of the following known components or methods are avoided so as not to unnecessarily obscure the present disclosure: for example, specific and alternative processor architectures, specific logic circuits / codes for the described algorithms, specific firmware code, low-level interconnect operations, specific logic configurations, specific manufacturing techniques and materials, specific compiler implementations, specific algorithmic expressions in code form, specific power-down and gating techniques / logic, and other specific operational details of computer systems.

[0021] Although the following embodiments may be described with reference to energy conservation, energy efficiency, processing efficiency, etc. in a particular integrated circuit (e.g., in a computing platform or microprocessor), other embodiments are also applicable to other types of integrated circuits and logic devices. Similar techniques and teachings of the embodiments described herein may be applied to other types of circuits or semiconductor devices that may similarly benefit from these features. For example, the disclosed embodiments are not limited to server computer systems, desktop computer systems, laptop computers, or Ultrabooks. TM , and can also be used for other devices, such as handheld devices, smart phones, tablet computers, other thin notebook computers, system-on-chip (SOC) devices, and embedded applications. Some examples of handheld devices include cellular phones, Internet protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. Here, similar techniques for high-performance interconnects can be applied to enhance performance (or even save energy) in low-power interconnects. Embedded applications typically include microcontrollers, digital signal processors (DSPs), system-on-chips, network computers (NetPCs), set-top boxes, network centers, wide area network (WAN) switches, or any other system that can perform the functions and operations taught below. In addition, the apparatus, methods, and systems described herein are not limited to physical computing devices, but can also involve software optimization for energy conservation and efficiency. As can be apparent in the following description, it can be considered that the embodiments of the methods, apparatuses, and systems described herein (whether with reference to hardware, firmware, software, or a combination thereof) are essential for a "green technology" future that is balanced with performance considerations.

[0022] As computing systems evolve, the components therein become more complex. The complexity of the interconnect architecture used to couple and communicate between components has also increased to ensure that the bandwidth requirements for optimal component operation are met. In addition, different market segments require different aspects of the interconnect architecture to meet the corresponding market. For example, servers require higher performance, while the mobile ecosystem is sometimes able to sacrifice overall performance for energy conservation. However, the single purpose of most structures is to provide the highest possible performance and maximum energy conservation. Further, a variety of different interconnects can potentially benefit from the subject matter described in this article.

[0023] Peripheral Component Interconnect Express (PCI) (PCIe) interconnect architecture and Quick Path Interconnect (QPI) architecture and other examples (e.g., Ultrapath Interconnect (UPI)) can potentially be improved according to one or more principles described herein and other examples. For example, the main goal of PCIe is to enable components and devices from different vendors to interoperate in an open architecture, across multiple market segments; clients (desktop and mobile), servers (standard and enterprise), and embedded devices and communication devices. PCI Express is a high-performance general-purpose I / O interconnect that is defined for a variety of future computing and communication platforms. Some PCI attributes (e.g., its usage model, load-store architecture, and software interface) have been maintained through its revisions, and previous parallel bus implementations have been replaced by highly scalable, fully serial interfaces. The latest PCI Express versions utilize improvements in point-to-point interconnects, switch-based technologies, and packetized protocols to achieve new levels of performance and features. Some of the advanced features supported by PCI Express are power management, quality of service (QoS), hot-plug / hot-swap support, data integrity, and error handling. Although the primary discussion herein refers to a new high performance interconnect (HPI) architecture, aspects of the disclosure described herein may be applicable to other interconnect architectures, such as a PCIe-compliant architecture, a QPI-compliant architecture, a MIPI-compliant architecture, a high performance architecture, or other known interconnect architectures.

[0024] refer to Figure 1 , shows an embodiment of a structure consisting of point-to-point links interconnecting a set of components. System 100 includes a processor 105 and a system memory 110 coupled to a controller hub 115. Processor 105 may include any processing element, such as a microprocessor, a host processor, an embedded processor, a coprocessor, or other processor. Processor 105 is coupled to controller hub 115 via a front side bus (FSB) 106. In one embodiment, FSB 106 is a serial point-to-point interconnect as described below. In another embodiment, link 106 includes a serial differential interconnect architecture that conforms to different interconnect standards.

[0025] System memory 110 includes any memory device, such as random access memory (RAM), non-volatile (NV) memory, or other memory accessible to devices in system 100. System memory 110 is coupled to controller hub 115 via memory interface 116. Examples of memory interfaces include double data rate (DDR) memory interfaces, dual channel DDR memory interfaces, and dynamic RAM (DRAM) memory interfaces.

[0026] In one embodiment, controller hub 115 may include, for example, a root hub, root complex, or root controller in a PCIe interconnect hierarchy. Examples of controller hub 115 include chipsets, memory controller hubs (MCHs), north bridges, interconnect controller hubs (ICHs), south bridges, and root controllers / hubs. Often, the term chipset refers to two physically separate controller hubs, for example, a memory controller hub (MCH) coupled to an interconnect controller hub (ICH). Note that current systems often include an MCH integrated with processor 105, while controller 115 communicates with I / O devices in a manner similar to that described below. In some embodiments, peer-to-peer routing is optionally supported through root complex 115.

[0027] Here, controller hub 115 is coupled to switch / bridge 120 via serial link 119. Input / output modules 117 and 121 (also referred to as interfaces / ports 117 and 121) may include / implement a layered protocol stack to provide communication between controller hub 115 and switch 120. In one embodiment, multiple devices can be coupled to switch 120.

[0028] The switch / bridge 120 routes packets / messages from the device 125 upstream (i.e., toward the level of the root complex upward) to the controller hub 115, and from the processor 105 or the system memory 110 downstream (i.e., away from the level of the root controller downward) to the device 125. In one embodiment, the switch 120 is referred to as a logical component of multiple virtual PCI to PCI bridge devices. The device 125 includes any internal or external device or component to be coupled to the electronic system, for example, an I / O device, a network interface controller (NIC), an insert card, an audio processor, a network processor, a hard drive, a storage device, a CD / DVD ROM, a monitor, a printer, a mouse, a keyboard, a router, a portable storage device, a Firewire device, a universal serial bus (USB) device, a scanner, and other input / output devices. Often, in PCIe, terms such as devices are referred to as endpoints. Although not specifically shown, the device 125 may include a bridge (e.g., a PCIe to PCI / PCI-X bridge) to support legacy devices or other versions of devices, or interconnect structures supported by these devices.

[0029] The graphics accelerator 130 may also be coupled to the controller hub 115 via a serial link 132. In one embodiment, the graphics accelerator 130 is coupled to the MCH, which is coupled to the ICH. The switch 120, and therefore the I / O devices 125, are then coupled to the ICH. The I / O modules 131 and 118 are also used to implement a layered protocol stack to communicate between the graphics accelerator 130 and the controller hub 115. Similar to the MCH discussed above, the graphics controller or graphics accelerator 130 itself may be integrated into the processor 105.

[0030] Go to Figure 2 , shows an embodiment of a layered protocol stack. The layered protocol stack 200 may include any form of layered communication stack, such as a QPI stack, a PCIe stack, a next-generation high-performance computing interconnect (HPI) stack, or other layered stacks. In one embodiment, the protocol stack 200 may include a transaction layer 205, a link layer 210, and a physical layer 220. The interface (e.g., Figure 1 The interfaces 117, 118, 121, 122, 126 and 131 in the embodiment of the present invention can be represented as a communication protocol stack 200. The representation as a communication protocol stack can also be referred to as a module or interface that implements / includes the protocol stack.

[0031] Packets can be used to convey information between components. Packets can be formed in the transaction layer 205 and the data link layer 210 to carry information from a sending component to a receiving component. As the packets being sent flow through the other layers, the packets are extended with additional information for processing the packets at those layers. On the receiving side, the reverse process occurs, and the packet is transformed from its physical layer 220 representation to a data link layer 210 representation, and finally (for a transaction layer packet) to a form that can be processed by the transaction layer 205 of the receiving device.

[0032] In one embodiment, the transaction layer 205 may provide an interface between the processing core of the device and the interconnect architecture (e.g., the data link layer 210 and the physical layer 220). In this regard, the primary responsibilities of the transaction layer 205 may include the packaging and unpacking of packets (i.e., transaction layer packets or TLPs). The transaction layer 205 may also manage credit-based flow control for the TLPs. In some implementations, split transactions may be utilized, i.e., transactions in which requests and responses are separated in time, allowing the link to carry other traffic while the target device is collecting data for the response, as well as other examples.

[0033] Credit-based flow control can be used to implement virtual channels and networks using interconnect structures. In one example, a device can advertise the initial credit amount of each receive buffer in the transaction layer 205. An external device at the opposite end of the link (e.g., Figure 1The controller hub 115 in the example embodiment may count the number of credits consumed by each TLP. If the transaction does not exceed the credit limit, the transaction may be sent. Upon receiving a response, a certain amount of credit is restored. An example of the advantage of such a credit scheme is that as long as the credit limit is not encountered, the delay in the return of credits does not affect performance, as well as other potential advantages.

[0034] In one embodiment, the four transaction address spaces may include a configuration address space, a memory address space, an input / output address space, and a message address space. The memory space transaction includes one or more of a read request and a write request for transferring data to or from a memory mapped location. In one embodiment, the memory space transaction can use two different address formats, for example, a short address format (e.g., a 32-bit address) or a long address format (e.g., a 64-bit address). The configuration space transaction may be used to access the configuration space of various devices connected to the interconnect. Transactions for the configuration space may include read requests and write requests. Message space transactions (or simply messages) may also be defined to support in-band communication between interconnect agents. Therefore, in an example embodiment, the transaction layer 205 may package the packet header / payload 206.

[0035] Quick Reference Figure 3 , an example embodiment of a transaction layer packet descriptor is shown. In one embodiment, a transaction descriptor 300 may be a mechanism for carrying transaction information. In this regard, the transaction descriptor 300 supports identification of transactions in the system. Other potential uses include tracking modifications to default transaction ordering and association of transactions with channels. For example, the transaction descriptor 300 may include a global identifier field 302, an attribute field 304, and a channel identifier field 306. In the example shown, the global identifier field 302 is depicted as including a local transaction identifier field 308 and a source identifier field 310. In one embodiment, the global transaction identifier 302 is unique to all outstanding requests.

[0036] According to one implementation, the local transaction identifier field 308 is a field generated by the requesting agent and can be unique to all outstanding requests that are required to be completed for the requesting agent. In addition, in this example, the source identifier 310 uniquely identifies the requester agent within the interconnect hierarchy. Therefore, together with the source ID 310, the local transaction identifier field 308 provides a global identification of the transaction within the hierarchy domain.

[0037] Attribute field 304 specifies the characteristics and relationships of the transaction. In this regard, attribute field 304 is potentially used to provide additional information that allows modification of the default processing of the transaction. In one embodiment, attribute field 304 includes priority field 312, reserved field 314, sort field 316, and non-listening field 318. Here, priority subfield 312 can be modified by the initiator to assign a priority to the transaction. Reserved attribute field 314 is reserved for future use or vendor-defined use. Reserved attribute fields can be used to implement possible usage models that use priority or security attributes.

[0038] In this example, the sorting attribute field 316 is used to provide optional information that conveys the type of sorting that can modify the default sorting rules. According to an example implementation, a sorting attribute of "0" indicates that the default sorting rules are to be applied, wherein a sorting attribute of "1" indicates a relaxed sorting, wherein writes can be delivered in the same direction as writes, and read completions can be delivered in the same direction as writes. The snooping attribute field 318 is used to determine whether the transaction is snooped. As shown, the channel ID field 306 identifies the channel with which the transaction is associated.

[0039] Back to Figure 2 As discussed above, the link layer 210 (also referred to as the data link layer 210) can be used as an intermediate stage between the transaction layer 205 and the physical layer 220. In one embodiment, the responsibility of the data link layer 210 is to provide a reliable mechanism for exchanging transaction layer packets (TLPs) between two components on a link. One side of the data link layer 210 accepts the TLPs packaged by the transaction layer 205, applies a packet sequence identifier 211 (i.e., an identification number or packet number), calculates and applies an error detection code (i.e., CRC 212), and submits the modified TLP to the physical layer 220 for transmission across the physical layer to an external device.

[0040] In one example, the physical layer 220 includes a logic sub-block 221 and an electronic block 222 to physically send packets to an external device. Here, the logic sub-block 221 is responsible for the "digital" functions of the physical layer 220. In this regard, the logic sub-block may include a transmit portion for preparing outgoing information for transmission by the physical sub-block 222, and a receiver portion for identifying and preparing received information before passing it to the link layer 210.

[0041] Physical block 222 includes a transmitter and a receiver. The transmitter is provided with symbols by logic sub-block 221, and the transmitter serializes the symbols and sends them to an external device. The receiver is provided with serialized symbols from an external device, and the receiver converts the received signal into a bit stream. The bit stream is deserialized and provided to logic sub-block 221. In an example embodiment, an 8b / 10b transmission code is used, in which ten-bit symbols are sent / received. Here, special symbols are used to group packets into frames using frame 223. In addition, in one example, the receiver also provides a symbol clock recovered from the incoming serial stream.

[0042] As stated above, while the transaction layer 205, link layer 210, and physical layer 220 are discussed with reference to a specific embodiment of a protocol stack (e.g., a PCIe protocol stack), the layered protocol stack is not limited thereto. In fact, any layered protocol may be included / implemented and the features discussed herein applicable. As an example, a port / interface represented as a layered protocol may include: (1) a first layer for grouping packets, i.e., a transaction layer; a second layer for sequencing packets, i.e., a link layer; and a third layer for transmitting packets, i.e., a physical layer. As a specific example, a high performance interconnect layered protocol as described herein is used.

[0043] Next reference Figure 4 , an example embodiment of a serial point-to-point structure is shown. A serial point-to-point link may include any transmission path for transmitting serial data. In the embodiment shown, the link may include two low voltage differential drive signal pairs: a transmit pair 406 / 411 and a receive pair 412 / 407. Thus, device 405 includes transmit logic 406 for transmitting data to device 410 and receive logic 407 for receiving data from device 410. In other words, in some implementations of the link, two transmit paths (i.e., paths 416 and 417) and two receive paths (i.e., paths 418 and 419) are included.

[0044] A transmission path refers to any path for transmitting data, such as a transmission line, a copper line, an optical line, a wireless communication channel, an infrared communication link, or other communication path. A connection between two devices (e.g., device 405 and device 410) is called a link, such as link 415. A link can support one channel - each channel represents a set of differential signal pairs (one pair for transmission and one pair for reception). To expand bandwidth, a link can aggregate multiple channels represented by xN, where N is any supported link width, such as 1, 2, 4, 8, 12, 16, 32, 64, or wider.

[0045] A differential pair can refer to two transmission paths, e.g., lines 416 and 417, for transmitting differential signals. As an example, when line 416 switches from a low voltage level to a high voltage level (i.e., a rising edge), line 417 drives from a high logic level to a low logic level (i.e., a falling edge). Differential signals potentially exhibit better electrical characteristics, e.g., better signal integrity, i.e., cross-coupling, voltage overshoot / undershoot, ringing, and other example advantages. This allows for better timing windows, which enables faster transmission frequencies.

[0046] Accelerator Link (IAL) or other technologies (e.g., GenZ, CAPI, OpenCAPI specifications, CCIX, NVLink, etc.) define a generic memory interface that allows memory associated with discrete devices such as accelerators to be used as consistent memory. In many cases, discrete devices and associated memory can be connected cards or in a chassis separate from the (multiple) core processors. The result of introducing consistent memory associated with the device is that the device memory is not tightly coupled to the CPU or platform. Platform-specific firmware cannot be expected to know device details. For modularity and interoperability reasons, memory initialization responsibilities must be fairly divided between platform-specific firmware and device-specific firmware / software.

[0047] The present disclosure describes an extension to the existing Intel Accelerator Link (IAL) architecture. IAL uses a combination of three separate protocols called IAL.io, IAL.cache, and IAL.mem to implement IAL's bias-based consistency model (hereinafter referred to as the consistency bias model). The consistency bias model can promote high performance in accelerators while minimizing consistency overhead. The present disclosure provides mechanisms that allow accelerators to implement the consistency bias model using the IAL.io and IAL.mem protocols (with or without IAL.cache).

[0048] IAL.io is a PCIe-compatible input / output (IO) protocol used by IAL for functions such as discovery, configuration, initialization, interrupts, error handling, address translation services, etc. IAL.io is non-coherent in nature, supports variable payload sizes and follows PCIe ordering rules. The functionality of IAL.io is similar to the Intel On-Chip System-on-Ship Structure (IOSF). IOSF is a repackaged PCIe protocol for multiplexing, for discovery, register access, interrupts, etc.

[0049] IAL.mem is the I / O protocol used by the host to access data from device-attached memory. IAL.mem allows device-attached memory to be mapped into the system coherent address space. IAL.mem also has snoop and metadata semantics to manage the coherency of device-side caches. IAL.mem is similar to SMI3 for controlling memory flow.

[0050] IAL.cache is an I / O protocol used by devices to request cacheable data from host-attached memory. IAL.cache is non-posted and out-of-order, and supports cache line granularity payload sizes. IAL.cache is similar to the Intra-Die Interconnect (IDI) protocol for coherency requests and memory streaming.

[0051] This disclosure uses IAL attached memory (IAL.mem protocol) as an example implementation, but may also be extended to other technologies, such as those released by the GenZ Alliance or CAPI or OpenCAPI specifications, CCIX, NVLink, etc. IAL is built on top of PCIe and adds support for consistent memory attachment. However, in general, the systems, devices, and programs described herein may use other types of input / output buses that facilitate the attachment of consistent memory.

[0052] This disclosure describes a method that an accelerator can use to flip page bias from host to device bias through IAL.io. The method described herein retains many advanced capabilities of the IAL accelerator, but has a simpler device implementation. Both the host and the device can still obtain full bandwidth, consistent, and low-latency access to the accelerator-attached memory, and the device can still obtain consistent but non-cacheable access to the host-attached memory.

[0053] The methods described herein may also reduce security-related threats from the device because the device cannot send cacheable requests to the host-attached memory with IAL.cache.

[0054] Figure 5 is a schematic diagram of a processing system 500 including a connected accelerator according to an embodiment of the present disclosure. The processing system 500 may include a host device 501 and a connected device 530. The connected device 530 may be a discrete device connected across an IAL-based interconnect or connected through another similar interconnect. The connected device 530 may be integrated within the same chassis as the host device 501, or may be housed in a separate chassis.

[0055] The host device 501 may include a processor core 502 (labeled as CPU 502). The processor core 502 may include one or more hardware processors. The processor core 502 may be coupled to a memory module 505. The memory module 505 may include double data rate (DDR) interleaved memory, for example, dual in-line memory modules DIMM1 506 and DIMM2 508, but may also include more memory and / or other memory types. The host device 501 may include a memory controller 504 implemented in one or a combination of hardware, software or firmware. The memory controller 504 may include logic circuits for managing data flow to and from the host device 501 and the memory module 505.

[0056] The connected device 530 can be coupled to the host device 501 across an interconnect. As an example, the connected device 530 can include accelerators ACC1 532 and ACC2 542. ACC1 532 can include a memory controller MC1 534 capable of controlling a consistent memory ACC1_MEM 536. ACC2 542 can include a memory controller MC2 544 capable of controlling a consistent memory ACC2_MEM 546. The connected device 530 can include additional accelerators, memories, etc. ACC1_MEM 536 and ACC2_MEM 546 can be consistent memories used by the host processor; similarly, the memory module 505 can also be consistent memories. ACC1_MEM 536 and ACC2_MEM 546 can be or include host managed device memories (HDM).

[0057] The host device 501 may include a software module 520 for performing one or more memory initialization processes. The software module 520 may include an operating system (OS) 522, platform firmware (FW) 524, one or more OS drivers 526, and one or more EFI drivers 528. The software module 520 may include logic embodied on a non-transitory machine-readable medium, and may include instructions that, when executed, cause one or more software modules to initialize the consistent memories ACC1_MEM 536 and ACC2_MEM 546.

[0058] For example, the platform firmware 524 can determine the size of the consistent memory ACC1_MEM 536 and ACC2_MEM 546 and the overall characteristics of the memory in advance during boot-up through standard hardware registers or using a designated vendor-specific extended capability register (DVSEC). The platform firmware 524 maps the device memory ACC1_MEM 536 and ACC2_MEM 546 to the consistent address space. The device firmware or software 550 performs the device memory initialization and signals the platform firmware 524 and / or system software 520 (e.g., OS 522). The device firmware 550 then communicates the detailed memory characteristics to the platform firmware 524 and / or system software 520 (e.g., OS 522) via a software protocol.

[0059] Figure 6 An example of an operating environment 600 is shown that may represent various embodiments. Figure 6 The operating environment 600 depicted in FIG. 6 may include a device 602 operable to provide processing capabilities and / or memory capabilities. For example, the device 602 may be an accelerator or processor device communicatively coupled to a host processor 612 via an interconnect 650, which may be a single interconnect, a bus, a trace, etc. The device 602 and the host processor 612 may communicate via a link 650 to enable data and messages to be passed therebetween. In some embodiments, the link 650 may be operable to support multiple protocols and communication of data and messages via multiple interconnect protocols. For example, the link 650 may support various interconnect protocols, including but not limited to non-coherent interconnect protocols, coherent interconnect protocols, and memory interconnect protocols. Non-limiting examples of supported interconnect protocols may include PCI, PCle, USB, IDI, IOSF, SMI, SMI3, IAL.io, IAL.cache, and IAL.mem, etc. For example, the link 650 may support a coherent interconnect protocol (e.g., IDI), a memory interconnect protocol (e.g., SMI3), and a non-coherent interconnect protocol (e.g., IOSF).

[0060] In an embodiment, the device 602 may include an accelerator logic 604, which includes a circuit 605. In some instances, the accelerator logic 604 and the circuit 605 may provide processing power and memory capabilities. In some instances, the accelerator logic 604 and the circuit 605 may provide additional processing power in conjunction with the processing power provided by the host processor 612. Examples of the device 602 may include a producer-consumer device, a producer-consumer plus device, a software-assisted device memory device, an autonomous device storage device, and a large cache device, as previously discussed. The accelerator logic 604 and the circuit 605 may provide processing power and memory capabilities based on the device. For example, the accelerator logic 604 and the circuit 605 may communicate with the host processor 612 via the interface logic 606 and the circuit 607 using an interconnection, which uses, for example, a consistency interconnection protocol (e.g., IDI) for various functions such as consistency requests and memory streams. The interface logic 606 and the circuit 607 may determine the interconnection protocol based on the message and data used for communication. In another example, the accelerator logic 604 and circuit 605 may include consistency logic that includes or accesses bias mode information. The accelerator logic 604 including the consistency logic may communicate access bias mode information and related messages and data with the host processor 612 via the interface logic 606 and circuit 607 using a memory interconnect protocol (e.g., SMI3). The interface logic 606 and circuit 607 may determine to use a memory interconnect protocol based on the data and messages used for communication.

[0061] In some embodiments, the accelerator logic 604 and circuit 605 may include and process instructions for utilizing a non-coherent interconnect such as a structure-based protocol (e.g., IOSF) and / or a peripheral component interconnect express (PCIe) protocol. In various embodiments, the non-coherent interconnect protocol may be used for various functions, including but not limited to discovery, register access (e.g., registers of the device 602), configuration, initialization, interrupts, direct memory access, and / or address translation services (ATS). Note that the device 602 may include various accelerator logic 604 and circuit 605 to process information, and may be based on the type of device, for example, a producer-consumer device, a producer-consumer plus device, a software-assisted device memory device, an autonomous device memory device, and a large cache device. In addition, and as previously discussed, depending on the type of device, the device 602 including the interface logic 606, the circuit 607, the (multiple) protocol queues 609, and the multi-protocol multiplexer 608 may communicate according to one or more protocols, for example, a non-coherent protocol, a coherent protocol, and a memory interconnect protocol. The embodiments are not limited in this manner.

[0062] In various embodiments, host processor 612 may be similar to processor 105, such as Figure 1, and include similar or identical circuits to provide similar functionality. The host processor 612 may be operably coupled to the host memory 626 and may include consistency logic (or consistency and cache logic) 614, which may include a cache hierarchy and have a lower level cache (LLC). The consistency logic 614 may communicate with the interface logic 622 and one or more cores 618a-n including the circuit 623 using various interconnects. In some embodiments, the consistency logic 614 may communicate via one or more of a consistency interconnect protocol and a memory interconnect protocol. In some embodiments, the consistency LLC may include a combination of at least a portion of the host memory 626 and the accelerator memory 610. The embodiments are not limited in this manner.

[0063] The host processor 612 may include bus logic 616, which may be or may include PCIe logic. In various embodiments, the bus logic 616 may communicate over the interconnect using a non-uniform interconnect protocol (e.g., IOSF) and / or a peripheral component interconnect express (PCIe or PCI-E) protocol. In various embodiments, the host processor 612 may include multiple cores 618a-n, each with a cache. In some embodiments, the cores 618a-n may include Architecture (IA) core. Each of the cores 618a-n can communicate with the coherence logic 614 via an interconnect. In some embodiments, the interconnect coupling the cores 618a-n and the coherence and cache logic 614 can support a coherence interconnect protocol (e.g., IDI). In various embodiments, the host processor can include a device 620 operable to communicate with the bus logic 616 via the interconnect. In some embodiments, the device 620 can include an I / O device, such as a PCIe I / O device.

[0064] In an embodiment, the host processor 612 may include interface logic 622 and circuitry 623 to enable multi-protocol communications between components of the host processor 612 and the device 602. The interface logic 622 and circuitry 623 may dynamically process and enable communication of messages and data between the host processor 612 and the device 602 according to one or more interconnect protocols, such as a non-coherent interconnect protocol, a coherent interconnect protocol, and a memory interconnect protocol. In an embodiment, the interface logic 622 and circuitry 623 may support a single interconnect, link, or bus capable of dynamically processing data and messages according to multiple interconnect protocols.

[0065] In some embodiments, the interface logic 622 can be coupled to a multi-protocol multiplexer 624, which has one or more protocol queues 625 to send and receive messages and data with the device 602, which includes the multi-protocol multiplexer 608 and also has one or more protocol queues 609. The protocol queues 609 and 625 can be protocol specific. Therefore, each interconnection protocol can be associated with a specific protocol queue. The interface logic 622 and circuit 623 can process messages and data received from the device 602 and sent to the device 602 using the multi-protocol multiplexer 624. For example, when sending a message, the interface logic 622 and circuit 623 can process the message according to one of the interconnection protocols based on the message. The interface logic 622 and circuit 623 can send the message to the multi-protocol multiplexer 624 and the link controller. The multi-protocol multiplexer 624 or the arbitrator can store the message in the protocol queue 625, which can be protocol specific. Based on the availability of resources in the protocol-specific queues of the protocol queues 609 at the multi-protocol multiplexer 608 at the device 602, the multi-protocol multiplexer 624 and the link controller may determine when to send a message to the device 602. When a message is received, the multi-protocol multiplexer 624 may place the message in the protocol-specific queues of the queues 625 based on the message. The interface logic 622 and the circuit 623 may process the message according to one of the interconnect protocols.

[0066] In an embodiment, the interface logic 622 and circuitry 623 can dynamically process messages and data to and from the device 602. For example, the interface logic 622 and circuitry 623 can determine the message type of each message and determine which of a plurality of interconnect protocols to use to process each of the messages. Different interconnect protocols can be used to process the messages.

[0067] In an example, the interface logic 622 can detect a message to be communicated via the interconnect 650. In an embodiment, the message may have been generated by the core 618 or another I / O device 620 and is intended to be communicated to the device 602. The interface logic 622 can determine the message type of the message, for example, a non-coherent message type, a coherent message type, and a memory message type. In a specific example, the interface logic 622 can determine whether a message such as a request is an I / O request or a memory request for a coupled device based on a lookup in an address map. If the address associated with the message is mapped as an I / O request, the interface logic 622 can process the message using a non-coherent interconnect protocol and send the message as a non-coherent message to the link controller and the multi-protocol multiplexer 624 for communication to the coupled device. The multi-protocol multiplexer 624 can store the message in an interconnect-specific queue of the protocol queue 625 and cause the message to be sent to the device 602 when resources are available at the device 602. In another example, the interface logic 622 can determine based on a lookup in an address table that the address associated with the message indicates that the message is a memory request. The interface logic 622 can process the message using the memory interconnect protocol and send the message to the link controller and multi-protocol multiplexer 624 for communication to the coupled device 602. The multi-protocol multiplexer 624 can store the message in an interconnect protocol-specific queue of the protocol queue 625 and cause the message to be sent to the device 602 when resources are available at the device 602.

[0068] In another example, the interface logic 622 may determine that the message is a coherent message based on one or more cache coherence and memory access actions performed. More specifically, the host processor 612 may receive a coherence message or request sent by the coupled device 602. One or more of the cache coherence and memory access actions may be performed to process the message, and based on these actions; the interface logic 622 may determine that the message sent in response to the request may be a coherent message. The interface logic 622 may process the message according to the coherent interconnect protocol and send the coherent message to the link controller and the multi-protocol multiplexer 624 for sending to the coupled device 602. The multi-protocol multiplexer 624 may store the message in an interconnect protocol-specific queue of the queue 625 and cause the message to be sent to the device 602 when resources are available at the device 602. The embodiments are not limited in this manner.

[0069] In some embodiments, the interface logic 622 may determine the message type of the message based on an address associated with the message, an action caused by the message, information within the message (e.g., an identifier), a source of the message, a destination of the message, etc. The interface logic 622 may process the received message based on the determination and send the message to the appropriate component of the host processor 612 for further processing. The interface logic 622 may process the message to be sent to the device 602 based on the determination and send the message to a link controller (not shown) and a multi-protocol multiplexer 624 for further processing. The message type may be determined for a message sent from the host processor 612 or a message received by the host processor 612.

[0070] The current IAL architecture can implement IAL's bias-based consistency model (hereafter referred to as the "consistency bias model") using a combination of three separate protocols called IAL.io, IAL.cache, and IAL.mem. The consistency bias model can facilitate accelerators to achieve high performance while minimizing consistency overhead.

[0071] In an embodiment, the IAL architecture may support five types of accelerator models as defined below.

[0072]

[0073] Various embodiments herein relate to data transfer over a computer bus.

[0074] Note that flexible bus technologies (e.g. FlexBus technology) allows multiple protocols to be multiplexed onto a set of package-external pins using PCIe electrical. The flexible bus technology may include a system-on-chip design to facilitate on-chip communication between upstream devices and downstream devices. The flexible bus technology may include a dynamically configurable architecture. The architecture of the flexible bus technology may facilitate system-level topology adaptation (e.g., through dynamic bridge bypassing) and component-level topology adaptation (e.g., through component remapping).

[0075] For example, pins may be configured during discovery to support a first interconnect protocol type (e.g., a PCIe protocol) or a second interconnect protocol type (e.g., an accelerator link protocol, e.g., Accelerator Link (IAL) protocol (dynamic multiplexing of cache semantics, memory semantics, and load / store semantics). In addition, various latency optimizations can be enabled during discovery to meet the requirements of latency-sensitive applications that leverage cache semantics and memory semantics.

[0076] The present disclosure describes a flexible bus negotiation sequence using a PCIe alternate protocol negotiation mechanism. In an embodiment, during the negotiation, a decision may be made to enable an accelerator link protocol (e.g., IAL, GenZ, CAPI, OpenCAPI specification, CCIX, NVLink, etc.) or a PCIe protocol on a flexible bus link. Note that in the following description, reference will be repeatedly made to the flexible bus link, and FlexBus is one example type of such a flexible bus link. However, it should be understood that this is a non-limiting example and any equivalent technology should be understood to be within the scope of the present disclosure and the various flexible bus functions described.

[0077] In an embodiment, if the accelerator link protocol is selected, various delay optimizations may also be negotiated, including, for example, sync header suppression, skip ordered set suppression, drift buffer mode, and lane-to-lane de-skew bypass. In an embodiment, once the negotiation is complete, the upper protocol layers may be notified early in the link initialization process to provide lead time for any initialization required in the upper layers. However, according to various embodiments, the physical layer may enable the negotiated protocol and delay optimizations later in the link initialization process.

[0078] The present disclosure also describes a sequence for negotiating and enabling accelerator link protocols and features on a link that supports different interconnect protocols during initialization (e.g., an Intel Flexible Bus (or FlexBus) that supports IAL via PCIe electrical pins). The term "flexible bus link" is used below, but it should be understood that the present application contemplates other implementations of links and communication topologies that support interconnect protocols through a single set of electrical multiplexing. Generally, a flexible bus link can be a communication link that facilitates the transmission of data and control information between upstream devices and downstream devices, and can accommodate multiple interconnect protocol types, such as PCIe or IAL, through a single set of electrical pins. The flexible bus topology is described in more detail below.

[0079] Figure 7is a schematic diagram of an example flexible bus topology 700 according to an embodiment of the present disclosure. The flexible bus topology 700 illustrates at a high level various components for supporting multiple protocols across a link (e.g., a link conforming to a PCIe-based protocol). The flexible bus topology 700 may support an interconnect protocol 1 upper layer 702 or an interconnect protocol 2 upper layer 712. In the following example embodiment, the interconnect protocol 1 702 is a PCIe-based protocol; and the interconnect protocol 2 712 is an accelerator link protocol, such as IAL. The interconnect protocol 1 702 may include an interconnect protocol 1 transaction layer 704 and an interconnect protocol 1 link layer 706. The interconnect protocol 2 712 may include an interconnect protocol 2 transaction layer 714 and an interconnect protocol 2 link layer 720. The interconnect protocol 2 transaction layer 714 may include an input / output (I / O) transaction layer 716 (e.g., an I / O transaction layer for processing an IAL.io protocol) and a cache and memory transaction layer 718 (e.g., those for processing IAL.cache and IAL.mem transaction layer protocols). The interconnect protocol 2 link layer 720 may include an input / output (I / O) link layer 722 (e.g., an I / O link layer for processing the IAL.io protocol) and a cache and memory link layer 724 (e.g., those link layers for processing the IAL.cache and IAL.mem link layer protocols).

[0080] The flexible bus topology 700 may include a structure 730 to support the use of different interconnect protocols across the link 750. The structure 730 includes multiplexing (MUX) logic (static multiplexing logic 732 and interconnect protocol 2 MUX logic 734) and physical layer logic 740. During link initialization, the static multiplexing logic 732 can be configured to select a PCIe upper layer (e.g., interconnect protocol 1 upper layer 702) or an accelerator link protocol upper layer (e.g., interconnect protocol 2 upper layer 712) to communicate over the link 750. For example, if IAL mode is negotiated, the MUX 734 (e.g., IAL MUX) can be additionally configured to enable only a single protocol such as IAL.io, or to enable multiple protocols, such as IAL.io dynamically multiplexed with, for example, IAL.cache or IAL.mem or both (other configurations are contemplated). Finally, also during link initialization, a logic sub-block 744 of the physical layer logic 742 can be configured for PCIe mode or IAL mode. If IAL mode is enabled, any negotiated IAL delay optimization can also be enabled. The present disclosure describes a sequence to be implemented by the physical layer logic 742 for negotiating which IAL protocols and latency optimization features to enable using the PCIe Alternate Protocol Negotiation mechanism, and for subsequently notifying upper layers so that the appropriate logic can be activated in the flexible bus topology 700, and for enabling the appropriate logic in the logic sub-blocks 744 and (PCIe) electrical 744 within the physical layer logic 742. In general, the fabric 730 allows a host system to multiplex multiple protocols (e.g., Interconnect Protocol 1 or Interconnect Protocol 2) onto a set of pins using electrical associated with a single interconnect protocol (e.g., PCIe).

[0081] Note that the PCIe 5.0 specification defines a modified training sequence 1 / training sequence 2 (TS1 / TS2) ordered set to enable alternate protocol negotiation, allocating vendor-defined bits that can be used for vendor-defined alternate protocol negotiation. Tables 1 and 2 provided below describe how the vendor-defined bits of the modified TS1 / TS2 ordered set are defined for flexible bus negotiation according to various embodiments.

[0082] Table 1. Modified TS1 / TS2 ordered set usage for protocol mode negotiation

[0083]

[0084]

[0085]

[0086] Table 2. Additional information of modified TS1 / TS2 ordered sets

[0087]

[0088] In an embodiment, the modified TS1 / TS2 ordered sets may be used, for example, to negotiate which protocols (e.g., IAL protocol) should be enabled (e.g., IAL.io, IAL.mem, and IAL.cache) and to negotiate which low-latency features (e.g., IAL low-latency features) should be enabled (e.g., synchronization header suppression, SKP ordered set suppression, and drift buffer mode).

[0089] Fig. 8A 800 is a process flow chart for determining one or more features to enable negotiation using PCIe alternate protocol according to an embodiment of the present disclosure. Initially, the root complex may perform a two-phase alternate protocol negotiation (802) during configuration using a modified TS1 / TS2 ordered set while training at 2.5GT / s. In an embodiment, in accordance with the PCIe 5.0 specification, the negotiation may include a two-phase process that may occur at Configuration.Lanenum.Wait, Configuration.Lanenum.Accept, and Configuration.Complete before entering L0 at Gen1 speed:

[0090] Phase 1: The root complex sends a stream of modified TS1 ordered sets advertising its flexible bus capabilities; the endpoint device responds by sending a stream of modified TS1 ordered sets indicating which flexible bus capabilities the endpoint device wishes to enable (any retimer may communicate its capabilities by modifying the relevant bits in the modified TS1 ordered sets sent by the endpoint). This exchange occurs during Config.LaneNumber.Wait and / or Config.LaneNumber.Accept as per the PCIe 5.0 specification. At the end of this phase, the root complex has enough information to make a final choice about which capabilities to enable. Table 3 provided below specifies the rules used to resolve which low latency features to enable.

[0091] Table 3 - Rules for enabling the IAL low latency feature

[0092]

[0093] Phase 2: The root complex sends a stream of modified TS2 ordered sets to the endpoint device to indicate whether the link should operate in PCIe mode or IAL mode; for IAL mode, also specify which IAL protocols to enable and which low latency optimizations to enable. The endpoint acknowledges the enable request by sending a modified TS2 ordered set with the same flexible bus enable bit set. In an embodiment, this exchange may occur during Configuration.Complete per the PCIe 5.0 specification.

[0094] In an embodiment, the following sequence may be implemented by the flexible bus physical layer logic sub-block to negotiate the flexible bus feature and then enable the flexible bus feature:

[0095] The flexible bus physical layer logic sub-block may determine which protocol to use (IAL.io, IAL.cache, IAL.mem, PCIe, etc.) based on the modified TS2 ordered set (with the flexible bus enable bit set) received by the root complex from the endpoint device (804).

[0096] The flexible bus physical layer logic sub-block may determine the low latency features of the endpoint device (806). Examples of low latency features include drift buffering, sync header suppression, skip (SKP) ordered set (OS) suppression, etc. The flexible bus physical layer logic sub-block may determine if there are any retimer(s) and if the retimer(s) support bypass paths and any low latency features. If so, these features will be enabled after training to top speed; the logic PHY in the CPU will send CTRL SKP OS with the appropriate bits set after training to top speed to instruct the retimer to enable these features the next time it enters Recovery.Speed.

[0097] The Flexible Bus Physical Layer Logic sub-block can train the link to L0 at 2.5GT / s and notify the upper layer of the protocol decision (808). This notification allows the static multiplexing logic and IAL ARB / MUX logic to be configured and the appropriate upper layer to be properly activated and initialized when the link is initialized (810).

[0098] The flexible bus physical layer logic sub-block may train and equalize the link at a higher speed (812). After training to L0 at 2.5GT / s, the logical physical layer (PHY) reverts to sending regular TS1 / TS2 OS instead of modified TS1 / TS2 OS because the alternate protocol negotiation has been completed. The higher speed training may also include training the link to L0 at the highest speed.

[0099] The Flexible Bus Physical Layer Logic sub-block may send a control SKP OS with the appropriate bits set indicating that any retimers should enable any low latency features (including bypass paths) agreed upon in recovery.speed (814).

[0100] The Flexible Bus Physical Layer Logic sub-block may cause the speed change (rate remains the same) to force entry into Recovery.Speed ​​(816). Upon entry into Recovery.Speed, the retimer(s) enable bypass paths and low latency features if agreed upon during the Alternate Protocol negotiation and if the SKP OS control in step 4 so indicates. Upon entry into Recovery.Speed, the Flexible Bus Logic PHY enables any low latency features (e.g., wander buffering, sync header suppression, and SKP OS suppression) agreed upon during the Alternate Protocol negotiation (818).

[0101] The flexible bus physical layer logic sub-block may enable a de-skew bypass determination to be made during recovery after recovery.speed (820). If met, the de-skew bypass path is activated upon exit from recovery. De-skew bypass is an unnegotiated low latency optimization; it is determined locally by the flexible bus logic sub-block.

[0102] Figure 8B is a diagram illustrating sub-states in an example link training state machine. In one example, the PCIe physical layer can be used to support a variety of different protocols. Therefore, specific training states in the PCIe LTSSM can be used to negotiate protocols between devices on the link. As noted above, protocol determination may occur even before the link is trained to an active state (e.g., L0) at the lowest supported data rate (e.g., PCIe Gen 1 data rate). In one example, the PCIe configuration state can be used. The PCIe LTSSM can be used to negotiate protocols using modified PCIe training sets (e.g., TS1 and TS2) after link width negotiation and in parallel (at least in part) with the lane numbering performed during the configuration state.

[0103] For example, Figure 8BAs shown, a schematic diagram 850 is shown, which shows the sub-states of the PCIe configuration state. In this example, a configuration. link width. start (Configuration.Linkwidth.Start) substate 852 and a configuration. link width. accept (Configuration.Linkwidth.Accept) substate 854 can be provided, in which the link width is configured. These substates can involve sending training sequences, as is typically implemented during PCIe link training. When configuring the link width, additional substates (e.g., 856, 858, 860, etc.) can be provided. One or more of these configuration substates can be used to enable multi-protocol negotiation. For example, when transitioning to one of the configuration substates (e.g., 856, 858, 860) after configuring the link width, an enhanced or modified training sequence can be introduced, in which fields or symbols are configured to convey protocol determination information. The physical layer logic of each device in the device can process the received information to determine the supported protocols of the participating devices before the configuration state ends (e.g., before transitioning from the configuration. completed substate 860), as well as other examples. This example may additionally allow such protocol negotiation to be facilitated in a backward compatible manner so that legacy devices or other devices that do not support such functionality may be identified and communications adapted to the functionality of the other devices, among other examples.

[0104] Fig. 9 is a block diagram of a processor 900 that may have more than one core, may have an integrated memory controller, and may have integrated graphics, according to various embodiments. Fig. 9 The solid line box in the figure shows a processor 900 having a single core 902A, a system agent 910, and a set of one or more bus controller units 916; while the optional addition of the dashed line box shows an alternative processor 900 having multiple cores 902A-N, a set of one or more integrated memory controller units 914 in the system agent unit 910, and dedicated logic 908.

[0105] Thus, different implementations of processor 900 may include: 1) a CPU, where the dedicated logic 908 is integrated graphics and / or scientific (throughput) logic (which may include one or more cores), and cores 902A-N are one or more general-purpose cores (e.g., general-purpose in-order cores, general-purpose out-of-order cores, or a combination of both); 2) a coprocessor, where cores 902A-N are a large number of dedicated cores intended primarily for graphics and / or scientific (throughput); 3) a coprocessor, where cores 902A-N are a large number of general-purpose in-order cores. Thus, processor 900 may be a general-purpose processor, a coprocessor, or a dedicated processor, such as a network or communication processor, a compression and / or decompression engine, a graphics processor, a GPGPU (general-purpose graphics processing unit), a high-throughput many integrated core (MIC) coprocessor (e.g., including 30 or more cores), an embedded processor, or other fixed logic or configurable logic that performs logic operations. The processor may be implemented on one or more chips. Processor 900 may be part of one or more substrates using any of a variety of process technologies (e.g., BiCMOS, CMOS, or NMOS), and / or may be implemented on one or more substrates using any of a variety of process technologies.

[0106] In various embodiments, the processor may include any number of processing elements, which may be symmetric or asymmetric. In one embodiment, a processing element refers to hardware or logic that supports software threads. Examples of hardware processing elements include: thread units, thread slots, threads, processing units, contexts, context units, logical processors, hardware threads, cores and / or any other element that can maintain the state of a processor (e.g., execution state or architecture state). In other words, in one embodiment, a processing element refers to any hardware that can be independently associated with a code (e.g., a software thread, an operating system, an application, or other code). A physical processor (or processor socket) typically refers to an integrated circuit, which potentially includes any number of other processing elements, e.g., cores or hardware threads.

[0107] A core may refer to logic located on an integrated circuit capable of maintaining an independent architectural state, wherein each independently maintained architectural state is associated with at least some dedicated execution resources. A hardware thread may refer to any logic located on an integrated circuit capable of maintaining an independent architectural state, wherein the independently maintained architectural states share access to execution resources. As can be seen, the boundaries between the nomenclature of hardware threads and cores overlap when certain resources are shared and other resources are dedicated to an architectural state. Often, however, an operating system treats a core and a hardware thread as separate logical processors, wherein the operating system can schedule operations on each logical processor separately.

[0108] The memory hierarchy includes one or more levels of cache within the core, a set or one or more shared cache units 906, and external memory (not shown) coupled to the set of integrated memory controller units 914. The set of shared cache units 906 may include one or more intermediate level caches, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, a last level cache (LLC), and / or combinations thereof. While in one embodiment, a ring-based interconnect unit 912 interconnects dedicated logic (e.g., integrated graphics logic) 908, the set of shared cache units 906, and the system agent unit 910 / (multiple) integrated memory controller units 914, alternative embodiments may interconnect these units using any number of well-known techniques. In one embodiment, coherency is maintained between the one or more cache units 906 and the cores 902A-N.

[0109] In some embodiments, one or more of the cores 902A-N can be multithreaded. System agent 910 includes those components that coordinate and operate cores 902A-N. System agent unit 910 may include, for example, a power control unit (PCU) and a display unit. The PCU may be or include logic and components required to regulate the power state of cores 902A-N and dedicated logic 908. The display unit is used to drive one or more externally connected displays.

[0110] Cores 902A-N may be homogeneous or heterogeneous with respect to the architectural instruction set; that is, two or more of cores 902A-N may be capable of executing the same instruction set, while other cores may be capable of executing only a subset of the instruction set or a different instruction set.

[0111] Figure 10-14 is a block diagram of an exemplary computer architecture. Other system designs and configurations known in the art for laptop computers, desktop computers, handheld PCs, personal digital assistants, engineering workstations, servers, network devices, network centers, switches, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, microcontrollers, cellular phones, portable media players, handheld devices, and various other electronic devices are also suitable for performing the methods described in the present disclosure. In general, various systems or electronic devices that can contain processors and / or other execution logic as disclosed herein are generally suitable.

[0112] Fig.10A block diagram of a system 1000 is depicted in accordance with one embodiment of the present disclosure. The system 1000 may include one or more processors 1010, 1015 coupled to a controller hub 1020. In one embodiment, the controller hub 1020 includes a graphics memory controller hub (GMCH) 1090 and an input / output hub (IOH) 1050 (which may be on separate chips or on the same chip); the GMCH 1090 includes a memory controller and a graphics controller coupled to a memory 1040 and a coprocessor 1045; the IOH 1050 couples an input / output (I / O) device 1060 to the GMCH 1090. Alternatively, one or both of the memory controller and the graphics controller are integrated within the processor (as described herein), the memory 1040 and the coprocessor 1045 are directly coupled to the processor 1010, and the controller hub 1020 is a single chip including the IOH 1050.

[0113] The optional nature of the additional processor 1015 is Fig.10 Each processor 1010 , 1015 may include one or more of the processing cores described herein and may be a version of processor 900 .

[0114] The memory 1040 may be, for example, a dynamic random access memory (DRAM), a phase change memory (PCM), other suitable memory, or any combination thereof. The memory 1040 may store any suitable data, such as data used by the processors 1010, 1015 to provide the functionality of the computer system 1000. For example, data associated with an executed program or a file accessed by the processors 1010, 1015 may be stored in the memory 1040. In various embodiments, the memory 1040 may store data and / or instruction sequences used or executed by the processors 1010, 1015.

[0115] In at least one embodiment, the controller hub 1020 communicates with the processor(s) 1010, 1015 via a multi-drop bus such as a front side bus (FSB), a point-to-point interface such as a Quick Path Interconnect (QPI), or similar connection 1095.

[0116] In one embodiment, the coprocessor 1045 is a special purpose processor, such as a high throughput MIC processor, a network or communication processor, a compression and / or decompression engine, a graphics processor, a GPGPU, an embedded processor, etc. In one embodiment, the controller hub 1020 may include an integrated graphics accelerator.

[0117] There may be various differences between the physical resources 1010, 1015 in terms of a range of metrics of advantage including architectural characteristics, microarchitectural characteristics, thermal characteristics, power consumption characteristics, and the like.

[0118] In one embodiment, processor 1010 executes instructions that control general types of data processing operations. Embedded within the instructions may be coprocessor instructions. Processor 1010 recognizes these coprocessor instructions as being of a type that should be executed by an attached coprocessor 1045. Therefore, processor 1010 issues these coprocessor instructions (or control signals representing coprocessor instructions) to coprocessor 1045 on a coprocessor bus or other interconnect. Coprocessor(s) 1045 accept and execute the received coprocessor instructions.

[0119] Fig.11 1 depicts a block diagram of a more specific first exemplary system 1100 according to an embodiment of the present disclosure. Fig.11 As shown, multiprocessor system 1100 is a point-to-point interconnect system and includes a first processor 1170 and a second processor 1180 coupled via a point-to-point interconnect 1150. Each of processors 1170 and 1180 may be a version of a processor. In one embodiment of the disclosure, processors 1170 and 1180 are processors 1110 and 1115, respectively, and coprocessor 1138 is coprocessor 1145. In another embodiment, processors 1170 and 1180 are processors 1110 and coprocessor 1145, respectively.

[0120] Processors 1170 and 1180 are shown to include integrated memory controller (IMC) units 1172 and 1182, respectively. Processor 1170 also includes point-to-point (PP) interfaces 1176 and 1178 as part of its bus controller unit; similarly, second processor 1180 includes PP interfaces 1186 and 1188. Processors 1170, 1180 can exchange information via point-to-point (PP) interface 1150 using PP interface circuits 1178, 1188. Fig.11 As shown, IMCs 1172 and 1182 couple the processors to respective memories, namely, memory 1132 and memory 1134, which may be portions of main memory locally attached to the respective processors.

[0121] Processors 1170, 1180 may each exchange information with chipset 1190 via respective PP interfaces 1152, 1154 using point-to-point interface circuits 1176, 1194, 1186, 1198. Chipset 1190 may optionally exchange information with coprocessor 1138 via high performance interface 1139. In one embodiment, coprocessor 1138 is a special purpose processor, such as a high throughput MIC processor, a network or communication processor, a compression and / or decompression engine, a graphics processor, a GPGPU, an embedded processor, etc.

[0122] A shared cache (not shown) may be included in either processor or external to both processors but connected to the processors via the PP interconnect so that if either or both processors are placed in a low power mode, the processors' local cache information may be stored in the shared cache.

[0123] Chipset 1190 may be coupled to first bus 1116 via interface 1196. In one embodiment, first bus 1116 may be a peripheral component interconnect (PCI) bus, or a bus such as a PCI Express bus or another third generation I / O interconnect bus, but the scope of the present disclosure is not limited in this regard.

[0124] like Fig.11 As shown, various I / O devices 1114 may be coupled to the first bus 1116 along with a bus bridge 1118 which couples the first bus 1116 to a second bus 1120. In one embodiment, one or more additional processors 1115 such as a coprocessor, a high throughput MIC processor, a GPGPU, an accelerator (e.g., a graphics accelerator or a digital signal processing (DSP) unit), a field programmable gate array, or any other processor are coupled to the first bus 1116. In one embodiment, the second bus 1120 may be a low pin count (LPC) bus. In one embodiment, various devices may be coupled to the second bus 1120 including, for example, a keyboard and / or mouse 1122, communication devices 1127, and a storage unit 1128 such as a disk drive or other mass storage device which may include instructions / code and data 1130. Additionally, an audio I / O 1124 may be coupled to the second bus 1120. Note that the present disclosure contemplates other architectures. For example, instead of Fig.11 Instead of a point-to-point architecture, the system may implement a multi-point bus or other such architecture.

[0125] Fig.12 A block diagram of a more specific second exemplary system 1200 is depicted according to an embodiment of the present disclosure. Fig.11 and Fig.12 Like elements in FIG. 1 have like reference numerals, and Fig.12Omitted Fig.11 to avoid blurring certain aspects of Fig.12 other aspects.

[0126] Fig.12 It is shown that processors 1270, 1280 may include integrated memory and I / O control logic ("CL") 1272 and 1282, respectively. Thus, CL 1272, 1282 includes an integrated memory controller unit and includes I / O control logic. Fig.12 It is shown that not only the memory 1232, 1234 is coupled to the CL 1272, 1282, but also the I / O device 1214 is coupled to the control logic 1272, 1282. The legacy I / O device 1215 is coupled to the chipset 1290.

[0127] Fig.13 A block diagram of a SoC 1300 according to an embodiment of the present disclosure is depicted. In addition, dashed boxes are optional features on more advanced SoCs. Fig.13 , interconnect unit(s) 1302 are coupled to: application processor 1310, which includes a set of one or more cores 1004A-N and (multiple) shared cache units 1006; system agent unit 1010; bus controller unit(s) 1016; integrated memory controller unit(s) 1014; a set or one or more coprocessors 1320, which may include integrated graphics logic, image processor, audio processor, and video processor; static random access memory (SRAM) unit 1330; direct memory access (DMA) unit 1332; and display unit 1340, which is used to couple to one or more external displays. In one embodiment, coprocessor(s) 1320 include special purpose processors, such as network or communication processors, compression and / or decompression engines, GPGPUs, high throughput MIC processors, embedded processors, etc.

[0128] In some cases, the instruction converter can be used to convert instructions from a source instruction set to a target instruction set. For example, the instruction converter can convert (e.g., using static binary conversion, including dynamic binary conversion of dynamic compilation), deform, simulate or otherwise convert instructions to one or more other instructions to be processed by the core. The instruction converter can be implemented in software, hardware, firmware or a combination thereof. The instruction converter can be on the processor, outside the processor, or partly on the processor and partly outside the processor.

[0129] Fig.141 is a block diagram of a software instruction converter that converts binary instructions in a source instruction set into binary instructions in a target instruction set using a software instruction converter according to a comparison of an embodiment of the disclosure. In the illustrated embodiment, the instruction converter is a software instruction converter, but alternatively, the instruction converter can be implemented in software, firmware, hardware, or various combinations thereof. Fig.14 It is shown that a program in a high-level language 1402 can be compiled using an x86 compiler 1404 to generate x86 binary code 1406 that can be natively executed by a processor 1416 having at least one x86 instruction set core. The processor 1416 having at least one x86 instruction set core represents any processor that is capable of performing substantially the same functions as an Intel processor having at least one x86 instruction set core by compatibly executing or otherwise processing (1) a substantial portion of the instruction set of an Intel x86 instruction set core or (2) an object code version of an application or other software targeted to run on an Intel processor having at least one x86 instruction set core so as to achieve substantially the same results as an Intel processor having at least one x86 instruction set core. The x86 compiler 1404 represents a compiler that is operable to generate x86 binary code 1406 (e.g., object code) that can be executed on a processor 1416 having at least one x86 instruction set core with or without additional link processing. Similarly, Fig.14 It is shown that a program in a high-level language 1402 can be compiled using an alternative instruction set compiler 1408 to generate an alternative instruction set binary code 1410 that can be executed natively by a processor 1414 that does not have at least one x86 instruction set core (e.g., a processor having a core that executes the MIPS instruction set of MFS Technologies (Sunnyvale, CA) and / or executes the ARM instruction set of ARM Holdings (Sunnyvale, CA)). An instruction converter 1412 is used to convert the x86 binary code 1406 into code that can be executed natively by a processor 1414 that does not have an x86 instruction set core. The converted code is unlikely to be the same as the alternative instruction set binary code 1410 because an instruction converter that can do this is difficult to implement; however, the converted code will perform general operations and be composed of instructions from the alternative instruction set. Therefore, the instruction converter 1412 represents software, firmware, hardware, or a combination thereof that allows a processor or other electronic device that does not have an x86 instruction set processor or core to execute the x86 binary code 1406 through simulation, emulation, or any other process.

[0130] A design can go through various stages from creation to simulation to manufacturing. The data representing the design can represent the design in a variety of ways. First, as useful in simulation, a hardware description language (HDL) or another functional description language can be used to represent the hardware. In addition, a circuit level model with logic and / or transistor gates can be generated at certain stages of the design process. In addition, most designs reach a data level representing the physical placement of various devices in the hardware model at some stage. In the case of using conventional semiconductor manufacturing technology, the data representing the hardware model can be data specifying the presence or absence of various features on different mask layers of a mask used to produce an integrated circuit. In some implementations, such data can be stored in a database file format such as a Graphic Data System II (GDS II), an Open Artwork System Interchange Standard (OASIS), or a similar format.

[0131] In some implementations, software-based hardware models and HDL and other functional description language objects may include register transfer language (RTL) files and other examples. Such objects may be machine-parseable, so that design tools may accept HDL objects (or models), parse HDL objects for the properties of the described hardware, and determine physical circuits and / or on-chip layouts based on the objects. The output of the design tool may be used to manufacture physical devices. For example, the design tool may determine the configuration of various hardware and / or firmware elements based on the HDL object, such as bus width, registers (including size and type), memory blocks, physical link paths, structural topology, and other properties of the system that is implemented to implement the modeling in the HDL object. The design tool may include tools for determining the topology and structural configuration of systems on chip (SoC) and other hardware devices. In some instances, HDL objects may be used as the basis for developing models and design files that can be used by manufacturing equipment to manufacture the described hardware. In fact, the HDL object itself may be provided as input to the manufacturing system software to manufacture the described hardware.

[0132] In any representation of a design, data representing the design may be stored in any form of machine-readable medium. A memory such as a disk or a magnetic or optical storage device may be a machine-readable medium for storing information transmitted via light or electrical waves that are modulated or otherwise generated to transmit such information. When an electrical carrier wave indicating or carrying a code or design is transmitted, a new copy is made insofar as duplication, buffering, or retransmission of the electrical signal is performed. Thus, a communications provider or network provider may store an item (e.g., information encoded into a carrier wave embodying the techniques of an embodiment of the present disclosure) at least temporarily on a tangible machine-readable medium.

[0133] In various embodiments, a medium storing a representation of a design may be provided to a manufacturing system (e.g., a semiconductor manufacturing system capable of manufacturing integrated circuits and / or related components). The design representation may instruct the system to manufacture a device capable of performing any combination of the functions described above. For example, the design representation may instruct the system regarding which components to manufacture, how the components should be coupled together, where the components should be placed on the device, and / or regarding other suitable specifications related to the device to be manufactured.

[0134] Thus, one or more aspects of at least one embodiment may be implemented by representative instructions stored on a machine-readable medium, which represent various logic within a processor, which when read by a machine causes the machine to fabricate logic for performing the techniques described herein. Such representations, often referred to as "IP cores," may be stored on a non-transitory, tangible machine-readable medium and provided to various customers or manufacturing facilities to load into manufacturing machines that fabricate the logic or processor.

[0135] The embodiments of the mechanisms disclosed herein may be implemented in hardware, software, firmware, or a combination of these implementation methods. The embodiments of the disclosure may be implemented as a computer program or program code executed on a programmable system, the programmable system comprising at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0136] Such as Fig.11 Program codes such as code 1130 shown in can be applied to input instructions to perform the functions described herein and generate output information. The output information can be applied to one or more output devices in a known manner. For the purposes of this application, a processing system includes any system having a processor such as a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), or a microprocessor.

[0137] The program code can be implemented in a high-level procedural programming language or an object-oriented programming language to communicate with the processing system. If necessary, the program code can also be implemented in assembly language or machine language. In fact, the scope of the mechanism described herein is not limited to any specific programming language. In various embodiments, the language can be a compiled language or an interpreted language.

[0138] Embodiments of the methods, hardware, software, firmware, or code set forth above may be implemented via instructions or code stored on a machine-accessible, machine-readable, computer-accessible, or computer-readable medium that is executable (or otherwise accessible) by a processing element. Machine-accessible / readable media include any mechanism that provides (i.e., stores and / or transmits) information in a form readable by a machine (e.g., a computer or electronic system). For example, machine-accessible media include random access memory (RAM), such as static RAM (SRAM) or dynamic RAM (DRAM); ROM; magnetic or optical storage media; flash memory devices; electrical storage devices; optical storage devices; acoustic storage devices; other forms of storage devices for holding information received from transient (propagating) signals (e.g., carrier waves, infrared signals, digital signals), etc., which media are distinguished from non-transitory media from which information may be received.

[0139] Instructions for programming logic to perform embodiments of the disclosure may be stored in a memory (e.g., DRAM, cache, flash memory, or other storage device) in the system. In addition, instructions may be distributed via a network or through other computer-readable media. Therefore, a machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer), but is not limited to a floppy disk, an optical disk, a compact disk read-only memory (CD-ROM) and a magneto-optical disk, a read-only memory (ROM), a random access memory (RAM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a magnetic or optical card, a flash memory, or a tangible machine-readable storage device for transmitting information via an electrical, optical, acoustic, or other form of propagation signal (e.g., a carrier wave, an infrared signal, a digital signal, etc.) through the Internet. Therefore, a computer-readable medium includes any type of tangible machine-readable medium suitable for storing or transmitting electronic instructions or information in a form readable by a machine (e.g., a computer).

[0140] Logic can be used to implement any of the functions of various components. "Logic" can refer to hardware, firmware, software, and / or a combination of each thereof, for performing one or more functions. As an example, logic can include hardware such as a microcontroller or processor associated with a non-transitory medium, which is used to store code suitable for execution by the microcontroller or processor. Therefore, in one embodiment, reference to logic refers to hardware that is specifically configured to recognize and / or execute code to be retained on a non-transitory medium. In addition, in another embodiment, the use of logic refers to a non-transitory medium including code, which is particularly suitable for execution by a microcontroller to perform a predetermined operation. And as can be inferred, in yet another embodiment, the term logic (in this example) can refer to a combination of hardware and non-transitory media. In various embodiments, logic can include a microprocessor or other processing element operable to execute software instructions, discrete logic such as an application-specific integrated circuit (ASIC), a programming logic device such as a field programmable gate array (FPGA), a memory device containing instructions, a combination of logic devices (e.g., as can be found on a printed circuit board) or other suitable hardware and / or software. Logic may include one or more gates or other circuit components, which may be implemented by, for example, transistors. In some embodiments, logic may also be fully embodied as software. Software may be embodied as a software package, code, instructions, instruction sets, and / or data recorded on a non-temporary computer-readable storage medium. Firmware may be embodied as hard-coded (e.g., non-volatile) code, instructions, or instruction sets and / or data in a memory device. Often, logic boundaries shown as separate typically vary and potentially overlap. For example, a first logic and a second logic may share hardware, software, firmware, or a combination thereof, while potentially retaining some independent hardware, software, or firmware.

[0141] In one embodiment, the use of the phrase "for" or "configured to" refers to arranging, putting together, manufacturing, offering for sale, importing and / or designing a device, hardware, logic or element to perform a specified task or a determined task. In this example, if the device or its elements are designed, coupled and / or interconnected to perform the specified task, the device or its elements that are not operated are still "configured to" perform the specified task. As a purely illustrative example, a logic gate can provide a 0 or 1 during operation. However, the logic gate "configured to" provide an enable signal to the clock does not include that every potential logic gate can provide a 1 or 0. Instead, the logic gate is coupled in a certain way that a 1 or 0 output is used to enable the clock during operation. Note again that the use of the term "configured to" does not require operation, but focuses on the hidden state of the device, hardware and / or element, where in the hidden state, the device, hardware and / or element is designed to perform a specific task when the device, hardware and / or element is in operation.

[0142] Furthermore, in one embodiment, the use of the phrases "capable / capable for" and / or "operable for" refers to some device, logic, hardware, and / or element being designed in such a way that the device, logic, hardware, and / or element can be used in the specified manner. Note that as above, the use of for, capable of, or operable for in one embodiment refers to a hidden state of a device, logic, hardware, and / or element, where the device, logic, hardware, and / or element is not operational but is designed in such a way that the device can be used in the specified manner.

[0143] As used herein, value includes any known representation of a number, state, logic state, or binary logic state. Often, the use of logic levels, logic values, or logical values ​​is also referred to as the use of 1 and 0, which only represents a binary logic state. For example, 1 refers to a high logic level, and 0 refers to a low logic level. In one embodiment, a storage unit such as a transistor or a flash memory cell can hold a single logic value or multiple logic values. However, other representations of values ​​have been used in computer systems. For example, decimal tens can also be represented as a binary value 1010 and the hexadecimal letter A. Therefore, a value includes any representation of information that can be stored in a computer system.

[0144] In addition, a state can be represented by a value or a portion of a value. As an example, a first value (e.g., a logical one) can represent a default or initial state, while a second value (e.g., a logical zero) can represent a non-default state. In addition, in one embodiment, the terms reset and set refer to a default value or state and an updated value or state, respectively. For example, a default value potentially includes a high logic value (i.e., reset) and an updated value potentially includes a low logic value (i.e., set). Note that any combination of values ​​can be used to represent any number of states.

[0145] In this detailed description, reference is made to the accompanying drawings forming a part thereof, wherein the same reference numerals always represent the same parts, and wherein embodiments that can be practiced are shown by way of illustration. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description should not be regarded as having a limiting meaning, and the scope of the embodiments is defined by the appended claims and their equivalents.

[0146] Aspects of the disclosure are disclosed in the attached description. Alternative embodiments of the disclosure and their equivalents may be envisioned without departing from the spirit or scope of the disclosure. It should be noted that the same elements disclosed below are represented by the same reference numerals in the accompanying drawings.

[0147] The various operations may be described as multiple discrete actions or operations in a manner that is most helpful for understanding the claimed subject matter. However, the order of description should not be interpreted as implying that these operations must rely on the order. In particular, these operations may not be performed in the order presented. The described operations may be performed in an order different from the described embodiments. In additional embodiments, various additional operations may be performed and / or the described operations may be omitted.

[0148] For purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0149] The specification may use the phrases "in an embodiment" or "in embodiments," which may each refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," etc. as used with respect to the embodiments of the present disclosure are synonymous.

[0150] As used herein, the term "circuitry" may refer to, be part of, or include an application specific integrated circuit (ASIC), an electronic circuit, a (shared, dedicated, or group) processor and / or (shared, dedicated, or group) memory that executes one or more software or firmware programs, a combinational logic circuit, and / or other suitable components that provide the described functionality.

[0151] As used hereinafter including in the claims, the term "memory" may refer to one or more hardware devices for storing data, including random access memory (RAM), magnetic RAM, core memory, read-only memory (ROM), magnetic disk storage media, optical storage media, flash memory devices, and / or other machine-readable media for storing data. The term "computer-readable medium" may include, but is not limited to, memories, portable or fixed storage devices, optical storage devices, wireless channels, and various other media capable of storing, containing, or carrying (multiple) instructions and / or data.

[0152] As used hereinafter, including in the claims, the term "computing platform" may be considered synonymous with, and may occasionally be referred to hereinafter as: a computer device, a computing device, a client device or client, a mobile, a mobile unit, a mobile terminal, a mobile station, a mobile user, a mobile device, a user equipment (UE), a user terminal, a machine type communication (MTC) device, a machine to machine (M2M) device, an M2M device (M2ME), an Internet of Things (IoT) device, a subscriber, a user, a receiver, etc., and may describe any physical hardware device that is capable of sequentially and automatically performing a series of arithmetic or logical operations, is equipped for recording / storing data on a machine-readable medium, and sending and receiving data from one or more other devices in a communication network. Furthermore, the term “computing platform” may include any type of electronic device, such as a cellular telephone or smart phone, a tablet personal computer, a wearable computing device, an autonomous sensor, a personal digital assistant (PDA), a laptop computer, a desktop personal computer, a video game console, a digital media player, an in-vehicle infotainment system (IVI) and / or in-vehicle entertainment (ICE) device, an in-vehicle computing system, a navigation system, an autonomous driving system, a vehicle-to-vehicle (V2V) communication system, a vehicle-to-everything (V2X) communication system, a handheld messaging device, a personal data assistant, an e-book reader, an augmented reality device, and / or any other similar electronic device.

[0153] As used hereinafter including in the claims, the term "link" or "communication link" may refer to any tangible or intangible transmission medium for communicating data or data streams. Additionally, the term "link" may be synonymous and / or equivalent to "communication channel," "data communication channel," "transmission channel," "data transmission channel," "access channel," "data access channel," "channel," "data link," "radio link," "carrier," "radio frequency carrier," and / or any other similar term representing a path or medium through which data is communicated.

[0154] The systems, methods, computer program products, and apparatus may include one or a combination of the following examples:

[0155] Example 1 may include an apparatus for computing, comprising: a flexible bus link; and a flexible bus stack coupled to the flexible bus link, the flexible bus stack comprising multiplexing logic for selecting a PCIe upper layer mode or an accelerator link protocol upper layer mode for communicating over the flexible bus link.

[0156] Example 2 may include the apparatus for computing of Example 1 and / or any other example herein, wherein the multiplexing logic is used to perform the selection during link initialization.

[0157] Example 3 may include the apparatus for computing of Example 1 and / or any other example herein, wherein the multiplexing logic is further used to enable a single protocol or multiple protocols if the accelerator link mode is selected.

[0158] Example 4 may include the apparatus for computing of Example 1 and / or any other example herein, wherein if the accelerator link mode is selected, the apparatus is further configured to enable latency optimization.

[0159] Example 5 may include an apparatus for computing of Examples 3 and 4 and / or any other examples herein, wherein a modified PCIe 5.0 Training Set 1 / Training Set 2 (TS1 / TS2) ordered set is used to negotiate which accelerator link protocols are to be enabled.

[0160] Example 6 may include the apparatus for computing of Example 5 and / or any other example herein, wherein the modified PCIe TS1 / TS2 ordered sets are further used to negotiate which accelerator link low latency features to enable.

[0161] Example 7 may include the apparatus for computing of Example 5 and / or any other example herein, wherein the accelerator link protocol includes one or more of: IAL.io, IAL.mem, and IAL.cache.

[0162] Example 8 may include the apparatus for computing of Example 6 and / or any other example herein, wherein the low latency features include one or more of: synchronization header suppression, skip (SKP) ordered set suppression, and drift buffer mode.

[0163] Example 9 may include an apparatus for computing of Example 5 and / or any other example herein, wherein the negotiation comprises a two-phase process that occurs while in PCIe 5.0 Config.LaneNumber.Wait, Config.LaneNumber.Accept, and Config.Done and prior to entering L0 at Gen1 speed.

[0164] Example 10 may include an apparatus for computing of Example 9 and / or any other example herein, wherein the first stage comprises: receiving a stream of modified TS1 ordered sets providing flexible bus capabilities from a root complex, and sending, by the apparatus, a stream of modified TS1 ordered sets to the root complex indicating which flexible bus capabilities are to be enabled.

[0165] Example 11 may include the apparatus for computing of Example 10 and / or any other example herein, wherein the first phase is to occur during PCIe 5.0 Config.LaneNumber.Wait or Config.LaneNumber.Accept.

[0166] Example 12 may include an apparatus for computing of Example 10 and / or any other example herein, wherein the second stage includes: receiving an enable request from a root complex, the enable request including a stream of modified TS2 ordered sets indicating whether the flexible bus link is to operate in a PCIe upper layer mode or an accelerator link protocol upper layer mode, and sending, by the apparatus, a stream of modified TS2 ordered sets with the same flexible bus enable bit to the root complex to confirm the enable request.

[0167] Example 13 may include the apparatus for computing of Example 12 and / or any other example herein, wherein the second phase is to occur during PCIe 5.0 Configuration.Completion.

[0168] Example 14 may include one or more non-transitory computer-readable storage media including a plurality of instructions that, in response to being executed, cause multiplexing logic coupled to the flexible bus link to select a PCIe upper layer mode or an accelerator link protocol upper layer mode to communicate over the flexible bus link.

[0169] Example 15 may include the one or more non-transitory computer-readable storage media of Example 14 and / or any other examples herein, further comprising instructions that in response to being executed cause the multiplexing logic to perform selection during link initialization.

[0170] Example 16 may include one or more non-transitory computer-readable storage media of Example 14 and / or any other examples herein, further comprising instructions that, in response to being executed, cause the multiplexing logic to perform the following operations: if the accelerator link mode is selected, enable a single protocol or multiple protocols.

[0171] Example 17 may include one or more non-transitory computer-readable storage media of Example 14 and / or any other examples herein, further comprising instructions that, in response to being executed, cause the multiplexing logic to perform the following operations: if the accelerator link mode is selected, enable latency optimization.

[0172] Example 18 may include one or more non-transitory computer-readable storage media of Example 16 and / or any other examples herein, wherein a modified PCIe 5.0 Training Set 1 / Training Set 2 (TS1 / TS2) ordered set (OS) is used to negotiate which accelerator link protocols are to be enabled.

[0173] Example 19 may include one or more non-transitory computer-readable storage media of Example 17 and / or any other examples herein, wherein the modified PCIe TS1 / TS2 ordered sets are further used to negotiate which accelerator link low latency features to enable.

[0174] Example 20 may include the one or more non-transitory computer-readable storage media of Example 18 and / or any other examples herein, wherein the accelerator link protocol includes one or more of: IAL.io, IAL.mem, and IAL.cache.

[0175] Example 21 may include one or more non-transitory computer-readable storage media of Example 19 and / or any other example herein, wherein the low latency features include one or more of: synchronization header suppression, skip (SKP) ordered set suppression, and drift buffer mode.

[0176] Example 22 may include one or more non-transitory computer-readable storage media of Example 19 and / or any other examples herein, wherein the negotiation comprises a two-phase process that occurs while in PCIe 5.0 Config.LaneNumber.Wait, Config.LaneNumber.Accept, and Config.Done and prior to entering L0 at Gen1 speed.

[0177] Example 23 may include one or more non-transitory computer-readable storage media of Example 22 and / or any other examples herein, wherein the first stage includes receiving a stream of modified TS1 ordered sets providing flexible bus capabilities from a root complex, and sending, by the device, a stream of modified TS1 ordered sets to the root complex indicating which flexible bus capabilities are to be enabled.

[0178] Example 24 may include one or more non-transitory computer-readable storage media of Example 23 and / or any other examples herein, wherein the first phase is to occur during PCIe 5.0 Config.LaneNumber.Wait or Config.LaneNumber.Accept.

[0179] Example 25 may include one or more non-transitory computer-readable storage media of Example 22 and / or any other examples herein, wherein the second stage includes receiving an enable request from a root complex, the enable request including a stream of modified TS2 ordered sets indicating whether the flexible bus link is to operate in a PCIe upper layer mode or an accelerator link protocol upper layer mode, and sending, by the device to the root complex, a stream of modified TS2 ordered sets with the same flexible bus enable bit to confirm the enable request.

[0180] Example 26 may include the one or more non-transitory computer-readable storage media of Example 25 and / or any other examples herein, wherein the second phase is to occur during PCIe 5.0 Configuration.Complete.

[0181] Embodiment 27 is a device comprising: a flexible bus link; and a flexible bus stack coupled to the flexible bus link, the flexible bus stack comprising: multiplexing logic for selecting one of a Peripheral Component Interconnect Express (PCIe) upper layer mode or an accelerator link protocol upper layer mode, the PCIe upper layer mode or the accelerator link protocol upper layer mode being used for communicating through the flexible bus link; and physical layer logic for determining one or more low latency characteristics associated with one or both of the PCIe upper layer mode or the accelerator link protocol upper layer mode.

[0182] Example 28 is one or more non-transitory computer-readable storage media, comprising a plurality of instructions that, in response to being executed, cause a multiplexing logic coupled to a flexible bus link to select an upper layer mode based on a Peripheral Component Interconnect Express (PCIe) or an accelerator link protocol upper layer mode to communicate over the flexible bus link; and cause a physical layer logic coupled to the flexible bus link to determine one or more low latency features associated with one or both of the PCIe upper layer mode or the accelerator link protocol upper layer mode.

[0183] Example 29 is a system comprising a host device, the host device comprising: a root complex; a flexible bus link; and a flexible bus stack coupled to the flexible bus link, the flexible bus stack comprising: multiplexing logic for selecting one of a Peripheral Component Interconnect Express (PCIe) upper layer mode or an accelerator link protocol upper layer mode, the PCIe upper layer mode or the accelerator link protocol upper layer mode being used for communicating over the flexible bus link; and physical layer logic for determining one or more low latency characteristics associated with one or both of the PCIe upper layer mode or the accelerator link protocol upper layer mode; the system also comprising an endpoint device coupled to the host device across the flexible bus link.

[0184] Example 30 may include the subject matter of Example 29, wherein the root complex is used to: send a first set of modified training set (TS) 1 ordered sets to an endpoint device, the first set of TS1 ordered sets including a notification of one or more flexible bus capabilities of a flexible bus link; and receive a second set of modified TS1 ordered sets from the endpoint device, the second set of modified TS1 ordered sets identifying one or more flexible bus capabilities to be activated.

[0185] Example 31 may include the subject matter of Example 29 or 30, wherein the root complex is used to: send a first set of modified TS2 ordered sets to an endpoint device, the first set of modified TS2 ordered sets indicating whether the endpoint device should operate in PCIe mode or accelerator link mode; and receive a second set of modified TS2 ordered sets from the endpoint device, the second set of modified TS2 ordered sets indicating PCIe mode or accelerator link mode.

[0186] Example 32 may include the subject matter of Example 31, wherein the received second set of modified TS2 ordered sets indicates that an accelerator link mode is selected by the endpoint, and wherein the physical layer logic is used to activate a low latency feature setting associated with the accelerator link mode, the low latency feature setting indicating one or more low latency features, the low latency features including one or more of synchronization header suppression, skip (SKP) ordered set suppression, and a drift buffer mode.

[0187] Example 33 is a method comprising: selecting, by multiplexing logic, one of a Peripheral Component Interconnect Express (PCIe) upper layer mode or an accelerator link protocol upper layer mode, the PCIe upper layer mode or the accelerator link protocol upper layer mode being used for communicating over a flexible bus link; and physical layer logic for determining, by the flexible bus physical layer logic, one or more low latency characteristics associated with one or both of the PCIe upper layer mode or the accelerator link protocol upper layer mode.

Claims

1. A device for communication, comprising: A host device comprising: Processor core; and The root complex is used to: sending a first stream of modified training sequence 1 (TS1) ordered sets to an endpoint device, each modified TS1 ordered set in the first stream of modified TS1 ordered sets including a bit for advertising low delay capability; receiving a second stream of modified TS1 ordered sets from the endpoint device, each modified TS1 ordered set in the second stream of modified TS1 ordered sets comprising a bit set to indicate low latency capabilities of the endpoint device; and A stream of modified training sequence 2 (TS2) ordered sets is sent to the endpoint device, each modified TS2 ordered set in the stream of modified TS2 ordered sets including a bit set to indicate use of low delay capabilities on a link.

2. The device according to claim 1, wherein: The low latency capability is used to bypass synchronization header insertion.

3. The device according to claim 1 or 2, wherein: The root complex sends the first stream of the modified TS1 ordered-set during link training to advertise flexible bus capabilities.

4. The device according to claim 1 or 2, wherein: The root complex sends the modified stream of TS2 ordered sets to indicate to the endpoint device to use an accelerator link protocol instead of a protocol based on a Peripheral Component Interconnect Express (PCIe) protocol.

5. The device according to claim 4, wherein: The accelerator link protocol is based on a deviation-based consistency model.

6. The device according to claim 1 or 2, wherein: Each modified TS2 ordered-set in the first stream of modified TS2 ordered-sets includes a flexible bus capability bit that is set, and the second stream of modified TS2 ordered-sets includes an acknowledgement of the flexible bus capability bit that is set.

7. The device according to claim 6, wherein: The confirmation of the flexible bus capability bit being set includes setting the same flexible bus capability bit in each modified TS2 ordered set in the second stream of the modified TS2 ordered set as in each modified TS2 ordered set in the first stream of the modified TS2 ordered set.

8. The device according to claim 1 or 2, wherein: The root complex includes a flexible bus logic PHY for operating according to one of an accelerator link protocol or an interconnect protocol based on a Peripheral Component Interconnect Express (PCIe) protocol.

9. The device according to claim 1 or 2, wherein: The root complex includes physical layer electronic circuitry for operating in accordance with a Peripheral Component Interconnect Express (PCIe) protocol.

10. The device according to claim 1 or 2, wherein: The root complex is used to encode bits in symbols 12-14 so that the bits are used to advertise low delay capabilities in the first stream of the modified TS1 ordered-set.

11. A system for communication, comprising: Endpoint devices; as well as A host device coupled to the endpoint device via a link, the host device comprising: processor, and root complex; The root complex is configured to send a first stream of modified training sequence 1 (TS1) ordered sets for the endpoint device to the endpoint device to perform flexible bus negotiation with the endpoint device, each modified TS1 ordered set in the first stream of modified TS1 ordered sets including a bit for advertising low latency capability; the endpoint device being configured to send a second stream of modified TS1 ordered sets to the root complex, each modified TS1 ordered set in the second stream of modified TS1 ordered sets comprising a bit set to indicate a low latency capability of the endpoint device; and The root complex is to send a stream of modified training sequence 2 (TS2) ordered sets to the endpoint device, each modified TS2 ordered set in the stream of modified TS2 ordered sets including a bit set to indicate to the endpoint device to use the low latency capability on the link.

12. The system according to claim 11, wherein: The low latency capability is a bypass of sync header insertion.

13. The system according to claim 11 or 12, wherein: The root complex sends the first stream of the modified TS1 ordered-set during link training to advertise flexible bus capabilities.

14. The system according to claim 11 or 12, wherein: The root complex sends the modified TS2 ordered-set stream to indicate to the endpoint device the use of the accelerator link protocol.

15. The system of claim 14, wherein: The accelerator link protocol includes a deviation-based consistency model.

16. The system according to claim 11 or 12, wherein: The host device includes a host memory; The endpoint device comprises: accelerators; and Accelerator memory, Wherein, the memory is mapped to the host memory address space.

17. The system according to claim 11 or 12, wherein: Each modified TS2 ordered-set in a first stream of modified TS2 ordered-sets comprises a flexible bus capability bit set; and The endpoint device is configured to send a second stream of modified TS2 ordered sets from the endpoint device, each modified TS2 ordered set in the second stream of modified TS2 ordered sets including an acknowledgement of the flexible bus capability bit being set.

18. The system of claim 17, wherein: The confirmation of the flexible bus capability bit being set includes setting the same flexible bus capability bit in the second stream of the modified TS2 ordered-set as the first stream of the modified TS2 ordered-set.

19. The system according to claim 11 or 12, wherein: The root complex includes a flexible bus logic PHY for operating according to one of an accelerator link protocol or an interconnect protocol based on a Peripheral Component Interconnect Express (PCIe) protocol.

20. The system according to claim 11 or 12, wherein: The root complex includes physical layer electronic circuitry for operating in accordance with a Peripheral Component Interconnect Express (PCIe) protocol.

21. The system of claim 11 or 12, further comprising an arbiter / multiplexer (ARB / MUX) circuit for determining a protocol associated with a received flow control unit and sending the flow control unit to a link layer associated with the protocol.

22. An apparatus for communication, comprising: Endpoint devices, including: A processor and a memory, wherein the processor is configured to: receiving a first stream of modified training sequence 1 (TS1) ordered sets from a central processing unit (CPU), each modified TS1 ordered set in the first stream of modified TS1 ordered sets including a bit for advertising low delay capability; sending a second stream of modified TS1 ordered sets to the CPU, each modified TS1 ordered set in the second stream of TS1 ordered sets from the endpoint device including a bit set to indicate low latency capability of the endpoint device; receiving from the CPU a first stream of modified training sequence 2 (TS2) ordered sets, each modified TS2 ordered set in the first stream of modified TS2 ordered sets including a bit set to indicate use of low delay capability on a link; and A second stream of modified TS2 ordered sets is sent to the CPU to confirm use of the low latency capability on the link.

23. The apparatus of claim 22, wherein the endpoint device comprises: accelerator; as well as Accelerator memory, Wherein, the memory is mapped to the host memory address space.

24. The device according to claim 22 or 23, wherein: The low latency capability is a bypass of sync header insertion.

25. The device according to claim 22 or 23, wherein: The first stream of the modified TS2 ordered-set enables the endpoint device to use the accelerator link protocol.

26. The device according to claim 25, wherein The accelerator link protocol includes a deviation-based consistency model.

27. The device according to claim 22 or 23, wherein: Each modified TS2 ordered-set in the first stream of modified TS2 ordered-sets includes a set flexible bus capability bit; and each modified TS2 ordered-set in the second stream of modified TS2 ordered-sets includes an acknowledgement of the set flexible bus capability bit.

28. The device according to claim 27, wherein The confirmation of the flexible bus capability bit being set includes setting the same flexible bus capability bit in each modified TS2 ordered set in the second stream of the modified TS2 ordered set as in each modified TS2 ordered set in the first stream of the modified TS2 ordered set.

29. A method performed by a host device, the method comprising: sending a first stream of a modified training sequence 1 (TS1) ordered set to an endpoint device to advertise flexible bus capabilities; receiving a second stream of modified TS1 ordered sets from the endpoint device; identifying, from the second stream of the modified TS1 ordered-set, a low-latency capability for the endpoint device; determining to use the low latency capability; as well as A modified stream of training sequence 2 (TS2) ordered sets is sent to the endpoint device to inform the endpoint device to use the low delay capability.

30. The method of claim 29, wherein: The low latency capability is used to bypass synchronization header insertion.

31. The method according to claim 29 or 30, wherein: The first stream of the modified TS1 ordered-set includes an identification of the flexible bus capability of the host device.

32. The method according to claim 29 or 30, wherein: The first stream of the modified TS2 ordered-set includes an indication to use an accelerator link protocol instead of a protocol based on a Peripheral Component Interconnect Express (PCIe) protocol.

33. The method of claim 32, wherein: The accelerator link protocol is based on a deviation-based consistency model.

34. The method according to claim 29 or 30, wherein: The modified TS2 ordered set stream is a first stream of TS2 ordered sets, each modified TS2 ordered set in the first stream of the modified TS2 ordered sets includes a set flexible bus capability bit; the method comprising: A second stream of modified TS2 ordered sets is received from the endpoint device, each modified TS2 ordered set in the second stream of modified TS2 ordered sets including an acknowledgement of the flexible bus capability bit being set.

35. The method of claim 34, wherein: The confirmation of the flexible bus capability bit being set includes setting the same flexible bus capability bit in each modified TS2 ordered set in the second stream of the modified TS2 ordered set as in each modified TS2 ordered set in the first stream of the modified TS2 ordered set.

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