Solid-state image sensing device and electronic device

Abstract

This technology relates to a solid-state image sensing device and electronic device capable of reducing noise. The solid-state image sensing device includes: a photoelectric conversion unit; a charge retention unit for retaining charge transferred from the photoelectric conversion unit; a first transfer transistor for transferring charge from the photoelectric conversion unit to the charge retention unit; and a light shielding portion including a first light shielding portion and a second light shielding portion, wherein the first light shielding portion is arranged between a second surface opposite to a first surface of the photoelectric conversion unit, which is a light receiving surface, and covers the charge retention unit and has a first opening formed therein, and the second light shielding portion surrounds a side surface of the photoelectric conversion unit. This technology is applicable, for example, to a back-illuminated solid-state image sensing device.

Description

[0001] This application is a divisional application of patent application No. 201680011099.2, filed on February 12, 2016, with the invention name “Solid-state imaging device and electronic device”. Technical Field

[0002] The present technology relates to a solid-state image sensing device and an electronic device, and in particular, to a solid-state image sensing device and an electronic device capable of reducing noise. Background Art

[0003] Conventionally, a back-illuminated solid-state image sensing device in a global shutter system has been proposed, in which a floating diffusion region that transfers charges accumulated in a photodiode is substantially covered by a horizontal shading portion, and a vertical shading portion is formed between adjacent pixels (for example, see Patent Document 1).

[0004] Citation List

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Laid-Open No. 2013-98446 Summary of the Invention

[0007] Technical issues

[0008] However, the technology described in Patent Document 1 is insufficient for shielding light on the surface opposite to the light-receiving surface of the photodiode. Therefore, there is a problem that charges generated by light that is not absorbed by the photodiode but passes through the photodiode invade the floating diffusion region and noise may occur.

[0009] The present technology is disclosed in light of such circumstances, and aims to reduce noise.

[0010] Technical Solution

[0011] According to a first aspect of the present technology, a solid-state image sensing device includes: a photoelectric conversion unit; a charge holding unit for holding the charge transferred from the photoelectric conversion unit; a first transfer transistor for transferring the charge from the photoelectric conversion unit to the charge holding unit; and a light shielding portion, including a first light shielding portion and a second light shielding portion, wherein the first light shielding portion is arranged between a second surface opposite to a first surface as a light receiving surface of the photoelectric conversion unit and the charge holding unit and covers the second surface, and is formed with a first opening, and the second light shielding portion surrounds the side surface of the photoelectric conversion unit.

[0012] The cross section of the first light shielding portion may gradually shrink from the connection portion with the second light shielding portion toward the first opening.

[0013] A third light shielding portion for covering at least a surface of the charge holding unit opposite to a surface facing the first light shielding portion may be further provided at a position away from the first light shielding portion from the device formation surface where the first transfer transistor is formed.

[0014] The gate electrode of the first transfer transistor may have a first electrode portion parallel to the first light-shielding portion and a second electrode portion perpendicular to the first light-shielding portion and extending from the first light-shielding portion closer to the charge holding unit toward the photoelectric conversion unit via the first opening.

[0015] The solid-state image sensing device may further include a fourth light shielding portion connected to the first light shielding portion and at least partially arranged closer to the charge holding unit than to the first light shielding portion and parallel to the second surface at a position different from the second light shielding portion.

[0016] The photoelectric conversion unit may be formed on a first semiconductor substrate, the charge retention unit may be formed on a second semiconductor substrate, the first transfer transistor may be formed over the first semiconductor substrate and the second semiconductor substrate, and a bonding interface between the first semiconductor substrate and the second semiconductor substrate may be formed in a channel of the first transfer transistor.

[0017] The bonding interface may be formed closer to the drain terminal of the transfer transistor than to the source terminal of the transfer transistor.

[0018] The second light shielding portion may be formed by the second surface of the photoelectric conversion unit, and the solid-state image sensing device may further be provided with a fifth light shielding portion formed by the first surface of the photoelectric conversion unit and connected to the second light shielding portion.

[0019] The photoelectric conversion unit, the charge holding unit, and the first transfer transistor may be made of single crystal silicon.

[0020] The photoelectric conversion unit may have a protrusion extending from the first light shielding portion toward the charge holding unit via the first opening on the second surface.

[0021] The protrusion may extend parallel to the second surface closer to the charge holding unit side than to the first light shielding portion.

[0022] The solid-state image sensing device is further provided with a discharge unit for discharging charges accumulated in the photoelectric conversion unit, and the discharge unit may be arranged at a position where light having a predetermined incident angle is incident when the light passes through the first opening.

[0023] The discharge cell may be disposed between a first pixel and a second pixel adjacent to each other and may be shared by the first pixel and the second pixel.

[0024] The first opening may be arranged near the discharge unit in the first pixel and the second pixel, respectively, a second opening having substantially the same size as the first opening may be formed at a position in the first pixel corresponding to the first opening in the second pixel, and a third opening having substantially the same size as the first opening may be formed at a position in the second pixel corresponding to the first opening in the first pixel.

[0025] The sacrificial film for forming the first light shielding portion may be made of SiGe, and the solid-state image sensing device may further be provided with an alignment mark made of the sacrificial film that is not removed.

[0026] A cross-section of the first light shielding portion may be circular at the first opening.

[0027] The solid-state image sensing device may also be provided with a charge-voltage conversion unit and a second transfer transistor for transferring the charge retained in the charge holding unit to the charge-voltage conversion unit, and the first light shielding portion may be arranged between the second surface of the photoelectric conversion unit and the charge holding unit and the charge-voltage conversion unit.

[0028] An electronic device according to a second aspect of the present technology includes a solid-state image sensing device, which includes: a photoelectric conversion unit; a charge holding unit for holding the charge transferred from the photoelectric conversion unit; a first transfer transistor for transferring the charge from the photoelectric conversion unit to the charge holding unit; and a light shielding portion, including a first light shielding portion and a second light shielding portion, wherein the first light shielding portion is arranged between a second surface opposite to a first surface which is a light receiving surface of the photoelectric conversion unit and the charge holding unit and covers the second surface, and is formed with a first opening, and the second light shielding portion surrounds the side surface of the photoelectric conversion unit.

[0029] According to the third aspect of the present technology, a solid-state image sensing device includes: a photoelectric conversion unit; a charge holding unit for holding the charge transferred from the photoelectric conversion unit; a transfer transistor for transferring the charge from the photoelectric conversion unit to the charge holding unit; and a light shielding portion, including a first light shielding portion and a second light shielding portion formed with an opening, wherein the first light shielding portion is arranged parallel to the light receiving surface of the photoelectric conversion unit and arranged between the photoelectric conversion unit and the charge holding unit, and covers the photoelectric conversion unit except the opening, and the second light shielding portion surrounds the side surface of the photoelectric conversion unit.

[0030] According to the first to third aspects of the present technology, light passing through the photoelectric conversion unit is blocked by the first light blocking portion, and light from the adjacent pixel is blocked by the second light blocking portion.

[0031] The beneficial effects of the present invention are as follows:

[0032] According to the first to third aspects of the present technology, noise can be reduced.

[0033] Additionally, the effects described herein are not necessarily limited, and any effects described in the present disclosure can be obtained. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 is a block diagram illustrating an exemplary configuration of functions of a solid-state image sensing device according to a first embodiment of the present technology;

[0035] Figure 2 is a circuit diagram showing an exemplary configuration of a pixel in the solid-state image sensing device according to the first embodiment;

[0036] Figure 3 is a cross-sectional view schematically showing an exemplary configuration of a solid-state image sensing device according to a first embodiment;

[0037] Figure 4 This is an enlarged view of the structure around the TRX;

[0038] Figure 5 A diagram illustrating the position of a grain boundary of a polysilicon thin film transistor (TFT);

[0039] Figure 6 A diagram for explaining a potential barrier at a position in a channel of a TFT;

[0040] Figure 7 is a diagram for explaining a change in an electric field at each position in a channel of a TFT;

[0041] Figure 8 is a top view schematically showing an exemplary configuration of a device forming surface of the solid-state image sensing device according to the first embodiment;

[0042] Figure 9 For enlarged views, cross sections around the TRM and MEM are schematically shown;

[0043] Figure 10 A diagram for explaining a method of manufacturing the solid-state image sensing device according to the first embodiment;

[0044] Figure 11 A diagram for explaining a method of manufacturing the solid-state image sensing device according to the first embodiment;

[0045] Figure 12 A diagram for explaining a method of manufacturing the solid-state image sensing device according to the first embodiment;

[0046] Figure 13 A diagram for explaining a method of manufacturing the solid-state image sensing device according to the first embodiment;

[0047] Figure 14A diagram for explaining a method of manufacturing the solid-state image sensing device according to the first embodiment;

[0048] Figure 15 A diagram for explaining a method of manufacturing the solid-state image sensing device according to the first embodiment;

[0049] Figure 16 A diagram for explaining a method of manufacturing the solid-state image sensing device according to the first embodiment;

[0050] Figure 17 A diagram for explaining a method of manufacturing the solid-state image sensing device according to the first embodiment;

[0051] Figure 18 A diagram for explaining a method of manufacturing the solid-state image sensing device according to the first embodiment;

[0052] Figure 19 A diagram for explaining a method of manufacturing the solid-state image sensing device according to the first embodiment;

[0053] Figure 20 A diagram for explaining a method of manufacturing the solid-state image sensing device according to the first embodiment;

[0054] Figure 21 A diagram for explaining a method of manufacturing the solid-state image sensing device according to the first embodiment;

[0055] Figure 22 A diagram for explaining a method of manufacturing the solid-state image sensing device according to the first embodiment;

[0056] Figure 23 A diagram for explaining a method of manufacturing the solid-state image sensing device according to the first embodiment;

[0057] Figure 24 A diagram for explaining a method of manufacturing the solid-state image sensing device according to the first embodiment;

[0058] Figure 25 A diagram for explaining a method of manufacturing the solid-state image sensing device according to the first embodiment;

[0059] Figure 26 A diagram for explaining a method of manufacturing the solid-state image sensing device according to the first embodiment;

[0060] Figure 27 A diagram for explaining a method of manufacturing the solid-state image sensing device according to the first embodiment;

[0061] Figure 28 A diagram for explaining a method of manufacturing the solid-state image sensing device according to the first embodiment;

[0062] Figure 29 A diagram for explaining a method of manufacturing the solid-state image sensing device according to the first embodiment;

[0063] Figure 30 A diagram for explaining a method of manufacturing the solid-state image sensing device according to the first embodiment;

[0064] Figure 31 A diagram for explaining a method of manufacturing the solid-state image sensing device according to the first embodiment;

[0065] Figure 32 A diagram for explaining a method of manufacturing the solid-state image sensing device according to the first embodiment;

[0066] Figure 33 A diagram for explaining a method of manufacturing the solid-state image sensing device according to the first embodiment;

[0067] Figure 34 A diagram for explaining a method of manufacturing the solid-state image sensing device according to the first embodiment;

[0068] Figure 35 A diagram for explaining a method of manufacturing the solid-state image sensing device according to the first embodiment;

[0069] Figure 36 A diagram for explaining a method of manufacturing the solid-state image sensing device according to the first embodiment;

[0070] Figure 37 A diagram for explaining a method of manufacturing the solid-state image sensing device according to the first embodiment;

[0071] Figure 38 A diagram for explaining a method of manufacturing the solid-state image sensing device according to the first embodiment;

[0072] Figure 39 A diagram for explaining a method of manufacturing the solid-state image sensing device according to the first embodiment;

[0073] Figure 40 A diagram for explaining a method of manufacturing the solid-state image sensing device according to the first embodiment;

[0074] Figure 41 A diagram for explaining a method of manufacturing the solid-state image sensing device according to the first embodiment;

[0075] Figure 42 A diagram for explaining a method of manufacturing the solid-state image sensing device according to the first embodiment;

[0076] Figure 43A diagram for explaining a method of manufacturing the solid-state image sensing device according to the first embodiment;

[0077] Figure 44 A diagram for explaining a method of manufacturing the solid-state image sensing device according to the first embodiment;

[0078] Figure 45 A diagram for explaining a method of manufacturing the solid-state image sensing device according to the first embodiment;

[0079] Figure 46 A diagram for explaining a method of manufacturing the solid-state image sensing device according to the first embodiment;

[0080] Figure 47 A diagram for explaining a method of manufacturing the solid-state image sensing device according to the first embodiment;

[0081] Figure 48 A diagram for explaining a method of manufacturing the solid-state image sensing device according to the first embodiment;

[0082] Figure 49 A diagram for explaining a method of manufacturing the solid-state image sensing device according to the first embodiment;

[0083] Figure 50 A diagram for explaining a method of manufacturing the solid-state image sensing device according to the first embodiment;

[0084] Figure 51 A diagram for explaining a method of manufacturing the solid-state image sensing device according to the first embodiment;

[0085] Figure 52 is a cross-sectional view schematically showing an exemplary configuration of a solid-state image sensing device according to a second embodiment of the present technology;

[0086] Figure 53 is a cross-sectional view schematically showing an exemplary configuration of a solid-state image sensing device according to a third embodiment of the present technology;

[0087] Figure 54 is a cross-sectional view schematically showing an exemplary configuration of a solid-state image sensing device according to a fourth embodiment of the present technology;

[0088] Figure 55 is a cross-sectional view schematically showing an exemplary configuration of a solid-state image sensing device according to a fifth embodiment of the present technology;

[0089] Figure 56 is a cross-sectional view schematically showing an exemplary configuration of a solid-state image sensing device according to a sixth embodiment of the present technology;

[0090] Figure 57 is a diagram for illustrating how to drive the solid-state image sensing device according to the sixth embodiment;

[0091] Figure 58 is a top view schematically showing an exemplary configuration of a device forming surface of a solid-state image sensing device according to a seventh embodiment of the present technology;

[0092] Figure 59 is a cross-sectional view schematically illustrating an exemplary configuration of a TRM and a MEM of a mesa structure;

[0093] Figure 60 is a cross-sectional view schematically showing an exemplary configuration of a mesa transistor;

[0094] Figure 61 is a cross-sectional view schematically showing an exemplary configuration of a mesa transistor;

[0095] Figure 62 is a cross-sectional view schematically showing an exemplary configuration of a mesa transistor;

[0096] Figure 63 is a cross-sectional view schematically showing an exemplary configuration of a mesa transistor;

[0097] Figure 64 is a circuit diagram showing an exemplary configuration of a pixel in a solid-state image sensing device according to an eighth embodiment of the present technology;

[0098] Figure 65 is a cross-sectional view schematically showing an exemplary configuration of a solid-state image sensing device according to an eighth embodiment;

[0099] Figure 66 is a top view schematically showing an exemplary configuration of a device forming surface of a solid-state image sensing device according to an eighth embodiment;

[0100] Figure 67 is a diagram for illustrating how to drive the solid-state image sensing device according to the eighth embodiment;

[0101] Figure 68 is a block diagram showing an exemplary configuration of a solid-state image sensing device according to a ninth embodiment of the present technology;

[0102] Figure 69 A diagram illustrating the advantage of providing an ADC for each pixel;

[0103] Figure 70 A diagram illustrating the advantage of providing an ADC for each pixel;

[0104] Figure 71FIG is a circuit diagram showing an exemplary configuration of a circuit in which an ADC is provided for each pixel;

[0105] Figure 72 FIG1 is a top view schematically showing an exemplary configuration of a device forming surface in the case where an ADC is provided in each pixel;

[0106] Figure 73 is a cross-sectional view schematically showing an exemplary configuration of a solid-state image sensing device according to a tenth embodiment of the present technology;

[0107] Figure 74 is a top view schematically showing an exemplary configuration of a device forming surface of a solid-state image sensing device according to a tenth embodiment and the position of a vertical light shielding portion;

[0108] Figure 75 is a top view showing the position of a horizontal light shielding portion in a solid-state image sensing device according to a tenth embodiment;

[0109] Figure 76 A diagram for explaining a method of manufacturing a solid-state image sensing device according to a tenth embodiment;

[0110] Figure 77 A diagram for explaining a method of manufacturing a solid-state image sensing device according to a tenth embodiment;

[0111] Figure 78 A diagram for explaining a method of manufacturing a solid-state image sensing device according to a tenth embodiment;

[0112] Figure 79 A diagram for explaining a method of manufacturing a solid-state image sensing device according to a tenth embodiment;

[0113] Figure 80 A diagram for explaining a method of manufacturing a solid-state image sensing device according to a tenth embodiment;

[0114] Figure 81 A diagram for explaining a method of manufacturing a solid-state image sensing device according to a tenth embodiment;

[0115] Figure 82 A diagram for explaining a method of manufacturing a solid-state image sensing device according to a tenth embodiment;

[0116] Figure 83 A diagram for explaining a method of manufacturing a solid-state image sensing device according to a tenth embodiment;

[0117] Figure 84 is a cross-sectional view schematically showing an exemplary configuration of a solid-state image sensing device according to an eleventh embodiment of the present technology;

[0118] Figure 85 A diagram for explaining a first method of manufacturing the solid-state image sensing device according to the eleventh embodiment;

[0119] Figure 86 A diagram for explaining a first method of manufacturing the solid-state image sensing device according to the eleventh embodiment;

[0120] Figure 87 A diagram for explaining a first method of manufacturing the solid-state image sensing device according to the eleventh embodiment;

[0121] Figure 88 A diagram for explaining a first method of manufacturing the solid-state image sensing device according to the eleventh embodiment;

[0122] Figure 89 A diagram for explaining a first method of manufacturing the solid-state image sensing device according to the eleventh embodiment;

[0123] Figure 90 A diagram for explaining a first method of manufacturing the solid-state image sensing device according to the eleventh embodiment;

[0124] Figure 91 A diagram for explaining a first method of manufacturing the solid-state image sensing device according to the eleventh embodiment;

[0125] Figure 92 A diagram for explaining a first method of manufacturing the solid-state image sensing device according to the eleventh embodiment;

[0126] Figure 93 A diagram for explaining a first method of manufacturing the solid-state image sensing device according to the eleventh embodiment;

[0127] Figure 94 A diagram for explaining a first method of manufacturing the solid-state image sensing device according to the eleventh embodiment;

[0128] Figure 95 A diagram for explaining a first method of manufacturing the solid-state image sensing device according to the eleventh embodiment;

[0129] Figure 96 A diagram for explaining a first method of manufacturing the solid-state image sensing device according to the eleventh embodiment;

[0130] Figure 97 A diagram for explaining a first method of manufacturing the solid-state image sensing device according to the eleventh embodiment;

[0131] Figure 98 A diagram for explaining a first method of manufacturing the solid-state image sensing device according to the eleventh embodiment;

[0132] Figure 99 A diagram for comparing steps of manufacturing an alignment mark;

[0133] Figure 100 is a diagram for considering other methods of manufacturing alignment marks;

[0134] Figure 101 is a diagram for considering other methods of manufacturing alignment marks;

[0135] Figure 102 is a diagram for considering other methods of manufacturing alignment marks;

[0136] Figure 103 is a diagram for considering other methods of manufacturing alignment marks;

[0137] Figure 104 is a diagram for explaining a second method of manufacturing the solid-state image sensing device according to the eleventh embodiment;

[0138] Figure 105 A diagram for explaining a second method of manufacturing the solid-state image sensing device according to the eleventh embodiment;

[0139] Figure 106 A diagram for explaining a second method of manufacturing the solid-state image sensing device according to the eleventh embodiment;

[0140] Figure 107 is a diagram for explaining a second method of manufacturing the solid-state image sensing device according to the eleventh embodiment;

[0141] Figure 108 is a diagram for explaining a second method of manufacturing the solid-state image sensing device according to the eleventh embodiment;

[0142] Figure 109 is a diagram for explaining a second method of manufacturing the solid-state image sensing device according to the eleventh embodiment;

[0143] Figure 110 is a diagram for explaining a second method of manufacturing the solid-state image sensing device according to the eleventh embodiment;

[0144] Figure 111 is a diagram for explaining a second method of manufacturing the solid-state image sensing device according to the eleventh embodiment;

[0145] Figure 112 is a diagram for explaining a second method of manufacturing the solid-state image sensing device according to the eleventh embodiment;

[0146] Figure 113 is a diagram for explaining a second method of manufacturing the solid-state image sensing device according to the eleventh embodiment;

[0147] Figure 114 A diagram for explaining a second method of manufacturing the solid-state image sensing device according to the eleventh embodiment;

[0148] Figure 115 is a diagram for explaining a second method of manufacturing the solid-state image sensing device according to the eleventh embodiment;

[0149] Figure 116 A diagram for explaining a second method of manufacturing the solid-state image sensing device according to the eleventh embodiment;

[0150] Figure 117 is a diagram for explaining a second method of manufacturing the solid-state image sensing device according to the eleventh embodiment;

[0151] Figure 118 A diagram for explaining a second method of manufacturing the solid-state image sensing device according to the eleventh embodiment;

[0152] Figure 119 is a diagram for explaining a second method of manufacturing the solid-state image sensing device according to the eleventh embodiment;

[0153] Figure 120 is a diagram for explaining a second method of manufacturing the solid-state image sensing device according to the eleventh embodiment;

[0154] Figure 121 is a graph for considering the minimum value of the horizontal shading portion;

[0155] Figure 122 A diagram for explaining a third method of manufacturing the solid-state image sensing device according to the eleventh embodiment;

[0156] Figure 123 A diagram for explaining a third method of manufacturing the solid-state image sensing device according to the eleventh embodiment;

[0157] Figure 124 A diagram for explaining a third method of manufacturing the solid-state image sensing device according to the eleventh embodiment;

[0158] Figure 125 A diagram for explaining a third method of manufacturing the solid-state image sensing device according to the eleventh embodiment;

[0159] Figure 126 A diagram for explaining a third method of manufacturing the solid-state image sensing device according to the eleventh embodiment;

[0160] Figure 127 A diagram for explaining a third method of manufacturing the solid-state image sensing device according to the eleventh embodiment;

[0161] Figure 128A diagram for explaining a third method of manufacturing the solid-state image sensing device according to the eleventh embodiment;

[0162] Figure 129 A diagram for explaining differences in the configuration of a solid-state image sensing device depending on a manufacturing method;

[0163] Figure 130 is a cross-sectional view schematically showing an exemplary configuration of a solid-state image sensing device according to a twelfth embodiment of the present technology;

[0164] Figure 131 A diagram for explaining a method of manufacturing a solid-state image sensing device according to a twelfth embodiment;

[0165] Figure 132 A diagram for explaining a method of manufacturing a solid-state image sensing device according to a twelfth embodiment;

[0166] Figure 133 A diagram for explaining a method of manufacturing a solid-state image sensing device according to a twelfth embodiment;

[0167] Figure 134 A diagram for explaining a method of manufacturing a solid-state image sensing device according to a twelfth embodiment;

[0168] Figure 135 A diagram for explaining a method of manufacturing a solid-state image sensing device according to a twelfth embodiment;

[0169] Figure 136 A diagram for explaining a method of manufacturing a solid-state image sensing device according to a twelfth embodiment;

[0170] Figure 137 A diagram for explaining a method of manufacturing a solid-state image sensing device according to a twelfth embodiment;

[0171] Figure 138 A diagram for explaining a method of manufacturing a solid-state image sensing device according to a twelfth embodiment;

[0172] Figure 139 A diagram for explaining a method of manufacturing a solid-state image sensing device according to a twelfth embodiment;

[0173] Figure 140 is a cross-sectional view schematically showing an exemplary configuration of a solid-state image sensing device according to a thirteenth embodiment of the present technology;

[0174] Figure 141 is a cross-sectional view schematically showing an exemplary configuration of a solid-state image sensing device according to a fourteenth embodiment of the present technology;

[0175] Figure 142is a cross-sectional view schematically showing an exemplary configuration of a solid-state image sensing device according to a fifteenth embodiment of the present technology;

[0176] Figure 143 is a top view schematically showing an exemplary configuration of a device forming surface of a solid-state image sensing device according to a fifteenth embodiment;

[0177] Figure 144 is a cross-sectional view schematically showing an exemplary configuration of a solid-state image sensing device according to a sixteenth embodiment of the present technology;

[0178] Figure 145 is a top view schematically showing an exemplary configuration of a device forming surface of a solid-state image sensing device according to a seventeenth embodiment of the present technology;

[0179] Figure 146 is a top view schematically showing an exemplary configuration of a device forming surface of a solid-state image sensing device according to an eighteenth embodiment of the present technology;

[0180] Figure 147 A diagram illustrating an exemplary application of a solid-state image sensing device;

[0181] Figure 148 is a block diagram showing an exemplary configuration of an electronic device. DETAILED DESCRIPTION

[0182] The specific implementation methods (hereinafter referred to as embodiments) will be described below.

[0183] 1. First Embodiment (First and Second Semiconductor Substrates Applied to Manufacturing a Solid-State Image Sensing Device)

[0184] 2. Second embodiment (deleting the barrier film)

[0185] 3. Third embodiment (addition of a light-shielding film formed by a light-receiving surface)

[0186] 4. Fourth embodiment (wiring layer has a light shielding film)

[0187] 5. Fifth embodiment (deleting the vertical light shielding portion)

[0188] 6. Sixth embodiment (changing cross-sectional structure)

[0189] 7. Seventh embodiment (each device is a table structure)

[0190] 8. Eighth Embodiment (OFG is a vertical gate structure)

[0191] 9. Ninth Embodiment (Pixel Array Section Has Pixel ADC Processing Unit)

[0192] 10. Tenth Embodiment (Conductive Layer with a Charge Opposite to Signal Charge Covering the Light-Shielding Film)

[0193] 11. Eleventh Example (Generating a Light-Shielding Film Using a Different Manufacturing Method)

[0194] 12. Twelfth Embodiment (PD has a plug extending upward from the opening of the light shielding film)

[0195] 13. Thirteenth embodiment (a cover is provided at the top end of the plug of the PD)

[0196] 14. Fourteenth embodiment (PD plug closer to the vertical light shielding portion)

[0197] 15. Fifteenth embodiment (discharge unit is arranged at the incident position of oblique light)

[0198] 16. Sixteenth Embodiment (Discharge Unit Shared by Adjacent Pixels)

[0199] 17. Seventeenth Embodiment (FD is shared by adjacent pixels)

[0200] 18. Eighteenth embodiment (setting a virtual opening)

[0201] 19. Modification

[0202] 20. Exemplary Applications of Solid-State Image Sensing Devices

[0203] <1. First embodiment>

[0204] First, refer to Figures 1 to 51 A first embodiment of the present technology will be described.

[0205] {Exemplary Configuration of Solid-State Image Sensing Device 101 a}

[0206] Figure 1 2 is a block diagram illustrating an exemplary configuration of functions of the solid-state image sensing device 101 a according to the first embodiment of the present technology.

[0207] The solid-state image sensor 101a is a back-illuminated image sensor in a global shutter system composed of, for example, a complementary metal oxide semiconductor (CMOS). The solid-state image sensor 101a receives light from a subject, photoelectrically converts the light, and generates an image signal, thereby capturing an image.

[0208] A global shutter system is a system for performing global exposure, starting exposure at all pixels substantially simultaneously and ending exposure at all pixels simultaneously. Here, "all pixels" refers to all pixels in a portion appearing on an image, excluding virtual pixels, etc. Furthermore, a global shutter system includes a system that performs global exposure on a row-by-row basis (such as several dozen rows) rather than simultaneously across all pixels when time differences or image distortion are negligible. Furthermore, a global shutter system includes a system that performs global exposure on pixels in a predetermined area rather than on all pixels in a portion appearing on an image.

[0209] A back-illuminated image sensor is an image sensor constructed so that a photoelectric conversion unit (such as a photodiode) for receiving light from a subject and converting it into an electrical signal is arranged between a light receiving surface on which light from the subject is incident and a wiring layer having wiring for driving a transistor, etc. for each pixel.

[0210] In addition, the present technology is not limited to application to CMOS image sensors.

[0211] The solid-state image sensing device 101 a includes a pixel array section 111 , a vertical drive unit 112 , a ramp module 113 , a clock module 114 , a data storage unit 115 , a horizontal drive unit 116 , a system control unit 117 , and a signal processing unit 118 .

[0212] The pixel array section 111 is formed on a semiconductor substrate (not shown) in the solid-state image sensing device 101a. Peripheral circuits such as the vertical drive unit 112 to the signal processing unit 118 may be formed, for example, on the same semiconductor substrate as the pixel array section 111, or may be formed on a logic layer stacked on the semiconductor substrate. Furthermore, for example, some of the peripheral circuits may be formed on the same semiconductor substrate as the pixel array section 111, while the rest may be formed on a logic layer.

[0213] In addition, in the case where the peripheral circuit is formed on the same semiconductor substrate as the pixel array section 111 , each of the devices (such as transistors) constituting the peripheral circuit may be a mesa structure.

[0214] The pixel array section 111 is formed of pixels, each of which has a photoelectric conversion device that generates and accumulates charge based on the amount of light incident from the subject. The pixels (not shown) that constitute the pixel array section 111 are arranged two-dimensionally in the horizontal (row) direction and the vertical (column) direction. For example, in the pixel array section 111, each row of pixels arranged in the row direction is wired with a pixel drive line (not shown) in the row direction, and each column of pixels arranged in the column direction is wired with a vertical signal line (not shown) in the column direction.

[0215] The vertical driving unit 112 is formed of a shift register, an address decoder, and the like, and supplies a signal and the like to each pixel via a pixel driving line, thereby driving all pixels in the pixel array section 111 simultaneously or in row units.

[0216] The ramp wave module 113 generates a ramp wave signal for performing analog / digital (A / D) conversion on the pixel signal and supplies it to a column processing unit (not shown). The column processing unit is composed of, for example, a shift register, an address decoder, etc., and performs noise reduction processing, correlated double sampling processing, A / D conversion processing, etc., thereby generating pixel signals. The column processing unit supplies the generated pixel signals to the signal processing unit 118.

[0217] The clock module 114 provides an operation clock signal to each unit in the solid-state image sensing device 101 a .

[0218] The horizontal driving unit 116 sequentially selects the unit circuits corresponding to a column of pixels in the column processing unit. Through the selective scanning of the horizontal driving unit 116, the pixel signals processed by each unit circuit in the column processing unit are sequentially output to the signal processing unit 118.

[0219] The system control unit 117 is composed of a timing generator for generating various timing signals, etc. The system control unit 117 drives and controls the vertical drive unit 112, ramp module 113, clock module 114, horizontal drive unit 116, and column processing unit according to the timing signals generated by the timing generator.

[0220] The signal processing unit 118 performs signal processing such as calculation processing on the pixel signal supplied from the column processing unit and outputs an image signal composed of each pixel signal while temporarily storing the data in the data storage unit 115 as necessary.

[0221] {Exemplary Configuration of Pixels}

[0222] The following will refer to Figure 2 To form Figure 1 An exemplary circuit configuration of pixels in the pixel array section 111 will be described. Figure 2 An exemplary circuit configuration of one pixel in the pixel array section 111 is shown.

[0223] In this example, each pixel in the pixel array section 111 includes a photoelectric conversion unit (PD) 151, a first transfer transistor (TRX) 152, a second transfer transistor (TRM) 153, a charge retention unit (MEM) 154, a third transfer transistor (TRG) 155, a charge-voltage conversion unit (FD) 156, a discharge transistor (OFG) 157, a reset transistor (RST) 158, an amplification transistor (AMP) 159, and a selection transistor (SEL) 160.

[0224] In this example, TRX 152, TRM 153, TRG 155, OFG 157, RST 158, AMP 159, and SEL 160 are each composed of an N-type MOS transistor. Drive signals TRX, TRM, TRG, OFG, RST, and SEL are supplied to the gate electrodes of TRX 152, TRM 153, TRG 155, OFG 157, RST 158, and SEL 160, respectively. The drive signals are pulse signals that are active (on) as a high level state and inactive (off) as a low level state. In the following, activating a drive signal will be referred to as "driving signal on," and deactivating a drive signal will be referred to as "driving signal off."

[0225] The PD 151 is a photoelectric conversion device formed of, for example, a PN-junction photodiode, which receives light from a subject and generates and accumulates charges according to the amount of received light through photoelectric conversion.

[0226] The TRX 152 is connected between the PD 151 and the TRM 153 , and transfers the charges accumulated in the PD 151 to the MEM 154 in response to a driving signal TRX applied to a gate electrode.

[0227] In addition, as described below, at least two semiconductor substrates are applied, and a bonding interface as an active surface is formed in the channel of the TRX 152 in the solid-state image sensing device 101a. Then, a parasitic resistance Rp is generated in parallel with the PD 151 at the bonding interface in the TRX 152.

[0228] The TRM 153 controls the potential of the MEM 154 in response to the drive signal TRM applied to the gate electrode. For example, when the drive signal TRM is on and the TRM 153 is conductive, the potential of the MEM 154 is deep, and when the drive signal TRM is off and the TRM 153 is off, the potential of the MEM 154 is shallow. Then, for example, when the drive signal TRX and the drive signal TRM are on and the TRX 152 and the TRM 153 are conductive, the charge accumulated in the PD 151 is transferred to the MEM 154 via the TRX 152 and the TRM 153.

[0229] The MEM 154 is a region that temporarily holds the charges accumulated in the PD 151 to implement a global shutter function.

[0230] The TRG 155 is connected between the TRM 153 and the FD 156, and transfers the charge held in the MEM 154 to the FD 156 in response to the drive signal TRG applied to the gate electrode. For example, when the drive signal TRM is turned off, the TRM 153 is turned off, the drive signal TRG is turned on, and the TRG 155 is turned on, the charge held in the MEM 154 is transferred to the FD 156 via the TRM 153 and the TRG 155.

[0231] The FD 156 is a floating diffusion region that converts the charge transferred from the MEM 154 via the TRG 155 into an electric signal such as a voltage signal and outputs the electric signal. The FD 156 is connected to the RST 158 and is connected to the vertical signal line VSL via the AMP 159 and the SEL 160 .

[0232] The drain of OFG 157 is connected to the power supply VDD, and the source of OFG 157 is connected between TRX 152 and TRM 153. OFG 157 initializes (resets) PD 151 in response to the drive signal OFG applied to the gate electrode. For example, when the drive signal TRX and the drive signal OFG are turned on and TRX 152 and OFG 157 are turned on, the potential of PD 151 is reset to the level of power supply voltage VDD. In other words, PD 151 is initialized.

[0233] Furthermore, the OFG 157 forms an overflow path between the TRX 152 and the power supply VDD, and discharges the charge overflowing from the PD 151 to the power supply VDD.

[0234] The drain of RST 158 is connected to power supply VDD, and the source of RST 158 is connected to FD 156. RST 158 initializes (resets) each region of MEM 154 to FD 156 in response to a drive signal RST applied to its gate electrode. For example, when drive signal TRG and drive signal RST are turned on and TRG 155 and RST 158 are conductive, the potentials of MEM 154 to FD 156 are reset to the level of power supply voltage VDD. In other words, MEM 154 and FD 156 are initialized.

[0235] The gate electrode of the AMP 159 is connected to the FD 156, the drain of the AMP 159 is connected to the power supply VDD, and the AMP 159 serves as an input unit of a source follower circuit for reading the charge obtained by photoelectric conversion in the PD 151. That is, the source of the AMP 159 is connected to the vertical signal line VSL via the SEL 160, thereby constituting a source follower circuit in which a constant current source is connected to one end of the vertical signal line VSL.

[0236] The SEL 160 is connected between the source of the AMP 159 and the vertical signal line VS1, and the drive signal SEL is supplied as a selection signal to the gate electrode of the SEL 160. When the drive signal SEL is on, the SEL 160 is in a conductive state, and the pixel having the SEL 160 is in a selected state. When the pixel enters the selected state, the pixel signal output from the AMP 159 is read by the column processing unit (not shown) via the vertical signal line VSL.

[0237] In addition, in each pixel, for example, a pixel driving line (not shown) is wired per row of pixels. Then, driving signals TRX, TRM, TRG, OFG, RST, and SEL are supplied from the vertical driving unit 112 to the pixels via the pixel driving lines.

[0238] in addition, Figure 2 The pixel circuit in FIG. 1 is an exemplary pixel circuit that can be used in the pixel array section 111, and pixel circuits of other configurations can be employed. In addition, the transistors of the RST 158, the AMP 159, and the SEL 160 will be hereinafter referred to as pixel transistors.

[0239] Figure 3 Schematically shows Figure 1 A cross section of the solid-state image sensing device 101a in FIG. Figure 3 A cross section of a portion including one pixel in the solid-state image sensing device 101 a is shown, but other pixels have basically the same configuration.

[0240] In the figures, the symbols "P" and "N" represent a P-type semiconductor region and an N-type semiconductor region, respectively. Furthermore, the "+" and "-" at the end of the symbols "P++," "P+," "P-," and "P--," as well as "N++," "N+," "N-," and "N--," respectively, represent the impurity concentrations in the P-type and N-type semiconductor regions. A larger number of "+"s indicates a higher impurity concentration, while a larger number of "-"s indicates a lower impurity concentration. This applies to the following figures.

[0241] In addition, assuming Figure 3 The bottom of the solid-state image sensing device 101a is the light receiving surface. Figure 3 In the figure, the upward direction is the upper surface or top surface of the solid-state image sensing device 101a, and the downward direction is the lower surface or bottom surface of the solid-state image sensing device 101a. In addition, hereinafter, the lower surface of each layer in the solid-state image sensing device 101a will be referred to as the back surface or lower surface, and the upper surface of each layer in the solid-state image sensing device 101a will be referred to as the surface or upper surface.

[0242] The solid-state image sensing device 101 a has a three-layer structure in which a first semiconductor substrate 201 , a second semiconductor substrate 202 , and a logic layer 203 are stacked.

[0243] An insulating film 214 , a planarizing film 212 , and a microlens 211 are stacked on a lower surface of an N − -type semiconductor region 215 in the first semiconductor substrate 201 .

[0244] An N-type semiconductor region 216 is formed above the microlens 211 inside the N-type semiconductor region 215. A P+ type semiconductor region 217 is stacked on the N-type semiconductor region 216. A hole accumulation diode (HAD, registered trademark) type PD 151 is composed of the N-type semiconductor region 216 and the P+ type semiconductor region 217.

[0245] Light incident in the light receiving surface of the solid-state image sensing device 101 a is photoelectrically converted by the PD 151 , and charges generated by the photoelectric conversion are accumulated in the N-type semiconductor region 216 .

[0246] The P-type semiconductor region 218 is formed around a portion where the vertical terminal (electrode) portion 152AB of the gate terminal (electrode) 152A of the TRX 152 is inserted above the N-type semiconductor region 216 .

[0247] The light shielding film 213 is formed between the PDs 151 (the N-type semiconductor region 216 and the P+ type semiconductor region 217) in adjacent pixels on the lower surface of the insulating film 214. The light shielding film 213 is arranged to extend, for example, in the column direction over a plurality of pixels between a plurality of columns of pixels adjacent in the row direction in the pixel array section 111. Furthermore, the light shielding film 213 is arranged to extend, for example, in the row direction over a plurality of pixels between a plurality of rows of pixels adjacent in the column direction in the pixel array section 111.

[0248] Furthermore, the upper surface and side surfaces of the PD 151 (N-type semiconductor region 216 and P+ type semiconductor region 217) are surrounded by a light shielding film 219. More specifically, the light shielding film 219 is composed of a horizontal light shielding portion 219A and a vertical light shielding portion 219B.

[0249] The horizontal light shielding portion 219A has a planar shape parallel to the light receiving surface of the solid-state image sensing device 101a. The horizontal light shielding portion 219A covers the top surfaces of the N-type semiconductor region 216 and the P+ type semiconductor region 217 constituting the PD 151 except for the opening 219C. In addition, the horizontal light shielding portion 219A is similar to the following reference Figure 75 The horizontal light shielding portion 804A of the tenth embodiment described above is also arranged over the entire area of the pixel array portion 111 except for the opening 219C in each pixel.

[0250] The vertical light shielding portion 219B has a wall shape perpendicular to the light receiving surface of the solid-state image sensing device 101a. The vertical light shielding portion 219B is formed to surround the side surfaces of the N-type semiconductor region 216 and the P+ type semiconductor region 217 constituting the PD 151. In addition, the vertical light shielding portion 219B is formed as shown in the following reference. Figure 74 The vertical light shielding portion 804B of the tenth embodiment is arranged to extend over a plurality of pixels between a plurality of columns of pixels adjacent in the row direction in the pixel array portion 111 in the column direction. Figure 74 The vertical light shielding portion 804B of the tenth embodiment is similarly arranged to extend in the row direction over a plurality of pixels between a plurality of rows of pixels adjacent in the column direction in the pixel array portion 111 .

[0251] The opening 219C is provided to insert the vertical terminal (electrode) portion 152AB of the gate terminal (electrode) 152A of the TRX 152 into the N− type semiconductor region 216 and transfer charges accumulated in the N− type semiconductor region 216 to the N+ type semiconductor region 231 .

[0252] Light that is not absorbed by the PD 151 and passes through the PD 151 is reflected by the horizontal light shielding portion 219A and is prevented from intruding into layers above the horizontal light shielding portion 219A. Thus, for example, charge generated by light passing through the PD 151 is prevented from intruding into the N+ type semiconductor region 231 constituting the MEM 154 or the N++ type semiconductor region 230 constituting the FD 156, thereby preventing the occurrence of noise. Furthermore, the vertical light shielding portion 219B prevents light incident from adjacent pixels from leaking into the PD 151, thereby preventing the occurrence of noise such as color mixing.

[0253] The light shielding film 213 limits oblique light incident on the PD 151 (N-type semiconductor region 216 ).

[0254] In addition, the opening 219C is desirably as small as possible to prevent the passage of light passing through the PD 151. In addition, the opening 219C is desirably arranged at the end of the pixel (near the vertical light shielding portion 219B) to prevent oblique light with a large incident angle from passing.

[0255] The light shielding films 213 and 219 are made of a material containing, for example, a specific metal, metal alloy, metal nitride, or metal silicide. The light shielding film 219 is made of, for example, tungsten (W), titanium (Ti), tantalum (Ta), nickel (Ni), molybdenum (Mo), chromium (Cr), iridium (Ir), platinum-iridium, titanium nitride (TiN), or a tungsten-silicon compound. The materials used to make the light shielding films 213 and 219 are not limited to these. For example, a substance other than metal having light shielding properties may be used.

[0256] The light shielding film 219 is covered by an insulating film 220. The insulating film 220 is made of, for example, a silicon oxide film (SiO). The insulating film 220 is covered by a P++ type semiconductor region 221. An N++ type semiconductor region 222 is formed between the insulating film 220 and the P++ type semiconductor region 221 on the lower surface of the horizontal light shielding portion 219A and around the vertical light shielding portion 219B. The N++ type semiconductor region 222 causes a gettering effect. A barrier film 223 is formed between the insulating film 220 and the P++ type semiconductor region 221 above the horizontal light shielding portion 219A. The barrier film 223 is made of, for example, a SiN film or a SiCN film.

[0257] The gate terminal (electrode) 152A of the TRX 152, the gate terminal (electrode) 153A of the TRM 153, the gate terminal (electrode) 155A of the TRG 155, and the gate terminal (electrode) 157A of the OFG 157 are formed on the upper surface of the P-type semiconductor region 224 in the second semiconductor substrate 202 via the insulating film 232. The gate terminals (electrodes) 153A, 155A, and 157A are arranged above the horizontal light shielding portion 219A, and the gate terminal (electrode) 152A is arranged above the opening 219C of the light shielding film 219.

[0258] In addition, the figure shows an example in which each device such as a transistor constituting a pixel in the solid-state image sensor device 101a is planar. With a planar structure, terminal electrodes can be formed on the same plane and the current path can be shortened.

[0259] The TRX 152 has a vertical gate structure, where the gate terminal (electrode) 152A consists of a horizontal terminal (electrode) portion 152AA and a vertical terminal (electrode) portion 152AB. Like the gate terminals (electrodes) of other transistors, the horizontal terminal (electrode) portion 152AA is formed on the upper surface of the P-type semiconductor region 224, parallel to the horizontal light shielding portion 219A, and via the insulating film 232. The vertical terminal (electrode) portion 152AB is perpendicular to the horizontal light shielding portion 219A and extends vertically downward from the horizontal terminal (electrode) portion 152AA. The vertical terminal (electrode) portion 152AB then passes through the second semiconductor substrate 202 from the side closer to the N+-type semiconductor region 231 (MEM 154) than to the horizontal light shielding portion 219A, and extends into the N-type semiconductor region 216 via the opening 219C in the light shielding film 219. Furthermore, the vertical terminal (electrode) portion 152AB is covered by the insulating film 232. Therefore, the gate terminal (electrode) 152A contacts the N-type semiconductor region 216 via the insulating film 232 .

[0260] In addition, although Figure 3 Although the example of gate terminal (electrode) 152A having a T-shaped cross section is shown, the shape of gate terminal (electrode) 152A is not limited to this example. For example, gate terminal (electrode) 152A may have an L-shaped cross section. Furthermore, gate terminal (electrode) 152A may have a ring-shaped or C-shaped shape when viewed from above to surround the channel.

[0261] In addition, although not shown, the gate terminal (electrode) of the RST 158 is formed between the P++ type semiconductor region 225 and the N++ type semiconductor region 226 on the upper surface of the P-type semiconductor region 224 via the insulating film 232. In addition, a side wall is formed on the side surface of each gate terminal (electrode).

[0262] In addition, a surface where a gate terminal (electrode) of each transistor constituting a pixel in the solid-state image sensing device 101 a and the like are formed (such as the upper surface of the P-type semiconductor region 224 ) will be hereinafter referred to as a device formation surface.

[0263] The P++ type semiconductor region 225, the N++ type semiconductor region 226, the N+ type semiconductor region 227, the P type semiconductor region 228, the N+ type semiconductor region 229 and the N++ type semiconductor region 230 are formed near the surface of the P- type semiconductor region 224 in the second semiconductor substrate 202 above the horizontal light shielding portion 219A.

[0264] The P++ type semiconductor region 225 is arranged on the left side of the gate terminal (electrode) of the RST 158 (not shown), thereby constituting a discharge cell.

[0265] The N++ type semiconductor region 226 is arranged on the left side of the gate terminal (electrode) 155A of the TRG 155 , thereby constituting the FD 156 .

[0266] The N+ type semiconductor region 227 is arranged on the left side of the gate terminal (electrode) 155A of the TRG 155 , and is adjacently arranged on the right side of the N++ type semiconductor region 226 .

[0267] The P-type semiconductor region 228 extends from the left side of the gate terminal (electrode) 155A of the TRG 155 to the right side of the gate terminal (electrode) 157A of the OFG 157. The P-type semiconductor region 228 surrounds the vertical terminal (electrode) portion 152AB of the TRX 152 except for the top end of the TRX 152 via the insulating film 232.

[0268] The N + -type semiconductor region 229 is arranged on the right side of the gate terminal (electrode) 157A of the OFG 157 .

[0269] The N++ type semiconductor region 230 is adjacently arranged on the right side of the N+ type semiconductor region 229, thereby constituting a discharge cell.

[0270] An N+ type semiconductor region 231 is formed within the P-type semiconductor region 228 above the horizontal light shielding portion 219A. The N+ type semiconductor region 231 extends from around the left end of the gate terminal (electrode) 155A to around the right end of the gate terminal (electrode) 153A. The horizontal light shielding portion 219A is arranged between the N+ type semiconductor region 231 and the upper surface (the surface opposite the light receiving surface) of the N-type semiconductor region. The N+ type semiconductor region 231 constitutes the HAD-type MEM 154.

[0271] A wiring layer, an interlayer insulating film, and the like are formed between the insulating film 232 and the logic layer 203 in the second semiconductor substrate 202 .

[0272] Each peripheral circuit in the solid-state image sensing device 101a is arranged on, for example, the second semiconductor substrate 202 or the logic layer 203. In the case where the peripheral circuit is formed on the second semiconductor substrate 202, each device constituting the peripheral circuit is formed in a mesa structure on, for example, the device formation surface of the second semiconductor substrate 202.

[0273] In addition, Figure 3 In the logic layer 203, only the wiring of the peripheral circuits that are rectangular and long in the horizontal direction are shown.

[0274] Here, the first semiconductor substrate 201 and the second semiconductor substrate 202 are applied to each other, and an active surface between the two substrates is assumed to be a bonding interface S in the solid-state image sensing device 101 a .

[0275] Figure 4 for Figure 3 152 is an enlarged view of the structure around TRX 152. The source terminal of TRX 152 is the portion of the N-type semiconductor region 216 that contacts the lower end of the vertical terminal (electrode) portion 152AB via the insulating film 232, and the drain terminal of TRX 152 is located immediately below the left end of the horizontal terminal (electrode) portion 152AA of the P-type semiconductor region 228. The channel of TRX 152 is then formed between the source terminal and the drain terminal of the gate terminal (electrode) 152A, and a bonding interface S is formed in the channel of TRX 152, as shown in FIG. Figure 4 shown.

[0276] Therefore, the bonding interface S is perpendicular to the direction of current flowing between the source and drain of the TRX 152. In addition, the bonding interface S can be set at any position in the vertical direction in the figure. Therefore, the distance between the bonding interface S and the drain terminal of the TRX 152 can be adjusted. In addition, the distance between the bonding interface S and the drain terminal of the TRX 152 can be made the same for all pixels in the solid-state image sensing device 101a.

[0277] Incidentally, a band gap is created at the bonding interface S, which tends to prevent charge transfer. Furthermore, the crystallographic direction changes around the bonding interface S, and grain boundaries appear. New lattice defects can form in the crystal at the grain boundaries, and the lattice defect concentration is higher around the grain boundaries. Consequently, the electric field is higher around the bonding interface S, and hot carriers are more likely to appear, which can easily lead to transistor performance degradation.

[0278] Figure 5 This figure illustrates the influence of grain boundaries on the bonding interface and their electrical characteristics, as well as the location of grain boundaries in a polysilicon thin-film transistor (TFT). As shown in the figure, the grain boundary is located between the drain and source electrodes.

[0279] Figure 6 This diagram illustrates potential barriers at locations within a polysilicon thin-film transistor (TFT) channel. The horizontal axis represents the location within the TFT channel, and the vertical axis represents the potential. Line L1 represents the potential depending on the location within the channel. Additionally, Pd on the horizontal axis represents the location of the drain terminal of the channel, and Ps represents the location of the source terminal of the channel.

[0280] If there is a position with a higher potential than the source terminal in the channel, then the charge cannot be transferred from the source to the drain. In addition, if the potential is high at any position in the channel, a trap is formed and the charge transfer performance is easily degraded.

[0281] like Figure 6 As shown in FIG, the potential of the source terminal of the channel is high, and the potential of the drain terminal is low. Therefore, when the bonding interface is formed in the TFT channel, it is desirable to form it near the drain terminal. This is because even if the bonding interface is formed near the drain terminal and the potential of the drain terminal is high, the potential is much lower than the potential of the source terminal and has little effect on the charge transfer performance. That is, when the bonding interface is formed in the TFT channel, the bonding interface is ideally formed near the drain terminal. Figure 6 In the dotted oval.

[0282] Figure 7 This diagram illustrates the electric field variation at various locations within a TFT channel. The horizontal axis represents the location within the TFT channel, and the vertical axis represents the electric field magnitude. Line L2 represents the electric field magnitude depending on the location within the channel. Additionally, Pd on the horizontal axis represents the location of the drain end of the channel, and Ps represents the location of the source end of the channel. As shown in the diagram, peaks P1 through P7 are formed along line L2.

[0283] like Figure 7 As shown, peak P1 is assumed to be high, and peaks P2 to P7 are assumed to be lower than peak P1. Specifically, when the junction interface is formed at the drain end (position Pd on the horizontal axis), the electric field in the channel is significantly higher at that location. In this way, when the electric field in the channel is significantly high, hot carriers appear, which has a negative impact on the device's lifespan and the resistance of the gate oxide film.

[0284] Therefore, when the bonding interface is formed in the TFT channel, it is desirable that the bonding interface is formed near the drain terminal (near the peak P3 in the figure) while avoiding the drain terminal (peak P1 in the figure). That is, when the bonding interface is formed in the TFT channel, the bonding interface is ideally formed near the drain terminal (near the peak P3 in the figure). Figure 7 In the dotted oval.

[0285] Therefore, the bonding interface S is formed near the drain terminal of the TRX 152 in the solid-state image sensing device 101a. The bonding interface S is formed substantially closer to the drain terminal of the TRX 152 than to the source terminal of the TRX 152.

[0286] Figure 8 This is a top view schematically illustrating an exemplary configuration of the device forming surface of the second semiconductor substrate 202 in the solid-state image sensing device 101a. The figure shows the region of one pixel in the solid-state image sensing device 101a. The dashed square in the figure indicates the location of the light-receiving surface of the PD 151 (the lower surface of the N-type semiconductor region 216). Furthermore, the dashed circle in the figure indicates the location of the vertical terminal (electrode) portion 152AB of the TRX 152.

[0287] The gate terminal (electrode) 152A of the TRX 152, the gate terminal (electrode) 153A of the TRM 153, the gate terminal (electrode) 155A of the TRG 155, and the gate terminal (electrode) 158A of the RST 158 are arranged in a row in the transverse direction in the figure. The gate terminal (electrode) 159A of the AMP 159 and the gate terminal (electrode) 160A of the SEL 160 are arranged in a row in the transverse direction in the figure, so as to oppose the row of gate terminals (electrodes) 152A, 153A, 155A, and 158A. The gate terminal (electrode) 152A of the TRX 152 and the gate terminal (electrode) 157A of the OFG 157 are arranged in a row in the longitudinal direction in the figure. Each gate terminal (electrode) is arranged on the upper surface of the P-type semiconductor region 228 via an insulating film 232 (not shown), and is connected in series via the N++-type semiconductor region 272 .

[0288] Drive signals TRX, TRM, TRG, OFG, RST, and SEL are applied to gate terminals (electrodes) 152A, 153A, 155A, 157A, 158A, and 160A via metal wiring, respectively. FD 156 and gate terminal (electrode) 159A are connected via metal wiring. Power supply voltage VDD is applied between gate terminal (electrode) 158A and gate terminal (electrode) 159A in N++ type semiconductor region 272 via metal wiring. In the figure, the right side of gate terminal (electrode) 160A in N++ type semiconductor region 272 is connected to vertical signal line VSL via metal wiring.

[0289] In addition, a P-well contact 271 is formed substantially at the center of the gate terminal (electrode) of each arranged transistor. The P-well contact 271 is connected to the ground via, for example, a metal wiring.

[0290] Figure 9 As an enlarged view, a cross section around the TRM 153 and the MEM 154 is schematically shown. Figure 9 Omitted Figure 3 Some of the components shown.

[0291] The TRM 153 has a planar structure, similar to each transistor in the pixel. Specifically, a P-type semiconductor region 228 is arranged below the gate terminal (electrode) 153A of the TRM 153 in the P-type semiconductor region 224 via an insulating film 232. The N+ type semiconductor region 231 constituting the MEM 154 is then formed in the P-type semiconductor region 228. Thus, the MEM 154 having a HAD structure is formed.

[0292] {Method of Manufacturing Solid-State Image Sensing Device 101a}

[0293] The following will refer to Figures 10 to 51 An exemplary method of manufacturing the solid-state image sensing device 101a is described. Figure 3 The corresponding part in Figures 10 to 51 Incidentally, in order to facilitate understanding of the drawings, reference numerals not related to the description are omitted as needed.

[0294] First, prepare the first semiconductor substrate 201, such as Figure 10 In this stage, an N-type semiconductor region 215 is formed on the first semiconductor substrate 201 .

[0295] A SiO2 film 301 is then formed on the surface of the first semiconductor substrate 201 by thermal oxidation or chemical vapor deposition (CVD), as shown in FIG. Figure 11 shown.

[0296] Then, P-type ions are implanted, and a P-type semiconductor region 218 is formed between the N-type semiconductor region 215 and the SiO2 film 301. Figure 12 shown.

[0297] A portion of the surface of the SiO2 film 301 is then masked by a photoresist 302, such as Figure 13 Then, N-type ions are implanted from the portion not masked by the photoresist 302 to generate an N-type semiconductor region 216 in the N-type semiconductor region 215. Thereafter, the photoresist 302 is removed.

[0298] A portion of the surface of the SiO2 film 301 is then masked by a photoresist 303, as shown in FIG. Figure 14In a later step, the opening 219C of the light shielding film 219 and the vertical terminal (electrode) portion 152AB of the TRX 152 are formed at a position masked by the photoresist 303 .

[0299] The portion of the P-type semiconductor region 218 not masked by the photoresist 303 is then removed by dry etching down to a predetermined depth, such as Figure 15 shown.

[0300] Then remove the SiO2 film 301 and the photoresist 303, as shown in FIG. Figure 16 shown.

[0301] A SiO film 304 is then formed on the surface of the first semiconductor substrate 201 (the P-type semiconductor region 218), as shown in FIG. Figure 17 shown.

[0302] The SiO film 304 is then patterned, and an opening 304A is formed in the SiO film 304, as shown in FIG. Figure 18 The opening 304A is formed to surround the side surface of the N-type semiconductor region 216 in each pixel, for example.

[0303] The trench 201A is then formed below the opening 304A of the SiO film 304 by dry etching, as shown in FIG. Figure 19 The trench 201A passes through the P-type semiconductor region 218 and reaches a position lower than the lower end of the N-type semiconductor region 216 in the N-type semiconductor region 215. In addition, the trench 201A is formed between the N-type semiconductor regions 216 in adjacent pixels.

[0304] Then, the SiO film 304 is completely removed, as shown in FIG. Figure 20 shown.

[0305] An insulating film 220 made of SiO is then formed on the surface of the first semiconductor substrate 201 by, for example, oxidation, as shown in FIG. Figure 21 Not only the surface of the P-type semiconductor region 218 but also the inner wall of the trench 201A is covered with the insulating film 220 .

[0306] A portion of the surface of the first semiconductor substrate 201 is then masked by a photoresist 305, such as Figure 22 As shown. Furthermore, the inner side of trench 201A is also masked with photoresist 306. P+ ions are then implanted from the portion not masked by photoresist 305, and P+ semiconductor region 217 is formed above N-type semiconductor region 216 within P-type semiconductor region 218. Thereafter, photoresist 305 is removed.

[0307] A portion of the top of the protrusion of the P-type semiconductor region 218 in the surface of the first semiconductor substrate 201 is then masked by a photoresist 306, as shown in FIG. Figure 23 As shown. P++-type ions are then implanted from the portion not masked by the photoresist 306, creating a P++-type semiconductor region 221 beneath the insulating film 220. Specifically, the portion below the insulating film 220, except for the upper surface of the protruding portion of the P-type semiconductor region 218, is covered by the P++-type semiconductor region 221. Thereafter, the photoresist 306 is removed.

[0308] Here, the P++-type semiconductor region 221 surrounding the trench 201A is formed by obliquely implanting P++ ions into the trench 201A. Consequently, the thickness of the P++-type semiconductor region 221 is substantially uniform, horizontally uniform around the trench 201A. Consequently, the N-type semiconductor region 216, whose side surfaces are surrounded by the P++-type semiconductor region 221 and constitute the PD 151, can be made wider horizontally, increasing the area of its light-receiving surface. Consequently, the sensitivity of the pixel is improved. Furthermore, the substantially uniform thickness of the P++-type semiconductor region 221 eliminates the formation of potential wells and facilitates surface pinning design.

[0309] On the other hand, for example, if the P++-type semiconductor region 221 is formed by ion implantation from the surface of the first semiconductor substrate 201 without forming the trench 201A, the thickness of the P++-type semiconductor region 221 is non-uniform in the horizontal direction and is wider at deeper locations. As a result, the N-type semiconductor region 216 constituting the PD 151 is narrower in the horizontal direction, and its light-receiving surface area is smaller. Consequently, the sensitivity of the pixel is reduced. Furthermore, the non-uniform thickness of the P++-type semiconductor region 221 creates a potential well, which causes charge transfer failure and makes surface pinning design more difficult.

[0310] The protrusions of the P-type semiconductor region 218 in the surface of the first semiconductor substrate 201 are then masked by a photoresist 307, as shown in FIG. Figure 24 Then, N++ type ions and carbon (C) ions are implanted from the portion not masked by the photoresist 307. Thus, an N++ type semiconductor region 222 is generated between the insulating film 220 and the P++ type semiconductor region 221. Thereafter, the photoresist 307 is removed.

[0311] A light shielding film 219 is then formed on the surface of the first semiconductor substrate 201 by CVD, as shown in FIG. Figure 25 The light shielding film 219 is also embedded in the trench 201A and forms a vertical light shielding portion 219B.

[0312] The portion other than the periphery of the protrusion of the P-type semiconductor region 218 in the surface of the first semiconductor substrate 201 is then masked by a photoresist 308, as shown in FIG. Figure 26 As shown. Then, the light shielding film 219 at the portion not masked by the photoresist 308 is removed by dry etching. Thus, the horizontal light shielding portion 219A and the opening 219C are formed in the light shielding film 219. Thereafter, the photoresist 308 is removed.

[0313] A SiO film is then formed on the surface of the first semiconductor substrate 201 by CVD, as shown in FIG. Figure 27 As shown. The SiO film is Figure 21 The insulating film 220 is formed by combining with the SiO film formed in the step 110 .

[0314] A barrier film 223 is then formed on the surface of the first semiconductor substrate 201, as shown in FIG. Figure 28 shown.

[0315] A SiO film 309 is then formed on the surface of the barrier film 223 by CVD, as shown in FIG. Figure 29 shown.

[0316] The surface of the first semiconductor substrate 201 is then planarized by chemical mechanical polishing (CMP). Figure 30 As shown. Thus, the surface of the P-type semiconductor region 218 is exposed. At this time, the barrier film 223 prevents the SiO film 309 from being over-polished. In addition, although Figure 30 Although not shown in the figure, the SiO film 309 remains on the surface of the barrier film 223 as a part of the insulating film 220 .

[0317] A silicon film 310 is then formed on the surface of the first semiconductor substrate 201 by epitaxial growth, as shown in FIG. Figure 31 At this time, the single crystal silicon 310A is epitaxially grown only on the P-type semiconductor region 218 and the P++ type semiconductor region 221, and the polycrystalline silicon 310B is formed in the other portions.

[0318] In addition, the silicon film 310 can be formed by a method other than epitaxial growth, for example. In addition, for example, amorphous silicon can be formed instead of polysilicon 310B. In addition, for example, silicon can be directly bonded to other silicon without epitaxial growth.

[0319] The surface of the silicon film 310 is then polished by CMP, as shown in FIG. Figure 32 shown.

[0320] Then, P-type ions and P++ type ions are implanted into the silicon film 310, as shown in FIG. Figure 33Specifically, P-type ions are implanted above the P-type semiconductor region 218 in the silicon film 310, and P++ type ions are implanted in the remaining portions. As a result, the P++ type semiconductor region 221 extends to the surface of the second semiconductor substrate 202. Furthermore, the P-type semiconductor region 218 extends to the surface of the first semiconductor substrate 201.

[0321] The second semiconductor substrate 202 is then applied to the upper surface of the first semiconductor substrate 201, as Figure 34 In this step, it is assumed that the surfaces on which the first semiconductor substrate 201 and the second semiconductor substrate 202 are applied are the bonding interface S.

[0322] Here, the second semiconductor substrate 202 employs, for example, a P-type single-crystal silicon substrate having a Si (111) crystal orientation. The mobility in the channel is higher in the case of a (111) crystal orientation than in the case of a (100) plane, for example. Therefore, when charges are transferred from the PD 151 to the MEM 154, the transfer characteristics are enhanced. Furthermore, the crystal orientation is not limited to (111), and bonding can be performed in any orientation.

[0323] In addition, the method of applying the first semiconductor substrate 201 and the second semiconductor substrate 202 is not particularly limited, and for example, a technique for applying a silicon-on-insulator (SOI) substrate can be adopted. For example, a method such as plasma bonding, direct bonding using van der Waals bonding, bonding in a vacuum atmosphere, and a thermal annealing treatment after the bonding can be adopted.

[0324] In addition, the surface treatment method before applying the first semiconductor substrate 201 and the second semiconductor substrate 202 is not particularly limited, and hydrophilic or hydrophobic treatment is performed to reduce voids on the bonding interface S and improve bonding strength.

[0325] For example, the following methods can be used: immersing the respective surfaces of the first semiconductor substrate 201 and the second semiconductor substrate 202 in a hydrofluoric acid solution, drying, and then bonding; immersing the respective surfaces of the first semiconductor substrate 201 and the second semiconductor substrate 202 in a solution of ammonia and hydrogen peroxide, drying, and then bonding; immersing the respective surfaces of the first semiconductor substrate 201 and the second semiconductor substrate 202 in a solution of hydrochloric acid or sulfuric acid and hydrogen peroxide, drying, and then bonding; irradiating the respective surfaces of the first semiconductor substrate 201 and the second semiconductor substrate 202 with plasma under vacuum, and then bonding; or irradiating the respective surfaces of the first semiconductor substrate 201 and the second semiconductor substrate 202 with plasma under an ammonium or hydrogen atmosphere, and then bonding.

[0326] In addition, the inner side of the second semiconductor substrate 202 may be a SOI substrate in advance so that when polishing is performed later, the thickness of the second semiconductor substrate 202 can be adjusted. For example, the second semiconductor substrate 202 is made of an SOI substrate to prevent the second semiconductor substrate 202 from being over-polished.

[0327] Then, a thermal annealing treatment is performed, such as Figure 35 As shown in FIG. As a result, the tightness of the bonding interface S between the first semiconductor substrate 201 and the second semiconductor substrate 202 is enhanced. Furthermore, the P+ type impurities diffuse into the P++ type semiconductor region 221 to form a pinning layer. Furthermore, the N++ type semiconductor region 222 acts as a gettering layer, and the crystallinity of the HAD structure formed by the N-type semiconductor region 216 and the P+ type semiconductor region 217 is enhanced.

[0328] The surface of the second semiconductor substrate 202 (the surface of the P-type semiconductor region 224) is then polished by CMP, as shown in FIG. Figure 36 shown.

[0329] A SiO film 311 is then formed on the surface of the second semiconductor substrate 202, as shown in FIG. Figure 37 shown.

[0330] Then, P-type ions are implanted to form a P-type semiconductor region 228, as shown in FIG. Figure 38 As shown. Furthermore, N+ type ions are implanted to generate an N+ type semiconductor region 231 in the P-type semiconductor region 228. MEM 154 is formed by N+ type semiconductor region 231. Furthermore, the charge transfer path from N- type semiconductor region 216 (PD 151) to N+ type semiconductor region 231 (MEM 154) and the channel of each transistor are formed by P-type semiconductor region 228.

[0331] The SiO film 311 is then patterned as Figure 39 That is, the opening 311A is formed at the portion where the vertical terminal (electrode) portion 152AB of the TRX 152 is formed in the SiO film 311 .

[0332] A trench 312 is then formed below the opening 311A of the SiO film 311 by dry etching, as shown in FIG. Figure 40 The trench 312 penetrates the second semiconductor substrate 202 , passes through the opening 219C of the light shielding film 219 , and reaches the inside of the N-type semiconductor region 216 .

[0333] Then the SiO film 311 is removed, as shown in FIG. Figure 41 shown.

[0334] The surface of the second semiconductor substrate 202 and the trench 312 are then oxidized to form an insulating film 232, such as Figure 42shown.

[0335] Polysilicon is then formed on the surface of the second semiconductor substrate 202 and inside the trench 312 by CVD, as shown in FIG. Figure 43 Then, P++ type ions are implanted into the formed polysilicon, thereby forming a P++ type silicon film 313.

[0336] The P++ type silicon film 313 is then processed by dry etching and generates the gate terminal (electrode) of each transistor, as shown in FIG. Figure 44 shown. Figure 44 It is shown how the gate terminal (electrode) 152A of the TRX 152, the gate terminal (electrode) 153A of the TRM 153, the gate terminal (electrode) 155A of the TRG 155, and the gate terminal (electrode) 157A of the OFG 157 are generated.

[0337] Then generate a lightly doped drain (LDD), such as Figure 45 Specifically, N+ type ions are implanted and an N+ type semiconductor region 227 is generated on the left side of the gate terminal (electrode) 155A and around the boundary between the P- type semiconductor region 224 and the P-type semiconductor region 228. In addition, N+ type ions are implanted and an N+ type semiconductor region 229 is generated on the right side of the gate terminal (electrode) 157A and inside the P-type semiconductor region 228.

[0338] Sidewalls are then formed on the side surfaces of the gate terminal (electrode) of each transistor, as Figure 46 shown.

[0339] Then N++ type ions and P++ type ions are injected, such as Figure 47 As shown in FIG. As a result, an N++ type semiconductor region 226 constituting FD 156 is generated on the left side of N+ type semiconductor region 227. Furthermore, an N++ type semiconductor region 230 constituting a discharge cell is generated on the right side of N+ type semiconductor region 229. Furthermore, a P++ type semiconductor region 225 constituting a discharge cell is generated near the left end of the figure in P- type semiconductor region 224.

[0340] An interlayer insulating film and a wiring layer are then formed on the upper layer of the device formation surface of the second semiconductor substrate 202, as shown in FIG. Figure 48 shown.

[0341] The logic layer 203 is then applied to the upper surface of the second semiconductor substrate 202, as shown Figure 49 In addition, the method of bonding the second semiconductor substrate 202 and the logic layer 203 can adopt the method described in Japanese Patent Application Laid-Open No. 2012-204810, for example.

[0342] The lower surface of the first semiconductor substrate 201 is then polished and planarized by CMP. Figure 50 shown.

[0343] The lower surface of the first semiconductor substrate 201 is then processed to complete the solid-state image sensing device 101a, as shown in FIG. Figure 51 As shown. Specifically, an insulating film 214 is formed on the lower surface of the first semiconductor substrate 201. In addition, a light shielding film 213 is formed between the PDs 151 in adjacent pixels (N-type semiconductor region 216 and P+ type semiconductor region 217) on the lower surface of the insulating film 214. The light shielding film 213 is formed so as to block the vertical light shielding portion 219B, the insulating film 220, the N++ type semiconductor region 22, and the P++ type semiconductor region 221 from the lower surface of the insulating film 214.

[0344] Furthermore, a planarization film 212 is generated on the lower surface of the insulating film 214. Furthermore, a microlens 211 and the like are formed on the lower surface of the planarization film 212 and the solid-state image sensing device 101a is completed.

[0345] As described above, in the solid-state image sensing device 101 a , light is shielded between pixels by the vertical light shielding portion 219B, so that light leaked from adjacent pixels is prevented from entering the PD 151 and noise such as color mixture is prevented from occurring.

[0346] Furthermore, light that is not absorbed by PD 151 and passes through PD 151 is blocked by horizontal light shielding portion 219A and prevented from intruding into layers above horizontal light shielding portion 219A. Thus, charge generated by light passing through PD 151 is prevented from intruding into MEM 154 or FD 156, preventing the occurrence of noise. The longer the charge is accumulated in MEM 154 or FD 156, the greater the effect.

[0347] Furthermore, the horizontal light shielding portion 219A prevents an electric field occurring in a transistor constituting each pixel from affecting the PD 151. That is, dark current due to the electric field of each transistor is prevented from flowing into the PD 151, and noise is prevented from occurring.

[0348] In addition, in the solid-state image sensing device 101a, the bonding interface S between the first semiconductor substrate 201 and the second semiconductor substrate 202 can be arranged at any position in the channel of the TRX 152 of all pixels. Moreover, in an image sensor having hundreds of thousands or more pixels, the bonding interface S can be arranged at the same position in the channel of the TRX 152 of all pixels. In addition, the bonding interface does not need to be formed inside the PD 151, inside the MEM 154, inside the FD 156, or inside the transistors other than the TRX 152.

[0349] Furthermore, the bonding interface S can be formed near the drain end of the channel of the TRX 152 in the solid-state image sensing device 101a. Thus, degradation of charge transfer performance is limited, and the lifetime of the device or the resistance of the gate oxide film can be improved.

[0350] Furthermore, parasitic resistance is generated in the bonding interface S, and this parasitic resistance becomes a cause of leakage current. Figure 2 The parasitic resistance Rp in φ152 is represented, and a leakage current is caused in the TRX 152 due to the parasitic resistance Rp.

[0351] Here, when TRX 152 is disconnected, current does not flow into parasitic resistance Rp, and noise does not occur. On the other hand, when TRX 152 is turned on, noise due to parasitic resistance Rp may appear in the signal through the charge transferred from PD 151 to MEM 154. However, if the channel of TRX 152 is configured as a HAD structure or the switching speed of TRX 152 is further increased, the signal transferred from PD 151 to MEM 154 will be large enough to withstand the noise caused by parasitic resistance Rp. Therefore, solutions such as improving the channel structure or switching speed of TRX 152 can sufficiently reduce the influence of noise due to leakage current.

[0352] Furthermore, in the solid-state image sensing device 101a, each transistor, MEM 154, and FD 156 constituting each pixel are formed on the second semiconductor substrate 202, which is a single-crystal substrate. Therefore, excellent IV characteristics compatible with fine pixel signals can be obtained, thereby limiting performance variations per pixel.

[0353] <2. Second embodiment>

[0354] The following will refer to Figure 52 A second embodiment of the present technology will be described.

[0355] Figure 52 is a cross-sectional view schematically showing an exemplary configuration of a solid-state image sensing device 101b according to a second embodiment of the present technology. Figure 3 The corresponding parts in the figure are represented by the same figure marks, and their descriptions are omitted as needed.

[0356] Figure 52 The solid-state image sensing device 101b and Figure 3 The solid-state image sensing device 101a in FIG. 1 is different in that the blocking film 223 is deleted and the insulating film 220 is formed at the deleted portion instead.

[0357] As above Figure 30As described above, the barrier film 223 is only used to prevent the solid-state image sensing device 101a from being over-polished during manufacturing and does not play any special role after manufacturing. Therefore, the barrier film 223 can be deleted in the solid-state image sensing device 101b.

[0358] <3. Third embodiment>

[0359] The following will refer to Figure 53 A third embodiment of the present technology will be described.

[0360] Figure 53 is a cross-sectional view schematically showing an exemplary configuration of a solid-state image sensing device 101c according to a third embodiment of the present technology. Figure 52 The corresponding parts in the figure are represented by the same figure marks, and their descriptions are omitted as needed.

[0361] Figure 53 The solid-state image sensing device 101c and Figure 52 The difference between the solid-state image sensing device 101b in FIG. 1 is that the light shielding film 213 on the light-receiving surface side of the first semiconductor substrate 201 and the vertical light shielding portion 219B of the light shielding film 219 are connected via the light shielding film 401. The light shielding film 401, like the vertical light shielding portion 219B, is arranged to extend in the column direction over a plurality of pixels between a plurality of columns of pixels adjacent in the row direction in the pixel array portion 111. Furthermore, like the vertical light shielding portion 219B, the light shielding film 401 is arranged to extend in the row direction over a plurality of pixels between a plurality of rows of pixels adjacent in the column direction in the pixel array portion 111. Thus, the light shielding performance between adjacent pixels is enhanced, and color mixing is prevented.

[0362] In addition, the light shielding film 401 is made of, for example, the same material as that of the light shielding film 219 .

[0363] In addition, the light shielding film 401 is formed by Figure 51 The insulating film 214 is formed in the step of forming the insulating film 214, and then the lower surface of the first semiconductor substrate 201 is patterned to form a groove by etching and a metal film is embedded in the formed groove.

[0364] That is, the light-shielding film 401 is formed by the light-receiving surface side of the N-type semiconductor region 216 constituting the PD 151, and the vertical light-shielding portion 219B is formed by the upper surface side of the N-type semiconductor region 216, and the light-receiving surface side of the N-type semiconductor region 216 and the upper surface side of the N-type semiconductor region 216 are finally bonded.

[0365] <4. Fourth embodiment>

[0366] The following will refer to Figure 54 A fourth embodiment of the present technology will be described.

[0367] Figure 54 is a cross-sectional view schematically showing an exemplary configuration of a solid-state image sensing device 101d according to a fourth embodiment of the present technology. Figure 53 The corresponding parts in the figure are represented by the same figure marks, and their descriptions are omitted as needed.

[0368] Figure 54 The solid-state image sensing device 101d and Figure 53 The solid-state image sensing device 101c shown in FIG. 1 is different in that a light shielding film 411 is formed. The light shielding film 411 is formed to cover at least the upper surface (the surface opposite to the surface opposing the horizontal light shielding portion 219A) of the N+-type semiconductor region 231 constituting the MEM 154 in the wiring layer of the second semiconductor substrate 202 (farther from the horizontal light shielding portion 219A than the device forming surface of the second semiconductor substrate 202). Alternatively, for example, the light shielding film 411 may be formed to completely cover the second semiconductor substrate 202.

[0369] The light shielding film 411 prevents light emitted when the transistors in the logic layer 203 are operating, for example, from entering the device forming surface of the second semiconductor substrate 202. This prevents light from the transistors in the logic layer 203 from entering the P-type semiconductor region 228, preventing the generation of charge, preventing the generated charge from being mixed into the N+-type semiconductor region 231, and preventing the occurrence of noise. Furthermore, noise due to the electric field caused by the logic layer 203 can be prevented.

[0370] <5. Fifth embodiment>

[0371] The following will refer to Figure 55 A fifth embodiment of the present technology will be described.

[0372] Figure 55 is a cross-sectional view schematically showing an exemplary configuration of a solid-state image sensing device 101e according to a fifth embodiment of the present technology. Figure 52 The corresponding parts in the figure are represented by the same figure marks, and their descriptions are omitted as needed.

[0373] Figure 55 The solid-state image sensing device 101e and Figure 52 The solid-state image sensing device 101b in FIG. 1 is different in that the light shielding film 219 is composed of only the horizontal light shielding portion 219A and no vertical light shielding portion 219B is formed. An insulating film 220 is formed at a portion of the solid-state image sensing device 101b corresponding to the vertical light shielding portion 219B.

[0374] Since there is no vertical light shielding portion 219B, the solid-state image sensing device 101e has lower light shielding performance between adjacent pixels than the solid-state image sensing device 101b. However, light incident on adjacent pixels can be sufficiently shielded by the insulating film 220, thereby limiting the occurrence of noise such as color mixing.

[0375] <6. Sixth embodiment>

[0376] The following will refer to Figure 56 and Figure 57 A sixth embodiment of the present technology will be described.

[0377] The sixth embodiment differs from the above-described first embodiment and the like in that the configuration of the cross section of the pixel is different.

[0378] {Exemplary Configuration of Solid-State Image Sensing Device 101f}

[0379] Figure 56 is a cross-sectional view schematically showing an exemplary configuration of a solid-state image sensing device 101f according to a sixth embodiment of the present technology. Figure 3 The corresponding parts in the figure are represented by the same figure marks, and their descriptions are omitted as needed.

[0380] The insulating film 214, the planarizing film 212, and the microlens 211 are stacked on the lower surface of the N-type semiconductor region 451 in the first semiconductor substrate 201. The P+ type semiconductor region 452 is formed on the N-type semiconductor region 451. The PD 151 is composed of the N-type semiconductor region 451 and the P+ type semiconductor region 452.

[0381] Light incident in the light receiving surface of the solid-state image sensing device 101 f is photoelectrically converted by the PD 151 , and charges generated by the photoelectric conversion are accumulated in the N-type semiconductor region 451 .

[0382] The light shielding film 213 is formed between the PDs 151 (the N − type semiconductor region 451 and the P + type semiconductor region 452 ) in adjacent pixels on the lower surface of the insulating film 214 .

[0383] Furthermore, the upper surface and the side surface of the PD 151 (the N-type semiconductor region 451 and the P+ type semiconductor region 452) are surrounded by a light shielding film 453. The light shielding film 453 is made of, for example, Figure 3 The light shielding film 453 is made of the same material as the light shielding film 219. In addition, the light shielding film 453 is composed of a horizontal light shielding portion 453A and a vertical light shielding portion 453B.

[0384] The horizontal light shielding portion 453A has a planar shape parallel to the light receiving surface of the solid-state image sensing device 101f. The horizontal light shielding portion 453A covers the upper surfaces of the N-type semiconductor region 451 and the P+ type semiconductor region 452 constituting the PD 151 except for the opening 453C. In addition, the horizontal light shielding portion 453A is similar to the following reference Figure 75 The horizontal light shielding portion 453A of the tenth embodiment described above is also arranged over the entire area of the pixel array portion 111 except for the opening 453C in each pixel.

[0385] The vertical light shielding portion 453B has a wall shape perpendicular to the light receiving surface of the solid-state image sensing device 101f. The vertical light shielding portion 453B is formed so as to surround the side surfaces of the N-type semiconductor region 451 and the P+ type semiconductor region 452 constituting the PD 151. In addition, the vertical light shielding portion 453B is formed as shown in the following reference. Figure 74 The vertical light shielding portion 804B of the tenth embodiment is arranged to extend over a plurality of pixels between a plurality of columns of pixels adjacent in the row direction in the pixel array portion 111 in the column direction. Figure 74 The vertical light shielding portion 804B of the tenth embodiment is similarly arranged to extend in the row direction over a plurality of pixels between a plurality of rows of pixels adjacent in the column direction in the pixel array portion 111 .

[0386] The opening 453C is provided to insert the vertical terminal (electrode) portion 152AB of the gate terminal (electrode) 152A of the TRX 152 into the N− type semiconductor region 451 and to transfer charges accumulated in the N− type semiconductor region 451 to the N+ type semiconductor region 468 .

[0387] Light that is not absorbed by the PD 151 and passes through the PD 151 is reflected by the horizontal light shielding portion 453A and is prevented from intruding into a surface above the horizontal light shielding portion 453A. Thus, for example, charge generated by light passing through the PD 151 is prevented from intruding into the N+ type semiconductor region 468 constituting the MEM 154 or the N++ type semiconductor region 462 constituting the FD 156, thereby preventing the occurrence of noise. Furthermore, the vertical light shielding portion 453B prevents light incident from adjacent pixels from leaking into the PD 151, thereby preventing the occurrence of noise such as color mixing.

[0388] The opening 453C is desirably as small as possible so that light passing through the PD 151 does not pass through. The opening 453C is desirably arranged at the end of the pixel (near the vertical light shielding portion 453B) to prevent oblique light with a large incident angle from passing through.

[0389] The light shielding film 453 is covered by an insulating film 454. The insulating film 454 is made of, for example, a silicon oxide film (SiO). The insulating film 454 is covered by a P++ type semiconductor region 455. An N++ type semiconductor region 456 is formed between the insulating film 454 and the P++ type semiconductor region 455 below the horizontal light shielding portion 453A and around the vertical light shielding portion 453B. The N++ type semiconductor region 456 causes a gettering effect. A barrier film 457 is formed between the insulating film 454 and the P++ type semiconductor region 455 above the horizontal light shielding portion 453A. The barrier film 457 is made of, for example, a SiN film or a SiCN film.

[0390] The gate terminal (electrode) 152A of the TRX 152, the gate terminal (electrode) 153A of the TRM 153, the gate terminal (electrode) 155A of the TRG 155, the gate terminal (electrode) 157A of the OFG 157, and the gate terminal (electrode) 158A of the RST 158 are formed on the device formation surface of the second semiconductor substrate 202 via the insulating film 469. The gate terminals (electrodes) 153A, 155A, 157A, and 158A are arranged above the horizontal light shielding portion 453A, and the gate terminal (electrode) 152A is arranged above the opening 453C of the light shielding film 453.

[0391] The gate terminal (electrode) 152A of the TRX 152 is composed of a horizontal terminal (electrode) portion 152AA and a vertical terminal (electrode) portion 152AB. Like the gate terminals (electrodes) of other transistors, the horizontal terminal (electrode) portion 152AA is formed on the device forming surface of the second semiconductor substrate 202 via an insulating film 469. The vertical terminal (electrode) portion 152AB extends vertically downward from the horizontal terminal (electrode) portion 152AA, passes through the second semiconductor substrate 202, and extends into the N-type semiconductor region 451 via an opening 453C in the light shielding film 453. Furthermore, the vertical terminal (electrode) portion 152AB is covered by the insulating film 469. Therefore, the gate terminal (electrode) 152A contacts the N-type semiconductor region 451 via the insulating film 469.

[0392] N++ type semiconductor region 459, N+ type semiconductor region 460, N+ type semiconductor region 461, N++ type semiconductor region 462, N+ type semiconductor region 463, P-- type semiconductor region 464, P- type semiconductor region 465, N+ type semiconductor region 466 and N++ type semiconductor region 467 are formed around the surface of the P- type semiconductor region 458 in the second semiconductor substrate 202 above the horizontal light shielding portion 453A.

[0393] The P-type semiconductor region 458 is arranged at least from around the right end of the horizontal terminal (electrode) portion 152AA of the TRX 152 to around the right end of the gate terminal (electrode) 155A of the TRG 155. Therefore, the P-type semiconductor region 458 is arranged at least directly below the gate terminal (electrode) 153A of the TRM 153 and directly below the gate terminal (electrode) 155A of the TRG 155.

[0394] The N++ type semiconductor region 459 is arranged on the right side of the gate terminal (electrode) 158A of the RST 158, thereby constituting a discharge cell.

[0395] The N+ type semiconductor region 460 is arranged on the right side of the gate terminal (electrode) 158A of the RST 158 and adjacently on the left side of the N++ type semiconductor region 459 .

[0396] The N + -type semiconductor region 461 is arranged on the left side of the gate terminal (electrode) 158A of the RST 158 .

[0397] The N++-type semiconductor region 462 is adjacently arranged on the left side of the N+-type semiconductor region 461 , thereby constituting the FD 156 .

[0398] The N + type semiconductor region 463 is arranged on the right side of the gate terminal (electrode) 155A of the TRG 155 and adjacently on the left side of the N ++ type semiconductor region 462 .

[0399] The P-type semiconductor region 464 is arranged directly below the gate terminal (electrode) 152A of the TRX 152. The P-type semiconductor region 464 surrounds the vertical terminal (electrode) portion 152AB of the TRX 152 except for the top end thereof via the insulating film 469.

[0400] The P-type semiconductor region 465 is arranged from around the left side of the gate terminal (electrode) 152A to around the right end of the gate terminal (electrode) 157A.

[0401] The N + -type semiconductor region 466 is arranged on the left side of the gate terminal (electrode) 157A and adjacently arranged on the left side of the P − -type semiconductor region 465 .

[0402] The N++ type semiconductor region 467 is adjacently arranged on the left side of the N+ type semiconductor region 466, thereby constituting a discharge cell.

[0403] N+ type semiconductor region 468 is formed inside P type semiconductor region 458 above horizontal light shielding portion 453A. N+ type semiconductor region 468 extends from around the left end of gate terminal (electrode) 155A to around the left end of gate terminal (electrode) 153A. N+ type semiconductor region 468 constitutes HAD type MEM 154.

[0404] {Example of How to Drive the Solid-State Image Sensing Device 101f}

[0405] The following will refer to Figure 57 The potential diagram in exemplifies how to drive the solid-state image sensing device 101f.

[0406] First, TRX 152 and OFG 157 are turned on, and TRM 153, TRG 155, and RST 158 are turned off. The charge accumulated in PD 151 (N-type semiconductor region 451) is then transferred to N++ type semiconductor region 467 as a discharge unit via TRX 152 and OFG 157 to be discharged to the outside. Thus, PD 151 is reset.

[0407] Then, TRX 152 and OFG 157 are turned off, and TRG 155 and RST 158 are turned on. The charges accumulated in MEM 154 (N+ type semiconductor region 468) and FD 156 (N++ type semiconductor region 462) are then transferred to N++ type semiconductor region 459 as a discharge unit via TRG 155 and RST 158 to be discharged to the outside. Thus, MEM 154 and FD 156 are reset.

[0408] Then, TRG 155 and RST 158 are disconnected, and the exposure time begins. During the exposure time, PD 151 (N-type semiconductor region 451) generates and accumulates charge based on the amount of received light. Here, the potential difference due to the difference in impurity concentration is between P-type semiconductor region 458 and P-type semiconductor region 465. Therefore, when TRX 152, TRM 153, and OFG 157 are disconnected, the potential of the OFG 157 channel is slightly lower than the potential of the TRM 153 channel, which is closer to TRX 152. As a result, an overflow path is formed between PD 151 (N-type semiconductor region 451) and N++ type semiconductor region 467, which serves as a discharge cell. Therefore, charge overflowing from PD 151 (N-type semiconductor region 451) is discharged to N++ type semiconductor region 467 via the overflow path without leaking into MEM 154 (N+ type semiconductor region 468).

[0409] Then, TRX 152 and TRM 153 are turned on, and the exposure time ends. Here, the potential difference due to the difference in impurity concentration is between the P-type semiconductor region 464 and the N+ type semiconductor region 468. Therefore, when TRX 152 and TRM 153 are turned on, the potential of the channel of TRM 153 is lower than the potential of the channel of TRX 152. Thus, the charge accumulated in PD 151 (N-type semiconductor region 451) during the exposure time is transferred to MEM 154 (N+ type semiconductor region 468) via TRX 152 and TRM 153 and is retained in MEM 154 (N+ type semiconductor region 468).

[0410] Then, TRX 152 and TRM 153 are turned off, and TRG 155 is turned on. As a result, the charge held in MEM 154 (N+ type semiconductor region 468) is transferred to FD 156 (N++ type semiconductor region 462) via TRM 153 and TRG 155. The potential of FD 156 is then output as a signal level to vertical signal line VSL via AMP 159 and SEL 160.

[0411] In addition, the solid-state image sensing device 101f can generate Figure 3 The same effect is achieved by the solid-state image sensing device 101a in FIG.

[0412] <7. Seventh embodiment>

[0413] The following will refer to Figures 58 to 63 A seventh embodiment of the present technology will be described.

[0414] Although the solid-state image sensing device 101a in which each device (such as a transistor) constituting a pixel is of a planar structure has been described, the seventh embodiment will be described assuming that each device is of a mesa structure.

[0415] Figure 58 1 is a top view schematically showing an exemplary configuration of a device forming surface of the second semiconductor substrate 202 in the solid-state image sensing device 101g according to the seventh embodiment of the present technology. Figure 8 The corresponding parts in the figure are indicated by the same reference numerals.

[0416] Figure 58The arrangement of each device in the solid-state image sensing device 101g is similar to that of each device in the solid-state image sensing device 101a. Incidentally, the TRX 152, TRM 153, TRG 155, OFG 157, RST 158, AMP 159, and SEL 160 are each composed of a mesa transistor. In addition, each device has a mesa structure, so the horizontal light shielding portion 501A of the light shielding film 501 corresponding to the light shielding film 219 in the solid-state image sensing device 101a is connected via the insulating film 502 ( Figure 59 etc.) are formed around the surface of the device formation surface of the second semiconductor substrate 202.

[0417] Figure 59 is a cross-sectional view schematically illustrating an exemplary configuration of the TRM 153 and the MEM 154. A P+-type semiconductor region 512 is formed on an insulating film 502 formed on the device forming surface of the second semiconductor substrate 202. An N-type semiconductor region 511 constituting the MEM 154 is then formed within the P+-type semiconductor region 512. The N-type semiconductor region 511 is covered by the P+-type semiconductor region 512, thereby forming the HAD-type MEM 154. The upper and side surfaces of the P+-type semiconductor region 512 are covered by a polysilicon film 514 via an insulating film 513. The insulating film 513 is made of, for example, an SiO film. The polysilicon film 514 constitutes the gate terminal (electrode) 153A of the TRM 153.

[0418] In the above Figure 9 In the planar structure, the electric field through the gate terminal (electrode) 153A is provided to the channel (MEM 154 (N+ type semiconductor region 231)) in only one direction. On the other hand, in Figure 59 In the mesa structure, the electric field applied to the channel (MEM 154 (N-type semiconductor region 511)) via the gate terminal (electrode) 153A (polysilicon film 514) is applied in three directions. Therefore, the electric field applied to the MEM 154 varies more significantly in the mesa structure. Consequently, the amount of charge accumulated in the MEM 154 can be reduced accordingly as the electric field variation increases. Furthermore, the charge transfer characteristics in the channel (MEM 154) are enhanced.

[0419] Figures 60 to 63 is a cross-sectional view schematically showing an exemplary configuration of each transistor in the solid-state image sensing device 101g. Figure 59 The corresponding parts in the figure are indicated by the same reference numerals.

[0420] exist Figure 60In the exemplary configuration of FIG, a P+ type semiconductor region 522 is formed on the upper surface of the insulating film 502, and an N-type semiconductor region 521 is formed on the P+ type semiconductor region 522. The upper surfaces and side surfaces of the N-type semiconductor region 521 and the P+ type semiconductor region 522 are covered with a polysilicon film 514 via an insulating film 513.

[0421] Figure 61 The exemplary construction and Figure 60 The exemplary configuration of is different in that a P-type semiconductor region 531 is formed instead of the N-type semiconductor region 521 .

[0422] In addition, the TRM 153 and TRG 155 have Figure 59 and each transistor except TRM 153 and TRG 155 has Figure 60 or Figure 61 In the case of the exemplary configuration, the P+ type semiconductor region 512 of the TRM 153 and the P+ type semiconductor region 522 of each transistor are connected via Figure 58 The P+ type semiconductor region 503 in the transistor is connected. The P+ type semiconductor region 503 is then connected to the ground via, for example, the P well contact 271 and the metal wiring. Thus, the body potential of each transistor is stabilized.

[0423] Figure 62 The exemplary construction and Figure 60 The exemplary configuration of is different in that an N-type semiconductor region 541 is formed instead of the N-type semiconductor region 521 and the P + -type semiconductor region 522 .

[0424] Figure 63 The exemplary construction and Figure 62 The exemplary configuration of is different in that a P-type semiconductor region 551 is formed instead of the N-type semiconductor region 531 .

[0425] Furthermore, the use of mesa-structured transistors increases the response speed of each transistor, completely isolates the transistors from each other, and prevents mixed noise. Furthermore, the mesa structure of AMP 159 reduces random noise. Furthermore, the mesa structure of FD 156 improves charge transfer speed.

[0426] <8. Eighth embodiment>

[0427] The following will refer to Figures 64 to 67 An eighth embodiment of the present technology will be described.

[0428] The eighth embodiment differs from the above-described first embodiment and the like in the circuit configuration and cross-sectional configuration of a pixel.

[0429] {Exemplary Configuration of Solid-State Image Sensing Device 101h}

[0430] Figure 64 A solid-state image sensing device 101h ( Figure 65 ) is an exemplary circuit configuration of a pixel. Figure 2 The corresponding parts in the figure are indicated by the same reference numerals.

[0431] Figure 64 The circuit structure and Figure 2 The circuit configuration differs in that TRM 153 is omitted and the connection positions of MEM 154 and OFG 157 are different. Specifically, TRX 152 and TRG 155 are directly connected to each other without TRM 153. One end of MEM 154 is connected between TRX 152 and TRG 155, and the other end of MEM 154 is connected to ground. OFG 157 is connected between power supply VDD and the cathode of PD 151.

[0432] Figure 65 is a cross-sectional view schematically showing an exemplary configuration of a solid-state image sensing device 101h. Figure 56 The corresponding parts in the figure are represented by the same figure marks, and their descriptions are omitted as needed.

[0433] The insulating film 214, the planarizing film 212, and the microlens 211 are stacked on the lower surface of the N-type semiconductor region 601 in the first semiconductor substrate 201. The P+ type semiconductor region 602 is formed on the N-type semiconductor region 601. The PD 151 is composed of the N-type semiconductor region 601 and the P+ type semiconductor region 602.

[0434] Light incident in the light receiving surface of the solid-state image sensing device 101 h is photoelectrically converted by the PD 151 , and charges generated by the photoelectric conversion are accumulated in the N-type semiconductor region 601 .

[0435] The light shielding film 213 is formed between the PDs 151 (the N − type semiconductor region 601 and the P + type semiconductor region 602 ) in adjacent pixels on the lower surface of the insulating film 214 .

[0436] Furthermore, the upper surface of the PD 151 (the N-type semiconductor region 601 and the P+ type semiconductor region 602) is surrounded by a light shielding film 603. The light shielding film 603 is made of, for example, Figure 56 The light shielding film 453 is made of the same material.

[0437] The light shielding film 603 has a planar shape parallel to the light receiving surface of the solid-state image sensing device 101f. The light shielding film 603 covers the upper surfaces of the N-type semiconductor region 601 and the P+ type semiconductor region 602 constituting the PD 151 except for the opening 603A and the opening 603B. In addition, the light shielding film 603 is as shown in the following reference. Figure 75 The horizontal light shielding portion 804A of the tenth embodiment is also arranged over the entire pixel array portion 111 except for the opening 603A and the opening 603B in each pixel.

[0438] The opening 603A is provided to insert the vertical terminal (electrode) portion 152AB of the gate terminal (electrode) 152A of the TRX 152 into the N− type semiconductor region 601 and to transfer charges accumulated in the N− type semiconductor region 601 to the N+ type semiconductor region 468 .

[0439] The opening 603B is provided to insert the vertical terminal (electrode) portion 157AB of the gate terminal (electrode) 157A of the OFG 157 into the N− type semiconductor region 601 and to transfer charges accumulated in the N− type semiconductor region 601 to the N ++ type semiconductor region 467 .

[0440] Light that is not absorbed by the PD 151 and passes through the PD 151 is reflected on the light shielding film 603 and is prevented from invading layers above the light shielding film 603. Thus, for example, charge caused by light passing through the PD 151 is prevented from invading the N+ type semiconductor region 468 constituting the MEM 154 or the N++ type semiconductor region 462 constituting the FD 156, and the occurrence of noise is prevented.

[0441] In addition, the opening 603A and the opening 603B are desirably as small as possible so that the light passing through the PD 151 does not pass through.

[0442] The light shielding film 603 is covered by an insulating film 604. The insulating film 604 is made of, for example, a silicon oxide film (SiO). The insulating film 604 is covered by a P++ type semiconductor region 605. An N++ type semiconductor region 606 is formed between the lower surface of the insulating film 604 and the P++ type semiconductor region 605. The N++ type semiconductor region 606 causes a gettering effect. A barrier film 607 is formed between the insulating film 604 and the P++ type semiconductor region 605 above the light shielding film 603. The barrier film 607 is made of, for example, a SiN film or a SiCN film.

[0443] The gate terminal (electrode) 152A of the TRX 152, the gate terminal (electrode) 155A of the TRG 155, the gate terminal (electrode) 157A of the OFG 157, and the gate terminal (electrode) 158A of the RST 158 are formed on the device formation surface of the second semiconductor substrate 202 via the insulating film 611. The gate terminals (electrodes) 155A and 158A are arranged above the light shielding film 603, the gate terminal (electrode) 152A is arranged above the opening 603A of the light shielding film 603, and the gate terminal (electrode) 157A is arranged above the opening 603B of the light shielding film 603.

[0444] The gate terminal (electrode) 152A of the TRX 152 is composed of a horizontal terminal (electrode) portion 152AA and a vertical terminal (electrode) portion 152AB. Like the gate terminals (electrodes) of other transistors, the horizontal terminal (electrode) portion 152AA is formed on the device forming surface of the second semiconductor substrate 202 via an insulating film 611. The vertical terminal (electrode) portion 152AB extends vertically downward from the horizontal terminal (electrode) portion 152AA, passes through the second semiconductor substrate 202, and extends into the N-type semiconductor region 601 via an opening 603A in the light shielding film 603. Furthermore, the vertical terminal (electrode) portion 152AB is covered by the insulating film 611. Therefore, the gate terminal (electrode) 152A contacts the N-type semiconductor region 601 via the insulating film 611.

[0445] OFG 157 has a vertical gate structure, and gate terminal (electrode) 157A is composed of a horizontal terminal (electrode) portion 157AA and a vertical terminal (electrode) portion 157AB. Horizontal terminal (electrode) portion 157AA is formed on the device forming surface of second semiconductor substrate 202 via insulating film 611, like the gate terminals (electrodes) of other transistors. Vertical terminal (electrode) portion 157AB extends vertically downward from horizontal terminal (electrode) portion 157AA, passes through second semiconductor substrate 202, and extends into N-type semiconductor region 601 via opening 603B in light shielding film 603. Furthermore, vertical terminal (electrode) portion 157AB is covered by insulating film 611. Therefore, gate terminal (electrode) 157A contacts N-type semiconductor region 601 via insulating film 611.

[0446] Therefore, the TRX 152 and the OFG 157 are electrically connected via the N-type semiconductor region 601 .

[0447] N++ type semiconductor region 459, N+ type semiconductor region 460, N+ type semiconductor region 461, N++ type semiconductor region 462, N+ type semiconductor region 463, P+ type semiconductor region 609, P-- type semiconductor region 610, N+ type semiconductor region 466 and N++ type semiconductor region 467 are formed around the surface of the P type semiconductor region 608 in the second semiconductor substrate 202 above the light shading film 603.

[0448] The P + -type semiconductor region 609 is arranged between the horizontal terminal (electrode) portion 152AA of the TRX 152 and the horizontal terminal (electrode) portion 157AA of the OFG 157 .

[0449] The P-type semiconductor region 610 is arranged directly below the horizontal terminal (electrode) portion 157AA of the OFG 157. The P-type semiconductor region 610 surrounds the vertical terminal (electrode) portion 157AB of the OFG 157 except for the top end thereof via an insulating film 611.

[0450] Figure 66 This is a top view schematically showing an exemplary configuration of the device forming surface of the second semiconductor substrate 202 in the solid-state image sensing device 101h. The figure shows the area of one pixel in the solid-state image sensing device 101h. The dotted square area in the figure indicates the position of the light receiving surface of the PD 151 (the lower surface of the N-type semiconductor region 601). Figure 8 The corresponding parts in the figure are represented by the same figure marks, and their descriptions are omitted as needed.

[0451] Figure 66 An exemplary configuration of pixels in Figure 8 The difference between the exemplary configuration of the pixel in FIG. 1 and FIG. 2 is that the TRM 153 is deleted and the horizontal terminal (electrode) portion 152AA of the TRX 152 is extended almost to the Figure 8 157A. In addition, the difference is that a vertical terminal (electrode) portion 157AB is added to the OFG 157 and the TRX 152 is not directly connected to the OFG 157. In addition, the difference is that each gate terminal (electrode) is arranged on the upper surface of the P-type semiconductor region 608 via an insulating film 611 (not shown).

[0452] {Example of How to Drive the Solid-State Image Sensing Device 101h}

[0453] The following will refer to Figure 67 The potential diagram of FIG. 1 illustrates how to drive the solid-state image sensing device 101h.

[0454] First, OFG 157 is turned on, and TRX 152, TRG 155, and RST 158 are turned off. Charge accumulated in PD 151 (N-type semiconductor region 601) is then transferred to N++ type semiconductor region 467 as a discharge unit via OFG 157 to be discharged to the outside. Thus, PD 151 is reset.

[0455] Then, OFG 157 is turned off, and TRG 155 and RST 158 are turned on. Then, the charges accumulated in MEM 154 (N+ type semiconductor region 468) and FD 156 (N++ type semiconductor region 462) are transferred to N++ type semiconductor region 459 as a discharge unit via TRG 155 and RST 158 to be discharged to the outside. Thus, MEM 154 and FD 156 are reset.

[0456] Then, TRG 155 and RST 158 are disconnected, and the exposure time begins. During the exposure time, PD 151 (N-type semiconductor region 601) generates and accumulates charge based on the amount of received light. Here, when TRX 152 and OFG 157 are disconnected, the potential of the OFG 157 channel is set slightly lower than the potential of the TRX 152 channel. This creates an overflow path between PD 151 (N-type semiconductor region 601) and N++ type semiconductor region 467, which serves as a discharge cell. Therefore, charge overflowing from PD 151 (N-type semiconductor region 601) is discharged to N++ type semiconductor region 467 via the overflow path without leaking into MEM 154 (N+ type semiconductor region 468).

[0457] Then, the TRX 152 is turned on and the exposure time ends. Thus, the charge accumulated in the PD 151 (N-type semiconductor region 601) during the exposure time is transferred to the MEM 154 (N+ type semiconductor region 468) via the TRX 152 and is retained in the MEM 154 (N+ type semiconductor region 468).

[0458] Then, the TRX 152 is turned off and the TRG 155 is turned on. As a result, the charge held in the MEM 154 (N+ type semiconductor region 468) is transferred to the FD 156 (N++ type semiconductor region 462) via the TRG 155. The potential of the FD 156 is then output as a signal level to the vertical signal line VSL via the AMP 159 and the SEL 160.

[0459] In addition, the solid-state image sensing device 101h can produce the same effect as that obtained by the vertical light shielding portion 219B. Figure 3 The solid-state image sensing device 101a in FIG.

[0460] <9. Ninth embodiment>

[0461] The following will refer to Figures 68 to 72 A ninth embodiment of the present technology is described. The ninth embodiment differs from the first embodiment in the arrangement of the peripheral circuits.

[0462] Figure 68 is a block diagram showing an exemplary configuration of the functions of a solid-state image sensing device 101i according to a ninth embodiment of the present technology. Figure 1 The corresponding parts in the figure are represented by the same figure marks, and their descriptions are omitted as needed.

[0463] Figure 68 The solid-state image sensing device 101i and Figure 1 The difference between the solid-state image sensing device 101a and the solid-state image sensing device 101a is that the pixel array portion 702 includes a pixel ADC processing unit and has a two-layer structure of a first layer 701A and a second layer 701B. For example, the first layer 701A is composed of the second semiconductor substrate 202, and the second layer 701B is formed on a third semiconductor substrate (not shown).

[0464] The first layer 701A is configured to include a pixel array section 702, a vertical drive unit 112, a ramp module 113, a clock module 114, and a horizontal drive unit 116. The vertical drive unit 112, the ramp module 113, the clock module 114, and the horizontal drive unit 116 are formed on the device-forming surface of the second semiconductor substrate 202, which is a single-crystal silicon substrate, using, for example, a mesa structure. Furthermore, the pixel ADC (A / D converter) processing unit arranged in the pixel array section 702 is also formed on the device-forming surface of the second semiconductor substrate 202, which is a single-crystal silicon substrate, using, for example, a mesa structure. Furthermore, each pixel is provided with an ADC for performing A / D conversion on the pixel signal of each pixel in the pixel array section 702.

[0465] The second layer 701B is configured to include a latch circuit 703, a data storage unit 115, a system control unit 117, and a signal processing unit 118. The latch circuit 703 is arranged at a position corresponding to the ADC provided for each pixel in the pixel array section 702.

[0466] Furthermore, the first layer 701A is bonded to the second layer 701B via, for example, Cu-Cu bonding.

[0467] This article will refer to Figure 69 and Figure 70 The advantages of providing an ADC for each pixel will be described.

[0468] Figure 69FIG7 shows a portion of an equivalent circuit in which an ADC is provided for each row. In this example, pixel signals output from pixels in the same vertical column are provided to the same ADC. For example, pixel signals output from pixels P(1,1) to P(m,1) in the first column are provided to ADC1, and pixel signals output from pixels P(1,n) to P(m,n) in the nth column are provided to ADCn. Each ADC performs AD conversion on the pixel signal based on the ramp signal provided by DAC 711 and provides the converted digital pixel signal to the latch circuit. In addition, the current value of the pixel signal flowing on the bit line connecting each pixel and the ADC is amplified by amplifier transistors 712-1 to 712-n.

[0469] Here, as shown in the figure, wiring resistance and parasitic capacitance are introduced into the wiring between each pixel and the ADC. Furthermore, the wiring resistance and parasitic capacitance differ between the upper and lower pixels in the figure because the wiring distances between pixels in the same column and the ADC vary. For example, the wiring resistance and parasitic capacitance differ between pixel P(1,1) and pixel P(m,1). Consequently, the time constant of the wiring between the pixel and the ADC differs between pixels in the same column.

[0470] Therefore, noise such as horizontal lines or vertical black spots is likely to appear in captured images. Furthermore, the amplification factor of amplifier transistors 712-1 to 712-n needs to be increased to reduce the influence of signal loss due to wiring resistance and parasitic capacitance of pixel signals flowing on the bit lines. Consequently, power consumption in amplifier transistors 712-1 to 712-n increases, making it difficult to increase the drive frequency.

[0471] on the other hand, Figure 70 The equivalent circuit for providing an ADC for each pixel is shown. Specifically, ADCs (1,1) to (m,n) are provided for pixels P(1,1) to P(m,n), respectively. Each pixel then performs AD conversion on the pixel signal output by a different ADC based on the ramp signal provided by DAC 711. The AD-converted pixel signals are provided via bit lines to latch circuits L1 to Ln provided for each column.

[0472] In this case, the wiring resistance and parasitic capacitance caused in the wiring between each pixel and ADC are lower than Figure 69 The wiring resistance and parasitic capacitance in the example are almost the same in all pixels. Therefore, the time constant of the wiring between the pixel and the ADC is almost the same in all pixels.

[0473] Therefore, noise such as horizontal lines or vertical black spots is reduced. In addition, the time constant of the wiring is reduced, which enables high-speed driving using a high-frequency clock. In addition, due to the reduced noise, the amplification factor of the amplifier transistors 712-1 to 712-n can be reduced, thereby reducing power consumption.

[0474] In addition, in the solid-state image sensing device 101i, an ADC may be provided for each pixel instead of each pixel, such as Figure 71 and Figure 72 shown.

[0475] Figure 71 An exemplary circuit configuration of four pixels in the solid-state image sensing device 101i is shown. Figure 2 The parts corresponding to the parts in the drawings are denoted by the same reference numerals in the drawings. Incidentally, some reference numerals are omitted for ease of understanding of the drawings.

[0476] In this example, the four pixels P1 to P4 share the FD 156 , RST 158 , AMP 159 , SEL 160 , and ADC circuit 751 . ADC circuit 751 is composed of transistors TR1 to TR8 . A digital signal output from ADC circuit 751 is supplied to latch circuit 703 .

[0477] Therefore, the charges held in the MEM 154 in the pixels P1 to P4 are sequentially transferred to the FD 156 , and a pixel signal corresponding to the charges held in the FD 156 is supplied to the ADC circuit 751 via the AMP 159 and the SEL 160 .

[0478] Figure 72 This is a top view schematically showing an exemplary configuration of the device forming surface of the second semiconductor substrate 202 in the solid-state image sensing device 101i. The figure shows the region of four pixels in the solid-state image sensing device 101i. Figure 8 The parts corresponding to the parts in the drawings are denoted by the same reference numerals in the drawings. Incidentally, some reference numerals are omitted for ease of understanding of the drawings.

[0479] in addition, Figure 72 Examples and Figure 71 The difference from the example of is that the FD 156 and the RST 158 are provided for each pixel and the AMP 159, the SEL 160, and the ADC circuit 751 are shared among the pixels P1 to P4.

[0480] Pixels P1 to P4 are arranged adjacent to each other. Pixel P1 and pixel P2 are adjacent in the horizontal direction in the figure, and the pixel layout is symmetrical to each other. Pixel P3 and pixel P4 are adjacent in the horizontal direction in the figure, and the pixel layout is symmetrical to each other. Pixel P1 and pixel P3 are adjacent in the vertical direction in the figure, and the pixel layout is vertically symmetrical to each other. Pixel P2 and pixel P4 are adjacent in the vertical direction in the figure, and the pixel layout is vertically symmetrical to each other.

[0481] The AMP 159 is arranged adjacent to the right of the pixel P2 in the figure, and the SEL 160 is arranged above the AMP 159 in the figure.

[0482] The ADC circuit 751 is arranged so as to be adjacent to the pixel P1 and the pixel P2 in the figure upward. In addition, it is assumed that each transistor constituting the ADC circuit 751 has a mesa structure as described above, for example.

[0483] In this manner, the ADC circuit 751 is shared among a plurality of pixels, so that almost the same effect as that in the case where an ADC is provided for each pixel can be obtained, and the device can be miniaturized.

[0484] <10. Tenth embodiment>

[0485] The following will refer to Figures 73 to 83 The tenth embodiment of the present technology is described below. The tenth embodiment differs from the first embodiment mainly in the cross-sectional structure and manufacturing method of the pixel.

[0486] {Exemplary Configuration of Solid-State Image Sensing Device 101j}

[0487] Figure 73 A cross section of a solid-state image sensing device 101j according to a tenth embodiment of the present technology is schematically shown. Figure 3 The corresponding parts in the figure are indicated by the same reference numerals.

[0488] Although Figure 73 A cross section of a portion including one pixel in the solid-state image sensing device 101j is shown, but the other pixels have basically the same configuration. The lower side in the figure is a light receiving surface (back side) of the solid-state image sensing device 101j.

[0489] The N-type semiconductor region 802 and the N-type semiconductor region 803 constituting the PD 151 are embedded in the semiconductor substrate 801 in the solid-state image sensing device 101j. Light incident on the light receiving surface of the solid-state image sensing device 101j is photoelectrically converted in the N-type semiconductor region 802, and the generated charge is accumulated in the N-type semiconductor region 803.

[0490] In addition, the boundary line as shown in the figure is not necessarily set between the N-type semiconductor region 802 and the N-type semiconductor region 803 , and the N-type impurity concentration gradually increases from the N-type semiconductor region 802 to the N-type semiconductor region 803 .

[0491] The upper surface and side surfaces of the PD 151 (the N-type semiconductor region 802 and the N-type semiconductor region 803) are surrounded by a light shielding film 804. More specifically, the light shielding film 804 is composed of a horizontal light shielding portion 804A, a vertical light shielding portion 804B, a vertical light shielding portion 804C, and a horizontal light shielding portion 804D ( Figure 82 ) is formed. In addition, the light shielding film 804 is formed by, for example, Figure 3 The light shielding film 219 is made of the same material.

[0492] The horizontal light shielding portion 804A has a planar shape parallel to the light receiving surface of the solid-state image sensing device 101j and covers the upper surfaces of the N-type semiconductor region 802 and the N-type semiconductor region 803 constituting the PD 151 except for the opening 804E.

[0493] The vertical light shielding portion 804B has a wall shape perpendicular to the light receiving surface of the solid-state image sensing device 101 j and is formed to surround the side surfaces of the N-type semiconductor region 802 and the N-type semiconductor region 803 constituting the PD 151 .

[0494] The vertical light shielding portion 804C is arranged around the boundary between the horizontal light shielding portion 804A and the opening 804E and has a wall shape perpendicular to the light receiving surface. The vertical light shielding portion 804C is formed so as to oppose the vertical light shielding portion 804B (closer to the N-type semiconductor region 808) in a direction perpendicular to the horizontal light shielding portion 804A relative to the horizontal light shielding portion 804A. Furthermore, the vertical light shielding portion 804C is formed at a different position from the vertical light shielding portion 804B in a direction parallel to the horizontal light shielding portion 804A. Furthermore, the vertical light shielding portion 804C is formed so as to block light between at least the vertical terminal (electrode) portion 152AB of the TRX 152 and the N-type semiconductor region 808 that constitutes the MEM 154.

[0495] Next, the horizontal light shielding portion 804D will be described.

[0496] The opening 804E is provided to insert the vertical terminal (electrode) portion 152AB of the TRX 152 into the N-type semiconductor region 802 and to transfer the charge accumulated in the N-type semiconductor region 803 to the N-type semiconductor region 808 .

[0497] The opening 804E is desirably as small as possible so that light passing through the PD 151 does not pass through. The opening 804E is desirably arranged at the end of the pixel (near the vertical light shielding portion 804B) to prevent oblique light with a large incident angle from passing through.

[0498] In addition, at least one of the vertical light shielding portion 804C and the horizontal light shielding portion 804D may not be formed.

[0499] The light shielding film 804 is covered with an insulating film 805. The insulating film 805 is formed of a high dielectric constant such as HfO2, TaO2, or Al2O3.

[0500] The periphery of the light shielding film 804 and the lower surface of the N-type semiconductor region 802 are covered with a P-type semiconductor region 806, which serves as a conductive layer opposite to the signal charge. The thickness of the P-type semiconductor region 806 is substantially uniform, and is assumed to be within 20 nm, for example. The P-type semiconductor region 806 has an impurity concentration that is as high as possible to limit the generation of charge at the defect level at the interface between the light shielding film 804 and the semiconductor substrate 802, and to serve as a pinning layer.

[0501] In addition, the insulating film 805 is made of a high dielectric film and has a predetermined potential, thereby enhancing the pinning effect of the P-type semiconductor region 806. In addition, a potential is directly supplied from the outside to the light shielding film 804, thereby obtaining the same effect.

[0502] The gate terminal (electrode) 152A of the TRX 152 and the gate terminal (electrode) 155A of the TRG 155 are formed on the upper surface (device formation surface) of the semiconductor substrate 801. The gate terminal (electrode) 155A is arranged above the horizontal light shielding portion 804A, and the gate terminal (electrode) 152A is arranged above the opening 804E of the light shielding film 804.

[0503] The gate terminal (electrode) 152A of the TRX 152 is composed of a horizontal terminal (electrode) portion 152AA and a vertical terminal (electrode) portion 152AB. Horizontal terminal (electrode) portion 152AA, like gate terminal (electrode) 155A, is formed on the upper surface (device formation surface) of the semiconductor substrate 801. Vertical terminal (electrode) portion 152AB extends vertically downward from horizontal terminal (electrode) portion 152AA and extends into the N-type semiconductor region 802 through an opening 804E in the light shielding film 804.

[0504] A P-type semiconductor region 807 , an N− type semiconductor region 809 , and a P+ type semiconductor region 810 are formed around the surface of the semiconductor substrate 801 above the horizontal light shielding portion 219A.

[0505] The P-type semiconductor region 807 is arranged on the right side of the vertical terminal (electrode) portion 152AB of the TRX 152 and directly below the horizontal terminal (electrode) portion 152AA.

[0506] The N-type semiconductor region 809 is arranged on the right side of the gate terminal (electrode) 155A of the TRG 155 , thereby constituting the FD 156 .

[0507] The P + -type semiconductor region 810 is arranged between the vertical terminal (electrode) portion 152AB of the TRX 152 and the N − -type semiconductor region 809 .

[0508] The N-type semiconductor region 808 is arranged just below the P-type semiconductor region 807 , thereby constituting the MEM 154 . The vertical light shielding portion 804C is arranged between the vertical terminal (electrode) portion 152AB of the gate terminal (electrode) 152A and the N-type semiconductor region 808 .

[0509] When the drive signal TRX applied to the gate terminal (electrode) 152A of the TRX 152 is turned on and the TRX 152 is turned on, a channel is formed between the N-type semiconductor region 802 (PD 151) and the N-type semiconductor region 808 (MEM 154). The charge accumulated in the N-type semiconductor region 803 is then transferred to the N-type semiconductor region 808 via the channel and is retained in the N-type semiconductor region 808.

[0510] Furthermore, when the drive signal TRG applied to the gate terminal (electrode) 155A of the TRG 155 is turned on and the TRG 155 is turned on, a channel is formed between the N-type semiconductor region 808 (MEM 154) and the N-type semiconductor region 809 (FD 156). The charge held in the N-type semiconductor region 808 is then transferred to the N-type semiconductor region 809 via the channel. The potential of the N-type semiconductor region 809 is then output as a signal level to the vertical signal line VSL via the AMP 159 and the SEL 160 (not shown).

[0511] Figure 74 and Figure 75 are top views schematically showing exemplary configurations of device forming surfaces of the solid-state image sensing device 101j. Figure 74 In FIG, the area where the vertical light shielding portion 804B is arranged is indicated by an auxiliary dot-dash line. That is, as shown by the arrow in the figure, the vertical light shielding portion 804B is arranged between two auxiliary lines. In addition, Figure 75 Shown from Figure 74 The auxiliary lines indicating the area where the vertical light shielding portion 804B is arranged are deleted and a slanted line pattern indicating the area where the horizontal light shielding portion 804A is arranged is added.

[0512] Figure 74 and Figure 75 Four pixels P1 to P4 constituting the pixel array portion 111 are shown. Pixel P1 and pixel P2 are adjacent in the horizontal direction (row direction) in the figure, and the pixel layout is symmetrical to each other. Pixel P3 and pixel P4 are adjacent in the horizontal direction (row direction) in the figure, and the pixel layout is symmetrical to each other. Pixel P1 and pixel P3 are adjacent in the vertical direction (column direction) in the figure, and the pixel layout is vertically symmetrical to each other. Pixel P2 and pixel P4 are adjacent in the vertical direction (column direction) in the figure, and the pixel layout is vertically symmetrical to each other.

[0513] In addition, if Figure 74 As shown, the vertical light shielding portion 804B is arranged to extend over a plurality of pixels between a plurality of columns of pixels adjacent in the row direction in the pixel array portion 111 in which a plurality of pixels are arranged in the row direction and the column direction. In addition, the vertical light shielding portion 804B is arranged to extend over a plurality of pixels between a plurality of rows of pixels adjacent in the column direction in the pixel array portion 111 in the row direction.

[0514] In addition, if Figure 75 As shown, the horizontal light shielding portion 219A is arranged over the entire area except for the opening 219C in each pixel. Thus, in each pixel, light is blocked by the horizontal light shielding portion 804A surrounding the vertical terminal (electrode) portion 152AB of the TRX 152 except for the opening 804E.

[0515] Therefore, light that is not absorbed by the PD 151 and passes through it is reflected by the horizontal light shielding portion 804A and prevented from intruding into layers above the horizontal light shielding portion 804A. Even if light that is not absorbed by the PD 151 and passes through it passes through the opening 804E of the light shielding film 804, the vertical light shielding portion 804C prevents the light from intruding into the N-type semiconductor region 808 that constitutes the MEM 154. Thus, for example, charge generated by light that passes through the PD 151 is prevented from intruding into the N-type semiconductor region 808 that constitutes the MEM 154 or the N-type semiconductor region 809 that constitutes the FD 156, thereby preventing the occurrence of noise. Furthermore, the vertical light shielding portion 804B prevents light incident from adjacent pixels from leaking into the PD 151, thereby preventing the occurrence of noise such as color mixing.

[0516] Furthermore, the channel formed on the surface of the semiconductor substrate 801 directly below the horizontal terminal (electrode) portion 152AA of the gate terminal (electrode) 152A can be formed shallower than the N-type semiconductor region 808, the P+-type semiconductor region 810, and the like. Therefore, the thickness of the horizontal light shielding portion 804A can be adjusted, or the vertical light shielding portion 804C can be provided below the horizontal terminal (electrode) portion 152AA. This further prevents charge from leaking into the N-type semiconductor region 808 or the N-type semiconductor region 809.

[0517] Furthermore, the region where the gate terminal (electrode) 152 contacts the insulating film is a metal gate structure, thereby further improving the light shielding capability.

[0518] {Method of Manufacturing Solid-State Image Sensing Device 101j}

[0519] The following will refer to Figures 76 to 83 A method for manufacturing the solid-state image sensing device 101j is described. Figure 73 The corresponding part in Figures 76 to 83 Incidentally, in order to facilitate understanding of the drawings, reference numerals not related to the description are omitted as needed.

[0520] First, if Figure 76 As shown, ions (such as boron) are implanted into a semiconductor substrate 801 made of single crystal silicon to form a P-type semiconductor region 806, which serves as a conductive layer with a charge opposite to that of the signal, and a P+-type semiconductor region 851, which serves as a sacrificial film. The P-type semiconductor region 806 and the P+-type semiconductor region 851 are formed in the region serving as the light shielding film 804 and the aforementioned pinning layer. At this time, the impurity concentrations in the P-type semiconductor region 806 and the P+-type semiconductor region 851 are adjusted so that only the P+-type semiconductor region 851 is removed in the subsequent wet etching step without removing the P-type semiconductor region 806.

[0521] Then, N-type semiconductor region 802 and N-type semiconductor region 803 (N-type semiconductor region 802 and N-type semiconductor region 803 are conductive layers with the same signal charge) are formed on a portion of the pinned layer by ion implantation to form a depletion layer for photoelectric conversion.

[0522] Then, if Figure 77 As shown, a single crystal silicon film is formed on the upper surface of a semiconductor substrate 801 by epitaxial growth. A transfer channel, a transfer gate, a charge retention unit, and peripheral circuits are then formed on the resulting single crystal silicon film. Specifically, for example, gate terminal (electrode) 152A, gate terminal (electrode) 155A, P-type semiconductor region 807, N-type semiconductor region 808, N-type semiconductor region 809, and P+ type semiconductor region 810 are formed.

[0523] Then, if Figure 78 As shown, a wiring layer (not shown) is formed on the upper surface of the semiconductor substrate 801, and then, a support substrate 852 is applied to the upper surface of the semiconductor substrate 801. Here, the support substrate 852 may be formed of a signal circuit.

[0524] in addition, Figure 78 The subsequent image is vertically reversed to the previous image.

[0525] Then, if Figure 79As shown, the back surface of the semiconductor substrate 801 is thinned by CMP to around the surface of the N-type semiconductor region 802 (PD151).

[0526] Then, if Figure 80 As shown, the P-type semiconductor region 806 is removed from the back surface of the semiconductor substrate 801 by dry etching such as reactive ion etching (RIE). As a result, a trench 853 is formed, which extends vertically from the back surface of the semiconductor substrate 801 and reaches the P+-type semiconductor region 851. In addition, the P-type semiconductor region 806 is not uniformly removed and remains thin enough to serve as a pinning layer around the trench 853.

[0527] Then, if Figure 81 As shown, the P+ type semiconductor region 851 is removed by wet etching using an acidic solution. Here, as described above, the component ratio of the solution is adjusted so that the P-type semiconductor region 806 remains as a pinning layer and only the P+ type semiconductor region 851 is removed. As a result, the trench 853 extends to the portion where the P+ type semiconductor region 851 is removed. In addition, the P-type semiconductor region 806 is formed to be uniformly thin.

[0528] Then, if Figure 82 As shown, an insulating film 805 is formed on the inner wall of the trench 853 by, for example, atomic layer deposition (ALD) to limit the interface level of silicon on the inner wall of the trench 853.

[0529] Then, a metal film is embedded in the groove 853 by a method such as CVD, and the horizontal light shielding portion 804A, the vertical light shielding portion 804B, and the vertical light shielding portion 804C of the light shielding film 804 are formed. In addition, a horizontal light shielding portion 804D is formed on the back surface of the semiconductor substrate 801 to block the entrance of the groove 853. The horizontal light shielding portion 804D is arranged to extend over a plurality of pixels between a plurality of columns of pixels adjacent to each other in the row direction in the pixel array section 111, for example, in the column direction. In addition, the horizontal light shielding portion 804D is arranged to extend over a plurality of pixels between a plurality of rows of pixels adjacent to each other in the column direction in the pixel array section 111, for example, in the row direction.

[0530] In this case, a metal film for light shielding may be formed in a pixel region for determining the black level of a pixel signal and a portion of the phase difference detection pixel.

[0531] Furthermore, an insulating film 805 is formed on the back surface of the semiconductor substrate 801 .

[0532] On-chip color filters 854, on-chip microlenses 855, etc. are then formed on the back surface of the semiconductor substrate 801, and the solid-state image sensing device 101j is completed. Figure 83 shown.

[0533] The solid-state image sensing device 101j can produce almost the same effects as the solid-state image sensing device 101a described above.

[0534] Furthermore, unlike the solid-state image sensing device 101a, the solid-state image sensing device 101j does not have a bonding interface between the applied substrate, so there is no defect level in the channel of the TRX 152. Furthermore, the PD 151, TRX 152, and MEM 154 are all made of single-crystal silicon. Therefore, undesirable charge transfer between the PD 151 and MEM 154 can be prevented.

[0535] Furthermore, the solid-state image sensing device 101 j has a vertical light shielding portion 804C for shielding light between the vertical terminal (electrode) portion 152AB of the TRX 152 and the N-type semiconductor region 808 constituting the MEM 154 , thereby further improving light shielding performance.

[0536] Furthermore, the P-type semiconductor region 806 can be formed to be uniformly thin, and the volume of the N-type semiconductor region 802 constituting the PD 151 can be increased in the solid-state image sensing device 101j. Consequently, the saturation charge amount increases, and sensitivity is improved. Furthermore, oblique light characteristics are enhanced.

[0537] In addition, for example, in the above Figure 76 In the step of , the columnar P-type semiconductor region 806 can be the following structure: a conductive layer of a conductive type opposite to the signal charge (P-type conductive layer, and hereinafter referred to as an inner conductive layer) is arranged in the core of the column, a silicon layer into which impurities are not injected (hereinafter referred to as a silicon layer) is arranged around the inner conductive layer, and a conductive layer of a conductive type opposite to the signal charge (P-type conductive layer, and hereinafter referred to as an outer conductive layer) is arranged around the silicon layer. Thus, for example, in the above Figure 80 and Figure 81 In the steps of removing the inner conductive layer by dry etching, and then removing the silicon layer by wet etching using an alkaline solution and leaving only the outer conductive layer, it is easy to form a silicon layer having the same Figure 73 The conductive layer has the same shape as the P-type semiconductor region 806.

[0538] <11. Eleventh embodiment>

[0539] The following will refer to Figures 84 to 129 An eleventh embodiment of the present technology will be described.

[0540] {Exemplary Configuration of Solid-State Image Sensing Device 101k}

[0541] Figure 84 The cross section of a solid-state image sensing device 101k according to the eleventh embodiment of the present technology is schematically shown. Figure 841 shows a cross section of a portion including one pixel in the solid-state image sensing device 101k, but the other pixels have basically the same configuration. Figure 84 The lower side in FIG. 1 is a light receiving surface of the solid-state image sensing device 101 k.

[0542] The solid-state image sensing device 101 k differs from the solid-state image sensing device 101 j according to the tenth embodiment of the present technology described above mainly in the cross-sectional configuration and manufacturing method of the pixel.

[0543] The PD 151 is embedded around the back surface of the semiconductor substrate 1001 in the solid-state image sensing device 101k. In addition, the upper surface and side surface of the PD 151 are covered with a light shielding film 1002. Specifically, the light shielding film 1002 is composed of a horizontal light shielding portion 1002A and a vertical light shielding portion 1002B. In addition, the light shielding film 1002 is composed of, for example, Figure 3 The light shielding film 219 is made of the same material.

[0544] The horizontal light shielding portion 1002A has a planar shape parallel to the light receiving surface of the solid-state image sensing device 101k. The horizontal light shielding portion 1002A covers the upper surface of the PD 151 except the opening 1002C. Figure 75 The horizontal light shielding portion 804A according to the tenth embodiment is similarly arranged in the entire area of the pixel array portion 111 except for the opening 1002C in each pixel.

[0545] The vertical light shielding portion 1002B has a wall shape perpendicular to the light receiving surface of the solid-state image sensing device 101k. The vertical light shielding portion 1002B is formed to surround the side surface of the PD 151. In addition, the vertical light shielding portion 1002B is similar to the one described above with reference to FIG. Figure 74 The vertical light shielding portion 804B according to the tenth embodiment is arranged to extend over a plurality of pixels between a plurality of columns of pixels adjacent in the row direction in the pixel array portion 111 in the column direction. Figure 74 The vertical light shielding portion 804B according to the tenth embodiment is also arranged to extend over a plurality of pixels between a plurality of rows of pixels adjacent in the column direction in the pixel array portion 111 in the row direction.

[0546] The opening 1002C is provided to insert the vertical terminal (electrode) portion 152AB of the gate terminal (electrode) 152A of the TRX 152 into the PD 151 and transfer the charge accumulated in the PD 151 to the MEM 154 .

[0547] Light that is not absorbed by the PD 151 and passes through it is reflected by the horizontal light shielding portion 1002A and prevented from intruding into layers above the horizontal light shielding portion 1002A. Thus, for example, charges generated by light passing through the PD 151 are prevented from intruding into the MEM 154 or the FD 156, thereby preventing noise from occurring. Furthermore, the vertical light shielding portion 1002B prevents light incident from adjacent pixels from leaking into the PD 151, thereby preventing noise such as color mixing from occurring.

[0548] The opening 1002C is desirably as small as possible so that light passing through the PD 151 does not pass through. The opening 1002C is desirably arranged at the end of the pixel (near the vertical light shielding portion 1002B) to prevent oblique light with a large incident angle from passing through.

[0549] The gate terminal (electrode) 152A of the TRX 152, the gate terminal (electrode) 155A of the TRG 155, and the gate terminal (electrode) 1005A of the pixel transistor are formed on the upper surface (device formation surface) of the semiconductor substrate 1001. The gate terminal (electrode) 155A and the gate terminal (electrode) 1005A are arranged above the horizontal light shielding portion 1002A, and the gate terminal (electrode) 152A is arranged above the opening 1002C of the light shielding film 1002.

[0550] The gate terminal (electrode) 152A of the TRX 152 is composed of a horizontal terminal (electrode) portion 152AA and a vertical terminal (electrode) portion 152AB. The horizontal terminal (electrode) portion 152AA is formed on the device formation surface of the semiconductor substrate 1001, similar to the gate terminals (electrodes) of other transistors. The vertical terminal (electrode) portion 152AB extends vertically downward from the horizontal terminal (electrode) portion 152AA and extends into the PD 151 through the opening 1002C of the light shielding film 1002.

[0551] FD 156 and source / drain regions (SD) 1003 and 1004 are formed around the upper surface of semiconductor substrate 1001 above horizontal light shield 1002A. FD 156 is arranged to the right of gate terminal (electrode) 155A. SD 1003 and SD 1004 are arranged on both sides of gate terminal (electrode) 1005A.

[0552] Furthermore, the MEM 154 is formed slightly deeper than the upper surface of the semiconductor substrate 1001 just below the horizontal terminal (electrode) portion 152AA of the gate terminal (electrode) 152A and above the horizontal light shielding portion 1002A.

[0553] When the drive signal TRX applied to the gate terminal (electrode) 152A of the TRX 152 is turned on and the TRX 152 is turned on, a channel is formed between the PD 151 and the MEM 154. The charge accumulated in the PD 151 is then transferred to the MEM 154 via the channel and held therein.

[0554] Furthermore, when the drive signal TRG applied to the gate terminal (electrode) 155A of the TRG 155 is turned on and the TRG 155 is turned on, a channel is formed between the MEM 154 and the FD 156. The charge held in the MEM 154 is then transferred to the FD 156 via the channel. The potential of the FD 156 is then output as a signal level to the vertical signal line VSL via the AMP 159 and the SEL 160 (not shown).

[0555] {Method of Manufacturing Solid-State Image Sensing Device 101k}

[0556] The following will refer to Figures 85 to 129 A method of manufacturing the solid-state image sensing device 101 k will be described.

[0557] (First Manufacturing Method)

[0558] First, refer to Figures 85 to 98 A first method of manufacturing the solid-state image sensing device 101 k will be described.

[0559] First, if Figure 85 As shown, a hard mask 1102 is formed on the surface of a semiconductor substrate 1101. The hard mask 1102 is made of, for example, SiO2 or SiN. The hard mask 1102 is formed at a position where the opening 1002C of the light shielding film 1002 is formed.

[0560] Then, if Figure 86 As shown, a sacrificial film 1103 is formed at a region on the surface of the semiconductor substrate 1101 excluding the hard mask 1102. The sacrificial film 1103 uses, for example, SiGe as a material lattice-matched to silicon.

[0561] In addition, the thickness of the sacrificial film 1103 is set to, for example, 200 nm or more in consideration of light shielding properties and visual properties. Here, the visual properties refer to the visual properties of the alignment mark because a portion of the sacrificial film 1103 is not removed and remains and serves as an alignment mark, as described below.

[0562] In addition, if Figure 87 As shown, the sacrificial film 1103 may be grown beyond the upper end of the hard mask 1102. In this case, the sacrificial film 1103 is polished to a predetermined thickness by CMP, as shown in FIG. Figure 88 shown.

[0563] The hard mask 1102 is then removed by wet etching, as shown in FIG. Figure 89 shown.

[0564] A silicon film 1104 is then formed on the upper surface of the semiconductor substrate 1101 and the sacrificial film 1103 by epitaxial growth, as shown in FIG. Figure 90 shown.

[0565] The silicon film 1104 is then polished to a predetermined thickness by CMP. Figure 91 shown.

[0566] Then form the pixel circuit, such as Figure 92 That is, the PD 151 , the gate terminal (electrode) 152A, the MEM 154 , the gate terminal (electrode) 155A, the SD 1003 , the SD 1004 , the gate terminal (electrode) 1005A, etc. are formed. In addition, a wiring layer (not shown) is formed on the silicon film 1104 , for example.

[0567] A support substrate (not shown) is then applied to the wiring layer (not shown). In addition, the back surface of the semiconductor substrate 1001 is thinned to around the surface of the PD 151, as shown in FIG. Figure 93 shown.

[0568] in addition, Figure 93 The subsequent image is vertically reversed to the previous image.

[0569] A trench 1105 is then formed on the back side of the semiconductor substrate 1001, as shown in FIG. Figure 94 The trench 1105 is formed at the position where the vertical light shielding portion 1002B of the light shielding film 1002 is formed, and the top end of the trench 1105 reaches the sacrificial film 1103 .

[0570] In addition, the groove 1105 is formed as shown in FIG. Figure 19 The method is similar to that described above.

[0571] Furthermore, the groove 1105 is not formed in a region other than the pixel region (such as a scribe region).

[0572] The sacrificial film 1103 is then removed by wet etching using a predetermined solution, such as Figure 95 Then, a cavity 1106 is formed, which extends horizontally at the position where the sacrificial film 1103 is removed and opens into the trench 1105. The thickness of the cross section of the cavity 1106 is almost uniform.

[0573] In addition, for example, a mixed solution of HF, H2O2, and CH3COOH is used for wet etching.

[0574] Furthermore, as described above, the groove 1105 is not formed in areas other than the pixel area. Figure 95 In the steps of , it is not removed by wet etching and remains as it is, such as Figure 96 The opening 1103A of the sacrificial film 1103 surrounded by the dotted line in the figure is then used as an alignment mark.

[0575] Then generate the light shielding film 1002, such as Figure 97 For example, a fixed charge film (not shown) is first formed on the surface of the groove 1105 and the cavity 1106. The fixed charge film is made of, for example, HfO2, Al2O3, etc.

[0576] An insulating film (not shown) is then formed on the surface of the fixed charge film. The insulating film is made of, for example, a SiO2 film.

[0577] The light shielding film 1002 is then embedded in the groove 1105 and the cavity 1106 .

[0578] Then, if Figure 98 As shown, a planarization film 1107 is formed on the back surface of the semiconductor substrate 1101, and then an on-chip color filter 1108, an on-chip microlens 1109, and the like are formed, so that a solid-state image sensing device 101k is completed.

[0579] In the first manufacturing method, the alignment mark of the solid-state image sensing device 101k can be referred to as above. Figure 96 The formation is performed without requiring special manufacturing steps.

[0580] Figure 99 The steps for manufacturing the alignment mark of the solid-state image sensing device 101k in the first manufacturing method are the same as those described above. Figure 73 101j. The following diagrams compare the steps for manufacturing the alignment mark of the solid-state image sensing device 101j in FIG. Furthermore, manufacturing step A shows the step for manufacturing the alignment mark of the solid-state image sensing device 101k, and manufacturing step B shows the step for manufacturing the alignment mark of the solid-state image sensing device 101j.

[0581] In the solid-state image sensing device 101k, as described above, the silicon film 1104 is Figure 90 In the step of epitaxial growth on the upper surface of the sacrificial film 1103 made of SiGe, the silicon film 1104 is only Figure 91 Polishing is performed in the steps in the figure to form the alignment mark of the dotted square.

[0582] On the other hand, until the sacrificial film ( Figure 76 and Figure 77 The steps of epitaxially growing a silicon film on the upper surface of the P+ type semiconductor region 851 in FIG. 1 and polishing the silicon film are almost similar to those in the solid-state image sensing device 101k.

[0583] Here, boron-implanted silicon has poor visual properties and is difficult to use for alignment marks. In addition, when the boron concentration is increased for higher visual properties, many defects appear, and many defects appear in the silicon film to be grown epitaxially, deteriorating the quality.

[0584] Therefore, after pre-processing, the surface of the silicon film is masked with photoresist. Then, the alignment mark is processed and then post-processed. Thus, the alignment mark is formed in the dotted square in the figure.

[0585] In this way, the number of steps for manufacturing the alignment mark can be further reduced in the solid-state image sensing device 101 k than in the solid-state image sensing device 101 j .

[0586] In addition, this article will refer to Figures 100 to 103 A discussion is made as to whether or not the alignment mark can be formed by removing the sacrificial film 1103 in the region where the alignment mark is to be formed, as in the pixel region.

[0587] For example, the groove 1105 is formed in Figure 100 Around the opening 1103A of the sacrificial film 1103, as shown in the dotted circle, Figure 101 shown.

[0588] Then, if Figure 102 As shown, the sacrificial film 1103 is removed by wet etching to form a cavity 1106. At this time, residues 1103B and 1103C of the sacrificial film may remain in the area surrounded by the dotted line 1121 in the figure or at one end of the sacrificial film 1103.

[0589] Then, if Figure 103 As shown, a film 1122 made of a fixed charge film and an insulating film is formed on the surfaces of the groove 1105 and the cavity 1106 , and then the light shielding film 1002 is embedded in the film 1122 .

[0590] Here, residues 1103B and 1103C are not removed and remain in the area enclosed by dotted line 1121. Therefore, if this area is used for an alignment mark, the shape of the mark is changed and asymmetrical. Therefore, it is assumed that the alignment mark recognition accuracy has deteriorated, and the area enclosed by dotted line 1121 is considered unsuitable for alignment marks.

[0591] (Second Manufacturing Method)

[0592] The following will refer to Figures 104 to 120 A second method for manufacturing the solid-state image sensing device 101k will be described. Figures 85 to 98 The corresponding part in Figures 104 to 120 The same reference numerals are used in the drawings.

[0593] First, if Figure 104 As shown above Figure 85 Similar to the steps in , a hard mask 1102 is formed on the surface of the semiconductor substrate 1101.

[0594] Then, if Figure 105 As shown, a sacrificial film 1201 is formed on the surface of the semiconductor substrate 1101 except for the hard mask film 1102 .

[0595] Sacrificial film 1201 is made of SiGe, similar to sacrificial film 1103 in the first manufacturing method. Unlike sacrificial film 1103, sacrificial film 1201 is adjusted so that the Ge concentration increases toward the center and decreases toward the upper and lower ends. Consequently, the wet etching rate (WER) of sacrificial film 1201 increases toward the center and decreases toward the upper and lower ends.

[0596] In addition, if Figure 106 As shown, the sacrificial film 1201 may be formed outside the upper end of the hard mask 1102. In this case, as shown in FIG. Figure 107 As shown, the sacrificial film 1201 is polished to a predetermined thickness by CMP. In addition, during the formation of the sacrificial film 1201, the concentration of Ge in the sacrificial film 1201 is adjusted so that the concentration of Ge in the polished sacrificial film 1201 is higher toward the center and lower toward the upper and lower ends.

[0597] Then, if Figure 108 As shown above Figure 89 Similar to the steps in , the hard mask 1102 is removed by wet etching.

[0598] Then, if Figure 109 As shown above Figure 90 Similar to the steps in , a silicon film 1104 is formed on the upper surfaces of the semiconductor substrate 1101 and the sacrificial film 1201 by epitaxial growth.

[0599] Then, if Figure 110 As shown above Figure 91 Similar to the steps in , the silicon film 1104 is polished to a predetermined thickness by CMP.

[0600] Then, if Figure 111 As shown above Figure 92 The steps are similar to those in , forming a pixel circuit.

[0601] Then, if Figure 112 As shown above Figure 93 Similar to the steps in , a support substrate (not shown) is applied and the back side of the semiconductor substrate 1101 is thinned.

[0602] Figure 112 The subsequent image is vertically reversed to the previous image.

[0603] Then, if Figure 113As shown above Figure 94 Similar to the steps in FIG. 1 , a trench 1202 is formed on the back surface of the semiconductor substrate 1101. The top of the trench 1202 reaches the sacrificial film 1201.

[0604] Then, if Figure 114 As shown above Figure 95 Similar to the steps in FIG. 1 , the sacrificial film 1201 is removed by wet etching. Thus, a cavity 1203 is formed, which opens into the trench 1202 and extends perpendicularly to the trench 1202 and horizontally.

[0605] Here, as described above, the WER of sacrificial film 1201 is higher toward the center and lower toward the upper and lower ends. Therefore, after removing sacrificial film 1201, cavity 1203 becomes thicker as it approaches trench 1202 and thinner as it moves away from trench 1202. In other words, the cross-section of cavity 1203 is thickest at the junction with trench 1202 and gradually tapers toward the ends.

[0606] Then generate the light shielding film 1002, such as Figure 115 As shown. For example, an insulating film (not shown) is first formed on the surface of the groove 1202 and the cavity 1203. The insulating film is made of, for example, SiO2. The light shielding film 1002 is then embedded in the groove 1202 and the cavity 1203.

[0607] Here, this article will refer to Figure 116 The difference in the shape of the light-shielding film 1002 between the first manufacturing method and the second manufacturing method will be described. Figure 116 The upper portion of FIG. 1 schematically shows a cross section of the light shielding film 1002 generated in the first manufacturing method. Figure 116 The lower portion in FIG schematically shows a cross section of the light shielding film 1002 produced in the second manufacturing method.

[0608] In the first manufacturing method, the thickness of the cross section of the cavity 1106 (in which the horizontal light shielding portion 1002A is formed) is almost uniform, as described above with reference to FIG. Figure 96 Therefore, the thickness of the cross section of the horizontal light shielding portion 1002A is almost uniform, as shown in FIG. Figure 116 As shown in the upper part of .

[0609] Here, in the case where the light shielding film 1002 is embedded in the groove 1105 and the cavity 1106 by a method such as CVD, a material gas or a carrier gas is introduced into the groove 1105 from the entrance of the groove 1105. At this time, the material gas or the carrier gas may accumulate and may not sufficiently reach the inside of the cavity 1106. In particular, the material gas or the carrier gas is less likely to reach the end portion closer to the cavity 1106 and farther from the entrance of the groove 1105. Therefore, for example, voids 1251 and 1252 are caused in the horizontal light shielding portion 1002A, as shown in FIG. Figure 116 As shown in the upper part of , the light-shielding performance may be deteriorated.

[0610] On the other hand, in the second manufacturing method, the cross section of the cavity 1203 (in which the horizontal light shielding portion 1002A is formed) is gradually shrunk, as described above with reference to FIG. Figure 114 As described above, the cavity 1203 is thickest at the connection portion with the groove 1202 and becomes thinner toward the end portion.

[0611] Here, in the case where the light shielding film 1002 is embedded in the groove 1202 and the cavity 1203 from the entrance of the groove 1202 by a method such as CVD, the material gas or the carrier gas may accumulate and may not be enough to reach the inside of the cavity 1203, as described above. In particular, the material gas or the carrier gas is less likely to reach the end closer to the cavity 1203. However, because the cavity 1203 gradually shrinks and the connection with the groove 1202 is wider, the material gas or the carrier gas accumulates less. In addition, the end of the cavity 1203 gradually shrinks, so even if the amount of gas reaching the end of the cavity 1203 decreases, the cavity 1203 can be embedded without any gap. Therefore, a horizontal light shielding portion 1002A that gradually shrinks from the connection with the vertical light shielding portion 1002B to the end (opening 1002C) and has no gap can be formed, as shown in FIG. Figure 116 As shown in the lower part, the light-shielding performance can be maintained better.

[0612] The following will refer to Figures 117 to 119 The relationship between the depth of the groove 1202 and the shape of the horizontal light shielding portion 1002A will be described.

[0613] Figure 117 An exemplary shape of the horizontal light shielding portion 1002A in the case where the groove 1202 is formed at a shallow position on the surface of the sacrificial film 1201 is schematically shown. Figure 118 An exemplary shape of the horizontal light shielding portion 1002A in the case where the groove 1202 is formed to near the center of the sacrificial film 1201 is schematically shown. Figure 119 An exemplary shape of the horizontal light shielding portion 1002A in the case where the trench 1202 is formed deeper than the sacrificial film 1201 is schematically shown.

[0614] When the groove 1202 is formed at a shallow position on the surface of the sacrificial film 1201 , the cross-sectional shape of the horizontal light shielding portion 1002A does not gradually shrink to be vertically symmetrical, but gradually shrinks toward the groove 1202 (vertical light shielding portion 1002B).

[0615] On the other hand, the shape of the horizontal light shielding portion 1002A does not differ much between the case where the groove 1202 is formed to near the center of the sacrificial film 1201 and the case where the groove 1202 is formed deeper than the sacrificial film 1201. That is, the shape of the cross section of the horizontal light shielding portion 1002A gradually shrinks to be almost vertically symmetrical.

[0616] Returning to the description of the manufacturing method, Figure 98 Similar to the steps in FIG. 1 , a planarization film 1107, an on-chip color filter 1108, an on-chip microlens 1109, etc. are then formed on the back surface of the semiconductor substrate 1101, and the solid-state image sensing device 101k is completed, as shown in FIG. Figure 120 shown.

[0617] As described above, in the second manufacturing method, the cross section of the horizontal light shielding portion 1002A of the light shielding film 1002 is gradually shrunk, thereby forming the light shielding film 1002 having no voids and excellent light shielding properties.

[0618] This article discusses the conditions for the thickness of the gradually shrinking horizontal light shielding portion 1002A.

[0619] Figure 121 The above table shows the relationship between the material and thickness of the horizontal light shielding portion 1002A and the transmittance.

[0620] For example, when the horizontal light-shielding portion 1002A is made of W, the transmittance is -50 dB or less for a thickness of 80 nm or more, and -100 dB or less for a thickness of 180 nm or more. When the horizontal light-shielding portion 1002A is made of Ti, the transmittance is -50 dB or less for a thickness of 70 nm or more, and -100 dB or less for a thickness of 140 nm or more. When the horizontal light-shielding portion 1002A is made of Ta, the transmittance is -50 dB or less for a thickness of 70 nm or more, and -100 dB or less for a thickness of 150 nm or more. When the horizontal light-shielding portion 1002A is made of Al, the transmittance is -50 dB or less for a thickness of 40 nm or more, and -100 dB or less for a thickness of 70 nm or more.

[0621] The minimum value Dmin of the horizontal light shielding portion 1002A is determined by the material and required light shielding performance of the horizontal light shielding portion 1002A. It is assumed that the minimum value Dmin is the thickness at a position slightly away from the tip of the horizontal light shielding portion 1002A, not at the tip.

[0622] For example, it is assumed that the minimum value Dmin is the thickness at a position a predetermined distance from the top end of the horizontal light shielding portion 1002A (the end of the opening 1002C).

[0623] Alternatively, for example, assuming that the length from the connection between the horizontal light-shielding portion 1002A and the vertical light-shielding portion 1002B to the top of the horizontal light-shielding portion 1002A is L, the minimum value Dmin is assumed to be the thickness at a distance L x x (%) from the top of the horizontal light-shielding portion 1002A. x is set to, for example, 10% or less. More specifically, x is set to, for example, 0.5%, 1%, 3%, 5%, 7%, or 10%.

[0624] For example, in the case where the horizontal light-shielding portion 1002A is made of W and the transmittance is set to −50 dB or less, the minimum value Dmin of the horizontal light-shielding portion 1002A is set to 80 nm or more.

[0625] {Third Method of Manufacturing Solid-State Image Sensing Device 101k}

[0626] The following will refer to Figures 122 to 128 A third method for manufacturing the solid-state image sensing device 101 k is described below. The third manufacturing method uses the silicon-on-a-chip (SON) technology.

[0627] First, a plurality of grooves are formed perpendicular to the surface of the silicon semiconductor substrate 1301 at predetermined intervals, such as Figure 122 In addition, no trench is formed in the region 1301A, and the vertical terminal (electrode) portion 152AB of the TRX 152 is formed in the region 1301A.

[0628] At about 1100 degrees Figure 122 The semiconductor substrate 1301 in the embodiment of the present invention is subjected to an annealing process using H2 gas for about 10 minutes. Thus, a horizontal cavity 1301B is formed in the semiconductor substrate 1301, as shown in FIG. Figure 123 In addition, the top of cavity 1301B is slightly rounded.

[0629] The surface of the semiconductor substrate 1301 is then drilled to open into the cavity 1301B, as shown in FIG. Figure 124 Then, a reinforcement film 1302 having a predetermined mechanical strength is embedded in the cavity 1301B through the hole and epitaxially grown. In addition, polysilicon 1303 is formed around the hole in the surface of the semiconductor substrate 1301.

[0630] In addition, the reinforcement film 1302 may be, for example, an oxide film such as SiO 2 , a high-k film, or a laminated film of a high-k film and an oxide film.

[0631] For example, when using directly Figure 123In the case of the semiconductor substrate 1301 in the middle, the horizontal cavity 1301B is formed, so the semiconductor substrate 1301 may be deformed or damaged during processing. In contrast, the cavity 1301B is embedded together with the reinforcement film 1302, so that the mechanical strength of the semiconductor substrate 1301 is enhanced, thereby preventing the semiconductor substrate 1301 from being deformed or damaged.

[0632] With the above Figure 92 The steps are similar to those in , and then the pixel circuit is formed, such as Figure 125 shown.

[0633] Then, with the above Figure 93 Similar to the steps in , a support substrate (not shown) is applied, and the back side of the semiconductor substrate 1301 is thinned, as shown in FIG. Figure 126 shown.

[0634] in addition, Figure 126 The subsequent image is vertically reversed to the previous image.

[0635] With the above Figure 94 Similar to the steps in FIG. 1 , a trench 1301C is then formed on the back side of the semiconductor substrate 1301, as shown in FIG. Figure 127 At this time, if the reinforcement film 1302 is not provided, the trench 1301C passes through the cavity 1301B, and the semiconductor substrate 1301 can be dug deeper than assumed. However, the trench 1301C is blocked by the reinforcement film 1302, thereby preventing the semiconductor substrate 1301 from being dug deeper than assumed.

[0636] Furthermore, the reinforcement film 1302 is removed by wet etching using a solution such as ammonium, and the cavity 1301B is formed again. At this time, the polysilicon 1303 formed after the reinforcement film 1302 is formed is not removed and remains in the above Figure 124 In the steps for forming the holes of the reinforcing film 1302.

[0637] Then generate the light shielding film 1002, such as Figure 128 As shown. For example, an insulating film (not shown) is first formed on the surface of the groove 1301C and the cavity 1301B. The insulating film is made of, for example, SiO2. The light shielding film 1002 is then embedded in the groove 1301C and the cavity 1301B.

[0638] As above Figure 98 or Figure 113 As described above, on-chip color filters and on-chip microlenses are then formed, so that the solid-state image sensing device 101k is completed.

[0639] This article will refer to Figure 129The structural difference between the case where a cavity is formed on a semiconductor substrate by wet etching using a sacrificial film to form the horizontal light shielding portion 1002A as in the first manufacturing method and the case where a cavity is formed on a semiconductor substrate using SON to form the horizontal light shielding portion 1002A as in the third manufacturing method is described. Figure 129 The upper portion in Schematic diagram schematically illustrates an exemplary shape of the light-shielding film 1002 formed in the first manufacturing method, and the lower portion schematically illustrates an exemplary shape of the light-shielding film 1002 formed in the third manufacturing method.

[0640] In the former case, the cross-sectional shape at the top end of the horizontal light shielding portion 1002A (the end of the opening 1002C) is almost rectangular. On the other hand, in the latter case, the cross-sectional shape at the top end of the horizontal light shielding portion 1002A (the end of the opening 1002C) is not rectangular but circular.

[0641] Furthermore, in the latter case, polysilicon 1303 that blocks the hole for embedding the reinforcement film 1302 is formed on the surface of the semiconductor substrate 1301. On the other hand, in the former case, no counterpart to the polysilicon 1303 is formed on the surface of the semiconductor substrate 1101.

[0642] <12. Twelfth Embodiment>

[0643] The following will refer to Figures 130 to 139 A twelfth embodiment of the present technology will be described.

[0644] {Exemplary Configuration of Solid-State Image Sensing Device 1011}

[0645] Figure 130 A cross section of a solid-state image sensing device 1011 according to a twelfth embodiment of the present technology is schematically shown. Figure 130 A cross section of a portion including two pixels in the solid-state image sensing device 1011 is shown, but other pixels have basically the same configuration.

[0646] In addition, with Figure 84 The corresponding parts in the figure are represented by the same figure marks, and their descriptions are omitted as needed.

[0647] Figure 130 The solid-state image sensing device 1011 in Figure 84 The solid-state image sensing device 101 k in FIG. 1 is different in the shape of the PD 151 and the gate terminal (electrode) 152A of the TRX 152 .

[0648] The PD 151 in the solid-state image sensing device 1011 is composed of a main body 151A and a protruding plug 151B.

[0649] The main body 151A has substantially the same shape as the PD 151 in the solid-state image sensing device 101k. The side surfaces of the main body 151A are surrounded by vertical light shielding portions 1002B of the light shielding film 1002. The upper surface of the main body 151A is covered by horizontal light shielding portions 1002A of the light shielding film 1002, excluding the opening 1002C.

[0650] The plug 151B extends vertically upward from the upper surface of the main body 151A and extends from the horizontal light shielding portion 1002A to the MEM 154 via the opening 1002C of the light shielding film 1002. The top end of the plug 151B then reaches near the surface of the semiconductor substrate 1001.

[0651] On the other hand, the gate terminal (electrode) 152A of TRX 152 differs from the gate terminal (electrode) 152A in the solid-state image sensing device 101k in that the vertical terminal (electrode) portion 152AB is not provided and only the portion corresponding to the horizontal terminal (electrode) portion 152AA is provided.

[0652] Therefore, even when incident light is not absorbed by the main body 151A of the PD 151 and passes through the opening 1002C of the light shielding film 1002, the incident light is absorbed by the plug 151B of the PD 151 in the solid-state image sensing device 101k. Thus, charges generated by light passing through the opening 1002C of the light shielding film 1002 are prevented from invading the MEM 154 or the FD 156, and the occurrence of noise is prevented.

[0653] {Method of Manufacturing Solid-State Image Sensing Device 1011}

[0654] The following will refer to Figures 131 to 139 A method of manufacturing the solid-state image sensing device 1011 will be described.

[0655] A high concentration boron (B) layer 1401 extending in the horizontal direction is first formed in the semiconductor substrate 1001, as shown in FIG. Figure 131 As shown in FIG. Furthermore, opening 1401A is formed in B layer 1401 at a position formed by opening 1002C of light shielding film 1002. Furthermore, it is assumed that the layer below B layer 1401 in semiconductor substrate 1001 is a silicon supporting layer, and the layer above B layer 1401 is a silicon active layer.

[0656] The active layer in the semiconductor substrate 1001 is then epitaxially grown, as Figure 132 shown.

[0657] Then, impurity ions are implanted into the semiconductor substrate 1001, and the body 151A of the PD 151 is formed in a layer lower than the B layer 1401, as shown in FIG. Figure 133 shown.

[0658] Then, impurity ions are implanted into the semiconductor substrate 1001 to form the plug 151B of the PD 151, as shown in FIG. Figure 134 The plug 151B protrudes vertically upward from the upper surface of the body 151A, passes through the opening 1401A of the B layer 1401 , and reaches near the surface of the semiconductor substrate 1001 .

[0659] Then form the pixel circuit, such as Figure 135 That is, a gate terminal (electrode) 152A, a MEM 154, a gate terminal (electrode) 155A, the SD 1003, the SD 1004, a gate terminal (electrode) 1005A, etc. are formed. In addition, for example, a wiring layer (not shown) is formed on the semiconductor substrate 1001.

[0660] Then, if Figure 136 As shown above Figure 93 Similar to the steps in , a support substrate (not shown) is applied and the back side of the semiconductor substrate 1001 is thinned.

[0661] in addition, Figure 136 The subsequent image is vertically reversed to the previous image.

[0662] Then, if Figure 137 As shown above Figure 94 Similar to the steps in , a trench 1001A is formed on the back surface of the semiconductor substrate 1001.

[0663] Then, if Figure 138 As shown above Figure 95 Similar to the steps in FIG. 1 , the B layer 1401 is removed by wet etching. Thus, a cavity 1001B is formed, which opens into the trench 1001A, extends perpendicular to the trench 1001A and extends in the horizontal direction.

[0664] Then generate the light shielding film 1002, such as Figure 139 As shown. For example, an insulating film (not shown) is first formed on the surface of the trench 1001A and the cavity 1001B. The insulating film is made of, for example, SiO2. A light shielding film 1002 is then embedded in the trench 1001A and the cavity 1001B.

[0665] Then, the on-chip color filters and on-chip microlenses are formed, as shown above. Figure 98 or Figure 113 As described above, the solid-state image sensing device 1011 is completed.

[0666] <13. Thirteenth embodiment>

[0667] The following will refer to Figure 140 A thirteenth embodiment of the present technology will be described.

[0668] {Exemplary Configuration of Solid-State Image Sensing Device 101m}

[0669] Figure 140 A cross section of a solid-state image sensing device 101m according to a thirteenth embodiment of the present technology is schematically shown. Figure 130 The corresponding parts in the figure are represented by the same figure marks, and their descriptions are omitted as needed.

[0670] Figure 140 The solid-state image sensing device 101m and Figure 130 The solid-state image sensing device 1011 in FIG. 101 is different in the shape of the PD 151. That is, a cover 151C is formed at the top end of the plug 151B in the PD 151 in the solid-state image sensing device 101m.

[0671] The cover 151C extends from the top end of the plug 151B along the upper surface of the semiconductor substrate 1001 parallel to the upper surface of the body 151A and opposite to the MEM 154 .

[0672] Among the light that is not absorbed by the main body 151A of the PD 151 and passes through the opening 1002C of the light shielding film 1002, the dotted light with a small incident angle is incident on the plug 151B and is easily absorbed. On the other hand, the solid oblique light with a large incident angle is likely to pass through the plug 151B. This also applies to the diffracted light that passes through the opening 1002C.

[0673] Therefore, the cover 151C is provided at the top end of the plug 151B so that light that is not absorbed by the plug 151B and passes through the plug 151B can be absorbed by the cover 151C. Therefore, it is possible to prevent charges generated by light that passes through the opening 1002C of the light shielding film 1002 from invading the MEM 154 or the FD 156, and it is possible to more effectively prevent the occurrence of noise.

[0674] <14. Fourteenth embodiment>

[0675] The following will refer to Figure 141 A fourteenth embodiment of the present technology will be described.

[0676] {Exemplary Configuration of Solid-State Image Sensing Device 101n}

[0677] Figure 141 A cross section of a solid-state image sensing device 101n according to a fourteenth embodiment of the present technology is schematically shown. Figure 130 The corresponding parts in the figure are represented by the same figure marks, and their descriptions are omitted as needed.

[0678] Figure 141 The solid-state image sensing device 101n in Figure 130The solid-state image sensing device 101l shown in FIG. 1 differs from the solid-state image sensing device 101n in the positions of the opening 1002C of the light shielding film 1002, the plug 151B of the PD 151, the SDs 1003 and 1004, and the gate terminal (electrode) 1005A. Specifically, the solid-state image sensing device 101n differs from the solid-state image sensing device 101l in that the opening 1002C and the plug 151B are positioned closer to the vertical light shielding portion 1002B (the end of the pixel). In addition, the SDs 1003 and 1004 and the gate terminal (electrode) 1005A are shifted to the right of the FD 156.

[0679] In this manner, opening 1002C of light-shielding film 1002 is positioned closer to vertical light-shielding portion 1002B. Consequently, oblique light with a large incident angle rarely passes through opening 1002C, as indicated by the solid arrow in the figure. Consequently, the majority of light passing through opening 1002C is light with a small incident angle, and light passing through opening 1002C is more likely to be absorbed by plug 151B. Consequently, charges generated by light passing through opening 1002C of light-shielding film 1002 can be prevented from intruding into MEM 154 or FD 156, effectively preventing the occurrence of noise.

[0680] <15. Fifteenth embodiment>

[0681] The following will refer to Figure 142 and Figure 143 A fifteenth embodiment of the present technology will be described.

[0682] {Exemplary Configuration of Solid-State Image Sensing Device 101o}

[0683] Figure 142 A cross section of a solid-state image sensing device 101 o according to a fifteenth embodiment of the present technology is schematically shown. Figure 143 1 is a top view schematically showing an exemplary configuration of a device forming surface of a semiconductor substrate 1001 in a solid-state image sensing device 101o. Figure 141 The corresponding parts in the figure are represented by the same figure marks, and their descriptions are omitted as needed.

[0684] Figure 142 The solid-state image sensing device 101o and Figure 141 The solid-state image sensing device 101 n in FIG. 1 is different in that a gate terminal (electrode) 157A forming an OFG 157 and a discharge unit (OFD) 1501 are provided.

[0685] A gate terminal (electrode) 157A of the OFG 157 is formed on the left side of the plug 151B of the PD 151 on the device formation surface of the semiconductor substrate 1001 .

[0686] The OFD 1501 is formed on the left side of the gate terminal (electrode) 157A of the OFG 157 and at the end portion of the pixel around the surface of the semiconductor substrate 1001 .

[0687] When the drive signal OFG applied to the gate terminal (electrode) 157A of the OFG 157 is turned on and the OFG 157 is turned on, the charge accumulated in the PD 151 is transferred to the OFD 1501 via the OFG 157 to be discharged to the outside. Thus, the PD 151 is reset.

[0688] Furthermore, oblique light passing through the opening 1002C of the light shielding film 1002 is incident on the OFD 1501, as indicated by the solid arrow in the figure. Charge generated by the light incident on the OFD 1501 is then discharged from the OFD 1501 to the outside. Therefore, charge generated by light passing through the opening 1002C of the light shielding film 1002 can be prevented from intruding into the MEM 154 or the FD 156, and the occurrence of noise can be more effectively prevented.

[0689] In addition, the OFD 1501 does not necessarily need to be arranged between adjacent pixels. For example, when oblique light having a predetermined incident angle passes through the opening 1002C of the light shielding film 1002, the OFD 1501 is arranged at a position where the oblique light is incident.

[0690] <16. Sixteenth embodiment>

[0691] The following will refer to Figure 144 A sixteenth embodiment of the present technology will be described.

[0692] {Exemplary Configuration of Solid-State Image Sensing Device 101p}

[0693] Figure 144 A cross section of a solid-state image sensing device 101p according to a sixteenth embodiment of the present technology is schematically shown. Figure 142 The corresponding parts in the figure are represented by the same figure marks, and their descriptions are omitted as needed.

[0694] Figure 144 The solid-state image sensing device 101p in Figure 142 The solid-state image sensing device 101o shown in FIG. 1 is different in that the gate terminal (electrode) 158A of the RST 158 is added, the position of the OFD 1501 is different, and the SD 1003, SD 1004, and gate terminal (electrode) 1005A are deleted. Furthermore, the SD 1003, SD 1004, and gate terminal (electrode) 1005A are not actually deleted, and are arranged at different positions in the solid-state image sensing device 101p.

[0695] A gate terminal (electrode) 158A of the RST 158 is formed on the right side of the FD 156 on the device formation surface of the semiconductor substrate 1001 .

[0696] The OFD 1501 is disposed between adjacent pixels P1 and P2. More specifically, the OFD 1501 is disposed between the gate terminal (electrode) 158A of the RST 158 in the pixel P1 and the gate terminal (electrode) 157A of the OFG 157 in the pixel P2 around the surface of the semiconductor substrate 1001.

[0697] For example, when the driving signal RST applied to the gate terminal (electrode) 158A of the RST 158 in the pixel P1 is turned on and the RST 158 is turned on, the charge accumulated in the FD 156 is transferred to the OFD 1501 via the RST 158 to be discharged to the outside.

[0698] When the OFG 157 is turned on, the charge accumulated in the PD 151 is transferred to the OFD 1501 via the OFG 157 to be discharged to the outside.

[0699] Therefore, the OFD 1501 is shared between the pixel P1 and the pixel P2 adjacent to each other in the solid-state image sensing device 101 p .

[0700] Furthermore, as in the solid-state image sensing device 101o, in the solid-state image sensing device 101p, oblique light passing through the opening 1002C of the light shielding film 1002 is incident on the OFD 1501. Charge generated by the light incident on the OFD 1501 is then discharged to the outside from the OFD 1501. Therefore, charge generated by light passing through the opening 1002C of the light shielding film 1002 can be prevented from intruding into the MEM 154 or the FD 156, and the occurrence of noise can be more effectively prevented.

[0701] <17. Seventeenth embodiment>

[0702] The following will refer to Figure 145 A seventeenth embodiment of the present technology will be described.

[0703] {Exemplary Configuration of Solid-State Image Sensing Device 101q}

[0704] Figure 145 17 is a top view schematically showing an exemplary configuration of a device forming surface of a solid-state image sensing device 101q according to a seventeenth embodiment of the present technology. Figure 144The corresponding parts in the figure are represented by the same figure marks, and their descriptions are omitted as needed.

[0705] Figure 145 The exemplary configuration of the device forming surface of the pixels P1 and P2 in the solid-state image sensing device 101q is schematically shown. In this example, the pixels P1 and P2 are arranged side by side in the figure, and the layouts of the pixels P1 and P2 are symmetrical to each other.

[0706] In addition, the solid-state image sensing device 101q and Figure 144 The solid-state image sensing device 101 p in FIG. 1 is different in that a pixel P1 and a pixel P2 adjacent to each other share not only the OFD 1501 but also the FD 156 .

[0707] <18. Eighteenth embodiment>

[0708] The following will refer to Figure 146 An eighteenth embodiment of the present technology will be described.

[0709] {Exemplary Configuration of Solid-State Image Sensing Device 101r}

[0710] Figure 146 1 is a top view schematically showing an exemplary configuration of a device forming surface of a solid-state image sensing device 101r according to an eighteenth embodiment of the present technology. Figure 145 The corresponding parts in the figure are represented by the same figure marks, and their descriptions are omitted as needed.

[0711] Solid-state image sensing device 101r and Figure 145 The solid-state image sensing device 101q in FIG. 1 is different in that a dummy opening 1551L is formed in the pixel P1 and a dummy opening 1551R is formed in the pixel P2.

[0712] A dummy opening 1551L is formed in pixel P1 at a position corresponding to the position where the plug 151B of the PD 151 in pixel P2 is formed (or the position where the opening 1002C (not shown) of the light shielding film 1002 in pixel P2 is formed). The dummy opening 1551L has substantially the same size as the opening 1002C of the light shielding film 1002.

[0713] A dummy opening 1551R is formed in pixel P2 at a position corresponding to the position where the plug 151B of the PD 151 in pixel P1 is formed (or the position where the opening 1002C (not shown) of the light shielding film 1002 in pixel P1 is formed). The dummy opening 1551R has substantially the same size as the opening 1002C of the light shielding film 1002.

[0714] Therefore, opening 1551L and opening 1551R are respectively provided at substantially the same positions in pixel P1 and pixel P2 to be symmetrical with each other. Thus, the optical characteristics of the oblique light indicated by the arrows in the figure can be adjusted in pixel P1 and pixel P2, for example. Thus, color variations or brightness variations between pixels can be limited.

[0715] <19. Modifications>

[0716] Although the description has been made on the case where the cross section of the light shielding film is assumed to gradually shrink in the second manufacturing method according to the eleventh embodiment of the present technology, films other than the light shielding film may gradually shrink in this manufacturing method.

[0717] Furthermore, for example, a portion of the side surface of the PD may not be surrounded by the light shielding film as necessary.

[0718] Furthermore, the present technology can be applied to a solid-state image sensing device in a system other than the global shutter system or, for example, a surface illumination type solid-state image sensing device within the applicable range.

[0719] In addition, although each of the above embodiments has been described assuming that electrons are essentially electric charges, the present technology can be applied to a case where holes are assumed to be electric charges. In addition, in each of the above circuit configurations, the polarity of the transistors (N-type MOS transistors and P-type MOS transistors) can be interchanged.

[0720] <20. Exemplary Applications of Solid-State Image Sensing Device>

[0721] Figure 147 2 is a diagram illustrating an exemplary application of a solid-state image sensing device.

[0722] The above-described solid-state image sensing device can be used in various situations for sensing light such as visible light, infrared light, ultraviolet light, and X-rays, as described below.

[0723] A device for capturing images for viewing, such as a digital camera or a portable device equipped with a camera

[0724] Traffic devices, such as in-vehicle sensors for capturing images of the front, rear, and surrounding areas of a car and its interior for safe driving (such as automatic stopping) or recognizing the driver's status, surveillance cameras for monitoring traveling vehicles or roads, and distance measurement sensors for measuring the distance between vehicles

[0725] Home appliances such as TVs, refrigerators, and air conditioners, which can capture user gestures and operate the devices based on them

[0726] Medical or healthcare devices, such as endoscopes or angiography devices that use infrared light

[0727] Security devices such as surveillance cameras or personal authentication cameras for crime prevention

[0728] Beauty care devices, such as skin measurement devices for photographing skin or microscopes for photographing head skin

[0729] Sports devices, such as action cameras or wearable sports cameras

[0730] Agricultural equipment, such as cameras used to monitor the status of fields or crops

[0731] {Camera}

[0732] Figure 148 17 is a block diagram showing an exemplary configuration of a photographing device (camera device) 1701 as an exemplary electronic device to which the present technology is applied.

[0733] like Figure 148 As shown, the camera 1701 has an optical system including a lens 1711, an imaging device 1712, a DSP circuit 1713 as a camera signal processing unit, a frame memory 1714, a display device 1715, a recording device 1716, an operating system 1717, a power supply system 1718, etc. The DSP circuit 1713, the frame memory 1714, the display device 1715, the recording device 1716, the operating system 1717, and the power supply system 1718 are connected to each other via a bus 1719.

[0734] The lens group 1711 captures incident light (image light) from a subject and forms an image on the imaging surface of the imaging device 1712. The imaging device 1712 converts the amount of incident light formed as an image on the imaging surface by the lens group 1711 into an electrical signal in units of pixels and outputs the electrical signal as a pixel signal.

[0735] The display device 1715 is configured from a panel-type display device such as a liquid crystal display device or an organic electroluminescent (EL) display device, and displays the moving image or still image captured by the imaging device 1712. The recording device 1716 records the moving image or still image captured by the imaging device 1712 in a recording medium such as a memory card, a videotape, or a digital versatile disk (DVD).

[0736] In response to user operations, the operating system 1717 issues operating commands for various functions of the imaging device 1701. The power supply system 1718 supplies power to the DSP circuit 1713, the frame memory 1714, the display device 1715, the recording device 1716, and the operating system 1717 as needed.

[0737] The camera 1701 is suitable for use as an additional camera module for a video camera or a digital still camera, as well as a mobile device such as a smartphone or a cellular phone. Furthermore, the solid-state image sensing device according to each of the above embodiments can be used as the imaging device 1712 in the camera 1701. Thus, the image quality of the camera 1701 can be improved.

[0738] In addition, the embodiments of the present technology are not limited to the above-described embodiments, and various changes can be made without departing from the spirit of the present technology.

[0739] For example, each of the above embodiments can be combined within a feasible range. For example, the fourth embodiment, the ninth embodiment, or the eighteenth embodiment can be combined with other embodiments.

[0740] Furthermore, for example, the present technology can adopt the following configurations.

[0741] (1) A solid-state image sensing device comprising:

[0742] Photoelectric conversion unit;

[0743] a charge holding unit for holding the charge transferred from the photoelectric conversion unit;

[0744] a first transfer transistor for transferring the charge from the photoelectric conversion unit to the charge holding unit; and

[0745] The light shielding portion includes a first light shielding portion and a second light shielding portion,

[0746] wherein the first light shielding portion is arranged between a second surface opposite to a first surface as a light receiving surface of the photoelectric conversion unit and the charge holding unit and covers the second surface, and is formed with a first opening, and

[0747] The second light shielding portion surrounds a side surface of the photoelectric conversion unit.

[0748] (2) The solid-state image sensing device according to (1),

[0749] The cross section of the first light shielding portion gradually shrinks from the connection portion with the second light shielding portion toward the first opening.

[0750] (3) The solid-state image sensing device according to (1) or (2), further comprising:

[0751] A third light shielding portion is configured to cover at least a surface of the charge holding unit opposite to a surface opposing the first light shielding portion at a position away from the first light shielding portion from a device forming surface on which the first transfer transistor is formed.

[0752] (4) The solid-state image sensing device according to any one of (1) to (3),

[0753] The gate electrode of the first transfer transistor includes a first electrode portion parallel to the first light shielding portion and a second electrode portion perpendicular to the first light shielding portion and extending from the first light shielding portion closer to the charge holding unit to the photoelectric conversion unit via the first opening.

[0754] (5) The solid-state image sensing device according to (4), further comprising:

[0755] A fourth light-shielding portion is connected to the first light-shielding portion and is at least partially arranged closer to the charge holding unit than to the first light-shielding portion and is arranged parallel to the second surface at a position different from that of the second light-shielding portion.

[0756] (6) The solid-state image sensing device according to (4),

[0757] wherein the photoelectric conversion unit is formed on a first semiconductor substrate,

[0758] The charge holding unit is formed on the second semiconductor substrate,

[0759] The first transfer transistor is formed on the first semiconductor substrate and the second semiconductor substrate, and

[0760] A bonding interface between the first semiconductor substrate and the second semiconductor substrate is formed in a channel of the first transfer transistor.

[0761] (7) The solid-state image sensing device according to (6),

[0762] The bonding interface is formed closer to a drain terminal of the transfer transistor than to a source terminal of the transfer transistor.

[0763] (8) The solid-state image sensing device according to (6) or (7),

[0764] wherein the second light shielding portion is formed by the second surface of the photoelectric conversion unit,

[0765] The device further comprises:

[0766] A fifth light-shielding portion is formed by the first surface of the photoelectric conversion unit and connected to the second light-shielding portion.

[0767] (9) The solid-state image sensing device according to any one of (1) to (5),

[0768] The photoelectric conversion unit, the charge holding unit, and the first transfer transistor are made of single crystal silicon.

[0769] (10) The solid-state image sensing device according to any one of (1) to (3),

[0770] wherein the photoelectric conversion unit includes a protrusion extending from the second surface via the first opening from the first light shielding portion toward the charge holding unit.

[0771] (11) The solid-state image sensing device according to (10),

[0772] The protrusion extends from the first light shielding portion toward the charge holding unit in parallel with the second surface.

[0773] (12) The solid-state image sensing device according to (10), further comprising:

[0774] a discharge unit for discharging charges accumulated in the photoelectric conversion unit,

[0775] The discharge cell is arranged at a position where light having a predetermined incident angle is incident when the light passes through the first opening.

[0776] (13) The solid-state image sensing device according to (12),

[0777] The discharge unit is arranged between a first pixel and a second pixel adjacent to each other, and is shared by the first pixel and the second pixel.

[0778] (14) The solid-state image sensing device according to (13),

[0779] wherein the first openings are respectively arranged near discharge cells in the first pixel and the second pixel,

[0780] A second opening having substantially the same size as the first opening is formed in the first pixel at a position corresponding to the first opening in the second pixel, and

[0781] A third opening having substantially the same size as the first opening is formed in the second pixel at a position corresponding to the first opening in the first pixel.

[0782] (15) The solid-state image sensing device according to (1),

[0783] wherein the sacrificial film constituting the first light shielding portion is made of SiGe, and

[0784] The device further comprises:

[0785] Alignment marks made of the sacrificial film that is not removed and remains.

[0786] (16) The solid-state image sensing device according to (1),

[0787] The cross section of the first light shielding portion is circular at the first opening.

[0788] (17) The solid-state image sensing device according to any one of (1) to (16), further comprising:

[0789] a charge-to-voltage conversion unit; and

[0790] a second transfer transistor for transferring the charge held in the charge holding unit to the charge-voltage conversion unit,

[0791] The first light shielding portion is arranged between the second surface of the photoelectric conversion unit and the charge holding unit and the charge-voltage conversion unit.

[0792] (18) An electronic device comprising a solid-state image sensing device, the solid-state image sensing device comprising:

[0793] Photoelectric conversion unit;

[0794] a charge holding unit for holding the charge transferred from the photoelectric conversion unit;

[0795] a first transfer transistor for transferring the charge from the photoelectric conversion unit to the charge holding unit; and

[0796] The light shielding portion includes a first light shielding portion and a second light shielding portion,

[0797] wherein the first light shielding portion is arranged between a second surface opposite to a first surface as a light receiving surface of the photoelectric conversion unit and the charge holding unit and covers the second surface, and is formed with a first opening, and

[0798] The second light shielding portion surrounds a side surface of the photoelectric conversion unit.

[0799] (19) A solid-state image sensing device comprising:

[0800] Photoelectric conversion unit;

[0801] a charge holding unit for holding the charge transferred from the photoelectric conversion unit;

[0802] a transfer transistor for transferring the charge from the photoelectric conversion unit to the charge holding unit; and

[0803] The light shielding portion includes a first light shielding portion and a second light shielding portion formed with an opening,

[0804] wherein the first light shielding portion is arranged parallel to a light receiving surface of the photoelectric conversion unit and between the photoelectric conversion unit and the charge holding unit, and covers the photoelectric conversion unit except for the opening, and

[0805] The second light shielding portion surrounds a side surface of the photoelectric conversion unit.

[0806] Reference Signs List

[0807] 101a to 101r solid-state image sensing devices

[0808] 111 Pixel array unit

[0809] 112 vertical drive units

[0810] 113 Ramp Module

[0811] 116 horizontal drive unit

[0812] 117 System Control Unit

[0813] 118 signal processing unit

[0814] 151 PD

[0815] 151A Main Body

[0816] 151B Plug

[0817] 151C lid

[0818] 152 TRX

[0819] 152A Gate terminal (electrode)

[0820] 152AA horizontal terminal (electrode) part

[0821] 152AB vertical terminal (electrode) part

[0822] 153 TRM

[0823] 153A Gate terminal (electrode)

[0824] 154 MEM

[0825] 155 TRG

[0826] 155A Gate terminal (electrode)

[0827] 156 FD

[0828] 157 OFG

[0829] 157A Gate terminal (electrode)

[0830] 157AA horizontal terminal (electrode) part

[0831] 157AB vertical terminal (electrode) part

[0832] 158 RST

[0833] 158A Gate terminal (electrode)

[0834] 159 AMP

[0835] 159A Gate terminal (electrode)

[0836] 160 SEL

[0837] 160A Gate terminal (electrode)

[0838] 201 first semiconductor substrate

[0839] 201A Groove

[0840] 202 second semiconductor substrate

[0841] 203 Logical Layer

[0842] 216 N-type semiconductor region

[0843] 217 P+ type semiconductor region

[0844] 219 Shading part

[0845] 219A horizontal shading part

[0846] 219B vertical shading part

[0847] 219C Opening

[0848] 226 N++ type semiconductor region

[0849] 228 P-type semiconductor region

[0850] 231 N+ type semiconductor region

[0851] 310 Silicon Film

[0852] 312 Groove

[0853] 401 shading film

[0854] 411 shading film

[0855] 451 N-type semiconductor region

[0856] 452 P+ type semiconductor region

[0857] 453 shading film

[0858] 453A horizontal shading part

[0859] 453B vertical shading part

[0860] 453C Opening

[0861] 462 N++ type semiconductor region

[0862] 468 N+ type semiconductor region

[0863] 501 shading film

[0864] 501A horizontal shading part

[0865] 601 N-type semiconductor region

[0866] 602 P+ type semiconductor region

[0867] 603 shading film

[0868] 603A, 603B opening

[0869] 701A First Floor

[0870] 701B Second Floor

[0871] 702 Pixel Array Unit

[0872] 703 Latch Circuit

[0873] 751 ADC Circuit

[0874] 801 Semiconductor Substrate

[0875] 802 N-type semiconductor region

[0876] 804 shading film

[0877] 804A horizontal shading part

[0878] 804B vertical shading unit

[0879] 804C vertical shading unit

[0880] 804D horizontal shading part

[0881] 804E Opening

[0882] 806 P-type semiconductor region

[0883] 808 N-type semiconductor region

[0884] 809 N-type semiconductor region

[0885] 853 Grooves

[0886] 1001 Semiconductor Substrate

[0887] 1001A Groove

[0888] 1001B cavity

[0889] 1002 shading film

[0890] 1002A horizontal shading part

[0891] 1002B vertical shading part

[0892] 1002C Opening

[0893] 1101 Semiconductor Substrate

[0894] 1103 sacrificial film

[0895] 1103A Opening

[0896] 1103B, 1103C residues

[0897] 1104 Silicon Film

[0898] 1105 Groove

[0899] 1106 cavity

[0900] 1201 sacrificial film

[0901] 1202 Groove

[0902] 1203 cavity

[0903] 1301 Semiconductor Substrate

[0904] 1301B cavity

[0905] 1301C Groove

[0906] 1302 reinforcement film

[0907] 1303 polysilicon

[0908] 1401 Boron Layer

[0909] 1501 OFD

[0910] 1551L, 1551R virtual opening

[0911] 1701 Filming Device

[0912] 1712 Imaging device.

Claims

1. A solid-state image sensing device comprising: a photoelectric conversion unit including a main body and a protruding plug; a charge holding unit for holding the charge transferred from the photoelectric conversion unit; a discharge transistor for resetting the photoelectric conversion unit, and a first light shielding portion arranged between a second surface of the main body of the photoelectric conversion unit opposite to the first surface as the light receiving surface and the charge holding unit and covering the second surface, and formed with a first opening, wherein a portion of the discharge transistor is formed to overlap with the first light shielding portion in a stacking direction of the solid-state image sensing device, and The protruding plug extends from the second surface and extends toward the charge retention unit through the first opening.

2. The solid-state image sensing device according to claim 1 , further comprising: A second light shielding portion surrounds a side surface of the main body of the photoelectric conversion unit.

3. The solid-state image sensing device according to claim 1 , further comprising: A first transfer transistor is configured to transfer the charge from the photoelectric conversion unit to the charge holding unit.

4. The solid-state image sensing device according to claim 1, in, The charge holding unit is formed to overlap with the first light shielding portion in the stacking direction of the solid-state image sensing device.

5. The solid-state image sensing device according to claim 3, in, The photoelectric conversion unit is formed on a first semiconductor substrate. The charge holding unit is formed on the second semiconductor substrate, The first transfer transistor is formed over the first semiconductor substrate and the second semiconductor substrate.

6. The solid-state image sensing device according to claim 5, in, The gate electrode of the first transfer transistor is composed of a horizontal terminal portion formed on a device formation surface of the second semiconductor substrate and a vertical terminal portion extending vertically downward from the horizontal terminal portion to the photoelectric conversion unit.

7. The solid-state image sensing device according to claim 3 , further comprising: a second transfer transistor for transferring the charge held in the charge holding unit to a floating diffusion region; an amplifying transistor for reading out the charge in the floating diffusion region; and The selection transistor is used to select a pixel so that the signal of the pixel outputted from the amplification transistor is read to the vertical signal line.

8. A solid-state image sensing device comprising: a photoelectric conversion unit including a main body and a protruding plug; a charge holding unit for holding the charge transferred from the photoelectric conversion unit; a discharge transistor, configured to reset the photoelectric conversion unit; a first light shielding portion arranged between a second surface of the main body of the photoelectric conversion unit opposite to the first surface as a light receiving surface and the charge holding unit and covering the second surface, and formed with a first opening and a second opening, and a second light shielding portion formed between the photoelectric conversion units in adjacent pixels; wherein a portion of the discharge transistor is formed to overlap with the second light shielding portion in a stacking direction of the solid-state image sensing device, and The protruding plug extends from the second surface and extends toward the charge retention unit through the first opening.

9. The solid-state image sensing device according to claim 8, further comprising: A first transfer transistor is configured to transfer the charge from the photoelectric conversion unit to the charge holding unit.

10. The solid-state image sensing device according to claim 8, wherein The charge holding unit is formed to overlap with the first light shielding portion in the stacking direction of the solid-state image sensing device.

11. The solid-state image sensing device according to claim 9, in, The photoelectric conversion unit is formed on a first semiconductor substrate. The charge holding unit is formed on the second semiconductor substrate, The first transfer transistor is formed over the first semiconductor substrate and the second semiconductor substrate.

12. The solid-state image sensing device according to claim 11, in, The gate electrode of the first transfer transistor is composed of a horizontal terminal portion formed on a device formation surface of the second semiconductor substrate and a vertical terminal portion extending vertically downward from the horizontal terminal portion to the photoelectric conversion unit.

13. The solid-state image sensing device according to claim 11, in, The gate electrode of the discharge transistor is composed of a horizontal terminal portion formed on the device formation surface of the second semiconductor substrate and a vertical terminal portion extending vertically downward from the horizontal terminal portion to the photoelectric conversion unit.

14. The solid-state image sensing device according to claim 9, further comprising: a second transfer transistor for transferring the charge held in the charge holding unit to a floating diffusion region; an amplifying transistor for reading out the charge in the floating diffusion region; and The selection transistor is used to select a pixel so that the signal of the pixel outputted from the amplification transistor is read to the vertical signal line.

15. The solid-state image sensing device according to claim 9, in, A gate electrode of the first transfer transistor is arranged above the first opening.

16. The solid-state image sensing device according to claim 10, in, A gate electrode of the discharge transistor is arranged above the second opening.

17. An electronic device comprising the solid-state image sensing device according to any one of claims 1 to 16.

Images