Electronic circuit, drive circuit, and control system

Abstract

To provide an electronic circuit capable of outputting stored data when an input of a control pulse is started, a drive circuit, and a control system.SOLUTION: An electronic circuit includes: a shift register circuit including a plurality of charge holding circuits; a counter circuit that counts the number of control pulses generated based on a control signal and input to the shift register circuit; and a selector circuit that selects any one of outputs of the plurality of charge holding circuits based on the control signal and a count value of the counter circuit.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present embodiment relates to an electronic circuit, a drive circuit, and a control system. [Background technology]

[0002] In the field of power electronics, semiconductor switching elements such as silicon (Si) or silicon carbide (SiC) MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), IGBTs (Insulated Gate Bipolar Transistors), and GaN are used. In circuits containing these switching elements, power loss can be reduced by speeding up the switching operation of the elements. However, if the switching operation of the elements is made too fast, noise will be generated. In other words, there is a trade-off between reducing power loss and suppressing noise.

[0003] Active gate control technology has been researched as a method for optimizing the above trade-off. In active gate control technology, the waveforms of the drive signals for turning on and off a switching element are determined experimentally or theoretically in advance so as to achieve both reduced power loss and noise suppression, and these waveform data are stored in an electronic circuit. The drive circuit for the switching element generates a drive signal based on the waveform data read from the electronic circuit, and drives the switching element using the drive signal.

[0004] For example, when the switching operation of a switching element is PWM controlled, the drive circuit needs to read waveform data from an electronic circuit in response to a PWM signal (control signal) that instructs the switching operation. [Prior art documents] [Non-patent literature]

[0005] [Non-Patent Document 1] “A Digital Gate Driver IC with Active Gate Waveform Calibration Technique Achieving Switching Loss Reduction by 24% and DESAT Turn-off Arbitrary Waveform Memory for Overcurrent Protection Targeting 1200V SiC MOSFETs”, S. Kawai, T. Ueno, K. Miyazaki, K. Onizuka, H. Ishihara, 2023 IEEE Energy Conversion Congress and Exposition (ECCE) Summary of the Invention [Problem to be solved by the invention]

[0006] An object of the present embodiment is to provide an electronic circuit, a drive circuit, and a control system that can output stored data when input of a control pulse starts. [Means for solving the problem]

[0007] In order to solve the above problem, the electronic circuit of this embodiment includes a shift register circuit including a plurality of charge holding circuits, a counter circuit that counts the number of control pulses generated based on a control signal and input to the shift register circuit, and a selector circuit that selects one of the outputs of the plurality of charge holding circuits based on the control signal and the count value of the counter circuit.

[0008] Another electronic circuit according to the present embodiment includes a shift register circuit including N charge retention circuits, a correction circuit that generates correction pulses and outputs them to the shift register circuit, and a counter circuit that counts the sum of the number of control pulses and the number of correction pulses that are generated based on a control signal and input to the shift register circuit. The counter circuit counts N integer values, and the correction circuit starts outputting correction pulses when the state of the control signal changes and continues outputting the correction pulses until the count value of the counter circuit returns to its initial value.

[0009] The drive circuit according to the present embodiment includes a pulse generation circuit that generates and outputs control pulses based on a control signal, an electronic circuit that receives the control pulses sequentially and outputs waveform data sequentially in synchronization with the control pulses, and a signal generation circuit that generates a drive signal for a switching element based on the waveform data. The electronic circuit includes a shift register circuit including a plurality of charge retention circuits, a counter circuit that counts the number of control pulses input to the shift register circuit, and a first selector circuit that selects one of the outputs of the plurality of charge retention circuits based on the control signal and the count value of the counter circuit.

[0010] a first selector circuit for selecting one of the plurality of electronic circuits to which the control pulses are input and which outputs waveform data in synchronization with the control pulses; a second selector circuit for selecting one of the plurality of electronic circuits based on a selection signal; a third selector circuit for selecting one of the plurality of electronic circuits based on the selection signal; a signal generation circuit for generating a drive signal for a switching element based on the waveform data; a detection circuit for detecting the operating state of the switching element; and a control circuit for generating a control signal and a selection signal based on the operating state of the switching element. The electronic circuit includes a shift register circuit including a plurality of charge retention circuits, a counter circuit for counting the number of control pulses input to the shift register circuit, and a first selector circuit for selecting one of the outputs of the plurality of charge retention circuits based on the control signal and the count value of the counter circuit. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a diagram illustrating a configuration of a motor control system. [Figure 2] FIG. 2 is a diagram showing a detailed configuration of a drive circuit. [Figure 3] FIG. 10 is a diagram illustrating an example of waveform data stored in an electronic circuit. [Figure 4] FIG. 10 is a diagram illustrating an example of waveform data stored in an electronic circuit. [Figure 5] 4 is a timing chart showing how waveform data is output from an electronic circuit. [Figure 6] 1 is a diagram showing a configuration of an electronic circuit according to a first embodiment. [Figure 7] FIG. 2 is a diagram illustrating a detailed configuration of a pulse counter circuit. [Figure 8] FIG. 10 is a diagram illustrating a truth table of a selector circuit. [Figure 9] 4 is a timing chart illustrating the normal operation of the electronic circuit. [Figure 10]FIG. 2 is a diagram illustrating an internal state of a shift register circuit. [Figure 11] FIG. 2 is a diagram illustrating an internal state of a shift register circuit. [Figure 12] 4 is a timing chart illustrating an operation of an electronic circuit when an abnormal pulse occurs. [Figure 13] FIG. 2 is a diagram illustrating an internal state of a shift register circuit. [Figure 14] FIG. 2 is a diagram illustrating an internal state of a shift register circuit. [Figure 15] FIG. 10 is a diagram showing a configuration of an electronic circuit according to a second embodiment. [Figure 16] FIG. 2 is a diagram illustrating a detailed configuration of a correction circuit. [Figure 17] FIG. 10 is a diagram illustrating a truth table of a selector circuit. [Figure 18] 4 is a timing chart illustrating an operation of an electronic circuit when an abnormal pulse occurs. [Figure 19] FIG. 2 is a diagram illustrating an internal state of a shift register circuit. [Figure 20] FIG. 2 is a diagram illustrating an internal state of a shift register circuit. [Figure 21] FIG. 2 is a diagram illustrating an internal state of a shift register circuit. [Figure 22] FIG. 10 is a diagram showing a configuration of an electronic circuit according to a third embodiment. [Figure 23] FIG. 2 is a diagram illustrating a detailed configuration of a correction circuit. [Figure 24] 4 is a timing chart illustrating an operation of an electronic circuit when an abnormal pulse occurs. [Figure 25] FIG. 2 is a diagram illustrating an internal state of a shift register circuit. [Figure 26] FIG. 2 is a diagram illustrating an internal state of a shift register circuit. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, the present embodiment will be described with reference to the drawings. In the drawings, the same or corresponding elements are designated by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0013] (Embodiment 1) 1 is a diagram showing the configuration of a motor control system 1 according to embodiment 1. The motor control system 1 includes a three-phase AC motor 2 as a load, a DC power supply Vdc, switching elements 31A-31F that constitute a three-phase inverter circuit 30, and drive circuits 40A-40F that drive the switching elements 31A-31F, respectively. The motor control system 1 also includes a detection circuit 5 that detects the operating states of the switching elements 31A-31F, and a control circuit 6 that controls the drive circuits 40A-40F.

[0014] The switching elements 31A and 31B are N-channel MOSFETs. The switching elements 31A and 31B form a U-phase arm pair of the inverter circuit 30. The drive circuit 40A controls the gate current serving as a drive signal for the switching element 31A to control the switching operation, i.e., turn-on and turn-off, of the switching element 31A. The drive circuit 40B controls the gate current serving as a drive signal for the switching element 31B to control the switching operation, i.e., turn-on and turn-off, of the switching element 31B.

[0015] Similarly, the switching elements 31C and 31D are N-channel MOSFETs. The switching elements 31C and 31D form a V-phase arm pair of the inverter circuit 30. The drive circuit 40C controls the switching operation of the switching element 31C by controlling a drive signal for the switching element 31C. The drive circuit 40D controls the switching operation of the switching element 31D by controlling a drive signal for the switching element 31D.

[0016] Similarly, the switching elements 31E and 31F are N-channel MOSFETs. The switching elements 31E and 31F form a W-phase arm pair of the inverter circuit 30. The drive circuit 40E controls the drive signal for the switching element 31E to control the switching operation of the switching element 31E. The drive circuit 40F controls the drive signal for the switching element 31F to control the switching operation of the switching element 31F.

[0017] The detection circuit 5 detects the operating states of the switching elements 31A to 31F based on the current values ​​of the U, V, and W phases of the motor 2, and transmits the detected operating states to the control circuit 6. Alternatively, the detection circuit 5 may detect the operating states of the switching elements 31A to 31F based on temperature information acquired by a temperature sensor (not shown) built into the motor 2. Or, the detection circuit 5 may detect the operating states of the switching elements 31A to 31F based on a signal received from a control microcomputer (not shown).

[0018] Based on the operating states of the switching elements 31A to 31F received from the detection circuit 5, the control circuit 6 supplies the drive circuits 40A to 40F with PWM signals as control signals for controlling the switching operations of the switching elements 31A to 31F, selection signals for selecting waveform data of the drive signals of the switching elements 31A to 31F, and clock signals, respectively.

[0019] 2 is a diagram showing the detailed configuration of the drive circuit 40. Since the drive circuits 40A to 40F all have the same configuration, they will hereinafter be collectively described as the drive circuit 40. The drive circuit 40 includes a pulse generation circuit 41, eight electronic circuits 100a to 100h, a selector circuit 42, a selector circuit 43, and a signal generation circuit 44.

[0020] The pulse generation circuit 41 generates and outputs N=32 control pulses synchronized with the clock signal in response to the rising and falling edges of the PWM signal supplied from the control circuit 6. Specifically, when the pulse generation circuit 41 detects a rising edge of the PWM signal, it starts outputting control pulses synchronized with the clock signal. At this time, if the high-level PWM signal is long enough, 32 control pulses are output. However, if the PWM signal is not long enough, for example, if it is shorter than the time required for 32 clock signals, the output of the control pulses may be stopped when fewer than 32 control pulses have been output. Also, when the pulse generation circuit 41 detects a falling edge of the PWM signal, it starts outputting control pulses synchronized with the clock signal. At this time, if the low-level PWM signal is long enough, 32 control pulses are output. However, if the low-level PWM signal is not long enough, for example, if it is shorter than the time required for 32 clock signals, the output of the control pulses may be stopped when fewer than 32 control pulses have been output.

[0021] However, the configuration of the pulse generating circuit 41 is not particularly limited to the above configuration. As an example, the configuration described in Japanese Patent Application Laid-Open No. 2024-022328 can also be adopted. In the present embodiment 1, the value of N is not limited to 32. In the present embodiment 1, the value of N may be an integer equal to or greater than 1, that is, a positive integer.

[0022] The electronic circuits 100a to 100h all have the same configuration and, as will be described in detail later, include 12 shift register circuits with N=32 bits. The electronic circuit 100a stores waveform data obtained by sampling 32 points in the time direction at a sampling period Tc and quantizing the waveform of the drive signal when the switching element 31 is turned on, which has been theoretically or experimentally determined in advance, and then quantizing the waveform data by 12 bits in the amplitude direction (see FIG. 3). That is, the electronic circuit 100a stores 32 points of waveform data quantized by 12 bits.

[0023] The electronic circuits 100b to 100d also store different versions of waveform data of the drive signal when the switching element 31 is turned on. Therefore, the drive circuit 40 holds four types of waveform data as the waveform of the drive signal when the switching element 31 is turned on. However, the number of turn-on waveform data held by the drive circuit 40 is not limited to four. By appropriately adjusting the number of electronic circuits 100 and the number of bits of the selection signal, the drive circuit 40 can hold any number of waveform data.

[0024] Similarly, the electronic circuit 100e stores waveform data obtained by sampling 32 points in the time direction at a sampling period Tc and quantizing the waveform by 12 bits in the amplitude direction for the waveform of the drive signal when the switching element 31 is turned off, which has been theoretically or experimentally determined in advance (see FIG. 4). That is, the electronic circuit 100e stores 32 points of waveform data quantized by 12 bits.

[0025] The electronic circuits 100f to 100h also store different versions of waveform data of the drive signal when the switching element 31 is turned off. Therefore, the drive circuit 40 holds four types of waveform data as the waveform of the drive signal when the switching element 31 is turned off. However, the number of waveform data when the drive circuit 40 holds is not limited to four. By appropriately adjusting the number of electronic circuits 100 and the number of bits of the selection signal, the drive circuit 40 can hold any number of waveform data.

[0026] Based on a selection signal supplied from the control circuit 6, the selector circuit 42 supplies the control pulse output from the pulse generating circuit 41 to one of the electronic circuits 100a to 100h.

[0027] When control pulses are sequentially input to any one of the electronic circuits 100a to 100h, waveform data for 32 points quantized by 12 bits is sequentially output from the electronic circuit 100 to which the control pulses are input in synchronization with each control pulse. That is, each time one control pulse is input, the electronic circuit 100 outputs one point of waveform data quantized by 12 bits, and a total of 32 points of waveform data are sequentially output (see FIG. 5).

[0028] Based on a selection signal supplied from the control circuit 6, the selector circuit 43 sequentially supplies the signal generating circuit 44 with 32 points of waveform data sequentially output from the electronic circuit 100 to which the control pulse has been input.

[0029] The signal generating circuit 44 functions as a D / A converter with a 12-bit input, and generates a drive signal (analog signal) for the switching element 31 based on 32 points of waveform data (digital signal) quantized by 12 bits that are sequentially supplied from the selector circuit 43. The generated drive signal has a waveform that connects the sampling points of FIG. 3 or 4, for example, and is supplied to the switching element 31.

[0030] Fig. 6 is a diagram showing the detailed configuration of the electronic circuit 100. As mentioned above, the electronic circuits 100a to 100h all have the same configuration, and therefore will be collectively described as the electronic circuit 100. Furthermore, the actual electronic circuit 100 includes 12 of each of the components 101, 103, and 104 shown in Fig. 6, which are connected in the same topology, but for simplicity of explanation, Fig. 6 shows only one representative of each component.

[0031] The electronic circuit 100 includes a 32-bit shift register circuit 101, a counter circuit 103, and a selector circuit 104. The shift register circuit 101 is configured by cascading N=32 D flip-flops (D-FFs) 102. A control pulse supplied from a pulse generation circuit 41 is input to a clock terminal of each D-FF 102 serving as a charge holding circuit. The counter circuit 103 counts the number of control pulses input to the shift register circuit 101. The selector circuit 104 selects one of the outputs of the 32 D-FFs 102 based on the PWM signal and the count value of the counter circuit 103, and sets the selected output as its own output OUT.

[0032] The shift register circuit 101 has a cyclic configuration. More specifically, in the shift register circuit 101, the Q output of the 31st D-FF 102 (the D-FF on the right side in the figure) is connected to the D input of the 0th D-FF 102 (the D-FF on the left side in the figure). As a result, every time a control pulse is input to the clock terminal of each D-FF 102, the data held in each D-FF 102 is cyclically shifted to the right in the figure, and when 32 control pulses have been input, the data returns to the initial state.

[0033] The output of each D-FF 102 is connected to the selector circuit 104. In detail, the output of the 0th D-FF 102 is connected to the 0th input port I of the selector circuit 104. <0> The output of the first D-FF 102 is connected to the first input port I of the selector circuit 104. <1> Similarly, the output of the 31st D-FF 102 is connected to the 31st input port I of the selector circuit 104. <31> is connected to.

[0034] 7 is a diagram showing a detailed configuration of the counter circuit 103. The counter circuit 103 is configured by cascading five D-FFs 105, each having a D input and an inverted Q output connected to each other. This allows the counter circuit 103 to count N integer values ​​from 0 to N-1, specifically 32 integer values ​​from 0 to 31.

[0035] 8 is a diagram showing a truth table of the selector circuit 104. All bits (n<4:0>) of the count value of the counter circuit 103 are input to the selector circuit 104. The selector circuit 104 selects one of the outputs of the D-FFs 102 included in the shift register circuit 101 from the count value of the counter circuit 103 at the timing when a rising edge or a falling edge of the PWM signal is detected, according to the truth table of FIG. 8, and sets the selected output as its own output OUT.

[0036] In detail, the selector circuit 104 included in the electronic circuits 100a to 100d, which stores waveform data when the switching element 31 is turned on, selects one of the outputs of the D-FF 102 included in the shift register circuit 101 from the count value of the counter circuit 103 at the timing when the "rising edge" of the PWM signal is detected, according to the truth table of Figure 8, and sets it as its own output OUT.

[0037] On the other hand, the selector circuit 104 included in the electronic circuits 100e to 100h, which store waveform data when the switching element 31 is turned off, selects one of the outputs of the D-FF 102 included in the shift register circuit 101 from the count value of the counter circuit 103 at the timing when the "falling edge" of the PWM signal is detected, according to the truth table of Figure 8, and sets it as its own output OUT.

[0038] The operation of the selector circuit 104 included in the electronic circuits 100a to 100e and the operation of the selector circuit 104 included in the electronic circuits 100f to 100h are all the same except for whether their output OUT is switched at the rising edge or the falling edge of the PWM signal. Therefore, hereinafter, the selector circuit 104 will be described as switching its output OUT at the rising edge of the PWM signal.

[0039] Next, the operation of the electronic circuit 100 according to the first embodiment will be described in two parts: normal operation and operation when an unintended abnormal pulse occurs in the PWM signal. Possible causes of an unintended abnormal pulse occurring in the PWM signal include, for example, a sudden change in the duty ratio of the PWM signal or the influence of noise that occurs when the duty ratio of the PWM signal is high.

[0040] (Normal operation) In the initial state at time t0 in Figure 9, N = 32 pieces of data (D0, D1, ... D31) are stored in a predetermined order in the shift register circuit 101 of the electronic circuit 100. The upper part of Figure 10 shows the internal state of the shift register circuit 101 in the initial state at time t0. The 0th D-FF (FF0) holds the 0th data D0. The 1st D-FF (FF1) holds the 31st data D31. Similarly, the 31st D-FF (FF31) holds the 1st data D1.

[0041] 9, when a rising edge of the PWM signal is detected, the pulse generating circuit 41 starts outputting a control pulse. When the input of the control pulse from the pulse generating circuit 41 starts, the electronic circuit 100 starts outputting data stored in its own shift register circuit 101. In detail, the selector circuit 104 selects one of the outputs of the D-FFs 102 included in the shift register circuit 101 from the count value of the counter circuit 103 at the timing when the rising edge of the PWM signal is detected, in accordance with the truth table of FIG. 8, and sets the selected output as its own output OUT.

[0042] Specifically, at time t1, the count value of the counter circuit 103 is 0 (n <4> =n <3> =n <2> =n <1> =n <0> =0), the selector circuit 104 selects its 0th input port I <0> and sets the output of the 0th D-FF 102 connected to the 0th D-FF 103 as its own output OUT. The lower part of Fig. 10 shows the count value of the counter circuit 103 at time t1 and the internal state of the shift register circuit 101. After this, each time a control pulse is input from the pulse generation circuit 41, the electronic circuit 100 outputs the data stored in the shift register circuit 101 one by one in a predetermined order (D0, D1, ... D31).

[0043] 11 shows the count value of the counter circuit 103 and the internal state of the shift register circuit 101 at the time when five control pulses are input. Since the shift register circuit 101 has a cyclic configuration, the data D0 to D4 that have already been output are stored again in FF5 to FF1.

[0044] At time t2 in Figure 9, the pulse generating circuit 41 completes outputting 32 control pulses. The electronic circuit 100 completes outputting 32 data items. The lower part of Figure 11 shows the count value of the counter circuit 103 and the internal state of the shift register circuit 101 at the time when the output of 32 data items is complete. Because the shift register circuit 101 has a cyclic configuration, the internal state when the output of 32 data items is complete (lower part of Figure 11) is the same as the internal state in the initial state (upper part of Figure 10). In addition, the count value of the counter circuit 103 has returned to 0 after counting 32 control pulses.

[0045] (Operation when an unintended abnormal pulse occurs in the PWM signal) 12, in the initial state at time t0, 32 pieces of data (D0, D1, ... D31) are stored in a predetermined order in the shift register circuit 101 of the electronic circuit 100. The upper part of Fig. 13 shows the count value of the counter circuit 103 and the internal state of the shift register circuit 101 in the initial state at time t0.

[0046] 12, when a rising edge (false rising edge) of the PWM signal caused by an unintended abnormal pulse is detected, the pulse generating circuit 41 starts outputting a control pulse. When the input of the control pulse from the pulse generating circuit 41 starts, the electronic circuit 100 starts outputting the data stored in its own shift register circuit 101.

[0047] In detail, at time t1, the count value of the counter circuit 103 is 0, so the selector circuit 104 selects its 0th input port I <0> 13, the electronic circuit 100 selects the output of the 0th D-FF 102 connected to the shift register circuit 101 and sets this as its own output OUT. The lower part of Fig. 13 shows the count value of the counter circuit 103 at time t1 and the internal state of the shift register circuit 101. After this, each time a control pulse is input from the pulse generation circuit 41, the electronic circuit 100 outputs the data stored in the shift register circuit 101 one by one in a predetermined order (D0, D1, ...).

[0048] When the falling edge of the PWM signal is detected at time t2 in Figure 12, the pulse generating circuit 41 starts outputting a control pulse again from that timing. However, the control pulse output at this time is not input to the currently explained electronic circuit 100, but to another electronic circuit that stores waveform data for turn-off. In Figure 12, the control pulse output at the falling edge of the PWM signal is omitted.

[0049] 12, when a rising edge (true rising edge) of the PWM signal is detected again, the pulse generating circuit 41 starts outputting control pulses again from that timing. When the input of control pulses from the pulse generating circuit 41 starts again, the electronic circuit 100 starts outputting data stored in its shift register circuit 101 again.

[0050] At this time, the electronic circuit 100 does not start outputting from the continuation of the data that has already been output, but outputs the 32 pieces of data again from the beginning in a predetermined order (D0, D1, . . . D31). For example, at time t3, the count value of the counter circuit 103 is 2(n <4> =0, n <3> =0, n <2> =0, n <1> = 1, n <0> =0), the selector circuit 104 selects its second input port I <2> Select the output of the second D-FF102 connected to the , and set it as its own output OUT.

[0051] 14 shows the count value of the counter circuit 103 and the internal state of the shift register circuit 101 at time t3. As described above, the selector circuit 104 selects the output of the second D-FF (FF2), and therefore the output of FF2 becomes the output of the electronic circuit 100. Thereafter, the output of FF2 changes in the order of D0, D1, ..., D31 each time a control pulse is input. Therefore, each time a control pulse is input from the pulse generation circuit 41, the electronic circuit 100 outputs the 32 pieces of data stored in the shift register circuit 101 one by one in a predetermined order (D0, D1, ..., D31).

[0052] At time t4 in Fig. 12, the pulse generating circuit 41 completes outputting 32 control pulses. The electronic circuit 100 completes outputting 32 data items. The lower part of Fig. 14 shows the count value of the counter circuit 103 and the internal state of the shift register circuit 101 at the time when output of 32 data items has been completed.

[0053] In this state, the count value of the counter circuit 103 is 2, which corresponds to FF2 in which the leading data D0 is held. Therefore, the counter circuit 103 can handle the input of the next and subsequent control pulses in this state without resetting the counter circuit 103. In other words, there is no need to provide a reset mechanism in the counter circuit 103.

[0054] As described above, the electronic circuit 100 according to the first embodiment includes a shift register circuit 101 including a plurality of D-FFs 102, a counter circuit 103 that counts the number of control pulses generated based on a PWM signal and input to the shift register circuit 101, and a selector circuit 104 that selects one of the outputs of the plurality of D-FFs 102 based on the PWM signal and the count value of the counter circuit 103.

[0055] Due to the above-mentioned features, the electronic circuit 100 according to the first embodiment can always output the stored data in a predetermined order (D0, D1, ... D31) when the input of the control pulse generated based on the PWM signal starts, even if an unintended abnormal pulse occurs in the PWM signal.

[0056] Furthermore, in the electronic circuit 100 according to the first embodiment, all of the outputs of the N=32 D-FFs 102 are connected to the selector circuit 104. As a result, no matter when the input of the control pulse is interrupted, the next and subsequent inputs of the control pulse can be handled according to the internal state of the shift register circuit 101 at that time.

[0057] Moreover, the drive circuit 40 according to the first embodiment includes a pulse generation circuit 41 that generates and outputs a control pulse based on a PWM signal, an electronic circuit 100 that receives the control pulses sequentially and outputs waveform data sequentially in synchronization with the control pulses, and a signal generation circuit 44 that generates a drive signal for the switching element 31 based on the waveform data.

[0058] Due to the above-mentioned features, the waveform of the drive signal for the switching element 31 can be determined experimentally or theoretically in advance so as to achieve both reduced power loss and suppressed noise, and such waveform data can be stored in the electronic circuit 100. The drive circuit 40 can generate a drive signal based on the waveform data stored in the electronic circuit 100 and drive the switching element 31 using the drive signal. In this case, even if an unintended abnormal pulse occurs in the PWM signal and is followed by a true rising pulse, the electronic circuit 100 always outputs waveform data in a predetermined order (D0, D1, ... D31).

[0059] The drive circuit 40 according to the first embodiment includes a plurality of electronic circuits 100a-100h, a selector circuit 42 that inputs a control pulse output from a pulse generation circuit 41 to any one of the plurality of electronic circuits 100a-100h based on a selection signal, and a selector circuit 43 that inputs waveform data output from any one of the plurality of electronic circuits 100a-100h to a signal generation circuit 44 based on the selection signal. With these features, any one of the plurality of waveform data can be selected, and a drive signal for the switching element 31 can be generated based on the waveform data.

[0060] Furthermore, the motor control system 1 according to the first embodiment includes the above-described drive circuit 40, a detection circuit 6 that detects the operating state of the switching element 31, and a control circuit 7 that generates a PWM signal and a selection signal based on the operating state. Due to these features, the motor control system 1 according to the first embodiment can generate an optimal drive signal that achieves both reduced power loss and suppressed noise based on the operating state of the switching element 31, and drive the switching element 31 with the drive signal.

[0061] (Embodiment 2) 15 is a diagram showing the configuration of an electronic circuit 200 according to embodiment 2. The electronic circuit 200 includes a 32-bit shift register circuit 201, a counter circuit 203, a selector circuit 204, and a correction circuit 206. The correction circuit 206 generates and outputs a correction pulse based on the PWM signal inverted by a NOT gate 207 and the count value of the counter circuit 203.

[0062] The shift register circuit 201 is configured by cascading N=32 D-FFs 102. The shift register circuit 201 receives, via an OR gate 208, both a control pulse output from the pulse generating circuit 41 and a correction pulse output from the correction circuit 206.

[0063] In the above-described first embodiment, the outputs of all the D-FFs 102 included in the shift register circuit 101 are connected to the selector circuit 104. In contrast, in the second embodiment, of the N=32 D-FFs 102 included in the shift register circuit 201, M=4 are grouped together, and only one output of each of the four is connected to the selector circuit 204.

[0064] Specifically, when the 0th to 3rd D-FFs 102 are taken as a group, only the output of the third D-FF 102 in the group is connected to the 0th input port I of the selector circuit 204. <0> Next, the fourth to seventh D-FFs 102 are grouped together, and only the output of the seventh D-FF 102 is connected to the first input port I of the selector circuit 204. <1> Similarly, the 28th to 31st D-FFs 102 are grouped together, and only the output of the 31st D-FF 102 is connected to the 7th input port I of the selector circuit 204. <7> is connected to.

[0065] In the second embodiment, the values ​​of N and M are not limited to 32 and 4. In the second embodiment, M may be any positive integer, and N may be any multiple of M.

[0066] The detailed configuration of the counter circuit 203 is the same as that of the counter circuit 103 of the first embodiment (see FIG. 7). The counter circuit 203 receives, via an OR gate 209, both the control pulses output from the pulse generation circuit 41 and the correction pulses output from the correction circuit 206. As a result, the counter circuit 203 counts the number of correction pulses input to the shift register circuit 201 in addition to the number of control pulses input to the shift register circuit 201. In other words, the counter circuit 203 counts the sum of the number of control pulses and the number of correction pulses input to the shift register circuit 201.

[0067] 16 is a diagram showing a detailed configuration of the correction circuit 206. The correction circuit 206 receives the two least significant bits (n<1:0>) of the count value of the pulse counter circuit 203, the PWM signal, and the same clock signal (see FIG. 2) as that input to the pulse generation circuit 41. The correction circuit 206 is composed of NOT gates 210 and 211, an AND gate 212, a NOT gate 213, an AND gate 214, and an AND gate 215. With this configuration, the correction circuit 206 starts outputting correction pulses when it detects a "falling edge" of the PWM signal, and continues outputting correction pulses until the count value of the counter circuit 203 becomes a multiple of M=4.

[0068] 17 is a diagram showing a truth table of the selector circuit 204. The selector circuit 204 receives the upper three bits (n<4:2>) of the count value of the counter circuit 203. The selector circuit 204 selects one of the outputs of the D-FFs 102 included in the shift register circuit 201 and corresponding to multiples of M=4, in accordance with the truth table of FIG. 17, from the upper three bits (n<4:2>) of the count value of the counter circuit 203 at the timing when the rising edge of the PWM signal is detected, and sets the selected output as its own output OUT.

[0069] Next, a description will be given of the operation of the electronic circuit 200 according to the second embodiment when an unintended abnormal pulse occurs in the PWM signal. Note that the normal operation is the same as that of the first embodiment described above, and therefore the description will be omitted.

[0070] (Operation when an unintended abnormal pulse occurs in the PWM signal) 18, in the initial state at time t0, 32 pieces of data (D0, D1, ... D31) are stored in a predetermined order in the shift register circuit 201 of the electronic circuit 200. The upper part of Fig. 19 shows the count value of the pulse count circuit 203 and the internal state of the shift register circuit 201 in the initial state at time t0.

[0071] 18, when a rising edge (false rising edge) of the PWM signal caused by an unintended abnormal pulse is detected, the pulse generating circuit 41 starts outputting a control pulse. When the input of the control pulse from the pulse generating circuit 41 starts, the electronic circuit 200 starts outputting the data stored in the shift register circuit 201.

[0072] In detail, at time t1, the count value of the counter circuit 203 is 0, and the upper three bits are n <4> =n <3> =n <2> =0. Therefore, the selector circuit 204 selects its 0th input port I <0> 19 selects the output of the third D-FF connected to the shift register circuit 201 and sets it as its own output OUT. The lower part of Fig. 19 shows the count value of the counter circuit 203 at time t1 and the internal state of the shift register circuit 201. After this, each time a control pulse is input from the pulse generation circuit 41, the electronic circuit 200 outputs the data stored in the shift register circuit 201 one by one in a predetermined order (D0, D1, ...).

[0073] When the falling edge of the PWM signal is detected at time t2 in Figure 18, the pulse generating circuit 41 starts outputting a control pulse again from that timing. However, the control pulse output at this time is not input to the currently explained electronic circuit 200, but to another electronic circuit that stores waveform data for turn-off. In Figure 18, the control pulse output at the falling edge of the PWM signal is omitted.

[0074] 18, when a falling edge of the PWM signal is detected, the correction circuit 206 starts outputting correction pulses and continues outputting the correction pulses until the count value of the counter circuit 203 becomes a multiple of M=4. For example, at time t2, if the count value of the counter circuit 203 becomes 2 (i.e., the lower two bits are n), <1> = 1, n <0> =0), the correction circuit 206 calculates the count value of the counter circuit 203 as 4, which is a multiple of M=4 (i.e., the lower two bits are n <1> =n <0> = 0).

[0075] Therefore, 4-2=2 correction pulses are output from the correction circuit 206. The upper part of Fig. 20 shows the count value of the counter circuit 203 before the correction pulses are output and the internal state of the shift register circuit 201. The lower part of Fig. 20 shows the count value of the counter circuit 203 after the correction pulses are output and the internal state of the shift register circuit 201.

[0076] 18, when a rising edge (true rising edge) of the PWM signal is detected again, the pulse generating circuit 41 starts outputting control pulses again from that timing. When the input of control pulses from the pulse generating circuit 41 starts again, the electronic circuit 200 starts outputting the data stored in the shift register circuit 201 again.

[0077] At this time, the electronic circuit 200 does not start outputting from the continuation of the data that has already been output, but outputs the 32 pieces of data again from the beginning in a predetermined order (D0, D1, . . . D31). In detail, at time t3, the count value of the counter circuit 203 is 4, and the upper three bits of the count value are n <4> =0, n <3> =0, n <2> =1. Therefore, the selector circuit 204 selects its first input port I <1> The output of the seventh D-FF connected to is selected and set as its own output OUT.

[0078] 21 shows the count value of the counter circuit 203 and the internal state of the shift register circuit 201 at time t3. As described above, the selector circuit 204 selects the output of the seventh D-FF (FF7), and therefore the output of FF7 becomes the output of the electronic circuit 200. Thereafter, the output of FF7 changes in the order D0, D1, ..., D31 each time a control pulse is input. Therefore, each time a control pulse is input from the pulse generation circuit 41, the electronic circuit 200 outputs the 32 pieces of data stored in the shift register circuit 201 one by one in a predetermined order (D0, D1, ..., D31).

[0079] At time t4 in Fig. 18, the pulse generating circuit 41 completes outputting 32 control pulses. The electronic circuit 200 completes outputting 32 data items. The lower part of Fig. 21 shows the count value of the counter circuit 203 and the internal state of the shift register circuit 201 at the time when output of 32 data items has been completed.

[0080] In this state, the count value of the counter circuit 203 is 4, which corresponds to FF7 where the leading data D0 is held. Therefore, the counter circuit 203 can handle the input of the next and subsequent control pulses in this state without resetting the counter circuit 203. In other words, there is no need to provide a reset mechanism in the counter circuit 203.

[0081] As described above, the electronic circuit 200 according to the second embodiment includes the correction circuit 206 that generates a correction pulse and outputs it to the shift register circuit 201. When a falling pulse of the PWM signal is detected, the correction circuit 206 starts outputting a correction pulse, and continues outputting the correction pulse until the count value of the counter circuit 203 becomes a multiple of M=4.

[0082] In general, the number p of correction pulses output from the correction circuit 206 can be expressed as follows, where q is the number of control pulses output due to abnormal pulses:

[0083] (i) When Mod(q / M)=0 p=0 (ii) When Mod(q / M)≠0 p=M-(Mod(q / M))

[0084] In the above equation, Mod(q / M) means the remainder when q is divided by M.

[0085] Alternatively, the number p of correction pulses output from the correction circuit 206 can be expressed as follows, where n is the count value of the counter circuit 203 at the timing when the falling edge of the PWM signal is detected:

[0086] (i) When Mod(n / M)=0 p=0 (ii) When Mod(n / M)≠0 p=M-(Mod(n / M))

[0087] In the above equation, Mod(n / M) means the remainder when n is divided by M.

[0088] Due to the above-mentioned features, in the second embodiment, the number of wires extending from the shift register circuit 201 to the outside, specifically the number of wires between the shift register circuit 201 and the selector circuit 204, can be significantly reduced compared to the first embodiment described above. More specifically, the number of wires between the two can be reduced to 1 / M compared to the first embodiment. This allows for significant reductions in the cost required for design and the mounting area of ​​the circuit.

[0089] Furthermore, in the second embodiment, by setting the frequency of the correction pulses higher than the frequency of the control pulses, it is possible to insert more correction pulses in the period between t2 and t3 in Fig. 18. This makes it possible to accommodate not only the case where M=4, but also the cases where M=8, 16, 32, etc. As a method for setting the frequency of the correction pulses higher than the frequency of the control pulses, for example, instead of the clock signal input to the correction circuit 206 in Fig. 16, a clock signal with a higher frequency than the clock signal may be input.

[0090] In general, the frequency fc of the correction pulse must satisfy the following relationship, where Tmin is the minimum pulse width of the PWM signal:

[0091] fc>M / Tmin

[0092] The minimum pulse width Tmin of the PWM signal is determined based on the maximum and minimum values ​​of the duty ratio of the PWM signal, the minimum pulse width of the isolator (not shown) inserted in the stage preceding the PWM input of the drive circuit 40 in FIG. 2, the input capacitance of the switching element 31, the load current, the power supply voltage, etc.

[0093] (Embodiment 3) 22 is a diagram showing the configuration of an electronic circuit 300 according to the third embodiment. The electronic circuit 300 includes a 32-bit shift register circuit 301, a counter circuit 303, a buffer circuit 304, and a correction circuit 306. When a rising edge of the PWM signal is detected, the buffer circuit 304 outputs a signal to its input port I <0> The output of the 31st D-FF 102 connected to the 31st D-FF 102 is set as its own output OUT.

[0094] In the second embodiment described above, of the N=32 D-FFs 102 included in the shift register circuit 201, M=4 D-FFs are grouped into sets, and only one output of each set is connected to the selector circuit 204. In contrast, in the third embodiment, only one specific output of the N=32 D-FFs 102 included in the shift register circuit 301, specifically, only the output of the 31st D-FF 102, is connected to the input port I of the buffer circuit 304. <0> is connected to.

[0095] The detailed configuration of the counter circuit 303 is the same as that of the counter circuits 103 and 203 in the first and second embodiments (see FIG. 7). The counter circuit 303 counts the sum of the number of control pulses and the number of correction pulses input to the shift register circuit 301.

[0096] 23 is a diagram showing a detailed configuration of the correction circuit 306. All bits (n<4:0>) of the count value of the pulse counter circuit 303, the PWM signal, and a clock signal with a higher frequency than the clock signal input to the pulse generation circuit 41 are input to the correction circuit 306. The correction circuit 306 is composed of NOT gates 316a to 316e, an AND gate 312, a NOT gate 213, an AND gate 214, and an AND gate 215. With this configuration, the correction circuit 306 starts outputting correction pulses when it detects a "falling edge" of the PWM signal, and continues outputting correction pulses until the count value of the counter circuit 303 returns to the initial value of 0.

[0097] Next, a description will be given of the operation of the electronic circuit 300 according to the third embodiment when an unintended abnormal pulse occurs in the PWM signal. Note that the normal operation is the same as in the first and second embodiments described above, and therefore the description will be omitted.

[0098] (Operation when an unintended abnormal pulse occurs in the PWM signal) In the initial state at time t0 in Fig. 24, 32 pieces of data (D0, D1, ... D31) are stored in a predetermined order in the shift register circuit 301 of the electronic circuit 300. The upper part of Fig. 25 shows the count value of the pulse count circuit 303 and the internal state of the shift register circuit 301 in the initial state at time t0.

[0099] 24, when a rising edge (false rising edge) of the PWM signal caused by an unintended abnormal pulse is detected, the pulse generating circuit 41 starts outputting a control pulse. When the input of the control pulse from the pulse generating circuit 41 starts, the electronic circuit 300 starts outputting the data stored in the shift register circuit 301.

[0100] In particular, the output OUT of the buffer circuit 304 is always connected to its input port I <0> Therefore, every time a control pulse is input from the pulse generating circuit 41, the electronic circuit 300 outputs the data stored in the shift register circuit 301 one by one in a predetermined order (D0, D1, ...).

[0101] When the falling edge of the PWM signal is detected at time t2 in Fig. 24, the pulse generating circuit 41 starts outputting a control pulse again from that timing. However, the control pulse output at this time is not input to the currently explained electronic circuit 300, but to another electronic circuit that stores waveform data for turn-off. In Fig. 24, the control pulse output at the falling edge of the PWM signal is omitted.

[0102] 24, when a falling edge of the PWM signal is detected, the correction circuit 306 starts outputting correction pulses and continues outputting the correction pulses until the count value of the counter circuit 303 returns to the initial value 0. For example, at time t2, if the count value of the counter circuit 303 is 2(n <4> =0, n <3> =0, n <2> =0, n <1> = 1, n <0> =0), the correction circuit 306 resets the count value of the counter circuit 303 to the initial value 0 (n <4> =n <3> =n <2> =n <1> =n <0> = 0).

[0103] Therefore, 32-2=30 correction pulses are output from the correction circuit 306. The lower part of Fig. 25 shows the count value of the counter circuit 303 before the correction pulses are output and the internal state of the shift register circuit 301. The upper part of Fig. 26 shows the count value of the counter circuit 303 after the correction pulses are output and the internal state of the shift register circuit 301.

[0104] 24, when a rising edge (true rising edge) of the PWM signal is detected again, the pulse generating circuit 41 starts outputting control pulses again from that timing. When the input of control pulses from the pulse generating circuit 41 starts again, the electronic circuit 300 starts outputting the data stored in the shift register circuit 301 again.

[0105] At this time, the internal state of the shift register circuit 303 has returned to the same initial state as that shown in the upper part of Fig. 25. The count value of the counter circuit 303 has also returned to the initial value of 0. Therefore, every time a control pulse is input from the pulse generating circuit 41, the electronic circuit 300 outputs the 32 pieces of data stored in the shift register circuit 301 one by one in a predetermined order (D0, D1, ... D31).

[0106] At time t4 in Fig. 24, the pulse generating circuit 41 completes outputting 32 control pulses. The electronic circuit 300 completes outputting 32 data items. The lower part of Fig. 26 shows the count value of the counter circuit 303 and the internal state of the shift register circuit 301 at the time when output of 32 data items has been completed.

[0107] In this state, the count value of the counter circuit 303 returns to the initial value of 0. Therefore, the counter circuit 303 can handle the input of the next and subsequent control pulses in this state without resetting the counter circuit 303. In other words, there is no need to provide a reset mechanism for the counter circuit 303.

[0108] As described above, the electronic circuit 300 according to the third embodiment includes a shift register circuit 301 including N=32 D-FFs 102, a correction circuit 306 that generates correction pulses and outputs them to the shift register circuit 301, and a counter circuit 303 that counts the sum of the number of control pulses and the number of correction pulses that are generated based on a PWM signal and input to the shift register circuit 301.

[0109] The counter circuit 303 counts integer values, N=32. When a falling edge of the PWM signal is detected, the correction circuit 306 starts outputting a correction pulse, and continues outputting the correction pulse until the count value of the counter circuit 303 returns to the initial value 0.

[0110] Due to the above-described features, in the third embodiment, compared to the first and second embodiments described above, it is possible to further reduce the number of wires extending from the shift register circuit 301 to the outside, specifically, the number of wires between the shift register circuit 301 and the buffer circuit 304. This makes it possible to further reduce the cost required for design and the mounting area of ​​the circuit.

[0111] In the third embodiment, the number p of correction pulses output from the correction circuit 306 can be expressed as follows, where q is the number of control pulses output due to abnormal pulses:

[0112] (i) When Mod(q / N)=0 p=0 (ii) When Mod(q / N)≠0 p=N-(Mod(q / N))

[0113] In the above equation, Mod(q / N) means the remainder when q is divided by N.

[0114] Alternatively, the number p of correction pulses output from the correction circuit 306 can be expressed as follows, where n is the count value of the counter circuit 303 at the timing when the falling edge of the PWM signal is detected:

[0115] (i) When Mod(n / N)=0 p=0 (ii) When Mod(n / N)≠0 p=N-(Mod(n / N))

[0116] In the above equation, Mod(n / N) means the remainder when n is divided by N.

[0117] Furthermore, in the third embodiment, the frequency fc of the correction pulse needs to satisfy the following relationship, where Tmin is the minimum pulse width of the PWM signal.

[0118] fc>N / Tmin

[0119] The minimum pulse width Tmin of the PWM signal is determined based on the maximum and minimum values ​​of the duty ratio of the PWM signal, the minimum pulse width of the isolator (not shown) inserted in the stage preceding the PWM input of the drive circuit 40 in FIG. 2, the input capacitance of the switching element 31, the load current, the power supply voltage, etc.

[0120] (Variation) In the above first to third embodiments, the three-phase inverter circuit 30 is configured using the switching elements 31. Instead of this, for example, a converter circuit may be configured using switching elements and diodes.

[0121] Furthermore, the switching element 31 is not limited to a MOSFET. For example, the switching element 31 may be an IGBT. Alternatively, the switching element 31 may be a BJT (Bipolar Junction Transistor).

[0122] As the semiconductor forming the switching element 31, various materials such as Si (Silicon), SiC (Silicon Carbide), or GaN (Gallium Nitride) can be used.

[0123] Although several embodiments have been described, these embodiments are presented as examples and are not intended to limit the scope of the embodiments. These embodiments can be implemented in various other forms, and various omissions, substitutions, modifications, combinations, etc. can be made without departing from the spirit of the embodiments. These embodiments and their modifications are included in the scope of the claims and their equivalents, as well as the scope and spirit of the embodiments.

[0124] This embodiment can also be configured as follows. [1] (Examples 1 and 2) a shift register circuit including a plurality of charge holding circuits; a counter circuit that counts the number of control pulses that are generated based on a control signal and input to the shift register circuit; a selector circuit that selects one of the outputs of the charge holding circuits based on the control signal and the count value of the counter circuit; An electronic circuit comprising: [2] (Examples 1 and 2) the shift register circuit includes N charge holding circuits; the counter circuit counts N integer values; when the state of the control signal changes, the selector circuit selects the output of the charge holding circuit that corresponds to the count value of the counter circuit at the timing of the change. Item 1. The electronic circuit according to item 1. [3] (Example 1) the shift register circuit includes the 0th to N-1th charge holding circuits, the counter circuit counts integer values ​​from 0 to N-1; when the state of the control signal changes, the selector circuit selects the output of the n-th charge holding circuit, with the count value of the counter circuit at the timing of the change being n. Item 1 or 2. An electronic circuit according to item 1 or 2. [4] (Example 1) all of the outputs of the plurality of charge retention circuits are connected to the selector circuit; 4. The electronic circuit according to any one of items 1 to 3. [5] (Example 2) the electronic circuit further includes a correction circuit that generates a correction pulse and outputs it to the shift register circuit; the counter circuit counts the sum of the number of the control pulses and the number of the correction pulses input to the shift register circuit; the shift register circuit includes N charge holding circuits, N being a multiple of a positive integer M; the correction circuit starts outputting the correction pulse when the state of the control signal changes, and continues outputting the correction pulse until the count value of the counter circuit becomes a multiple of the positive integer M. Item 1 or 2. An electronic circuit according to item 1 or 2. [6] (Example 2) Among the N charge retention circuits, M circuits are grouped together, and only one output of each of the M circuits is connected to the selector circuit. Item 5. The electronic circuit according to item 5. [7] (Example 2) the correction circuit operates based on lower bits of the count value of the counter circuit. Item 7. The electronic circuit according to item 5 or 6. [8] (Example 2) the selector circuit operates based on the most significant bits of the count value of the counter circuit; 8. The electronic circuit according to any one of items 5 to 7. [9] (Example 2) the counter circuit counts integer values ​​from 0 to N-1; The number p of the correction pulses output from the correction circuit is expressed as follows: (i) If Mod(q / M)=0, p=0 (ii) If Mod(q / M)≠0, then p=M-(Mod(q / M)) represented by Item 9. The electronic circuit according to any one of items 5 to 8.

[10] (Example 2) the counter circuit counts integer values ​​from 0 to N-1; The number p of the correction pulses output from the correction circuit is expressed as follows, where n is the count value of the counter circuit: (i) If Mod(n / M)=0, p=0 (ii) If Mod(n / M)≠0, p=M-(Mod(n / M)) represented by 10. The electronic circuit according to any one of items 5 to 9.

[11] (Example 2) The frequency of the correction pulse is higher than the frequency of the control pulse. 11. The electronic circuit according to any one of items 5 to 10.

[12] (Example 2) The frequency fc of the correction pulse is expressed as follows, where Tmin is the minimum pulse width of the control signal: fc>M / Tmin Satisfy the relationship of 12. The electronic circuit according to any one of items 5 to 11.

[13] (Example 3) a shift register circuit including N charge retention circuits; a correction circuit that generates a correction pulse and outputs it to the shift register circuit; a counter circuit that counts the sum of the number of control pulses generated based on a control signal and input to the shift register circuit and the number of correction pulses; Equipped with the counter circuit counts N integer values; the correction circuit starts outputting the correction pulse when the state of the control signal changes, and continues outputting the correction pulse until the count value of the counter circuit returns to an initial value. electronic circuit.

[14] (Example 3) The electronic circuit further includes a buffer circuit connected to an output of a specific one of the N charge retention circuits; When the state of the control signal changes, the buffer circuit selects the output of the specific one charge holding circuit as its own output. Item 14. The electronic circuit according to item 13.

[15] (Example 3) The frequency of the correction pulse is higher than the frequency of the control pulse. Item 15. The electronic circuit according to item 13 or 14.

[16] (Example 3) The frequency fc of the correction pulse is expressed as follows, where Tmin is the minimum pulse width of the control signal: fc>N / Tmin Satisfy the relationship of 16. The electronic circuit according to any one of items 13 to 15.

[17] (Drive circuit) a pulse generating circuit that generates and outputs a control pulse based on a control signal; an electronic circuit that receives the control pulses in sequence and outputs waveform data in sequence in synchronization with the control pulses; a signal generating circuit that generates a drive signal for a switching element based on the waveform data; Equipped with The electronic circuit a shift register circuit including a plurality of charge holding circuits; a counter circuit that counts the number of the control pulses input to the shift register circuit; a first selector circuit that selects one of the outputs of the charge holding circuits based on the control signal and the count value of the counter circuit; a drive circuit including:

[18] (Drive circuit) a plurality of said electronic circuits; a second selector circuit that inputs the control pulse output from the pulse generating circuit to any one of the plurality of electronic circuits based on a selection signal; a third selector circuit that inputs the waveform data output from any one of the plurality of electronic circuits to the signal generating circuit based on the selection signal; Further provided with Item 18. The drive circuit according to item 17.

[19] (Control System) a pulse generating circuit that generates and outputs a control pulse based on a control signal; a plurality of electronic circuits to which the control pulses are sequentially input and which sequentially output waveform data in synchronization with the control pulses; a second selector circuit that inputs the control pulse output from the pulse generating circuit to any one of the plurality of electronic circuits based on a selection signal; a third selector circuit that inputs the waveform data output from any one of the plurality of electronic circuits to the signal generating circuit based on the selection signal; a signal generating circuit that generates a drive signal for a switching element based on the waveform data; a detection circuit for detecting an operating state of the switching element; a control circuit that generates the control signal and the selection signal based on the operating state; Equipped with The electronic circuit a shift register circuit including a plurality of charge holding circuits; a counter circuit that counts the number of the control pulses input to the shift register circuit; a first selector circuit that selects one of the outputs of the charge holding circuits based on the control signal and the count value of the counter circuit; a control system. [Explanation of symbols]

[0125] 1. Motor Control System 2 motors 5 Detection circuit 6 Control Circuit 30 Inverter circuit 31 Switching element 40 Drive circuit 41 Pulse generation circuit 42 Selector circuit 43 Selector circuit 44 Signal generation circuit 100 electronic circuits 101 Shift register circuit 102 D-FF 103 Counter Circuit 104 Selector Circuit 105 D-FF 200 Electronic circuits 201 Shift register circuit 203 Counter Circuit 204 Selector Circuit 206 Correction circuit 207 NOT Gate 208 OR Gate 209 OR Gate 210 NOT Gate 211 NOT Gate 212 AND Gate 213 NOT Gate 214 AND Gate 215 AND Gate 300 Electronic circuits 301 Shift register circuit 303 Counter Circuit 304 Buffer Circuit 306 Correction Circuit 312 AND Gate 316 NOT Gate

Claims

1. a shift register circuit including a plurality of charge holding circuits; a counter circuit that counts the number of control pulses that are generated based on a control signal and input to the shift register circuit; a selector circuit that selects one of the outputs of the charge holding circuits based on the control signal and the count value of the counter circuit; An electronic circuit comprising:

2. the shift register circuit includes N charge holding circuits; the counter circuit counts N integer values; when the state of the control signal changes, the selector circuit selects the output of the charge holding circuit that corresponds to the count value of the counter circuit at the timing of the change.

10. The electronic circuit of claim 1.

3. the shift register circuit includes the 0th to N-1th charge holding circuits, the counter circuit counts integer values ​​from 0 to N-1; when the state of the control signal changes, the selector circuit selects the output of the n-th charge holding circuit, with the count value of the counter circuit at the timing of the change being n.

10. The electronic circuit of claim 1.

4. all of the outputs of the plurality of charge retention circuits are connected to the selector circuit; 10. The electronic circuit of claim 1.

5. the electronic circuit further includes a correction circuit that generates a correction pulse and outputs it to the shift register circuit; the counter circuit counts the sum of the number of the control pulses and the number of the correction pulses input to the shift register circuit; the shift register circuit includes N charge holding circuits, the N being a multiple of a positive integer M; the correction circuit starts outputting the correction pulse when the state of the control signal changes, and continues outputting the correction pulse until the count value of the counter circuit becomes a multiple of the positive integer M.

10. The electronic circuit of claim 1.

6. Among the N charge holding circuits, M circuits are grouped together, and only one output of each of the M circuits is connected to the selector circuit.

6. The electronic circuit of claim 5.

7. the correction circuit operates based on lower bits of the count value of the counter circuit.

6. The electronic circuit of claim 5.

8. the selector circuit operates based on the most significant bits of the count value of the counter circuit; 6. The electronic circuit of claim 5.

9. the counter circuit counts integer values ​​from 0 to N-1; The number p of the correction pulses output from the correction circuit is expressed as follows, where q is the number of the control pulses output due to abnormal pulses occurring in the control signal: (i) If Mod(q / M) = 0, p=0 (ii) If Mod(q / M)≠0, p=M-(Mod(q / M)) represented by 6. The electronic circuit of claim 5.

10. the counter circuit counts integer values ​​from 0 to N-1; The number p of the correction pulses output from the correction circuit is expressed as follows, where n is the count value of the counter circuit: (i) If Mod(n / M) = 0, p=0 (ii) If Mod(n / M)≠0, p=M-(Mod(n / M)) represented by 6. The electronic circuit of claim 5.

11. The frequency of the correction pulse is higher than the frequency of the control pulse.

6. The electronic circuit of claim 5.

12. The frequency fc of the correction pulse is expressed as follows, where Tmin is the minimum pulse width of the control signal: fc>M / Tmin Satisfy the relationship of 6. The electronic circuit of claim 5.

13. a shift register circuit including N charge holding circuits; a correction circuit that generates a correction pulse and outputs it to the shift register circuit; a counter circuit that counts the sum of the number of control pulses generated based on a control signal and input to the shift register circuit and the number of correction pulses; Equipped with the counter circuit counts N integer values; the correction circuit starts outputting the correction pulse when the state of the control signal changes, and continues outputting the correction pulse until the count value of the counter circuit returns to an initial value. electronic circuit.

14. The electronic circuit further includes a buffer circuit connected to the output of a specific one of the N charge retention circuits; When the state of the control signal changes, the buffer circuit selects the output of the specific charge holding circuit as its own output.

14. The electronic circuit of claim 13.

15. The frequency of the correction pulse is higher than the frequency of the control pulse.

14. The electronic circuit of claim 13.

16. The frequency fc of the correction pulse is expressed as follows, where Tmin is the minimum pulse width of the control signal: fc>N / Tmin Satisfy the relationship of 14. The electronic circuit of claim 13.

17. a pulse generating circuit that generates and outputs a control pulse based on a control signal; an electronic circuit that receives the control pulses in sequence and outputs waveform data in sequence in synchronization with the control pulses; a signal generating circuit that generates a drive signal for a switching element based on the waveform data; Equipped with The electronic circuit a shift register circuit including a plurality of charge holding circuits; a counter circuit that counts the number of the control pulses input to the shift register circuit; a first selector circuit that selects one of the outputs of the charge holding circuits based on the control signal and the count value of the counter circuit; a drive circuit including:

18. a plurality of said electronic circuits; a second selector circuit that inputs the control pulse output from the pulse generating circuit to any one of the plurality of electronic circuits based on a selection signal; a third selector circuit that inputs the waveform data output from any one of the plurality of electronic circuits to the signal generating circuit based on the selection signal; Further provided with 18. The drive circuit of claim 17.

19. a pulse generating circuit that generates and outputs a control pulse based on a control signal; a plurality of electronic circuits to which the control pulses are sequentially input and which sequentially output waveform data in synchronization with the control pulses; a second selector circuit that inputs the control pulse output from the pulse generating circuit to any one of the plurality of electronic circuits based on a selection signal; a third selector circuit that inputs the waveform data output from any one of the plurality of electronic circuits to the signal generating circuit based on the selection signal; a signal generating circuit that generates a drive signal for a switching element based on the waveform data; a detection circuit for detecting an operating state of the switching element; a control circuit that generates the control signal and the selection signal based on the operating state; Equipped with The electronic circuit a shift register circuit including a plurality of charge holding circuits; a counter circuit that counts the number of the control pulses input to the shift register circuit; a first selector circuit that selects one of the outputs of the charge holding circuits based on the control signal and the count value of the counter circuit; a control system.

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