Transistor having source / drain regions with epitaxial semiconductor material segments

Abstract

The present invention relates to a transistor having a source / drain region with an epitaxial semiconductor material segment, and discloses a structure of a field effect transistor and a method for forming the structure of the field effect transistor. A first and a second gate structure extend above a semiconductor body. The source / drain region is laterally located between the first gate structure and the second gate structure. The source / drain region includes a semiconductor layer having a first segment, a second segment, and a third segment. A first portion of the semiconductor body is located between the first segment of the semiconductor layer and the second segment of the semiconductor layer. A second portion of the semiconductor body is located between the second segment of the semiconductor layer and the third segment of the semiconductor layer.

Description

Technical Field

[0001] The present invention relates to semiconductor device manufacturing and integrated circuits, and more particularly to a structure for a field effect transistor and a method for forming the structure for a field effect transistor. Background Art

[0002] A complementary metal oxide semiconductor (CMOS) process can be used to create a combination of p-type and n-type field effect transistors, which are used as devices to construct, for example, logic cells. A field effect transistor typically includes a source, a drain, a channel region between the source and the drain, and a gate electrode superimposed on the channel region. When a control voltage exceeding a characteristic threshold voltage is applied to the gate electrode, carrier flow occurs in the channel region between the source and the drain, thereby generating a device output current. A field effect transistor may include multiple gates superimposed on multiple channel regions.

[0003] One method of forming the source and drain of a field effect transistor is to implant ions containing p-type dopants or n-type dopants into a region of a semiconductor body to provide the source and drain. Another method is to epitaxially grow sections of semiconductor material from regions of the semiconductor body to provide the source and drain. The semiconductor material may be doped in situ with p-type dopants or n-type dopants during epitaxial growth.

[0004] A problem associated with wide gate spacing in multi-gate field effect transistors is underfilling of the semiconductor material epitaxially grown in the cavity to provide the source and drain. The underfilling may degrade device performance, for example, by reducing radio frequency performance indicators such as power gain. The underfilling may also degrade other performance indicators. For example, the drain current (Idsat) when the transistor is biased in the saturation region may be reduced. The contact resistance of the source and drain may be increased, and the underfilling may also cause contact open problems.

[0005] There is a need for improved structures for field effect transistors and methods of forming structures for field effect transistors. Summary of the invention

[0006] In one embodiment of the present invention, a structure for a field effect transistor is provided. The structure includes first and second gate structures extending above a semiconductor body, and a source / drain region laterally located between the first gate structure and the second gate structure. The source / drain region includes a semiconductor layer having a first section, a second section, and a third section. A first portion of the semiconductor body is located between the first section of the semiconductor layer and the second section of the semiconductor layer. A second portion of the semiconductor body is located between the second section of the semiconductor layer and the third section of the semiconductor layer.

[0007] In one embodiment of the present invention, a method of forming a structure for a field effect transistor is provided. The method includes forming first and second gate structures extending above a semiconductor body, and forming a first section, a second section, and a third section of a semiconductor layer laterally located between the first gate structure and the second gate structure. A portion of the semiconductor body is located between the first section of the semiconductor layer and the second section of the semiconductor layer. A second portion of the semiconductor body is located between the second section of the semiconductor layer and the third section of the semiconductor layer. The first section, the second section, and the third section of the semiconductor layer are components of a source / drain region of the field effect transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings, which are included in and constitute a part of this specification, illustrate various embodiments of the present invention and, together with the general description of the present invention made above and the detailed description of these embodiments made below, are used to explain these embodiments of the present invention. In the accompanying drawings, like reference numerals represent similar features in different views.

[0009] Figure 1-4 A cross-sectional view showing the structure of a field effect transistor at successive manufacturing stages of a processing method according to an embodiment of the present invention.

[0010] Figure 5A Display in Figure 4 A cross-sectional view of the structure following a manufacturing stage of the process.

[0011] Figure 5B , 5C 5D shows a vertical axis substantially parallel to the gate structure. Figure 5A Cross-sectional views of different parts of the structure.

[0012] Figure 6 Display in Figure 5A A cross-sectional view of the structure following a manufacturing stage of the process.

[0013] Figure 7 A cross-sectional view showing a structure according to an alternative embodiment of the present invention. DETAILED DESCRIPTION

[0014] Please refer to Figure 1 According to an embodiment of the present invention, the field effect transistor structure 10 includes a fin 12 disposed above a substrate 14 and protruding upward from the substrate. The fin 12 and the substrate 14 may be composed of a single crystal semiconductor material, such as single crystal silicon. The fin 12 may be formed by patterning the substrate 14 using a photolithography and etching process, or by a self-aligned multi-patterning process. The shallow trench isolation 16 ( Figure 5B , 5C , 5D) can surround the lower section 60 of the fin 12. The upper section 62 of the fin 12 is exposed above the top surface of the shallow trench isolation 16. The fin 12 defines a semiconductor body that can be used to form a field effect transistor. The upper section 62 of the fin 12 includes a top surface 11 and a side surface 13.

[0015] The gate structures 18 extend laterally along their respective longitudinal axes above and across the fins 12 and on the shallow trench isolations 16. Each gate structure 18 is aligned laterally with respect to the fins 12, overlapping and covering the top surface 11 and the side surface 13 of the upper section 62 of the fins 12. Each gate structure 18 may include a dummy gate 20 composed of a conductor (e.g., polysilicon) and a dielectric layer 22 composed of a dielectric material (e.g., silicon dioxide). A gate cap 21 may be disposed above each gate structure 18.

[0016] Sidewall spacers 24 are disposed adjacent to the side surfaces or sidewalls 19 of each gate structure 18. The sidewall spacers 24 may be formed by depositing a conformal layer of dielectric material (eg, low-k dielectric material) and etching the deposited conformal layer using an anisotropic etching process (eg, reactive ion etching).

[0017] Doped regions 26 and 28 may be formed in the fin 12 and laterally disposed between the side spacers 24 on adjacent pairs of gate structures 18. The doped regions 26 and 28 contain a certain concentration of n-type or p-type dopants. The doped regions 26 and 28 may be formed by an ion implantation process that introduces energetic ions, as indicated by a single arrow, and the ion trajectory stops within a certain depth range in the fin 12. The ions may be generated from a suitable source gas and implanted into the fin 12 using an ion implantation tool under given implantation conditions. Implantation conditions (e.g., ion species, dose, kinetic energy, tilt angle) may be selected to adjust the characteristics (e.g., depth distribution) of the doped regions 26 and 28. An implantation mask may be temporarily formed over a region (not shown) of the substrate 14 for forming other types of field effect transistors. The doped regions 26 and 28 extend to a depth d1 relative to the top surface 11 of the fin 12.

[0018] In one embodiment, the doped regions 26, 28 may be formed simultaneously in the fin 12 by implanting ions of a p-type dopant (e.g., boron) that provides p-type conductivity. In an alternative embodiment, the doped regions 26, 28 may be formed simultaneously in the fin 12 by implanting ions of an n-type dopant (e.g., phosphorus and / or arsenic) that provides n-type conductivity. In one embodiment, the dopant concentrations of the doped regions 26, 28 may be equal or substantially equal. The gate structure 18 and the sidewall spacers 24 may be used to self-align the ion implantation process that forms the doped regions 26, 28 in the fin 12.

[0019] In an alternative embodiment, doped regions 26 , 28 may be omitted from the device construction, thereby not changing the initial doping (if any) of fin 12 .

[0020] Please refer to Figure 2 , wherein similar reference numerals denote Figure 1 , and in the next manufacturing stage, a conformal layer 30 is deposited on the gate cap 21, the sidewall spacers 24, and the top surface 11 of the fin 12 above the doped regions 26, 28 on the gate structure 18 as a liner. The conformal layer 30 may be composed of a metal (e.g., tantalum, tantalum nitride, titanium, or titanium nitride) and may be deposited by, for example, atomic layer deposition. The material of the conformal layer 30 may be selected to be different from the material of the gate cap 21 and the sidewall spacers 24 to facilitate subsequent etching processes. The conformal layer 30 may be deposited with a conformal thickness t (which is independent of position).

[0021] Spacers 32 are formed by depositing a conformal layer over the gate cap 21, the side spacers 24, and the conformal layer 30 on the doped regions 26 and 28 on the gate structure 18, and etching by an anisotropic etching process. Spacers 32 may be composed of, for example, amorphous carbon, silicon dioxide, silicon nitride, or a metal oxide, and may be deposited by, for example, atomic layer deposition. The etching process may be a reactive ion etching process that selectively etches the material that constitutes the spacers 32 relative to the material that constitutes the conformal layer 30. When referring to a material removal process (e.g., etching), the term "selective" as used herein means that the material removal rate (i.e., etching rate) of the target material is higher than the material removal rate (i.e., etching rate) of at least another material exposed to the material removal process. Spacers 32 have a width established by the thickness of the etched conformal layer.

[0022] Please refer to Figure 3 , wherein similar reference numerals denote Figure 2 and in the next manufacturing stage, the conformal layer 30 is etched using an anisotropic etching process ( Figure 2). The etching process may be a reactive ion etching process that selectively etches the material constituting the conformal layer 30 relative to the material of the fin 12, the gate cap 21, the side spacers 24, and the spacers 32. The spacers 32 (which are temporary structural components and can be shortened by the etching process) mask the underlying portion of the conformal layer 30. Except for the masked portion of the conformal layer 30, the conformal layer 30 is removed by the etching process. The unremoved portion of the conformal layer 30 may have a width w1 that is equal to or substantially equal to the width of the spacers 32.

[0023] An opening 34 is defined between the spacer 32 and the side spacer 24. The opening 34 extends vertically to the top surface 11 of the fin 12 above each of the doped regions 26, 28. Since the overlying portion of the conformal layer 30 is completely removed by the etching process, the top surface 11 of the fin 12 is exposed at the bottom of the opening 34.

[0024] Please refer to Figure 4 , wherein similar reference numerals denote Figure 3 , and in the next manufacturing stage, cavities 36, 38, 40 are formed in the fins 12 between each adjacent pair of gate structures 18. The cavities 36, 38, 40 may extend into the fins 12 to a given depth d2. The cavities 36, 38, 40 may be formed by an etching process that is selective with respect to the materials of the gate cover 21, the side spacers 24, and the spacers 32. The spacers 32 act as a protective cover during the etching process to mask and maintain portions 41, 43 of the fins 12. Portion 41 of the fin 12 is laterally located between cavity 36 and cavity 38, and portion 43 of the fin 12 is laterally located between cavity 38 and cavity 40. The spacers 32 may be partially consumed and thereby shortened during the etching process. Portions 41, 43 of the fins 12 may have equal or substantially equal widths w2. Portions of conformal layer 30 are located on top surface 11 of fin 12 above portions 41 , 43 of fin 12 , and width w2 of portions 41 , 43 may be equal to or substantially equal to width w1 of overlying portions of conformal layer 30 .

[0025] The formation of the cavities 36, 38, 40 removes portions of the doped regions 26, 28 adjacent to the portions 41, 43 of the fin 12. The portions of the doped regions 26 remain intact within the respective portions 41, 43 of the fin 12 between a pair of gate structures 18, and the portions of the doped regions 28 remain intact within the respective portions 41, 43 of the fin 12 between another pair of gate structures 18. The portions of the doped regions 26, 28 may have a depth d1 ( Figure 1 ) have substantially equal thickness. In one embodiment, the depth d2 of the cavities 38 , 40 may be greater than the thickness of the doped regions 26 , 28 .

[0026] Please refer to Figure 5A ,5B , 5C, 5D, wherein similar reference numerals denote Figure 4 , and in the next manufacturing stage, the spacers 32 are removed by an etching process that is selective to the materials of the fins 12, the gate cap 21, the side spacers 24, and the conformal layer 30. The selective etching process may be a reactive etching process. The portion of the conformal layer 30 exposed by removing the spacers 32 is not removed, but remains on the top surface 11 above the portions 41, 43 of the fins 12.

[0027] A layer 42 containing epitaxial semiconductor material is grown in respective segments from the surface of the fin 12 bordering the cavities 36, 38, 40, and in particular from the side surfaces 13 of the portions 41, 43 of the fin 12 between the cavities 38, 40. The segments of the epitaxial semiconductor layer 42 are independently grown inside each of the cavities 36, 38, 40, thereby collectively providing a significantly larger surface area for epitaxial growth than a single large cavity. The epitaxial semiconductor layer 42 may extend laterally from the space between the gate structures 18. Each segment of the epitaxial semiconductor layer 42 is partially located in one of the cavities 36, 38, 40 and partially extends above the top surface 11 of the fin 12. Different segments of the epitaxial semiconductor layer 42 merge over the portions 41, 43 of the fin 12 and the portions of the conformal layer 30 located above the portions 41, 43 of the fin 12. Portions of the conformal layer 30 may be enclosed within the interior of the epitaxial semiconductor layer 42.

[0028] The epitaxial growth process may be selective in that the semiconductor material is not grown from dielectric surfaces, such as the surfaces of the shallow trench isolation 16, the gate cap 21, and the sidewall spacers 24. The epitaxial semiconductor layer 42 may be doped in situ during the epitaxial growth with a concentration of dopants. In one embodiment, the epitaxial semiconductor layer 42 may have the same conductivity type as the doped regions 26, 28. In one embodiment, the epitaxial semiconductor layer 42 may be doped in situ during the epitaxial growth with an n-type dopant, such as phosphorus and / or arsenic, that provides n-type conductivity. In an alternative embodiment, the epitaxial semiconductor layer 42 may be doped in situ during the epitaxial growth with a p-type dopant, such as boron, that provides p-type conductivity. The epitaxial semiconductor layer 42 may have a composition containing germanium and silicon, and in one embodiment, the epitaxial semiconductor layer 42 may be composed of silicon-germanium. In one embodiment, the epitaxial semiconductor layer 42 may be composed of silicon-germanium and may contain a p-type dopant, such as boron. In an alternative embodiment, the epitaxial semiconductor layer 42 may be composed of silicon and may contain an n-type dopant, such as phosphorus.

[0029] The segments of epitaxial semiconductor layer 42 in each group of cavities 36, 38, 40 contact portions 41 of fin 12 between cavities 36 and 38, and portions 43 of fin 12 between cavities 38 and 40. The segments of epitaxial semiconductor layer 42 in each cavity 36 may be in direct contact with one side surface 13 of portion 41 of fin 12, the segments of epitaxial semiconductor layer 42 in each cavity 38 may be in direct contact with one side surface 13 of portion 41 of fin 12 and one side surface 13 of portion 43 of fin 12, and the segments of epitaxial semiconductor layer 42 in each cavity 40 may be in direct contact with one side surface 13 of portion 43 of fin 12. Portions of doped regions 26 or portions of doped regions 28 are included in portions 41, 43 of fin 12 below portions of conformal layer 30. Portion 41 of fin 12 defines a separation between a section of epitaxial semiconductor layer 42 in cavity 36 and a section of epitaxial semiconductor layer 42 in cavity 38. Portion 43 of fin 12 defines a separation between a section of epitaxial semiconductor layer 42 in cavity 38 and a section of epitaxial semiconductor layer 42 in cavity 40.

[0030] Please refer to Figure 6 , wherein similar reference numerals denote Figure 5A , and in the next manufacturing stage, a replacement gate process is performed to replace the gate structure 18 with the gate structures 46, 47, 48 and complete the structure 10 of the field effect transistor. The gate structures 46, 47, 48 may include an electrode layer 64 composed of one or more metal gate materials (e.g., work function metals) and a gate dielectric layer 66 composed of a dielectric material (e.g., a high-k dielectric material such as hafnium oxide). The gate structures 46, 47, 48 have opposite side surfaces 49, and the side spacers 24 are adjacent to the side surfaces 49.

[0031] The structure 10 includes a source / drain region 50 provided by a segment of an epitaxial semiconductor layer 42, portions 41, 43 of the fin 12, and a doped region 26 located in portions 41, 43 of the fin 12. The structure 10 includes a source / drain region 52 provided by a segment of an epitaxial semiconductor layer 42, portions 41, 43 of the fin 12, and a doped region 28 located in portions 41, 43 of the fin 12. The term "source / drain region" as used herein refers to a doped region of semiconductor material that can serve as a source or drain of a field effect transistor. In one embodiment, the source / drain region 50 can provide a source in the structure 10, and the source / drain region 52 can provide a drain in the structure 10. In an alternative embodiment, the source / drain region 50 can provide a drain in the structure 10, and the source / drain region 52 can provide a source in the structure 10. The source / drain regions 50, 52 are doped to have the same polarity of conductivity type.

[0032] The source / drain region 50 is located between the side surface 49 of the gate structure 46 and the side surface 49 of the gate structure 47, and the source / drain region 52 is located between the side surface 49 of the gate structure 47 and the side surface 49 of the gate structure 48. The fin 12 provides a semiconductor body for forming the source / drain regions 50, 52. The channel region 55 is provided in the portion of the fin 12 between the source / drain region 50 and the source / drain region 52 and below the overlying gate structure 47.

[0033] Then, the middle process and back-end process are performed, including forming contacts, vias, and interconnection structures coupled to the field effect transistor. The contacts 56 in the interlayer dielectric layer 58 of the interconnection structures are coupled to the source / drain regions 50 and 52 .

[0034] The source / drain regions 50, 52 may exhibit improvements in filling with the epitaxial semiconductor material of the epitaxial semiconductor layer 42. Relying on a group of smaller cavities 36, 38, 40 rather than a single larger cavity with epitaxially grown semiconductor material provides a smaller filling volume and can compensate for a larger gate spacing to alleviate underfilling. Due to the segmented formation and the reduction of underfilling, the source / drain regions 50, 52 may include a larger overall volume of epitaxial semiconductor material. The structure 10 may include additional gate structures with wider gate spacings, and the source / drain regions 50, 52 may be repeated for pairs of gate structures to form multi-gate field effect transistors for radio frequency integrated circuits. Adding portions of the conformal layer 30 composed of metal to the source / drain regions 50, 52 may be used to reduce the contact resistance of the source / drain regions 50, 52.

[0035] Please refer to Figure 7 , wherein similar reference numerals denote Figure 6 According to alternative embodiments, the width of the spacer 32 and / or the thickness of the conformal layer 30 can be used to adjust the width of each segment of the epitaxial semiconductor layer 42 in each set of cavities 36, 38, 40 and the width of the portions 41, 43 of the fin 12. Figure 7 , the width of the spacer 32 may be increased, and the thickness of the conformal layer 30 may also be increased to accommodate a wider gate pitch. Although not shown, the source / drain region 52 may be modified in a similar manner to the source / drain region 50. The width of the spacer 32 and the thickness of the conformal layer 30 may be adjusted to adjust the formation of the source / drain regions 50, 52 for different gate pitches of the gate structures 46, 47, 48.

[0036] The above method is used for the manufacture of integrated circuit chips. The manufacturer can distribute the resulting integrated circuit chips in raw wafer form (e.g., as a single wafer with multiple unpackaged chips), as a bare chip, or in a packaged form. In the latter case, the chip is mounted in a single-chip package (e.g., a plastic carrier with pins attached to a motherboard or other higher-level carrier) or in a multi-chip package (e.g., a ceramic carrier with single-sided or double-sided interconnects or embedded interconnects). In any case, the chip can be integrated with other chips, discrete circuit elements and / or other signal processing devices as part of an intermediate product or a final product.

[0037] Terms such as "vertical", "horizontal", etc. are cited herein as examples to establish a reference frame and are not limiting. The term "horizontal" as used herein is defined as a plane parallel to the conventional plane of the semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms "vertical" and "orthogonal" refer to directions perpendicular to the horizontal plane as just defined. The term "lateral" refers to a direction within the horizontal plane.

[0038] Terms modified by approximate language such as "about," "approximately," and "substantially" cited herein are not limited to the exact value specified. The approximate language may correspond to the precision of the instrument used to measure the value, and may represent + / -10% of the value unless otherwise dependent on the precision of the instrument.

[0039] A feature that is "connected" or "coupled" to another feature may be directly connected or coupled to the other feature, or one or more intermediate features may be present. A feature may be "directly connected" or "directly coupled" to another feature if there are no intermediate features. A feature may be "not directly connected" or "not directly coupled" to another feature if there are at least one intermediate feature. A feature that is "on" or "in contact with" another feature may be directly on or in direct contact with the other feature, or one or more intermediate features may be present. A feature may be directly "on" or "in direct contact with" another feature if there are no intermediate features. A feature may not be "directly" "on" or "not directly in contact with" another feature if there are at least one intermediate feature.

[0040] The description of various embodiments of the present invention is for illustrative purposes and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein are selected to best explain the principles of the embodiments, practical applications, or technical improvements over commercially known technologies, or to enable those of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A structure for a field effect transistor, the structure comprising: Semiconductor substrate; A semiconductor fin protrudes from the semiconductor substrate, the semiconductor fin comprising an upper section and a lower section located between the upper section and the semiconductor substrate, and the upper section of the semiconductor fin comprises a first cavity, a second cavity and a third cavity; A first gate structure extending above the semiconductor fin; a second gate structure extending above the semiconductor fin; as well as a first source / drain region laterally located between the first gate structure and the second gate structure, the first source / drain region comprising a first semiconductor layer having a first section located in the first cavity, a second section located in the second cavity, and a third section located in the third cavity, The semiconductor fin includes a first part and a second part, the first part of the semiconductor fin is located between the first section of the first semiconductor layer and the second section of the first semiconductor layer, and the second part of the semiconductor fin is located between the second section of the first semiconductor layer and the third section of the first semiconductor layer.

2. The structure of claim 1, wherein: The second section of the first semiconductor layer located in the second cavity directly contacts the first portion of the semiconductor fin, and the second section of the first semiconductor layer located in the second cavity directly contacts the second portion of the semiconductor fin.

3. The structure of claim 2, wherein: The first section of the first semiconductor layer located in the first cavity directly contacts the first portion of the semiconductor fin, and the third section of the first semiconductor layer located in the third cavity directly contacts the second portion of the semiconductor fin.

4. The structure of claim 1, wherein: The semiconductor fin has a top surface, and the first section, the second section, and the third section of the first semiconductor layer include respective portions that merge over the first portion of the semiconductor fin and the second portion of the semiconductor fin.

5. The structure of claim 1, wherein: The semiconductor fin has a top surface, the first portion of the semiconductor fin includes a first doped region containing a first dopant, the second portion of the semiconductor fin includes a second doped region containing the first dopant, and the first doped region and the second doped region have substantially the same thickness relative to the top surface of the semiconductor fin.

6. The structure of claim 1, wherein: The semiconductor fin has a top surface, and a first portion of a layer is located on the top surface of the semiconductor fin above the first portion of the semiconductor fin, and a second portion of the layer is located on the top surface of the semiconductor fin above the second portion of the semiconductor fin.

7. The structure of claim 6, wherein: The first segment, the second segment, and the third segment of the first semiconductor layer include respective portions that merge over the first portion of the layer and the second portion of the layer.

8. The structure of claim 6, wherein: This layer consists of metal.

9. The structure of claim 6, wherein: The first portion and the second portion of the layer are directly on the top surface of the semiconductor fin.

10. The structure of claim 1, further comprising: A contact is connected to the first source / drain region.

11. The structure of claim 1, further comprising: The second source / drain region includes a second semiconductor layer having a first section, a second section and a third section, The semiconductor fin includes a third part and a fourth part, the third part of the semiconductor fin is located between the first section of the second semiconductor layer and the second section of the second semiconductor layer, the fourth part of the semiconductor fin is located between the second section of the second semiconductor layer and the third section of the second semiconductor layer, and the first gate structure is laterally located between the first source / drain region and the second source / drain region.

12. A method of forming a structure for a field effect transistor, the method comprising: forming a first gate structure extending above the semiconductor fin; forming a second gate structure extending above the semiconductor fin; forming a first cavity, a second cavity and a third cavity in an upper section of the semiconductor fin, wherein the semiconductor fin includes a lower section between the upper section and a semiconductor substrate; forming a first section, a second section and a third section of a semiconductor layer in the first cavity, the second cavity and the third cavity respectively; wherein the semiconductor fin protrudes from the semiconductor substrate, The semiconductor fin includes a first part and a second part, the first part of the semiconductor fin is located between the first section of the semiconductor layer and the second section of the semiconductor layer, the second part of the semiconductor fin is located between the second section of the semiconductor layer and the third section of the semiconductor layer, and the first section, the second section and the third section of the semiconductor layer are components of the source / drain region of the field effect transistor, and the source / drain region of the field effect transistor is laterally located between the first gate structure and the second gate structure.

13. The method according to claim 12, in, The first section of the semiconductor layer is epitaxially grown in the first cavity, the second section of the semiconductor layer is epitaxially grown in the second cavity, and the third section of the semiconductor layer is epitaxially grown in the third cavity.

14. The method of claim 13, wherein: Forming the first segment, the second segment, and the third segment of the semiconductor layer laterally located between the first gate structure and the second gate structure includes: A first spacer and a second spacer are formed on the semiconductor fin at respective positions laterally located between the first gate structure and the second gate structure.

15. The method of claim 14, wherein: Forming the first cavity, the second cavity, and the third cavity in the semiconductor fin includes: The semiconductor fin is etched by utilizing the first spacer and the second spacer on the semiconductor fin to form the first cavity, the second cavity, and the third cavity in the semiconductor fin.

16. The method of claim 15, wherein: The first portion of the semiconductor fin is located below the first spacer, and the second portion of the semiconductor fin is located below the second spacer.

17. The method of claim 15, wherein: The first cavity is formed in the semiconductor fin laterally located between the first gate structure and the first spacer, the second cavity is formed in the semiconductor fin laterally located between the first spacer and the second spacer, and the third cavity is formed in the semiconductor fin laterally located between the second spacer and the second gate structure.

Images