Large panel display with reduced routing line resistance

Abstract

The present disclosure relates to large panel displays with reduced routing line resistance. Disclosed herein is an electronic device that can include a display having pixels formed with light emitting diodes, thin film silicon transistors, thin film semiconductor oxide transistors, and capacitors. The silicon transistors, semiconductor transistors, and capacitors can have control terminals coupled to gate lines or routing lines that extend across the face of the display and are formed in a low resistance source-drain metal routing layer. Forming the routing / gate lines with the low resistance source-drain metal routing layer significantly reduces the resistance of the gate lines, which enables better timing margins for large display panels operating at higher refresh rates.

Description

[0001] This patent application claims priority to U.S. Patent Application No. 17 / 143,939, filed January 7, 2021, and U.S. Provisional Patent Application No. 62 / 994,747, filed March 25, 2020, which are hereby incorporated by reference in their entirety. BACKGROUND

[0002] The present disclosure relates generally to electronic devices, and more particularly to electronic devices having displays.

[0003] Electronic devices often include displays. For example, an electronic device can have an organic light emitting diode (OLED) display based on organic light emitting diode pixels. In this type of display, each pixel includes a light emitting diode and a thin film transistor for controlling the application of a signal to the light emitting diode to produce light. The light emitting diode can include an OLED layer positioned between an anode and a cathode.

[0004] Conventional displays often include gate drivers for outputting scan control signals to corresponding rows of pixels via respective scan lines. The scan lines are often connected to low temperature poly silicon (LTPS) transistors and are routed across the face of the display with high resistance metal. This can not be a problem for devices with smaller displays, but for devices with large panel displays operating at high refresh rates such as 120Hz, the amount of load on the high resistance scan lines can be increased such that the rise and fall times of the scan control signals are increased to a point where data can no longer be properly sampled onto the display pixels. SUMMARY

[0005] An electronic device having a display is provided. The display can include an array of pixels formed in an active area. Each pixel can include an organic light emitting diode coupled to an associated thin film transistor (TFT) structure such as one or more silicon transistors, one or more semiconductor oxide transistors, and / or one or more capacitors.

[0006] The pixels can be formed on a substrate. In particular, the silicon transistors can include an active silicon region formed on the substrate and a gate conductor formed in a first gate metal layer. The capacitors can include a first capacitor terminal formed in the first gate metal layer and a second capacitor terminal formed in a second gate metal layer. The semiconductor oxide transistors can include a semiconductor oxide region formed over the second gate metal layer and a gate conductor formed in a third gate metal layer. The conductors formed in the first, second, and third gate metal layers can be formed with high resistance metals such as molybdenum and / or titanium.

[0007] The gate conductors of the silicon transistors, the second capacitor terminal, and the gate conductors of the semiconductor oxide transistors can be coupled to respective routing lines formed in a first source-drain (SD1) routing layer above the third gate metal layer. The conductors in the SD1 routing layer can be formed with a low-resistance metal such as aluminum, copper, silver, or gold. The SD1 routing lines coupled to the gate conductors of the silicon transistors and the semiconductor oxide transistors can be used as gate lines, scan lines, emission lines, initialization lines, reset lines, or other row control lines. Routing the row control lines in the SD1 routing layer can help reduce the resistance on these lines, which will improve the timing margin for large display panels operating at high refresh rates.

[0008] A first planarization layer can be formed above the SD1 routing layer. A second source-drain (SD2) routing layer can be formed on the first planarization layer. A second planarization layer can be formed on the first planarization layer. The routing lines in the SD2 layer can be configured to route power supply signals such as a positive power supply voltage and a ground power supply voltage. The power supply lines can be routed in any direction through the active area to help ensure that the point of highest voltage drop associated with the ground power supply lines is located at the center of the display and / or to reduce brightness differences across the display. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 is a schematic diagram of an exemplary electronic device having a display in accordance with an embodiment.

[0010] Figure 2A is a diagram of an exemplary display having an array of light-emitting elements in accordance with an embodiment.

[0011] Figure 2B is a circuit diagram of an exemplary display pixel in accordance with an embodiment.

[0012] Figure 3 is a cross-sectional side view of an exemplary thin-film transistor circuit in a display in accordance with an embodiment.

[0013] Figure 4 is a cross-sectional side view of an exemplary low-resistance routing structure in accordance with an embodiment.

[0014] Figure 5 is a top plan view of a display pixel showing how gate conductors are coupled to routing lines formed in a first source-drain (SD1) layer in accordance with an embodiment.

[0015] Figure 6 is a top plan view of a display pixel showing how gate conductors are coupled to routing lines formed in a second source-drain (SD2) layer in accordance with an embodiment.

[0016] Figure 7This is a top plan view of a display according to one embodiment, illustrating how multiple grounding power lines can be routed across the surface of the display.

[0017] Figure 8 This is a top plan view of a display according to one embodiment, illustrating how multiple positive power lines can be routed across the surface of the display. Detailed Implementation

[0018] Figure 1 The illustration shows exemplary electronic devices of various types that may have displays. Electronic device 10 may be a computing device such as a laptop computer, a computer monitor containing an embedded computer, a tablet computer, a cellular phone, a media player or other handheld or portable electronic device, a smaller device (such as a wristwatch, a hanging device, a headset or handset, a device embedded in glasses or other equipment worn on a user's head, or other wearable or micro-devices), a display, a computer monitor containing an embedded computer, a computer monitor not containing an embedded computer, a gaming device, a navigation device, an embedded system (such as a system in which electronic equipment with a display is installed in an information kiosk or a car), or other electronic equipment. Electronic device 10 may have the shape of a pair of glasses (e.g., a support frame), may be formed with a helmet-shaped shell, or may have other configurations for helping to mount and secure components of one or more displays on or near a user's head.

[0019] like Figure 1 As shown, the electronic device 10 may include control circuitry 16 for supporting the operation of the device 10. Control circuitry 16 may include storage devices such as hard disk drive storage devices, non-volatile memory (e.g., flash memory configured to form a solid-state drive or other electrically programmable read-only memory), volatile memory (e.g., static random access memory or dynamic random access memory), and so on. Processing circuitry in control circuitry 16 can be used to control the operation of device 10. This processing circuitry may be based on one or more microprocessors, microcontrollers, digital signal processors, baseband processors, power management units, audio chips, application-specific integrated circuits, etc.

[0020] Input-output circuitry in device 10, such as input-output device 12, can be used to allow data to be supplied to device 10 and to be supplied from device 10 to external devices. Input-output device 12 may include buttons, joysticks, scroll wheels, touchpads, keypads, keyboards, microphones, speakers, audio generators, vibrators, cameras, sensors, LEDs and other status indicators, data ports, etc. Users can control the operation of device 10 by supplying commands through the input resources of input-output device 12, and can receive status information and other outputs from device 10 using the output resources of input-output device 12.

[0021] Input-output device 12 can include one or more displays, such as display 14. Display 14 can be a touchscreen display that includes a touch sensor for gathering touch input from a user, or display 14 can be touch-insensitive. The touch sensor of display 14 can be based on an array of capacitive touch sensor electrodes, acoustic touch sensor structures, resistive touch components, force-based touch sensor structures, light-based touch sensors, or other suitable touch sensor arrangements. The touch sensor for display 14 can be formed from electrodes formed on a common display substrate with the display pixels of display 14, or can be formed from a separate touch sensor panel that overlaps the pixels of display 14. If desired, display 14 can be touch-insensitive (i.e., the touch sensor can be omitted). Display 14 in electronic device 10 can be a heads-up display, which can be viewed without requiring the user to look away from a typical viewpoint, or can be a head-mounted display incorporated into a device worn on the user's head. If desired, display 14 can also be a holographic display for displaying holograms.

[0022] Control circuit 16 can be used to run software on device 10, such as operating system code and application programs. During operation of device 10, software running on control circuit 16 can display images on display 14.

[0023] Display 14 can be an organic light-emitting diode display or can be a display based on other types of display technology. Device configurations in which display 14 is an organic light-emitting diode display are described as examples at times herein. However, this is merely illustrative. If desired, any suitable type of display can be used. In general, display 14 can have a rectangular shape (i.e., display 14 can have a rectangular footprint and a rectangular perimeter edge extending around the rectangular footprint) or can have other suitable shapes. Display 14 can be planar or can have a curved profile.

[0024] Figure 2A A top view of a portion of display 14 is shown in FIG. 1C. As shown in FIG. 1C, display 14 can include a plurality of display pixels 18. Display pixels 18 can be arranged in rows and columns. In general, display pixels 18 can be arranged in any suitable manner. For example, display pixels 18 can be arranged in a rectangular grid pattern. If desired, display pixels 18 can be arranged in other suitable patterns. Figure 2AAs shown, the display 14 can have an array of pixels 22 formed on a substrate. The pixels 22 can receive data signals over signal paths such as data lines D, and can receive one or more control signals over control signal paths such as horizontal control lines G (sometimes referred to as gate lines, scan lines, emission control lines, etc.). There can be any suitable number of rows and columns of pixels 22 in the display 14 (e.g., tens or more, hundreds or more, or thousands or more). Each pixel 22 can have a light-emitting diode 26 that emits light 24 under the control of pixel control circuitry formed from thin-film transistor circuitry such as thin-film transistors 28 and thin-film capacitors. The thin-film transistors 28 can be polycrystalline silicon thin-film transistors, semiconductor oxide thin-film transistors (such as indium gallium zinc oxide (IGZO) transistors), and / or thin-film transistors formed from other semiconductors. The pixels 22 can include light-emitting diodes of different colors (e.g., red, green, and blue) to provide the display 14 with the ability to display color images, or can be monochrome pixels.

[0025] A display driver circuit can be used to control the operation of the pixels 22. The display driver circuit can be formed from integrated circuits, thin-film transistor circuitry, and / or other suitable circuitry. Figure 2A The display driver circuit 30 can include communication circuitry for communicating with a system control circuit such as the control circuit 16 over a path 32. The path 32 can be formed from traces on a flexible printed circuit or other cabling. During operation, the control circuit (e.g., the control circuit 16) can provide the display driver circuit 30 with information about the images to be displayed on the display 14. Figure 1 Figure 1 The control circuit 16 can provide the display driver circuit 30 with information about the images to be displayed on the display 14.

[0026] To display an image on the display pixels 22, the display driver circuit 30 can provide image data onto the corresponding data lines, while issuing clock signals and other control signals to support display driver circuits such as the gate driver circuit 34 over the path 38. Data signals D, a positive power supply signal VDD, and a ground power supply signal VSS can be supplied to each column of pixels via corresponding column lines 40. If desired, the display driver circuit 30 can also provide clock signals and other control signals to the gate driver circuit 34 on the opposite edge of the display 14.

[0027] ​The gate driver circuit 34 (sometimes referred to as the row control circuit) may be implemented as part of an integrated circuit and / or may be implemented using thin-film transistor circuitry. The horizontal control lines 42 in the display 14 may carry gate (G) line signals, such as scan line signals, transmit enable control signals, reset signals, initialization signals, reference signals, and other horizontal control signals for controlling each row of display pixels 22. Any suitable number of horizontal control signals may be present per row of pixels 22 (e.g., one or more row control signals, two or more row control signals, three or more row control signals, four or more row control signals, etc.).

[0028] The area on display 14 that forms display pixels 22 is sometimes referred to herein as the effective area (AA). Electronic device 10 has an outer casing with peripheral edges. The area surrounding the effective area and within the peripheral edges of device 10 is the boundary area. Images can only be displayed to the user of the device within the effective area. It is generally desirable to minimize the boundary area of ​​device 10. For example, device 10 may be provided with a full-screen display 14 extending across the entire front of the device. If desired, display 14 may also wrap around the edges of the front, such that at least a portion of the side edges or at least a portion of the back surface of device 10 is used for display purposes.

[0029] Figure 2B This is a circuit diagram illustrating an organic light-emitting diode (OLED) display pixel 22 in display 14. Figure 2B As shown, display pixel 22 may include a storage capacitor Cst and associated pixel transistors, such as a semiconductor oxide transistor Toxide, a drive transistor Tdrive, a data loading transistor Tdata, a first emitter transistor Tem1, a second emitter transistor Tem2, and an anode reset transistor Tar. While the transistor Toxide is formed using semiconductor oxides (e.g., transistors having an n-type channel formed from semiconductor oxides such as indium gallium zinc oxide or IGZO), other transistors may be thin-film transistors formed from semiconductors such as silicon (e.g., polycrystalline silicon channels deposited using low-temperature processes, sometimes referred to as "LTPS" or low-temperature polycrystalline silicon). Semiconductor oxide transistors exhibit lower leakage than silicon transistors, therefore implementing the transistor Toxide as a semiconductor oxide transistor will help reduce flicker (e.g., by preventing current leakage away from the gate terminal of the drive transistor Tdrive).

[0030] In another suitable arrangement, transistors Toxide and Tdrive can be implemented as semiconductor oxide transistors, while the remaining transistors Tdata, Temi, Tem2, and Tar are silicon (LTPS) transistors. Transistor Tdrive acts as a drive transistor and has a threshold voltage that is critical to the emission current of pixel 22. Since the threshold voltage of transistor Tdrive can experience hysteresis, forming the drive transistor as a top-gate semiconductor oxide transistor can help reduce hysteresis (e.g., a top-gate IGZO transistor experiences less Vth hysteresis than a silicon transistor). If desired, any of the remaining transistors Tdata, Temi, Tem2, and Tar can be implemented as semiconductor oxide transistors. In yet another suitable arrangement, all of the transistors within pixel 22 can be implemented as silicon transistors (i.e., pixel 22 need not include any semiconductor oxide transistors). Generally, any silicon transistor can be n-type (i.e., n-channel) or p-type (i.e., p-channel) LTPS thin-film transistor. If desired, pixel 22 can include more or fewer than six transistors and / or can include more or fewer than one internal capacitor.

[0031] Display pixel 22 can include an organic light emitting diode (OLED) 204. A positive supply voltage VDDEL can be provided to positive supply terminal 200, and a ground supply voltage VSS EL can be provided to ground supply terminal 202. Positive supply voltage VDDEL can be 3 V, 4 V, 5 V, 6 V, 7 V, 2 V to 8 V, or any suitable positive supply voltage level. Ground supply voltage VSS EL can be 0 V, -1 V, -2 V, -3 V, -4 V, -5 V, -6 V, -7 V, or any suitable ground or negative supply voltage level. The state of drive transistor Tdrive controls the amount of current flowing from terminal 200 to terminal 202 through diode 204, and thus controls the amount of emitted light from display pixel 22. Organic light emitting diode 204 can have an associated parasitic capacitance C OLED (not shown).

[0032] Terminal 209 can be used to provide an anode reset voltage Var to help turn off diode 204 when diode 204 is not in use. Thus, terminal 209 is sometimes referred to as an anode reset or initialization line. The anode reset voltage Var can be provided from a display driver circuit such as display driver circuit 100 (FIG. 1) or display driver circuit 200 (FIG. 2). Figure 2AControl signals for the row driver circuit 34 are provided to control terminals, such as row control terminals 212, 214-1, 214-2, and 214-3. The row control terminal 212 can function as an emission control terminal (sometimes referred to as an emission line or emission control line), while the row control terminals 214-1, 214-2, and 214-3 can function as a first scan control terminal, a second scan control terminal, and a third scan control terminal (sometimes referred to as scan lines or scan control lines). An emission control signal EM can be provided to the terminal 212. Scan control signals SCI, SC2, and SC3 can be applied to the scan terminals 214-1, 214-2, and 214-3, respectively. A data input terminal, such as a data signal terminal 210, is coupled to a respective data line D for receiving image data for the display pixel 22. The data terminal 210 can also be referred to as a data line. Figure 2A

[0033] In the example of FIG. 1, the transistor Teml, Tdrive, Tem2, and OLED 304 can be coupled in series between the power terminal 200 and the power terminal 202. Specifically, a first emission control transistor Teml can have a source terminal coupled to the positive power terminal 200, a gate terminal that receives an emission control signal EM2 via the emission line 212, and a drain terminal (labeled as node 1). The terms “source” and “drain” terminals of a transistor can sometimes be used interchangeably, and thus can be referred to as “source-drain” terminals. The drive transistor Tdrive can have a source terminal coupled to node 1, a gate terminal (labeled as node 2), and a drain terminal (labeled as node 3). A second emission control transistor Tem2 can have a source terminal coupled to node 3, a gate terminal that also receives the emission control signal EM via the emission line 212, and a drain terminal (labeled as node 4) that is coupled to the ground power terminal 202 via the light emitting diode 204. Configured in this way, the emission control signal EM can be asserted during an emission phase to turn on the transistors Teml and Tem2 to allow current to flow through the light emitting diode 204. Figure 2B

[0034] A storage capacitor Cst can have a first terminal coupled to the positive power line 200 and a second terminal coupled to node 2. Image data loaded into the pixel 22 can be at least partially stored on the pixel 22 by using the capacitor Cst to hold a charge throughout the emission phase. A transistor Toxide can have a source terminal coupled to node 2, a gate terminal configured to receive a scan control signal SCI via the scan line 214-1, and a drain terminal coupled to node 3. The signal SCI can be asserted to turn on the transistor Toxide, thereby shorting the drain and gate terminals of the transistor Tdrive. A transistor configuration in which the gate and drain terminals are shorted is sometimes referred to as being “diode-connected.”

[0035] ​​The data loading transistor Tdata may have a source terminal coupled to data line 210, a gate terminal configured to receive scan control signal SC2 via scan line 214-2, and a drain terminal coupled to node 1. In this configuration, signal SC2 can be asserted to turn on transistor Tdata, which will allow the data voltage from data line 210 to be loaded onto node 1. The transistor Tar may have a source terminal coupled to node 4, a gate terminal configured to receive scan control signal SC3 via scan line 214-3, and a drain terminal coupled to initialization line 209. In this configuration, scan control signal SC3 can be asserted to turn on transistor Tar, which will drive node 4 to the anode reset voltage level Var. If needed, the anode reset voltage Var on line 209 can be dynamically biased to different levels during operation of pixel 22.

[0036] Figure 3 This is a cross-sectional side view of an exemplary thin-film transistor circuit that may be included within display pixel 22 according to one embodiment. Figure 3 As shown, the display stack-up structure may include a substrate layer such as substrate 302, which may include one or more semiconductor layers, one or more insulating layers, a combination of semiconductor layers and insulating layers, one or more buffer layers, etc. In some embodiments, substrate 302 may be formed of glass, metal, plastic, ceramic, sapphire, or other suitable substrate materials. For example, substrate 302 may be an organic substrate formed of polyimide (PI), polyethylene terephthalate (PET), or polyethylene naphthalate (PEN). The surface of substrate 302 may optionally be covered with one or more buffer layers (e.g., inorganic buffer layers, such as silicon oxide layers, silicon nitride layers, etc.).

[0037] A polysilicon layer (e.g., an LTPS layer) may be formed on substrate 302, patterned, and etched to form LTPS region 352. The two opposite ends of LTPS region 406 may optionally be doped (e.g., n-doped or p-doped) to form source-drain regions of silicon transistor 350. Figure 3 The thin-film silicon transistor 350 in the cross-section can generally represent any LTPS transistor within pixel 22.

[0038] A gate insulating layer 304 may be formed on the substrate 302 and over the silicon region 352. A first metal layer (e.g., a first gate metal layer "GE1") may be formed over the gate insulating layer 304. The first metal layer may be patterned and etched to form the gate conductor of the transistor 350. Figure 3 In the example, the first metal layer can also be patterned and etched to form the first terminal of the storage capacitor Cst (e.g., GE1 can also be used to form the substrate of the storage capacitor). Any additional capacitor structure within pixel 22 (inFigure 3 The pixel 22 can also have one of its capacitor terminals formed in the GE1 metal layer (not shown in FIG. 3A in order not to obscure the present embodiment).

[0039] A first interlayer dielectric (ILD1) layer 306 can be formed over the first gate metal layer GE1 and the silicon transistor 350. The dielectric layer 306 can be formed, for example, of silicon nitride, silicon oxide, and other suitable insulating materials. A second metal layer (e.g., a second gate metal layer "GE2") can be formed on the ILD1 layer 306. The second metal layer can be patterned and etched to form a second terminal of the storage capacitor Cst (e.g., GE2 can be used to form the top plate of the storage capacitor). If desired, any additional capacitor structures within the pixel 22 (e.g., a capacitor Cst' in FIG. 3A) can be formed at this time. Figure 3 The pixel 22 can also have one of its capacitor terminals formed in the GE2 metal layer (not shown in FIG. 3A in order not to obscure the present embodiment).

[0040] A second interlayer dielectric (ILD2) layer 308 can be formed over the second gate metal layer GE2 and over the capacitor Cst. The dielectric layer 308 can be formed of silicon nitride, silicon oxide, and other suitable insulating materials. One or more buffer layers such as a buffer layer 310 (e.g., an inorganic buffer layer such as a silicon oxide layer, a silicon nitride layer, etc.) can be formed over the dielectric layer 308.

[0041] A semiconductor oxide layer (e.g., an IGZO layer) can be formed over the buffer layer 310, which is sometimes referred to as an oxide buffer layer. The semiconductor oxide layer can be patterned and etched to form a semiconductor oxide region 362. An insulating layer such as a gate insulator layer 311 can be formed on the IGZO region 362. An oxide (third) gate metal layer "OGE" can be formed on the gate insulator layer 311 to serve as a gate conductor for the semiconductor oxide transistor 360. The source-drain regions of the oxide region 362 can be n-doped or p-doped by hydrogenation, ion implantation, or other suitable doping methods. Another interlayer dielectric (OILD) layer 312 can be formed on the buffer layer 310 and over the transistor 360. Figure 3 The thin-film semiconductor oxide transistor 360 in cross-section can represent generally any semiconductor oxide transistor within the pixel 22. In other suitable arrangements in which the pixel 22 does not include any semiconductor oxide transistor, one or more of the layers such as the oxide buffer layer 310, the semiconductor oxide region 362, the gate liner 311, the OGE layer, and / or the oxide ILD layer 312 can not be formed at the time of manufacturing the pixel 22.

[0042] A first interconnect layer above the silicon transistor 350 and above the semiconductor oxide transistor 360 can be formed on the dielectric layer 312. Conductive routing structures formed in the first interconnect layer can be coupled down to the source-drain regions of each of the underlying transistors in the pixel 22, and thus can sometimes be referred to as a first source-drain metal layer “SD1.” In Figure 3 In the example of FIG. 3, the source-drain terminals of the silicon region 352 can be coupled to corresponding SD1 conductors through conductive vias 370 (e.g., contacts 370 through layers 304, 306, 308, 310, and 312). The source-drain terminals of the semiconductor oxide region 362 can also be coupled to corresponding SD1 conductors through conductive vias 372 (e.g., contacts 372 through layer 312).

[0043] The gate metal conductors can also be coupled to the SD1 routing conductors. For example, the GE1 gate conductor of the silicon transistor 350 can be coupled to a corresponding SD1 conductor through a conductive via 371. The OGE gate conductor of the optional semiconductor oxide transistor 360 can be coupled to a corresponding SD1 conductor through a conductive via 373. The GE2 top plate terminal of the capacitor can also be coupled to a corresponding SD1 conductor through a conductive via 375.

[0044] A first planarization (PLN1) layer such as layer 314 can be formed above the SD1 metal routing layer. A second interconnect layer can also be formed on the first planarization layer 314. Conductive routing structures formed in the second interconnect layer can be coupled down to the SD1 conductors, and thus can sometimes be referred to as a second source-drain metal layer “SD2.”

[0045] A second planarization (PLN2) layer such as layer 316 can be formed on the planarization layer 314 and above the SD2 routing metal lines. The planarization layers 314 and 316 can be formed of an organic dielectric material such as a polymer. In contrast, the layers below the organic planarization layers such as layers 304, 306, 308, 310, and 312 are typically formed of an inorganic dielectric material such as silicon nitride, silicon oxide, etc.

[0046] An anode 318 (e.g., the anode terminal of the organic light emitting diode 204 of FIG. 1) can be formed above the second planarization layer 316. Additional structures can be formed above the anode 318. For example, pixel defining layers, light emitting diode emissive materials, cathodes, and other pixel structures can also be included in the layer stack of the display pixel 22. However, these additional structures are omitted for brevity. Figure 2B

[0047] ​The GE1 gate conductor of display pixel silicon transistors, the GE2 capacitor terminal of display pixel capacitors, and the OGE gate conductor of display pixel semiconductor oxide transistors are typically formed using high-resistivity materials (such as molybdenum, titanium, some combination of high-resistivity materials, or other suitable metals). This high-resistivity material is required to form these gate metal conductors due to the requirements of the LTPS process used in manufacturing silicon transistors.

[0048] Figure 4 This is a cross-sectional side view of an illustrative SD1 or SD2 route conductor. (Example) Figure 4 As shown, the SD1 / SD2 routing conductor may include a low-resistivity material 404 optionally sandwiched between two high-resistivity liners 402. The liners 402 may be formed using molybdenum, titanium, some combination of high-resistivity materials, or other suitable metals. In contrast, the body of the SD1 / SD2 conductor may include a material 404 formed from aluminum, copper, silver, gold, zinc, brass, some combination of low-resistivity materials, and other suitable metals with high conductivity. When formed in this way, the SD1 / SD2 conductor may exhibit significantly higher conductivity and lower resistance than the GE1 / GE2 / OGE conductor. For example, a “low” resistance SD1 / SD2 metallic routing structure may exhibit a sheet resistance of approximately 0.05 Ω / □, 0.01–0.05 Ω / □, 0.05–0.1 Ω / □, or less than 0.01 Ω / □. The "high" resistivity GE1 / GE2 / OGE metal structures can exhibit sheet resistances of approximately 0.5 Ω / □, 0.1-0.5 Ω / □, 0.5-1.0 Ω / □, or greater than 1.0 Ω / □. Generally speaking, the resistivity of the GE1 / GE2 / OGE metal structure can be at least 5 times, at least 10 times, or at least 100 times that of the SD1 / SD2 metal structure.

[0049] In conventional displays, scan control signals can be routed across the display surface using scan lines formed of a high-resistivity metal. For example, scan lines feeding the gate terminals of silicon transistors are routed in the GE1 metal layer, and scan lines feeding the gate terminals of semiconductor oxide transistors are routed in the OGE metal layer. Interconnections associated with capacitors are also routed in the GE2 metal layer. Using high-resistivity materials to route scan lines or gate lines in this way is acceptable for devices with smaller displays. However, for devices with large-panel displays operating at high refresh rates (e.g., 120Hz, 60Hz or higher, or refresh rates above 120Hz), the load on the high-resistivity scan lines can be increased such that the resulting rise and fall times of the gate line signals are increased to the point where data can no longer be correctly sampled onto the display pixels.

[0050] According to one embodiment, gate line signals such as scan control signals, emission control signals, reset signals, initialization signals, reference signals, enable signals, power signals (e.g., positive power supply voltage or ground power supply voltage), and / or other row control signals can be routed across the face of the display using a low resistance material such as the SD1 metal routing layer (see, e.g., FIG. 1). Figure 5 ) across the face of the display. Figure 5 is a top plan (layout) view of a pixel 22 showing how gate conductors are coupled to routing lines formed in the SD1 metal routing layer. As shown in Figure 5 , a first row control line coupled to a GE1 metal conductor in the pixel 22, a second row control line coupled to a GE2 metal conductor in the pixel 22, and a third row control line coupled to an OGE metal conductor in the pixel 22 are all routed across the face of the display using the low resistance SD1 routing layer (e.g., the control lines are routed through at least two pixels 22, at least 10 pixels 22, at least 100 pixels, or any suitable number of pixels along a given pixel row). If desired, other row control signals associated with the display pixels 22 can also be routed using the SD1 metal. In the example of Figure 5 , data lines (DL), positive power (VDD) lines, and ground power (VSS) lines can be routed in the column direction using routing lines formed in the SD2 metal routing layer (e.g., the SD2 routing lines can be routed across at least two pixels, at least 10 pixels, at least 100 pixels, or any suitable number of pixels in a pixel column). The SD2 routing lines can be perpendicular to the SD1 routing lines. In general, the terms "row" and "column" can be used interchangeably depending on the orientation of the display. If desired, the SD1 routing lines can also be routed parallel to the SD1 routing lines.

[0051] When configured and operated in this manner, the resistance of the gate lines routed across the display panel will be substantially reduced (e.g., by at least a factor of 5, at least a factor of 10, or more), which can reduce the rise and fall times of the gate line signals so that data signals can be properly loaded into large display panels operating at high refresh rates. By reducing the load on the gate lines, the brightness uniformity of the display can also be improved.

[0052] Examples of Figure 6 where the row control signals are routed using SD1 metal lines and the column control signals are routed using SD2 metal lines are merely exemplary and are not intended to limit the scope of embodiments of the present disclosure. Figure 6 Another suitable arrangement is shown in which the row control signals (e.g., gate lines, scan signals, emission signals, reset signals, initialization signals, etc.) are routed using SD2 metal lines and the column control signals (e.g., data signals, power signals, etc.) are routed using SD1 metal lines. Although SD1 and SD2 are illustrated as being perpendicular to each other, they can also be routed parallel to each other if desired.

[0053] Figure 7 is a top plan (layout) view of a display 14 showing how a plurality of ground power lines can be routed across the face of the display, according to one embodiment. As shown, the display 14 can have a perimeter edge 702, a power circuit 704 formed along the bottom edge of the perimeter (when viewing the display 14 along a direction Z at a face of the display parallel to the XY plane). The power circuit 704 can be configured to provide a ground supply voltage VSS onto a ground line 706 routed along the entire perimeter edge 702 of the display 14. According to one embodiment, additional ground lines such as ground line 708 can be routed across the face of the display 14 in a direction Y perpendicular to the bottom perimeter edge of the display along which the power circuit 704 is formed. For example, the ground line 708 can be formed in every pixel column, in every other pixel column, in every 2-10 pixel columns, or at other suitable intervals. Figure 7

[0054] Configured in this way, the ground line 708 can help provide lower resistance current paths for pixels further away from the edges of the display, such that the pixels experiencing the highest current-resistance (“IR” or voltage) drop at the power terminals are positioned in the center of the display 14, as shown by the dot 710. Without forming the ground line 708 in this way, the point of highest IR drop can undesirably be shifted toward the upper perimeter edge of the display, which would decrease the driving margin of the pixels near the center of the display while increasing overall power consumption.

[0055] Unlike the routing of the VSS lines, the routing of the VDD lines can affect the brightness of the display. For example, if the resistance across the VDD current path is high, the overall brightness of pixel columns having more black pixels can be higher than the brightness of pixel columns having fewer black pixels. To help mitigate this shift in brightness, a plurality of positive supply (VDD) lines can be routed across the face of the display (see, e.g., FIG. 8). As shown, the display 14 can have a perimeter edge 702, a power circuit 704 formed along the bottom edge of the perimeter (when viewing the display 14 along a direction Z at a face of the display parallel to the XY plane). The power circuit 704 can be configured to provide a positive supply voltage VDD onto a power line 806 routed along the perimeter edge 702 of the display 14. Figure 8 Figure 8

[0056] ​​​According to one embodiment, additional power lines, such as positive power lines 808, can be routed across the face of the display 14 in a direction X parallel to a bottom perimeter edge of the display along which the power circuit 704 is formed. For example, VDD lines 808 can be formed in every pixel row, in every other pixel row, in every 2-10 pixel rows, or at other suitable intervals. Configured in this way, the power lines 808 can help provide lower resistance current paths for pixels further from the edges of the display, such that the display brightness will remain the same regardless of the number of darker pixels in each column.

[0057] According to one embodiment, a display is provided, the display comprising: a display driver circuit configured to generate display driver signals; a plurality of pixels formed on a substrate in an active area, each pixel of the plurality of pixels comprising a silicon transistor formed on the substrate, the silicon transistor comprising a gate conductor formed in a first gate metal layer, and the gate conductor of the silicon transistor having a first resistance, and a control line formed over the gate conductor of the silicon transistor, the control line configured to provide the display driver signals generated from the display driver circuit to the gate conductor of the silicon transistor in at least two pixels of the plurality of pixels in the active area, and the control line is formed in a first source-drain layer with a material having a second resistance less than the first resistance.

[0058] According to another embodiment, each pixel of the plurality of pixels comprises a capacitor having a first terminal formed in the first gate metal layer.

[0059] According to another embodiment, the capacitor comprises a second terminal formed in a second gate metal layer over the first gate metal layer.

[0060] According to another embodiment, the display comprises an additional control line routed to the second terminal of the capacitor in the at least two pixels of the plurality of pixels in the active area, the additional control line is formed in the first source-drain layer with the material having the second resistance.

[0061] According to another embodiment, each of the plurality of pixels includes a semiconductor oxide transistor formed over the silicon transistor, the semiconductor oxide transistor including a gate conductor formed in a third gate metal layer, and the gate conductor of the semiconductor oxide transistor has a third electrical resistance that is higher than the second electrical resistance, and an additional control line formed over the gate conductor of the semiconductor oxide transistor, the additional control line configured to provide the display driver signal generated from the display driver circuit to the gate conductor of the semiconductor oxide transistor in the at least two of the plurality of pixels, and the additional control line is formed in the first source-drain layer with the material having the second electrical resistance.

[0062] According to another embodiment, the control line and the additional control line include a gate line configured to carry a scan signal.

[0063] According to another embodiment, the display includes a first planarization layer formed over the silicon transistor, an additional conductive line in a second source-drain layer formed on the first planarization layer, and a second planarization layer formed over the additional routing line.

[0064] According to another embodiment, the additional conductive line is configured to route a data signal to at least two of the plurality of pixels in the active area.

[0065] According to another embodiment, the additional conductive line is configured to route a positive power signal to at least two of the plurality of pixels in the active area.

[0066] According to another embodiment, the additional conductive line is configured to route a ground power signal to at least two of the plurality of pixels in the active area.

[0067] According to another embodiment, the additional conductive line is perpendicular to the control line.

[0068] According to another embodiment, the first electrical resistance is at least five times greater than the second electrical resistance.

[0069] According to another embodiment, the first electrical resistance is at least ten times greater than the second electrical resistance.

[0070] According to another embodiment, the gate conductor of the silicon transistor is formed with molybdenum.

[0071] According to another embodiment, a material in the first source-drain layer is formed with a metal selected from a group consisting of aluminum, copper, silver, and gold.

[0072] According to one embodiment, there is provided a display comprising a perimeter, a plurality of pixels formed in an active area within the perimeter, a power supply circuit formed along an edge of the perimeter, a ground power supply line formed along an entire perimeter of the display, and an additional ground power supply line formed through the plurality of pixels in the active area, the additional ground power supply line configured to ensure that a point of highest voltage drop associated with the ground power supply line is positioned at a center of the display.

[0073] According to another embodiment, the additional ground power supply line is perpendicular to the edge of the perimeter along which the power supply circuit is formed.

[0074] According to another embodiment, each column of the plurality of pixels is coupled to one of the additional ground power supply lines.

[0075] According to one embodiment, there is provided a display comprising a perimeter, a plurality of pixels formed in an active area within the perimeter, a power supply circuit formed along an edge of the perimeter, a positive power supply line formed along an entire perimeter of the display, and an additional positive power supply line formed through the plurality of pixels in the active area, the additional positive power supply line configured to mitigate brightness differences across the display.

[0076] According to another embodiment, the additional positive power supply line is parallel to the edge of the perimeter along which the power supply circuit is formed.

[0077] The foregoing merely illustrates the embodiments and variations can be made thereto without departing from the scope and spirit of the embodiments. The foregoing embodiments can be implemented independently or in any combination.

Claims

1. A display, comprising: Display driver circuitry, the display driver circuitry being configured to generate display driver signals; A plurality of pixels, the plurality of pixels being formed on a substrate in an effective region, wherein each of the plurality of pixels comprises: A silicon transistor formed on the substrate, wherein the silicon transistor includes a gate conductor formed in a first gate metal layer, and wherein the gate conductor of the silicon transistor has a first resistance; and A semiconductor oxide transistor formed above the silicon transistor, wherein the semiconductor oxide transistor includes a gate conductor formed in a third gate metal layer, and wherein the gate conductor of the semiconductor oxide transistor has a second resistance; and A control line is formed above the gate conductor of the silicon transistor and the gate conductor of the semiconductor oxide transistor, wherein the control line is configured to provide a display driver signal generated from the display driver circuit to the gate conductor of the silicon transistor in at least two of the plurality of pixels in the effective region, and wherein the control line is formed in a first source-drain layer using a material having a third resistance less than the first resistance and less than the second resistance.

2. The display according to claim 1, wherein each of the plurality of pixels further comprises: A capacitor having a first terminal formed in the first gate metal layer.

3. The display according to claim 2, wherein the capacitor further comprises: The second terminal is formed in a second gate metal layer above the first gate metal layer.

4. The display according to claim 3, further comprising: An additional control line is routed to the second terminal of the capacitor in at least two of the plurality of pixels in the effective region, wherein the additional control line is formed in the first source-drain layer using the material having the third resistance.

5. The display of claim 3, wherein each of the plurality of pixels further comprises: An additional control line is formed above the gate conductor of the semiconductor oxide transistor, wherein the additional control line is configured to provide a display driver signal generated from the display driver circuit to the gate conductor of the semiconductor oxide transistor in at least two of the plurality of pixels, and wherein the additional control line is formed in the first source-drain layer using the material having the third resistance.

6. The display of claim 5, wherein the control line and the additional control line include gate lines configured to carry scan signals.

7. The display according to claim 1, further comprising: A first planarization layer is formed above the silicon transistor; Additional conductive lines are formed in a second source-drain layer on the first planarization layer; as well as A second planarization layer is formed above the additional conductive line.

8. The display of claim 7, wherein the additional conductive line is configured to route a data signal to at least two of the plurality of pixels in the effective area.

9. The display of claim 8, wherein the additional conductive line is configured to route a positive power signal to at least two of the plurality of pixels in the effective area.

10. The display of claim 7, wherein the additional conductive line is configured to route a ground power signal to at least two of the plurality of pixels in the effective area.

11. The display of claim 7, wherein the additional conductive line is perpendicular to the control line.

12. The display of claim 1, wherein the first resistor is at least five times the third resistor.

13. The display of claim 1, wherein the first resistor is at least ten times the third resistor.

14. The display of claim 1, wherein the gate conductor of the silicon transistor is formed using molybdenum.

15. The display of claim 1, wherein the material in the first source-drain layer is formed using a metal selected from the group consisting of aluminum, copper, silver and gold.

16. The display according to claim 1, further comprising: The perimeter surrounding the effective area; A power supply circuit, the power supply circuit being formed along the edge of the periphery; A grounding power line is formed along the entire periphery of the display; as well as An additional grounding power line is formed through the plurality of pixels in the effective area, wherein the additional grounding power line is configured to ensure that the point of the highest voltage drop associated with the grounding power line is located at the center of the display.

17. The display of claim 16, wherein the additional ground power line is perpendicular to the periphery along the edge that forms the power circuit therein.

18. The display of claim 16, wherein each pixel column of the plurality of pixels is coupled to one of the additional ground power lines.

19. The display according to claim 1, further comprising: The perimeter surrounding the effective area; A power supply circuit, the power supply circuit being formed along the edge of the periphery; A positive power line, which is formed along the entire periphery of the display; as well as An additional positive power line is formed through the plurality of pixels in the effective area, wherein the additional positive power line is configured to mitigate brightness differences on the display.

20. The display of claim 19, wherein the additional positive power line is parallel to the periphery along the edge that forms the power circuit.

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