Semiconductor devices and electrical equipment having the semiconductor devices

Abstract

A novel semiconductor device is provided. The semiconductor device includes a driving circuit and a first transistor layer to a third transistor layer. The first transistor layer includes a first memory cell having a first transistor and a first capacitor. The second transistor layer includes a second memory cell having a second transistor and a second capacitor. The third transistor layer includes a switching circuit and an amplification circuit. The first transistor is electrically connected to a first local bit line. The second transistor is electrically connected to a second local bit line. The switching circuit has the function of selecting whether the first local bit line or the second local bit line is electrically connected to the amplification circuit. The first transistor layer to the third transistor layer are disposed on a silicon substrate. The third transistor layer is disposed between the first transistor layer and the second transistor layer.

Description

Technical Field

[0001] This manual describes semiconductor devices, etc.

[0002] In this specification, a semiconductor device refers to a device that utilizes the properties of semiconductors, and includes circuits containing semiconductor elements (transistors, diodes, photodiodes, etc.) and devices having such circuits. Furthermore, a semiconductor device refers to all devices capable of functioning by utilizing the properties of semiconductors. Examples of semiconductor devices include integrated circuits, chips containing integrated circuits, and electronic components that house chips in packages. Additionally, storage devices, display devices, light-emitting devices, lighting devices, and electronic devices are themselves semiconductor devices, or sometimes include semiconductor devices. Background Technology

[0003] Metal oxides have attracted attention as semiconductors that can be used in transistors. In-Ga-Zn oxides, such as "IGZO", are typical examples of multi-component metal oxides. Through the study of IGZO, CAAC (c-axis aligned crystalline) and nc (nanocrystalline) structures, which are neither single crystals nor amorphous, have been discovered (e.g., Non-Patent Literature 1).

[0004] Transistors containing metal-oxide-semiconductor transistors (hereinafter sometimes referred to as "oxide-semiconductor transistors" or "OS transistors") in the channel formation region are reported to have extremely small off-state currents (e.g., Non-Patent Documents 1, 2). Various semiconductor devices using OS transistors (e.g., Non-Patent Documents 3, 4) have been manufactured.

[0005] The manufacturing process of OS transistors can be incorporated into the existing CMOS process of Si transistors, and OS transistors can be stacked on top of Si transistors. For example, Patent Document 1 discloses a structure in which multiple arrays of memory cells including OS transistors are stacked on a substrate on which Si transistors are disposed.

[0006] [Preliminary Technology Documents]

[0007] [Patent Literature]

[0008] [Patent Document 1] U.S. Patent Application Publication No. 2012 / 0063208

[0009] [Non-patent literature]

[0010] [Non-patent document 1] S.Yamazaki et al., "Properties of crystalline In-Ga-Zn-oxide semiconductor and its transistor characteristics," Jpn.J.Appl.Phys., vol.53, 04ED18 (2014).

[0011] [Non-patent document 2] K. Kato et al., "Evaluation of Off-State Current Characteristics of Transistor Using Oxide Semiconductor Material, Indium-Gallium-Zinc Oxide," Jpn.J.Appl.Phys., vol.51, 021201 (2012).

[0012] [Non-patent document 3] S.Amano et al., "Low Power LC Display Using In-Ga-Zn-Oxide TFTs Based on Variable Frame Frequency," SID Symp.Dig.Papers, vol.41, pp.626-629 (2010).

[0013] [Non-Patent Literature 4] T. Ishizu et al., “Embedded Oxide Semiconductor Memories: AKey Enabler for Low-Power ULSI,” ECS Tran., vol.79, pp.149-156 (2017). Summary of the Invention

[0014] The technical problem that the invention aims to solve

[0015] One objective of this invention is to provide a semiconductor device with a novel structure. Another objective is to provide a semiconductor device with a novel structure that reduces manufacturing costs in semiconductor devices used as memory devices utilizing extremely small off-state currents. Another objective is to provide a semiconductor device with a novel structure that achieves low power consumption in semiconductor devices used as memory devices utilizing extremely small off-state currents. Another objective is to provide a semiconductor device with a novel structure that enables miniaturization in semiconductor devices used as memory devices utilizing extremely small off-state currents. Finally, an objective is to provide a semiconductor device with a novel structure that exhibits small variations in the electrical characteristics of transistors and excellent reliability in semiconductor devices used as memory devices utilizing extremely small off-state currents.

[0016] The description of multiple objectives does not preclude the existence of mutually exclusive objectives. One aspect of the invention does not need to achieve all of the exemplified objectives. Furthermore, objectives other than those listed above are naturally apparent from the description in this specification, etc., and such objectives may become objectives of one aspect of the invention.

[0017] means of solving technical problems

[0018] One aspect of the present invention is a semiconductor device comprising: a driving circuit having a plurality of transistors using a silicon substrate as a channel; and a first transistor layer to a third transistor layer having a plurality of transistors using a metal oxide as a channel, wherein the first transistor layer includes a first memory cell having a first transistor and a first capacitor, the second transistor layer includes a second memory cell having a second transistor and a second capacitor, the third transistor layer includes a switching circuit and an amplification circuit, the first transistor is electrically connected to a first local bit line, the second transistor is electrically connected to a second local bit line, the switching circuit has the function of selecting the first local bit line or the second local bit line and being electrically connected to the amplification circuit, the first transistor layer to the third transistor layer are disposed on the silicon substrate, and the third transistor layer is disposed between the first transistor layer and the second transistor layer.

[0019] In one aspect of the semiconductor device of the present invention, the first local bit line and the second local bit line are preferably disposed in a direction perpendicular or substantially perpendicular to the surface of the silicon substrate.

[0020] In one aspect of the semiconductor device of the present invention, it is preferred to include a global bit line that has the function of electrically connecting an amplifier circuit and a driver circuit.

[0021] In one aspect of the semiconductor device of the present invention, the global bit lines are preferably disposed in a direction perpendicular or substantially perpendicular to the surface of the silicon substrate.

[0022] In one aspect of the semiconductor device of the present invention, the metal oxide preferably comprises In, Ga and Zn.

[0023] One aspect of the present invention is a semiconductor device comprising: a driving circuit having a plurality of transistors using a silicon substrate as a channel; and a component layer having a plurality of transistor layers stacked on top of each other, wherein the component layer includes a first transistor layer to a third transistor layer having a plurality of transistors using a metal oxide as a channel, the first transistor layer including a first memory cell having a first transistor and a first capacitor, the second transistor layer including a second memory cell having a second transistor and a second capacitor, the third transistor layer including a switching circuit and an amplification circuit, the first transistor being electrically connected to a first local bit line, the second transistor being electrically connected to a second local bit line, the switching circuit having the function of selecting either the first local bit line or the second local bit line and being electrically connected to the amplification circuit, the component layer being stacked on a silicon substrate, and the third transistor layer being disposed between the first transistor layer and the second transistor layer.

[0024] In one aspect of the semiconductor device of the present invention, the first local bit line and the second local bit line are preferably disposed in a direction perpendicular or substantially perpendicular to the surface of the silicon substrate.

[0025] In one aspect of the semiconductor device of the present invention, it is preferred to include a global bit line that has the function of electrically connecting an amplifier circuit and a driver circuit.

[0026] In one aspect of the semiconductor device of the present invention, the global bit lines are preferably disposed in a direction perpendicular or substantially perpendicular to the surface of the silicon substrate.

[0027] In one aspect of the semiconductor device of the present invention, the metal oxide preferably comprises In, Ga and Zn.

[0028] One aspect of the present invention is an electronic device comprising at least one of the semiconductor device described above, an antenna, a battery, an operating switch, a microphone, and a speaker.

[0029] Note that other aspects of the present invention are described in the following description and accompanying drawings of the embodiments.

[0030] Invention Effects

[0031] One aspect of the present invention can provide a semiconductor device with a novel structure. Another aspect of the present invention can provide a semiconductor device with a novel structure that reduces manufacturing costs in a semiconductor device used as a memory device utilizing extremely small off-state currents. Another aspect of the present invention can provide a semiconductor device with a novel structure that achieves low power consumption in a semiconductor device used as a memory device utilizing extremely small off-state currents. Another aspect of the present invention can provide a semiconductor device with a novel structure that enables miniaturization of the device in a semiconductor device used as a memory device utilizing extremely small off-state currents. Finally, another aspect of the present invention can provide a semiconductor device with a novel structure that exhibits small variations in the electrical characteristics of transistors and excellent reliability in a semiconductor device used as a memory device utilizing extremely small off-state currents.

[0032] The description of multiple effects does not preclude the existence of each other's effects. Furthermore, one aspect of the invention does not necessarily require all of the aforementioned effects. In one aspect of the invention, objectives, effects, and novel features beyond the foregoing can be readily understood from the description and drawings herein.

[0033] Brief description of the attached figures

[0034] Figure 1 This is a block diagram illustrating an example of the structure of a semiconductor device.

[0035] Figure 2A This is a block diagram illustrating an example of the structure of a semiconductor device. Figure 2B This is a circuit diagram illustrating an example of the structure of a semiconductor device.

[0036] Figure 3A , Figure 3B This is a circuit diagram illustrating an example of the structure of a semiconductor device.

[0037] Figure 4A , Figure 4B This is a schematic diagram illustrating an example of the structure of a semiconductor device.

[0038] Figure 5 This is a schematic diagram illustrating an example of the structure of a semiconductor device.

[0039] Figure 6 This is a circuit diagram illustrating an example of the structure of a semiconductor device.

[0040] Figure 7A , Figure 7B , Figure 7C This is a circuit diagram illustrating an example of the structure of a semiconductor device.

[0041] Figure 8A , Figure 8B This is a circuit diagram illustrating an example of the structure of a semiconductor device.

[0042] Figure 9A This is a block diagram illustrating an example of the structure of a semiconductor device. Figure 9B This is a circuit diagram illustrating an example of the structure of a semiconductor device.

[0043] Figure 10A , Figure 10B This is a block diagram illustrating an example of the structure of a semiconductor device.

[0044] Figure 11 This is a circuit diagram illustrating an example of the structure of a semiconductor device.

[0045] Figure 12 This is a timing diagram illustrating an example of the structure of a semiconductor device.

[0046] Figure 13 This is a cross-sectional schematic diagram showing an example of the structure of a semiconductor device.

[0047] Figure 14A , Figure 14B This is a cross-sectional schematic diagram showing an example of the structure of a semiconductor device.

[0048] Figure 15A , Figure 15B , Figure 15C This is a cross-sectional schematic diagram showing an example of the structure of a semiconductor device.

[0049] Figure 16 This is a cross-sectional schematic diagram showing an example of the structure of a semiconductor device.

[0050] Figure 17 This is a cross-sectional schematic diagram showing an example of the structure of a semiconductor device.

[0051] Figure 18A This is a top view showing an example of the structure of a semiconductor device. Figure 18B , Figure 18C This is a cross-sectional schematic diagram showing an example of the structure of a semiconductor device.

[0052] Figure 19A , Figure 19B , Figure 19C , Figure 19D This is a top view showing an example of the structure of a semiconductor device.

[0053] Figure 20A A diagram illustrating the classification of IGZO crystal structures. Figure 20B The diagram illustrates the XRD pattern of quartz glass. Figure 20C This shows the XRD pattern of crystalline IGZO.

[0054] Figure 21 This is a block diagram illustrating an example of the structure of a semiconductor device.

[0055] Figure 22 This is a schematic diagram illustrating an example of the structure of a semiconductor device.

[0056] Figure 23A , Figure 23B This is a schematic diagram illustrating an example of an electronic component.

[0057] Figure 24 This is a diagram showing an example of an electronic device.

[0058] Methods of implementing the invention

[0059] The embodiments will now be described with reference to the accompanying drawings. Note that one aspect of the present invention is not limited to the following description; those skilled in the art will readily understand that the embodiments can be implemented in many different forms, and their manner and details can be varied in various ways without departing from the spirit and scope of the present invention. Therefore, one aspect of the present invention should not be construed as being limited only to the contents described in the embodiments shown below.

[0060] Note that in this specification, ordinal numbers such as "first," "second," and "third" are added to avoid confusion regarding the constituent elements. Therefore, these ordinal numbers do not limit the number of constituent elements. Furthermore, these ordinal numbers do not limit the order of the constituent elements. Additionally, for example, in this specification, a constituent element referred to by "first" in one embodiment may be designated as a constituent element referred to by "second" in other embodiments or within the scope of the claims. Furthermore, for example, in this specification, a constituent element referred to by "first" in one embodiment may be omitted in other embodiments or within the scope of the claims.

[0061] In the accompanying drawings, the same symbol is sometimes used to represent the same element or elements with the same function, elements of the same material or elements formed at the same time, and sometimes repeated descriptions are omitted.

[0062] In this specification, the power supply potential VDD is sometimes simply referred to as potential VDD, VDD, etc. The same applies to other components (e.g., signals, voltages, circuits, components, electrodes, and wiring).

[0063] In addition, when multiple elements use the same symbol and it is necessary to distinguish them, symbols such as “_1”, “_2”, “[n]”, “[m,n]” are sometimes added to the symbol for identification. For example, the second wiring GL is represented as wiring GL[2].

[0064] (Implementation Method 1)

[0065] Reference Figures 1 to 12 An example of the structure of a semiconductor device as one embodiment of the present invention will be described.

[0066] Note that a semiconductor device is a device that utilizes the properties of semiconductors, and also includes a circuit containing semiconductor elements (transistors, diodes, photodiodes, etc.) or a device including such a circuit. The semiconductor device described in this embodiment can be used as a memory device utilizing transistors with extremely low off-state current.

[0067] Figure 1 A block diagram illustrating the cross-sectional structure of the semiconductor device 10 is shown.

[0068] The semiconductor device 10 includes multiple element layers 50_1 to 50_M (M is a natural number) on a silicon substrate 60. Each element layer 50_1 to 50_M includes a transistor layer 20, a transistor layer 30, and a transistor layer 40. Transistor layer 30 is composed of multiple transistor layers 31_1 to 31_k (k is a natural number greater than 2). Transistor layer 40 is composed of multiple transistor layers 32_1 to 32_k.

[0069] exist Figure 1 The block diagram shown illustrates the z-axis direction as defined for the configuration of each structure. The z-axis direction refers to the direction perpendicular to or approximately perpendicular to the surface of the silicon substrate 60. Note that "approximately perpendicular" means an angle of 85° or more but less than 95°. For ease of understanding, the z-axis direction is sometimes referred to as the vertical direction. The surface of the silicon substrate 60 corresponds to the surface formed by the x-axis and y-axis, which are defined as perpendicular to or approximately perpendicular to the z-axis direction. For ease of understanding, the x-axis direction is sometimes referred to as the depth direction, and the y-axis direction is sometimes referred to as the horizontal direction.

[0070] Each transistor layer in transistor layer 30, which consists of multiple transistor layers 31_1 to 31_k, includes multiple memory cells (not shown). Each memory cell includes a transistor and a capacitor. Note that a capacitor is sometimes referred to as a capacitor element. Additionally, a component layer refers to a layer in which components such as capacitors or transistors are disposed, and also includes layers containing components such as conductors, semiconductors, and insulators.

[0071] Similarly, each transistor layer in transistor layer 40, which consists of multiple transistor layers 32_1 to 32_k, includes multiple memory cells. Each memory cell includes a transistor and a capacitor.

[0072] Note that the memory cells included in each transistor layer 31_1 to 31_k and 32_1 to 32_k can also be referred to as DOSRAM (Dynamic Oxide Semiconductor Random Access Memory) in which an oxide semiconductor transistor (hereinafter referred to as an OS transistor) is contained in the channel forming region. Because this memory cell can be composed of a transistor and a capacitor, high-density memory can be achieved. In addition, by using OS transistors, the data retention period can be extended.

[0073] By using a memory cell including an OS transistor in one embodiment of the invention, the leakage current flowing between the source and drain (hereinafter referred to as the off-state current) is minimal when the cell is off. This characteristic can be utilized to retain the charge corresponding to the desired voltage in a capacitor connected to the other of the source and drain terminals. In other words, written data can be retained in the memory cell for an extended period. Therefore, the frequency of data refresh can be reduced, resulting in lower power consumption.

[0074] Furthermore, in memory cells using OS transistors, data can be rewritten and read through charging or discharging, thus enabling virtually unlimited data writing and reading. Because OS transistor-based memory cells do not involve atomic-level structural changes like those in magnetic or resistive random access memory, they exhibit excellent write resistance. Additionally, unlike flash memory, OS transistor-based memory cells do not suffer from instability due to the increase in electron trapping centers even with repeated rewriting.

[0075] Furthermore, memory cells using OS transistors can be freely configured on silicon substrates containing silicon transistors (hereinafter referred to as Si transistors) with channel formation regions, thus facilitating integration. Additionally, OS transistors can be manufactured using the same fabrication equipment as Si transistors, allowing for low-cost manufacturing.

[0076] Furthermore, when an OS transistor has a back gate electrode in addition to the gate, source, and drain electrodes, it can become a 4-terminal semiconductor device. An OS transistor can be configured as a circuit network where the input and output of the signal flowing between the source and drain can be independently controlled based on the voltage applied to the gate or back gate electrode. Therefore, circuit design can be performed in the same way as an LSI. In addition, OS transistors have superior electrical characteristics compared to Si transistors at high temperatures. Specifically, even at temperatures above 125°C and below 150°C, the ratio of on-state current to off-state current is high, thus enabling good switching operation.

[0077] Transistor layer 20 has the function of writing and reading data from one of the multiple memory cells included in transistor layer 30 and transistor layer 40.

[0078] Transistor layer 20 includes multiple switching circuits and amplifier circuits. The switching circuits have the function of selecting a local bit line connected to one of multiple memory cells. By employing this structure, the small potential difference of the local bit line can be amplified during readout and output to the global bit line (GBL), further amplifying the readout data using a sense amplifier disposed on the silicon substrate. The amplifier circuits have the function of amplifying the signal from the local bit line to the global bit line (GBL) for input.

[0079] Note that local bit lines are bit lines directly connected to memory cells. Global bit lines (GBLs) are bit lines selected from multiple local bit lines that are electrically connected to memory cells. Data signals supplied to global or local bit lines are equivalent to signals written to or read from memory cells. The data signal is explained as a binary signal with a potential corresponding to a high or low level for data 1 or data 0. Alternatively, the data signal can also be multi-valued (three or more values). Note that in the accompanying drawings, thick lines or thick dashed lines are sometimes used to indicate global bit lines (GBLs) for improved visibility.

[0080] like Figure 1 As shown, transistor layer 20 is disposed between transistor layers 30 and 40 in the z-axis direction. Each transistor layer 20, including element layers 50_1 to 50_M, has the function of outputting a data signal selected by the switching circuit and amplified by the amplification circuit to the driving circuit included in the silicon substrate 60 via the global bit line GBL. Furthermore, transistor layer 20 has the function of supplying the data signal output by the driving circuit included in the silicon substrate 60 to the local bit line selected by the switching circuit.

[0081] The silicon substrate 60 includes drive circuitry for writing or reading data from selected memory cells in the transistor layer 20 via global bit lines (GBLs) and local bit lines. The drive circuitry includes a plurality of Si transistors that use the silicon substrate 60 as a channel.

[0082] In one aspect of the present invention, OS transistors with extremely low off-state current are used as transistors disposed in each element layer. Therefore, the refresh frequency of data held in the memory cell can be reduced, enabling a low-power semiconductor device. OS transistors can be stacked and manufactured by repeatedly using the same manufacturing process in the vertical direction, thus reducing manufacturing costs. Furthermore, in another aspect of the present invention, the transistors constituting the memory cell can be arranged vertically rather than planarly to increase storage density, thereby enabling device miniaturization. Additionally, OS transistors exhibit less variation in electrical characteristics even at high temperatures than Si transistors, thus enabling a semiconductor device with minimal variation in the electrical characteristics of stacked and integrated transistors, and suitable for use as a reliable memory device.

[0083] then, Figure 2A Showing equivalent to Figure 1 A block diagram of any one of the component layers 50_1 to 50_M.

[0084] like Figure 1 As shown, in one embodiment of the present invention, the element layer 50 is a layer located above and below the transistor layer 20 in the z-axis direction, and a structure is provided for multiple transistor layers 30, 40 including memory cells. By adopting this structure, the distance between the transistor layer 20 and the transistor layer 30 or transistor layer 40 can be shortened. When the local line is shortened, parasitic capacitance can be reduced. By repeatedly manufacturing multiple transistor layers 30, 40 in the vertical direction using the same manufacturing process, manufacturing costs can be reduced.

[0085] Figure 2B It is shown using circuit symbols. Figure 2A A diagram of the various structures in element layer 50 is shown.

[0086] Transistor layer 20 includes a switching circuit 21 and an amplifier circuit 22. Transistor layers 31_1, 31_2, 32_1, and 32_2 each include a plurality of memory cells 33. Memory cells 33 include transistors 34 and capacitors 35. Transistors 34 are used as switches to switch between on and off states according to a word line WL connected to the gate. Local bit lines LBL_A1 and LBL_A2 correspond to local bit lines connected to memory cells 33 located in the lower layer of switching circuit 21. Local bit lines LBL_B1 and LBL_B2 correspond to local bit lines connected to memory cells 33 located in the upper layer of switching circuit 21.

[0087] like Figure 2BAs shown, local bit lines LBL_A1, LBL_A2, LBL_B1, and LBL_B2 are connected to one of the source and drain terminals of the transistor 34 included in each memory cell. Capacitor 35 is connected to the other of the source and drain terminals of the transistor 34.

[0088] Transistor 34 is the aforementioned OS transistor. Capacitor 35 has a structure in which an insulator is sandwiched between conductors used as electrodes. Note that, in addition to metals, conductive semiconductor layers or the like can also be used as conductors constituting electrodes. Furthermore, capacitor 35 can be positioned above or below transistor 34, or a portion of the semiconductor layer or electrodes constituting transistor 34 can be used as an electrode of capacitor 35, as will be explained in detail later.

[0089] The switching circuit 21 has the function of supplying the potential of a local bit line to the amplifier circuit 22 based on a signal that selects any one of the local bit lines LBL_A1, LBL_A2, LBL_B1, and LBL_B2. The switching circuit 21 includes circuitry that functions as a multiplexer.

[0090] Amplifier circuit 22 has the function of amplifying the potential of the local bit line selected by switching circuit 21 and outputting it to the global bit line GBL. Alternatively, it has the function of transferring the potential of the global bit line GBL to the local bit line selected by switching circuit 21. Amplifier circuit 22 has the function of a readout circuit that can amplify the potential of the local bit line and output it to the global bit line GBL based on the readout signal of the control data signal. Furthermore, amplifier circuit 22 has the function of a write circuit that can transfer the potential of the global bit line GBL to the local bit line selected by switching circuit 21 based on the write signal of the control data signal.

[0091] The transistors comprising the switching circuit 21 and the amplification circuit 22 in transistor layer 20 are preferably composed of OS transistors, similar to transistor 34. Since transistor layers 20, 30, and 40 of the constituent element layer 50 using OS transistors can be stacked on a silicon substrate including Si transistors, they can be easily integrated.

[0092] Figure 2B The diagram shows the structure of local bit lines LBL_A1, LBL_A2, LBL_B1, and LBL_B2 of the memory cells connected to the upper and lower sides of the transistor layer 20 in the switching circuit 21, but other structures may also be used.

[0093] Figure 3A , Figure 3B Showing with Figure 2BThe local bit lines LBL_A1, LBL_A2, LBL_B1, and LBL_B2 are connected in different structures as described in the document.

[0094] Alternatively, a structure can be adopted in which the switching circuit is configured in each local bit line pair on the layers above and below the transistor layer that includes the switching circuit. For example, as Figure 3A As shown, the following structure can also be adopted: local bit lines LBL_A1 and LBL_B1 are switched by switching circuit 21_A, and the output is sent to the global bit line GBL through amplifier circuit 22_A and switch 27A; local bit lines LBL_A2 and LBL_B2 are switched by switching circuit 21_B, and the output is sent to the global bit line GBL through amplifier circuit 22_B and switch 27B. Alternatively, switches 27A and 27B can be constructed using the OS transistors described above.

[0095] Alternatively, a structure can be adopted in which the switching circuit is set on each local bit line on a layer above or below the transistor layer that includes the switching circuit. For example, as Figure 3B As shown, the following structure can also be adopted: local bit lines LBL_A1 and LBL_A2 are switched by switching circuit 21_A, and the output is sent to the global bit line GBL through amplifier circuit 22_A and switch 27C; local bit lines LBL_B1 and LBL_B2 are switched by switching circuit 21_B, and the output is sent to the global bit line GBL through amplifier circuit 22_B and switch 27D. Alternatively, switches 27C and 27D can be constructed using the OS transistors described above.

[0096] Figure 4A Showing will Figure 1 The diagram shows a perspective view of a semiconductor device 10 with element layers 50_1 to 50_M disposed on a silicon substrate 60. Figure 4A The diagram shows the vertical direction (z-axis direction), the depth direction (x-axis direction), and the horizontal direction (y-axis direction).

[0097] exist Figure 4A In the diagram, dashed lines represent the memory cells 33 included in transistor layers 31_1, 31_2, 32_1, and 32_2. Additionally, dashed lines represent the switching circuit 21 and the amplifier circuit 22 included in transistor layer 20.

[0098] like Figure 4AAs shown, a semiconductor device 10 according to one aspect of the present invention has transistor layers 20, 30, and 40, including OS transistors, stacked in a manner. Therefore, the semiconductor device 10 can be manufactured repeatedly in the vertical direction using the same manufacturing process, thereby reducing manufacturing costs. Furthermore, in the semiconductor device 10 according to one aspect of the present invention, storage density can be increased by stacking the transistor layers 30 and 40, including memory cells 33, in a vertical direction rather than a planar direction, thereby enabling device miniaturization.

[0099] also, Figure 4B Omitted Figure 4A The structures included in the element layers 50_1 to 50_M are shown, and the circuits disposed on the silicon substrate 60 are shown. Figure 4B The control logic circuit 61, row drive circuit 62, column drive circuit 63, and output circuit 64, which are composed of Si transistors in a silicon substrate 60, are shown. Embodiment 4 describes the control logic circuit 61, row drive circuit 62, column drive circuit 63, and output circuit 64 in detail.

[0100] also, Figure 5 draw out Figure 4A The transistor layers 20, 31_1, 31_2, 32_1, and 32_2 of the semiconductor device 10 are shown in the figure. Figure 5 The switching circuit 21 and the amplifier circuit 22 in transistor layer 20 are shown. Furthermore, Figure 5 The diagram shows the transistor 34, capacitor 35, local bit line LBL, and word line WL included in the memory cells of transistor layers 31_1, 31_2, 32_1, and 32_2. Figure 5 In the text, for clarity, the local bit line LBL is represented by a dashed line. Furthermore, in... Figure 5 In the diagram, the global bit line (GBL) is illustrated along the z-axis, passing through each transistor layer. As mentioned above, for clarity, the global bit line (GBL) is represented by a line thicker than the other lines.

[0101] like Figure 5 As shown, in the semiconductor device 10, the local bit line LBL connected to the transistor 34 included in the memory cell, the amplifier circuit 22 connected to the transistor layer 20, and the global bit line GBL connected to the silicon substrate 60 are arranged in the z-axis direction, that is, in the direction perpendicular to the silicon substrate 60. By adopting this structure, the local bit line LBL between each memory cell and the switching circuit can be shortened. Therefore, the parasitic capacitance of the local bit line LBL can be significantly reduced, so that the potential can be read even if the data signal held by the memory cell is multi-valued. In addition, in one aspect of the present invention, the data held by the memory cell can be read as a current, so that the data can be easily read even if multi-valued.

[0102] Figure 6 This is a diagram illustrating an example of a circuit structure for the switching circuit 21 and the amplifier circuit 22 included in the transistor layer 20. Figure 6 Showing options for selection Figure 2B The transistors 21_1 to 21_4 of any one of the local bit lines LBL_A1, LBL_A2, LBL_B1, and LBL_B2 described herein are used as multiplexers or demultiplexers, and the transistors 22_1 to 22_3 constitute the amplifier circuit 22.

[0103] Transistor 21_1 controls the conduction state between local bit line LBL_A1 and the gate of transistor 22_1. The gate of transistor 21_1 is supplied with the signal SEL1, which controls the conduction state of transistor 21_1. Transistors 21_2 to 21_4 similarly control the conduction state between local bit lines LBL_A2, LBL_B1, or LBL_B2 and the gate of transistor 22_1. The gates of transistors 21_2 to 21_4 are supplied with signals SEL2 to SEL4.

[0104] Transistors 22_1 and 22_3 are transistors that constitute a readout circuit for data signals held in memory cell 33. The gate of transistor 22_1 is connected to one of the sources and drains of transistors 21_1 to 21_4. The source of transistor 22_1 is connected to a wiring SL with a constant potential applied. The drain of transistor 22_1 is connected to the source of transistor 22_3. The drain of transistor 22_3 is connected to the global bit line GBL. The potential of the gate of transistor 22_1 is amplified by transistor 22_1, and readout is performed to the global bit line GBL according to the control of the signal RE supplied to the gate of transistor 22_3.

[0105] Transistor 22_2 is a transistor that constitutes the write circuit for the data signal held in memory cell 33. One of the source and drain of transistor 22_2 is connected to one of the source and drain of transistors 21_1 to 21_4. The other of the source and drain of transistor 22_2 is connected to the global bit line GBL. Transistor 22_2 can write the potential of the global bit line GBL into memory cell 33 according to the control of the gate-supplied signal WE and the signal supplied to the word line WL.

[0106] Figures 7A to 7C Explanation shown Figure 6 The circuit diagram shows a modified example of the switching circuit 21 and the amplifier circuit 22.

[0107] Figure 7A It is shown Figure 6 The circuit diagram illustrates the structure of the switching circuit 21 and the amplifier circuit 22. (See diagram for example.) Figure 7AAs shown, transistors 21_1 to 21_4 constituting switching circuit 21 select any one of the local bit lines LBL_A1, LBL_A2, LBL_B1, and LBL_B2, controlling the conduction state between them and the gate of transistor 22_1. Furthermore, transistors 21_1 to 21_4 constituting switching circuit 21 control the supply of the potential of the global bit line GBL to any one of the local bit lines LBL_A1, LBL_A2, LBL_B1, and LBL_B2 through transistor 22_2. Amplifier circuit 22 controls the conversion of the potential of the gate of transistor 22_1 into current and transmits it to the global bit line GBL.

[0108] Figure 7B It is equivalent to changing Figure 7A The circuit diagram shows the connection of one terminal between the source and drain of transistor 22_2. Furthermore, Figure 7C It is equivalent to Figure 7A The transistor 22_3 is changed to a circuit diagram with the wiring SL side connected. Thus, the switching circuit 21 and the amplifier circuit 22 of one embodiment of the present invention can have various circuit structures.

[0109] in addition, Figures 7A to 7C The transistors shown are either top-gate or bottom-gate structures without a back gate electrode, but the transistor structure is not limited to these. For example, as... Figure 8A As shown, transistors 23_1 to 23_4, 24_1 to 24_3, which include a back gate electrode connected to the back gate electrode line BGL, can also be used. By employing... Figure 8A The structure makes it easier to control the threshold voltage and other electrical characteristics of transistors 23_1 to 23_4 and 24_1 to 24_3 from the outside.

[0110] Or, such as Figure 8B As shown, transistors 25_1 to 25_4, 26_1 to 26_3, which include a back gate electrode connected to the gate electrode, can also be used. By employing... Figure 8B The structure can increase the amount of current flowing through transistors 25_1 to 25_4 and 26_1 to 26_3.

[0111] Explanation Figure 1 The semiconductor device 10 may include one type of memory cell, but it may also include two or more types of memory cells. Figure 9A A block diagram of a semiconductor device 10A, which is a modified example of semiconductor device 10, is shown.

[0112] The difference between semiconductor device 10A and semiconductor device 10 is that transistor layers 41A and 41B, which contain memory cells with different circuit structures, are provided between transistor layers 20 and 30 and between transistor layers 20 and 40.

[0113] Figure 9B This is a circuit diagram illustrating an example structure of the memory cell included in transistor layers 41A and 41B. Memory cell 41 includes transistor 42, transistor 43, and capacitor 44.

[0114] One of the source and drain of transistor 42 is connected to the gate of transistor 43. The gate of transistor 43 is connected to one electrode of capacitor 44. The other of the source and drain of transistor 42, and one of the source and drain of transistor 42, are connected to wiring BL2. The other of the source and drain of transistor 43 is connected to wiring SL2. The other electrode of capacitor 44 is electrically connected to wiring CAL. Here, the node where one of the source and drain of transistor 42, the gate of transistor 43, and one electrode of capacitor 44 are connected to each other is called node N.

[0115] The wiring CAL is used as wiring to apply a specified potential to the other electrode of capacitor 44. The potential of the wiring CAL when reading data from memory cell 41 is different from the potential of the wiring CAL when writing data to memory cell 41 and when retaining data in memory cell 41. Therefore, the threshold voltage on the appearance of transistor 43 when reading data from memory cell 41 is different from the threshold voltage on the appearance of transistor 43 when writing data to memory cell 41 and when retaining data in memory cell 41.

[0116] In storage unit 41, Figure 9B In the structure shown, when writing data to memory cell 41 and when retaining data in memory cell 41, current does not flow between wiring SL2 and wiring BL2, regardless of the data written to memory cell 41. On the other hand, when reading data from memory cell 41, current corresponding to the data retained in memory cell 41 flows between wiring SL2 and wiring BL2.

[0117] Transistors 42 and 43 are preferably OS transistors. As described above, the off-state current of an OS transistor is extremely small. Therefore, the charge corresponding to the data written to memory cell 41 can be maintained in node N for a long time. In other words, the written data can be retained in memory cell 41 for a long time. Therefore, the frequency of data refresh can be reduced, thereby reducing the power consumption of the semiconductor device according to one aspect of the present invention.

[0118] Figure 9BThe storage cell 41 shown can be referred to as a NOSRAM (Nonvolatile Oxide Semiconductor RAM) that uses OS transistors for memory. NOSRAM has the characteristic of being able to be read non-destructively. On the other hand, when reading the data held in the aforementioned DOSRAM, a destructive read is performed.

[0119] Semiconductor device 10A can write frequently read data from DOSRAM to NOSRAM by including memory cell 41. As described above, NOSRAM can be read non-destructively, thus reducing the frequency of data refresh. Therefore, the power consumption of the semiconductor device according to one aspect of the present invention can be reduced.

[0120] Figure 10A , Figure 10B Explanation shown Figure 1 A circuit diagram of a modified example of the semiconductor device 10 shown.

[0121] Figure 10A Shown in Figure 1 Semiconductor device 10B, in which the transistor layer 40 is omitted from the element layers 50_1 to 50_M of the semiconductor device 10 shown. Figure 10A The semiconductor device 10B shown includes a transistor layer 30 with transistors 31_1 to 31_k in the lower layer of the transistor layer 20, which includes switching circuits and amplification circuits. In this structure, operation controlled by the memory cells of the switching circuits and amplification circuits can also be realized.

[0122] Figure 10B Shown in Figure 1 Semiconductor device 10C, in which the transistor layer 30 is omitted from the element layers 50_1 to 50_M of the semiconductor device 10 shown. Figure 10B The semiconductor device 10C shown includes a transistor layer 40 with transistor layers 32_1 to 32_k above the transistor layer 20, which includes switching and amplification circuits. This structure also allows operation controlled by the memory cells of the switching and amplification circuits.

[0123] Figure 11 As shown, Figure 6 , Figure 7A Apart from the storage cell 33, the OS transistors 21_1 to 21_4 and 22_1 to 22_3 constituting the switching circuit and the amplification circuit, the pre-charge circuit 62_A, the pre-charge circuit 62_B, the readout amplifier 62_C, the switching circuit 62_D, the switching circuit 62_E and the write readout circuit 69, which are composed of Si transistors on the silicon substrate 60, are described.

[0124] In addition, such as Figure 11 As shown, transistors 22_2 and 22_3 included in transistor layer 20 are connected to global bit lines GBL_A and GBL_B. Global bit lines GBL_A and GBL_B, like local bit lines LBL_A1, LBL_A2, LBL_B1, and LBL_B2, are disposed in a direction perpendicular to the surface of silicon substrate 60 and connected to Si transistors.

[0125] The precharge circuit 62_A is composed of n-channel transistors 65_1 to 65_3. The precharge circuit 62_A is used to precharge the global bit line GBL_A, the global bit line GBL_B, and the selected local bit line to an intermediate potential VPC, which is equivalent to the potential VDD / 2 between VDD and VSS, according to the precharge signal and the signal WE supplied to the precharge line PCL1.

[0126] The precharge circuit 62_B is composed of n-channel transistors 65_4 to 65_6. The precharge circuit 62_B is used to precharge the global bit line GBL_A, the global bit line GBL_B, and the selected local bit line to an intermediate potential VPC, which is equivalent to the potential VDD / 2 between VDD and VSS, according to the precharge signal and the signal WE supplied to the precharge line PCL2.

[0127] The readout amplifier 62_C is composed of p-channel transistors 67_1 and 67_2 and n-channel transistors 67_3 and 67_4 connected to wiring VHH or wiring VLL. Wiring VHH or wiring VLL is a wiring that supplies VDD or VSS. Transistors 67_1 to 67_4 are transistors that form an inverter loop. The potential change of the selected local bit line LBL is determined by setting the word line WL to a high level, and the current flowing through transistor 22_1 changes accordingly. Global bit lines GBL_A and GBL_B become either high supply potential VDD or low supply potential VSS based on the current flowing through transistor 22_1. The potentials of global bit lines GBL_A and GBL_B can be output to the outside via the write-read circuit 69 through switching circuits 62_D and 62_E. The write-read circuit 69 is controlled by the signal EN_data to write data signals.

[0128] Switching circuit 62_D controls the conduction state between the sense amplifier 62_C and global bit lines GBL_A and GBL_B. Switching circuit 62_D can be switched on or off by controlling the switching signal CSEL1. When switches 66_A and 66_B are n-channel transistors, they are on when the switching signal CSEL1 is high and off when it is low. Switching circuit 62_E controls the conduction state between the write-read circuit 69 and the bit line pair connected to the sense amplifier 62_C. Switching circuit 62_E can be switched on or off by controlling the switching signal CSEL2. The structure of switches 68_C and 68_D can be the same as that of switches 66_A and 66_B.

[0129] also, Figure 12 Explanation shown Figure 11 The circuit diagram shown is a timing diagram of its operation. Figure 12 In the timing diagram shown, period T11 corresponds to the write operation period, period T12 corresponds to the pre-charge operation period of bit line BL, period T13 corresponds to the pre-charge operation period of global bit line GBL, period T14 corresponds to the charge sharing operation period, period T15 corresponds to the read standby operation period, and period T16 corresponds to the read operation period. In the operation description, the local bit line connected to the memory cell to which data is to be written is called the local bit line LBL, and the signal supplied to the gate of the transistor connected to the local bit line LBL is called the signal SEL. The signal SEL is equivalent to any one of the signals SEL_1 to SEL_4 that control the local bit line connected to the selected memory cell and the gate of transistor 22_1 to be in the on state.

[0130] During period T11, the word line WL connected to the gate of the transistor included in the memory cell to which the data signal is to be written is made high. During period T11, the signals SEL, WE, and EN_data are made high, and the data signal is written to the memory cell via the global bit line GBL and the bit line BL.

[0131] During period T12, in order to precharge the local bit line LBL, the precharge line PCL1 is made high while signals SEL and WE are high. The local bit line LBL is precharged to the precharge potential. During period T12, it is preferable to make the wiring VHH and wiring VLL supplying the power supply voltage to the sense amplifier 62_C both VDD / 2 to suppress power consumption caused by the through current.

[0132] During period T13, to precharge the global bit line GBL, the precharge line PCL2 is set to a high level. The global bit line GBL is then precharged to the precharge potential. During period T13, by setting both routing VHH and routing VLL to VDD, the heavily loaded global bit line GBL can be precharged for a short time.

[0133] During period T14, in order to perform charge sharing to balance the charge held in memory cell 33 and the pre-charged charge on local bit line LBL, word line WL and signal SEL are set to high level. Local bit line LBL and the gate of transistor 22_1 are made at the same potential. During period T14, it is preferable to make wiring VHH and wiring VLL, which supply power to the sense amplifier 62_C, both VDD / 2 to suppress power consumption caused by through current.

[0134] During period T15, word line WL and signal RE are set high. Current flows through transistor 22_1 based on the gate potential of transistor 22_1, and the potential of global bit line GBL fluctuates according to this current. The fluctuation of global bit line GBL's potential is prevented from being affected by the sense amplifier 62_C by setting the switching signal CSEL1 low. Wiring VHH or wiring VLL is the same as wiring VHH or wiring VLL during period T14.

[0135] During period T16, by making the switching signal CSEL1 high, the potential variation of the global bit line GBL is amplified by the bit line pair connected to the sense amplifier 62_C, so as to read out the data signal written to the memory cell.

[0136] In one aspect of the present invention, OS transistors with extremely low off-state current are used as transistors disposed in each element layer. Therefore, the refresh frequency of data stored in the memory cell can be reduced, enabling a low-power semiconductor device. OS transistors can be stacked and manufactured by repeatedly using the same manufacturing process in the vertical direction, thus reducing manufacturing costs. Furthermore, in another aspect of the present invention, the transistors constituting the memory cell can be arranged vertically rather than planarly to increase storage density, thereby enabling device miniaturization. Additionally, OS transistors exhibit less variation in electrical characteristics even at high temperatures than Si transistors, thus enabling a semiconductor device with minimal variation in transistor electrical characteristics when stacked and integrated, and suitable for use as a reliable memory device.

[0137] In one embodiment of the present invention, the component layer employs a structure in which a transistor layer including a memory cell is disposed above and below a transistor layer having a switching circuit and an amplification circuit in the z-axis direction. By adopting this structure, the distance between the memory cell and the switching circuit and amplification circuit can be shortened. When the local linear distance is shortened, parasitic capacitance can be reduced. By repeatedly manufacturing multiple transistor layers 30, 40 using the same manufacturing process in the vertical direction, manufacturing costs can be reduced.

[0138] (Implementation Method 2)

[0139] The following describes an example of a semiconductor device used as a storage device according to one aspect of the present invention.

[0140] Figure 13 This is a diagram illustrating an example of a semiconductor device in which memory cells 470 (memory cells 470_1 to memory cells 470_m: m is a natural number greater than or equal to 2) are stacked on a component layer 411 including a circuit disposed on a semiconductor substrate 311. Figure 13 In the example shown, a component layer 411 and a plurality of memory cells 470 on the component layer 411 are stacked. In each of the plurality of memory cells 470, a transistor layer 413 (transistor layer 413_1 to transistor layer 413_m) and a plurality of memory device layers 415 (memory device layers 415_1 to memory device layers 415_n: n is a natural number of 2 or more) are respectively provided. Furthermore, as an example shown, each memory cell 470 has a memory device layer 415 on the transistor layer 413; however, this embodiment is not limited to this. The transistor layer 413 can be provided on the plurality of memory device layers 415, or the memory device layers 415 can be provided above and below the transistor layer 413.

[0141] The component layer 411 may include transistors 300 disposed on the semiconductor substrate 311 and circuitry (sometimes referred to as peripheral circuitry) used as semiconductor devices. Examples of such circuitry include column drivers, row drivers, column decoders, row decoders, sense amplifiers, precharge circuits, amplifier circuits, word line driver circuits, output circuits, and control logic circuits.

[0142] Transistor layer 413 may include transistor 200T and is used as circuitry to control each memory cell 470. Memory device layer 415 includes memory device 420. The memory device 420 shown in this embodiment includes transistor 200M and capacitor element 292.

[0143] Furthermore, there are no particular restrictions on the value of m, but it is preferably 2 or more and 100 or less, more preferably 2 or more and 50 or less, and even more preferably 2 or more and 10 or less. Similarly, there are no particular restrictions on the value of n, but it is preferably 2 or more and 100 or less, more preferably 2 or more and 50 or less, and even more preferably 2 or more and 10 or less. Additionally, the product of m and n is preferably 4 or more and 256 or less, more preferably 4 or more and 128 or less, and even more preferably 4 or more and 64 or less.

[0144] in addition, Figure 13 A cross-sectional view along the channel length of transistors 200T and 200M included in the memory cell is shown.

[0145] like Figure 13 As shown, a transistor 300 is disposed on a semiconductor substrate 311. A transistor layer 413 and a memory device layer 415, comprising a memory cell 470, are disposed on the transistor 300. In one memory cell 470, the transistor 200T included in the transistor layer 413 and the memory device 420 included in the memory device layer 415 are electrically connected by a plurality of conductors 424. The transistor 300 and the transistor 200T included in the transistor layer 413 of each memory cell 470 are electrically connected by conductors 426. Furthermore, the conductors 426 are preferably electrically connected to the transistor 200T via conductors 428 that are electrically connected to any one of the source, drain, and gate of the transistor 200T. The conductors 424 are preferably disposed in each layer of the memory device layer 415. Additionally, the conductors 426 are preferably disposed in each layer of the transistor layer 413 and the memory device layer 415.

[0146] Furthermore, it is preferable to provide an insulator that inhibits the permeation of impurities such as water or hydrogen, or oxygen, on the sides of conductor 424 and conductor 426. Details will be described later. As such an insulator, silicon nitride, aluminum oxide, or silicon oxynitride are preferred.

[0147] The memory device 420 includes a transistor 200M and a capacitor element 292. The transistor 200M has the same structure as the transistor 200T included in the transistor layer 413. In addition, transistors 200T and 200M are sometimes collectively referred to as transistor 200.

[0148] Here, it is preferable to use a metal oxide (hereinafter sometimes referred to as an oxide semiconductor) as an oxide semiconductor in transistor 200 for the semiconductor that includes the region in which the channel is formed (hereinafter sometimes referred to as the channel forming region).

[0149] For example, In-M-Zn oxides (where element M is selected from one or more of aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium) are preferred as oxide semiconductors. Indium oxide, In-Ga oxide, and In-Zn oxide are also preferred as oxide semiconductors. Note that by using oxide semiconductors with a high indium ratio, the on-state current or field-effect mobility of transistors can be improved.

[0150] Since the leakage current in the non-conducting state of the transistor 200, which uses oxide semiconductor in the channel formation region, is extremely small, a low-power semiconductor device can be provided. Furthermore, since oxide semiconductor can be formed using methods such as sputtering, it can be used to construct transistors 200 that form highly integrated semiconductor devices.

[0151] On the other hand, in transistors using oxide semiconductors, their electrical characteristics are affected by impurities and oxygen vacancies (also known as V0) in the oxide semiconductor. O The voltage (oxygen vacancy) varies, so the transistor is prone to always-on characteristics (meaning that the channel exists and current flows through the transistor even when no voltage is applied to the gate electrode).

[0152] Therefore, oxide semiconductors with reduced impurity concentration and defect state density are preferred. Note that in this specification, the condition of low impurity concentration and low defect state density is referred to as high-purity intrinsic or substantially high-purity intrinsic.

[0153] Therefore, it is preferable to minimize the impurity concentration in oxide semiconductors. Examples of impurities in oxide semiconductors include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0154] In particular, hydrogen, as an impurity contained in oxide semiconductors, sometimes forms oxygen vacancies in the oxide semiconductor. Furthermore, hydrogen enters defects within these oxygen vacancies (hereinafter sometimes referred to as V0). O H) may generate electrons that become charge carriers. Furthermore, a portion of the hydrogen may react with oxygen atoms bonded to metal atoms to generate electrons that become charge carriers.

[0155] Therefore, transistors using oxide semiconductors containing a large amount of hydrogen tend to have always-on characteristics. Furthermore, because hydrogen in oxide semiconductors is easily mobile due to heat, electric fields, etc., a large amount of hydrogen in the oxide semiconductor may lead to a decrease in transistor reliability.

[0156] Therefore, as an oxide semiconductor for transistor 200, it is preferable to use an intrinsically high-purity oxide semiconductor with reduced impurities such as hydrogen and oxygen vacancies.

[0157] <Sealing Structure>

[0158] Therefore, in order to suppress impurities introduced from the outside, it is preferable to use a material that suppresses the diffusion of impurities (hereinafter also referred to as a material that blocks impurities) to seal the transistor 200.

[0159] Note that in this specification, barrier properties refer to the ability to inhibit the diffusion of the corresponding substance (also known as low permeability). Alternatively, it refers to the ability to capture and fix the corresponding substance (also known as gettering).

[0160] For example, materials that can inhibit the diffusion of hydrogen and oxygen include alumina, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon oxynitride. In particular, silicon nitride or silicon oxynitride has high hydrogen barrier properties and is therefore preferred as a sealing material.

[0161] For example, metal oxides such as aluminum oxide, hafnium oxide, gallium oxide, and indium gallium zinc oxide are materials that can capture and fix hydrogen.

[0162] Insulators 211, 212, and 214 are preferably disposed between transistors 300 and 200 as barrier layers. By using a material that inhibits the diffusion or permeation of impurities such as hydrogen in at least one of insulators 211, 212, and 214, the diffusion of impurities such as hydrogen or water contained in the semiconductor substrate 311 and transistor 300 into transistor 200 can be suppressed. Furthermore, by using a material that inhibits oxygen permeation in at least one of insulators 211, 212, and 214, the diffusion of oxygen contained in the channel or transistor layer 413 of transistor 200 into element layer 411 can be suppressed. For example, materials that inhibit the permeation of impurities such as hydrogen or water are used as insulators 211 and 212, and materials that inhibit oxygen permeation are preferably used as insulator 214. Additionally, a material with the property of absorbing and storing hydrogen is preferably used as insulator 214. For example, nitrides such as silicon nitride and silicon oxynitride can be used as insulators 211 and 212. For example, metal oxides such as aluminum oxide, hafnium oxide, gallium oxide, and indium gallium zinc oxide can be used as insulators 214. Aluminum oxide is particularly preferred as insulator 214.

[0163] Furthermore, an insulator 287 is preferably provided on the side surface of the transistor layer 413 and the memory device layer 415, that is, on the side surface of the memory cell 470, and an insulator 282 is preferably provided on the top surface of the memory cell 470. In this case, the insulator 282 is preferably in contact with the insulator 287, and the insulator 287 is preferably in contact with at least one of the insulators 211, 212, and 214. A material suitable for the insulator 214 is preferably used as both the insulator 287 and the insulator 282.

[0164] Furthermore, insulators 283 and 284 are preferably provided in a manner that covers insulators 282 and 287, and insulator 283 preferably contacts at least one of insulators 211, 212, and 214. Figure 13 In this embodiment, insulator 287 contacts the side surface of insulator 214, the side surface of insulator 212, and the top and side surfaces of insulator 211; insulator 283 contacts the top and side surfaces of insulator 287 and the top surface of insulator 211. However, this embodiment is not limited to this. Insulator 287 may also contact the side surface of insulator 214 and the top and side surfaces of insulator 212, and insulator 283 may also contact the top and side surfaces of insulator 287 and the top surface of insulator 212. Materials suitable for insulators 211 and 212 are preferably used for insulators 282 and 287.

[0165] In the above structure, materials that suppress oxygen permeation are preferably used as insulators 287 and 282. Furthermore, materials with hydrogen-trapping and fixing properties are more preferably used as insulators 287 and 282. By using a material with hydrogen-trapping and fixing functions on the side adjacent to transistor 200, hydrogen in transistor 200 or memory cell 470 is trapped and fixed by insulators 214, 287, and 282, thereby reducing the hydrogen concentration in transistor 200. Additionally, materials that suppress the permeation of impurities such as hydrogen or water are preferably used as insulators 283 and 284.

[0166] By employing the above structure, the memory cell 470 is surrounded by insulators 211, 212, 214, 287, 282, 283, and 284. Specifically, the memory cell 470 is surrounded by insulators 214, 287, and 282 (sometimes referred to as a first structure), and the memory cell 470 and the first structure are surrounded by insulators 211, 212, 283, and 284 (sometimes referred to as a second structure). Furthermore, such a structure, in which multiple structures in two or more layers surround the memory cell 470, is sometimes referred to as a nested structure. Here, the case where the memory cell 470 is surrounded by multiple structures is described as the case where the memory cell 470 is sealed by multiple insulators.

[0167] Furthermore, the second structure seals the transistor 200 through the first structure. Therefore, the second structure can suppress the diffusion of hydrogen present outside the second structure into the interior of the second structure (on the transistor 200 side). In other words, the first structure can efficiently capture and immobilize hydrogen present in the internal structure of the second structure.

[0168] Specifically, as described above, the first structure can be a metal oxide such as aluminum oxide, while the second structure can be a nitride such as silicon nitride. More specifically, it is preferable to place an aluminum oxide film between the transistor 200 and the silicon nitride film.

[0169] Furthermore, by appropriately setting the film-forming conditions, the hydrogen concentration in the materials used in the structure can be reduced.

[0170] Generally, membranes formed by CVD have higher coverage than those formed by sputtering. On the other hand, the compound gases used in CVD often contain hydrogen, therefore membranes formed by CVD have a higher hydrogen content than those formed by sputtering.

[0171] Therefore, for example, the film adjacent to the transistor 200 is preferably a film with a reduced hydrogen concentration (specifically, a film formed by sputtering). On the other hand, when a film with high coverage and a high hydrogen concentration (specifically, a film formed by CVD) is used as a film to suppress the diffusion of impurities, it is preferable to arrange a film with the function of trapping and fixing hydrogen and with a reduced hydrogen concentration between the transistor 200 and the film with a high hydrogen concentration and high coverage.

[0172] In other words, a membrane with a low hydrogen concentration is preferably used as the membrane disposed adjacent to the transistor 200. On the other hand, it is preferable to dispose of a membrane with a high hydrogen concentration separately from the transistor 200.

[0173] Specifically, when using a silicon nitride film-sealed transistor 200 formed by CVD, it is preferable to place an aluminum oxide film formed by sputtering between the transistor 200 and the silicon nitride film formed by CVD. More preferably, it is preferable to place a silicon nitride film formed by sputtering between the silicon nitride film formed by CVD and the aluminum oxide film formed by sputtering.

[0174] In addition, when using CVD to form films, the concentration of hydrogen contained in the formed film can be reduced by using a compound gas that does not contain hydrogen atoms or contains few hydrogen atoms.

[0175] Furthermore, it is preferable to provide insulators 282 and 214 between each transistor layer 413 and memory device layer 415, or between each memory device layer 415. It is also preferable to provide insulator 296 between insulators 282 and 214. The same material as insulators 283 and 284 can be used as insulator 296. Alternatively, silicon oxide or silicon oxynitride can be used. Alternatively, known insulating materials can be used. Here, insulators 282, 296, and 214 can also be elements constituting transistor 200. Since insulators 282, 296, and 214 also serve as elements constituting transistor 200, the number of manufacturing steps required for semiconductor devices can be reduced, which is therefore preferred.

[0176] Furthermore, the sides of insulators 282, 296, and 214, preferably disposed between each transistor layer 413 and memory device layer 415 or between each memory device layer 415, are preferably in contact with insulator 287. With this structure, the transistor layer 413 and memory device layer 415 are surrounded and sealed by insulators 282, 296, 214, 287, 283, and 284, respectively.

[0177] Alternatively, an insulator 274 may be disposed around an insulator 284. Alternatively, a conductor 430 may be formed by embedding itself within insulators 274, 284, 283, and 211. The conductor 430 is electrically connected to the transistor 300, i.e., the circuitry included in the element layer 411.

[0178] Furthermore, in the memory device layer 415, the capacitor element 292 is disposed on the same layer as the transistor 200M. Therefore, the height of the memory device 420 and the height of the transistor 200M can be made to be similar, thus preventing the height of each memory device layer 415 from becoming too large. As a result, it is easier to increase the number of memory device layers 415. For example, the layers consisting of the transistor layer 413 and the memory device layer 415 can be stacked to about 100 layers.

[0179] <Transistor 200>

[0180] Reference Figure 14A This describes transistor 200, which can be used in transistor 200T included in transistor layer 413 and transistor 200M included in memory device 420.

[0181] like Figure 14AAs shown, transistor 200 includes insulator 216, conductor 205 (conductor 205a and conductor 205b), insulator 222, insulator 224, oxide 230 (oxide 230a, oxide 230b and oxide 230c), conductor 242 (conductor 242a and conductor 242b), oxide 243 (oxide 243a and oxide 243b), insulator 272, insulator 273, insulator 250, and conductor 260 (conductor 260a and conductor 260b).

[0182] Furthermore, an insulator 216 and a conductor 205 are disposed on an insulator 214, and an insulator 280 and an insulator 282 are disposed on an insulator 273. The insulators 214, 280, and 282 can be considered as part of the transistor 200.

[0183] Additionally, one embodiment of the semiconductor device of the present invention includes a conductor 240 (conductor 240a and conductor 240b) electrically connected to a transistor 200 and used as a plug. Alternatively, an insulator 241 (insulator 241a and insulator 241b) may be provided in contact with the side of the conductor 240 used as a plug. Furthermore, conductors 246 (conductors 246a and conductor 246b) electrically connected to the conductor 240 and used as wiring are provided on the insulator 282 and the conductor 240.

[0184] Furthermore, conductors 240a and 240b are preferably made of conductive materials with tungsten, copper, or aluminum as the main components. Additionally, conductors 240a and 240b may have a laminated structure.

[0185] When the conductor 240 adopts a multilayer structure, it is preferable to use a conductive material that has the function of suppressing the permeation of impurities such as water or hydrogen and oxygen. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide are preferred. Furthermore, the conductive material that suppresses the permeation of impurities such as water or hydrogen and oxygen can be used as a single layer or in multilayers. By using this conductive material, it is possible to further reduce the amount of impurities such as water or hydrogen diffusing from the insulator 280 and entering the oxide 230 through the conductors 240a and 240b. In addition, it is possible to prevent oxygen added to the insulator 280 from being absorbed by the conductors 240a and 240b.

[0186] Furthermore, the insulator 241, which is provided in contact with the side of the conductor 240, can be, for example, silicon nitride, aluminum oxide, or silicon oxynitride. Because the insulator 241 is provided in contact with insulators 272, 273, 280, and 282, impurities such as water or hydrogen from insulators 280 can be prevented from entering the oxide 230 through conductors 240a and 240b. In particular, silicon nitride is preferred due to its high hydrogen barrier properties. Furthermore, it can prevent the absorption of oxygen contained in the insulator 280 by conductors 240a and 240b.

[0187] The conductor 246 is preferably made of a conductive material with tungsten, copper, or aluminum as its main components. Additionally, the conductor may have a multilayer structure, for example, a multilayer structure of titanium or titanium nitride with the aforementioned conductive material. Furthermore, the conductor may be formed by embedding it within an opening in an insulator.

[0188] In transistor 200, conductor 260 is used as the first gate of the transistor, and conductor 205 is used as the second gate of the transistor. In addition, conductors 242a and 242b are used as source electrodes or drain electrodes.

[0189] Oxide 230 is used as a semiconductor including the channel formation region.

[0190] Insulator 250 is used as the first gate insulator. Insulators 222 and 224 are used as the second gate insulators.

[0191] Here, in Figure 14A In the transistor 200 shown, a conductor 260 is formed in a self-aligned manner in the openings provided in the insulator 280, insulator 273, insulator 272 and conductor 242, with oxide 230c and insulator 250 in between.

[0192] In other words, the conductor 260 is formed by being embedded in an opening provided in the insulator 280, etc., with the oxide 230c and the insulator 250 in between. Therefore, it is not necessary to align the conductor 260 in the region between the conductor 242a and the conductor 242b.

[0193] Here, it is preferable to provide oxide 230c within the opening formed in insulator 280, etc. Therefore, insulator 250 and conductor 260 include regions of a stacked structure of oxides 230b and 230a separated by oxide 230c. By employing this structure, oxide 230c and insulator 250 can be formed continuously, thereby maintaining a clean interface between oxide 230 and insulator 250. Therefore, the influence of interface scattering on carrier conduction is reduced, resulting in high on-state current and high frequency characteristics for transistor 200.

[0194] exist Figure 14A In the transistor 200 shown, the bottom and side surfaces of the conductor 260 are in contact with the insulator 250. Furthermore, the bottom and side surfaces of the insulator 250 are in contact with the oxide 230c.

[0195] In addition, such as Figure 14A As shown, transistor 200 has a structure in which insulator 282 and oxide 230c are in direct contact. By employing this structure, the diffusion of oxygen contained in insulator 280 into conductor 260 can be suppressed.

[0196] Therefore, the oxygen contained in the insulator 280 can be efficiently supplied to oxides 230a and 230b through oxide 230c, thereby reducing oxygen vacancies in oxides 230a and 230b and improving the electrical characteristics and reliability of transistor 200.

[0197] The detailed structure of a semiconductor device including a transistor 200 according to one aspect of the present invention will now be described.

[0198] Preferably, in transistor 200, a metal oxide (hereinafter, sometimes referred to as oxide semiconductor) used as an oxide semiconductor is used in oxide 230 (oxide 230a, oxide 230b and oxide 230c) including the channel forming region.

[0199] For example, the bandgap of the metal oxide used as an oxide semiconductor is 2 eV or more, preferably 2.5 eV or more. By using a metal oxide with a wide bandgap, the leakage current (off-state current) of the transistor 200 in the non-conducting state can be minimized. By employing such a transistor, a low-power semiconductor device can be provided.

[0200] Specifically, the oxide 230 preferably uses an In-M-Zn oxide (where element M is selected from one or more of aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium). In particular, aluminum, gallium, yttrium, or tin can be used as element M. Furthermore, In-M oxide, In-Zn oxide, or M-Zn oxide can also be used as oxide 230.

[0201] like Figure 14A As shown, oxide 230 preferably includes oxide 230a on insulator 224, oxide 230b on oxide 230a, and oxide 230c disposed on oxide 230b, at least a portion of which is in contact with the top surface of oxide 230b. Preferably, oxide 230c is disposed such that its side surface is in contact with oxide 243a, oxide 243b, conductor 242a, conductor 242b, insulator 272, insulator 273, and insulator 280.

[0202] In other words, oxide 230 includes oxide 230a, oxide 230b on oxide 230a, and oxide 230c on oxide 230b. When oxide 230a is disposed under oxide 230b, the diffusion of impurities from the structure formed under oxide 230a to oxide 230b can be suppressed. When oxide 230c is disposed on oxide 230b, the diffusion of impurities from the structure formed above oxide 230c to oxide 230b can be suppressed.

[0203] Note that in transistor 200, three layers of oxide 230a, oxide 230b, and oxide 230c are stacked in and around the channel formation region, but the present invention is not limited thereto. For example, a single layer of oxide 230b, a two-layer structure of oxide 230b and oxide 230a, a two-layer structure of oxide 230b and oxide 230c, or a stacked structure of four or more layers can be provided. For example, oxide 230c can also have a two-layer structure to form a four-layer stacked structure.

[0204] Furthermore, oxide 230 preferably has a stacked structure of multiple oxide layers having different atomic ratios for each metal atom. Specifically, the atomic ratio of element M in the constituent elements of the metal oxide used for oxide 230a is preferably greater than that in the constituent elements of the metal oxide used for oxide 230b. Additionally, the atomic ratio of element M relative to In in the metal oxide used for oxide 230a is preferably greater than that in the metal oxide used for oxide 230b. Furthermore, the atomic ratio of In relative to element M in the metal oxide used for oxide 230b is preferably greater than that in the metal oxide used for oxide 230a. Additionally, oxide 230c can use a metal oxide that can be used for either oxide 230a or oxide 230b.

[0205] Specifically, as oxide 230a, a metal oxide with an In:Ga:Zn ratio of 1:3:4 or similar, or an In:Ga:Zn ratio of 1:1:0.5 or similar, can be used.

[0206] Alternatively, as oxide 230b, a metal oxide with an In:Ga:Zn ratio of 4:2:3 or similar, or an In:Ga:Zn ratio of 1:1:1 or similar, can be used. Alternatively, as oxide 230b, a metal oxide with an In:Ga:Zn ratio of 5:1:3 or similar, or an In:Ga:Zn ratio of 10:1:3 or similar, can also be used. Furthermore, In-Zn oxides (e.g., In:Zn = 2:1 or similar, In:Zn = 5:1 or similar, or In:Zn = 10:1 or similar) can also be used. Additionally, In oxides can also be used as oxide 230b.

[0207] Alternatively, as oxide 230c, a metal oxide with an In:Ga:Zn ratio of 1:3:4 or similar, a Ga:Zn ratio of 2:1 or similar, or a Ga:Zn ratio of 2:5 or similar can be used. Furthermore, as oxide 230c, a material suitable for oxide 230b can be used, and it can be arranged in a single layer or in a multilayer. For example, as specific examples of oxide 230c having a layered structure, we can cite layered structures with In:Ga:Zn = 4:2:3 [atomic ratio] or near and In:Ga:Zn = 1:3:4 [atomic ratio] or near, Ga:Zn = 2:1 [atomic ratio] or near and In:Ga:Zn = 4:2:3 [atomic ratio] or near, Ga:Zn = 2:5 [atomic ratio] or near and In:Ga:Zn = 4:2:3 [atomic ratio] or near, and gallium oxide and In:Ga:Zn = 4:2:3 [atomic ratio] or near, etc.

[0208] Note that the structure of the OS transistor included in the memory cell 33 shown in Embodiment 1 may also be different from the structure of the OS transistor included in the element layer 50. For example, the oxide 230c included in the OS transistor provided in the memory cell 33 may be a metal oxide with an In:Ga:Zn ratio of 4:2:3 or similar, and the oxide 230c included in the OS transistor provided in the element layer 50 may be a metal oxide with an In:Ga:Zn ratio of 5:1:3 or similar, an In:Ga:Zn ratio of 10:1:3 or similar, an In:Zn ratio of 10:1 or similar, an In:Zn ratio of 10:1 or similar, an In:Zn ratio of 5:1 or similar, or an In:Zn ratio of 2:1 or similar.

[0209] Furthermore, in oxides 230b and 230c, increasing the indium ratio can improve the on-state current or field-effect mobility of transistors, making them preferred. Additionally, the aforementioned composition includes a range of ±30% of the desired atomic number ratio.

[0210] Furthermore, the oxide 230b can also be crystalline. For example, CAAC-OS (c-axisaligned crystalline oxide semiconductor) is preferably used. Crystalline oxides such as CAAC-OS have a highly crystalline and dense structure with few impurities and defects (oxygen vacancies, etc.). Therefore, oxygen extraction from the oxide 230b at the source or drain electrode can be suppressed. In addition, even with heat treatment, oxygen extraction from the oxide 230b can be reduced, so the transistor 200 is also stable against the high temperatures (so-called thermal budget) in the manufacturing process.

[0211] The conductor 205 is arranged to overlap with the oxide 230 and the conductor 260. Furthermore, the conductor 205 is preferably disposed in an insulator 216.

[0212] When conductor 205 is used as the gate electrode, the threshold voltage (Vth) of transistor 200 can be controlled by independently changing the potential supplied to conductor 205 without linking it to the potential applied to conductor 260. In particular, by applying a negative potential to conductor 205, the Vth of transistor 200 can be increased and the off-state current can be reduced. Therefore, compared with not applying a negative potential to conductor 205, applying a negative potential to conductor 205 can reduce the drain current when the potential applied to conductor 260 is 0V.

[0213] In addition, such as Figure 14AAs shown, conductor 205 is preferably larger than the area in oxide 230 that does not overlap with conductors 242a and 242b. Although not shown, conductor 205 preferably extends to the region outside oxides 230a and 230b in the channel width direction of oxide 230. That is, conductors 205 and 260 preferably overlap with an insulator on the outer side of the side in the channel width direction of oxide 230. By making conductor 205 large, localized charging (also known as charge up) can sometimes be mitigated in plasma processing during manufacturing steps after conductor 205 is formed. However, one aspect of the invention is not limited to this. It is sufficient that conductor 205 overlaps at least with oxide 230 located between conductors 242a and 242b.

[0214] Furthermore, taking the bottom surface of the insulator 224 as a standard, the bottom surface of the conductor 260 in the region where the oxides 230a and 230b and the conductor 260 do not overlap is preferably located at a position lower than the bottom surface of the oxide 230b.

[0215] Although not illustrated, by having the conductor 260, used as the gate, have a structure in the channel width direction such that the sides and top surfaces of the oxide 230b, which is separated from the oxide 230c and the insulator 250, cover the channel-forming region, it is easy for the electric field generated from the conductor 260 to act on the entire channel-forming region formed in the oxide 230b. Therefore, the on-state current of the transistor 200 can be increased to improve the frequency characteristics. In this specification, the structure of the transistor in which the electric fields of the conductor 260 and the conductor 205 surround the channel-forming region is referred to as a surrounded channel (S-channel) structure.

[0216] Conductor 205a is preferably a conductor that suppresses the permeation of impurities such as water or hydrogen, as well as oxygen. For example, titanium, titanium nitride, tantalum, or tantalum nitride can be used. Furthermore, conductor 205b is preferably made of a conductive material with tungsten, copper, or aluminum as the main component. In addition, although a conductor 205 with a two-layer structure is shown, conductor 205 may also have a multilayer structure with three or more layers.

[0217] Here, by continuously forming different types of films in a manner that does not expose them to the atmosphere, an intrinsically high-purity oxide semiconductor film with a reduced concentration of impurities (especially hydrogen and water) can be formed, which is therefore preferred.

[0218] At least one of insulators 222, 272, and 273 is preferably used as a barrier insulating film to prevent impurities such as water or hydrogen from mixing into the transistor 200 from one side or above the substrate. Therefore, as at least one of insulators 222, 272, and 273, an insulating material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms (making it difficult for the aforementioned impurities to permeate) is preferably used. Furthermore, an insulating material that has the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (making it difficult for the aforementioned oxygen to permeate) is preferably used.

[0219] For example, silicon nitride or silicon oxynitride is preferably used as insulator 273, while aluminum oxide or hafnium oxide is preferably used as insulator 222 and insulator 272.

[0220] This can suppress the diffusion of impurities such as water or hydrogen through insulator 222 to the transistor 200 side. Alternatively, it can suppress the diffusion of oxygen contained in insulator 224, etc., through insulator 222 to the substrate side.

[0221] Furthermore, it can also suppress the diffusion of impurities such as water or hydrogen from the insulator 280, which is disposed between insulators 272 and 273, to the transistor 200 side. Thus, it is preferable to adopt a structure in which the transistor 200 is surrounded by insulators 272 and 273, which have the function of suppressing the diffusion of impurities such as water or hydrogen and oxygen.

[0222] Here, the insulator 224 in contact with the oxide 230 is preferably heated to remove oxygen. In this specification, the oxygen removed by heating is sometimes referred to as excess oxygen. For example, silicon oxide or silicon oxynitride can be suitably used as the insulator 224. By providing an insulator containing excess oxygen in a manner that allows it to contact the oxide 230, oxygen vacancies in the oxide 230 can be reduced, thereby improving the reliability of the transistor 200.

[0223] Specifically, as the insulator 224, an oxide material that undergoes partial oxygen removal upon heating is preferably used. An oxide that undergoes oxygen removal upon heating is defined as one in which the amount of oxygen molecules removed in thermal desorption spectroscopy (TDS) analysis is 1.0 × 10⁻⁶. 18 molecules / cm 3 The preferred value is 1.0 × 10⁴. 19 molecules / cm 3 The above is further preferred to be 2.0×10 19 molecules / cm 3 Above, or 3.0 × 10 20molecules / cm 3 The above-mentioned oxide film. Furthermore, the surface temperature of the film during the above TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0224] Insulator 222 is preferably used as a barrier insulating film to prevent impurities such as water or hydrogen from mixing into transistor 200 from the substrate side. For example, the hydrogen permeability of insulator 222 is preferably lower than that of insulator 224. By surrounding insulator 224 and oxide 230 with insulator 222 and insulator 283, impurities such as water or hydrogen from the outside can be prevented from entering transistor 200.

[0225] Furthermore, insulator 222 preferably has the function of inhibiting the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (making it difficult for the aforementioned oxygen to permeate). For example, the oxygen permeability of insulator 222 is preferably lower than that of insulator 224. By enabling insulator 222 to have the function of inhibiting the diffusion of oxygen or impurities, the diffusion of oxygen present in oxide 230 to the underside of insulator 222 can be reduced, which is therefore preferred. In addition, the reaction between conductor 205 and oxygen present in insulator 224 and oxide 230 can be suppressed.

[0226] The insulator 222 is preferably an insulator containing an oxide of one or both of aluminum and hafnium as insulating materials. Alumina, hafnium oxide, and oxides containing aluminum and hafnium (hafnium aluminate) are preferred as insulators containing one or both of aluminum and hafnium. When this material is used to form the insulator 222, the insulator 222 serves as a layer to suppress the release of oxygen from the oxide 230 or the entry of impurities such as hydrogen from the periphery of the transistor 200 into the oxide 230.

[0227] Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide can be added to the insulator. Alternatively, the insulator can be nitrided. Alternatively, silicon oxide, silicon oxynitride, or silicon nitride can be laminated onto the insulator.

[0228] Furthermore, as the insulator 222, high-k materials such as alumina, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST) can be used as a single layer or in a stack. For example, when the insulator 222 has a stacked structure, a three-layer stack of zirconium oxide, alumina, and zirconium oxide formed sequentially, or a four-layer stack of zirconium oxide, alumina, zirconium oxide, and alumina formed sequentially, can be used. Additionally, compounds containing hafnium and zirconium can be used as the insulator 222. During the miniaturization and high integration of semiconductor devices, the thin-film dielectric used for gate insulators and capacitor elements sometimes causes problems such as leakage current in transistors or capacitor elements. By using high-k materials as the insulator used as the dielectric for gate insulators and capacitor elements, the gate potential during transistor operation can be reduced while maintaining the physical thickness, and the capacitance of the capacitor element can be ensured.

[0229] Alternatively, insulators 222 and 224 may also have a multilayer structure with two or more layers. In this case, it is not limited to a multilayer structure made of the same material, but may also be a multilayer structure made of different materials.

[0230] Alternatively, oxide 243 (oxide 243a and oxide 243b) can be disposed between oxide 230b and conductor 242 (conductor 242a and conductor 242b) used as source or drain electrodes. Since conductor 242 does not contact oxide 230b, the absorption of oxygen from oxide 230b by conductor 242 can be suppressed. That is, by preventing oxidation of conductor 242, the decrease in conductivity of conductor 242 can be suppressed. Therefore, oxide 243 preferably has the function of suppressing oxidation of conductor 242.

[0231] When an oxide 243, which has the function of inhibiting oxygen permeation, is disposed between the conductor 242, which is used as the source electrode or drain electrode, and the oxide 230b, the resistance between the conductor 242 and the oxide 230b decreases, which is therefore preferred. By adopting this structure, the electrical characteristics and reliability of the transistor 200 can be improved.

[0232] As oxide 243, a metal oxide having one or more elements M selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium can also be used. In particular, aluminum, gallium, yttrium, or tin is preferred as element M. The concentration of element M in oxide 243 is preferably higher than that in oxide 230b. In addition, gallium oxide can also be used as oxide 243. Furthermore, metal oxides such as In-M-Zn oxide can also be used as oxide 243. Specifically, the atomic ratio of element M relative to In in the metal oxide used for oxide 243 is preferably greater than that in the metal oxide used for oxide 230b. In addition, the thickness of oxide 243 is preferably 0.5 nm or more and 5 nm or less, more preferably 1 nm or more and 3 nm or less. In addition, oxide 243 is preferably crystalline. When oxide 243 is crystalline, the release of oxygen from oxide 230 can be better suppressed. For example, when oxide 243 has a hexagonal or other crystalline structure, it can sometimes suppress the release of oxygen from oxide 230.

[0233] Furthermore, oxide 243 is not necessarily required. In this case, because conductor 242 (conductors 242a and 242b) is in contact with oxide 230, oxygen in oxide 230 diffuses into conductor 242, thereby sometimes oxidizing conductor 242. The possibility of the conductivity of conductor 242 decreasing due to oxidation increases. Note that the diffusion of oxygen from oxide 230 into conductor 242 can also be referred to as conductor 242 absorbing oxygen from oxide 230.

[0234] Furthermore, when oxygen in oxide 230 diffuses into conductor 242 (conductors 242a and 242b), another layer may form between conductor 242a and oxide 230b, and between conductor 242b and oxide 230b. Because this other layer contains more oxygen than conductor 242, it is presumed that this other layer has insulating properties. In this case, the three-layer structure of conductor 242, this other layer, and oxide 230b can be considered a metal-insulator-semiconductor three-layer structure, sometimes referred to as a MIS (Metal-Insulator-Semiconductor) structure or a diode structure dominated by MIS.

[0235] Note that the other layer is not limited to being formed between conductor 242 and oxide 230b. For example, another layer may be formed between conductor 242 and oxide 230c, or between conductor 242 and oxide 230b and between conductor 242 and oxide 230c.

[0236] Conductors 242 (conductors 242a and conductors 242b) used as source and drain electrodes are provided on oxide 243. The thickness of conductor 242 can be, for example, 1 nm or more and 50 nm or less, preferably 2 nm or more and 25 nm or less.

[0237] As the conductor 242, it is preferable to use a metallic element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, an alloy containing the above-mentioned metallic elements, or an alloy combining the above-mentioned metallic elements. For example, tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are conductive materials that are not easily oxidized or that maintain conductivity even when absorbing oxygen, so they are preferred.

[0238] An insulator 272 is disposed in contact with the top surface of the conductor 242, and the insulator 272 is preferably used as a barrier layer. By employing this structure, the absorption of excess oxygen contained in the insulator 280 by the conductor 242 can be suppressed. Furthermore, by suppressing the oxidation of the conductor 242, the increase in contact resistance between the transistor 200 and the wiring can be suppressed. Thus, the transistor 200 can be endowed with good electrical characteristics and reliability.

[0239] Therefore, insulator 272 preferably has the function of suppressing oxygen diffusion. For example, insulator 272 preferably has the function of suppressing the diffusion of oxygen from insulator 280. As insulator 272, for example, it is preferably formed as an insulator containing an oxide of one or both of aluminum and hafnium. In addition, as insulator 272, for example, an insulator containing aluminum nitride can be used.

[0240] like Figure 14A As shown, insulator 272 contacts a portion of the top surface and the side surface of conductor 242b. Although not shown, insulator 272 contacts a portion of the top surface and the side surface of conductor 242a. Additionally, insulator 273 is disposed on insulator 272. By employing this structure, for example, it is possible to suppress the absorption of oxygen added to insulator 280 by conductor 242.

[0241] Insulator 250 is used as a gate insulator. Insulator 250 is preferably disposed in contact with the top surface of oxide 230c. Insulator 250 can be silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, silicon oxide with added carbon and nitrogen, or porous silicon oxide. In particular, silicon oxide and silicon oxynitride are preferred due to their thermal stability.

[0242] Similar to insulator 224, insulator 250 is preferably formed using an insulator that releases oxygen upon heating. By providing an insulator that releases oxygen upon heating in contact with the top surface of oxide 230c as insulator 250, oxygen can be efficiently supplied to the channel formation region of oxide 230b. Similar to insulator 224, it is preferable to reduce the concentration of impurities such as water or hydrogen in insulator 250. The thickness of insulator 250 is preferably 1 nm or more and 20 nm or less.

[0243] Alternatively, a metal oxide can be disposed between the insulator 250 and the conductor 260. This metal oxide preferably suppresses the diffusion of oxygen from the insulator 250 to the conductor 260. By disposing of a metal oxide that suppresses oxygen diffusion, the diffusion of oxygen from the insulator 250 to the conductor 260 can be suppressed. In other words, the reduction in the amount of oxygen supplied to the oxide 230 can be suppressed. Furthermore, oxidation of the conductor 260 due to oxygen in the insulator 250 can be suppressed.

[0244] Furthermore, this metal oxide is sometimes used as part of the gate insulator. Therefore, when silicon oxide or silicon oxynitride is used for the insulator 250, a metal oxide that is a high-k material with a high relative permittivity is preferably used as the metal oxide. By making the gate insulator have a stacked structure of insulator 250 and this metal oxide, a stacked structure with thermal stability and a high relative permittivity can be formed. Therefore, the gate potential applied during transistor operation can be reduced while maintaining the physical thickness of the gate insulator. In addition, the equivalent oxide thickness (EOT) of the insulator used as the gate insulator can be reduced.

[0245] Specifically, one or more metal oxides selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, and magnesium can be used. In particular, aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium (hafnium aluminate) are preferred as insulators containing one or both of aluminum and hafnium.

[0246] Alternatively, the metal oxide is sometimes used as part of the gate. In this case, it is preferable to provide an oxygen-containing conductive material on one side of the channel formation region. By providing an oxygen-containing conductive material on one side of the channel formation region, oxygen detached from the conductive material can be easily supplied to the channel formation region.

[0247] In particular, as the conductor used as the gate, a conductive material containing a metal element and oxygen contained in the metal oxide forming the channel is preferably used. Alternatively, a conductive material containing the aforementioned metal element and nitrogen can also be used. Furthermore, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide with added silicon can be used. Additionally, indium gallium zinc oxide containing nitrogen can also be used. By using the above materials, hydrogen contained in the metal oxide forming the channel can sometimes be trapped. Alternatively, hydrogen mixed in from external insulators or the like can sometimes be trapped.

[0248] Although Figure 14A In the conductor 260, there is a two-layer structure, but it can also have a single-layer structure or a stacked structure of three or more layers.

[0249] The conductor 260a preferably uses a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. Furthermore, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.).

[0250] Furthermore, when the conductor 260a has the function of inhibiting oxygen diffusion, it can prevent the oxygen contained in the insulator 250 from oxidizing the conductor 260b and causing a decrease in conductivity. As a conductive material with the function of inhibiting oxygen diffusion, tantalum, tantalum nitride, ruthenium, or ruthenium oxide are preferably used, for example.

[0251] Furthermore, a conductive material with tungsten, copper, or aluminum as its main component is preferably used as the conductor 260b. Additionally, since the conductor 260 is also used for wiring, a conductor with high conductivity is preferred. For example, a conductive material with tungsten, copper, or aluminum as its main component can be used. Furthermore, the conductor 260b can have a multilayer structure, for example, it can have a multilayer of titanium or titanium nitride with the aforementioned conductive material.

[0252] <<Metal Oxides>>

[0253] As oxide 230, a metal oxide that is used as an oxide semiconductor is preferred. Hereinafter, metal oxides that can be used in oxide 230 according to the present invention will be described.

[0254] The metal oxide preferably contains at least indium or zinc. It is particularly preferred to contain both indium and zinc. Additionally, it preferably contains gallium, yttrium, tin, etc. Alternatively, it may contain one or more of boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium.

[0255] Here, it is estimated that the metal oxide is an In-M-Zn oxide containing indium, element M, and zinc (element M is selected from one or more of aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium). In particular, aluminum, gallium, yttrium, or tin can be used as element M.

[0256] Note that in this specification and other materials, nitrogen-containing metal oxides are sometimes referred to as metal oxides. Furthermore, nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0257] <Transistor 300>

[0258] use Figure 14B Transistor 300 is described. Transistor 300 is disposed on semiconductor substrate 311 and includes: a conductor 316 serving as a gate, an insulator 315 serving as a gate insulator, a semiconductor region 313 formed by a portion of semiconductor substrate 311; and low-resistance regions 314a and 314b serving as source or drain regions. Transistor 300 can be p-channel or n-channel.

[0259] Here, in Figure 14B In the transistor 300 shown, the semiconductor region 313 (a portion of the semiconductor substrate 311) forming the channel has a convex shape. The side and top surfaces of the semiconductor region 313 are provided in such a way that they can be covered by a conductor 316 with an insulator 315 in between. Furthermore, the conductor 316 can be made of a material with an adjustable work function. Because of the convex portion of the semiconductor substrate 311, this transistor 300 is also called a FIN-type transistor. In addition, an insulator for forming the convex portion can also be provided in such a way that it contacts the upper surface of the convex portion. Furthermore, although the case where the convex portion is formed by processing a portion of the semiconductor substrate 311 is shown here, the semiconductor film with the convex portion can also be formed by processing an SOI substrate.

[0260] Notice, Figure 14B The structure of transistor 300 shown is just an example and is not limited to the above structure. Appropriate transistors can be used depending on the circuit structure or driving method.

[0261] <Storage Device 420>

[0262] Next, the explanation Figure 13 The storage device 420 is shown. Furthermore, regarding the transistor 200M included in the storage device 420, descriptions that are redundant with those of transistor 200 are omitted.

[0263] In the storage device 420, the conductor 242a of the transistor 200M is used as one of the electrodes of the capacitor element 292, and the insulators 272 and 273 are used as dielectrics. A conductor 290 is disposed such that it overlaps the conductor 242a with the insulators 272 and 273 in between, and is used as another electrode of the capacitor element 292. The conductor 290 can also be used as another electrode of the capacitor element 292 included in an adjacent storage device 420. Furthermore, the conductor 290 can also be electrically connected to another conductor 290 included in an adjacent storage device 420.

[0264] Conductor 290 is disposed on the top surface and side surface of conductor 242a, separated by insulators 272 and 273. In this case, capacitor element 292 can achieve a larger capacitance than the capacitance obtained by utilizing the overlapping area of ​​conductors 242a and 290, and is therefore preferred.

[0265] Conductor 424 is electrically connected to conductor 242b, and is electrically connected to conductor 424 in the layer below through conductor 205.

[0266] The dielectric material used as capacitor element 292 can be silicon nitride, silicon oxynitride, aluminum oxide, and hafnium oxide, etc. Alternatively, a stack of these materials can be used. When the dielectric material of capacitor element 292 has a stacked structure, a stack of aluminum oxide and silicon nitride, or a stack of hafnium oxide and silicon oxide, can be used. Here, the top and bottom layers of the stack are not limited. For example, silicon nitride can be stacked on aluminum oxide, or aluminum oxide can be stacked on silicon nitride.

[0267] Furthermore, zirconium oxide, which has a higher dielectric constant than the materials described above, can be used as the dielectric of capacitor element 292. Zirconia can be used as a single layer or as part of a stack as the dielectric of capacitor element 292. For example, a stack of zirconium oxide and aluminum oxide can be used. Alternatively, a three-layer stack can be used as the dielectric of capacitor element 292, with zirconium oxide used as the first and third layers and aluminum oxide used as the second layer between the first and third layers.

[0268] By using zirconium oxide, which has a high dielectric constant, as the dielectric of capacitor element 292, the area occupied by capacitor element 292 in memory device 420 can be reduced. Therefore, the area required for memory device 420 can be reduced, thereby improving bit cost, which is preferable.

[0269] In addition, materials that can be used for conductors 205, 242, 260 and 424 can be used as conductors 290.

[0270] This embodiment shows an example where transistors 200M and capacitors 292 are symmetrically arranged with conductors 424 between them. By arranging a pair of transistors 200M and capacitors 292, the number of conductors 424 electrically connected to transistors 200M can be reduced. Therefore, the area required for the memory device 420 can be reduced, thus improving bit cost, which is preferable.

[0271] When the insulator 241 is provided on the side of the conductor 424, the conductor 424 is connected to at least a portion of the top surface of the conductor 242b.

[0272] By using conductors 424 and 205, transistor 200T in memory cell 470 can be electrically connected to memory device 420.

[0273] <Example 1 of a variation of storage device 420>

[0274] Next, refer to Figure 15B As a variation of storage device 420, storage device 420A is described. Storage device 420A includes transistor 200M and capacitor element 292A electrically connected to transistor 200M. Capacitor element 292A is disposed below transistor 200M.

[0275] In the storage device 420A, a conductor 242a is disposed in an opening formed in oxides 243a, 230b, 230a, insulator 224, and 222, and is electrically connected to a conductor 205 at the bottom of the opening. The conductor 205 is electrically connected to a capacitor element 292A.

[0276] Capacitor element 292A includes a conductor 294 used as one of the electrodes, an insulator 295 used as a dielectric, and a conductor 297 used as the other electrode. Conductor 297 overlaps conductor 294 across insulator 295. Additionally, conductor 297 is electrically connected to conductor 205.

[0277] Conductors 294 are disposed at the bottom and sides of the opening formed in the insulator 298 on the insulator 296, and the insulator 295 is disposed such that it covers the insulator 298 and the conductors 294. In addition, conductors 297 are formed in a way that they are embedded in the recesses of the insulator 295.

[0278] Additionally, a conductor 299 is formed by embedding it into an insulator 296, and the conductor 299 is electrically connected to the conductor 294. The conductor 299 can also be electrically connected to the conductor 294 of an adjacent storage device 420A.

[0279] Conductor 297 is disposed on the top surface and side surface of conductor 294, separated by insulator 295. In this case, capacitor element 292A can achieve a larger capacitance than the capacitance obtained by utilizing the overlapping area of ​​conductor 294 and conductor 297, and is therefore preferred.

[0280] The insulator 295, which serves as the dielectric for capacitor element 292A, can be made of silicon nitride, silicon oxynitride, aluminum oxide, or hafnium oxide. Alternatively, a stack of these materials can be used. When the insulator 295 has a stacked structure, a stack of aluminum oxide and silicon nitride, or a stack of hafnium oxide and silicon oxide, can be used. The top and bottom layers of the stack are not limited. For example, silicon nitride can be stacked on aluminum oxide, or aluminum oxide can be stacked on silicon nitride.

[0281] Furthermore, zirconium oxide, which has a higher dielectric constant than the materials described above, can be used as insulator 295. Zirconia 295 can be used as a single layer or as part of a stack. For example, a stack of zirconium oxide and alumina can be used. Additionally, a three-layer stack can be used as insulator 295, with zirconium oxide as the first and third layers and alumina as the second layer between the first and third layers.

[0282] By using zirconium oxide, which has a high dielectric constant, as the insulator 295, the area occupied by the capacitor element 292A in the memory device 420A can be reduced. Therefore, the area required for the memory device 420A can be reduced, thereby improving bit cost, which is preferable.

[0283] In addition, materials that can be used in conductors 205, 242, 260, and 424 can be used as conductors 297, 294, and 299.

[0284] In addition, materials that can be used for insulators 214, 216, 224 and 280 can be used as insulator 298.

[0285] <Example 2 of the variation of storage device 420>

[0286] Next, refer to Figure 15C As a variation of storage device 420, storage device 420B is described. Storage device 420B includes transistor 200M and capacitor element 292B electrically connected to transistor 200M. Capacitor element 292B is disposed above transistor 200M.

[0287] Capacitor element 292B includes a conductor 276 used as one of the electrodes, an insulator 277 used as a dielectric, and a conductor 278 used as the other of the electrodes. Conductor 278 overlaps conductor 276 through insulator 277.

[0288] An insulator 275 is provided on an insulator 282, and a conductor 276 is provided at the bottom and sides of the openings formed in the insulators 275, 282, 280, 273, and 272. An insulator 277 is provided to cover the insulator 282 and the conductor 276. Furthermore, a conductor 278 is provided to overlap the conductor 276 in a recess of the insulator 277, with at least a portion of it disposed on the insulator 275 across the insulator 277. The conductor 278 can also be used as another electrode of the capacitor element 292B included in the adjacent storage device 420B. Additionally, the conductor 278 can be electrically connected to the conductor 278 included in the adjacent storage device 420B.

[0289] Conductor 278 is disposed on the top surface and side surface of conductor 276, separated by insulator 277. In this case, capacitor element 292B can achieve a larger capacitance than the capacitance obtained by utilizing the overlapping area of ​​conductors 276 and 278, and is therefore preferred.

[0290] Alternatively, the insulator 279 can be formed by embedding it into the recess provided in the conductor 278.

[0291] The insulator 277, which serves as the dielectric of capacitor element 292B, can be made of silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, etc. Alternatively, a stack of these materials can be used. When the insulator 277 has a stacked structure, a stack of aluminum oxide and silicon nitride, or a stack of hafnium oxide and silicon oxide, can be used. Here, the top and bottom layers of the stack are not limited. For example, silicon nitride can be stacked on aluminum oxide, or aluminum oxide can be stacked on silicon nitride.

[0292] Furthermore, zirconium oxide, which has a higher dielectric constant than the materials described above, can be used as insulator 277. Zirconia 277 can be a single layer or used as part of a stack. For example, a stack of zirconium oxide and alumina can be used. Additionally, a three-layer stack can be used as insulator 277, with zirconium oxide as the first and third layers and alumina as the second layer between the first and third layers.

[0293] By using zirconium oxide, which has a high dielectric constant, as the insulator 277, the area occupied by the capacitor element 292B in the memory device 420B can be reduced. Therefore, the area required for the memory device 420B can be reduced, thereby improving bit cost.

[0294] In addition, materials that can be used for conductors 205, 242, 260 and 424 can be used as conductors 276 and 278.

[0295] In addition, materials that can be used in insulators 214, 216, 224 and 280 can be used as insulators 275 and 279.

[0296] <Connection of storage device 420 and transistor 200T>

[0297] exist Figure 13 In the area 422 surrounded by the dotted line, although the storage device 420 is electrically connected to the gate of the transistor 200T via a conductor 424 or the like, this embodiment is not limited to this.

[0298] Figure 16 An example is shown where the storage device 420 is electrically connected to a conductor 242b, which is used as one of the source and drain terminals of a transistor 200T, via conductors 424, 205, 246b, and 240b.

[0299] Thus, the connection method between the storage device 420 and the transistor 200T can be determined based on the function of the circuit included in the transistor layer 413.

[0300] Figure 17 An example is shown where the memory cell 470 includes a transistor layer 413 with transistors 200T and four memory device layers 415 (memory device layers 415_1 to memory device layers 415_4).

[0301] Storage device layers 415_1 to 415_4 each include multiple storage devices 420.

[0302] The memory device 420 is electrically connected to the memory device 420 included in the different memory device layers 415 and the transistor 200T of the transistor layer 413 via conductors 424 and 205.

[0303] The memory cell 470 is sealed by insulators 211, 212, 214, 287, 282, 283, and 284. An insulator 274 is disposed around the insulator 284. Furthermore, conductors 430 are provided on insulators 274, 284, 283, and 211 and are electrically connected to the element layer 411.

[0304] In addition, an insulator 280 is provided inside the sealed structure. The insulator 280 has the function of releasing oxygen upon heating. In addition, the insulator 280 has an excess oxygen region.

[0305] Furthermore, insulators 211, 283, and 284 are preferably materials with high hydrogen barrier properties. Additionally, insulators 214, 282, and 287 are preferably materials that trap or fix hydrogen.

[0306] For example, silicon nitride or silicon oxynitride are examples of materials that have high hydrogen barrier properties. In addition, aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium (hafnium aluminate) are examples of materials that can capture or fix hydrogen.

[0307] Note that in this specification, barrier properties refer to the ability to inhibit the diffusion of the corresponding substance (also known as low permeability). Alternatively, it refers to the ability to capture and fix the corresponding substance (also known as gettering).

[0308] Furthermore, there are no particular restrictions on the crystal structure of the materials used for insulators 211, 212, 214, 287, 282, 283, and 284; however, structures with either amorphous or crystalline properties are acceptable. For example, amorphous alumina films are preferred as materials for capturing or fixing hydrogen. Compared to highly crystalline alumina, amorphous alumina sometimes captures and fixes a larger amount of hydrogen.

[0309] Here, the excess oxygen in the insulator 280 can be estimated as the diffusion of hydrogen in the oxide semiconductor of the insulator 280, with the following model.

[0310] Hydrogen present in the oxide semiconductor diffuses to other structures through insulator 280 in contact with the oxide semiconductor. Excess oxygen in insulator 280 reacts with hydrogen in the oxide semiconductor to form OH bonds and diffuses into insulator 280. When hydrogen atoms with OH bonds reach a material that traps or fixes hydrogen (typically insulator 282), the hydrogen atoms react with oxygen atoms (e.g., metal atoms, etc.) bonded to insulator 282 and are trapped or fixed in insulator 282. On the other hand, oxygen atoms with OH bonds in the excess oxygen are estimated to remain in insulator 280 as excess oxygen. In other words, the excess oxygen in insulator 280 is highly likely to have a bridging effect during the diffusion of hydrogen.

[0311] To satisfy the above model, one of the important elements is the manufacturing process of semiconductor devices.

[0312] As an example, after forming an insulator 280 containing excess oxygen in the oxide semiconductor, an insulator 282 is formed. Then, a heat treatment is preferably performed. Specifically, this heat treatment is performed at a temperature of 350°C or higher, preferably 400°C or higher, in an atmosphere containing oxygen, an atmosphere containing nitrogen, or a mixture of oxygen and nitrogen. The heat treatment time is 1 hour or more, preferably 4 hours or more, and more preferably 8 hours or more.

[0313] Through the aforementioned heat treatment, hydrogen in the oxide semiconductor can diffuse to the outside through insulators 280, 282, and 287. In other words, the absolute amount of hydrogen present in and around the oxide semiconductor can be reduced.

[0314] Insulators 283 and 284 are formed after the above heat treatment. Because insulators 283 and 284 are materials with high hydrogen barrier properties, hydrogen that diffuses to the outside or hydrogen present in the outside can be suppressed from entering the interior, specifically on the oxide semiconductor or insulator 280 side.

[0315] Note that while the above-described heat treatment is shown as being performed after the formation of insulator 282, it is not limited to this. For example, the heat treatment can be performed after the formation of transistor layer 413 or after the formation of memory device layers 415_1 to 415_3. Furthermore, when hydrogen is diffused to the outside by the above-described heat treatment, the hydrogen is diffused to the top or lateral direction of transistor layer 413. Similarly, when the heat treatment is performed after the formation of memory device layers 415_1 to 415_3, the hydrogen diffuses to the top or lateral direction.

[0316] In addition, the above manufacturing process produces the sealing structure formed by bonding insulator 211 and insulator 283 together.

[0317] As described above, by employing the above structure and manufacturing process, a semiconductor device using an oxide semiconductor with reduced hydrogen concentration can be provided. Therefore, a semiconductor device with high reliability can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with excellent electrical characteristics can be provided.

[0318] Figures 18A to 18C The configuration of conductor 424 is shown. Figure 17 Diagrams showing different examples. Figure 18A This shows a layout diagram of the storage device 420 as viewed from the top. Figure 18B Shown in Figure 18A The cross-sectional view of the portion indicated by the dashed lines A1-A2. Figure 18C Shown in Figure 18A The cross-sectional view shows the portion indicated by the dashed lines B1-B2. Additionally, in... Figure 18A For clarity, conductor 205 is omitted. When conductor 205 is provided, conductor 205 includes a region that overlaps with conductor 260 and conductor 424.

[0319] like Figure 18A As shown, an opening for the conductor 424 is provided, meaning that the conductor 424, in addition to overlapping the regions of oxides 230a and 230b, is also disposed on the outer side of oxides 230a and 230b. Figure 18A The illustration shows an example in which the conductor 424 protrudes to the B2 side of oxides 230a and 230b; however, this embodiment is not limited to this. The conductor 424 may be provided in a manner that protrudes to the B1 side of oxides 230a and 230b, or it may be provided in a manner that protrudes to both the B1 side and the B2 side.

[0320] Figure 18B and Figure 18C An example is shown where a memory device layer 415_p is stacked on top of a memory device layer 415_p-1 (p is a natural number greater than 2 and less than n). The memory device 420 included in the memory device layer 415_p-1 is electrically connected to the memory device 420 included in the memory device layer 415_p via conductors 424 and 205.

[0321] Figure 18B An example is shown in which conductor 424 in storage device layer 415_p-1 is connected to conductor 242 in storage device layer 415_p-1 and conductor 205 in storage device layer 415_p. Here, conductor 424 is connected to conductor 205 in storage device layer 415_p-1 on the outer side of conductor 242, oxide 243, oxide 230b, and oxide 230a on the B2 side.

[0322] exist Figure 18C In this configuration, conductor 424 is formed along the side of conductor 242, oxide 243, oxide 230b, and oxide 230a on the B2 side, and is electrically connected to conductor 205 through openings formed in insulators 280, 273, 272, 224, and 222. Here, in... Figure 18B In the diagram, a dotted line shows an example where conductor 424 is formed along the side surface of conductor 242, oxide 243, oxide 230b, and oxide 230a on the B2 side. Additionally, sometimes an insulator 241 is formed between conductor 242, oxide 243, oxide 230b, oxide 230a, insulator 224, the side surface of insulator 222 on the B2 side, and conductor 424.

[0323] By providing conductors 424 in areas that do not overlap with conductors 242, the storage device 420 can be electrically connected to storage devices 420 disposed in different storage device layers 415. Alternatively, the storage device 420 can also be electrically connected to transistors 200T disposed in transistor layer 413.

[0324] Furthermore, when conductor 424 is used as a bit line, by also providing conductor 424 in a region that does not overlap with conductor 242, the distance between bit lines of adjacent memory devices 420 in the B1-B2 direction can be increased. For example... Figure 18A As shown, the distance between conductors 424 on conductor 242 is d1, but the distance between conductors 424 in the layer below oxide 230a, i.e., in the opening formed by insulator 224 and insulator 222, is d2. Therefore, d2 is larger than d1. Compared to the case where the distance between adjacent conductors 424 in the B1-B2 direction is d1, setting a portion of the distance to d2 can reduce the parasitic capacitance of conductors 424. By reducing the parasitic capacitance of conductors 424, the capacitance required for capacitor element 292 can be reduced, which is preferable.

[0325] A conductor 424, serving as a common bit line for two memory cells, is provided in the memory device 420. By appropriately adjusting the dielectric constant of the dielectric or the parasitic capacitance between the bit lines, the cell size of each memory cell can be reduced. Here, estimations of the cell size, bit density, and bit cost of a memory cell with a channel length of 30 nm (also known as the 30 nm node) are explained. Furthermore, the following explanation... Figures 19A to 19D For clarity, conductor 205 is omitted. When conductor 205 is provided, conductor 205 includes a region that overlaps with conductor 260 and conductor 424.

[0326] exist Figure 19A The diagram shows an example of a dielectric material used as a capacitor element, consisting of a 10 nm thick layer of hafnium oxide and a 1 nm thick layer of silicon oxide stacked sequentially. A slit is formed between the conductors 242, oxide 243, oxide 230a, and oxide 230b of each memory cell included in the memory device 420, and a conductor 424, used as a bit line, is arranged in a manner overlapping the conductor 242 and the slit. The memory cell 432 obtained by this method is referred to as cell A.

[0327] The element size in element A is 45.25F. 2 .

[0328] exist Figure 19BThe diagram shows an example of a dielectric material serving as a capacitor element, consisting of a first zirconium oxide, an aluminum oxide layer thereon, and a second zirconium oxide layer thereon, stacked sequentially. A slit is formed between the conductors 242, oxide 243, oxide 230a, and oxide 230b of each memory cell included in the memory device 420, and a conductor 424, used as a bit line, is arranged in a manner overlapping the conductor 242 and the slit. The memory cell 433 obtained in this way is referred to as cell B.

[0329] Because the dielectric constant of the capacitor element in cell B is higher than that in cell A, the area of ​​the capacitor element can be reduced. Therefore, the cell size in cell B can be reduced compared to cell A. The cell size in cell B is 25.53F. 2 .

[0330] Unit A and Unit B correspond to Figure 13 , Figures 15A to 15C and Figure 16 The storage units included in the storage device 420, storage device 420A or storage device 420B shown.

[0331] exist Figure 19C The diagram shows a dielectric material serving as a capacitor element, consisting of a first zirconium oxide, an aluminum oxide layer thereon, and a second zirconium oxide layer thereon, stacked sequentially. Each memory cell shares the conductor 242, oxide 243, oxide 230a, and oxide 230b included in the memory device 420. An example is shown where the conductor 424, used as a bit line, is arranged such that it overlaps with a portion of the conductor 242 and a portion of the outer side of the conductor 242. The memory cell 434 obtained in this manner is referred to as cell C.

[0332] Compared to the layer above conductor 242, the distance between conductors 424 in cell C, below oxide 230a, is greater. Therefore, the parasitic capacitance of conductor 424 can be reduced, and the area of ​​the capacitor element can be decreased. Furthermore, no slits are formed between conductors 242, oxide 243, oxide 230a, and oxide 230b. Thus, cell C can have a smaller cell size compared to cells A and B. The cell size in cell C is 17.20F. 2 .

[0333] exist Figure 19D The diagram shows an example where the conductor 205 and the insulator 216 are not provided in cell C. This type of storage cell 435 is referred to as cell D.

[0334] By omitting the conductor 205 and insulator 216 in cell D, the thickness of the memory device 420 can be reduced. Therefore, the memory device layer 415 including the memory device 420 can be thinned, and the height of the memory cell 470, which consists of multiple stacked memory device layers 415, can be reduced. When the conductor 424 and conductor 205 are considered as bit lines, the bit lines in the memory cell 470 can be shortened. Because the bit lines can be shortened, the parasitic load on the bit lines is reduced, thereby further reducing the parasitic capacitance of the conductor 424, and the area of ​​the capacitor element can be reduced. Furthermore, no slits are formed in the conductor 242, oxide 243, oxide 230a, and oxide 230b. Therefore, compared to cells A, B, and C, cell D can have a smaller cell size. The cell size in cell D is 15.12F. 2 .

[0335] Units C and D correspond to Figures 18A to 18C The storage unit included in the storage device 420 shown.

[0336] Here, the bit density and bit cost C of cells A to D, and cell E in cell D that is multivalued, are estimated. b Furthermore, the obtained estimates are compared with the estimated bit density and bit cost of currently commercially available DRAM.

[0337] The bit cost C in a semiconductor device according to one aspect of the present invention is estimated using Equation 1. b .

[0338] [Equation 1]

[0339]

[0340] Here, n represents the number of stacked storage device layers, P c The common part mainly represents the patterning number of element layer 411, P s This represents the number of patterning iterations and D for each of the memory device layer 415 and the transistor layer 413. d Indicates the bit density of DRAM, D 3d This represents the bit density of a memory device layer 415, P d This indicates the number of patterning iterations in the DRAM. Note that P... d This includes any increase that occurs due to reduction.

[0341] Table 1 shows estimated bit densities of commercially available DRAMs and estimated bit densities of a semiconductor device according to one embodiment of the present invention. Furthermore, the commercially available DRAMs are available in two process nodes: 18nm and 1Xnm. Additionally, the bit density of a semiconductor device according to one embodiment of the present invention is estimated under the following conditions: a process node of 30nm, and the number of memory device layers stacked in cells A to E being 5, 10, and 20 layers, respectively.

[0342] [Table 1]

[0343]

[0344] Table 2 shows the results of estimating the relative bit cost of a semiconductor device according to one aspect of the present invention based on the bit cost of commercially available DRAM. Note that DRAM with a process node of 1Xnm is used in the bit cost comparison. In addition, the relative bit cost of a semiconductor device according to one aspect of the present invention is estimated under the following conditions: process node of 30nm, and the number of stacked memory device layers in cells A to D is 5, 10, and 20 layers, respectively.

[0345] [Table 2]

[0346]

[0347] The structure shown in this embodiment can be implemented by appropriately combining it with structures described in other embodiments, etc.

[0348] (Implementation Method 3)

[0349] In this embodiment, the configurations of CAC-OS (Cloud-Aligned Composite Oxide Semiconductor) and CAAC-OS (c-axis Aligned Crystal Oxide Semiconductor), which are metal oxides that can be used as OS transistors described in the above embodiments, will be described.

[0350] <Composition of Metal Oxides>

[0351] CAC-OS or CAC-metal oxide possesses conductive properties in one part of the material and insulating properties in another, thus functioning as a semiconductor as a whole. Furthermore, when CAC-OS or CAC-metal oxide is used as the active layer of a transistor, the conductive function allows electrons (or holes) used as charge carriers to flow through, while the insulating function prevents electrons from flowing through. Through the complementary effects of conductive and insulating functions, CAC-OS or CAC-metal oxide can possess switching functions (on / off functionality). By separating these functions within CAC-OS or CAC-metal oxide, each function can be maximized.

[0352] Furthermore, CAC-OS or CAC-metal oxide comprises conductive and insulating regions. The conductive regions possess the aforementioned conductive function, and the insulating regions possess the aforementioned insulating function. Moreover, in the material, the conductive and insulating regions are sometimes separated at the nanoparticle level. Additionally, the conductive and insulating regions are sometimes unevenly distributed within the material. Furthermore, conductive regions with blurred edges and cloud-like connections are sometimes observed.

[0353] Furthermore, in CAC-OS or CAC-metal oxide, conductive and insulating regions are sometimes dispersed in the material at a size of 0.5 nm or more and 10 nm or less, preferably 0.5 nm or more and 3 nm or less.

[0354] Furthermore, CAC-OS or CAC-metal oxide is composed of components with different band gaps. For example, CAC-OS or CAC-metal oxide is composed of a component with a wide gap originating from an insulating region and a component with a narrow gap originating from a conductive region. In this structure, when charge carriers flow through, they mainly flow through the component with the narrow gap. Moreover, the component with the narrow gap, through complementary interaction with the component with the wide gap, causes charge carriers to flow through the component with the wide gap. Therefore, when the above-mentioned CAC-OS or CAC-metal oxide is used in the channel formation region of a transistor, a high current driving force, i.e., a large on-state current and a high field-effect mobility, can be obtained in the transistor's on-state.

[0355] In other words, CAC-OS or CAC-metal oxide can also be referred to as matrix composite or metal matrix composite.

[0356] <Structure of Metal Oxides>

[0357] Oxide semiconductors are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include CAAC-OS (c-axis aligned crystalline oxide semiconductor), polycrystalline oxide semiconductors, nc-OS (nanocrystalline oxide semiconductor), a-like OS (amorphous-like oxide semiconductor), and amorphous oxide semiconductors.

[0358] Furthermore, when considering crystal structure, oxide semiconductors sometimes belong to a different category than those described above. Here, refer to... Figure 20A Explain the classification of crystal structures in oxide semiconductors. Figure 20A This diagram illustrates the classification of crystal structures of oxide semiconductors, typically IGZO (a metal oxide containing In, Ga, and Zn).

[0359] like Figure 20A As shown, IGZO is broadly classified into Amorphous, Crystalline, and Crystal. Amorphous includes completely amorphous. Crystalline includes CAAC (c-axis aligned crystalline), nc (nanocrystalline), and CAC (Cloud-Aligned Composite). Crystal includes single crystal and poly crystal.

[0360] Figure 20A The structure shown in the thick box belongs to the New crystalline phase. This structure is located in the boundary region between Amorphous and Crystalline. In other words, Crystalline can be considered completely different from the energetically unstable Amorphous.

[0361] X-ray diffraction (XRD) patterns can be used to evaluate the crystal structure of films or substrates. Here, Figure 20B , Figure 20C The XRD spectra of quartz glass and IGZO (also known as Crystalline IGZO) with a crystal structure classified as Crystalline are shown. Figure 20B It is the XRD spectrum of quartz glass. Figure 20CThis is the XRD pattern of crystalline IGZO. Figure 20C The crystalline IGZO shown has an In:Ga:Zn ratio of 4:2:3 [atomic number ratio]. Figure 20C The thickness of the crystalline IGZO shown is 500 nm.

[0362] like Figure 20B As indicated by the arrows, the XRD peaks of quartz glass are roughly symmetrical. On the other hand, as... Figure 20C As indicated by the arrow, the XRD peaks of crystalline IGZO are asymmetrical. Asymmetrical XRD peaks clearly indicate the presence of crystals. In other words, unless the XRD peaks are symmetrical, it cannot be considered amorphous.

[0363] CAAC-OS exhibits c-axis orientation, with multiple nanocrystals linked along the ab-plane direction, and its crystal structure is distorted. Note that distortion refers to the portion of the lattice alignment direction that changes between regions with consistent lattice alignment and other regions with consistent lattice alignment within the region where multiple nanocrystals are linked.

[0364] Although nanocrystals are primarily hexagonal, they are not limited to regular hexagons and can be non-regular hexagonal. Furthermore, pentagonal or heptagonal lattice arrangements are sometimes observed in the distortion. Additionally, in CAAC-OS, no distinct grain boundaries are observed even near the distortion. That is, it is known that grain boundary formation is suppressed due to lattice arrangement distortion. This is because CAAC-OS can contain distortion due to the low density of oxygen atoms in the ab-plane direction or changes in interatomic bonding distance caused by metal element substitution. Crystalline structures with clearly defined grain boundaries are called polycrystals. Grain boundaries are primarily recombination sites, increasing the likelihood of carrier trapping and a decrease in transistor on-state current or electric field mobility. Therefore, CAAC-OS without clearly observed grain boundaries is one type of crystalline oxide with an appropriate crystalline structure in the semiconductor layer of the transistor. For the construction of CAAC-OS, a structure containing Zn is preferred. For example, In-Zn oxides and In-Ga-Zn oxides suppress the formation of grain boundaries compared to In oxides, so they are preferred.

[0365] CAAC-OS tends to have a layered crystalline structure (also called a layered structure), in which layers containing indium and oxygen (hereinafter referred to as In layers) and layers containing elements M, zinc, and oxygen (hereinafter referred to as (M, Zn) layers) are stacked. Furthermore, indium and element M can substitute for each other; when element M in a (M, Zn) layer is replaced by indium, the layer can also be represented as an (In, M, Zn) layer. Similarly, when indium in an In layer is replaced by element M, the layer can also be represented as an (In, M) layer.

[0366] CAAC-OS is a highly crystalline oxide semiconductor. Furthermore, no distinct grain boundaries are observed in CAAC-OS, thus reducing the likelihood of decreased electron mobility due to grain boundaries. Moreover, the crystallinity of oxide semiconductors can sometimes decrease due to the introduction of impurities or the formation of defects; therefore, CAAC-OS can be considered an oxide semiconductor with few impurities or defects (such as oxygen vacancies). Consequently, oxide semiconductors containing CAAC-OS exhibit stable physical properties. Thus, oxide semiconductors containing CAAC-OS possess high heat resistance and high reliability. Furthermore, CAAC-OS is also stable against high temperatures (so-called thermal accumulation) during manufacturing processes. Therefore, by using CAAC-OS in OS transistors, the degrees of freedom in manufacturing processes can be increased.

[0367] In nc-OS, the atomic arrangement in tiny regions (e.g., regions above 1 nm and below 10 nm, particularly above 1 nm and below 3 nm) exhibits periodicity. Furthermore, no regularity in crystal orientation is observed between different nanocrystals in nc-OS. Therefore, no orientation is observed in the overall film. Thus, sometimes nc-OS is indistinguishable from a-like OS or amorphous oxide semiconductors in certain analytical methods.

[0368] a-like OS is an oxide semiconductor with a structure intermediate between nc-OS and amorphous oxide semiconductors. A-like OS contains voids or low-density regions. In other words, a-like OS has lower crystallinity than nc-OS and CAAC-OS.

[0369] Oxide semiconductors possess various structures and properties. One embodiment of the present invention may also include two or more of amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, nc-OS, and CAAC-OS.

[0370] Transistors with oxide semiconductors

[0371] Next, we will explain the application of the aforementioned oxide semiconductor in transistors.

[0372] By using the aforementioned oxide semiconductors in transistors, transistors with high field-effect mobility can be realized. Furthermore, transistors with high reliability can also be achieved.

[0373] Furthermore, it is preferable to use oxide semiconductors with low carrier concentrations in transistors. When it is necessary to reduce the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film can be reduced to decrease the defect state density. In this specification, the state of low impurity concentration and low defect state density is referred to as high-purity intrinsic or substantially high-purity intrinsic.

[0374] Furthermore, high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor films have a lower defect state density, and therefore sometimes a lower trap state density.

[0375] Furthermore, the charge trapped in the trap levels of oxide semiconductors takes a relatively long time to dissipate, sometimes acting like a fixed charge. Therefore, the electrical characteristics of transistors with channel formation regions formed in oxide semiconductors with high trap state density are sometimes unstable.

[0376] Therefore, reducing the impurity concentration in the oxide semiconductor is effective in stabilizing the electrical characteristics of the transistor. To further reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0377] <Impurities>

[0378] Here, we will explain the effects of various impurities in oxide semiconductors.

[0379] When an oxide semiconductor contains silicon or carbon, one of Group 14 elements, defect energy levels are formed in the oxide semiconductor. Therefore, the concentration of silicon or carbon in or near the interface of the oxide semiconductor (the concentration measured by secondary ion mass spectrometry (SIMS)) is set to 2 × 10⁻⁶. 18 atoms / cm 3 The following is preferred: 2×10 17 atoms / cm 3 the following.

[0380] Furthermore, when oxide semiconductors contain alkali metals or alkaline earth metals, defect energy levels can sometimes form, leading to the formation of charge carriers. Therefore, transistors using oxide semiconductors containing alkali metals or alkaline earth metals tend to exhibit always-on characteristics. Consequently, it is preferable to reduce the concentration of alkali metals or alkaline earth metals in the oxide semiconductor. Specifically, the concentration of alkali metals or alkaline earth metals in the oxide semiconductor, as measured by SIMS, should be 1 × 10⁻⁶. 18 atoms / cm3 The following is preferred: 2×10 16 atoms / cm 3 the following.

[0381] When oxide semiconductors contain nitrogen, electrons are readily generated as charge carriers, increasing the charge carrier concentration and resulting in n-type characteristics. Consequently, transistors using nitrogen-containing oxide semiconductors tend to exhibit always-on characteristics. Therefore, it is preferable to minimize the nitrogen content in the oxide semiconductor as much as possible; for example, the nitrogen concentration in the oxide semiconductor measured using SIMS should be below 5 × 10⁻⁶. 19 atoms / cm 3 Preferably 5×10 18 atoms / cm 3 Hereinafter, 1×10 is more preferred. 18 atoms / cm 3 The following is a further preferred option: 5×10 17 atoms / cm 3 the following.

[0382] Hydrogen contained in oxide semiconductors reacts with oxygen bonded to metal atoms to form water, thus sometimes creating oxygen vacancies. When hydrogen enters these oxygen vacancies, electrons are sometimes generated as charge carriers. Additionally, sometimes a portion of the hydrogen bonds with oxygen bonded to metal atoms, generating electrons as charge carriers. Therefore, transistors using oxide semiconductors containing hydrogen tend to have always-on characteristics. Thus, it is preferable to minimize the amount of hydrogen in the oxide semiconductor. Specifically, in the oxide semiconductor, the hydrogen concentration, as measured by SIMS, is set to be less than 1 × 10⁻⁶. 20 atoms / cm 3 Preferably less than 1×10 19 atoms / cm 3 More preferably, less than 5×10 18 atoms / cm 3 Further optimization of less than 1×10 18 atoms / cm 3 .

[0383] By using oxide semiconductors with sufficiently reduced impurities in the channel formation region of a transistor, the transistor can have stable electrical characteristics.

[0384] This embodiment can be appropriately combined with other embodiments shown in this specification.

[0385] (Implementation Method 4)

[0386] In this embodiment, the detailed contents of the control logic circuit 61, row drive circuit 62, column drive circuit 63 and output circuit 64 disposed on the silicon substrate 60 in the semiconductor device 10 described in Embodiment 1 will be explained.

[0387] Figure 21 This is a block diagram illustrating an example structure of a semiconductor device used as a memory device. The semiconductor device 10E includes peripheral circuitry 80 and a memory cell array 70. The peripheral circuitry 80 includes control logic circuitry 61, row drive circuitry 62, column drive circuitry 63, and output circuitry 64.

[0388] The memory cell array 70 includes multiple memory cells 33. The row driving circuit 62 includes a row decoder 71 and a word line driving circuit 72. The column driving circuit 63 includes a column decoder 81, a precharge circuit 82, an amplifier circuit 83, and a write circuit 84. The precharge circuit 82 precharges the global bit line (GBL) and local bit lines (LBL). The amplifier circuit 83 amplifies the data signal read from the global bit line (GBL) or local bit line (LBL). The amplified data signal is output as a digital data signal RDATA to the outside of the semiconductor device 10E via the output circuit 64.

[0389] The semiconductor device 10E is supplied with a low power supply voltage (VSS) as the power supply voltage, the peripheral circuit 80 is supplied with a high power supply voltage (VDD) and the memory cell array 70 is supplied with a high power supply voltage (VIL) from the outside.

[0390] The semiconductor device 10E receives external control signals (CE, WE, RE), address signal ADDR, and data signal WDATA. The address signal ADDR is input to the row decoder 71 and the column decoder 81, and the WDATA is input to the write circuit 84.

[0391] The control logic circuit 61 processes external input signals (CE, WE, RE) to generate control signals for the row decoder 71 and column decoder 81. CE is the chip enable signal, WE is the write enable signal, and RE is the read enable signal. The signals processed by the control logic circuit 61 are not limited to these; other control signals can be input as needed. For example, a control signal used to determine faulty bits can be input to identify the data signal read from a specific memory cell address as a faulty bit.

[0392] The circuits or signals mentioned above can be used appropriately as needed.

[0393] Generally speaking, as semiconductor devices in computers and the like, various storage devices (memory) can be used depending on their application. Figure 22This illustrates the hierarchy of various storage devices. Higher-level storage devices require faster access speeds, while lower-level devices require larger storage capacities and higher recording densities. Figure 22 In the middle, from the top layer, are the memory installed as registers in the CPU and other computing devices, SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), and 3D NAND memory.

[0394] Because memory installed along with registers in arithmetic processing devices such as CPUs is used for temporary storage of calculation results, it is accessed frequently by the arithmetic processing device. Therefore, a faster operating speed than storage capacitors is required. Furthermore, registers also have the function of holding settings information of the arithmetic processing device.

[0395] SRAM is used, for example, in caches. A cache has the function of copying and maintaining a portion of the information that is kept in main memory. By copying frequently used data into the cache, the speed of data access can be improved.

[0396] DRAM is used, for example, in main memory. Main memory has the function of holding programs or data read from storage. The recording density of DRAM is approximately 0.1 to 0.3 Gbit / mm². 2 .

[0397] 3D NAND flash memory is used for storage, for example. Storage devices have the function of holding data that needs to be preserved for a long time and various programs used by computing devices. Therefore, compared to faster operating speeds, storage requires larger storage capacitors and higher recording densities. The recording density of storage devices used for storage is approximately 0.6 to 6.0 Gbit / mm². 2 .

[0398] The semiconductor device used as a storage device according to one aspect of the present invention operates at high speed and is capable of retaining data for long periods. The semiconductor device according to one aspect of the present invention can be used as a semiconductor device located in the boundary region 901 between the cache layer and the main memory layer. Furthermore, the semiconductor device according to one aspect of the present invention can be used as a semiconductor device located in the boundary region 902 between the main memory layer and the storage layer.

[0399] (Implementation Method 5)

[0400] This embodiment shows an example of an electronic component and electronic device equipped with the semiconductor device or the like described in the above embodiment.

[0401] <Electronic Components>

[0402] First, refer to Figure 23A and Figure 23B An example of an electronic component assembled with a semiconductor device 10, etc., will be described.

[0403] Figure 23A A perspective view of the electronic component 700 and the substrate (mounting substrate 704) on which the electronic component 700 is mounted is shown. Figure 23A The electronic component 700 shown includes a semiconductor device 10 with a layer of elements 50 stacked on a silicon substrate 60 in mold 711. Figure 23A To show the interior of the electronic component 700, a portion of it is omitted in the accompanying drawings. The electronic component 700 includes a connection land 712 on the outside of the mold 711. The connection land 712 is electrically connected to electrode pads 713, which are electrically connected to the semiconductor device 10 via wires 714. The electronic component 700 is mounted, for example, on a printed circuit board 702. By combining multiple such electronic components and electrically connecting them individually on the printed circuit board 702, a mounting substrate 704 is thus completed.

[0404] Figure 23B A perspective view of electronic component 730 is shown. Electronic component 730 is an example of SiP (System in Package) or MCM (Multi-Chip Module). In electronic component 730, an interposer 731 is provided on a package substrate 732 (printed circuit board), and semiconductor devices 735 and multiple semiconductor devices 10 are provided on the interposer 731.

[0405] An example of using semiconductor device 10 as high-bandwidth memory (HBM) is shown in electronic component 730. Alternatively, semiconductor device 735 can use integrated circuits (semiconductor devices) such as CPUs, GPUs, and FPGAs.

[0406] The packaging substrate 732 can be a ceramic substrate, a plastic substrate, or a glass epoxy substrate, etc. The through-hole board 731 can be a silicon through-hole board, a resin through-hole board, etc.

[0407] The through-hole board 731 includes multiple wirings and has multiple integrated circuits with different electrical connection terminal spacings. The multiple wirings are composed of a single layer or multiple layers. Furthermore, the through-hole board 731 has the function of electrically connecting the integrated circuits disposed on the through-hole board 731 to electrodes disposed on the package substrate 732. Therefore, the through-hole board is sometimes referred to as a "rewiring substrate" or "intermediate substrate". Additionally, sometimes a through electrode is provided in the through-hole board 731 to electrically connect the integrated circuit to the package substrate 732. Furthermore, in the case of using a silicon through-hole board, a TSV (Through Silicon Via) can also be used as the through electrode.

[0408] Silicon interposers are preferably used as the interposer 731. Since silicon interposers do not require active components, they can be manufactured at a lower cost than integrated circuits. On the other hand, the wiring of silicon interposers can be formed in semiconductor processes, making it easy to form fine wiring that is difficult to form when using resin interposers.

[0409] In HBM, numerous wirings are required to achieve wide memory bandwidth. Therefore, the mounting board for HBM must be capable of forming fine wirings at high density. Consequently, silicon mounting boards are preferred as mounting boards for HBM.

[0410] Furthermore, in SiP or MCM applications using silicon interposers, reliability degradation due to differences in the coefficients of thermal expansion between the integrated circuit and the interposer is less likely to occur. Additionally, due to the high surface flatness of the silicon interposer, poor connection between the integrated circuit and the interposer is less likely to occur. Silicon interposers are particularly preferred for 2.5D packages (2.5D mounting) in which multiple integrated circuits are arranged side-by-side on the interposer.

[0411] Alternatively, a heat sink (heat plate) may be provided overlapping with the electronic component 730. When a heat sink is provided, it is preferable that the integrated circuits provided on the insert 731 have the same height. For example, in the electronic component 730 shown in this embodiment, it is preferable that the semiconductor device 10 and the semiconductor device 735 have the same height.

[0412] In order to mount the electronic component 730 on other substrates, an electrode 733 can be provided on the bottom of the package substrate 732. Figure 23B An example of forming electrode 733 using solder balls is shown. BGA (Ball Grid Array) mounting can be achieved by arranging solder balls in a matrix on the bottom of the package substrate 732. Alternatively, electrode 733 can also be formed using conductive pins. PGA (Pin Grid Array) mounting can be achieved by arranging conductive pins in a matrix on the bottom of the package substrate 732.

[0413] Electronic component 730 can be mounted on other substrates using various mounting methods, not limited to BGA and PGA. For example, it can be mounted using SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), or QFN (Quad Flat Non-leaded package).

[0414] <Electronic Devices>

[0415] Next, refer to Figure 24 Examples of electronic devices equipped with the aforementioned electronic components will be described.

[0416] Robot 7100 includes an illuminance sensor, microphone, camera, speaker, display, various sensors (infrared sensor, ultrasonic sensor, accelerometer, piezoelectric sensor, light sensor, gyroscope sensor, etc.) and a movement mechanism. Electronic component 730 includes a processor and has the function of controlling these peripheral devices. For example, electronic component 700 has the function of storing data measured by the sensors.

[0417] The microphone detects audio signals such as the user's voice and ambient sounds. The speaker emits audio signals such as sounds and warning tones. Robot 7100 can analyze the audio signals input through the microphone and emit the necessary audio signals from the speaker. Robot 7100 can communicate with the user using both the microphone and speaker.

[0418] The camera has the function of capturing images of the surroundings of robot 7100. Additionally, robot 7100 has the function of moving using a locomotion mechanism. Robot 7100 can analyze the images captured by the camera to determine the presence or absence of obstacles during movement.

[0419] The flying object 7120 includes a propeller, camera, and battery, and has autonomous flight capabilities. The electronic component 730 has the function of controlling these peripheral devices.

[0420] For example, image data captured by a camera is stored in electronic component 700. Electronic component 730 can analyze the image data to determine the presence or absence of obstacles during movement. Furthermore, electronic component 730 can use changes in battery capacity to estimate the remaining battery power.

[0421] The 7140 robotic vacuum cleaner includes a display on the top, multiple cameras on the sides, brushes, control buttons, and various sensors. Although not shown, the 7300 robotic vacuum cleaner is equipped with tires and a suction inlet. The 7300 can move automatically, detect debris, and suck it up from the suction inlet on the bottom.

[0422] For example, the electronic component 730 can determine the presence or absence of obstacles such as walls, furniture, or steps by analyzing images captured by a camera. Furthermore, if image analysis detects objects such as wiring that might become entangled in the brush, the brush's rotation can be stopped.

[0423] The vehicle 7160 includes an engine, tires, brakes, steering system, cameras, etc. For example, the electronic component 730 performs optimized control of the vehicle 7160's driving state based on data such as navigation information, speed, engine status, gear selection status, and brake usage frequency. For example, image data captured by the camera is stored in the electronic component 700.

[0424] Electronic components 700 and / or 730 can be installed in television receiver (TV) devices 7200, smartphones 7210, PCs (personal computers) 7220, 7230, game consoles 7240, game consoles 7260, etc.

[0425] For example, the electronic component 730 disposed within the TV device 7200 can be used as an image engine. For example, the electronic component 730 can perform image processing such as noise removal and resolution up-conversion.

[0426] Smartphone 7210 is an example of a portable information terminal. Smartphone 7210 includes a microphone, camera, speaker, various sensors, and a display. Electronic components 730 control these peripheral devices.

[0427] PC7220 and PC7230 are examples of a notebook PC and a desktop PC, respectively. A keyboard 7232 and a display device 7233 can be connected to PC7230 wirelessly or via a wired connection. Game console 7240 is an example of a portable game console. Game console 7260 is an example of a stationary game console. Game console 7260 connects to controller 7262 wirelessly or via a wired connection. Electronic components 700 and / or 730 can be installed on controller 7262.

[0428] This embodiment can be implemented by appropriately combining the structures described in other embodiments, etc.

[0429] (Notes regarding the contents of this instruction manual, etc.)

[0430] Below, additional notes are added to the descriptions of the above embodiments and the structures in those embodiments.

[0431] The structures shown in each embodiment can be appropriately combined with the structures shown in other embodiments or examples to constitute a mode of the present invention. Furthermore, when multiple structural examples are shown in one embodiment, these structural examples can be appropriately combined.

[0432] In addition, the content (or a portion thereof) described in one embodiment may be applied / combined / replaced with other content (or a portion thereof) described in that embodiment and / or content (or a portion thereof) described in one or more other embodiments.

[0433] Note that the content described in the embodiments refers to the content illustrated using various accompanying drawings or the content described using the text in the specification.

[0434] Furthermore, more figures can be formed by combining the figures (or portions thereof) shown in one embodiment with other portions of the figures, other figures (or portions thereof) shown in that embodiment, and / or figures (or portions thereof) shown in one or more other embodiments.

[0435] In this specification, components are categorized according to function and represented by independent boxes in block diagrams. However, in actual circuits, it is difficult to categorize components according to function; sometimes a circuit involves multiple functions or multiple circuits involve a single function. Therefore, the division of boxes in block diagrams is not limited to the components described in the specification and may vary appropriately depending on the circumstances.

[0436] For ease of explanation, dimensions, layer thicknesses, or regions are arbitrarily shown in the accompanying drawings. Therefore, the invention is not limited to the dimensions shown in the drawings. The drawings are schematic for clarity and are not limited to the shapes or values ​​shown in the drawings. For example, they may include non-uniformity of signals, voltages, or currents caused by noise or timing deviations.

[0437] Furthermore, the positional relationships of the constituent elements shown in the accompanying drawings are relative. Therefore, when describing the constituent elements with reference to the accompanying drawings, terms such as "upper" and "lower" indicating positional relationships are sometimes used for convenience. The positional relationships of the constituent elements are not limited to those described in this specification, and the terms may be appropriately changed as needed.

[0438] In this specification and other materials, when describing the connection relationship of transistors, the terms "one of the source and drain" (first electrode or first terminal) and "the other of the source and drain" (second electrode or second terminal) are used. This is because the source and drain of a transistor may vary depending on the transistor's structure or operating conditions. Note that, depending on the circumstances, the source and drain of a transistor may be appropriately referred to as source (drain) terminals or source (drain) electrodes, etc.

[0439] Furthermore, in this specification and the like, "electrode" or "wiring" does not functionally limit its constituent elements. For example, sometimes an "electrode" is used as part of a "wiring," and vice versa. Moreover, "electrode" or "wiring" also includes cases where multiple "electrodes" or "wiring" are formed as a single unit.

[0440] Additionally, voltage and potential can be interchanged appropriately in this instruction manual and other documents. Voltage refers to the potential difference from a reference potential; for example, when the reference potential is ground voltage (grounding voltage), voltage can also be referred to as potential. Grounding potential does not necessarily mean 0V. Note that potential is relative, and the potential supplied to wiring, etc., sometimes varies according to the reference potential.

[0441] In this specification and other materials, nodes may also be referred to as terminals, wiring, electrodes, conductive layers, conductors, or impurity regions, depending on the circuit structure or device structure. Additionally, terminals and wiring may also be referred to as nodes.

[0442] In this specification, A and B connection refers to A and B being electrically connected. Here, A and B electrical connection means a connection that allows the transmission of electrical signals between A and B when there is an object (a switch, transistor, diode, or other similar element, or a circuit containing such an element and wiring) between A and B. Note that A and B electrical connection includes the case of A and B being directly connected. Here, A and B direct connection means a connection where A and B can transmit electrical signals between them via wiring (or electrodes) without passing through the aforementioned object. In other words, direct connection means a connection that can be considered as the same circuit diagram when using equivalent circuit representation.

[0443] In this specification and the like, a switch refers to a component that controls whether current flows by changing to a conducting state (on state) or a non-conducting state (off state). Alternatively, a switch refers to a component that selects and switches current paths.

[0444] In this specification, for example, the channel length refers to the distance between the source and drain in the region where the semiconductor (or the portion of the semiconductor through which current flows when the transistor is in the on state) and the gate overlap or in the region forming the channel, in a top view of the transistor.

[0445] In this specification, for example, the channel width refers to the length of the portion of the semiconductor (or the portion of the semiconductor through which current flows when the transistor is in the on state) and the gate electrode that overlaps, or the portion of the source and drain electrodes opposite each other in the region that forms the channel.

[0446] In this specification and other materials, the terms "film" and "layer" may be interchanged depending on the situation or condition. For example, "conductive layer" may sometimes be replaced with "conductive film." Furthermore, "insulating film" may sometimes be replaced with "insulating layer."

[0447] [Symbol Explanation]

[0448] 10: Semiconductor device, 10A: Semiconductor device, 10B: Semiconductor device, 10C: Semiconductor device, 10E: Semiconductor device, 20: Transistor layer, 21: Switching circuit, 21_A: Switching circuit, 21_B: Switching circuit, 21_1: Transistor, 21_2: Transistor, 21_4: Transistor, 22: Amplifier circuit, 22_A: Amplifier circuit, 22_B: Amplifier circuit, 22_1: Transistor, 22_2: Transistor, 22_3: Transistor, 22_4: Transistor, 23_1: Transistor, 23_4: Transistor, 24_1: Transistor, 24_3: Transistor, 25_1: Transistor, 25_4: Transistor, 26_1: Transistor, 26_3: Transistor, 27 A: Switch, 27B: Switch, 27C: Switch, 27D: Switch, 30: Transistor layer, 31_k: Transistor layer, 31_1: Transistor layer, 31_2: Transistor layer, 32: Transistor layer, 32_k: Transistor layer, 32_1: Transistor layer, 32_2: Transistor layer, 33: Memory cell, 34: Transistor, 35: Capacitor, 40: Transistor layer, 41: Memory cell, 41A: Transistor layer, 41B: Transistor layer, 42: Transistor, 43: Transistor, 44: Capacitor, 50: Component layer, 50_M: Component layer, 50_1: Component layer, 60: Silicon substrate, 61: Control logic circuit, 62: Horizontal drive circuit, 62_A: Precharge circuit, 62_B: Precharge circuit 62_C: Readout Amplifier, 62_D: Switching Circuit, 62_E: Switching Circuit, 63: Column Driver Circuit, 64: Output Circuit, 65_1: Transistor, 65_3: Transistor, 65_4: Transistor, 65_6: Transistor, 66_A: Switch, 67_1: Transistor, 67_2: Transistor, 67_3: Transistor, 67_4: Transistor, 68_C: Switch, 69: Circuit, 70: Memory Cell Array, 71: Row Decoder, 72: Word Line Driver Circuit, 80: Peripheral Circuit, 81: Column Decoder, 82: Precharge Circuit, 83: Amplifier Circuit, 84: Circuit, 200: Transistor, 200M: Transistor, 200T: Transistor, 205: Conductor, 205a: Conductor, 205b: Conductor, 211: Insulator, 212: Insulator, 214: Insulator, 216: Insulator, 222: Insulator, 224: Insulator, 230: Oxide, 230a: Oxide, 230b: Oxide, 230c: Oxide, 240: Conductor, 240a: Conductor, 240b: Conductor, 241: Insulator, 241a: Insulator, 241b: Insulator, 242: Conductor, 242a: Conductor, 242b: Conductor, 243: Oxide, 243a: Oxide, 243b: Oxide, 246: Conductor, 246a: Conductor, 246b: Conductor, 250: Insulator, 260: Conductor, 260a: Conductor260b: Conductor, 272: Insulator, 273: Insulator, 274: Insulator, 275: Insulator, 276: Conductor, 277: Insulator, 278: Conductor, 279: Insulator, 280: Insulator, 282: Insulator, 283: Insulator, 284: Insulator, 287: Insulator, 290: Conductor, 292: Capacitive element, 292A: Capacitive element, 292B: Capacitive element, 294: Conductor, 295: Insulator, 296: Insulator, 297: Conductor, 298: Insulator, 299 300: Conductor; 311: Transistor; 313: Semiconductor substrate; 314a: Low-resistance region; 314b: Low-resistance region; 315: Insulator; 316: Conductor; 411: Component layer; 413: Transistor layer; 413_m: Transistor layer; 413_1: Transistor layer; 415: Memory device layer; 415_n: Memory device layer; 415_p: Memory device layer; 415_p-1: Memory device layer; 415_1: Memory device layer; 415_3: Memory device layer; 415_4: Memory device layer 420: Storage device; 420A: Storage device; 420B: Storage device; 422: Area; 424: Conductor; 426: Conductor; 428: Conductor; 430: Conductor; 432: Storage cell; 433: Storage cell; 434: Storage cell; 435: Storage cell; 470: Storage cell; 470_m: Storage cell; 470_1: Storage cell; 700: Electronic component; 702: Printed circuit board; 704: Circuit board; 711: Mold; 712: Connecting pad; 713: Electrode pad; 714 730: Wire; 731: Plug-in board; 732: Packaging substrate; 733: Electrode; 735: Semiconductor device; 901: Boundary area; 902: Boundary area; 7100: Robot; 7120: Flying object; 7140: Robotic vacuum cleaner; 7160: Automobile; 7200: TV device; 7210: Smartphone; 7220: PC; 7230: PC; 7232: Keyboard; 7233: Display device; 7240: Game console; 7260: Game console; 7262: Controller; 7300: Robotic vacuum cleaner.

Claims

1. A semiconductor device, comprising: A drive circuit having multiple transistors using a silicon substrate as a channel; as well as The first to third transistor layers have multiple transistors with metal oxide used for the channel. The first transistor layer includes a first memory cell having a first transistor and a first capacitor. The second transistor layer includes a second memory cell having a second transistor and a second capacitor. The third transistor layer includes a switching circuit and an amplification circuit. Both the switching circuit and the amplification circuit include transistors containing metal-oxide-semiconductor components in the channel formation region. The first transistor is electrically connected to the first local bit line. The second transistor is electrically connected to the second local bit line. The switching circuit is configured to select either the first local bit line or the second local bit line, and the selected local bit line is electrically connected to the amplifier circuit. The first transistor layer to the third transistor layer are disposed on the silicon substrate. Furthermore, the third transistor layer is disposed between the first transistor layer and the second transistor layer.

2. The semiconductor device of claim 1, wherein the first local bit line and the second local bit line are disposed in a direction perpendicular to or substantially perpendicular to the surface of the silicon substrate.

3. The semiconductor device of claim 2, further comprising a global bit line, wherein the global bit line is configured to electrically connect the amplification circuit to the driving circuit.

4. The semiconductor device of claim 3, wherein the global bit line is disposed in a direction perpendicular or substantially perpendicular to the surface of the silicon substrate.

5. The semiconductor device according to any one of claims 1, 2, and 4, wherein the metal oxide comprises In, Ga, and Zn.

6. The semiconductor device of claim 1, wherein the driving circuitry comprises at least one of a column driver, a row driver, a column decoder, a row decoder, a sense amplifier, a precharge circuit, a word line driver circuit, an output circuit, and a control logic circuit.

7. A semiconductor device, comprising: A drive circuit having multiple transistors using a silicon substrate as a channel; as well as A component layer having multiple transistor layers stacked on top of each other. The element layer includes a first transistor layer to a third transistor layer having a plurality of transistors with metal oxide used for the channel. The first transistor layer includes a first memory cell having a first transistor and a first capacitor. The second transistor layer includes a second memory cell having a second transistor and a second capacitor. The third transistor layer includes a switching circuit and an amplification circuit. Both the switching circuit and the amplification circuit include transistors containing metal-oxide-semiconductor components in the channel formation region. The first transistor is electrically connected to the first local bit line. The second transistor is electrically connected to the second local bit line. The switching circuit is configured to select either the first local bit line or the second local bit line, and the selected local bit line is electrically connected to the amplifier circuit. The components are stacked on the silicon substrate. Furthermore, the third transistor layer is disposed between the first transistor layer and the second transistor layer.

8. The semiconductor device of claim 7, wherein the first local bit line and the second local bit line are disposed in a direction perpendicular to or substantially perpendicular to the surface of the silicon substrate.

9. The semiconductor device of claim 8, further comprising a global bit line, wherein the global bit line is configured to electrically connect the amplification circuit to the driving circuit.

10. The semiconductor device of claim 9, wherein the global bit line is disposed in a direction perpendicular or substantially perpendicular to the surface of the silicon substrate.

11. The semiconductor device according to any one of claims 7, 8, and 10, wherein the metal oxide comprises In, Ga, and Zn.

12. The semiconductor device of claim 7, wherein the driving circuitry comprises at least one of a column driver, a row driver, a column decoder, a row decoder, a sense amplifier, a precharge circuit, a word line driver circuit, an output circuit, and a control logic circuitry.

13. An electronic device, comprising: The semiconductor device according to any one of claims 1 to 12; as well as At least one of the following: antenna, battery, operating switch, microphone, and speaker.

Images