Light emitting element and display device including the same

Abstract

A light emitting element may include an emission stacking pattern, the emission stacking pattern including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer stacked in one direction. Here, the active layer may include a first surface in contact with the first conductive semiconductor layer in the longitudinal direction of the emission stacking pattern and a second surface in contact with the second conductive semiconductor layer and opposite to the first surface at the same time. The first conductive semiconductor layer may include at least one n-type semiconductor layer, and the second conductive semiconductor layer may include at least one p-type semiconductor layer. In addition, the first surface of the active layer may be located within the emission stacking pattern at a point corresponding to a range of ‑20% to +20% deviation from half of the total length of the emission stacking pattern in the longitudinal direction of the emission stacking pattern.

Description

Technical Field

[0001] Various embodiments of the present disclosure relate to a light emitting element, and more particularly, to an ultra-small light emitting element and a display device having the ultra-small light emitting element. Background Art

[0002] Light emitting diodes (LEDs) may have relatively satisfactory durability even under adverse environmental conditions and may have excellent performance in terms of life span and brightness. Recently, research on technology for applying such LEDs to various display devices has become significantly more active.

[0003] As part of such research, a technology is being developed to manufacture LEDs having very small sizes corresponding to a range from micrometers to nanometers using an inorganic crystal structure (e.g., a structure obtained by growing a nitride-based semiconductor). The LEDs can be manufactured in sizes small enough to form pixels of a display panel, etc. After the LEDs are independently grown on a substrate, the grown LEDs can be separated and used to manufacture a display panel. Summary of the invention

[0004] Technical issues

[0005] An object of the present disclosure is to provide a light emitting element which places an active layer interposed between two semiconductor layers having different conductivities in the center in a longitudinal direction, thereby improving light emitting efficiency.

[0006] In addition, another object of the present disclosure is to provide a display device having the above-mentioned light-emitting element.

[0007] Technical Solution

[0008] According to an embodiment of the present disclosure, a light emitting element may include an emission stacking pattern including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer sequentially stacked in one direction. The active layer may include a first surface and a second surface, the first surface being in contact with the first conductive semiconductor layer in a longitudinal direction of the emission stacking pattern, and the second surface being opposite to the first surface and in contact with the second conductive semiconductor layer.

[0009] In an embodiment of the present disclosure, the first conductive semiconductor layer may include at least one n-type semiconductor layer, and the second conductive semiconductor layer may include at least one p-type semiconductor layer.

[0010] In an embodiment of the present disclosure, the first surface of the active layer may be located within the emission stack pattern at a point corresponding to a range of -20% to +20% deviation from half of the total length of the emission stack pattern in a longitudinal direction of the emission stack pattern.

[0011] In an embodiment of the present disclosure, a point corresponding to half of the total length of the emission stack pattern may be located between the first surface and the second surface of the active layer.

[0012] In an embodiment of the present disclosure, in a cross-sectional view, a distance from the first surface of the active layer to an upper surface of the second conductive semiconductor layer may be different from a distance from a lower surface of the first conductive semiconductor layer to an upper surface of the first conductive semiconductor layer in contact with the first surface of the active layer.

[0013] In an embodiment of the present disclosure, in a cross-sectional view, a distance from the first surface of the active layer to an upper surface of the second conductive semiconductor layer may be the same as a distance from a lower surface of the first conductive semiconductor layer to an upper surface of the first conductive semiconductor layer in contact with the first surface of the active layer.

[0014] In an embodiment of the present disclosure, the emission stack pattern may have a cylindrical shape in which the first conductive semiconductor layer, the active layer, and the second conductive semiconductor layer are sequentially stacked in a longitudinal direction of the emission stack pattern.

[0015] In an embodiment of the present disclosure, in a cross-sectional view, a ratio of a distance from the second surface of the active layer to an upper surface of the second conductive semiconductor layer to a total length of the emission stack pattern may be 0.5 or less.

[0016] In an embodiment of the present disclosure, the emission stack pattern may further include an electrode layer on the second conductive semiconductor layer. In a cross-sectional view, a ratio of a distance from the second surface of the active layer to an upper surface of the electrode layer to a total length of the emission stack pattern may be 0.5 or less.

[0017] In an embodiment of the present disclosure, the electrode layer may be thicker than the second conductive semiconductor layer in a longitudinal direction of the emission stack pattern, and may be thinner than the first conductive semiconductor layer in the longitudinal direction of the emission stack pattern.

[0018] In an embodiment of the present disclosure, in a cross-sectional view, a distance from the first surface of the active layer to an upper surface of the electrode layer may be different from a distance from a lower surface of the first conductive semiconductor layer to an upper surface of the first conductive semiconductor layer contacting the first surface of the active layer.

[0019] In an embodiment of the present disclosure, the electrode layer may include a transparent metal oxide, and may have a thickness of 0.5 μm to 1 μm in a longitudinal direction of the emission stack pattern.

[0020] In an embodiment of the present disclosure, the light emitting element may further include an insulating film surrounding the periphery of the emission stack pattern.

[0021] According to aspects of the present disclosure, a display device may include: a substrate including a display area and a non-display area; and a plurality of pixels arranged in the display area of ​​the substrate and each including a plurality of sub-pixels. Each of the plurality of sub-pixels may include a pixel circuit layer and a display element layer, the pixel circuit layer including at least one transistor, and the display element layer including at least one light-emitting element that emits light.

[0022] In an embodiment of the present disclosure, the display element layer may include a first electrode and a second electrode spaced apart from each other, and the light emitting element has a first end and a second end in a longitudinal direction and is connected to each of the first electrode and the second electrode.

[0023] In an embodiment of the present disclosure, a light emitting element may include: an emission stack pattern including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer sequentially stacked in a longitudinal direction, the emission stack pattern being located on a pixel circuit layer; and an insulating film configured to surround the periphery of the emission stack pattern. The active layer may include a first surface in contact with the first conductive semiconductor layer in the longitudinal direction and a second surface opposite to the first surface and in contact with the second conductive semiconductor layer.

[0024] In an embodiment of the present disclosure, the first conductive semiconductor layer may include at least one n-type semiconductor layer, and the second conductive semiconductor layer may include at least one p-type semiconductor layer.

[0025] In an embodiment of the present disclosure, the first surface of the active layer may be located at a point corresponding to a range of -20% to +20% deviation from half of the total length of the emission stack pattern in the longitudinal direction within the emission stack pattern.

[0026] In an embodiment of the present disclosure, in a cross-sectional view, a distance from the first surface of the active layer to an upper surface of the second conductive semiconductor layer may be different from a distance from a lower surface of the first conductive semiconductor layer to an upper surface of the first conductive semiconductor layer in contact with the first surface of the active layer.

[0027] In an embodiment of the present disclosure, in a cross-sectional view, a ratio of a distance from the second surface of the active layer to an upper surface of the second conductive semiconductor layer to a total length of the emission stack pattern is 0.5 or less.

[0028] In an embodiment of the present disclosure, the emission stack pattern may further include an electrode layer disposed on the second conductive semiconductor layer. The electrode layer may include a transparent metal oxide and may have a thickness of 0.5 μm to 1 μm in a longitudinal direction of the emission stack pattern.

[0029] In an embodiment of the present disclosure, in a cross-sectional view, a ratio of a distance from the second surface of the active layer to an upper surface of the electrode layer to a total length of the emission stack pattern may be 0.5 or less.

[0030] In an embodiment of the present disclosure, in a cross-sectional view, a distance from the first surface of the active layer to an upper surface of the electrode layer may be different from a distance from a lower surface of the first conductive semiconductor layer to an upper surface of the first conductive semiconductor layer contacting the first surface of the active layer.

[0031] In an embodiment of the present disclosure, the display element layer may further include an insulating layer disposed on the light emitting element to expose the first end and the second end of the light emitting element. The insulating layer may have a width in the longitudinal direction of the light emitting element that is equal to or less than the distance from the lower surface of the first conductive semiconductor layer to the upper surface of the first conductive semiconductor layer.

[0032] In an embodiment of the present disclosure, the display element layer may further include: a first contact electrode electrically connecting one of the first and second ends of the light-emitting element to the first electrode; and a second contact electrode electrically connecting the other one of the first and second ends of the light-emitting element to the second electrode.

[0033] In an embodiment of the present disclosure, the first contact electrode and the second contact electrode may be disposed on the insulating layer.

[0034] Beneficial Effects

[0035] According to an embodiment of the present disclosure, the active layer of the emission stack pattern grown on the substrate can be located at the center (or middle) of the emission stack pattern in the longitudinal direction of the emission stack pattern, thereby emitting light of uniform intensity from both ends, thereby improving light luminous efficiency.

[0036] Furthermore, an embodiment of the present disclosure may provide a display device including the above-mentioned light emitting element.

[0037] The aspects and features of the embodiments of the present disclosure are not limited to the foregoing, and various other aspects and features are contemplated herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1a is a perspective cross-sectional view schematically showing a light emitting element according to an embodiment of the present disclosure.

[0039] Figure 1b It is shown Figure 1a A cross-sectional view of a light-emitting element.

[0040] Figures 2a to 2j is shown in order to manufacture Figure 1a and Figure 1b A cross-sectional view of a method of light emitting element.

[0041] Figure 3a is a perspective cross-sectional view schematically showing a light emitting element according to an embodiment of the present disclosure.

[0042] Figure 3b It is shown Figure 3a A cross-sectional view of a light-emitting element.

[0043] Figures 4a to 4i The manufacturing sequence is shown in Figure 3a and Figure 3b A cross-sectional view of a method of light emitting element.

[0044] Figure 5 The present invention is a display device according to an embodiment of the present invention, specifically, using Figure 1a and Figure 1b or Figure 3a and Figure 3b Schematic plan view of a display device in which the light-emitting element shown in FIG. 1 is used as a light source.

[0045] Figures 6a to 6c is a diagram showing various embodiments including Figure 5 Circuit diagram of a pixel region of a first sub-pixel in one of the pixels shown in .

[0046] Figure 7 It is schematically shown that the Figure 5 1 is a plan view of first to third sub-pixels in one of the pixels shown in FIG.

[0047] Figure 8 It is along Figure 7 A cross-sectional view taken along line II'.

[0048] Figure 9a yes Figure 8 An enlarged cross-sectional view of portion EA1.

[0049] Figure 9b It shows that Figure 9a An enlarged cross-sectional view of a state in which a portion of an insulating film of a light-emitting element is separated.

[0050] Fig.10 Shown include Figure 3a The light emitting element shown in the figure is a part of the display element layer and is Figure 8 The enlarged cross-sectional view corresponding to portion EA1.

[0051] Fig.11 It is along Figure 7 The line I-I' intercepts Figure 8 The partition wall shown in FIG. 1 is a sectional view of a partition wall realized in different forms.

[0052] Fig.12 Shows Figure 7 , and is a schematic plan view of the first sub-pixel including only some components of the display element layer.

[0053] Fig.13 It is along Fig.12 A cross-sectional view taken along line II-II'.

[0054] Fig.14 yes Fig.13 An enlarged cross-sectional view of portion EA2.

[0055] Fig.15 Shown include Figure 3a The light emitting element shown in the figure is a part of the display element layer and is Fig.13 The enlarged cross-sectional view corresponding to portion EA2.

[0056] Fig.16 According to another embodiment Figure 8 The first contact electrode and the second contact electrode are shown in FIG. Figure 7 A cross-sectional view taken along line II'.

[0057] Fig.17 yes Fig.16 An enlarged cross-sectional view of portion EA3.

[0058] Fig.18 Shown include Figure 3a The light emitting element shown in the figure is a part of the display element layer and is Fig.16 The enlarged cross-sectional view corresponding to portion EA3. DETAILED DESCRIPTION

[0059] Since the present disclosure allows various changes and many embodiments, specific embodiments will be shown in the drawings and described in detail in the written description. However, this is not intended to limit the present disclosure to a specific mode of practice, and it will be understood that all changes, equivalents and substitutes that do not depart from the spirit and technical scope of the present disclosure are included in the present disclosure.

[0060] Throughout the disclosure, throughout the various figures and embodiments of the present disclosure, the same reference numerals refer to the same parts. For clarity of explanation, the size of the elements in the drawings may be exaggerated. It will be understood that, although the terms "first", "second", etc. may be used here to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the teachings of the present disclosure, the first element discussed below may be named as the second element. Similarly, the second element may also be named as the first element. In the present disclosure, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form.

[0061] It will also be understood that when the terms "comprise", "include", "have", etc. are used in this specification, it indicates the presence of the stated features, wholes, steps, operations, elements, components and / or combinations thereof, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof. In addition, when a first component such as a layer, film, region or plate is disposed on a second component, the first component may not only be directly on the second component, but a third component may be between the first component and the second component. In addition, when it is stated that a first component such as a layer, film, region or plate is formed on a second component, the surface of the second component on which the first component is formed is not limited to the upper surface of the second component, but may include other surfaces, such as the side surface or the lower surface of the second component. In contrast, when a first component such as a layer, film, region or plate is below a second component, the first component may not only be directly below the second component, but a third component may be between the first component and the second component.

[0062] The embodiments of the present disclosure and corresponding details are described with reference to the accompanying drawings to describe the present disclosure in detail so that a person skilled in the art can easily practice the present disclosure. In addition, a singular form may include a plural form as long as it is not particularly mentioned in a sentence.

[0063] Figure 1a is a perspective cross-sectional view schematically showing a light emitting element according to an embodiment of the present disclosure, and Figure 1b It is shown Figure 1a A cross-sectional view of a light-emitting element.

[0064] Although for ease of explanation, Figure 1a and Figure 1b A cylindrical light emitting element is shown, but the type and / or shape of the light emitting element according to an embodiment of the present disclosure is not limited thereto.

[0065] Reference Figure 1a and Figure 1b The light emitting element LD according to an embodiment of the present disclosure may include a first semiconductor layer (or a first conductive semiconductor layer) 11, a second semiconductor layer (or a second conductive semiconductor layer) 13, and an active layer 12 disposed between the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13.

[0066] In an embodiment of the present disclosure, the light emitting element LD may be implemented as an emission stack pattern 10 formed by continuously stacking a first conductive semiconductor layer 11, an active layer 12, and a second conductive semiconductor layer 13 in sequence. In other words, the emission stack pattern 10 may include a first conductive semiconductor layer 11, an active layer 12 disposed on a surface of the first conductive semiconductor layer 11, and a second conductive semiconductor layer 13 disposed on a surface of the active layer 12. In an embodiment, the emission stack pattern 10 may further include an electrode layer 15 disposed on a surface of the second conductive semiconductor layer 13.

[0067] In an embodiment of the present disclosure, the light emitting element LD may be formed in the shape of a rod extending in one direction. If the direction along which the light emitting element LD extends is defined as a longitudinal direction, the light emitting element LD may have a first end (or a lower end) and a second end (or an upper end) in the extending direction. One of the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13 may be disposed in the first end (or the lower end), and the other of the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13 may be disposed in the second end (or the upper end).

[0068] In an embodiment of the present disclosure, the light emitting element LD may be arranged in a cylindrical shape. However, the light emitting element may be arranged in a polygonal prism shape, a triangular prism shape, etc., without being limited thereto. The light emitting element LD may have a rod-like shape or a strip-like shape extending in the longitudinal direction (i.e., having an aspect ratio greater than 1). For example, the length L of the light emitting element LD in the longitudinal direction may be greater than its diameter D (or the width of its cross section). The light emitting element LD may include a light emitting diode manufactured to have a small size (e.g., having a length L and / or a diameter D corresponding to a size ranging from micrometers to nanometers).

[0069] In the embodiment of the present disclosure, the diameter D of the light emitting element LD may be in the range of about 0.5 μm to about 6 μm, and the length L thereof may be in the range of about 1 μm to about 10 μm. However, the size of the light emitting element LD is not limited thereto, and the size of the light emitting element LD may be changed to meet the requirements of the lighting device or self-luminous display device to which the light emitting element LD is applied.

[0070] The first conductive semiconductor layer 11 may include, for example, at least one n-type semiconductor layer. For example, the first conductive semiconductor layer 11 may include an n-type semiconductor layer including any one of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN semiconductor materials, and doped with a first conductive dopant such as Si, Ge, or Sn. However, the material forming the first conductive semiconductor layer 11 is not limited thereto, and the first conductive semiconductor layer 11 may be formed of various other materials.

[0071] The active layer 12 may be disposed on the first conductive semiconductor layer 11 and have a single quantum well structure or a multi-quantum well structure. In an embodiment, a cladding layer (not shown) doped with a conductive dopant may be formed above and / or below the active layer 12. For example, the cladding layer may be formed of an AlGaN layer or an InAlGaN layer. In an embodiment, the active layer 12 may be formed using a material such as AlGaN or AlInGaN, and various other materials may be used to form the active layer 12.

[0072] If an electric field of a predetermined voltage or higher is applied between opposite ends of the light emitting element LD, the light emitting element LD emits light by combining electron-hole pairs in the active layer 12. Since the light emission of the light emitting element LD can be controlled based on the aforementioned principle, the light emitting element LD can be used as a light source for various light emitting devices and pixels of a display device.

[0073] The active layer 12 includes a first surface 12a contacting the upper surface 11b of the first conductive semiconductor layer 11 and a second surface 12b contacting the lower surface 13a of the second conductive semiconductor layer 13. The first surface 12a and the second surface 12b may face each other in the longitudinal direction of the light emitting element LD.

[0074] The second conductive semiconductor layer 13 may be disposed on the second surface 12b of the active layer 12, and may include a semiconductor layer of a different type from that of the first conductive semiconductor layer 11. For example, the second conductive semiconductor layer 13 may include at least one p-type semiconductor layer. For example, the second conductive semiconductor layer 13 may include a p-type semiconductor layer including at least one semiconductor material of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and doped with a second conductive dopant such as Mg. However, the material forming the second conductive semiconductor layer 13 is not limited thereto, and the second conductive semiconductor layer 13 may be formed of various other materials.

[0075] In an embodiment of the present disclosure, the emission stack pattern 10 may include an electrode layer 15 disposed on the upper surface 13b of the second conductive semiconductor layer 13. Therefore, the emission stack pattern 10 may include a stack structure formed by continuously stacking the first conductive semiconductor layer 11, the active layer 12, the second conductive semiconductor layer 13 and the electrode layer 15 in sequence.

[0076] The emission stack pattern 10 may be arranged and / or formed into a shape corresponding to the shape of the light emitting element LD. For example, when the light emitting element LD is arranged and / or formed into a cylindrical shape, the emission stack pattern 10 may also be arranged into a cylindrical shape. In addition, when the emission stack pattern 10 is arranged and / or formed into a cylindrical shape, each of the first conductive semiconductor layer 11, the active layer 12, the second conductive semiconductor layer 13, and the electrode layer 15 included in the emission stack pattern 10 may have a cylindrical shape.

[0077] The first conductive semiconductor layer 11 may be disposed in a first end (or lower end) of the light emitting element LD, and the electrode layer 15 may be disposed in a second end (or upper end) of the light emitting element LD. The light emitting element LD may include a lower surface 11a of the first conductive semiconductor layer 11 located on opposite ends of the light emitting element LD and exposed to the outside, and an upper surface 15b of the electrode layer 15. The lower surface 11a of the first conductive semiconductor layer 11 and the upper surface 15b of the electrode layer 15 may be surfaces that are in contact with an external conductive material to be electrically connected thereto. In an embodiment of the present disclosure, the lower surface 11a of the first conductive semiconductor layer 11 may be a lower surface LD_1 of the light emitting element LD, and the upper surface 15b of the electrode layer 15 may be an upper surface LD_2 of the light emitting element LD.

[0078] When the light emitting element LD has a cylindrical shape, the first conductive semiconductor layer 11 may be disposed in the lower portion of the cylinder, and the electrode layer 15 may be disposed in the upper portion of the cylinder. When the light emitting element LD has a cylindrical shape, each of the lower surface 11a or LD_1 of the first conductive semiconductor layer 11 and the upper surface 15b or LD_2 of the electrode layer 15 may have a circular shape. In an embodiment, when the light emitting element LD has an elliptical cylinder shape, each of the lower surface 11a or LD_1 of the first conductive semiconductor layer 11 and the upper surface 15b or LD_2 of the electrode layer 15 may have an elliptical shape. Furthermore, in another embodiment, when the light emitting element LD has a polygonal pyramid shape, each of the lower surface 11a or LD_1 of the first conductive semiconductor layer 11 and the upper surface 15b or LD_2 of the electrode layer 15 may have a polygonal shape.

[0079] When the emission stack pattern 10 is set to a shape corresponding to the shape of the light emitting element LD, the emission stack pattern 10 may have a length substantially similar to or equal to the length L of the light emitting element LD. For example, when the light emitting element LD has a length L of about 3.5 μm, the emission stack pattern 10 may also have a length L of about 3.5 μm. In the following embodiments, the description will be made on the premise that the length of the emission stack pattern 10 is the same as the length L of the light emitting element LD. The length of the emission stack pattern 10 is represented by the same reference numeral as the length L of the light emitting element LD.

[0080] The electrode layer 15 may be an ohmic contact electrode electrically connected to the second conductive semiconductor layer 13, but the present disclosure is not limited thereto. The electrode layer 15 may include a metal or a metal oxide. For example, Cr, Ti, Al, Au, Ni, and oxides or alloys thereof, ITO, IZO, ITZO may be used alone or in combination with each other. In addition, the electrode layer 15 may be substantially transparent or translucent. Thus, the light generated from the active layer 12 may be emitted to the outside of the light emitting element LD after passing through the electrode layer 15.

[0081] In an embodiment of the present disclosure, the electrode layer 15 may be selectively made of a transparent metal oxide (such as indium tin oxide (ITO)) or an opaque metal according to the color of the light ultimately emitted from the active layer 12. For example, when the active layer 12 emits blue-based and / or green-based light in the wavelength range of 400nm to 580nm, the electrode layer 15 may be made of a transparent metal oxide (such as indium tin oxide (ITO)). In addition, when the active layer 12 emits red-based and / or infrared-based light in the wavelength range of 580nm to 900nm, the electrode layer 15 may be made of an opaque metal (such as Cr, Ti, or Ni). However, the present disclosure is not limited thereto. In an embodiment, the electrode layer 15 may be formed of a transparent metal oxide to ensure light transmittance when the active layer 12 emits red-based or infrared-based light in the wavelength range of 580nm to 900nm.

[0082] In the above-mentioned embodiments, although the electrode layer 15 has been described and illustrated as a single conductive layer made of a transparent metal oxide and / or a single conductive layer made of an opaque metal, the present disclosure is not limited thereto. In an embodiment, the electrode layer 15 may be a multilayer structure formed by stacking a conductive layer made of at least one transparent metal oxide and a conductive layer made of at least one opaque metal.

[0083] In addition, in the embodiment, the light emitting element LD may further include an insulating film 14 disposed on the periphery (or surface) of the emission stack pattern 10. The insulating film 14 may include a transparent insulating material. For example, the insulating film 14 may include a SiO 2 、Si 3 N 4 、Al 2 O 3 and TiO 2 At least one insulating material selected from the group consisting of, but not limited to. In other words, various materials with insulating properties can be used.

[0084] The insulating film 14 can prevent the active layer 12 from being short-circuited due to contact with conductive materials other than the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13 of the same light-emitting element LD. Due to the insulating film 14, the occurrence of defects on the surface of the light-emitting element LD can be reduced or minimized, thereby improving the life and efficiency of the light-emitting element. In the case where a plurality of light-emitting elements LD are arranged in close contact with each other, the insulating film 14 can prevent an undesired short circuit from occurring between the light-emitting elements LD. Whether the insulating film 14 is provided is not limited as long as the active layer 12 can be prevented from being short-circuited with an external conductive material.

[0085] The insulating film 14 may be formed and / or disposed on the surface (or periphery) of the emission stack pattern 10 to surround at least the outer peripheral surface of the active layer 12. In addition, the insulating film may also surround the region of each of the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13 and the outer peripheral surface of the electrode layer 15. In an embodiment of the present disclosure, the insulating film 14 may completely surround the outer peripheral surfaces of both ends of the light emitting element LD having different polarities, but the present disclosure is not limited thereto. In an embodiment, the insulating film 14 may surround a portion of the outer peripheral surface of the first conductive semiconductor layer 11 and / or a portion of the outer peripheral surface of the electrode layer 15.

[0086] The insulating film 14 may include a lower surface 14a parallel to the lower surface 11a of the first conductive semiconductor layer 11 in a direction intersecting the longitudinal direction of the light emitting element LD, an upper surface 14b facing the lower surface 14a in the longitudinal direction, and a side surface 14c surrounding the surface (or peripheral surface) of the emission stack pattern 10. The lower surface 14a of the insulating film 14, the upper surface 14b of the insulating film 14, and the side surface 14c of the insulating film 14 may be continuously connected to each other. Here, the upper surface 14b of the insulating film 14 may be defined as an imaginary surface including the periphery of the upper end of the insulating film 14, and the lower surface 14a of the insulating film 14 may be defined as an imaginary surface including the periphery of the lower end of the insulating film 14.

[0087] In an embodiment of the present disclosure, the insulating film 14 may completely surround the outer peripheral surface of the electrode layer 15. In this case, the upper surface 14b of the insulating film 14 and the upper surface 15b of the electrode layer 15 may be arranged and / or formed at the same surface (or the same line (or straight line)). However, the present disclosure is not limited to this. In an embodiment, when the insulating film 14 partially surrounds or does not surround the periphery of the electrode layer 15, the upper surface 14b of the insulating film 14 and the upper surface 15b of the electrode layer 15 or LD_2 may be arranged and / or formed at different surfaces (or different lines).

[0088] In an embodiment of the present disclosure, the insulating film 14 may completely surround the outer peripheral surface of the first conductive semiconductor layer 11. In this case, the lower surface 14a of the insulating film 14 and the lower surface 11a of the first conductive semiconductor layer 11 or LD_1 may be disposed and / or formed at the same surface (or the same line). However, the present disclosure is not limited thereto. In an embodiment, when the insulating film 14 partially surrounds or does not surround the outer peripheral surface of the first conductive semiconductor layer 11, the lower surface 14a of the insulating film 14 and the lower surface 11a of the first conductive semiconductor layer 11 or LD_1 may be disposed and / or formed at different surfaces (or different lines).

[0089] In an embodiment of the present disclosure, the length of the side surface 14c of the insulating film 14 relative to the longitudinal direction of the light emitting element LD may be equal to the length L of the emission stack pattern 10 including the first conductive semiconductor layer 11, the active layer 12, the second conductive semiconductor layer 13 and the electrode layer 15, but the present disclosure is not limited thereto. In an embodiment, the length of the side surface 14c of the insulating film 14 relative to the longitudinal direction of the light emitting element LD may be shorter or longer than the length L of the emission stack pattern 10.

[0090] The lower surface 14a of the insulating film 14 may be located at the same surface (or the same line) as the lower surface 11a of the first conductive semiconductor layer 11 or LD_1, and the upper surface 14b of the insulating film 14 may be located at the same surface (or the same line) as the upper surface 15b of the electrode layer 15 or LD_2. The lower surface 14a of the insulating film 14 and the lower surface 11a of the first conductive semiconductor layer 11 or LD_1 may not necessarily be located at the same surface (or the same line). In an embodiment, they may be located at different surfaces (or different lines). Similarly, the upper surface 14b of the insulating film 14 and the upper surface 15b of the electrode layer 15 or LD_2 may not necessarily be located at the same surface (or the same line). In an embodiment, they may be located at different surfaces (or different lines).

[0091] In the embodiment of the present disclosure, the first conductive semiconductor layer 11, the active layer 12, the second conductive semiconductor layer 13, and the electrode layer 15 which are continuously stacked in the longitudinal direction of the light emitting element LD may have different thicknesses. More specifically, the thickness d1 of the first conductive semiconductor layer 11, the thickness d2 of the active layer 12, the thickness d3 of the second conductive semiconductor layer 13, and the thickness d4 of the electrode layer 15 in the longitudinal direction of the light emitting element LD may be different from each other.

[0092] In an embodiment of the present disclosure, the thickness d1 of the first conductive semiconductor layer 11 may represent a distance between a lower surface 11a or LD_1 of the first conductive semiconductor layer 11 and an upper surface 11b thereof in a longitudinal direction of the light emitting element LD. The first conductive semiconductor layer 11 may have a thickness d1 of about 1 μm to about 5 μm, but the present disclosure is not limited thereto.

[0093] The thickness d2 of the active layer 12 may represent a distance between a lower surface 12a of the active layer 12 and an upper surface 12b thereof in a longitudinal direction of the light emitting element LD. Here, the lower surface 12a of the active layer 12 may be in contact with the upper surface 11b of the first conductive semiconductor layer 11. The active layer 12 may have a thickness d2 of about 0.05 μm to about 0.5 μm, but the present disclosure is not limited thereto.

[0094] The thickness d3 of the second conductive semiconductor layer 13 may represent a distance between a lower surface 13a of the second conductive semiconductor layer 13 and an upper surface 13b thereof in a longitudinal direction of the light emitting element LD. Here, the lower surface 13a of the second conductive semiconductor layer 13 may be in contact with the upper surface 12b of the active layer 12. The second conductive semiconductor layer 13 may have a thickness d3 of about 0.08 μm to about 2 μm, but the present disclosure is not limited thereto.

[0095] The thickness d4 of the electrode layer 15 may represent a distance between a lower surface 15a of the electrode layer 15 and an upper surface 15b thereof in the longitudinal direction L of the light emitting element LD. Here, the lower surface 15a of the electrode layer 15 may be in contact with the upper surface 13b of the second conductive semiconductor layer 13. The electrode layer 15 may have a thickness d4 of about 0.5 μm to about 1 μm, but the present disclosure is not limited thereto. In addition, in an embodiment of the present disclosure, the thickness d4 of the electrode layer 15 may be greater than the thickness d3 of the second conductive semiconductor layer 13.

[0096] In an embodiment of the present disclosure, the thickness d1 of the first conductive semiconductor layer 11 may be greater than each of the thickness d2 of the active layer 12, the thickness d3 of the second conductive semiconductor layer 13, and the thickness d4 of the electrode layer 15. In addition, the thickness d1 of the first conductive semiconductor layer 11 may be equal to or similar to the sum of the thickness d2 of the active layer 12, the thickness d3 of the second conductive semiconductor layer 13, and the thickness d4 of the electrode layer 15, but the present disclosure is not limited thereto. In an embodiment, the thickness d1 of the first conductive semiconductor layer 11 may be less than or greater than the sum of the thickness d2 of the active layer 12, the thickness d3 of the second conductive semiconductor layer 13, and the thickness d4 of the electrode layer 15. In an embodiment of the present disclosure, the thickness d1 of the first conductive semiconductor layer 11 may be substantially equal to or similar to the sum of the thickness d2 of the active layer 12, the thickness d3 of the second conductive semiconductor layer 13, and the thickness d4 of the electrode layer 15.

[0097] The light emitting element LD may include a first region I and a second region II. The first region I and the second region II may be divided based on a lower surface 12a of the active layer 12 in contact with the upper surface 11b of the first conductive semiconductor layer 11 in the longitudinal direction of the light emitting element LD, but the present disclosure is not limited thereto. In an embodiment, the light emitting element LD may be divided into a first region I and a second region II based on an upper surface 12b of the active layer 12, a lower surface 13a of the second conductive semiconductor layer 13, and an upper surface 13b of the second conductive semiconductor layer 13. In addition, the light emitting element LD may not necessarily be divided into a first region I and a second region II. For ease of description, the light emitting element has been described as being divided into a first region I and a second region II.

[0098] In an embodiment of the present disclosure, the first region I may represent a region extending from the lower surface 11a of the first conductive semiconductor layer 11 to the lower surface 12a of the active layer 12 in the longitudinal direction of the light emitting element LD. In other words, the first region I may represent a region extending from the lower surface LD_1 of the light emitting element LD to the lower surface 12a of the active layer 12. The first conductive semiconductor layer 11 may be located in the first region I. The second region II may represent a region extending from the lower surface 12a of the active layer 12 to the upper surface 15b of the electrode layer 15 in the longitudinal direction of the light emitting element LD. In other words, the second region II may represent a region extending from the lower surface 12a of the active layer 12 to the upper surface LD_2 of the light emitting element LD. The active layer 12, the second conductive semiconductor layer 13, and the electrode layer 15 may be located in the second region II.

[0099] As described above, since the first conductive semiconductor layer 11 is located in the first region I, the width of the first region I in the longitudinal direction of the light emitting element LD may be substantially equal to the thickness d1 of the first conductive semiconductor layer 11. In addition, since components other than the first conductive semiconductor layer 11 (e.g., the active layer 12, the second conductive semiconductor layer 13, and the electrode layer 15) are located in the second region II, the width of the second region II in the longitudinal direction of the light emitting element LD may be substantially the same as the sum of the thickness d2 of the active layer 12, the thickness d3 of the second conductive semiconductor layer 13, and the thickness d4 of the electrode layer 15.

[0100] In an embodiment of the present disclosure, the first region I and the second region II may have substantially the same or similar widths. In this case, in the longitudinal direction of the light emitting element LD and / or the emission stack pattern 10, the active layer 12 may be closer to the upper surface 15b of the electrode layer 15 than the lower surface 11a of the first conductive semiconductor layer 11.

[0101] In an embodiment of the present disclosure, the active layer 12 may be located in the middle (or center) of the light emitting element LD in the longitudinal direction of the light emitting element LD, or may be located adjacent to the middle (or center) of the light emitting element LD. When viewed in a cross-sectional view, the upper surface 12b of the active layer 12 may not be located at a point corresponding to half of the length L of the light emitting element LD. More specifically, when the length L of the light emitting element LD is 3 μm, the upper surface 12b of the active layer 12 may not be located at a point corresponding to 1.5 μm, which is half of the length L of the light emitting element LD from the lower surface 11a of the first conductive semiconductor layer 11 in the longitudinal direction of the light emitting element LD. Similarly, when viewed in a cross-sectional view, the upper surface 12b of the active layer 12 may not be located at a point corresponding to half of the length L of the emission stack pattern 10.

[0102] When viewed in a cross-sectional view, a ratio of a distance from an upper surface 12b of the active layer 12 to an upper surface 15b of the electrode layer 15 to a length L of each of the light emitting element LD and / or the emission stack pattern 10 may be 0.5 or less. In other words, when viewed in a cross-sectional view, a sum of a thickness d3 of the second conductive semiconductor layer 13 and a thickness d4 of the electrode layer 15 in a longitudinal direction of the light emitting element LD may be equal to or less than half of the length L of each of the light emitting element LD and / or the emission stack pattern 10. For example, when the length L of each of the light emitting element LD and / or the emission stack pattern 10 is 3 μm, a sum of a thickness d3 of the second conductive semiconductor layer 13 and a thickness d4 of the electrode layer 15 may be equal to or less than 1.5 μm.

[0103] In an embodiment of the present disclosure, a point corresponding to half of the length L of each of the light emitting element LD and / or the emission stack pattern 10 may be located between the lower surface 12a of the active layer 12 and the upper surface 12b of the active layer 12. However, the present disclosure is not limited thereto. In an embodiment, a point corresponding to half of the length L of each of the light emitting element LD and / or the emission stack pattern 10 may correspond to the lower surface 12a of the active layer 12 or the upper surface 12b of the active layer 12. In addition, in an embodiment, a point corresponding to half of the length L of each of the light emitting element LD and / or the emission stack pattern 10 may be located between the lower surface 12a of the active layer 12 and the first conductive semiconductor layer 11, or between the upper surface 12b of the active layer 12 and the second conductive semiconductor layer 13.

[0104] In an embodiment of the present disclosure, when viewed in a cross-sectional view, the distance from the lower surface 12a of the active layer 12 to the upper surface 15b of the electrode layer 15 (i.e., the sum of the thickness d2 of the active layer 12, the thickness d3 of the second conductive semiconductor layer 13, and the thickness d4 of the electrode layer 15) can be equal to or less than the thickness d1 (or distance) from the lower surface 11a of the first conductive semiconductor layer 11 to its upper surface 11b.

[0105] As described above, when viewed in a cross-sectional view, when the sum of the thickness d3 of the second conductive semiconductor layer 13 and the thickness d4 of the electrode layer 15 is equal to or less than half of the length L of each of the light emitting element LD and / or the emission stack pattern 10, the active layer 12 may be located in the middle (or center) of the emission stack pattern 10 in the longitudinal direction of the light emitting element LD, or adjacent to the middle (or center) of the emission stack pattern 10. However, the present disclosure is not limited to this. In an embodiment, the active layer 12 may deviate from the middle (or center) of the light emitting element LD and / or the emission stack pattern 10 in the longitudinal direction of the light emitting element LD, and may be disposed and / or formed closer to the upper surface LD_2 of the light emitting element LD. In addition, in an embodiment, the active layer 12 may deviate from the middle (or center) of the light emitting element LD and / or the emission stack pattern 10 in the longitudinal direction of the light emitting element LD, and may be disposed and / or formed closer to the lower surface LD_1 of the light emitting element LD.

[0106] Specifically, in an embodiment of the present disclosure, the electrode layer 15 disposed and / or formed on the second conductive semiconductor layer 13 may have a thickness d4 of a predetermined level or greater. The electrode layer 15 may be disposed and / or formed on the second conductive semiconductor layer 13 by a conventional deposition method. In this case, the electrode layer 15 having a thickness d4 of a predetermined level or greater may be formed on the second conductive semiconductor layer 13 by controlling the deposition time. When the electrode layer 15 has a thickness d4 of a predetermined level or greater (for example, a thickness of about 1 μm), the length L of the light emitting element LD and / or the emission stack pattern 10 may be increased by about 0.9 μm compared to the existing electrode layer 15 having a thickness of about 0.1 μm. Therefore, the active layer 12 may be substantially located in the middle (or center) of the light emitting element LD and / or the emission stack pattern 10 in the longitudinal direction of the light emitting element LD, or may be positioned adjacent to the middle (or center) of the light emitting element LD and / or the emission stack pattern 10.

[0107] For example, when the light emitting element LD has a length L of about 3 μm, the lower surface 12a of the active layer 12 may contact the middle (or center) of the light emitting element LD corresponding to a point of 1.5 μm, which is half the length L of the light emitting element LD from the lower surface 11a of the first conductive semiconductor layer 11 in the longitudinal direction of the light emitting element LD. In an embodiment, when the light emitting element LD has a length L of about 3 μm, the lower surface 12a of the active layer 12 may contact a region adjacent to the middle (or center) of the light emitting element LD, which is located in the range of -20% to +20% from a point of 1.5 μm, which is half the length L of the light emitting element LD, from the lower surface 11a of the first conductive semiconductor layer 11 in the longitudinal direction of the light emitting element LD. In other words, when the light emitting element LD and / or the emission stack pattern 10 has a length L of 3 μm, the lower surface 12a of the active layer 12 may be located at a point of 1.2 μm to 1.8 μm in the longitudinal direction within the light emitting element LD and / or the emission stack pattern 10.

[0108] However, the area where the active layer 12 is located in the longitudinal direction of the light emitting element LD in the light emitting element LD and / or the emission stack pattern 10 is not limited to the above-mentioned embodiments. The position of the active layer 12 can be changed in various ways according to the design conditions, size and / or length L of the light emitting element LD and the requirements of the electronic device to which the light emitting element LD is applied.

[0109] As described above, when the active layer 12 is located in the middle (or center) of the light emitting element LD and / or the emission stack pattern 10 in the longitudinal direction of the light emitting element LD, or is adjacent to the middle (or center) of the light emitting element LD and / or the emission stack pattern 10, the light emitted from the active layer 12 can travel uniformly (or evenly) to both ends of the light emitting element LD and / or the emission stack pattern 10 without being biased in one direction. Therefore, the intensity of the light emitted from both ends of the light emitting element LD and / or the emission stack pattern 10 becomes uniform, so that the light efficiency of the light emitting element LD and / or the emission stack pattern 10 can be improved.

[0110] If the active layer 12 is disposed adjacent to one of the two ends, rather than being located in the middle (or center) of the light emitting element LD and / or the emission stack pattern 10, the light emitted from the active layer 12 will be concentrated on one of the two ends. In this case, the light emitted from the light emitting element LD and / or the emission stack pattern 10 will be concentrated in one direction, so that the light of the light emitting element LD will be output asymmetrically. Therefore, in an embodiment of the present disclosure, the electrode layer 15 is formed to have a thickness d4 of a predetermined level or greater, and then the active layer 12 is located in the middle (or center) of the light emitting element LD and / or the emission stack pattern 10, or is positioned adjacent to the middle (or center) of the light emitting element LD and / or the emission stack pattern 10, thereby allowing the light emitted from the active layer 12 to travel uniformly (or uniformly) to both ends of the light emitting element and / or the emission stack pattern 10. Therefore, according to an embodiment of the present disclosure, the luminous efficiency of the light emitting element LD can be improved.

[0111] The light emitting element LD can be used as a light source for various display devices. The light emitting element LD can be manufactured by a surface treatment process. For example, the light emitting element LD can be surface treated so that when a plurality of light emitting elements LD are mixed with a fluid solution (or solvent) and then supplied to each emission region (e.g., the emission region of each sub-pixel), the light emitting element LD can be uniformly distributed in the solution instead of being unevenly aggregated.

[0112] The light-emitting device including the above-mentioned light-emitting element LD can be used in various devices including a display device requiring a light source. For example, in the case where a plurality of light-emitting elements LD are arranged in the emission region of each sub-pixel of the display panel, the light-emitting element LD can be used as the light source of each sub-pixel. However, the application field of the light-emitting element LD is not limited to the above-mentioned example. For example, the light-emitting element LD can also be used in various devices (such as lighting devices) requiring a light source.

[0113] In an embodiment of the present disclosure, in addition to the first conductive semiconductor layer 11, the active layer 12, the second conductive semiconductor layer 13, the electrode layer 15 and the insulating film 14 described above, the light emitting element LD may also include additional components. For example, the emission stack pattern 10 of the light emitting element LD may also include one or more electrode layers and / or fluorescent layers disposed on one side of each of the first conductive semiconductor layer 11 and / or the active layer 12. Although not directly shown in the drawings, the light emitting element LD may also include at least one electrode layer disposed on one side of the first conductive semiconductor layer 11. The above-mentioned electrode layer may be an ohmic contact electrode. However, the electrode layer may include a material that is the same as or different from the material of the electrode layer 15 disposed on one side of the second conductive semiconductor layer 13, without being limited thereto.

[0114] Figures 2a to 2j The manufacturing sequence is shown in Figure 1a and Figure 1b A cross-sectional view of a method of light emitting element.

[0115] Reference Figure 1a , Figure 1b and Figure 2a , a substrate 1 configured to support the light emitting element LD is prepared.

[0116] The substrate 1 may be a GaAs, GaP or InP substrate. The substrate 1 may be a wafer for epitaxial growth. The substrate 1 may include a ZnO substrate having a GaAs layer on the surface. In addition, a Ge substrate having a GaAs layer on the surface and a Si substrate having a GaAs layer on a Si wafer with a buffer layer placed therebetween may also be used.

[0117] A commercially available single crystal substrate manufactured by a known manufacturing method may be used as the substrate 1. When a selection ratio for manufacturing the light emitting element LD is satisfied and epitaxial growth is smoothly performed, the material of the substrate 1 is not limited thereto.

[0118] It is desirable that the surface of the substrate 1 to be epitaxially grown is smooth. The size and diameter of the substrate 1 may vary depending on the product to which the substrate 1 is applied, and may be manufactured in a form capable of reducing the warping caused by the stacked structure caused by epitaxial growth. The shape of the substrate 1 is not limited to a circular shape, and may have a polygonal shape such as a rectangle.

[0119] Subsequently, a sacrificial layer 3 is formed on the substrate 1. In the process of manufacturing the light emitting element LD on the substrate 1, the sacrificial layer 3 may be located between the light emitting element LD and the substrate 1 to physically separate the light emitting element LD from the substrate 1.

[0120] The sacrificial layer 3 may have various structures, that is, a single layer structure or a multilayer structure. The sacrificial layer 3 may be a layer that is removed in the final manufacturing process of the light emitting element LD. When the sacrificial layer 3 is removed, interlayer separation may be performed above and below the sacrificial layer 3. Figure 2j A method of removing the sacrificial layer 3 will be described.

[0121] In the embodiment of the present disclosure, the sacrificial layer 3 may be formed of GaAs, AlAs or AlGaAs.

[0122] The first conductive semiconductor layer 11 is formed on the sacrificial layer 3. The first conductive semiconductor layer 11 may be formed by epitaxial growth, and may be formed by an MOCVD method, an MBE method, a VPE method, an LPE method, etc. In an embodiment, an additional semiconductor layer such as a buffer layer and an undoped semiconductor layer for improving crystallinity may be further formed between the first conductive semiconductor layer 11 and the sacrificial layer 3.

[0123] The first conductive semiconductor layer 11 may include a semiconductor material composed of III (Ga, Al, In) -V (P, As) group, and may include a semiconductor layer doped with a first conductive dopant such as Si, Ge, or Sn. For example, the first conductive semiconductor layer 11 may include at least one semiconductor material among GaP, GaAs, GaInP, and AlGaInP doped with Si. In other words, the first conductive semiconductor layer 11 may include at least one n-type semiconductor layer. The material forming the first conductive semiconductor layer 11 is not limited thereto, and the first conductive semiconductor layer 11 may be formed of various other materials.

[0124] In an embodiment, when the light emitting element LD includes a conductive material layer (not shown) contacting the lower surface 11 a of the first conductive semiconductor layer 11 , the conductive material layer may be formed before forming the first conductive semiconductor layer 11 on the sacrificial layer 3 .

[0125] Reference Figure 1a , Figure 1b , Figure 2a and Figure 2b , an active layer 12 is formed on the first conductive semiconductor layer 11. The active layer 12 is a region where electrons and holes recombine. As the electrons and holes recombine, the active layer 12 can transition to a low energy level and emit light having a wavelength corresponding thereto. The active layer 12 can be formed on the first conductive semiconductor layer 11 and have a single quantum well structure or a multi-quantum well structure. The position of the active layer 12 can be changed in various ways depending on the type of the light emitting element LD. In an embodiment of the present disclosure, the active layer 12 can be located in the middle (or center) along the length L of the light emitting element LD.

[0126] The active layer 12 may include at least one of GaInP, AlGaInP, GaAs, AlGaAs, InGaAs, InGaAsP, InP, and InAs. The active layer 12 may emit light having a wavelength of 400nm to 900nm. The active layer 12 may use a double heterostructure. In an embodiment, a cladding layer (not shown) doped with a conductive dopant may be further formed on the upper surface 12b and / or the lower surface 12a of the active layer 12.

[0127] Reference Figure 1a , Figure 1b , Figure 2a to Figure 2c, a second conductive semiconductor layer 13 is formed on the active layer 12. The second conductive semiconductor layer 13 may include a semiconductor layer of a type different from that of the first conductive semiconductor layer 11. The second conductive semiconductor layer 13 may include a semiconductor material composed of III (Ga, Al, In) -V (P, As) group, and may include a semiconductor layer doped with a second conductive dopant such as Mg. For example, the second conductive semiconductor layer 13 may include at least one semiconductor material among GaP, GaAs, GaInP, and AlGaInP doped with Mg. In other words, the second conductive semiconductor layer 13 may include a p-type semiconductor layer. The material forming the second conductive semiconductor layer 13 is not limited thereto, and the second conductive semiconductor layer 13 may be formed of various other materials.

[0128] Reference Figure 1a , Figure 1b , Figure 2a to Figure 2d , an electrode layer 15 is formed on the second conductive semiconductor layer 13 .

[0129] The electrode layer 15 may include a metal or a metal oxide. For example, the electrode layer 15 may use Cr, Ti, Al, Au, Ni, their oxides or alloys, ITO, IZO, ITZO alone or in combination. In an embodiment of the present disclosure, the electrode layer 15 may be made of a transparent metal oxide such as indium tin oxide (ITO) to minimize the loss of light generated from the active layer 12 and emitted to the outside of the light emitting element LD and to improve the current diffusion effect on the second conductive semiconductor layer 13.

[0130] As described above, the first conductive semiconductor layer 11 , the active layer 12 , the second conductive semiconductor layer 13 , and the electrode layer 15 sequentially stacked on the substrate 1 may form the emitter stack 10 ′.

[0131] The electrode layer 15 may be deposited on the second conductive semiconductor layer 13 by a sputtering method. However, since nitrogen vacancies are formed by plasma in the light emitting element LD including a nitride-based semiconductor, the ohmic contact characteristics of the electrode layer 15 deposited by the sputtering method may be deteriorated. Therefore, considering the amount of oxygen and the deposition temperature, the electrode layer 15 may be directly deposited on the second conductive semiconductor layer 13 by an electron beam evaporation method to improve the transmittance of the electrode layer 15. However, the method of forming the electrode layer 15 on the second conductive semiconductor layer 13 is not limited to the above-mentioned embodiment, but a conventional deposition method may be used. In an embodiment of the present disclosure, when the electrode layer 15 is formed on the second conductive semiconductor layer 13, an electrode layer 15 having a thickness d4 of a predetermined level (e.g., about 1 μm) is formed on the second conductive semiconductor layer 13 by controlling the amount of oxygen in the chamber in which the deposition process is performed, the deposition temperature, and the deposition time.

[0132] Reference Figure 1a, Figure 1b , Figure 2a to Figure 2e , a mask layer 20 is formed on the electrode layer 15. The mask layer 20 may include an insulating layer (not shown) and a metal layer (not shown). The insulating layer may be formed on the electrode layer 15. The insulating layer may be used as a mask for continuously etching the emitter stack 10'. The insulating layer may be formed of an oxide or a nitride, and may include, for example, silicon oxide (SiO x ) or silicon nitride (SiN x ). The thickness of the insulating layer may be about 0.5 μm to about 1.5 μm, but is not limited thereto. The metal layer may include a metal such as chromium (Cr), but is not limited thereto. The metal layer may have a thickness of about 30 nm to about 150 nm.

[0133] At least one micro-pattern FP may be formed on the mask layer 20. The micro-pattern FP may be formed by a polymer layer. The micro-pattern FP may be formed by forming a polymer layer on the mask layer 20 and then forming a pattern on the polymer layer at intervals from the nanometer scale to the micrometer scale. In detail, the micro-pattern FP may be formed at intervals from the nanometer scale to the micrometer scale by patterning the polymer layer on the mask layer 20 by a method such as photolithography, electron beam lithography, or nanoimprint lithography.

[0134] Reference Figure 1a , Figure 1b , Figure 2a to Figure 2f , at least one mask pattern 20' is formed by patterning the mask layer 20 using the micropattern FP as a mask. The mask pattern 20' may be formed in a shape corresponding to the micropattern FP. The above-mentioned mask pattern 20' may be used as an etching mask for forming the emission stack pattern 10 by etching the emission stack body 10'. The micropattern FP may be removed by a conventional wet etching or dry etching method, but the micropattern FP may be removed by a conventional removal method without being limited to the above-mentioned method.

[0135] Reference Figure 1a , Figure 1b , Figure 2a to Figure 2g An etching process is performed using the mask pattern 20 ′ as an etching mask to pattern the emission stack 10 ′ at intervals ranging from a nanometer level to a micrometer level, thereby forming a plurality of emission stack patterns 10 .

[0136] In the above etching process, the region of the emitter stack 10' not corresponding to the mask pattern 20' may be etched to form a groove HM exposing the region A of the first conductive semiconductor layer 11 to the outside. The region of the emitter stack 10' corresponding to the mask pattern 20' is not etched.

[0137] The groove HM may have a shape recessed from the upper surface 15 b of the electrode layer 15 of each emission stack pattern 10 to the region A of the first conductive semiconductor layer 11 in one direction (eg, a vertical direction or a vertical direction).

[0138] The etching for forming the plurality of emission stack patterns 10 may use a dry etching method, such as reactive ion etching (RIE), reactive ion beam etching (RIBE), or inductively coupled plasma reactive ion etching (ICP-RIE). Unlike the wet etching method, the dry etching method is suitable for forming the emission stack pattern 10 because anisotropic etching is possible. In other words, in the wet etching method, isotropic etching is performed so that etching is performed in all directions. In contrast, in the dry etching method, etching may be performed mainly in the depth direction to form the grooves HM, so that the size and spacing of the grooves HM may be formed in a desired pattern.

[0139] In an embodiment of the present disclosure, each emission stack pattern 10 may have a size ranging from a nanometer scale to a micrometer scale.

[0140] After performing the above-mentioned etching process, the residue (i.e., the mask pattern 20') remaining on the emission stack pattern 10 can be removed by a conventional wet etching or dry etching method. However, the embodiments of the present disclosure can remove the residue by a conventional removal method without being limited thereto. Here, the mask pattern 20' (or the residue) may include an etching mask, an insulating material, etc. required in the mask process.

[0141] Reference Figure 1a , Figure 1b , Figure 2a to Figure 2h , an insulating material layer 14' is formed on the region A of the emission stack pattern 10 and the first conductive semiconductor layer 11. The insulating material layer 14' may include an upper insulating material layer, a side insulating material layer, and a lower insulating material layer. The upper insulating material layer may completely cover the upper surface of each emission stack pattern 10. Here, the upper surface of each emission stack pattern 10 may be the upper surface 15b of the electrode layer 15. In other words, the upper insulating material layer may completely cover the upper surface 15b of the electrode layer 15 of each emission stack pattern 10. The side insulating material layer may completely cover the side surface of each emission stack pattern 10. The lower insulating material layer may completely cover the region A of the first conductive semiconductor layer 11 exposed to the outside through the groove HM.

[0142] The upper insulating material layer, the side insulating material layers, and the lower insulating material layer may be continuously connected to each other on the substrate 1 .

[0143] Although the method of forming the insulating material layer 14' may use a method of applying an insulating material to the emission stack pattern 10 attached to the substrate 1, the present disclosure is not limited thereto. The material used as the insulating material layer 14' may include a material made of SiO 2 、Si 3 N 4 、Al 2 O 3 and TiO 2 For example, Al can be formed by atomic layer deposition (ALD). 2 O 3 membrane, and can be supplied by pulsed supply of TMA (trimethylaluminum) and H 2 The O source forms a thin film using chemical adsorption and desorption. The thickness of the insulating material layer 14 ′ may be in the range of 30 nm to 150 nm, but is not limited thereto.

[0144] Reference Figure 1a , Figure 1b , Figures 2a to 2i , an etching process is performed to remove a portion of the insulating material layer 14 ′ formed on the substrate 1 , thereby forming the insulating film 14 .

[0145] In the etching process for forming the insulating film 14, the upper insulating material layer and the lower insulating material layer may be removed to finally form an insulating film 14 including only the side insulating material layer covering the side surface of each emission stack pattern 10. Through the above-mentioned etching process, the upper insulating material layer may be removed so that the upper surface 15b of the electrode layer 15 may be exposed to the outside. In this case, the upper surface 14b of the insulating film 14 and the upper surface 15b of the electrode layer 15 may be arranged and / or formed at the same surface (or the same line). In addition, the lower insulating material layer may be removed through the above-mentioned etching process so that the region A of the first conductive semiconductor layer 11 may be exposed to the outside.

[0146] Through the above etching process, a light emitting element LD including an emission stack pattern 10 and an insulating film 14 surrounding the periphery (or surface) of each emission stack pattern 10 can be finally formed. In this case, the upper surface 15b of the electrode layer 15 exposed to the outside can become the upper surface LD_2 of each light emitting element LD.

[0147] Reference Figure 1a , Figure 1b , Figures 2a to 2j , the light emitting element LD is separated from the substrate 1 by a chemical lift-off (CLO) method using an etchant. For example, the sacrificial layer 3 may be removed to separate the light emitting element LD from the substrate 1.

[0148] Generally, the chemical stripping method can be performed by a wet etching method. In an embodiment, a portion of the upper surface 15b of the electrode layer 15 exposed to the outside by the etching gas used in the chemical stripping method can be removed. However, since the electrode layer 15 has a thickness d4 of a predetermined level or more (e.g., about 1 μm), the electrode layer 15 may not be directly affected by the etching gas.

[0149] The method of separating the light emitting element LD from the substrate 1 is not limited to the above-described embodiment. In the embodiment, the light emitting element LD may be separated from the substrate 1 using a laser lift-off (LLO) method using laser, a physical lift-off method of forming an empty space (not shown) between the light emitting element LD and the substrate 1 and applying a small physical force or impact, or the like.

[0150] Through the above-described manufacturing process, each finally manufactured light emitting element LD may include an active layer 12 located in the middle (or center) of each light emitting element LD along the length L of each light emitting element LD or positioned adjacent to the middle (or center) thereof.

[0151] Figure 3a is a perspective view schematically showing a light emitting element according to an embodiment of the present disclosure, and Figure 3b It is shown Figure 3a A cross-sectional view of a light-emitting element.

[0152] To avoid redundant description, Figure 3a and Figure 3b The description of the light emitting element of the embodiment will focus on the differences from the light emitting element of the previous embodiment. Components not separately described in the following description of this embodiment are consistent with the components of the previous embodiment. The same reference numerals will be used to represent the same components, and similar reference numerals will be used to represent similar components.

[0153] Although for ease of explanation, Figure 3a and Figure 3b A cylindrical light emitting element is shown, but the type and / or shape of the light emitting element according to an embodiment of the present disclosure is not limited thereto.

[0154] Reference Figure 3a and Figure 3b The light emitting element LD according to an embodiment of the present disclosure may include a first conductive semiconductor layer 11 , a second conductive semiconductor layer 13 , and an active layer 12 interposed between the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13 .

[0155] In an embodiment of the present disclosure, the light emitting element LD may be implemented as an emission stack pattern 10 formed by continuously stacking a first conductive semiconductor layer 11, an active layer 12, and a second conductive semiconductor layer 13. The light emitting element LD may further include an insulating film 14 configured to surround the periphery (or surface) of the emission stack pattern 10.

[0156] The light emitting element LD and / or the emission stack pattern 10 may be set to a cylindrical shape, but may be set to a polygonal column or a triangular column shape, without being limited thereto. The light emitting element LD may be set to a rod shape extending in the longitudinal direction. The light emitting element LD may have a first end (or lower end) and a second end (or upper end) in the longitudinal direction. One of the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13 may be set in the first end (or lower end), and the other of the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13 may be set in the second end (or upper end). In an embodiment of the present disclosure, the first conductive semiconductor layer 11 may be set in the first end of the light emitting element LD, and the second conductive semiconductor layer 13 may be set in the second end of the light emitting element LD.

[0157] The light emitting element LD may include a lower surface 11a of a first conductive semiconductor layer 11 and an upper surface 13b of a second conductive semiconductor layer 13 located on opposite ends of the light emitting element and exposed to the outside. The lower surface 11a of the first conductive semiconductor layer 11 and the upper surface 13b of the second conductive semiconductor layer 13 may be surfaces contacting an external conductive material to be electrically connected thereto.

[0158] The first conductive semiconductor layer 11 may be at least one n-type semiconductor layer doped with n-type impurities. The first conductive semiconductor layer 11 may supply electrons to the active layer 12. The first conductive semiconductor layer 11 may include a GaN layer doped with n-type impurities (e.g., Si). However, the first conductive semiconductor layer 11 may include various semiconductor materials, without limitation thereto. The first conductive semiconductor layer 11 may be formed of any one of a GaInP layer, an AlGaN layer, an InAlGaN layer, an AlGaAs layer, a GaP layer, a GaAs layer, a GaAsP layer, and an AlGaInP layer. In an embodiment, the first conductive semiconductor layer 11 may include a lower cladding layer (not shown) in contact with the lower surface 12a of the active layer 12. The lower cladding layer may be formed of a semiconductor layer having a larger band gap than the band gap of the active layer 12 to confine electrons or holes.

[0159] The active layer 12 may be disposed and / or formed on the upper surface 11b of the first conductive semiconductor layer 11, and may include any one of a double heterostructure, a multi-well structure, a single quantum well structure, a multi-quantum well (MQW) structure, a quantum dot structure, and a quantum wire structure. The active layer 12 may be formed of a well layer and a barrier layer (e.g., a paired structure of at least one of AlGaN / AlGaN, InGaN / GaN, InGaN / InGaN, AlGaN / GaN, InAlGaN / GaN, GaAs (InGaAs) / AlGaAs, and GaP (InGaP) / AlGaP) using a compound semiconductor material of group III-V elements, but is not limited thereto. The well layer may be formed of a material having an energy bandgap smaller than an energy bandgap of the barrier layer.

[0160] In an embodiment of the present disclosure, the active layer 12 may emit red-based or infrared-based light in a wavelength range of 580 nm to 900 nm.

[0161] The second conductive semiconductor layer 13 may be disposed and / or formed on the upper surface 12b of the active layer 12, and may supply holes to the active layer 12. The second conductive semiconductor layer 13 may include a semiconductor layer of a different type from that of the first conductive semiconductor layer 11. For example, the second conductive semiconductor layer 13 may include at least one p-type semiconductor layer. For example, the second conductive semiconductor layer 13 may include at least one semiconductor material among InAlGaN, GaN, AlGaN, InGaN, AlN, and InN. In an embodiment, the second conductive semiconductor layer 13 may include an upper cladding layer (not shown) in contact with the upper surface 12b of the active layer 12. The upper cladding layer may be formed of a semiconductor layer having a band gap larger than that of the active layer 12 to confine electrons or holes.

[0162] The insulating film 14 may prevent the active layer 12 from being short-circuited due to contact with a conductive material other than the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13 of the same light emitting element LD.

[0163] In the embodiment of the present disclosure, the first conductive semiconductor layer 11, the active layer 12, and the second conductive semiconductor layer 13, which are continuously stacked in the longitudinal direction of the light emitting element LD, may have different thicknesses. More specifically, in the longitudinal direction of the light emitting element LD, the thickness d1 of the first conductive semiconductor layer 11, the thickness d2 of the active layer 12, and the thickness d3 of the second conductive semiconductor layer 13 may be different from each other.

[0164] In the embodiment of the present disclosure, the thickness d1 of the first conductive semiconductor layer 11 may represent the distance between the lower surface 11a or LD_1 of the first conductive semiconductor layer 11 and the upper surface 11b thereof in the longitudinal direction of the light emitting element LD. The thickness of the active layer 12 may represent the distance between the lower surface 12a of the active layer 12 and the upper surface 12b thereof in the longitudinal direction of the light emitting element LD. The thickness d3 of the second conductive semiconductor layer 13 may represent the distance between the lower surface 13a of the second conductive semiconductor layer 13 and the upper surface 13b thereof in the longitudinal direction of the light emitting element LD.

[0165] In an embodiment of the present disclosure, the thickness d1 of the first conductive semiconductor layer 11 may be greater than each of the thickness d2 of the active layer 12 and the thickness d3 of the second conductive semiconductor layer 13. In addition, the thickness d1 of the first conductive semiconductor layer 11 may be equal to or similar to the sum of the thickness d2 of the active layer 12 and the thickness d3 of the second conductive semiconductor layer 13. However, the present disclosure is not limited thereto. According to an embodiment, the thickness d1 of the first conductive semiconductor layer 11 may be less than or greater than the sum of the thickness d2 of the active layer 12 and the thickness d3 of the second conductive semiconductor layer 13. In an embodiment of the present disclosure, the thickness d1 of the first conductive semiconductor layer 11 may be substantially equal to or similar to the sum of the thickness d2 of the active layer 12 and the thickness d3 of the second conductive semiconductor layer 13.

[0166] The light emitting element LD may include a first region I and a second region II. The first region I and the second region II may be divided based on a lower surface 12a of the active layer 12 contacting the upper surface 11b of the first conductive semiconductor layer 11 in a longitudinal direction of the light emitting element LD.

[0167] In the embodiment of the present disclosure, the first region I may refer to a region extending from the lower surface 11a of the first conductive semiconductor layer 11 to the lower surface 12a of the active layer 12 in the longitudinal direction of the light emitting element LD. The first conductive semiconductor layer 11 may be located in the first region I. The second region II may refer to a region extending from the lower surface 12a of the active layer 12 to the upper surface 13b of the second conductive semiconductor layer 13 in the longitudinal direction of the light emitting element LD. The active layer 12 and the second conductive semiconductor layer 13 may be located in the second region II.

[0168] As described above, since the first conductive semiconductor layer 11 is located in the first region I, the width of the first region I in the longitudinal direction of the light emitting element LD may be substantially equal to the thickness d1 of the first conductive semiconductor layer 11. In addition, since components other than the first conductive semiconductor layer 11 (e.g., the active layer 12 and the second conductive semiconductor layer 13) are located in the second region II, the width of the second region II in the longitudinal direction of the light emitting element LD may be substantially the same as the sum of the thickness d2 of the active layer 12 and the thickness d3 of the second conductive semiconductor layer 13.

[0169] In an embodiment of the present disclosure, the first region I and the second region II may have the same width and / or similar width. In this case, in the longitudinal direction of the light emitting element LD and / or the emission stack pattern 10, the active layer 12 may be closer to the upper surface 13b of the second conductive semiconductor layer 13 than the lower surface 11a of the first conductive semiconductor layer 11.

[0170] In an embodiment of the present disclosure, the active layer 12 may be located in the middle (or center) of the light emitting element LD in the longitudinal direction of the light emitting element LD, or may be located adjacent to the middle (or center) of the light emitting element LD. When viewed in a cross-sectional view, the upper surface 12b of the active layer 12 may not be located at a point corresponding to half of the length L of the light emitting element LD. Similarly, when viewed in a cross-sectional view, the upper surface 12b of the active layer 12 may not be located at a point corresponding to half of the length L of the emission stack pattern 10.

[0171] When viewed in a cross-sectional view, a ratio of a distance from an upper surface 12b of the active layer 12 to an upper surface 13b of the second conductive semiconductor layer 13 to a length L of each of the light emitting element LD and / or the emission stack pattern 10 may be 0.5 or less. In other words, when viewed in a cross-sectional view, a thickness d3 of the second conductive semiconductor layer 13 in a longitudinal direction of the light emitting element LD may be equal to or less than half of the length L of each of the light emitting element LD and / or the emission stack pattern 10. For example, when the length L of each of the light emitting element LD and / or the emission stack pattern 10 is 3 μm, the thickness d3 of the second conductive semiconductor layer 13 may be equal to or less than 1.5 μm.

[0172] In an embodiment of the present disclosure, a point corresponding to half of the length L of each of the light emitting element LD and / or the emission stack pattern 10 may be located between the lower surface 12a of the active layer 12 and the upper surface 12b of the active layer 12. However, the present disclosure is not limited thereto. In an embodiment, a point corresponding to half of the length L of each of the light emitting element LD and / or the emission stack pattern 10 may correspond to the lower surface 12a of the active layer 12 or the upper surface 12b of the active layer 12.

[0173] When viewed in a cross-sectional view, the distance from the lower surface 12a of the active layer 12 to the upper surface 13b of the second conductive semiconductor layer 13 (i.e., the sum of the thickness d2 of the active layer 12 and the thickness d3 of the second conductive semiconductor layer 13) can be equal to or less than the thickness d1 (or distance) from the lower surface 11a of the first conductive semiconductor layer 11 to its upper surface 11b.

[0174] In an embodiment of the present disclosure, the second conductive semiconductor layer 13 disposed and / or formed on the active layer 12 may have a thickness d3 of a predetermined level or greater. For example, the second conductive semiconductor layer 13 may have a thickness d3 of about 1.8 μm, but the present disclosure is not limited thereto. The second conductive semiconductor layer 13 may have a thickness d3 of about 1 μm to about 2 μm. When the light emitting element LD is grown independently on a substrate (not shown), the second conductive semiconductor layer 13 may be designed to have a thickness d3 of about 1 μm to about 2 μm by increasing the thickness of at least one p-type semiconductor layer included in the second conductive semiconductor layer 13 to a predetermined level or greater. The at least one p-type semiconductor layer may be a transmissive conductive layer doped with a conductive dopant such as Mg, and may be, for example, a GaP layer.

[0175] As described above, when the second conductive semiconductor layer 13 has a thickness d3 of a predetermined level or greater, the length L of the light emitting element LD and / or the emission stack pattern 10 can be increased. Therefore, the active layer 12 can be substantially located in the middle (or center) of the light emitting element LD and / or the emission stack pattern 10 in the longitudinal direction of the light emitting element LD, or can be positioned adjacent to the middle (or center) of the light emitting element LD and / or the emission stack pattern 10.

[0176] For example, when the light emitting element LD has a length L of about 4.5 μm, the lower surface 12a of the active layer 12 may be in contact with the middle (or center) of the light emitting element LD, which corresponds to a point 2.25 μm away from the lower surface 11a of the first conductive semiconductor layer 11 by half the length L of the light emitting element LD in the longitudinal direction of the light emitting element LD. In an embodiment, when the light emitting element LD has a length L of about 4.5 μm, the lower surface 12a of the active layer 12 may be in contact with a region adjacent to the middle (or center) of the light emitting element LD, which is located in the range of -20% to +20% from the point 2.25 μm away from the lower surface 11a of the first conductive semiconductor layer 11 by half the length L of the light emitting element LD in the longitudinal direction of the light emitting element LD. In other words, when the light emitting element LD and / or the emission stack pattern 10 has a length L of 4.5 μm, the lower surface 12a of the active layer 12 can be located at a point of 1.8 μm to 2.7 μm in the longitudinal direction within the light emitting element LD and / or the emission stack pattern 10 .

[0177] However, the region where the active layer 12 is located in the longitudinal direction of the light emitting element LD in the light emitting element LD and / or the emission stack pattern 10 is not limited to the above-described embodiments. The position of the active layer 12 can be changed in various ways according to the design conditions, size and / or length of the light emitting element LD and the requirements of the electronic device to which the light emitting element LD is applied.

[0178] As described above, when the active layer 12 is located in the middle (or center) of the light emitting element LD and / or the emission stack pattern 10 in the longitudinal direction of the light emitting element LD, or is adjacent to the middle (or center) of the light emitting element LD and / or the emission stack pattern 10, the light emitted from the active layer 12 can travel uniformly (or evenly) to both ends of the light emitting element LD and / or the emission stack pattern 10 without being biased in one direction. Therefore, the intensity of the light emitted from both ends of the light emitting element LD and / or the emission stack pattern 10 becomes uniform, so that the light efficiency of the light emitting element LD and / or the emission stack pattern 10 can be improved.

[0179] Figures 4a to 4i The manufacturing sequence is shown in Figure 3a and Figure 3b A cross-sectional view of a method of light emitting element.

[0180] Reference Figure 3a , Figure 3b and Figure 4a , a sacrificial layer 3 is formed on the substrate 1, and a first conductive semiconductor layer 11 is formed.

[0181] The substrate 1 may include a GaAs substrate made of GaAs. The sacrificial layer may be formed of GaAs.

[0182] The first conductive semiconductor layer 11 may be formed on the sacrificial layer 3 and may be formed into a multi-layer structure including at least one n-type semiconductor layer. The n-type semiconductor layer may include at least one of GaAs, GaInP, AlGaInP, and AlInP.

[0183] Reference Figure 3a , Figure 3b , Figure 4a and Figure 4b , an active layer 12 is formed on the first conductive semiconductor layer 11. The active layer 12 may be formed on the first conductive semiconductor layer 11, and may be an intrinsic semiconductor layer not doped with impurities. The active layer 12 may be formed in a single well structure or a multi-well structure.

[0184] In an embodiment of the present disclosure, the active layer 12 may include at least one of GaInP, AlGaInP, GaAs, AlGaAs, InGaAs, InGaAsP, InP, and InAs. In addition, the active layer 12 may emit light in a red or infrared band having a wavelength of 580nm to 900nm.

[0185] Reference Figure 3a , Figure 3b , Figures 4a to 4cA second conductive semiconductor layer 13 is formed on the active layer 12. The second conductive semiconductor layer 13 may be formed as a multilayer structure including at least one p-type semiconductor layer. The p-type semiconductor layer may include at least one of AlInP, GaInP and GaP.

[0186] In an embodiment of the present disclosure, the second conductive semiconductor layer 13 may be a transparent conductive layer doped with a conductive dopant such as Mg, and may include a GaP layer. The transparent conductive layer may include a low-concentration layer doped with Mg and having a thickness of several micrometers and a high-concentration layer doped with carbon and having a thickness of several hundred nanometers stacked sequentially. When the second conductive semiconductor layer 13 is formed by epitaxial growth, a second conductive semiconductor layer 13 having a thickness d3 of a predetermined level or greater (e.g., about 1.8 μm) is formed on the active layer 12 by controlling the stacking thickness (or distance) of the low-concentration layer and the high-concentration layer of the above-mentioned transparent conductive layer. However, the method of forming the second conductive semiconductor layer 13 on the active layer 12 is not limited to the above-mentioned embodiment, but a conventional formation method may be adopted. For example, the second conductive semiconductor layer 13 may be formed on the active layer 12 using any one method selected from the MOCVD method, the MBE method, the VPE method, and the LPE method.

[0187] As described above, the first conductive semiconductor layer 11 , the active layer 12 , and the second conductive semiconductor layer 13 sequentially stacked on the substrate 1 may form the emitter stack 10 ′.

[0188] Reference Figure 3a , Figure 3b , Figures 4a to 4d A mask layer 20 is formed on the second conductive semiconductor layer 13. The mask layer 20 may be used as a mask for continuously etching the emitter stack 10'.

[0189] At least one micro pattern FP may be formed on the mask layer 20. The micro pattern FP may be formed by forming a polymer layer on the mask layer 20 and then forming a pattern on the polymer layer at intervals ranging from a nanometer scale to a micrometer scale.

[0190] Reference Figure 3a , Figure 3b , Figures 4a to 4e , at least one mask pattern 20' is formed by patterning the mask layer 20 using the micropattern FP as a mask. The mask pattern 20' may be formed in a shape corresponding to the micropattern FP. The mask pattern 20' may be used as an etching mask for forming the emission stack pattern 10 by etching the emission stack body 10'. After the mask pattern 20' is formed, the micropattern FP may be removed by a conventional etching method.

[0191] Reference Figure 3a , Figure 3b , Figures 4a to 4f An etching process is performed using the mask pattern 20 ′ as an etching mask to pattern the emission stack 10 ′ at intervals ranging from a nanometer level to a micrometer level, thereby forming a plurality of emission stack patterns 10 .

[0192] In the above etching process, the region of the emitter stack 10' not corresponding to the mask pattern 20' may be etched to form a groove HM exposing the region A of the first conductive semiconductor layer 11 to the outside. The region of the emitter stack 10' corresponding to the mask pattern 20' is not etched.

[0193] The groove HM may have a shape recessed from the upper surface 13 b of the second conductive semiconductor layer 13 of each emission stack pattern 10 to the region A of the first conductive semiconductor layer 11 in one direction (eg, a vertical direction).

[0194] In an embodiment of the present disclosure, each of the emission stack patterns 10 may have a size ranging from a nanometer scale to a micrometer scale.

[0195] After performing the above etching process, the mask pattern 20' remaining on the emission stack pattern 10 may be removed by a conventional wet etching or dry etching method. However, the present disclosure may remove the mask pattern by a conventional removal method without being limited thereto.

[0196] Reference Figure 3a , Figure 3b , Figure 4a to Figure 4g , an insulating material layer 14' is formed on the emission stack pattern 10 and the region A of the first conductive semiconductor layer 11. The insulating material layer 14' may completely cover the upper surface of each emission stack pattern 10 and the side surface of each emission stack pattern 10. In addition, the insulating material layer 14' may completely cover the region A of the first conductive semiconductor layer 11 exposed to the outside.

[0197] The material used as the insulating material layer 14' may include SiO 2 、Si 3 N 4 、Al 2 O 3 and TiO 2 Any one selected from the group consisting of, but not limited to.

[0198] Reference Figure 3a , Figure 3b , Figure 4a to Figure 4h An etching process is performed to remove a portion of the insulating material layer 14 ′ formed on the substrate 1 , thereby forming an insulating film 14 . The insulating film 14 may be finally formed to cover the side surface of each emission stack pattern 10 .

[0199] Due to the above-mentioned etching process, the upper surface 13b of the second conductive semiconductor layer 13 may be exposed to the outside. In this case, the upper surface 14b of the insulating film 14 and the upper surface 13b of the second conductive semiconductor layer 13 may be disposed and / or formed at the same surface (or the same line). In addition, the region A of the first conductive semiconductor layer 11 may be exposed to the outside by the above-mentioned etching process.

[0200] Through the above-mentioned etching process, a light emitting element LD including an emission stack pattern 10 and an insulating film 14 surrounding the periphery (or surface) of each emission stack pattern 10 can be finally formed. In this case, the upper surface 13b of the second conductive semiconductor layer 13 exposed to the outside can become the upper surface LD_2 of each light emitting element LD.

[0201] Reference Figure 3a , Figure 3b , Figures 4a to 4i , the light emitting element LD is separated from the substrate 1 by a chemical lift-off (CLO) method. For example, the sacrificial layer 3 may be removed to separate the light emitting element LD from the substrate 1.

[0202] Through the above-described manufacturing process, each finally manufactured light emitting element LD may include an active layer 12 located in the middle (or center) of each light emitting element LD along the length L of each light emitting element LD or positioned adjacent to the middle (or center) thereof.

[0203] Figure 5 is a diagram showing a display device according to an embodiment of the present disclosure (specifically, using Figure 1a and Figure 1b or Figure 3a and Figure 3b Schematic plan view of a display device in which the light-emitting element shown in FIG. 1 is used as a light source.

[0204] For illustration purposes, Figure 5 The display area on which the image is displayed schematically shows the structure of the display device. In some embodiments, although not shown, at least one driving circuit (eg, a scan driver and a data driver) and / or a plurality of signal lines may be further provided in the display device.

[0205] Reference Figure 1a , Figure 1b , Figure 3a , Figure 3b and Figure 5 A display device according to an embodiment of the present disclosure may include a substrate SUB, a plurality of pixels PXL disposed in the substrate SUB and including at least one light emitting element LD, a driver (not shown) disposed on the substrate SUB and driving the pixels PXL, and a line assembly (not shown) combining the pixels PXL with the driver.

[0206] The display device can be classified into a passive matrix type display device and an active matrix type display device according to a method of driving the light emitting element LD. For example, in the case where the display device is implemented as an active matrix type, each pixel PXL may include a driving transistor configured to control the amount of current to be supplied to the light emitting element LD and a switching transistor configured to transmit a data signal to the driving transistor.

[0207] Recently, considering resolution, contrast and operating speed, an active matrix display device capable of selectively turning on each pixel PXL has become mainstream. However, the present disclosure is not limited thereto. For example, a passive matrix display device in which the pixels PXL can be turned on in groups may also employ components (e.g., a first electrode and a second electrode) for driving the light emitting element LD.

[0208] The substrate SUB may include a display area DA and a non-display area NDA.

[0209] In an embodiment, the display area DA may be disposed in the central portion of the display device, and the non-display area NDA may be disposed in the peripheral portion of the display device to surround the display area DA. The positions of the display area DA and the non-display area NDA are not limited thereto, and their positions may vary.

[0210] The display area DA may be an area in which pixels PXL for displaying an image are disposed. The non-display area NDA may be an area in which a driver for driving the pixels PXL and a portion of a line assembly for coupling the pixels PXL to the driver are disposed.

[0211] The display area DA may have various shapes. For example, the display area DA may be set to various forms, such as a closed polygon including sides formed by straight lines, a circle, an ellipse, etc. including sides formed by curved lines, and a semicircle, a semiellipse, etc. including sides formed by straight lines and curved lines.

[0212] The non-display area NDA may be disposed at at least one side of the display area DA. In an embodiment of the present disclosure, the non-display area NDA may surround the periphery of the display area DA.

[0213] The substrate SUB may include a transparent insulating material to allow light to be transmitted. The substrate SUB may be a rigid substrate. For example, the substrate SUB may be one of a glass substrate, a quartz substrate, a glass ceramic substrate, and a crystallized glass substrate.

[0214] The substrate SUB may be a flexible substrate. Here, the substrate SUB may be a film substrate or a plastic substrate including a polymer organic material. For example, the substrate SUB may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyether sulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate. However, the material forming the substrate SUB may be changed in various ways and may include, for example, fiber reinforced plastic (FRP).

[0215] The pixels PXL may be disposed in the display area DA on the substrate SUB. Each pixel PXL displays an image, and a plurality of pixels may be provided.

[0216] Each pixel PXL may include a light emitting element LD configured to be driven in response to a corresponding scan signal and a corresponding data signal. The light emitting element LD may have a small size ranging from micrometer level to nanometer level and may be connected in parallel to a light emitting element LD disposed adjacent thereto. The light emitting element LD may form a light source of each pixel PXL.

[0217] In addition, each pixel PXL may include a plurality of sub-pixels. For example, each pixel PXL may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. In an embodiment, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may emit light of different colors. For example, the first sub-pixel SP1 may be a first color sub-pixel for emitting light of a first color, the second sub-pixel SP2 may be a second color sub-pixel for emitting light of a second color, and the third sub-pixel SP3 may be a third color sub-pixel for emitting light of a third color. Here, the light of the first color may be red light, the light of the second color may be green light, and the light of the third color may be blue light, but the present disclosure is not limited thereto. However, the color, type, and / or number of sub-pixels forming each pixel PXL are not particularly limited. For example, the color of the light emitted from each sub-pixel may be changed in various ways. Although in Figure 5 , an embodiment in which the pixels PXL are arranged in a stripe shape or a matrix shape in the display area DA is shown, but the present disclosure is not limited thereto. For example, the display area DA of the display device may have various well-known pixel arrangement shapes.

[0218] The driver may provide a signal to each pixel PXL through the line assembly and thus control the operation of each pixel PXL. Figure 5 , the wire components are omitted for illustration purposes.

[0219] The driver may include a scan driver configured to provide a scan signal to the pixel PXL through a scan line, an emission driver configured to provide an emission control signal to the pixel PXL through an emission control line, a data driver configured to provide a data signal to the pixel PXL through a data line, and a timing controller. The timing controller may control the scan driver, the emission driver, and the data driver.

[0220] Figures 6a to 6c is a diagram showing various embodiments including Figure 5 Circuit diagram of a pixel region of a first sub-pixel in one of the pixels shown in .

[0221] exist Figures 6a to 6c In the embodiment of the present invention, each of the first to third sub-pixels included in one pixel may be configured as an active pixel. However, the type, structure and / or driving method of each of the first to third sub-pixels are not particularly limited. For example, each of the first to third sub-pixels may be configured as a pixel of a passive or active display device of various known structures.

[0222] exist Figures 6a to 6c In the embodiment of the present invention, the first to third sub-pixels included in one pixel may have substantially the same or similar structures. Hereinafter, for convenience, the first sub-pixel among the first to third sub-pixels will be described as a representative.

[0223] First, refer to Figure 1a , Figure 5 and Figure 6a The first sub-pixel SP1 may include a light emitting element (hereinafter, also referred to as an emission area) EMA generating light with brightness corresponding to a data signal and a pixel driving circuit 144 driving the light emitting element EMA.

[0224] In an embodiment, the light emitting assembly EMA may include a plurality of light emitting elements LD connected in parallel to each other between a line to which a first driving power source VDD is applied and a line to which a second driving power source VSS is applied. Here, the first driving power source VDD and the second driving power source VSS may have different potentials. For example, the first driving power source VDD may be set to a high potential power source, and the second driving power source VSS may be set to a low potential power source. Here, during the light emitting period of the first sub-pixel SP1, the potential difference between the first driving power source VDD and the second driving power source VSS may be set to a threshold voltage of the light emitting element LD or greater. The first electrode (e.g., an anode electrode) of each light emitting element LD may be connected to the first driving power source VDD via the pixel driving circuit 144, and the second electrode (e.g., a cathode electrode) of each light emitting element LD may be connected to the second driving power source VSS.

[0225] Each light emitting element LD may emit light with brightness corresponding to a driving current controlled by the pixel driving circuit 144 .

[0226] although Figures 6a to 6c An embodiment in which the light emitting elements LD are connected in parallel to each other in the same direction (e.g., forward direction) between the first driving power supply VDD and the second driving power supply VSS is shown, but the present disclosure is not limited thereto. For example, in another embodiment, some of the light emitting elements LD may be connected to each other in the forward direction between the first driving power supply VDD and the second driving power supply VSS, and other light emitting elements LD may be connected to each other in the reverse direction. One of the first driving power supply VDD and the second driving power supply VSS may be supplied in the form of an AC voltage. In this case, the light emitting element LD may emit light alternately for each group having the same binding direction. Alternatively, in another embodiment, the first sub-pixel SP1 may include only a single light emitting element LD.

[0227] In the embodiment of the present disclosure, the pixel driving circuit 144 may include a first transistor T1, a second transistor T2, and a storage capacitor Cst. However, the structure of the pixel driving circuit 144 is not limited to Figure 6a The embodiment shown in .

[0228] The first terminal of the first transistor (switching transistor) T1 is connected to the data line Dj, and the second terminal thereof is connected to the first node N1. Here, the first terminal and the second terminal of the first transistor T1 are different from each other. For example, if the first terminal is a source electrode, the second terminal may be a drain electrode. The gate electrode of the first transistor T1 is connected to the scan line Si.

[0229] When a scan signal having a voltage (e.g., a low level voltage) capable of turning on the first transistor T1 is supplied from the scan line Si, the first transistor T1 is turned on to electrically connect the data line Dj to the first node N1. Here, a data signal of a corresponding frame is supplied to the data line Dj, thereby transmitting the data signal to the first node N1. The data signal transmitted to the first node N1 is charged in the storage capacitor Cst.

[0230] The first terminal of the second transistor (driving transistor) T2 is connected to the first driving power supply VDD, and the second terminal thereof is electrically connected to the first electrode of each light emitting element LD. The gate electrode of the second transistor T2 is connected to the first node N1. Such a second transistor T2 controls the amount of driving current supplied to the light emitting element LD in response to the voltage of the first node N1.

[0231] One electrode of the storage capacitor Cst is connected to the first driving power source VDD and the other electrode thereof is connected to the first node N1. The storage capacitor Cst charges a voltage corresponding to the data signal supplied to the first node N1 and maintains the charged voltage until a data signal of a subsequent frame is supplied.

[0232] To illustrate, Figure 6a A pixel driving circuit 144 having a relatively simple structure is shown, which includes a first transistor T1 configured to transmit a data signal to a first subpixel SP1, a storage capacitor Cst configured to store the data signal, and a second transistor T2 configured to supply a driving current corresponding to the data signal to the light emitting element LD.

[0233] However, the present disclosure is not limited thereto, and the structure of the pixel driving circuit 144 may be changed in various ways. For example, the pixel driving circuit 144 may further include at least one transistor element (such as a transistor element configured to compensate for the threshold voltage of the second transistor T2, a transistor element configured to initialize the first node N1, and / or a transistor element configured to control the emission time of the light emitting element LD) or other circuit elements (such as a boost capacitor for boosting the voltage of the first node N1).

[0234] In addition, despite the Figure 6a , the transistors (e.g., the first transistor T1 and the second transistor T2) included in the pixel driving circuit 144 have been shown to be formed of P-type transistors, but the present disclosure is not limited thereto. In other words, at least one of the first transistor T1 and the second transistor T2 included in the pixel driving circuit 144 may be changed to an N-type transistor.

[0235] Next, refer to Figure 1a , Figure 5 and Figure 6b , the first transistor T1 and the second transistor T2 according to the embodiment of the present disclosure may be formed by N-type transistors. In addition to the change in the connection position of some components caused by the change in the type of transistor, Figure 6b The configuration and operation of the pixel driving circuit 144 shown in FIG. Figure 6a The configuration and operation of the pixel driving circuit 144 are similar. Therefore, detailed descriptions thereon will be omitted.

[0236] In the embodiment of the present disclosure, the configuration of the pixel driving circuit 144 is not limited to Figure 6a and Figure 6b For example, the pixel driving circuit 144 can be connected with Figure 6c The embodiment shown in FIG. 1 is constructed in the same manner.

[0237] Reference Figure 1a , Figure 5 and Figure 6c , the pixel driving circuit 144 can be connected to the scan line Si and the data line Dj of the first subpixel SP1. For example, if the first subpixel SP1 is disposed in the i-th row and the j-th column of the display area DA, the pixel driving circuit 144 of the first subpixel SP1 can be connected to the i-th scan line Si and the j-th data line Dj of the display area DA.

[0238] In an embodiment, the pixel driving circuit 144 may also be connected to at least one different scan line. For example, the first sub-pixel SP1 disposed in the i-th row of the display area DA may also be connected to the i-1th scan line Si-1 and / or the i+1th scan line Si+1.

[0239] In an embodiment, the pixel driving circuit 144 may be connected not only to the first driving power source VDD and the second driving power source VSS, but also to a third power source. For example, the pixel driving circuit 144 may also be connected to an initialization power source Vint.

[0240] The pixel driving circuit 144 may include first to seventh transistors T1 to T7 and a storage capacitor Cst.

[0241] The first transistor (driving transistor) T1 may include a first terminal (e.g., source electrode) connected to the first driving power source VDD via a fifth transistor T5 and a second terminal (e.g., drain electrode) connected to the first end of the light emitting element LD via a sixth transistor T6. The gate electrode of the first transistor T1 may be connected to the first node N1. The first transistor T1 controls a driving current flowing between the first driving power source VDD and the second driving power source VSS via the light emitting element LD in response to a voltage of the first node N1.

[0242] The second transistor (switching transistor) T2 is connected between the first terminal of the first transistor T1 and the j-th data line Dj connected to the first sub-pixel SP1. The gate electrode of the second transistor T2 is connected to the i-th scan line Si connected to the first sub-pixel SP1. When a scan signal having a gate-on voltage (e.g., a low-level voltage) is supplied from the i-th scan line Si, the second transistor T2 is turned on to electrically connect the j-th data line Dj to the first terminal of the first transistor T1. Therefore, if the second transistor T2 is turned on, the data signal supplied from the j-th data line Dj is transmitted to the first transistor T1.

[0243] The third transistor T3 is connected between the second terminal of the first transistor T1 and the first node N1. The gate electrode of the third transistor T3 is connected to the i-th scan line Si. When a scan signal having a gate-on voltage is supplied from the i-th scan line Si, the third transistor T3 is turned on to electrically connect the drain of the first transistor T1 to the first node N1. Therefore, when the third transistor T3 is turned on, the first transistor T1 is connected in the form of a diode.

[0244] The fourth transistor T4 is connected between the first node N1 and the initialization power supply Vint. The gate electrode of the fourth transistor T4 is connected to the previous scan line, for example, the i-1th scan line Si-1. When the scan signal of the gate-on voltage is supplied to the i-1th scan line Si-1, the fourth transistor T4 is turned on, so that the voltage of the initialization power supply Vint is transmitted to the first node N1. Here, the initialization power supply Vint may have a voltage equal to or less than the minimum voltage of the data signal.

[0245] The fifth transistor T5 is connected between the first driving power supply VDD and the first transistor T1. The gate electrode of the fifth transistor T5 is connected to the corresponding emission control line, for example, the i-th emission control line Ei. When the emission control signal having the gate cut-off voltage is supplied to the i-th emission control line Ei, the fifth transistor T5 is turned off, and in other cases, the fifth transistor T5 is turned on.

[0246] The sixth transistor T6 is connected between the first transistor T1 and the second node N2 connected to the first end of the light emitting element LD. The gate electrode of the sixth transistor T6 is connected to the i-th emission control line Ei. When the emission control signal having the gate-off voltage is supplied to the i-th emission control line Ei, the sixth transistor T6 is turned off, and in other cases, the sixth transistor T6 is turned on.

[0247] The seventh transistor T7 is connected between the second node N2 and the initialization power supply Vint. The gate electrode of the seventh transistor T7 is connected to any one of the scan lines of the subsequent stage, for example, to the i+1th scan line Si+1. When a scan signal having a gate-on voltage is supplied to the i+1th scan line Si+1, the seventh transistor T7 is turned on, so that the voltage of the initialization power supply Vint is supplied to the first end of the light emitting element LD.

[0248] The storage capacitor Cst is connected between the first driving power source VDD and the first node N1. The storage capacitor Cst stores the data signal supplied to the first node N1 during each frame period and a voltage corresponding to the threshold voltage of the first transistor T1.

[0249] For convenience, all of the first transistor T1 to the seventh transistor T7 are Figure 6cFor example, at least one of the first to seventh transistors T1 to T7 included in the pixel driving circuit 144 may be changed to an N-type transistor, or all of the first to seventh transistors T1 to T7 may be changed to N-type transistors.

[0250] In addition, the structure of the first sub-pixel SP1 that can be applied to the present disclosure is not limited to Figures 6a to 6c , and each sub-pixel may have various well-known structures. For example, the pixel driving circuit 144 included in each sub-pixel may be formed by a well-known pixel circuit that may have various structures and / or may be operated by various driving schemes. In another embodiment of the present disclosure, each sub-pixel may be constructed in a passive light-emitting display device or the like. In this case, the pixel driving circuit 144 may be omitted, and the opposite ends of the light-emitting element LD included in the emission area EMA may be directly connected to the scan line Si, the data line Dj, the line to which the first drive power VDD is applied, the line to which the second drive power VSS is applied, and / or a predetermined control line.

[0251] Figure 7 It is schematically shown that the Figure 5 A plan view of first to third sub-pixels in one of the pixels shown in FIG. Figure 8 It is along Figure 7 A cross-sectional view taken along line II' of Figure 9a yes Figure 8 An enlarged cross-sectional view of part EA1, Figure 9b It shows that Figure 9a An enlarged cross-sectional view of a state in which a part of the insulating film of the light emitting element is separated, Fig.10 Shown include Figure 3a The light emitting element shown in FIG. 1 is a part of the display element layer and is related to Figure 8 The enlarged cross-sectional view of the portion EA1 corresponds to, and Fig.11 It is along Figure 7 The line I-I' intercepts Figure 8 The partition wall shown in FIG. 1 is a sectional view of a partition wall realized in different forms.

[0252] For convenience, Figure 7 Illustration of transistors connected to light-emitting elements and signal lines connected to the transistors has been omitted.

[0253] in addition, Figure 7 , Figure 8 , Figure 9a , Figure 9b , Fig.10 and Fig.11The structure of one pixel is simplified and illustrated, for example, each electrode is illustrated as a single electrode layer and each insulating layer is illustrated as a single insulating layer. However, the present disclosure is not limited thereto.

[0254] In addition, although for convenience, Figure 8 , Figure 9a , Figure 9b , Fig.10 and Fig.11 Only one first light-emitting element aligned between the 1-1 electrode and the second electrode among the light-emitting elements is shown, but one first light-emitting element may replace Figure 7 Each of the multiple light emitting elements shown in .

[0255] Reference Figure 5 , Figure 7 , Figure 8 , Figure 9a , Figure 9b , Fig.10 and Fig.11 , a display device according to an embodiment of the present disclosure may include a substrate SUB on which a plurality of pixels PXL are disposed.

[0256] Each pixel PXL may include a first subpixel SP1, a second subpixel SP2, and a third subpixel SP3 disposed in a substrate SUB. In an embodiment of the present disclosure, the first subpixel SP1 may be a red subpixel, the second subpixel SP2 may be a green subpixel, and the third subpixel SP3 may be a blue subpixel. However, the present disclosure is not limited thereto. In an embodiment, the first subpixel SP1 may be a green subpixel or a blue subpixel, the second subpixel SP2 may be a blue subpixel or a red subpixel, and the third subpixel SP3 may be a red subpixel or a green subpixel.

[0257] Each of the first to third subpixels SP1 to SP3 may include an emission area EMA that emits light and a peripheral area PPA located around the emission area EMA. The emission area EMA may refer to an area in which light is emitted from the light emitting element LD arranged (or disposed) in each subpixel, and the peripheral area PPA may refer to an area in which light is not emitted.

[0258] In an embodiment of the present disclosure, the pixel area of ​​each of the first to third sub-pixels SP1 to SP3 may include an emission area EMA and a peripheral area PPA of the corresponding sub-pixel. More specifically, the pixel area of ​​the first sub-pixel SP1 may include an emission area EMA of the first sub-pixel SP1 and a peripheral area PPA located around the emission area EMA. The pixel area of ​​the second sub-pixel SP2 may include an emission area EMA of the second sub-pixel SP2 and a peripheral area PPA located around the emission area EMA. The pixel area of ​​the third sub-pixel SP3 may include an emission area EMA of the third sub-pixel SP3 and a peripheral area PPA located around the emission area EMA.

[0259] In a pixel region of each of the first to third sub-pixels SP1 to SP3 , a substrate SUB, a pixel circuit layer PCL, and a display element layer DPL may be disposed.

[0260] The pixel circuit layer PCL of each of the first to third sub-pixels SP1 to SP3 may include a buffer layer BFL disposed on the substrate SUB, at least one transistor disposed on the buffer layer BFL, and a driving voltage line DVL. In addition, the pixel circuit layer PCL of each of the first to third sub-pixels SP1 to SP3 may further include a passivation layer PSV disposed on the transistor and the driving voltage line DVL.

[0261] The substrate SUB may include a transparent insulating material to allow light to be transmitted.

[0262] The substrate SUB may be a rigid substrate. For example, the substrate SUB may be one of a glass substrate, a quartz substrate, a glass ceramic substrate, and a crystallized glass substrate.

[0263] The substrate SUB may be a flexible substrate. Here, the substrate SUB may be a film substrate or a plastic substrate including a polymer organic material. For example, the substrate SUB may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyether sulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate. However, the material forming the substrate SUB is not limited to the above-described embodiments and may be changed in various ways.

[0264] The buffer layer BFL may be disposed on the substrate SUB and may prevent impurities from diffusing into the transistor. The buffer layer BFL may be omitted according to a material or process condition of the substrate SUB.

[0265] The transistor may include a driving transistor T1 and a switching transistor T2, the driving transistor T1 being electrically connected to some light emitting elements LD provided in each display element layer DPL of each sub-pixel to drive the light emitting elements LD, and the switching transistor T2 switching the driving transistor T1. In an embodiment, in addition to the above-mentioned driving transistor T1 and the switching transistor T2, the transistor included in the pixel circuit layer PCL may further include an additional transistor, such as a transistor for compensating for a threshold voltage of the switching transistor T2, or a transistor for controlling the emission time of each light emitting element LD.

[0266] Each of the driving transistor T1 and the switching transistor T2 may include a semiconductor layer SCL, a gate electrode GE, a first terminal EL1, and a second terminal EL2. The first terminal EL1 may be any one of a source electrode and a drain electrode, and the second terminal EL2 may be the other of the source electrode and the drain electrode. For example, when the first terminal EL1 is a drain electrode, the second terminal EL2 may be a source electrode.

[0267] The semiconductor layer SCL may be disposed on the buffer layer BFL. The semiconductor layer SCL may include a first region in contact with the first terminal EL1 and a second region in contact with the second terminal EL2. A region between the first region and the second region may be a channel region.

[0268] The semiconductor layer SCL may be a semiconductor pattern formed of polysilicon, amorphous silicon, an oxide semiconductor, etc. The channel region may be an intrinsic semiconductor as a semiconductor pattern not doped with impurities. Each of the source region and the drain region may be a semiconductor pattern doped with impurities.

[0269] The gate electrode GE may be disposed on the semiconductor layer SCL with the gate insulating layer GI interposed therebetween.

[0270] The first terminal EL1 and the second terminal EL2 may respectively contact the first region and the second region of the semiconductor layer SCL through corresponding contact holes passing through the interlayer insulating layer ILD and the gate insulating layer GI.

[0271] In an embodiment of the present disclosure, at least one transistor (e.g., a driving transistor T1 and a switching transistor T2) included in the pixel circuit layer PCL of each sub-pixel may be formed by an LTPS thin film transistor. However, according to an embodiment, the transistor may be formed by an oxide semiconductor thin film transistor, without being limited thereto. In addition, in an embodiment of the present disclosure, it has been shown that the driving transistor T1 and the switching transistor T2 are thin film transistors having a top gate structure, but the present disclosure is not limited thereto. According to an embodiment, the driving transistor T1 and the switching transistor T2 may be thin film transistors having a bottom gate structure.

[0272] The driving voltage line DVL may be disposed on the interlayer insulating layer ILD, but the present disclosure is not limited thereto. In an embodiment, the driving voltage line DVL may be disposed on any one of the insulating layers included in the pixel circuit layer PCL. The second driving power source VSS ( Figure 6a ) can be applied to the driving voltage line DVL.

[0273] The passivation layer PSV may include a first contact hole CH1 exposing a portion of the first terminal EL1 of the driving transistor T1 and a second contact hole CH2 exposing a portion of the driving voltage line DVL. The passivation layer PSV may include at least one of an inorganic insulating layer formed of an inorganic material and / or an organic insulating layer formed of an organic material. In an embodiment, the passivation layer PSV may be provided in the form of an inorganic insulating layer covering the driving transistor T1 and the switching transistor T2 and an organic insulating layer provided on the inorganic insulating layer. Here, the inorganic insulating layer may include silicon oxide (SiO x ) and silicon nitride (SiN x ). The organic insulating layer may include an organic insulating material that can transmit light. The organic insulating layer may include, for example, at least one of polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, and benzocyclobutene resin.

[0274] Next, the display element layer DPL of each of the first sub-pixel SP1 , the second sub-pixel SP2 , and the third sub-pixel SP3 will be described.

[0275] The display element layer DPL of each subpixel may include a bank pattern (or partition wall) PW, first and second electrodes REL1 and REL2 , first and second connection lines CNL1 and CNL2 , first and second contact electrodes CNE1 and CNE2 , and a plurality of light emitting elements LD.

[0276] The partition wall PW may be disposed on the passivation layer PSV in the emission area EMA of each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. Although not directly shown in the drawings, a dam (or bank) made of the same material as that of the partition wall PW may be formed and / or disposed in the peripheral area PPA between adjacent sub-pixels to define the emission area EMA of each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3.

[0277] The partition wall PW may be spaced apart from the adjacent partition wall PW on the passivation layer PSV by a predetermined distance. Two adjacent partition walls PW may be disposed on the passivation layer PSV to be spaced apart from each other by a length L of one light emitting element LD or more. Figure 8As shown in , the partition wall PW may include a curved surface having a cross-section having a shape such as a semicircle or a semi-ellipse whose width narrows from one surface of the passivation layer PSV toward the top, but the present disclosure is not limited thereto.

[0278] In an embodiment, Fig.11 As shown in , the partition wall PW may have a trapezoidal cross section whose width narrows from one surface of the passivation layer PSV toward the top. When viewed in cross section, the shape of the partition wall PW is not limited to the above-described embodiment, and may be variously changed within a range capable of improving the efficiency of light emitted from each light emitting element LD. Two adjacent partition walls PW may be disposed at the same plane of the passivation layer PSV and may have the same height.

[0279] Each of the first electrode REL1 and the second electrode REL2 may be disposed in the emission area EMA of each of the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3 and may extend in the second direction DR2 (eg, a “vertical direction”). The first electrode REL1 and the second electrode REL2 may be disposed at the same plane and may be spaced apart from each other.

[0280] The first electrode REL1 may be connected to the first connection line CNL1. More specifically, the first electrode REL1 may be integrally connected to the first connection line CNL1. In an embodiment of the present disclosure, the first electrode REL1 may include a 1-1 electrode REL1_1 and a 1-2 electrode REL1_2 branching from the first connection line CNL1 extending in the first direction DR1 along the second direction DR2. The 1-1 electrode REL1_1, the 1-2 electrode REL1_2, and the first connection line CNL1 may be integrally provided to be electrically and / or physically connected to each other. In the case where the first electrode REL1 and the first connection line CNL1 are integrally provided and / or formed, the first connection line CNL1 may be regarded as a region of the first electrode REL1. However, the present disclosure is not limited thereto. In an embodiment, the first electrode REL1 and the first connection line CNL1 may be formed separately so that they may be electrically connected to each other through a contact hole (not shown).

[0281] The second electrode REL2 may extend in the second direction DR2 and may be electrically connected to the second connection line CNL2. In an embodiment of the present disclosure, the second electrode REL2 may branch from the second connection line CNL2 along the second direction DR2. Therefore, the second electrode REL2 and the second connection line CNL2 may be integrally provided to be electrically and / or physically connected to each other. In the case where the second electrode REL2 and the second connection line CNL2 are integrally formed and / or provided, the second connection line CNL2 may be regarded as a region of the second electrode REL2. However, the present disclosure is not limited thereto. In an embodiment, the second electrode REL2 and the second connection line CNL2 may be formed separately so that they may be electrically connected to each other through a contact hole (not shown).

[0282] like Figure 7 As shown in , the first electrode REL1 can be electrically and / or physically connected to any one of the two ends EP1 and EP2 of each light emitting element LD through the first contact electrode CNE1. However, the present disclosure is not limited thereto. In an embodiment, the first electrode REL1 can be in direct contact with any one of the two ends EP1 and EP2 of each light emitting element LD to be electrically and / or physically connected to each light emitting element LD.

[0283] In addition, if Figure 7 As shown in, the second electrode REL2 can be electrically and / or physically connected to the remaining one of the two ends EP1 and EP2 of each light emitting element LD through the second contact electrode CNE2. However, the present disclosure is not limited thereto. In an embodiment, the second electrode REL2 can be in direct contact with any one of the two ends EP1 and EP2 of each light emitting element LD to be electrically and / or physically connected to each light emitting element LD.

[0284] Each of the first electrode REL1 and the second electrode REL2 may function as an alignment electrode for aligning the light emitting element LD in the emission area EMA of each of the first subpixel SP1 , the second subpixel SP2 , and the third subpixel SP3 .

[0285] Before the light emitting element LD is aligned in the emission area EMA of each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, a first alignment voltage may be applied to the first electrode REL1 through the first connection line CNL1, and a second alignment voltage may be applied to the second electrode REL2 through the second connection line CNL2. The first alignment voltage and the second alignment voltage may have different voltage levels. When predetermined alignment voltages having different voltage levels are applied to the first electrode REL1 and the second electrode REL2, respectively, an electric field may be formed between the first electrode REL1 and the second electrode REL2. The light emitting element LD may be aligned between the first electrode REL1 and the second electrode REL2 by the electric field.

[0286] In a plan view, the second electrode REL2 may be disposed between the 1-1 electrode REL1_1 and the 1-2 electrode REL1_2 and may be spaced apart from each of the 1-1 electrode REL1_1 and the 1-2 electrode REL1_2 by a predetermined distance.

[0287] After the light emitting element LD is aligned in the emission area EMA of each of the first subpixel SP1 , the second subpixel SP2 , and the third subpixel SP3 , each of the first electrode REL1 and the second electrode REL2 may function as a driving electrode for driving the light emitting element LD.

[0288] Each of the first electrode REL1 and the second electrode REL2 may include a material having a predetermined reflectivity so that light emitted from both ends EP1 and EP2 of each light emitting element LD travels in a direction in which an image of the display device is displayed. In an embodiment of the present disclosure, the first electrode REL1, the second electrode REL2, the first connection line CNL1, and the second connection line CNL2 may be disposed at the same layer and may be made of the same material.

[0289] Each of the first electrode REL1, the second electrode REL2, the first connection line CNL1, and the second connection line CNL2 may be made of a conductive material having a predetermined reflectivity. The conductive material may include a metal such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Ti, or an alloy thereof, a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin zinc oxide (ITZO), and a conductive polymer such as PEDOT. The material of each of the first electrode REL1, the second electrode REL2, the first connection line CNL1, and the second connection line CNL2 is not limited to the above materials.

[0290] In addition, each of the first electrode REL1, the second electrode REL2, the first connection line CNL1, and the second connection line CNL2 may be formed of a single layer, but the present disclosure is not limited thereto. In an embodiment, each of the first electrode REL1, the second electrode REL2, the first connection line CNL1, and the second connection line CNL2 may be formed as a multilayer structure in which two or more of metals, alloys, conductive oxides, and conductive polymers are stacked. Each of the first electrode REL1, the second electrode REL2, the first connection line CNL1, and the second connection line CNL2 may be formed as a multilayer structure having at least two layers to minimize a voltage drop caused by a signal delay when a signal is transmitted to both ends EP1 and EP2 of each light emitting element LD. When each of the first electrode REL1, the second electrode REL2, the first connection line CNL1, and the second connection line CNL2 is formed as a multilayer structure, each of the first electrode REL1, the second electrode REL2, the first connection line CNL1, and the second connection line CNL2 may include, for example, first to third conductive layers stacked sequentially. Here, the first conductive layer may be formed of ITO, the second conductive layer may be formed of Ag, and the third conductive layer may be formed of ITO. However, the present disclosure is not limited thereto. According to the embodiment, the material of each of the first to third conductive layers may be changed in any manner.

[0291] In an embodiment of the present disclosure, each of the first electrode REL1 and the second electrode REL2 may be disposed and / or formed on the partition wall PW to have a shape corresponding to the shape of the partition wall PW. Therefore, light emitted from both ends EP1 and EP2 of each light emitting element LD may be reflected by the first electrode REL1 and the second electrode REL2 to further move in the display direction of the display device. Therefore, the efficiency of light emitted from each light emitting element LD may be further enhanced.

[0292] In the embodiment of the present disclosure, the partition wall PW, the first electrode REL1 and the second electrode REL2 may function as a reflective member that allows light emitted from each light emitting element LD to travel in a display direction of the display device, thereby improving light emission efficiency of the light emitting element LD.

[0293] Any one of the first electrode REL1 and the second electrode REL2 may be an anode electrode, and the other may be a cathode electrode. In an embodiment of the present disclosure, the first electrode REL1 may be an anode electrode, and the second electrode REL2 may be a cathode electrode.

[0294] In the above embodiment, the first electrode REL1 is configured to include two electrodes branched from the first connection line CNL1 along the second direction DR2, for example, the 1-1 electrode REL1_1 and the 1-2 electrode REL1_2. However, the present disclosure is not limited thereto. In an embodiment, the first electrode REL1 may include at least one electrode branched from the first connection line CNL1 in the second direction DR2.

[0295] The first contact electrode CNE1 may be disposed on the first electrode REL1 to stably electrically and / or physically connect the first electrode REL1 and one of the two ends EP1 and EP2 of each light emitting element LD.

[0296] The first contact electrode CNE1 may be made of a transparent conductive material so that light emitted from each light emitting element LD and reflected by the first electrode REL1 to the display direction of the display device may move in the display direction without loss. The first contact electrode CNE1 may cover the first electrode REL1 and overlap the first electrode REL1. In addition, the first contact electrode CNE1 may cover and overlap one of the two ends EP1 and EP2 of each light emitting element LD. The first contact electrode CNE1 may include a 1-1st contact electrode CNE1_1 disposed and / or formed on the 1-1st electrode REL1_1 and a 1-2nd contact electrode CNE1_2 disposed and / or formed on the 1-2nd electrode REL1_2.

[0297] The third insulating layer INS3 may be disposed on the first contact electrode CNE1 to cover the first contact electrode CNE1. The third insulating layer INS3 may prevent the first contact electrode CNE1 from being exposed to the outside, thereby preventing the first contact electrode CNE1 from being corroded. The third insulating layer INS3 may include an inorganic insulating layer made of an inorganic material or an organic insulating layer made of an organic material. Although the third insulating layer INS3 may be formed of a single layer as shown in the drawings, the present disclosure is not limited thereto. In an embodiment, the third insulating layer INS3 may be formed into a multilayer structure. When the third insulating layer INS3 is formed into a multilayer structure, the third insulating layer INS3 may have a structure formed by alternately stacking at least one inorganic insulating layer and at least one organic insulating layer.

[0298] The second contact electrode CNE2 may be disposed on the second electrode REL2 to stably electrically and / or physically connect the second electrode REL2 to the remaining one of the two ends EP1 and EP2 of each light emitting element LD. In a plan view, the second contact electrode CNE2 may cover the second electrode REL2 and overlap with the second electrode REL2. In addition, the second contact electrode CNE2 may overlap with the remaining one of the two ends EP1 and EP2 of each light emitting element LD. The second contact electrode CNE2 may be made of the same material as that of the first contact electrode CNE1, but the present disclosure is not limited thereto.

[0299] The fourth insulating layer INS4 may be disposed on the second contact electrode CNE2 to cover the second contact electrode CNE2. The fourth insulating layer INS4 may prevent the second contact electrode CNE2 from being exposed to the outside, thereby preventing the second contact electrode CNE2 from being corroded. The fourth insulating layer INS4 may be formed of an inorganic insulating layer or an organic insulating layer.

[0300] An overcoat layer OC may be disposed on the fourth insulating layer INS4. The overcoat layer OC may be an encapsulation layer that reduces steps generated by the partition wall PW, the first and second electrodes REL1 and REL2, and the first and second contact electrodes CNE1 and CNE2 disposed under the overcoat layer, and prevents oxygen and moisture from entering the light emitting element LD. In an embodiment, the overcoat layer OC may be omitted in consideration of design conditions of a display device, etc.

[0301] In embodiments, a capping layer CPL may be formed and / or disposed in the emission area EMA of each sub-pixel.

[0302] The cap layer CPL may be disposed between the first electrode REL1 and the first contact electrode CNE1 and between the second electrode REL2 and the second contact electrode CNE2, respectively. The cap layer CPL may prevent damage to the corresponding electrode due to a failure occurring during a manufacturing process of the display device, and may further enhance adhesion between the corresponding electrode and the passivation layer PSV. The cap layer CPL may be formed of a transparent conductive material such as indium zinc oxide (IZO) to minimize the loss of light emitted from each light emitting element LD and then reflected by the corresponding electrode in a display direction of the display device.

[0303] Each light emitting element LD may be a light emitting diode made of a material having an inorganic crystal structure and having an ultra-small size (eg, corresponding to a range from a nanometer scale to a micrometer scale).

[0304] In an embodiment of the present disclosure, the light emitting element LD may include a first light emitting element LD1 and a second light emitting element LD2. The first light emitting element LD1 may be aligned between the 1-1 electrode REL1_1 and the second electrode REL2 in the emission area EMA of each sub-pixel, and the second light emitting element LD2 may be aligned between the second electrode REL2 and the 1-2 electrode REL1_2 in the emission area EMA of each sub-pixel.

[0305] like Figure 9a and Figure 9b As shown in , each light emitting element LD may include an emission stack pattern 10 formed by sequentially stacking a first conductive semiconductor layer 11, an active layer 12, a second conductive semiconductor layer 13, and an electrode layer 15 in a longitudinal direction of each light emitting element LD, and an insulating film 14 surrounding the periphery (or surface) of the emission stack pattern 10. In this case, the first conductive semiconductor layer 11, the active layer 12, the second conductive semiconductor layer 13, and the electrode layer 15 stacked continuously in the longitudinal direction of each light emitting element LD may have different thicknesses. In an embodiment of the present disclosure, the thickness d1 of the first conductive semiconductor layer 11 may be substantially equal to or similar to the sum of the thickness d2 of the active layer 12, the thickness d3 of the second conductive semiconductor layer 13, and the thickness d4 of the electrode layer 15. The longitudinal direction of each light emitting element LD may be a first direction DR1 in a plan view, and may be a horizontal direction in a cross-sectional view.

[0306] In an embodiment, Fig.10 As shown in , each light emitting element LD may include an emission stack pattern 10 formed by sequentially stacking a first conductive semiconductor layer 11, an active layer 12, and a second conductive semiconductor layer 13 in a longitudinal direction of each light emitting element LD, and an insulating film 14 surrounding the periphery (or surface) of the emission stack pattern 10. In this case, the first conductive semiconductor layer 11, the active layer 12, and the second conductive semiconductor layer 13 stacked continuously in the longitudinal direction L of each light emitting element LD may have different thicknesses. In an embodiment of the present disclosure, the thickness d1 of the first conductive semiconductor layer 11 may be substantially equal to or similar to the sum of the thickness d2 of the active layer 12 and the thickness d3 of the second conductive semiconductor layer 13. The longitudinal direction of each light emitting element LD may be a first direction DR1 in a plan view, and may be a horizontal direction in a cross-sectional view.

[0307] Each of the light emitting elements LD may have a first end EP1 and a second end EP2 in a longitudinal direction.

[0308] like Figure 9a and Figure 9bAs shown in , the first conductive semiconductor layer 11 may be disposed in the first end EP1 of each light emitting element LD, and the electrode layer 15 may be disposed in the second end EP2 thereof. Fig.10 As shown in , the first conductive semiconductor layer 11 may be disposed in the first end EP1 of each light emitting element LD, and the second conductive semiconductor layer 13 may be disposed in the second end EP2 thereof.

[0309] Each light emitting element LD may include a first region I and a second region II. The first region I and the second region II of each light emitting element LD may be divided based on a lower surface 12a of the active layer 12 contacting an upper surface 11b of the first conductive semiconductor layer 11 in a longitudinal direction of the light emitting element LD.

[0310] The first region I of each light emitting element LD may refer to a region extending from the lower surface 11a of the first conductive semiconductor layer 11 to the lower surface 12a of the active layer 12 in the longitudinal direction of each light emitting element LD. The first conductive semiconductor layer 11 may be positioned in the first region I. As described above, since the first conductive semiconductor layer 11 is positioned in the first region I, the width of the first region I in the longitudinal direction of each light emitting element LD may be substantially equal to the thickness d1 of the first conductive semiconductor layer 11.

[0311] like Figure 9a and Figure 9b As shown in , the second region II of each light emitting element LD may refer to a region extending from the lower surface 12a of the active layer 12 to the upper surface 15b of the electrode layer 15 in the longitudinal direction of each light emitting element LD. The active layer 12, the second conductive semiconductor layer 13, and the electrode layer 15 may be located in the second region II. Since the active layer 12, the second conductive semiconductor layer 13, and the electrode layer 15 are located in the second region II, the width of the second region II in the longitudinal direction of each light emitting element LD may be substantially the same as the sum of the thickness d2 of the active layer 12, the thickness d3 of the second conductive semiconductor layer 13, and the thickness d4 of the electrode layer 15.

[0312] In an embodiment, Fig.10 As shown in , the second region II of each light emitting element LD may refer to a region extending from the lower surface 12a of the active layer 12 to the upper surface 13b of the second conductive semiconductor layer 13 in the longitudinal direction of each light emitting element LD. In this case, the active layer 12 and the second conductive semiconductor layer 13 may be located in the second region II. Since the active layer 12 and the second conductive semiconductor layer 13 are located in the second region II, the width of the second region II in the longitudinal direction of each light emitting element LD may be substantially the same as the sum of the thickness d2 of the active layer 12 and the thickness d3 of the second conductive semiconductor layer 13.

[0313] In the embodiment of the present disclosure, when viewed in a cross-sectional view, the upper surface 12b of the active layer 12 may not be located at a point corresponding to half the length L of each light emitting element LD. Similarly, when viewed in a cross-sectional view, the upper surface 12b of the active layer 12 may not be located at a point corresponding to half the length L of the emission stack pattern 10 of each light emitting element LD. Figure 9a and Figure 9b As shown in , the ratio of the distance from the upper surface 12b of the active layer 12 to the upper surface 15b of the electrode layer 15 to the length L of each light emitting element LD may be 0.5 or less. In other words, when viewed in a cross-sectional view, the sum of the thickness d3 of the second conductive semiconductor layer 13 and the thickness d4 of the electrode layer 15 in the longitudinal direction of each light emitting element LD may be equal to or less than half of the length L of each light emitting element LD. In an embodiment, as Fig.10 As shown in , when viewed in a cross-sectional view, the ratio of the distance from the upper surface 12b of the active layer 12 to the upper surface 13b of the second conductive semiconductor layer 13 to the length L of each light emitting element LD may be 0.5 or less. In other words, when viewed in a cross-sectional view, the thickness d3 of the second conductive semiconductor layer 13 in the longitudinal direction of each light emitting element LD may be equal to or less than half of the length L of each light emitting element LD.

[0314] In the embodiment of the present disclosure, a point corresponding to half the length L of each light emitting element LD may be located between the lower surface 12 a of the active layer 12 and the upper surface 12 b of the active layer 12 , but the present disclosure is not limited thereto.

[0315] In the cross-sectional view, Figure 9a and Figure 9b As shown in , the sum of the thickness d3 of the second conductive semiconductor layer 13 and the thickness d4 of the electrode layer 15 is equal to or less than half of the length L of each light emitting element LD, or as Fig.10 As shown in , when the thickness d3 of the second conductive semiconductor layer 13 is equal to or less than half of the length L of each light emitting element LD, the active layer 12 in the longitudinal direction of each light emitting element LD can be located in the middle (or center) of each light emitting element LD, or positioned adjacent to the middle (or center) of each light emitting element LD. In this case, the light emitted from the active layer 12 of each light emitting element LD can travel uniformly (or evenly) to the two ends EP1 and EP2 of each light emitting element LD without being biased in one direction. Therefore, the intensity of the light emitted from the two ends EP1 and EP2 of each light emitting element LD becomes uniform, so that the luminous efficiency of each light emitting element LD can be enhanced.

[0316] A predetermined voltage may be applied to both ends EP1 and EP2 of each light emitting element LD through the first electrode REL1 and the second electrode REL2. Therefore, when electron-hole pairs are combined in the active layer 12 of each light emitting element LD, each light emitting element LD may emit light. Here, the active layer 12 may emit light having a wavelength range of 400 nm to 900 nm.

[0317] The first insulating layer INS1 may be disposed between each light emitting element LD and the passivation layer PSV.

[0318] The first insulating layer INS1 may be formed between the first electrode REL1 and the second electrode REL2 in the emission area EMA of each sub-pixel and / or disposed under each light emitting element LD. In the emission area EMA of each sub-pixel, the first insulating layer INS1 may fill the space between each light emitting element LD and the passivation layer PSV to stably support the light emitting element LD, and may prevent the light emitting element LD from being removed from the passivation layer PSV.

[0319] In addition, in the emission area EMA of each sub-pixel, the first insulating layer INS1 may expose the area of ​​the first electrode REL1 and cover the area except the area, thereby protecting the other areas of the first electrode REL1. In addition, the first insulating layer INS1 may expose the area of ​​the second electrode REL2 and cover the area except the area, thereby protecting the other areas of the second electrode REL2. Here, when the display element layer DPL of each sub-pixel includes the first contact electrode CNE1 and the second contact electrode CNE2, the area of ​​the first electrode REL1 may refer to the area thereof that is in electrical contact and / or physical contact with the first contact electrode CNE1, and the area of ​​the second electrode REL2 may refer to the area thereof that is in electrical contact and / or physical contact with the second contact electrode CNE2.

[0320] In addition, a first insulating layer INS1 may be formed in the peripheral area PPA of each subpixel and / or disposed on each of the first and second connection lines CNL1 and CNL2 to cover and protect the first and second connection lines CNL1 and CNL2.

[0321] The first insulating layer INS1 may include an inorganic insulating layer made of an inorganic material or an organic insulating layer made of an organic material. In an embodiment of the present disclosure, the first insulating layer INS1 may be formed of an inorganic insulating layer suitable for protecting the light emitting element LD from the pixel circuit layer PCL, but the present disclosure is not limited thereto. In an embodiment, the first insulating layer INS1 may be formed of an organic insulating layer suitable for flattening the support surface of the light emitting element LD.

[0322] In the emission area EMA of each sub-pixel, a second insulating layer INS2 may be disposed on each light emitting element LD.

[0323] The second insulating layer INS2 may be disposed on each light emitting element LD to cover a portion of the surface of each light emitting element LD and expose both ends EP1 and EP2 of each light emitting element LD to the outside. Specifically, the second insulating layer INS2 may include an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material, and may be fixed to each light emitting element LD aligned in the emission area EMA of each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. In an embodiment of the present disclosure, the second insulating layer INS2 may include an inorganic insulating layer suitable for protecting the active layer 12 of each light emitting element LD from external oxygen or moisture. However, the present disclosure is not limited thereto. According to the design conditions of the display device to which each light emitting element LD is applied, the second insulating layer INS2 may include an organic insulating layer including an organic material.

[0324] In an embodiment of the present disclosure, after the arrangement of the light emitting element LD has been completed in the emission area EMA of each sub-pixel, a second insulating layer INS2 is formed on each light emitting element LD so that the light emitting element LD can be prevented from being removed from the arrangement position. At the same time, when there is a space between the first insulating layer INS1 and the light emitting element LD before the second insulating layer INS2 is formed, the space can be filled with the second insulating layer INS2 in the process of forming the second insulating layer INS2. Therefore, the light emitting element LD can be reliably supported.

[0325] Meanwhile, when forming the second insulating layer INS2, as shown in FIG. Figure 9b As shown in FIG. 1 , a portion of the insulating film 14 of each light emitting element LD is separated so that a portion of the periphery (or surface) of the emission stack pattern 10 can be exposed to the outside. When the active layer 12 of the emission stack pattern 10 is exposed to the outside so that the active layer 12 contacts with an external conductive material (e.g., the first contact electrode CNE1 and / or the second contact electrode CNE2), each light emitting element LD is not driven normally.

[0326] In an embodiment of the present disclosure, a second insulating layer INS2 may be formed on each light emitting element LD to prevent the active layer 12 of each light emitting element LD from contacting an external conductive material. The second insulating layer INS2 may cover only a portion of the surface of each light emitting element LD and may expose both ends EP1 and EP2 of each light emitting element LD to the outside.

[0327] If the first conductive semiconductor layer 11 in each light emitting element LD occupies 2 / 3 or more of the length L of each light emitting element LD, the second insulating layer INS2 may expose a portion of the first conductive semiconductor layer 11 and a portion of the second conductive semiconductor layer 13 to the outside without covering a portion of the first conductive semiconductor layer 11 located in the first end EP1 of each light emitting element LD and a portion of the second conductive semiconductor layer 13 located in the second end EP2 of each light emitting element LD. When the first conductive semiconductor layer 11 in each light emitting element LD occupies 2 / 3 or more of the length L of each light emitting element LD, the first conductive semiconductor layer 11 may also be located in the second end EP2 of each light emitting element LD.

[0328] In this case, when the insulating film 14 is separated in the second end EP2 of each light emitting element LD in the process of forming the second insulating layer INS2, the second conductive semiconductor layer 13, the active layer 12, and the first conductive semiconductor layer 11 located in the second end EP2 of each light emitting element LD may be exposed to the outside. If the insulating film 14 is separated from the second end EP2 of each light emitting element LD when the electrode layer 15 is located in the second end EP2 of each light emitting element LD, the electrode layer 15, the second conductive semiconductor layer 13, the active layer 12, and the first conductive semiconductor layer 11 located in the second end EP2 of each light emitting element LD may be exposed to the outside. When the second contact electrode CNE2 is formed on the second conductive semiconductor layer 13 by a subsequent process, the second contact electrode CNE2 may be electrically connected to the second conductive semiconductor layer 13 and the active layer 12 and the first conductive semiconductor layer 11 exposed to the outside. Therefore, the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13 of each light emitting element LD are electrically connected to each other, so that a short circuit failure occurs, and each light emitting element LD is not driven normally.

[0329] Therefore, in the embodiment of the present disclosure, the active layer 12 of each light-emitting element LD can be located in the middle (or center) of each light-emitting element LD, or positioned adjacent to the middle (or center) of each light-emitting element LD, so that each of the two ends EP1 and EP2 of each light-emitting element LD corresponds to only one conductive semiconductor layer, thereby preventing a short-circuit failure caused by the separation of the insulating film 14.

[0330] Fig.12 Shows Figure 7 , and is a schematic plan view of the first sub-pixel including only some components of the display element layer, Fig.13 It is along Fig.12 A cross-sectional view taken along line II-II', Fig.14 yes Fig.13 is an enlarged cross-sectional view of portion EA2, and Fig.15 Shown include Figure 3aThe light emitting element shown in the figure is a part of the display element layer and is Fig.13 The enlarged cross-sectional view corresponding to portion EA2.

[0331] For convenience, Fig.12 Only the driving voltage line, the first and second electrodes, the first and second connecting lines, and the second insulating layer are shown.

[0332] In addition, although Figures 12 to 15 The structure of the first sub-pixel is more simply illustrated, for example, it is illustrated that each electrode is formed of a single electrode layer and each insulating layer is formed of a single insulating layer, but the present disclosure is not limited thereto.

[0333] To avoid redundant description, Figures 12 to 15 The description of the first sub-pixel of the embodiment will focus on the differences from the first sub-pixel of the previous embodiment. Components not separately described in the following description of this embodiment conform to the components of the previous embodiment. The same reference numerals will be used to represent the same components, and similar reference numerals will be used to represent similar components.

[0334] Reference Figure 5 , Figure 7 , Figure 8 and Figures 12 to 15 According to an embodiment of the present disclosure, the first subpixel SP1 may include a substrate SUB having an emission area EMA and a peripheral area PPA. In addition, the first subpixel SP1 may include a pixel circuit layer PCL disposed on the substrate SUB and a display element layer DPL disposed on the pixel circuit layer PCL.

[0335] like Fig.14 As shown in , each light emitting element LD may include an emission stack pattern 10 formed by sequentially stacking a first conductive semiconductor layer 11, an active layer 12, a second conductive semiconductor layer 13, and an electrode layer 15 in a longitudinal direction of each light emitting element LD, and an insulating film 14 surrounding the periphery (or surface) of the emission stack pattern 10. In an embodiment, as Fig.15 As shown in the figure, each light emitting element LD may include an emission stack pattern 10 formed by sequentially stacking a first conductive semiconductor layer 11, an active layer 12 and a second conductive semiconductor layer 13 in a longitudinal direction of each light emitting element LD, and an insulating film 14 surrounding the periphery (or surface) of the emission stack pattern 10.

[0336] The display element layer DPL may include a partition wall PW, first and second electrodes REL1 and REL2 , a cap layer CPL, a light emitting element LD, and at least one insulating layer.

[0337] In an embodiment of the present disclosure, the at least one insulating layer may include a first insulating layer INS1 and a second insulating layer INS2. However, the present disclosure is not limited thereto. The at least one insulating layer may further include a third insulating layer INS3 and a fourth insulating layer INS4 sequentially stacked on the second insulating layer INS2.

[0338] The first insulating layer INS1 may fill a space between each light emitting element LD in the emission area EMA of the first sub-pixel SP1 and the pixel circuit layer PCL, thereby reliably supporting the light emitting element LD.

[0339] The second insulating layer INS2 may overlap the light emitting element LD in the emission area EMA, and may expose both ends EP1 and EP2 of each light emitting element LD. In a plan view, the width W of the second insulating layer INS2 in a horizontal direction (e.g., a first direction DR1) may be smaller than the length L of each light emitting element LD. The width W of the second insulating layer INS2 in the horizontal direction may be the same as the thickness d1 of the first conductive semiconductor layer 11 of each light emitting element LD. In an embodiment, the width W of the second insulating layer INS2 in the horizontal direction may be smaller than the thickness d1 of the first conductive semiconductor layer 11 of each light emitting element LD.

[0340] In the embodiment of the present disclosure, the width W of the second insulating layer INS2 in the horizontal direction may be changed in any manner within the range that only one conductive semiconductor layer corresponding to each of the two ends EP1 and EP2 of each light emitting element LD may be exposed to the outside and the second insulating layer INS2 may fully cover the active layer 12 of each light emitting element LD. Fig.14 As shown in , the second insulating layer INS2 may have a horizontal width W of, for example, 3.5 μm or less to cover the active layer 12 located in the middle (or center) in the longitudinal direction of each light emitting element LD, while exposing a portion of the first conductive semiconductor layer 11 located in the first end EP1 of each light emitting element LD and a portion of the electrode layer 15 located in the second end EP2 of each light emitting element LD to the outside. In an embodiment, as Fig.15 As shown in the figure, the second insulating layer INS2 can have a horizontal width W of, for example, 3.5 μm or less, so as to cover the active layer 12 located in the middle (or center) of each light emitting element LD in the longitudinal direction, while exposing a portion of the first conductive semiconductor layer 11 located at the first end EP1 of each light emitting element LD and a portion of the second conductive semiconductor layer 13 in the second end EP2 of each light emitting element LD to the outside.

[0341] Fig.16 According to another embodiment Figure 8 The first contact electrode and the second contact electrode are shown in FIG. Figure 7A cross-sectional view taken along line II' of Fig.17 yes Fig.16 is an enlarged cross-sectional view of portion EA3, and Fig.18 Shown include Figure 3a The light emitting element shown in the figure is a part of the display element layer and is Fig.16 The enlarged cross-sectional view corresponding to portion EA3.

[0342] In addition to the first contact electrode and the second contact electrode being provided at the same layer, Fig.16 The display device shown in FIG. 1 may have Figure 8 The configuration of the display device shown in is basically the same or similar to that of the display device shown in FIG.

[0343] Therefore, to avoid redundant explanations, Figures 16 to 18 The description of the display device of the embodiment will focus on the differences from the display device of the previous embodiment. Components that are not explained separately in the following description of the embodiment of the present disclosure are consistent with the components of the previous embodiment. The same reference numerals will be used to represent the same components, and similar reference numerals will be used to represent similar components.

[0344] although Figures 16 to 18 Only one first light emitting element aligned between the 1-1 electrode and the second electrode among the light emitting elements is shown, but for convenience, one first light emitting element will be described to represent a plurality of light emitting elements.

[0345] In addition, although Figures 16 to 18 The structure of the display device is simply illustrated, for example, it is illustrated that each electrode is formed of a single electrode layer and each insulating layer is formed of a single insulating layer, but the present disclosure is not limited thereto.

[0346] Reference Figure 5 , Figure 7 and Figures 16 to 18 , a display device according to another embodiment of the present disclosure may include a substrate SUB on which a plurality of pixels PXL are disposed. Each pixel PXL may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3.

[0347] Each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may include an emission area EMA that emits light and a peripheral area PPA located around the emission area EMA. In addition, each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may include a pixel circuit layer PCL disposed on a substrate SUB and a display element layer DPL disposed on the pixel circuit layer PCL.

[0348] The pixel circuit layer PCL of each of the first, second, and third subpixels SP1, SP2, and SP3 may include a driving transistor T1 and a switching transistor T2 disposed on a substrate SUB, a driving voltage line DVL, and a passivation layer PSV having first and second contact holes CH1 and CH2.

[0349] The display element layer DPL of each of the first, second and third subpixels SP1, SP2 and SP3 may include partition walls PW, first and second connection lines CNL1 and CNL2, first and second electrodes REL1 and REL2, a capping layer CPL, a plurality of light emitting elements LD and first and second contact electrodes CNE1 and CNE2.

[0350] like Fig.17 As shown in , each light emitting element LD may include an emission stack pattern 10 formed by sequentially stacking a first conductive semiconductor layer 11, an active layer 12, a second conductive semiconductor layer 13, and an electrode layer 15 in a longitudinal direction of each light emitting element LD, and an insulating film 14 surrounding the periphery (or surface) of the emission stack pattern 10. In an embodiment, as Fig.18 As shown in the figure, each light emitting element LD may include an emission stack pattern 10 formed by sequentially stacking a first conductive semiconductor layer 11, an active layer 12 and a second conductive semiconductor layer 13 in a longitudinal direction of each light emitting element LD, and an insulating film 14 surrounding the periphery (or surface) of the emission stack pattern 10.

[0351] In the embodiment of the present disclosure, the active layer 12 may be located in the middle (or center) of each light emitting element LD in the longitudinal direction of each light emitting element LD, or may be positioned adjacent to the middle (or center) of each light emitting element LD. In this case, the light emitted from the active layer 12 of each light emitting element LD may travel uniformly (or evenly) to both ends EP1 and EP2 of each light emitting element LD without being biased in one direction. Therefore, the intensity of the light emitted from both ends EP1 and EP2 of each light emitting element LD becomes uniform, so that the luminous efficiency of each light emitting element LD can be enhanced.

[0352] In an embodiment of the present disclosure, the first contact electrode CNE1 and the second contact electrode CNE2 may be disposed on the corresponding electrode to be electrically and / or physically connected to the corresponding electrode. For example, the first contact electrode CNE1 may be disposed on the first electrode REL1 to be electrically and / or physically connected to the first electrode REL1. The second contact electrode CNE2 may be disposed on the second electrode REL2 to be electrically and / or physically connected to the second electrode REL2. More specifically, the first contact electrode CNE1 may be directly disposed on the cap layer CPL on the first electrode REL1 to be electrically and / or physically connected to the first electrode REL1 through the cap layer CPL. The second contact electrode CNE2 may be directly disposed on the cap layer CPL on the second electrode REL2 to be electrically and / or physically connected to the second electrode REL2 through the cap layer CPL.

[0353] In an embodiment of the present disclosure, the first contact electrode CNE1 and the second contact electrode CNE2 may be disposed at the same plane and may be spaced apart from each other on the second insulating layer INS2 to be electrically and / or physically separated from each other. In other words, the first contact electrode CNE1 and the second contact electrode CNE2 may be disposed at the same layer and may be formed by the same manufacturing process.

[0354] The third insulating layer INS3 may be disposed on the first contact electrode CNE1 and the second contact electrode CNE2 to cover the first contact electrode CNE1 and the second contact electrode CNE2. Figure 8 The third insulating layer INS3 may prevent the first contact electrode CNE1 and the second contact electrode CNE2 from being exposed to the outside, thereby preventing the first contact electrode CNE1 and the second contact electrode CNE2 from being corroded.

[0355] Although various embodiments have been described above, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the present disclosure.

[0356] Therefore, the embodiments disclosed in this specification are for illustrative purposes only and do not limit the technical scope of the present disclosure. The scope of the present disclosure can be defined by the appended claims.

Claims

1. A light-emitting element, comprising: an emission stack pattern, comprising a first semiconductor layer, an active layer, a second semiconductor layer and an electrode layer sequentially stacked in one direction, The active layer includes a first surface in contact with the first semiconductor layer in a longitudinal direction of the emission stack pattern and a second surface opposite to the first surface and in contact with the second semiconductor layer. wherein the first semiconductor layer includes at least one n-type semiconductor layer, and the second semiconductor layer includes at least one p-type semiconductor layer, wherein the first surface of the active layer is located within the emission stack pattern at a point corresponding to a range of -20% to +20% from half of the total length of the emission stack pattern in the longitudinal direction of the emission stack pattern, and wherein the electrode layer is thicker than the second semiconductor layer in the longitudinal direction of the emission stack pattern, and wherein the electrode layer is thinner than the first semiconductor layer in the longitudinal direction of the emission stack pattern.

2. The light-emitting element according to claim 1, wherein A point corresponding to a half of the total length of the emission stack pattern is located between the first surface and the second surface of the active layer.

3. The light-emitting element according to claim 2, wherein In a cross-sectional view, a distance from the first surface of the active layer to an upper surface of the second semiconductor layer is different from a distance from a lower surface of the first semiconductor layer to an upper surface of the first semiconductor layer in contact with the first surface of the active layer.

4. The light-emitting element according to claim 2, wherein In a cross-sectional view, a distance from the first surface of the active layer to an upper surface of the electrode layer is the same as a distance from a lower surface of the first semiconductor layer to an upper surface of the first semiconductor layer in contact with the first surface of the active layer.

5. The light emitting element according to claim 1, wherein The emission stack pattern has a cylindrical shape, wherein the first semiconductor layer, the active layer, and the second semiconductor layer are sequentially stacked in the longitudinal direction of the emission stack pattern.

6. The light-emitting element according to claim 5, wherein In a cross-sectional view, a ratio of a distance from the second surface of the active layer to an upper surface of the second semiconductor layer to the total length of the emission stack pattern is 0.5 or less.

7. The light-emitting element according to claim 5, in, In a cross-sectional view, a ratio of a distance from the second surface of the active layer to an upper surface of the electrode layer to the total length of the emission stack pattern is 0.5 or less.

8. The light-emitting element according to claim 7, wherein In a cross-sectional view, a distance from the first surface of the active layer to the upper surface of the electrode layer is different from a distance from a lower surface of the first semiconductor layer to an upper surface of the first semiconductor layer in contact with the first surface of the active layer.

9. The light-emitting element according to claim 6, wherein The electrode layer includes a transparent metal oxide and has a thickness of 0.5 μm to 1 μm in the longitudinal direction of the emission stack pattern. 10 . The light emitting element according to claim 1 , further comprising an insulating film surrounding a periphery of the emission stack pattern.

11. A display device, comprising: A substrate, including a display area and a non-display area; as well as A plurality of pixels are arranged in the display area of ​​the substrate and each includes a plurality of sub-pixels, Each of the plurality of sub-pixels comprises: a pixel circuit layer, comprising at least one transistor; and a display element layer, comprising at least one light-emitting element that emits light. wherein the display element layer includes a first electrode and a second electrode spaced apart from each other, and the light emitting element has a first end and a second end in a longitudinal direction and is connected to each of the first electrode and the second electrode, and The light emitting element comprises: an emission stacking pattern, comprising a first semiconductor layer, an active layer, a second semiconductor layer and an electrode layer sequentially stacked in the longitudinal direction, and the emission stacking pattern is located on the pixel circuit layer; and an insulating film, which is configured to surround the periphery of the emission stacking pattern, The active layer includes a first surface in contact with the first semiconductor layer in the longitudinal direction and a second surface opposite to the first surface and in contact with the second semiconductor layer. wherein the first semiconductor layer includes at least one n-type semiconductor layer, and the second semiconductor layer includes at least one p-type semiconductor layer, wherein the first surface of the active layer is located at a point in the longitudinal direction within the emission stack pattern corresponding to a range of -20% to +20% from half of the total length of the emission stack pattern, and wherein the electrode layer is thicker than the second semiconductor layer in the longitudinal direction of the emission stack pattern, and wherein the electrode layer is thinner than the first semiconductor layer in the longitudinal direction of the emission stack pattern.

12. The display device according to claim 11, wherein: In a cross-sectional view, a distance from the first surface of the active layer to an upper surface of the second semiconductor layer is different from a distance from a lower surface of the first semiconductor layer to an upper surface of the first semiconductor layer in contact with the first surface of the active layer.

13. The display device according to claim 11, wherein: In a cross-sectional view, a ratio of a distance from the second surface of the active layer to an upper surface of the second semiconductor layer to the total length of the emission stack pattern is 0.5 or less.

14. The display device according to claim 13, wherein: The electrode layer includes a transparent metal oxide and has a thickness of 0.5 μm to 1 μm in the longitudinal direction of the emission stack pattern.

15. The display device according to claim 13, wherein: In a cross-sectional view, a ratio of a distance from the second surface of the active layer to an upper surface of the electrode layer to the total length of the emission stack pattern is 0.5 or less.

16. The display device according to claim 13, wherein: In a cross-sectional view, a distance from the first surface of the active layer to an upper surface of the electrode layer is different from a distance from a lower surface of the first semiconductor layer to an upper surface of the first semiconductor layer in contact with the first surface of the active layer.

17. The display device according to claim 11, in, The display element layer further includes an insulating layer disposed on the light emitting element to expose the first end and the second end of the light emitting element, and The insulating layer has a width in the longitudinal direction of the light emitting element that is equal to or smaller than a distance from a lower surface of the first semiconductor layer to an upper surface of the first semiconductor layer.

18. The display device according to claim 17, wherein: The display element layer further comprises: a first contact electrode electrically connecting one of the first end and the second end of the light emitting element to the first electrode; and a second contact electrode electrically connecting the other one of the first end and the second end of the light emitting element to the second electrode, and Wherein, the first contact electrode and the second contact electrode are arranged on the insulating layer.

Images