Encoding special values in anchored data elements

Abstract

An apparatus comprising processing circuitry to perform data processing; and an instruction decoder to control the processing circuitry to perform an anchored data processing operation to generate an anchored data element. The anchored data element has an encoding comprising type information indicating whether the anchored data element represents a portion of a bit of a two's complement number that corresponds to a given range of significant values that can be represented using the anchored data element; or represents a special value other than the portion of the bit of the two's complement number.

Description

TECHNICAL FIELD

[0001] The present technology relates to the field of data processing. BACKGROUND

[0002] Floating point (FP) representation is commonly used in data processing systems. A floating point number comprises a significand and an exponent indicating the effective value of the bits of the significand. This allows a limited number of bits to be used to represent a large range of numerical values. However, a problem with floating point arithmetic is that the calculations are generally non-associative, which is the fact that causes the sum problem. In particular, programmers need to worry about getting different results even when adding a small number of values.

[0003] In an attempt to solve the associativity problem, a new data type has been proposed, which is known as a high precision anchored (HPA) number. A high precision anchored (HPA) number can comprise a pair (i, a) of a long two’s complement integer i (e.g. 200 bits) and a small anchor integer a representing the weights of the bits of i, typically by specifying the effective value of the least bit of i. A floating point value can be converted into HPA form and then addition can be performed in an associative manner. SUMMARY

[0004] At least some examples provide an apparatus comprising: processing circuitry to perform data processing; and instruction decoder to control the processing circuitry to perform an anchored data processing operation to generate an anchored data element; wherein: the anchored data element has an encoding comprising type information indicating that the anchored data element represents a portion of bits of a two’s complement number, the portion of bits corresponding to a given range of effective values that can be represented using the anchored data element; or represents a special value other than the portion of bits of a two’s complement number.

[0005] At least some examples provide a computer program for controlling a host data processing apparatus to provide an instruction execution environment for executing instructions; the computer program comprising: instruction decoding program logic to decode program instructions of object code to control the host data processing apparatus to perform data processing; the instruction decoding program logic comprising anchored data processing program logic to control the host data processing apparatus to perform an anchored data processing operation to generate an anchored data element, wherein: the anchored data element has an encoding comprising type information indicating that the anchored data element: represents a portion of bits of a two’s complement number, the portion of bits corresponding to a given range of effective values that can be represented using the anchored data element; or represents a special value other than the portion of bits of a two’s complement number.

[0006] The computer program can be stored on a storage medium. The storage medium can be a non-transitory storage medium.

[0007] At least some examples provide a data processing method comprising: decoding one or more instructions; and in response to the decoded instructions, controlling processing circuitry to perform an anchored data processing operation to generate an anchored data element, wherein: the anchored data element has an encoding comprising type information indicating that the anchored data element: is a part of a bit representing a two's complement number, the part of the bit corresponding to a given range of significant values that can be represented using the anchored data element; or is a special value other than the part of the bit representing the two's complement number.

[0008] Further aspects, features, and advantages of the technology will be apparent from the following description of examples, which is read in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 A data processing apparatus is schematically illustrated;

[0010] Figure 2 Different representations of numerical values are schematically illustrated;

[0011] Figure 3 An example of a relationship between a double-precision floating-point value and a high-precision anchored (HPA) value is schematically illustrated;

[0012] Figure 4 An example of a redundant HPA value is shown, the redundant HPA value representing a numerical value using a redundant representation comprising a plurality of N-bit portions having overlapping significant values;

[0013] Figure 5 How an HPA integer can be stored within a selected lane across multiple vector registers is schematically illustrated in one example;

[0014] Figure 6 A block diagram schematically illustrating how floating-point numbers can be converted into HPA form and processed according to one example arrangement;

[0015] Figure 7 A form of metadata that can be used in one example is schematically illustrated;

[0016] Figure 8 A schematic diagram showing in more detail conversion and processing circuitry that can be arranged in association with each lane in one example;

[0017] Figure 9 Encoding of an anchored data element is shown, the anchored data element comprising type information indicating whether the anchored data element is a part of a bit representing a two's complement number or a special value;

[0018] Figure 10Encoding of type information is shown;

[0019] Figure 11 Different results are shown for setting the type information of a result anchor data element based on the type information of the first and second operands;

[0020] Figure 12 An example of circuit logic for implementing the addition of two anchor data elements including type information is shown;

[0021] Figure 13 An example of an overlap propagation indication is shown;

[0022] Figure 14 An example of an overlap clear indication is shown; and

[0023] Figure 15 An example of a simulator that can be used is shown. DETAILED DESCRIPTION

[0024] As previously mentioned, the problem with floating point arithmetic is that the calculations are generally non-associative, which is the fact that causes the sum problem. For example, when adding several floating point values together, each time another value is added to the result of the previous addition, the result is rounded and normalized, which means that the overall result differs depending on the order in which the values are added. This makes it difficult to process floating point arithmetic in parallel, because unless done in exactly the same order, the sum is not reproducible. In order to generate a reproducible result, a series of additions or subtractions must generally be performed sequentially, which can make floating point arithmetic relatively slow.

[0025] Accordingly, programmers use a higher degree of accuracy than they need in the hope of avoiding such different results. As a result, programmers cannot easily process code in parallel, because unless computed in exactly the same order, the sum is not reproducible.

[0026] The problem is particularly acute for high performance computing (HPC) where a program can need to add millions of values. Programmers want to process these problems in parallel, but the lack of reproducibility makes it difficult to debug. Even if the reprogramming of those machines is done perfectly, each different machine configuration will produce a different answer.

[0027] As noted above, in an attempt to address the associativity problem, a new data type has been proposed, known as a high-precision anchored (HPA) number. An HPA number can comprise a pair (i, a) consisting of a long two's complement integer i (e.g., 200 bits) and a small anchor integer a representing the weight of a bit of i, typically by specifying the effective value of the least bit of i. The pair is somewhat analogous to the significand and exponent of an FP number, but differs in that the long integer i is not normalized and is typically much larger than an FP significand, and the anchor value a is fixed for all operands in HPA operations. Adding FP numbers can result in a change of exponent, but adding HPA numbers does not change the anchor.

[0028] As a trivial example, consider an HPA representation consisting of a 10-bit i and an anchor value a = -4. Some values of this format are given in Table 1.

[0029] i (binary) value (decimal) 00000_00001 0.0625 00000_01000 0.5 00000_11000 1.5 00001_00000 2.0 00100_11000 9.5 11111_01000 -1.5

[0030] Table 1 - Exemplary HPA numbers (i, -4)

[0031] When adding two of these numbers, such as 0.5 and 1.5, the anchor (-4) does not change, and the sum is conveniently given by simply adding the i values. Since HPA sums are merely two's complement additions, HPA sums are associative, exact, and repeatable when the range is sufficient.

[0032] FP numbers have a large range. A double-precision number (FP64) can be as small as 2 -1000 and as large as 2 1000 but most accumulations do not span this entire range. In fact, it is difficult to imagine a problem of the sort that would meaningfully accumulate values over all of this range, and even for HPC, most accumulations occur within a limited range. For all applications that require wider arithmetic than double-precision arithmetic, it is expected that 200 bits or so will be more than sufficient. Assume that the programmer determines that all data for a particular sum has a magnitude less than 2 100 and that bits below 2 -50 do not affect the sum in any meaningful way. If the data is added using the HPA format (i, -50) with a 200-bit i, the accumulation is associative, and at least 2 49 of the numbers can be added in any order without fear of overflow.

[0033] Most modern architectures have SIMD (Single Instruction Multiple Data) units that can be used to represent long integers. With some extension logic that facilitates carry between 64-bit lanes, a 256-bit SIMD unit can be used to add 256-bit integers. Alternatively, for most additions, the carry between lanes can be avoided by using a redundant representation that is discussed in more detail later. One approach for representing an HPA (anchored data) value (or long integer) in a SIMD register can be to allocate multiple HPA (anchored data) elements of the HPA value to corresponding vector lanes within a single SIMD register. Alternatively, as discussed below, another approach can be that a corresponding anchored data element of an HPA value can be allocated to a corresponding vector lane within multiple different SIMD registers, such that each portion of the overall anchored data value is in a corresponding position of a different vector register, and a single vector register can hold multiple anchored data elements, with each anchored data element forming a portion of a different anchored data value (HPA value).

[0034] In techniques discussed below, an apparatus can have processing circuitry to perform data processing and an instruction decoder to control the processing circuitry to perform anchored data processing operations to generate anchored data elements, with the anchored data elements having an encoding that includes type information. The type information indicates whether the anchored data element represents a portion of bits of a two's complement number (with the portion of bits corresponding to a given range of valid values that can be represented using the anchored data element), or represents a special value other than the portion of bits of the two's complement number within the given range of valid values. Providing an encoding that can represent a special value other than the portion of a two's complement number can be used to enable the anchored data format to represent special values of floating point numbers, such as Not-a-Number (NaN) or infinity. In addition, the special value can be used to represent a case where the given range of valid values assumed for the anchored data element is not suitable to represent a number resulting from a processing operation performed by the processing circuitry.

[0035] An alternative method for handling special values can be to encode at the fact that the anchored data element represents a special value separate from the anchored data element itself, either within a separate register or within a register that defines anchor information or anchor metadata that identifies a given range of valid values that can be represented using the anchored data element or other information about the manner in which the anchored data element is encoded. However, a problem with this approach is that it can require the processing circuitry to update two separate destination registers when performing anchored data processing operations. This can be undesirable for some microarchitecture implementations because it can be necessary to provide the processing circuitry with two separate register write ports. There can be relatively few instructions in an instruction set architecture that require two or more destination registers to be updated, so many microarchitecture implementations can only provide one register write port. Thus, avoiding the need to provide a second register write port to support the encoding of special values can help reduce circuit area and power consumption. Alternatively, even if the apparatus has more than one register write port, the second write port can be used to perform different register writes in response to different instructions when processing anchored data processing operations, rather than for the same instructions as the first register write port. Thus, special values of anchored data values can be represented without the need to use the second register write port, which can save circuit area and / or enable better performance by enabling the available register write port to be used to process additional instructions.

[0036] The processing circuitry can store the type information in the same register as the anchored data element.

[0037] In one example, the anchored data processing operation can comprise a float-to-anchor conversion operation to convert a floating point value to an anchored data element. The encoding of special values can be particularly useful for float-to-anchor conversion operations because this can help accommodate special values of floating point numbers. For example, when the floating point value to be converted represents a special number such as positive infinity or negative infinity or NaN, the processing circuitry can then generate an anchored data element with type information indicating that the anchored data element represents a special value. The type information can distinguish whether the special number represented by the floating point value is positive infinity, negative infinity or NaN. Thus, the type information can have different encodings assigned for each of the cases of positive infinity, negative infinity and NaN.

[0038] In a float-to-anchor conversion operation, the processing circuitry can generate an anchored data element based on anchor metadata indicating a given range of valid values for the anchored data element. For example, the anchored data element can specify a valid value for the least significant bit of that anchored data element (where the valid value indicates a power of two represented by that least significant bit), and can provide a parameter indicating the width (number of bits) of the portion of the two's complement number represented by the anchored data element. The float-to-anchor conversion operation can use this metadata to determine how to set the values of the bits within the anchored data element based on the provided floating-point number. The anchor metadata can also indicate other properties, such as a number of overlapping bits and / or lane information as described below, which indicates the relative position of the anchored data element relative to other elements for an anchored data value composed of one or more anchored data elements, e.g., whether the anchored data element is the most significant element, the least significant element, or an intermediate element representing the anchored data value. This can allow an anchored data value to be represented using multiple vector elements.

[0039] The above examples discuss the generation of a single data element, but it will be appreciated that the operations on anchored data elements can be implemented with vector instructions, where multiple processing lanes can be executed in response to one instruction, each processing lane generating a respective anchored data element based on a corresponding operand provided as input. For a float-to-anchor conversion operation, a respective floating-point value can be provided in each lane, and converted to a respective anchored data element based on a vector of anchor metadata. For addition operations as described below, pairs of independent respective anchored data elements can be added in a vector operation. As described below, it can be useful to have respective anchored data elements for a given anchored data value spread across corresponding data elements at corresponding positions in multiple different vector registers. However, it is also possible to represent respective elements of a single anchored data value in respective vector lanes of a single vector register.

[0040] In some examples, the type information can specify whether the anchor data element is a saturated type anchor data element. A saturated type anchor data element can be an anchor data element that depends on a previous anchor data processing operation that caused an overflow on the corresponding anchor data element, or a previous floating-to-anchor conversion operation for which the converted floating point value falls outside the allowed numerical range of the anchor data value comprising one or more anchor data elements. The saturated type can be supported in addition to the special values representing positive infinity, negative infinity, or NaN as described above, but unlike these special values, the saturated type does not have a similar special value in floating point representation. The saturated type can be used to indicate a case where the valid value range defined for the anchor data value does not apply to accommodate a required input of an anchor data processing operation. For example, if the metadata associated with the anchor data value defines a particular numerical range, but a floating point value is subsequently provided as input (outside of that range), the valid value range defined by the anchor metadata cannot be used to adequately represent the correct numerical result of processing that floating point value, and a saturated type anchor data element can be used to indicate this.

[0041] Thus, in one example, if a floating-to-anchor conversion operation is performed to convert a floating point value to an anchor data element, the processing circuitry can set the information type of the anchor data element to indicate the saturated type in one of the following cases: the anchor data element is to represent the most significant element of the anchor data value comprising one or more anchor data values, and representing the floating point value as a two's complement number would require at least one bit of greater significance than the given valid value range that can be represented using the anchor data element; or the anchor data element is to represent the least significant element of the anchor data value comprising one or more anchor data values, and representing the floating point value as a two's complement number would require at least one bit of lower significance than the given valid value range that can be represented using the anchor data element.

[0042] Thus, however, if the converted floating point value represents a special number, the anchor data value can be encoded as a special value representing one of positive infinity, negative infinity, or NaN as described above, and the saturated type can be used instead if the fact that the floating point value does not map to a two's complement number within the range that can be represented using the anchor data element is due to the range defining information about that anchor data element being set inappropriately. Distinguishing the saturated type from the other types of special values can be used to enable software code to identify the cause of a failure of a sequence of operations comprising processing of the anchor data value.

[0043] For anchored data elements designated as a saturated type, the encoding of the type information can not be able to distinguish whether the anchored data element represents a positive value or a negative value. In contrast, for infinity, different types of encoding can be provided for positive infinity and negative infinity, respectively. This recognizes that when the anchor metadata that limits the allowable range of anchored data values has been set inappropriately such that saturation occurs, it does not matter whether the value is positive or negative because in these cases it is likely that the code will be re-run later using different metadata. By providing an encoding that cannot distinguish between positive and negative values that are labeled as the saturated type, this can save some encoding space (which can enable more efficient encoding of anchored data elements) and allow more number of bits to be reserved for representing the bits of the represented two's complement number.

[0044] The processing circuitry can have addition circuitry to perform addition of two anchored data elements to generate a result anchored data element. As described above, in some cases this can be implemented as a vector operation such that a vector of first anchored data elements can be added to a vector of second anchored data elements, where multiple independent additions of elements at corresponding positions within the respective vectors are performed in response to a vector instruction to generate a result vector comprising a plurality of result anchored data elements. However, scalar addition instructions can also be implemented that perform a single addition of two anchored data elements to generate a result anchored data element.

[0045] When performing such addition of two anchored data elements, sometimes an overflow can occur. For example, in the addition to generate a result anchored data element that is to represent the most significant element of an anchored data value, an overflow can occur if the sum of the two anchored data elements being added would require at least one bit more significant than the most significant bit that can be represented by an anchored data value within the allowed range of significant values that can be limited by the anchor metadata. If an overflow occurs in the addition to generate a result anchored data element that is the most significant element of an anchored data value, the addition circuitry can generate the result anchored data element with type information that specifies that the result anchored data element is of a saturated type.

[0046] The type information of an anchored data element can be encoded in a variety of ways. However, in one example, an anchored data element can have an encoding in which when a predetermined bit of that anchored data element has a first value, the anchored data element represents that portion of the bits of the two's complement number, and when the predetermined bit of that anchored data element has a second value, the anchored data element represents a special value. For example, the predetermined bit can be the most significant bit of the anchored data element. This can be efficiently decoded, as a decoder can check the single bit to identify whether the particular form of special value represented needs to be examined by checking any other bits of the anchored data element, or whether the element simply represents a portion of the two's complement number that is not a part of a special value. For example, in the case that the predetermined bit has the second value, at least one further bit can represent a particular type of the special value represented. On the other hand, in the case that the predetermined bit has the first value, the at least one further bit can be reused to represent a portion of the portion of the two's complement number itself, or to represent at least one overlap bit for accommodating a carry from a portion of the anchored data element that does represent a portion of the two's complement number. This provides a particularly efficient encoding, as in the more common case that the element does not represent a special value, the bits used to encode a particular type of special value can be reused for other purposes.

[0047] In general, in a given anchored data processing operation, when an input anchored data element has a predetermined bit equal to a second value, the processing circuitry can generate a corresponding result anchored data element having a predetermined bit equal to the second value. The predetermined bit can thus be sticky in the sense that once set in a given sequence of processing operations, the corresponding anchored data elements generated in subsequent operations continue to retain the predetermined bit equal to the second value to mark that somewhere in the sequence of operations a floating point value was encountered that was a special number, or that the result of the anchored data processing operation could not be accurately represented within the given range of significant values defined by the anchor metadata for the given anchored data element.

[0048] More generally, in a given anchored data processing operation in which an input anchored data element is indicated by the type information to be a special number, the corresponding result anchored data element can also be indicated with type information that specifies a special value represented by the result anchored data element. Note that the particular form of special value indicated for the result can not always be the same as the form of special value indicated for the input anchored data element. For example, in the addition of two anchored data elements, when the type information of the two anchored data elements indicates that one anchored data element represents positive infinity and the other anchored data element represents negative infinity, the result anchored data element can be generated with type information that specifies that the result represents NaN.

[0049] In some examples, an anchored data element can be represented using a redundant representation, in which multiple overlapping bits can be allocated within the element to accommodate carries resulting from additions performed within the less significant portion of the data element. This can help reduce the likelihood of overflow of an anchored data element resulting from a series of anchored data processing operations. The representation can be redundant in the sense that there can be multiple different bit patterns of an anchored data value formed by multiple anchored data elements that can all represent the same numerical value of a two's complement number using different combinations of overlapping and non-overlapping bits. More information is provided below.

[0050] Thus, in general, an anchored data element can comprise an N-bit value comprising V overlapping bits and W non-overlapping bits. The particular number of overlapping and non-overlapping bits can be fixed or can be variable, for example by specifying information in the aforementioned anchor metadata.

[0051] In a floating-to-anchored conversion operation to convert a floating point value to an anchored data element, when the floating point value represents a number other than a special number and the number is within the allowed range of numbers of the anchored data value of which the anchored data element forms a part, the processing circuitry can set the W non-overlapping bits of the anchored data element to represent a portion of the bits of the two's complement number corresponding to the floating point value. In contrast, the V overlapping bits of the anchored data element can be set to be a sign extension of the W non-overlapping bits. Thus, the initial overlapping bits can be set to be a sign extension, for example all zeros or all ones. However, when the anchored data element generated by the floating-to-anchored conversion operation is subsequently processed in a series of additions, this can result in multiple carries into the overlapping bits. In order to compute the two's complement number represented by the overall anchored data value in a non-redundant representation, an overlap propagation operation can be provided to propagate the carries represented by the overlapping bits of one anchored data element into the non-overlapping bits of the next highest anchored data element of the anchored data value.

[0052] In some examples, N - V - W can be greater than 0. That is, the overlapping bits and the non-overlapping bits together do not occupy all N bits of the anchored data element. This is because at least one other bit can be used to represent type information indicating whether the element represents a special value.

[0053] As noted above, the overlap propagation operation can be performed periodically to propagate carries represented by the overlapping bits into the next highest data element. An overlap propagation instruction can be provided to control the processing circuitry to perform the overlap propagation operation. In response to the overlap propagation instruction, the processing circuitry can align the V overlapping bits of a first anchored data element with the W non-overlapping bits of a second anchored data element, and add the aligned overlapping bits and non-overlapping bits to generate an updated value of the second anchored data element. Again, this can be performed as a vector operation in which multiple lanes of overlap propagation are performed on a respective pair of first and second anchored data elements in response to a single instruction.

[0054] The overlap propagation operation can take into account the type information specified in the first and second anchor data elements to determine how to generate an updated value for the second anchor data element. When one of the first and second anchor data elements has type information specifying that it represents one of the special value types described above, the processing circuitry can preserve the previous value of the second anchor data element. For example, the update to the second anchor data element can be suppressed without adding the aligned overlap bits from the first anchor data element. This ensures that if a special value resulted from a previously executed sequence of anchor data processing operations, the execution of the overlap propagation operation does not overwrite that type information, and in fact, the special value is identified from the final result despite the execution of the overlap propagation operation. This can make it simpler to write or compile code to perform anchor data processing operations because it means that there is no need to frequently check for special values. Alternatively, in the case where the first anchor data element is a special value, the type information of the second anchor data element can be updated to match the type information of the first anchor data element. This propagates that type information to higher elements of the HPA value, which can simplify the checking of type information after a sequence of anchor data processing operations is performed.

[0055] On the other hand, when the addition of the aligned overlap bits and non-overlap bits results in an overflow of the second anchor data element, the processing circuitry can set the type information of the second anchor data element to indicate a saturation type value. Here, an overflow is considered to have occurred if there is already an overflow from the most significant overlap bits, and not considered to have occurred if there is no overflow from the non-overlap bits to the overlap bits. In the case where the addition for the overlap propagation operation results in an overflow from the most significant overlap bits, this means that the correct result can no longer be properly represented in the second anchor data element, so a saturation type can be specified to enable a subsequent instruction to detect what went wrong. For example, this can be a flag that software code should trigger the overlap propagation operation more frequently.

[0056] One use case for the overlap propagation instruction when used within program code can be to specify a pair of adjacent anchor data elements of the same anchor data value as the first and second anchor data elements respectively (where the second anchor data element is the element representing a higher significant portion of the anchor data value than the first anchor data element). Here, the instruction can be used to propagate a carry from the lower element to the next highest element of the same anchor data value.

[0057] However, another use case can be that the first anchored data element comprises the most significant anchored data element of a given anchored data value, and the second anchored data element comprises an "empty" anchored data element that is not part of the same anchored data value as the first anchored data element. This can be used to effectively extend the range of the anchored data value to include additional elements, accommodating a carry-in bit from the top element of the anchored data element of the previous representation, which can be useful in cases where the anchored data value comprising the first anchored data element is subsequently added to another anchored data value that includes bits with greater significant values than the bits of the first anchored data element.

[0058] It will be appreciated that these are just two examples of how the overlap propagation instruction can be used - programmers or compilers can also find other uses.

[0059] The processing circuitry can also clear the overlap bits of the target anchored data element to zero in response to an overlap clear instruction. This instruction can be used once the overlap propagation instruction has added those overlap bits into the non-overlap bits of the next most significant anchored data element. Splitting the overlap propagation and clear operations into two separate instructions can be used to avoid the need for either instruction to update both destination registers, which has the advantage described above. Other alternative architectures can choose to combine these instructions into a single instruction that can clear the overlap bits of the first anchored data element in response to the overlap propagation instruction itself. Such a combined overlap propagation instruction that also clears the overlap bits of the first anchored data element can also be considered an example of an overlap clear instruction.

[0060] In response to the overlap clear instruction, the processing circuitry can preserve the previous value of the target anchored data element when the target anchored data element has type information that specifies that it represents a special value, i.e. without clearing the overlap bits. Again, this enables the type information to be preserved.

[0061] In some examples of the overlap clear instruction, in addition to the target anchored data element (which can be expected to correspond in the program to the least significant element of the pair of first and second elements that the overlap propagation instruction acted on), the overlap clear instruction can also specify a second anchored data element (which is expected to correspond to the higher element of the pair), and the processing circuitry can also preserve the previous value of the target anchored data element if the type information of the second anchored data element indicates that it is a special value. Thus, even though the clearing of the overlap bits itself does not depend on the second anchored data element, taking into account the type information of that second anchored data element can allow the overlap clear instruction to continue in a similar manner to the overlap propagation instruction, such that in the case where either of those elements specifies that the element represents a special value, there is no change to the given pair of lower and higher anchored data elements of the same anchored data value.

[0062] As noted above, when not denoting a special value, a given anchored data element representation denotes a portion of bits corresponding to a given range of valid values that can be represented using the anchored data element representation. Here, the term valid value refers to a particular power of two represented by a given bit position. For example, the bit of a two's complement number representing 2 4 is considered to have a greater valid value than the bit of a two's complement number representing 2 3 . That is, the most significant bit of a two's complement number has the greatest valid value, and the least significant bit has the lowest valid value.

[0063] Particular examples will now be described with reference to the accompanying drawings.

[0064] The high-precision anchor (HPA) format is discussed below. More information regarding the HPA format can be found in U.S. Patent Applications 62 / 074,149, 14 / 582,974, 14 / 582,875, 14 / 582,812, 14 / 582,836, 14 / 582,978, 14 / 606,510, and 14 / 582,968, the contents of which are incorporated by reference herein in their entirety.

[0065] floating point number

[0066] Floating point (FP) is a useful way to take an approximation of a real number using a small number of bits. The IEEE 754-2008 FP standard proposes a number of different formats for FP numbers, some of which are binary64 (also known as double precision or DP), binary32 (also known as single precision or SP), and binary16 (also known as half precision or HP). The numbers 64, 32, and 16 refer to the number of bits required for each format.

[0067] representation

[0068] FP numbers are very similar to the "scientific notation" taught in science classes, where we write -2.0 x 10 6 instead of negative two million. The parts of this number are the sign (negative in this case), the significand (2.0), the base of the exponent (10), and the exponent (6). All of these parts have analogs in FP numbers, but there are differences, the most important of which is that the constituent parts are stored as binary numbers, and the base of the exponent is always 2.

[0069] More precisely, an FP number is composed of a sign bit, a certain number of biased exponent bits, and a certain number of fraction bits. Specifically, the DP, SP, and HP formats are composed of the following bits:

[0070] format sign exponent fraction exponent offset DP[63:0] 63 62:52 (11 bits) 51:0 (52 bits) 1023 SP[31:0] 31 30:23 (8 bits) 22:0 (23 bits) 127 HP[15:0] 15 14:10 (5 bits) 9:0 (10 bits) 15

[0071] Table 2

[0072] The sign of a negative number is 1, and the sign of a positive number is 0. Every number (including zero) has a sign.

[0073] The exponent is biased, meaning that the true exponent is different from the exponent stored in the number. For example, the biased SP exponent is 8 bits long and ranges from 0 to 255. The exponents 0 and 255 are special cases, but all other exponents have a bias of 127, meaning that the true exponent is 127 less than the biased exponent. The smallest biased exponent is 1, which corresponds to a true exponent of -126. The largest biased exponent is 254, which corresponds to a true exponent of 127. The HP and DP exponents are computed in the same way, with the biases shown in the table above.

[0074] The SP exponent 255 (or DP exponent 2047 or HP exponent 31) is reserved for infinity and a special symbol called NaN (not a number). Infinity (which can be positive or negative) has a zero fraction. Any number with exponent 255 and a non-zero fraction is NaN. Infinity provides a saturation value, so this effectively means something like "the calculation came out to a number larger than we can represent in this format". Returning NaN is used for operations that are not mathematically defined on the real numbers, such as dividing by zero or taking the square root of a negative number.

[0075] In any format, the exponent zero is reserved for subnormal numbers and zero. Normal numbers represent values of the form:

[0076] -1 符号 x 1. fraction x 2 e

[0077] where e is the true exponent computed from the biased exponent. The term 1. fraction is called the significand, and the 1 is not stored as part of the FP number, but is inferred from the exponent. All exponents except zero and the maximum exponent indicate a significand of the form 1. fraction. The exponent zero indicates a significand of the form 0. fraction, and for a given format equals 1 - bias of the true exponent. Such numbers are called subnormal (historically these numbers were called denormal, but modern usage prefers the term subnormal).

[0078] A number with both the exponent and the fraction equal to zero is zero.

[0079] The following table has some example numbers in the HP format. The entries are in binary, with the addition of the '_' character to increase readability. Note that the subnormal entry (line 4 in the table, with exponent zero) produces a different significand than the normal entry in the previous line.

[0080] sign 5-bit exponent 10-bit fraction 11-bit significand value (0 01111 00_0000_0000 100_0000_0000 1.0 x 2 0 ]] 1 01110 10_0000_0000 110_0000_0000 -1.1 x 2 -1 ]] 0 00001 10_0000_0000 110_0000_0000 1.1 x 2 -14 ]] 0 00000 10_0000_0000 010_0000_0000 0.1 x 2 -14 ]] 1 11111 00_0000_0000 - infinity 0 11111 00_1111_0011 NaN

[0081] Table 3

[0082] Much of the complexity of FP implementation is due to subnormal numbers, so these are often handled by microcode or software. Some processors handle subnormal numbers in hardware, speeding these operations by a factor of 10 to 100 compared to software or microcode implementation.

[0083] integer, fixed point, floating point

[0084] The FP way of handling signs of numbers is called sign-magnitude, and it is different from the usual way of storing integers in computers (two's complement). In sign-magnitude representation, the positive and negative versions of the same number differ only in the sign bit. A 4-bit sign-magnitude integer, consisting of a sign bit and 3 significant bits, would represent the following:

[0085] +1 = 0001

[0086] -1 = 1001

[0087] In two's complement representation, an (n+1 )-bit binary integer represents the value i - S*2n n where i is an n-bit integer represented by the lower n bits of the (n+1 )-bit value, and S is the bit value (0 or 1 ) of the most significant bit of the (n+1 )-bit value. Thus, unlike for sign-magnitude numbers, where the sign bit modifies the value of all other bits, for two's complement values the most significant bit is negatively weighted, and all other bits are positively weighted. Thus, a 4-bit two's complement integer would represent the following:

[0088] +1 = 0001

[0089] -1 = 1111

[0090] This two's complement format is actually universal for signed integers, because it simplifies computer arithmetic.

[0091] Fixed-point numbers look exactly like integers, but actually represent values with a certain number of fractional bits. Sensor data is often in fixed-point format, and there is a large amount of fixed-point software written before FP was widely adopted. Fixed-point number handling is very tedious, because the programmer must keep track of the "binary point", the separator between the integer and fractional parts of the number, and must constantly shift the number to keep the bits in the right place. FP numbers do not have this difficulty, so it is desirable to be able to convert between fixed-point and FP numbers. Being able to convert also means that we can still use fixed-point software and data, but we are not limited to fixed-point when writing new software.

[0092] rounding FP number

[0093] The IEEE-754 standard requires that most FP operations be computed as if the operation were performed with unbounded range and precision, then rounded to fit an FP number. If the computation exactly matches an FP number, that value is always returned, but often the computation yields a value that lies between two consecutive floating-point numbers. Rounding is the process of choosing which of the two consecutive numbers should be returned.

[0094] There are multiple ways to round, which are referred to as rounding modes; six of the modes are:

[0095]

[0096] Table 4

[0097] This definition does not tell us how to round in any practical way. One common implementation is to do the operation, look at the truncated value (i.e., the value that fits in the FP format) and all the remaining bits, then adjust the truncated value if certain conditions hold. These calculations are all based on:

[0098] L - the least significant bit of the truncated value

[0099] G - the next most significant bit (i.e., the first bit not included in the truncation)

[0100] S - the logical OR of all the remaining bits that are not part of the truncation

[0101] Given these three values and the truncated value, we can always compute the correctly rounded value according to the following table:

[0102] mode change to the rounding value RNE increment if (L & G) | (G & S) RNA increment if G RZ none RP increment if positive and (G | S) RM increment if negative and (G | S) RX set L if G | S

[0103] Table 5

[0104] For example, consider multiplying two 4-bit significand numbers and rounding to a 4-bit significand.

[0105] Sign 1 = 1011 (decimal 11)

[0106] Sign 2 = 0111 (decimal 7)

[0107] The multiplication yields

[0108] Sign 1 x Sign 2 = 1001 101 (decimal 77)

[0109] L G ss

[0110] The least significant bit of the truncated 4-bit result is labeled L, the next bit is labeled G, and S is the logical OR of the remaining bits labeled s (i.e., S = 0 | 1 = 1). To round, we adjust the 4-bit result (1001) according to the rounding mode and calculations in the table above. Thus, for example in RNA rounding, G is set, so we return 1001 + 1 = 1010. Since RX rounding G | S is true, we set L to 1 (it is already 1, so it does not change in this case) and return 1001.

[0111] rounding integer and fixed point numbers

[0112] In the case where we convert FP numbers to integers or fixed points, we also round. The concept is essentially the same as FP rounding. FP numbers that are exactly an integer are always rounded to that integer. All other FP numbers lie between two consecutive integers, and the rounding decides which integer to return. Unfortunately, the rounding logic for integers is somewhat more difficult due to the difference between two's complement and sign magnitude form. Incrementing a sign magnitude number always increases the magnitude, so the number is further from zero. The same thing happens for positive two's complement numbers, but negative two's complement numbers become closer to zero when incremented. This means that the rounding logic must change based on whether the integer is positive or negative. It also means that we must carefully choose the reference value (the value to increment or not). For positive integers, the value is simply the truncated FP significand, so 1.37 will have a reference value of 1, and a result of 1 or 2. For negative integers, we again truncate the significand and take the one's complement of the result (the one's complement is the original number with all bits flipped), -1.37 is truncated to 1, then flipped to give a reference value of -2. Then everything is workable, as we want the result to be -2 or -1 when incremented.

[0113] To make things further complicated, our conversion method needs some calculations to find L, G, and S for negative integers. The correct rounding will require us to do the two's complement process (flip and add 1), then calculate L, G, and S, but the add 1 is slower than just the flip. Ideally, we would like to calculate the actual L, G, and S from the original shifted input (i.e., from the input before we have done anything with the sign). So both floating point 1.37 or -1.37 will be right shifted to the integer 1).

[0114] Let L0, G0, and S0 be the least significant bits (lsbs), guard bits, and sticky bits before the flip, and let Li, Gi, and Si be the lsbs, guard bits, and sticky bits after the flip, and finally let L, G, and S be the lsbs, guard bits, and sticky bits after the flip and add 1.

[0115] If S0 is zero, then all the bits that contribute to Si are ones, so S (obtained by adding 1 to those Si bits) is also zero. If S0 is not zero, then Si is not all ones, so S is non-zero. Thus in all cases, S0 = S.

[0116] If G0 is zero, then Gi is 1, and G is also one, except when there is a carry from the S bits, which only happens if S0 is zero. If G0 is 1, then Gi is zero, and again G is also one, except when there is a carry from the S bits, which only happens if S0 is zero. Thus G = G0^S0.

[0117] By very similar logic, L = L0^(G0|S0).

[0118] Since we have L, G, and S for both negative and positive integers, we can derive the rounding rules:

[0119]

[0120]

[0121] Table 6

[0122] Fixed-point rounding works exactly the same way as for integers. The rules for unsigned conversion (to integer or fixed point) are the same as for positive conversion.

[0123] inject rounding

[0124] A faster way to do the rounding is to inject the rounding constants as part of the effective number addition, which is part of almost every FP operation. To see how this works, consider adding numbers in dollars and cents, then rounding to the nearest dollar. If we do the following addition:

[0125] $1.27

[0126] +$ 2.35

[0127] $3.62

[0128] We see that the sum, $3.62, is closer to $4 than to $3, so either rounding to the nearest mode should return $4. If we represent the numbers in binary, we can use the L, G, S method from the last section to get the same result. But suppose we just add fifty cents, then truncate the result? 1.27

[0130] +2.35

[0131] +0.50 (rounding injection) 4.12

[0133] If we just returned the dollar amount ($4) from the sum ($4.12), we have rounded correctly using the RNA rounding mode. If we added $0.99 instead of $0.50, we would round correctly using the RP rounding. The RNE is slightly more complicated: we add $0.50, truncate, and then see if the remaining cents are non-zero. If the remaining cents are non-zero, the truncated result is correct. If the remaining cents are zero, we have just between two dollar amounts before injection, so we pick the even dollar amount. For binary FP, this is equivalent to setting the least significant bit of the dollar amount to zero.

[0134] Adding three numbers is only slightly slower than adding two numbers, so we obtain the rounded result much faster than in the case of adding two significands by using rounding injection, checking L, G, and S, and then incrementing the result according to the rounding mode.

[0135] implement inject rounding

[0136] For FP, the rounding injection is one of three different values (depending on the rounding mode and, sometimes, the sign of the result).

[0137] Both RNA and RNE require us to inject 1 at the G position (which is like adding $0.50 in the dollar and cent example).

[0138] The RP and RM rounding depend on the sign as well as the mode. RP rounds up positive results (increasing the magnitude of the significand toward positive infinity), but truncates negative results (picking the significand closer to positive infinity). Similarly, RM rounds up negative results (increasing the magnitude of the significand toward negative infinity), but truncates positive results (picking the significand closer to negative infinity). Thus, we split the RM and RP into two cases: rounding up when the sign matches the direction of rounding (RU), and truncating when the sign does not match the rounding injection (RZ). For the RU case, we inject 1 at the G bit position and at each position that logically contributes to S (which is like adding $0.99 in the dollar and cent example).

[0139] For the RZ and RX modes, as well as for the RP and RM modes that reduce to the RZ mode, we inject zero.

[0140] For most rounding patterns, add the rounding injection and then truncate to give the correct rounding result. Two exceptions are RNE and RX, which require us to check G and S after addition. For RNE, if both G and S are zero, we set L to 0. For RX, if either G or S is non-zero, we set L to 1.

[0141] FP number is not a real number

[0142] It's easy to think of FP numbers like real numbers, but they are fundamentally different, even for the most basic properties:

[0143] They are not associative. For example, in SP, we can add three numbers together and return 1 million or zero, which may not be what people would consider rounding error:

[0144] (2 45 +-2 45 )+2 20 =2 20

[0145] 2 45 +(-2 45 +2 20 ) = 0

[0146] They do not obey the distributive law. Also in SP:

[0147] 3,000,001*(4.00001+5.00001)=0x4bcdfe83

[0148] (3,000,001*4.00001)+(3,000,001*5.00001)=0x4bcdfe82

[0149] And the situation becomes even worse when overflow occurs:

[0150] 2 50 *(2 78 -2 77 ) = 2 127

[0151] (2 50 *2 78 )-(2 50 *2 77 )=infinity

[0152] For some specific implementations, they are not even commutative, unless we are in the default NaN mode (the mode that converts all NaNs to a single NaN), because in general, nanA + nanB! = nanB + nanA. Number addition and multiplication are commutative.

[0153] Due to the IEEE NaN rules, there is no multiplicative identity or additive identity. One and zero serve as the identity for numerical values.

[0154] One useful way to think of FP numbers is as very long fixed point numbers, where at most a few (53 for DP) consecutive bits can be non-zero. For example, a non-infinite DP number can have the first bit of the significand in any of the 2046 positions, and that first bit is followed by 52 other significand bits, and there is a sign bit, so any finite DP number can be represented as a 2099-bit fixed point number. Examining this way, it becomes very obvious that adding two FP numbers together will not generally produce another FP number: the result of the addition must be rounded so that it becomes an FP number.

[0155] A known problem with floating point (FP) arithmetic is that it is non-associative, which is the fact that causes the sum problem:

[0156] • programmers need to worry about wildly different results, even when adding 3 numbers

[0157] • programmers use wider formats than they need, in the hope of avoiding wildly different results

[0158] • programmers cannot easily parallelize code, because the sum is not reproducible unless computed in exactly the same order.

[0159] For example, in single precision,

[0160] 2 20 +(-2 44 +2 44 )=2 20

[0161] But

[0162] (2 20 +-2 44 )+2 44 =0

[0163] Depending on the order in which the operations are performed, the result is one million or zero. This is an extreme example because the exponents differ by 24, but we can get different answers if the exponents differ by 1, or even if all the exponents are the same and we add more than 3 numbers. The C programming language solves the reproducibility problem by requiring that sums be evaluated in order, from left to right, but this has no effect on correctness, and makes parallelization impossible.

[0164] These problems are especially acute for high performance computing (HPC) where programs can need to add millions of numbers. Programmers handle these problems in parallel, but the lack of reproducibility makes debugging more difficult than it would otherwise be. Even if the reprogramming of the machines is done perfectly, different configurations of those machines will produce different answers.

[0165] HPA representation (anchored data value)

[0166] A new data type has been proposed that allows fast and correct accumulation of floating point (FP) numbers within a programmable range. For a modest range that will hold most problems, accumulation is faster than FP addition and is associative. Associative addition allows problems to be handled in parallel while still giving reproducible and correct results, enabling, for example, 100x or more speedup compared to existing hardware. We believe that these benefits will be irresistible in the high performance computing (HPC) space and attractive for many non-HPC applications.

[0167] Figure 1 A data processing apparatus 2 for performing data processing operations under the control of program instructions is shown schematically. The data processing apparatus 2 includes a memory 4 that stores program instructions 6 and data 8 to be processed. A processor core 10 is coupled to the memory 4 and includes a register file 12, processing circuitry 14, an instruction fetch unit 16, an instruction pipeline unit 18, and an instruction decoder 20. It will be appreciated that in practice the data processing system 2 can include many additional elements and that the representation has been simplified to aid understanding. Figure 1 In operation, program instructions 6 are fetched by the instruction fetch unit 16 from the memory 4 and provided to the instruction pipeline 18. As program instructions progress through the instruction pipeline 18, they are decoded by the instruction decoder 20 and generate control signals for controlling the operation of the register file 12 and the processing circuitry 14 to perform the processing operations specified by the decoded program instructions. A number of input operands can be read from the register file 12 and provided to the processing circuitry 14, where they are manipulated, and the resulting values are then written back to the register file 12.

[0168] The register file 12 can have a number of different forms. The operands to be manipulated can for example include floating point operands, fixed point operands, integer operands, and HPA or RHPA number operands (as will be described later). The register file 12 can be configured to store a mix of these types of operands, depending on the configuration of the register file 12. The operands can have different levels of precision, as can be predefined by their format, or as can be programmably specified using metadata associated with the registers, as will be described later with respect to HPA number operands.

[0169] AsFigure 1 As shown, the register set 12 can include a metadata register 22 for specifying metadata associated with the HPA or RHPA values stored in the corresponding data registers of the register set 12 (examples of the contents of the metadata are given below). In some cases, each data register can have a corresponding metadata register 22, while in other cases, two or more data registers can share metadata specified by a single metadata register 22.

[0170] Figure 2 A floating point operand is shown schematically. A floating point operand is comprised of a sign, an exponent, and a significand. A floating point operand can represent values of various magnitudes indicated by its exponent value. The precision with which numbers can be represented is limited by the size of the significand. Floating point operations are generally more complex and slower to implement than integer arithmetic.

[0171] Figure 2 A 64-bit integer operand is also shown. Such an integer operand can represent a number in the range 0 to (2 64 -1) for unsigned integers, or a number in the range -2 63 to 2 63 -1 for signed integers. Integer arithmetic is generally fast and consumes relatively little energy to perform (compared to floating point arithmetic), but the disadvantage is that a relatively limited range of values can be specified compared to the range of numbers that can be represented by floating point values.

[0172] Figure 2 An HPA (high precision anchored) number comprising a vector having multiple components (three in this example), each component comprising a 64-bit integer, is also shown in this example. The HPA number has metadata associated with it. The metadata includes an anchor value that indicates the effective value of the bits of a component that forms part of the HPA number. The anchor value specifies, directly or indirectly, a lower bound of the bit effective value and an upper bound of the bit effective value. The term metadata used below can be considered to correspond to data comprising an anchor value that specifies a bit effective value of an HPA number. The different components together specify bit values that span the bit effective value range contiguously. Depending on the location of the lower bound of the bit effective value and the upper bound of the bit effective value, the bit effective value range can include a binary point position. It is also possible that the binary point position can be outside the bit effective value range specified for a particular HPA value.

[0173] The anchor value can be provided so that it is able to represent a range of bit effective values that extends from the smallest effective value that can be represented by a floating point value (e.g. a double precision FP value) up to the highest bit effective value that can be represented by that floating point value.

[0174] The number of components forming the HPA number can vary between different implementations. In some embodiments, the size of the components can be fixed, but in other embodiments can be variable. In some embodiments, the overall width of the bit significand range can be constrained to change in units of the fixed component size (e.g., for 64-bit components, the bit significand range can have a width of, e.g., 64, 128, 192, 256,...). It is also possible that the width of the bit significand range can vary continuously in steps of one bit width.

[0175] The anchor value (within the metadata) can be programmable such that a programmer can set the significand value corresponding to the HPA value. The anchor value can specify the bit significand in a number of different ways. One example is to specify the lower bound bit significand for each vector component. Thus, each vector component can include an integer value representing the portion of the overall bit significand range that is significant for that value, and metadata representing the significand value of the lowest bit within that component (anchoring it). Another option is that the anchor value specifies the lower bound of the bit significand for the entire HPA number and the overall width of the bit significand range. Another option is that the anchor value can include data specifying the lower and upper bounds of the bit significand range. Still further variants are also possible, such as the anchor value including the lower bound of the bit significand range and the number of components, where those components are known to be fixed width components.

[0176] Figure 3 The relationship between the range of values that can be represented with a double precision floating point and the significand range of an HPA number is schematically illustrated. In terms of a double precision floating point number, the range of bit values that can be specified is from approximately 2 -1074 to 2 +1023 (not counting denormal numbers).

[0177] As illustrated, the HPA number has a programmable bit significand range that can be thought of as a window of bit significand values within the range of bit significand values that can be represented with a floating point value. This programmable bit significand can be specified by a lower bound and an upper bound, and depending on the values of the lower bound and the upper bound, can be thought of as sliding along the range of bit significand values provided by the floating point value. The width of the window, as well as its starting point and ending point, can be specified by appropriate values of the programmable metadata specifying the bit significand, which includes the anchor value. Thus, the HPA number can have a form selected by a programmer to match the computation to be performed.

[0178] The HPA format allows two or more values to be quickly, accurately, and associatively added together while still allowing a wide range of values of the effective value to be represented. Since HPA values are simply two's complement numbers, they can be added using integer adders and do not need to be rounded or normalized as in floating point arithmetic, which allows a series of additions to be processed in parallel since the result will be the same regardless of the order in which the values are added. However, by limiting the metadata that specifies the programmable effective value of the HPA values, the full range of effective values of an equivalent floating point value can still be represented, but without the need to provide very wide adders (e.g., to add two's complement numbers over the entire range that can be represented by a double precision floating point value would require a 2098 bit adder), instead the programmable effective value allows a smaller adder to focus on a particular window of programmable bit effective values within the larger range. In practice, most computations do not need the full range of effective values available to double precision floating point. For example, subatomic problems can accumulate very small values and astronomical complex functions can accumulate very large values, but adding the width of a proton to the distance between galaxies is not typically useful. Even for high performance computing, most accumulations occur within a limited range.

[0179] In general, the programmer writing the program will know the expected range of values that the useful results can fall into (which depends on the application). The programmer can determine that all of the data for a particular sum will have magnitudes less than 2 60 and values with magnitudes less than 2 -50 will not affect the sum in any meaningful way, so in this case the numbers can be added associatively in any order by using HPA format data with an overall data width of 128 bits and an anchor value that specifies the effective value of the least significant bit to be -50 for this particular application.

[0180] Thus, by using an anchor value to limit the range of effective values (for which results are computed), relatively small hardware can be used to compute results within a programmably defined window. If the addition results in an overflow above the upper effective value boundary of the defined range or an underflow below the lower effective value boundary, an exception can be generated and this can signal to the programmer that the effective value boundaries have been defined in error, and that the process should be repeated with different metadata (e.g., a different anchor value or a different overall size of the HPA values) to define a different effective value window for the results.

[0181] When two HPA values are added or subtracted, the anchor value is the same for both HPA values, and the result also has the same anchor value - this is unlike floating point arithmetic, where the addition or subtraction of two values can result in the result having a different exponent than either of the inputs due to the normalization of the result. If the inputs have different anchor metadata, the inputs are shifted to align their own values with the desired target range of valid values for the result. If the inputs are provided in a representation other than HPA (e.g., integers or floating point), they are converted to HPA values that share the same anchor value, and are added to form a result that has the same anchor value. Thus, the metadata of an HPA register can be viewed as defining a target range of valid values for the result values to be generated in that register, and regardless of the actual valid values of the input values, the hardware will not compute bits outside of the target range of valid values.

[0182] RHPA representation

[0183] While the HPA format allows for faster addition than floating point, when the size of the HPA values becomes relatively large, then it can still be relatively slow to add two HPA values using integer arithmetic. For example, the HPA format can require adding operands that span multiple lanes, which can be undesirable in larger vector implementations. For example, adding two 256-bit values or 512-bit values can take some time, as each 64-bit lane of the addition can be performed sequentially to accommodate the carry-in from one lane to the next.

[0184] By using a redundant high-precision anchor (RHPA) format as shown in Figure 4 As in the HPA format, RHPA numbers include a variable number of components with metadata that defines an anchor value that enables the processing circuit 14 to identify the valid values of the bits of each component. Again, the anchor value can be programmable. For RHPA, the metadata can identify the valid values of each component in any of the ways described above for HPA. However, in the RHPA format, the numerical values are represented using a redundant representation, where adjacent lanes of the vector include bits of overlapping valid values, which allows constant-time addition regardless of the number of lanes being computed. The redundancy enables operations such as addition, accumulation, and multiplication to be performed using shorter adders without propagating carry information between the adders. This greatly speeds up the processing of the data values.

[0185] As Figure 4The M-bit data value represented using RHPA is split into respective vector lanes (also referred to as components, elements, or parts) each comprising N bits, where N < M. In this example, N is 64 bits, but this is merely an example, and other lane sizes (e.g., 32 bits or 128 bits) are also possible. Each N-bit part is split into a number V of overlapping bits and N-V non-overlapping bits. In this example, the number V of overlapping bits is the same for each N-bit part, but it is also possible to have different N-bit parts with different numbers of overlapping bits.

[0186] When an integer or floating point number is converted into RHPA format, some of the non-overlapping bits are filled with non-sign information mapped from the original integer or floating point number, and the overlapping bits are filled with sign bits. For purposes of lane-based addition and subtraction, each lane behaves like an N-bit signed two’s complement number (with carry propagation from non-overlapping parts to overlapping parts as necessary), but when viewed from a multi-lane perspective, the lanes form a redundant mixed-sign representation of a larger P-bit number. In Figure 4 In the example of FIG. 1, there are four lanes, so M = 256, but the number of lanes can vary depending on the hardware implementation and / or metadata defined for a given RHPA number.

[0187] Figure 4 Part (2) of FIG. 1 shows the relative effective value of each bit of the RHPA number shown in part (1). The overlapping bit V[0] of the least significant lane has the same effective value as the V least significant bits of the non-overlapping bit NV[1] of the next lane. Likewise, the overlapping bits V[1] and V[2] have the same effective value as the V least significant bits of the non-overlapping bits NV[2] and NV[3], respectively. The overlap in effective value between lanes means that the RHPA number as a whole represents a P-bit value, which is less than the total number of stored bits. If V is the same for each N-bit part (except for the top part), then More generally, if different lanes can have different numbers of overlapping bits, then P = M -∑V, where∑V is the sum of the number of overlapping bits in each lane except for the top lane.

[0188] In each overlapping portion of the P-bit value, the actual bit value of the P-bit number is represented by the sum of the overlapping bits V of the lower lane and the non-overlapping bits NV in the higher lane (taking into account any carry that can result from adding the non-overlapping bits NV and the overlapping bits in the lower lane). Thus, in part (3) of FIG. 1, the RHPA value is converted to an equivalent integer value, where the overlapping bits in each lane are sign-extended and added to the non-overlapping bits of the higher lane (from low order to high order, adjusting the overlapping bits after each lane addition). Figure 4

[0189] ​The RHPA number is redundant in the sense that there are more than one way to represent a given P-bit number using the M bits of the RHPA value. For example, considering the overlap in the two lowest channels, in the example of the number of overlapping bits V=4, if the corresponding bit of the P-bit value is 1111, one way to represent this would be to have overlapping bits V[0]=0b0000 in the lower channel and non-overlapping bits NV[1]=0b1111 in the next highest channel. However, other ways to represent the same value could be, for example, V[0]=0b0101 and NV[1]=0b1010, or V[0]=0b1111 and NV[1]=0b0000.

[0190] It should be noted that the overlapping bit V[3] in the highest channel is not a true overlapping bit, since there are no higher-order channels to overlap. Therefore, it is often useful to consider higher-order channels as having all non-overlapping bits. Thus, in some cases, the top channel can be considered to be formed entirely of non-overlapping bits (such that the most significant bit of the P bit value as a whole corresponds to the most significant bit of the M bit value in the top channel).

[0191] However, in other implementations, it may be preferable to also treat the top channel as having overlapping bits, such that the most significant bit of the P-bit value represented by RHPA corresponds to the most significant bit of the non-overlapping portion (excluding the overlapping portion) of the top channel. This approach can make circuit implementation easier if it allows for more symmetrical processing of each channel (where fewer modifications are needed to the processing of the top channel compared to other channels).

[0192] Through such Figure 4 The diagram illustrates a P-bit value in redundant form, allowing the addition of several RHPA numbers without carry-over between channels. This is because carry-overs resulting from the addition of non-overlapping portions in a given channel can be accommodated within the overlapping portions of the same channel without propagating the carry to the next channel. The addition performed in each channel simply produces two or more N-bit signed integers, which are added by performing regular N-bit two's complement addition, completely independent of the corresponding N-bit additions in other channels. This means that each addition in the N-bit addition can be performed in parallel, allowing the entire M-bit value to be added in the time required to perform the N-bit addition, regardless of the number of channels.

[0193] In fact, even without carry between channels, any carry resulting from the addition of non-overlapping portions in the overlapping portion can be collected in the overlapping portion, which will result in at least (2) V-1 -1) sum of these RHPA numbers (if channels with different numbers of overlapping bits exist, then V in this expression will be the minimum number of overlapping bits in any given channel with overlapping bits). The (2) V-1) would be the first addition that could generate a carry between channels (because the top overlap bit is a sign bit, so channel overflow occurs when there is a positive or negative overflow from the second most significant overlap bit, which has already been performed a minimum of 2 V-1 additions after which it occurs starting from an RHPA number where all bits are 0). For example, if V = 14, this would allow at least 8191 RHPA numbers to be added to the accumulator (i.e., a total of 8192 values) before there is any risk of overflow from a single channel. This is particularly useful in the field of high performance computing where many input values are typically added together. In practice, since not every addition will result in a carry into the overflow portion, there can be times when more than 2 V-1 additions without overflow from the top bit of the N-bit portion.

[0194] Occasionally, if enough additions have been performed to result in a risk (or actually) overflow from the top bit of the N-bit channel, an overlap reduction operation can be performed to convert a given RHPA value to a second RHPA value in which the overlap bits represent a smaller magnitude than the overlap bits of the given RHPA value, effectively freeing up bit space in the overlap portion for more carries. Additionally, this overlap reduction can also be performed when converting an RHPA number back to another format such as an integer or a floating point. However, in practice, this overlap reduction operation is typically not needed, so the RHPA is able to greatly save processing time by allowing multiple M-bit additions of inputs to be performed in the time it takes for an N-bit addition. Note that the term "overlap reduction" does not mean that the overlap bits in every channel must be reduced to a smaller magnitude. It is sufficient that the magnitude of the overlap bits of at least one channel be reduced, and it is possible that some forms of overlap reduction can result in an increase in the magnitude of the overlap bits in a given channel.

[0195] efficient storage and manipulation of HPA numbers

[0196] For the following description, it will be assumed that the form of HPA used is the RHPA form described above in which each portion includes multiple overlap bits, but the techniques described herein are equally applicable to other forms of HPA, for example, HPA forms in which the different portions do not include overlap bits. In the following, the term HPA will be used to refer to the HPA values being manipulated, regardless of whether they are in redundant form.

[0197] According to the previously discussed Figure 4It will be obvious that different HPA portions (anchor data elements) of an HPA number (anchor data value) can reside in different channels of a single vector register. However, this presents several potential problems. For example, when creating the HPA form from a floating-point operand, the fractional part of that operand, along with the desired anchor value, needs to be propagated to all channels within the relevant vector register. Each channel will then have a different channel anchor based on the anchor value. Furthermore, this can lead to a waste of vector register resources if the vector register is significantly larger than the long integer value of the HPA number, such as when a 1024-bit register holds a 200-bit long integer of the HPA number. Additionally, processing can be problematic if the vector register does not have enough bits to represent all portions of the long integer of the HPA number, for example, if the vector register is 128 bits wide and needs to represent a 200-bit long integer of the HPA number.

[0198] In the examples discussed below, alternative storage arrangements are provided for the various portions of the HPA number. Specifically, the long integers of the HPA number are arranged to be stored within a shared channel spanning multiple vector registers, such as... Figure 5 The diagram is schematically illustrated. Specifically, a set of vector registers 100 is provided, where each vector register can be considered to consist of multiple segments for storing data values. Furthermore, multiple channels can be considered (to...) Figure 5 The orientation shown extends vertically through the vector register, with the first four channels... Figure 5 The figures 102, 104, 106, and 108 in the appendix indicate this. Long integers of HPA numbers can then be stored within a common channel by storing different portions of the HPA integer value in different vector registers. This is schematically illustrated for an exemplary HPA integer 110, which is considered to consist of four parts, one of which is stored in each of the vector registers Z0, Z1, Z2, and Z3. Furthermore, all parts are stored within the common channel 102. Storing the integers of HPA numbers in this way yields several significant benefits. For example, the size of the integer is not constrained by the width of a single vector register. Furthermore, inefficient use of vector registers can be avoided because multiple HPA integers can be stored across different channels of various vector registers, where these integer values ​​can be operated on in parallel in a SIMD manner. For example, consider… Figure 5 ,if Figure 5Each of the illustrated vector registers will provide 16 lanes, then 16 HPA numbers can be stored in four vector registers Z0 to Z3, each HPA number occupying a different lane. It can be seen therefore that this approach significantly improves scalability and provides a vector length independent technique. This therefore allows the technique to be employed in a variety of different systems, each of which can operate using different sized vector registers. There are therefore many applications where the use of this storage technique for HPA values will yield significant performance benefits, but one example is associated with systems employing the Scalable Vector Extension (SVE) proposed by Arm Limited.

[0199] Arm Limited has announced the Scalable Vector Extension (SVE) as its 64-bit ISA, targeting scientific HPC applications. While SVE does not currently include HPA support, it continues to evolve, and some modest additions to its instruction set will enable very high HPA performance. The "scalable" part of SVE refers to the fact that it does not need to be the same vector length for all implementations: SVE vectors can be implemented in hardware as any multiple of 64-bit lanes, from 128 bits to 2048 bits. A small chip might implement only 128-bit vectors, while a supercomputer might implement 1024 or even 2048-bit vectors. It would not be possible to hold a 200-bit integer within a 128-bit implementation, and it would be wasteful in a 2048-bit implementation, but holding a certain number of 200-bit integers that span 4 registers of these registers takes advantage of the scalability of SVE and works well on any hardware implementation, from small to large. SVE also allows programmers to use shorter or longer integers as needed: a 100-bit integer can fit in the corresponding lanes of 2 vector registers, and a 500-bit integer can fit in the corresponding lanes of 10 vector registers.

[0200] For performance and area reasons, SVE performs arithmetic within 64-bit lanes. We propose to perform HPA addition by breaking the large i HPA numbers into smaller redundant blocks. Each 64-bit lane will hold a specified portion of i (say p = 50 bits, but this can be programmable), with the remaining 64-p bits used to hold carries within the lane. These remaining bits are called "overlap" bits because they have the same numerical weight as the lsbs of the next most significant lane. Addition within a lane is simply a regular 64-bit integer addition. Every 2 64-p cycles (i.e. around every 16,000 cycles for p = 50), a redundancy elimination step can be needed to prevent lane overflow, and at the end of each computation, a lane-by-lane process will be needed to obtain the non-redundant answer.

[0201] To convert FP input f to HPA number format (i, a), each 64-bit lane checks the exponent of f, compares it to the anchor a, and then determines whether any part of the significand of f should be added to the considered i part. This comparison can be done in parallel across all applicable lanes. While the significand of f can span two parts (or three parts for FP64 products, depending on the value of p), each part can be created and manipulated independently.

[0202] An exemplary conversion of an FP32 number to a two-part HPA (where a is chosen to be 0 and p is chosen to be 50) is set forth below. In this example, assume that the FP32 number occupies the "right" 32 least significant bits of a vector register lane, and assume that the HPA number occupies a 64-bit register lane (including 50 bits of value and 14 overlapping bits). If the FP number is:

[0203] f = +1.0110 1011 1010 0010 1111 011 x 2 60

[0204] FP32 significand, f[23:0] = 1 0110 1011 1010 0010 1111 011

[0205] Part 1 of the HPA number will have an adjusted part anchor = 50, and is computed as follows: i[1] = f[23:0] - part anchor = 37 - 50 = -13 places (ve left shift +ve right shift -> i[1] = {{14 0's}, {39 0's}, f[23:13] = 1 0110 1011 10})

[0206] (The adjustment of the exponent by 23 takes into account the fact that the exponent representation of a floating point value implies that the decimal point is at the most significant bit of the 23rd decimal place of the significand, while the anchor represents the least significant bit of the decimal).

[0207] Part 0 of the HPA number will have an adjusted part anchor = 0, and is computed as follows: i[0] = f[23:0] - part anchor = 37 - 0 = 37 places -> i[1] = {{14 0's}, f[12:0] = 10 0010 1111 011, {37 0's}}

[0208] This results in the following HPA form:

[0209]

[0210] Table 7

[0211] In general, rounding the HPA result correctly to a single FP result must be a sequential process, requiring the propagation of carry and rounding information per lane. This will require multiple loops, but this must only happen once for each accumulation. Alternatively, if p < 53, a non-redundant HPA number occupying several 64-bit lanes can be converted in parallel with a vector of FP64 numbers. The resulting vector should then be "renormalized" so that the most significant element represents the full HPA number, with an accuracy of 0.5 ulp.

[0212] Having now described the basic principles of HPA processing at a high level, we now describe in more detail how HPA accumulators can be implemented in SVE.

[0213] SVE supports vector register lengths of k x 128 bits up to the current maximum of 2048 bits (i.e. 1 < k < 16), and is based on the concept of "vector length agnostic" (VLA) processing whereby different CPUs with different SVE vector register lengths can all run the same SVE program. An SVE program reads the available vector length from a system register and "self-adjusts" to make use of that available vector register length. Thus, an SVE program executes in 128-bit granules, where the CPU can support parallel processing of as many granules as the available vector hardware length.

[0214] As previously mentioned with reference to Figure 5 In order to implement vector length agnostic processing, HPA numbers can be laid out across multiple SVE registers. Each register can hold the bits of the same significant value of a different HPA number: i.e. each register is associated with a significant value that gives a number anchor adjusted relative to the position of each part of the HPA number.

[0215] Returning to the previous example of a 200-bit HPA number holding P = 50 bits in each part, if the anchor of the HPA number is -80, then the significant value information about the four parts would be (+70, +20, -30, -80), with 14 overlapping bits per 64-bit part. Note that, in accordance with the example in Figure 5 The parts of the HPA number need not be stored in consecutive registers.

[0216] The main advantage of laying out HPA numbers in this way is that they (or long integers) can be processed in SIMD fashion, even in SIMD implementations that are shorter than the long HPA numbers (e.g. 128-bit vectors). The secondary advantage is that by storing much shorter HPA numbers within each vector, longer SIMD implementations (e.g. 1024-bit vectors) are not wasted. Provided there are enough integers or HPA numbers to fully utilise the vector, regardless of the SVE implementation length.

[0217] Laying out HPA numbers across several registers also allows HPA arithmetic to be highly parallelised with vectors of FP numbers accumulated within their own 64-bit lanes. Furthermore, loading large numbers of FP numbers from memory reduces to simple and efficient contiguous vector loads. Finally, this layout of HPA numbers allows existing SVE instructions to be used to perform important HPA calculations such as eliminating redundancies or adding HPA numbers together, as multiple HPA integers can all be processed in parallel from low-order bit to high-order bit. This scheme also speeds up conversion of HPA numbers to FP and re-normalisation, again because multiple HPA numbers can all be processed simultaneously from high-order lane to low-order lane or from low-order lane to high-order lane.

[0218] Figure 6 The HPA numbers laid out in the manner discussed in Figure 5 how the HPA numbers laid out in the manner discussed in

[0219] The multiple 64-bit lanes 152, 154, 156 are considered to extend through the set of vector registers, and separate conversion and processing circuits 170, 172, 174 are associated with each lane. The circuits 170, 172, 174 are arranged to operate on a single portion of the HPA number at a time, in order to produce a corresponding result portion to be stored in a destination register 180. According to the previously discussed Figure 5 It will be appreciated that each result portion of the HPA result number will occupy a different destination register, so as the circuits process different portions of the HPA number, the corresponding result portions are written into different destination registers.

[0220] As will be discussed in more detail later, metadata is provided for the conversion and processing circuits 170, 172, 174 to reference when performing their conversion and processing steps. In particular, in this example, metadata is stored for each lane within the further source register 160. A portion of metadata within the lane metadata is provided for each portion of the HPA number being processed within that lane. The metadata will identify the significant value (adjusted anchor) associated with the corresponding portion, and can identify other information such as the number of overlap bits. When the circuits 170, 172, 174 are processing a particular portion of the HPA number, these circuits will retrieve the associated portion of metadata from the lane metadata held within the source register 160.

[0221] In Figure 6In the illustrated example, each conversion and processing circuit will receive an input floating point operand and the associated metadata portion for the portion of the HPA number to be processed, and will then generate the relevant HPA portion from the input floating point operand using techniques such as those described previously with reference to the example illustrated in Table 7. The generated HPA portion can then be stored directly in the result register 180, or can be subject to some processing function in order to generate the associated result portion. For example, in one embodiment, an accumulation operation can be performed in which the current HPA result portion is retrieved from the destination register, then accumulated with the HPA portion generated from the input floating point operand in order to produce an updated result portion, which is then written back to the relevant segment of the destination register 180.

[0222] With this approach, it can be seen that by performing multiple iterations, multiple accumulation operations can be performed in parallel within each lane in order to generate a result portion representing the accumulated result. This process can also be repeated for each of the portions of the HPA number in order to produce a series of result portions within each lane, which collectively represent the result HPA value.

[0223] In one example arrangement, HPA processing requires information about the anchor ("metadata"), lane overlap, and lane type or position within the mantissa (top, bottom, or middle). It is expected that HPA numbers will typically not exceed 200 bits wide, with the anchor range similar to IEEE FP32, such that the HPA accumulator will typically include no more than four portions. The HPA metadata for a 200-bit accumulator that traverses the 4 64-bit portions can then be organized as 4 16-bit fields, as illustrated in Figure 7 .

[0224] In particular, a source register 160 can be specified in which four metadata portions are provided within each lane (e.g., 64 bits), as illustrated by reference numerals 162, 164, 166, 168. Each metadata portion can then provide metadata for the associated portion of the accumulator result. As illustrated in the expanded segment in Figure 7 , the significant value (adjusted anchor) information can be included in a first sub-portion 192, e.g., using 9 bits, while the overlap information can be captured in a second sub-portion 194, e.g., including 5 bits. If desired, lane type information can also be captured in a third sub-portion 196 to identify whether the associated portion is a top portion (i.e., representing the most significant bits), a bottom portion (representing the least significant bits), or a middle portion.

[0225] Within any particular lane, the accumulated HPA values will all be arranged to have the same anchor, so the metadata for the lane will apply equally to all HPA values processed within the lane.

[0226] In principle, different metadata can be specified for each of the lanes, so that the values processed in one lane do not necessarily have the same anchor as the values processed in another lane. However, it is often the case that all values processed within all lanes will be arranged to have the same anchor value, and in this case the 64-bit metadata can be stored and replicated across the vector register 160. This enables the various HPA results produced for each of the lanes to then be easily accumulated with each other in sequence in order to produce a single scalar HPA result.

[0227] In this arrangement, an SVE instruction for HPA that requires reference to metadata can specify a metadata register as well as a 2-bit pointer to the specific 16-bit metadata for the HPA part being processed.

[0228] It should be noted that while Figure 7 One mechanism for providing the metadata is shown, but alternative schemes for storing the metadata in a more compressed manner can also be devised, so that for example 8 lanes of metadata can be stored in 64 bits. In particular, the "lane type" field can not be needed, and the size of the ovlp and valid value fields can be reduced to reflect the limited number of available configurations.

[0229] An important HPA operation is to convert and accumulate FP numbers into HPA format. This operation can be performed on each FP number to be accumulated, while other HPA operations (conversion back to FP, elimination of HPA redundancy, etc.) occur far less frequently. Therefore, it is desirable to provide efficient hardware support for converting and accumulating FP numbers.

[0230] Figure 8 A possible 64-bit datapath for this operation, which will be repeated on the vector unit, is shown, so Figure 8 The conversion and processing circuit 170, 172, 174 is shown in more detail. Figure 6 An exemplary configuration of each of the conversion and processing circuits 170, 172, 174 is shown.

[0231] The input floating point data 210 is made up of a sign portion 212, an exponent portion 214 and a fraction portion 216. The relevant metadata portion from the metadata held for the lane is then extracted as the metadata portion 200, which includes the lane type field 202, the overlap field 204 and the valid value field 206. An OR function 220 performs an OR operation on the bits of the exponent in order to generate the most significant bit of the significand, which is then preset to the fraction bit 216 in order to form the significand. In particular, if the exponent is non-zero, this indicates that the floating point number is a normal floating point number, and so the most significant bit of the significand is a logical one value. However, if all the bits of the exponent are zero, this indicates a subnormal value, and so the most significant bit of the significand should be set to zero.

[0232] Subtraction block 222 is arranged to subtract the significand 206 (adjusted as necessary for the exponent offset and small number length) from the exponent 214, e.g. using the technique described previously with reference to Table 7, to produce a shift amount, which is then used to control a shift circuit 224 to shift the floating point significand by the appropriate amount (performing a right shift or a left shift as necessary).

[0233] AND circuit 226 then receives the overlap information 204 and masks the output from the shift circuit by the specified number of overlap bits (equal to 64-P). Thereafter, if the floating point number is negative (as indicated by the sign value 212), XOR circuit 228 performs a ones complement function on the output from the AND circuit 226. At this point, the bits of the input floating point number pertaining to a particular HPA portion having a given significand and overlap amount can be used as a ones complement number and can be provided as one input to adder circuit 230 (which also takes a carry in value of 1 if the floating point operand is negative). It will thus be seen that the relevant HPA portion can be "dynamically" generated from the input floating point value and then subjected to the appropriate processing operation to generate the corresponding result portion.

[0234] In the example shown, it is assumed that the processing operation is a selective accumulation operation. In particular, AND circuit 240 can be used to selectively propagate the current value held in register 235 as a second input back to adder 230, thereby allowing the previous result portion to be accumulated with the input operand portion output from the conversion circuit to produce an updated result portion stored in register 235. The arrangement shown combines a 64-bit adder and register support to enable pipelined execution of back-to-back HPA conversion and accumulation instructions in the manner shown.

[0235] There are a number of ways in which the circuit shown can be used to perform the above-described operations, but in one embodiment a single instruction is used to initiate the above-described functionality of Figure 8 Figure 8 Such an instruction can be referred to as an FP to HPA conversion and accumulation instruction.

[0236] In one example, the opcode of the FP to HPA conversion and accumulation instruction (mnemonic "FCVTH{A}", where {A} indicates the optional accumulation) includes identifiers for the FP source register, the metadata register, the destination accumulator register, and an index to select a subfield of the metadata register. This is very much in line with the SVE ISA design philosophy of referencing no more than three vector registers from the opcode.

[0237] A short sequence of existing SVE instructions implementing other important HPA operations can be constructed.

[0238] ​Periodically, it is important to eliminate the redundancy of HPA numbers in order to avoid partial overflow. This can be achieved by simply adding the accumulated carry bits in the overlap region of the lower HPA part to the LSB of the next highest HPA part. In SVE, this can be achieved in a 3-instruction process:

[0239] (i) arithmetic right shift the lower part by P positions;

[0240] (ii) add the shifted overlap bits to the next higher HPA part;

[0241] (iii) immediate AND the overlap bits with a mask having P derived from the lower HPA part to force them to zero.

[0242] The process can be applied to each pair of adjacent HPA parts, proceeding from the lowest lane upwards.

[0243] Alternatively, dedicated instructions for overlap propagation and overlap clean-up can be provided, as described below with respect to Figure 13 and Figure 14 .

[0244] After a large number of FP numbers have been accumulated, the results are stored in a plurality of accumulators spanning multiple SVE lanes. These accumulators can then be added together to return a scalar result for each vector of HPA lanes having the same index. In SVE, this can be readily achieved by performing a vector reduction on the accumulators held in multiple HPA lanes to form a scalar HPA result. The resulting scalar HPA number can well contain carry bits in the overlap region of each part, so the redundancy elimination routine can then be run on the scalar HPA number before converting it back to FP form.

[0245] Finally, the accumulated reproducible HPA result can be converted back to floating point format. The algorithm for converting an HPA part exactly to a normalised FP64 number (i.e. assuming p > 53) is as follows:

[0246] (i) perform CLZ (count leading zeros) to locate the position of the leading '1'

[0247] (ii) compute the exponent as significand + (63 - CLZ) + FP64 exponent offset

[0248] (iii) for all parts except the highest HPA part, set bit

[63] of FP64 to 0; set bits [62:52] of the FP64 result to the computed exponent; if the offset exponent > 0, logically left shift the HPA part by CLZ - 11 positions: otherwise set the FP64 result to zero.

[0249] (iv) For the highest HPA part only: if the part is negative, set bit

[63] of the FP64 result to 1 and negate the part to obtain a positive two's complement number; set bits [62:52] of the FP64 result to the computed exponent; if the offset exponent > 0, logically shift the HPA part left by CLZ - 11 positions: otherwise set the FP64 result to zero.

[0250] The conversion algorithm can be implemented in typically 15 SVE instructions per HPA lane.

[0251] It should be noted that steps (iii) and (iv) above can be combined to cover the case where the part that is not the highest significant can be negative, if required, as follows:

[0252] (iii) if the part is negative, set bit

[63] of the FP64 result to 1 and negate the part to obtain a positive two's complement number; set bits [62:52] of the FP64 result to the computed exponent; if the offset exponent > 0, logically shift the HPA part left by CLZ - 11 positions: otherwise set the FP64 result to zero.

[0253] When required, a single FP64 result can be produced that represents the final accumulated value as accurately as possible. This can be achieved, for example, by applying the algorithm suggested by Y. Hida, X. S. Li and D. H. Bailey in "Algorithms for Quad-Double Precision Floating Point Arithmetic", in Proceedings of the Fifteenth IEEE Symposium on Computer Arithmetic, Vail CO, June 2001, pages 155-162.

[0254] Proceeding from the bottom pair of lanes upwards, the Fast2Sum operation is applied successively to the next higher lane and to the higher sum obtained from the Fast2Sum. The process is then repeated from the top pair of values just obtained downwards and successively to the next lower value and to the lower sum obtained from the Fast2Sum. The top element of the resulting vector of FP64 numbers can then be guaranteed to be within 0.5ulp of the HPA number.

[0255] A multi-part HPA accumulator has a word length of l×p bits and occupies l SVE vector registers. The FCVTH{A} instruction, executed on a k×128-bit SVE vector unit, can convert and accumulate 2k FP64 numbers or 4k FP32 numbers into a portion of 2k HPA accumulators. The FCVTH{A} instruction is fully pipelined, allowing a block of n FP64 add-ons to accumulate into 2k p×l-bit HPA accumulators in n×(l / 2k)+1 loops. Typical values ​​for l and k are 2-4 (although k can be as high as 16), such that if l = k, n FP64 numbers (or 2n FP32 numbers) can be accumulated in k parallel accumulators in n / 2 loops. In contrast, on the ARM Cortex-A72, the same reproducible accumulation would require 3n loops because the sums must occur sequentially, and the associated fused multiply-accumulate (FMA) operation requires 3 loops between additions. Therefore, HPA typically provides 12x speedup for FP32 accumulation compared to conventional FP processing.

[0256] As mentioned above, HPA redundancy will need to be periodically eliminated or resolved. The method described above uses 3 × (1-1) instructions and will require periodic elimination or resolution. 64-p Each accumulation is performed once: for a typical value of p = 50, this represents a tiny processing overhead of <0.1%. Similarly, this is equivalent to ≈n / 4 loops for HPA accumulation of n numbers (where n ≈ 10). 3 Compared to (or higher), reducing the vector of the HPA accumulator to scalar form, resolving redundancy in scalar HPA, and converting scalar HPA back to FP64 format typically uses 1+3×(1-1)+15×1≈19×1-3=35-73 instructions for 1 representative value.

[0257] Figure 9 Another example of encoding for an anchor data element is shown, which includes type information specifying whether the anchor data element represents part of a two's complement number or a special value. Note that the type information in an anchor data element differs from that in other cases. Figure 7 The channel type information 196 in the metadata is shown. In this encoding, the most significant bit (bit 63 in this example) is used to indicate whether the element represents a standard HPA bit or a special value, which represents a portion of a two's complement number. When the most significant bit is 0, then the HPA element represents a standard HPA bit (which represents a two's complement number), where the bits in the overlapping portion have the same significant value as the least significant bit of the next most significant bit in the HPA value, similar to the example above.

[0258] However, when the most significant bit of an element is 1, the element represents a special value of the HPA selected from the group of: positive infinity, negative infinity, not-a-number (NaN), and a saturated value. When the most significant bit is 1, then the next two most significant bits (e.g. bits 61 and 62 as shown in Figure 9 the encoding of bits 63 to 61 for a standard HPA digit and the corresponding type of special value. Figure 10 The encoding of bits 63 to 61 for a standard HPA digit and the corresponding type of special value are shown.

[0259] Thus, when the most significant bit is 0, then the next two bits represent some of the overlapping bits of the HPA digit. Alternatively, if a non-redundant HPA variant is used that does not have overlapping bits, then the next two bits can represent non-overlapping bits of the HPA digit. Thus, bits that would otherwise be used to encode which particular type of special value is represented can be reused to represent a two's complement number, which helps to provide an efficient encoding.

[0260] When the most significant bit is 1 and the third most significant bit is 0, then the HPA element represents infinity. The second most significant bit represents the sign of the infinity. Thus, the encoding 110 of bits 63 to 61 of an element can represent a negative infinity, and the encoding 100 can represent a positive infinity. The encodings for positive and negative infinity will also be exchanged. When an HPA element is indicated as representing a positive or negative infinity, then this means that it was generated in a sequence of operations at least one of which involved a conversion of a floating point value to the HPA format, where the floating point value was a positive or negative infinity.

[0261] When the three most significant bits of an element indicate 101, then the element represents a not-a-number (NaN). This can arise in two ways. Either the element can be generated in a sequence of operations involving a conversion of a floating point value that is a NaN, or the element can depend on the addition of two HPA values, one of which is a positive infinity and the other of which is a negative infinity.

[0262] On the other hand, when the three most significant bits of an HPA element are encoded as 111, then this represents that the value is a saturated HPA value. A saturated HPA value does not have a similar value in the floating point domain. However, the positive or negative infinity indication that the HPA value was generated by a conversion of a floating point value that was a positive or negative infinity, where the floating point value would have been derived from a calculation that generated a magnitude larger than can be represented in floating point format, the saturated HPA type can indicate that while any of the floating point numbers input into the sequence of HPA operations can not have been a NaN or an infinity, a saturation has arisen as a result of the HPA operations themselves, e.g. because the anchor metadata that sets the range of valid values that can be represented by the HPA values has been such that the input floating point values and / or the results of processing those values have generated numbers outside the range defined by the metadata.

[0263] For example, a saturation type can be generated when an HPA operation acting on the most significant HPA element of an HPA value (e.g. the element shown as the top element in the channel information 196 shown) causes an overflow from the most significant overlap bit. Alternatively, if the most significant HPA element and the overlap bits of an HPA value are not considered to be part of the two's complement number represented by the HPA value, then a saturation type can be produced if the most significant element of the HPA value overflows from the most significant non-overlap bit to the least significant overlap bit. In the case where the overlap bits of the top element of an HPA value are considered to be part of the overall two's complement number represented by the HPA value, it can be particularly useful to encode the saturation type as 111 in bits 63 to 61, since this would mean that, by definition, if there is an overflow from the top overlap bit, then the top two overlap bits would already both equal 1 and the overflow would cause the most significant bit of the element to switch from 0 to 1, so that the overflow itself can cause the corresponding element to be set with type information equal to 111 in the first three bits. This can simplify the logic for setting the type information, since it can not need special circuitry to detect the overflow and set the type information accordingly. On the other hand, if the overlap bits are not considered to be part of the two's complement number represented by the HPA value, then some additional logic can detect an overflow from the top non-overlap bit into the overlap region and set the first three bits of the type information accordingly. Figure 7

[0264] Optionally, a saturation type can also be used when an underflow occurs in an HPA operation. For example, if a floating point value to be converted into HPA format represents a number that would require some bits less significant than the least significant bit that can be represented using the HPA format for its exact representation in HPA format (as defined by the anchor metadata), then this can be detected as an underflow and can indicate a saturation data type. Alternatively, a type encoding can be used that distinguishes between overflows and underflows. However, in practice, it can be more important to signal an overflow than an underflow, since an underflow can simply result in a loss of precision, whereas an overflow can result in an incorrect processing result being returned. Thus, in some cases, it can be chosen to signal an underflow without using a data type indicated by the type information.

[0265] Thus, generally, an indication of a saturation type for an HPA value is supported by providing type information, which can allow program code to determine, after a sequence of HPA operations, whether any special values resulting from those operations were caused by an input floating point number that was a special number or by an overflow occurring due to the HPA processing. This can be useful, since in the second case the program code can be able to adjust the anchor metadata and then repeat the sequence of operations in order to maintain a valid result, whereas repeating the HPA processing with different anchor metadata will still not produce a non-special result if the special value came from a special number in the original floating point value.​

[0266] While Figure 10 One particular encoding is shown that can be used to provide type information for providing an efficient encoding scheme, but other encoding schemes can also be used.

[0267] Figure 9 Encoding is shown for a single HPA element. When an HPA value is formed by two or more HPA elements, the overall value can be considered special if any of those HPA elements has the top bit set to 1 to indicate a special value. In practice, since an HPA value can be scattered over multiple different vector registers as shown, each HPA processing instruction can only see one element at a time, and it can not be apparent when processing one of the HPA elements that one of the other HPA elements of the same vector value will detect a special value or overflow. While this can result in all elements of the HPA value that the input floating point number is converted to being set to indicate a special value if the input floating point value is infinite or not a number, in cases where saturation results from the HPA processing, the type of saturation can only be indicated in, for example, the most significant HPA element of the HPA value. Figure 5

[0268] When two HPA elements are added together, then the type information of the result element can be set according to the type information in the two elements that are added. Figure 11 A table is shown that shows the different data types that can occur according to the data types of the first and second operands. The columns on the left of the table show the different options for the data type in the first operand, and the rows along the top of the table show the different options for the data type in the second operand. The abbreviation Num represents a standard two's complement number, i.e. a data type where the most significant bit of an element is 0.

[0269] As Figure 11 shown, if both input operands that are added are standard two's complement numbers, then the result can be another standard two's complement number, or a saturated value in case there is an overflow from the most significant element of the HPA value. In case at least one of the two operands that are added is a special value, then the result will also be special. Thus, the most significant bit of an HPA element is sticky in the sense that once it is set to 1, all subsequent HPA elements of that element will generate a most significant bit equal to 1, so that the occurrence of a special value can be detected at the end of a sequence of operations.

[0270] As Figure 11 ​As shown, if either of the operands being added is a NaN, then the result will also be a NaN. If one of the operands being added is positive infinity and the other is negative infinity, then a NaN can also result. If one of the operands being added is positive infinity and the other is any type except negative infinity or NaN, then the result will be positive infinity. Similarly, if one of the operands is negative infinity and the other is any type except positive infinity or NaN, then the result will be negative infinity. Finally, if at least one of the operands is a saturated value, then the result will also be saturated if the other operand is a standard two's complement number or a saturated value.

[0271] In some cases, an exception can be triggered in response to an HPA addition that produces certain results. In the case where both operands of the addition are standard two's complement numbers but an overflow occurs and thus the result is saturated, then an overflow exception can be signaled. This exception should not occur for HPA elements other than the most significant element of the HPA value, because the program code should trigger an overlap propagation operation after a certain number of HPA additions have been performed, where the number is chosen such that the number of HPA additions cannot result in an overflow of the top overlap bits. However, for the most significant element, an overflow can occur if the anchor metadata has not been set correctly.

[0272] If different signed floating point infinities are added such that the result is set to a NaN, then an invalid operand exception can be raised.

[0273] Depending on the type of special value represented, other types of exceptions can be raised when converting from a floating point to an HPA or from an HPA to a floating point.

[0274] Figure 12 An example of circuit logic 300 for performing HPA additions is shown when considering special values encoded as in the example of Figure 9 to Figure 11 The circuit logic 300 includes a 63-bit adder 302 and a special value detection circuit 304. The adder 302 receives the lower 63 bits of each of the two HPA elements being added (not including the most significant bit that indicates whether the value is a special value), and adds the two sets of 63 bits together to produce a 63-bit sum (which is prefixed with a single bit value of 0 to produce a 64-bit result that is encoded as a non-special value), and provides the sum to a multiplexer 308.

[0275] In parallel with the addition by the adder, the special value detection circuit 304 receives the type information for each of the HPA elements being added (the first three bits). The special value detection circuit 304 checks the type information to determine which special values, if any, are represented and based on the type of special value represented, determines the appropriate exception to raise. For example, if the special value is a NaN, then an invalid operand exception is raised. If the special value is an infinity, then an overflow exception is raised. If the special value is a denormal, then an underflow exception is raised. If the special value is a standard two's complement number, then no exception is raised. Figure 11The logic 304 determines whether the result should represent a special value, and if so, which type of special value should be encoded, from the combinations shown in the table. When the result is a special value, then the special value detection circuit generates a 64-bit result 306 in which the first three bits are encoded according to the type of special value indicated in the table, which is selected based on the types of the two operands. In the case of a result that is special, the bit values in the lowest 61 bits can take any value, since once a special value occurs, the HPA value can no longer represent a valid two's complement number in the range, so it does not matter what information is specified in the lowest 61 bits. Figure 11

[0276] The multiplexer 308 selects between the 64-bit value provided by the special value detection circuit 304 and the 64-bit provided by the adder (including the top bits which are equal to 0) to indicate a non-special number. The multiplexer makes this selection based on the signal 310 provided by the special value detection circuit indicating whether the result should be a special value. In practice, this signal 310 can be only the upper bits of the 64-bit value 306, as Figure 12 indicated by the dashed line.

[0277] Thus, since the special value detection circuit 304 functions in parallel with the adder itself, the logic has high speed since it has the same logic depth as a standard saturating integer adder.

[0278] When the result is a special value, the special value detection circuit 304 can also set various floating point status flags according to the result, which can indicate properties of the floating point operation. This allows the HPA to reflect the processing that would be expected in the case that the processing has been performed using floating point arithmetic entirely. For example, these floating point flags can indicate whether a underflow exception or an overflow exception should be signaled or whether there was an invalid operation.

[0279] Figure 12 A single add lane is shown, but it will be appreciated that this circuit logic can be provided for each vector lane when separate additions are performed on respective pairs of HPA elements in corresponding lanes of a pair of vector registers (similar to the vectorization of the conversion operations shown in Figure 6 .

[0280] Special HPA values can also be considered when performing an overlap propagation operation. Figure 13 ​An overlap propagation instruction is shown that is a vector instruction that specifies three vector registers as inputs. Vector register Zdu provides HPA elements that represent the higher HPA element of a pair of adjacent HPA elements that are expected to represent the same HPA value, and also acts as a destination register that will store updated values for that higher HPA element of the pair. Source vector register Zl is a vector register in which each lane provides the lower element of the pair that corresponds to the higher element in the corresponding vector lane of Zdu. Vector register Zm provides anchor metadata for each of the vector processing lanes. In general, the anchor metadata in register Zm should be the anchor metadata associated with the lower HPA element of each pair specified in input register Zl, but if the number of overlapping bits in the higher and lower HPA elements of each pair is the same, then the register providing anchor metadata for the higher element in each pair can also be used. Thus, each vector lane of the 3 registers is related to a different HPA value and specifies a pair of adjacent elements Li, Ui and corresponding metadata Mi for that HPA value (in this example, there are 4 vector lanes, so i = 0...3, but other examples can have a different number of lanes).

[0281] Thus, within each vector processing lane, an overlap propagation operation 350 is performed based on the lower element Li and the higher element Ui of the corresponding pair of adjacent elements for a given HPA value and based on the metadata Mi associated with that pair of adjacent elements to generate an updated value Ui' that is stored to the corresponding element position within the destination register Zdu.

[0282] The operations of the overlap propagation function 350 performed within each lane are shown at the bottom of Figure 13 As shown, the operations include shifting the lower element Li of the corresponding pair of elements right by an alignment shift amount that depends on the metadata in the corresponding lane Mi of the metadata register Zm. The size of the alignment shift in the vector can correspond to the number of non-overlapping bits W within the lower element Li of each pair. Since different vector lanes correspond to completely different HPA values, different vector lanes can have different alignment shift sizes if the metadata for those different lanes specifies different numbers of overlapping bits. The alignment shift amount can be determined in different ways, depending on how the number of overlapping bits is encoded. If the number of non-overlapping bits is specified directly by the metadata, then that number can simply be used directly as the alignment shift amount. However, if the metadata specifies a number of overlapping bits V, then the alignment shift size can be derived from the total number of bits N in the data element and the number of overlapping bits V, such that when a 1-bit is used as an indicator of whether the value is special, the alignment shift size SH is equal to N-V-1.

[0283] Thus, after the lower element in the pair is right shifted by W bits, the shifted value is added to the corresponding higher element Ui in the pair to generate an updated value Ui' which is stored into the corresponding lane of the destination register. Thus, in the case where neither the higher element nor the lower element is a special number, the updated value of the higher element Ui' will be set such that the non-overlapping bits are equal to the sum of the overlapping bits of the lower element and the non-overlapping bits of the higher element in the pair.

[0284] However, if the top bit of the lower element Li is 1 or the top bit of the higher element Ui is 1 indicates that either of these elements is a special HPA value, then the higher element can remain unchanged without performing the shift and the addition of the overlapping and non-overlapping bits. This can reduce the amount of logic required. Thus, the special value and the element adjacent to the special value can remain unchanged during the carry elimination, such that the fact that a special value has occurred can be detected at the end of the sequence of HPA operations. If any one or more elements of the HPA number is a special value, then the entire HPA number can be considered to be numerically invalid.

[0285] Alternatively, another method for handling the occurrence of a special value can be that if the lower element Li in the pair is special, then the type information from the lower element Li can be copied to the type information of the updated higher element Ui' written to the destination register Zdu. Then, with this method, the signaling of a special value can be propagated gradually to the top lane when a series of carry elimination is performed by executing the carry propagation instruction on consecutive pairs of adjacent elements of the HPA value, which can make it simpler to detect whether any special value has been generated when reaching the end of the series of HPA operations, as this can allow the presence of a special value to be detected simply by checking the type information of the top lane without the need to check the type information in all elements of the HPA value.

[0286] On the other hand, if both the lower element and the higher element in the pair are non-special, but the addition of the non-overlapping bits in the higher element and the overlapping bits in the lower element results in an overflow, then bits 63 to 61 of the updated higher element Ui' can be set to 111 to indicate a saturated value, similar to the case of addition as described above.

[0287] Figure 13 The operations shown at the bottom of Figure 6 can be performed independently for each vector processing lane, such that the overlap propagation in one lane can generate a special value while the other lane does not generate a special value.

[0288] Providing a dedicated overlap propagation instruction as shown in Figure 6 can greatly reduce the code size required to perform overlap propagation compared to if separate instructions are required for performing the aligned shift, the addition and the setting of the pair type information. Figure 13 Providing a dedicated overlap propagation instruction as shown in Figure 6 can greatly reduce the code size required to perform overlap propagation compared to if separate instructions are required for performing the aligned shift, the addition and the setting of the pair type information.

[0289] Figure 14 illustrates a corresponding overlap clear instruction for removing overlap bits after the overlap propagation operation as Figure 13 illustrated. That is, once the overlap bits of the lower element of the pair have been added to the higher element, the overlap bits in the lower element can be cleared to 0.

[0290] As with the overlap propagate instruction, the overlap clear instruction specifies three vector registers, however, this time the destination register Zdl provides the lower HPA element of a pair of adjacent HPA elements of HPA values that will be updated as a result of the overlap clear instruction. The other two source registers Zm, Zu represent the metadata and the higher element of the pair, respectively. Again, these registers are vector registers, so the processing of multiple independent lanes is performed on each set of correspondingly positioned vector elements in the respective registers. At this time, the operation performed on each set of corresponding elements is the overlap clear operation 360, which takes the values of the pair of HPA elements Li and Ui and the corresponding metadata Mi as inputs, and generates an updated value Li' of the corresponding lane to be written back to the destination register Zdl.

[0291] The operation performed by each of the functions in the overlap clear function 360 is illustrated at the bottom of Figure 14 . As illustrated, the overlap clear operation simply clears the overlap bits of the lower element Li to 0, where the number of bits set to 0 will depend on the number of overlap bits 194 specified in the corresponding element Mi of the metadata Zm. The non-overlap bits of the lower element remain unchanged. In the case where neither the lower element nor the higher element represents a special value, the clearing of the overlap bits in the lower element is independent of the higher element Zu. Figure 14 If the top bit of the lower element Li is set to 1 to indicate a special value, the lower element can remain unchanged so that the updated value Li' is equal to the input value Li. Optionally, the lower element can also remain unchanged if the higher element Ui is special, although this is not required. If in one particular implementation the overlap clear is to be performed regardless of whether the higher element is indicated as a special value, then the instruction does not need to specify a register Zu corresponding to the higher element Ui at all. However, it can be useful for the operation to depend on whether the higher element is special in order to avoid performing unnecessary writes to the destination register. Unlike the overlap propagate instruction of

[0292] , for the overlap clear instruction of Figure 13 , it is less likely that one would want to propagate a special value from the lower element to the higher element in a given pair of adjacent elements within an HPA value, as this would require a second destination register for the instruction, and many microarchitectures can not have enough write ports to do so. Figure 14 Thus, in use, it is expected that

[0293] Figure 14 ​The overlap clear instruction can be followed by an overlap propagate instruction as shown in Figure 13 It can be useful to split this operation into two separate instructions, as it can be simpler to implement in micro-architecture to ensure that each instruction only needs to specify one destination register, as described above.

[0294] However, in an architecture that allows an instruction to update two different destination registers in response to the same instruction, a combined instruction would likely perform both functions of Figure 13 and Figure 14 That is, in the case of non-special inputs, the instruction can trigger the addition of the overlap bits of the lower element into the non-overlap bits of the upper element, and also clear the overlap bits of the lower element to 0. This instruction can handle special values in the same way as described above for Figure 13 and Figure 14 , where if either value at the input registers is special, the output value can remain unchanged, or the type information of the lower element is propagated to the upper element.

[0295] While Figure 13 and Figure 14 show an example where the first and second anchor data elements on which the overlap propagate and overlap clear instructions act are a pair of adjacent elements Li, Ui of the same HPA value, this is not required. Another use case can be where the first anchor data element (Li) specified by the overlap propagate / clear instruction is the most significant element of a given HPA value, and the second anchor data element (Ui) is a “null” HPA element that is only filled with sign bits. This can be useful if one wants to add an HPA value that includes the first anchor data value to another HPA value that includes bits with a greater significance value than the first anchor data value, in which case one can need to add the carry bits from the first anchor data value to the lanes within the second HPA value that have a greater significance value, which can be made simpler by first stripping the overlap bits from the top element of the first HPA value and adding them to the non-overlap bits of another “null” HPA element that can be given lane significance values corresponding to the lane significance values of the relevant HPA elements of the second HPA value. It should be understood that other use cases are possible for the instructions shown in Figure 13 and Figure 14 .

[0296] Figure 15Embodiments of simulators that can be used are shown. While the previously described embodiments implement the application in terms of apparatus and methods for operating specific processing hardware that support the technology involved, it is also possible to provide an instruction execution environment in accordance with the embodiments described herein that is implemented through the use of a computer program. Such computer programs are often referred to as simulators, in part because such computer programs provide a software-based implementation of a hardware architecture. Categories of simulator computer programs include emulators, virtual machines, models, and binary translators, including dynamic binary translators. In general, a simulator implementation can run on a host processor 430 that supports the simulator program 410, which optionally runs a host operating system 420. In some arrangements, there can be multiple simulation layers between the hardware and the provided instruction execution environment and / or multiple different instruction execution environments provided on the same host processor. Historically, powerful processors have been required to provide a simulator implementation that executes at a reasonable speed, but such an approach can be reasonable in certain situations, such as when it is desirable to run code native to another processor for compatibility or re-use reasons. For example, a simulator implementation can provide an instruction execution environment with additional functionality that is not supported by the host processor hardware, or provide an instruction execution environment that is normally associated with a different hardware architecture. An overview of simulation is given in "Some Efficient Architecture Simulation Techniques", Robert Bedichek, Winter 1990 USENIX Conference, pp. 53-63.

[0297] To the extent that embodiments have been previously described in terms of specific hardware configurations or features, in a simulated embodiment, equivalent functionality can be provided by suitable software configurations or features. For example, a particular circuit can be implemented as computer program logic in a simulated embodiment. Similarly, memory hardware such as registers or cache memory can be implemented as software data structures in a simulated embodiment. To the extent that one or more of the hardware elements referenced in the previously described embodiments exist in an arrangement on host hardware (e.g., host processor 430), some simulated embodiments can utilize the host hardware, as appropriate.

[0298] The emulator program 410 can be stored on a computer readable storage medium, which can be a non-transitory medium, and provides a program interface (instruction execution environment) to the target code 400, which can include an application, operating system, and hypervisor, that is identical to the application program interface of the hardware architecture that the emulator program 410 is modeling. Thus, program instructions of the target code 400, including instructions that support processing of HPA values as described above, can be executed from within the instruction execution environment using the emulator program 410 so that a host computer 430 that does not actually have the hardware features of the apparatus 2 described above can emulate those features. The emulator program 410 can include instruction decoding program logic 412 for decoding instructions of the target code 400 and mapping them to native instructions supported by the host hardware 430. The instruction decoding program logic 412 includes anchored data processing program logic 414 that maps HPA processing instructions to a local instruction set for performing HPA (anchored data processing) operations such as FP conversion, addition, or overlap propagation / clear operations as described above.

[0299] In this application, the word "configured" is used to mean that an element of the apparatus has the capability to carry out a defined operation. In this context, a "configuration" means an arrangement or manner of interconnection of hardware or software. For example, the apparatus can have dedicated hardware which provides the defined operation, or a processor or other processing device can be programmed to perform the function. "Configured" does not imply that the apparatus element needs to be changed in any way in order to provide the defined operation.

[0300] While exemplary embodiments of the present application have been described in detail hereinabove, it is to be understood that the application is not limited to the precise embodiments described, and as such, various modifications and changes can be made by those skilled in the art without departing from the scope and spirit of the application as defined by the appended claims.

Claims

1. An apparatus for data processing, the apparatus comprising: processing circuitry to perform data processing; and an instruction decoder to control the processing circuitry to perform an anchored data processing operation to generate an anchored data element; wherein: the anchored data element has an encoding comprising type information indicating whether the anchored data element represents: a portion of bits of a two’s complement number, the portion of bits corresponding to a given range of significant values that can be represented using the anchored data element, wherein the given range of significant values is defined by anchor metadata; or a special value other than the portion of bits of a two’s complement number; the type information specifies whether the special value is a positive infinity, a negative infinity, a not-a-number, or a saturated type of anchored data element; the processing circuitry is configured to set the type information to indicate the saturated type of anchored data element when the anchored data element depends on a previous anchored data processing operation that resulted in an overflow on a corresponding anchored data element due to an improper setting of the range of significant values indicated by the anchor metadata; and the processing circuitry is configured to store the type information in the same register as the anchored data element, the type information comprising an indication of whether the anchored data element represents the saturated type of anchored data element.

2. The apparatus of claim 1, wherein the anchored data processing operation comprises a float-to-anchor conversion operation to convert a floating-point value to the anchored data element.

3. The apparatus of claim 2, wherein when the floating-point value represents a special number, the processing circuitry is configured to generate the anchored data element with the type information indicating that the anchored data element represents the special value.

4. The apparatus of claim 3, wherein the type information distinguishes whether the special number represented by the floating-point value is a positive infinity, a negative infinity, or a not-a-number.

5. The apparatus of claim 2, wherein in the float-to-anchor conversion operation, the processing circuitry is configured to generate the anchored data element based on the anchor metadata.

6. The apparatus of claim 1, wherein in a float-to-anchor conversion operation to convert a floating-point value to the anchored data element, the processing circuitry is configured to set the type information of the anchored data element to indicate the saturated type when one of: the anchored data element would represent a most significant element of an anchored data value comprising one or more anchored data values, and representing the floating-point value as a two’s complement number would require at least one bit of higher significance than the given range of significant values that can be represented using the anchored data element; or the anchored data element would represent a least significant element of an anchored data value comprising one or more anchored data values, and representing the floating-point value as a two’s complement number would require at least one bit of lower significance than the given range of significant values that can be represented using the anchored data element. ​ 7. The apparatus of claim 1, wherein for an anchored data element designated as the saturated type, the encoding of the type information fails to distinguish whether the anchored data element represents a positive value or a negative value.

8. The apparatus of claim 1, wherein the processing circuitry comprises addition circuitry to perform addition of two anchored data elements to generate a result anchored data element; wherein: when the addition of the two anchored data elements results in an overflow when generating the result anchored data element, the addition circuitry is configured to generate the result anchored data element with the type information designating the result anchored data element as the saturated type, the result anchored data element representing a most significant element of an anchored data value comprising one or more anchored data elements each indicating a respective portion of bits of a two’s complement number represented by the anchored data value.

9. The apparatus of claim 1, wherein the anchored data elements have an encoding in which: when a predetermined bit of the anchored data element has a first value, the anchored data element represents the portion of bits of a two’s complement number; and when the predetermined bit of the anchored data element has a second value, the anchored data element represents the special value.

10. The apparatus of claim 9, wherein when the predetermined bit of the anchored data element has the second value, at least one additional bit of the anchored data element represents a type of special value represented by the anchored data element.

11. The apparatus of claim 10, wherein when the predetermined bit of the anchored data element has the first value, the at least one additional bit of the anchored data element represents a portion of the portion of the two’s complement number or represents at least one carry-in bit to accommodate a carry from a portion of the anchored data element representing the portion of the two’s complement number.

12. The apparatus of claim 9, wherein the predetermined bit is a most significant bit of the anchored data element.

13. The apparatus of claim 1, wherein in a given anchored data processing operation, when an input anchored data element has the type information designating the input anchored data element as a special value, the processing circuitry is configured to generate a corresponding result anchored data element with the type information designating the result anchored data element as a special value.

14. The apparatus of claim 1, wherein the processing circuitry comprises addition circuitry to perform addition of two anchored data elements to generate a result anchored data element, and when two type information of the two anchored data elements indicate that one of the two anchored data elements represents positive infinity and the other of the two anchored data elements represents negative infinity, the addition circuitry is configured to generate the result anchored data element with type information designating the result anchored data element as representing a non-number. ​ ​ ​ ​ 15. The apparatus of claim 1, wherein the anchor data element is an N-bit value, the N-bit value including V overlapping bits and W non-overlapping bits; and in a floating-to-anchor conversion operation to convert a floating-point value into the anchor data element, when the floating-point value represents a number other than a special number and the number represented by the floating-point value is within an allowed range of numbers, the processing circuitry is configured to set the W non-overlapping bits of the anchor data element to represent a portion of bits corresponding to the two’s complement number of the floating-point value, and to set the V overlapping bits of the anchor data element to be a sign extension of the W non-overlapping bits.

16. The apparatus of claim 15, wherein N - V - W > 0.

17. The apparatus of claim 15, wherein the processing circuitry is responsive to an overlap propagation instruction to align the V overlapping bits of a first anchor data element with W non-overlapping bits of a second anchor data element, and to add the aligned overlapping and non-overlapping bits to generate an updated value of the second anchor data element.

18. The apparatus of claim 17, wherein responsive to the overlap propagation instruction, when one of the first anchor data element and the second anchor data element has type information specifying the special value, the processing circuitry is configured to perform one of: preserving a previous value of the second anchor data element; or when the type information of the first anchor data element indicates a special value, propagating the type information of the first anchor data element to the type information of the second anchor data element.

19. The apparatus of any one of claims 17 and 18, wherein when the adding of the aligned overlapping and non-overlapping bits results in an overflow of the second anchor data element, the processing circuitry is configured to set the type information of the second anchor data element to indicate a saturated type value.

20. The apparatus of claim 15, wherein the processing circuitry is responsive to an overlap clear instruction to clear the overlapping bits of a target anchor data element to zero.

21. The apparatus of claim 20, wherein responsive to the overlap clear instruction, when the target anchor data element has type information specifying the special value, the processing circuitry is configured to preserve a previous value of the target anchor data element.

22. A computer program product comprising a computer program for controlling a host data processing apparatus to provide an instruction execution environment for executing instructions; the computer program comprising: instruction decode program logic to decode program instructions of object code to control the host data processing apparatus to perform data processing; the instruction decode program logic including anchor data processing program logic to control the host data processing apparatus to perform anchor data processing operations to generate anchor data elements, wherein: the type information specifies whether the special value is a positive infinity, a negative infinity, a non-number, or a saturated type of anchored data element; a portion of bits of a two's complement number, the portion of bits corresponding to a given range of valid values that can be represented using the anchored data element, wherein the given range of valid values is defined by anchor metadata; or a special value other than the portion of bits of the two's complement number; the type information specifies whether the special value is a positive infinity, a negative infinity, a non-number, or a saturated type of anchored data element; the instruction decode program logic is configured to control the host data processing apparatus to set the type information to indicate the saturated type of anchored data element when the anchored data element depends on a previous anchored data processing operation that overflowed a corresponding anchored data element due to an improper setting of the range of valid values indicated by the anchor metadata; and the type information is stored in the same register as the anchored data element, the type information including an indication of whether the anchored data element represents the saturated type of anchored data element.

23. A data processing method, the data processing method comprising: decoding one or more instructions; and in response to the decoded instructions, controlling processing circuitry to perform an anchored data processing operation to generate an anchored data element, wherein: the anchored data element has an encoding that includes type information indicating whether the anchored data element represents: a portion of bits of a two's complement number, the portion of bits corresponding to a given range of valid values that can be represented using the anchored data element, wherein the given range of valid values is defined by anchor metadata; or a special value other than the portion of bits of the two's complement number; the type information specifies whether the special value is a positive infinity, a negative infinity, a non-number, or a saturated type of anchored data element; the type information is set to indicate the saturated type of anchored data element when the anchored data element depends on a previous anchored data processing operation that overflowed a corresponding anchored data element due to an improper setting of the range of valid values indicated by the anchor metadata; and the type information is stored in the same register as the anchored data element, the type information including an indication of whether the anchored data element represents the saturated type of anchored data element.

24. An apparatus for data processing, the apparatus comprising: processing circuitry to perform data processing; and an instruction decoder to control the processing circuitry to perform an anchored data processing operation to generate an anchored data element; wherein: the anchored data element has an encoding that includes type information indicating whether the anchored data element represents: a portion of bits of a two's complement number, the portion of bits corresponding to a given range of valid values that can be represented using the anchored data element; or a special value other than the portion of bits of the two's complement number; and the anchored data element has an encoding, wherein: when a predetermined bit of the anchor data element has a first value, the anchor data element represents the portion of bits of the two's complement number; and when the predetermined bit of the anchor data element has a second value, the anchor data element represents the special value.

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