Dram test method, apparatus, computer readable storage medium, and electronic device

Abstract

The application discloses a DRAM test method, device, computer readable storage medium and electronic equipment, two rounds of tests are performed on a DRAM to be tested, the test comprises: writing preset test data into the DRAM to be tested until all storage units of the DRAM to be tested are written with data; based on a preset interval, all storage units of the DRAM to be tested are traversed through a snake path in a preset operation unit until all storage units of the DRAM to be tested are traversed; for a target preset operation unit traversed, data read-write operations are performed on the target preset operation unit based on the preset test data, the read data is compared with the corresponding written data, and a final test result is obtained through comparison results of the two rounds of tests, snake path access is realized, a previous test blind area is covered, and chip defects that are difficult to be found in the prior art are detected, fault coverage is improved, the reliability of test results is enhanced, and therefore product benignity is improved.

Description

Technical Field

[0001] This invention relates to the field of DRAM chip testing, and more particularly to a DRAM testing method, apparatus, computer-readable storage medium, and electronic device. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is an indispensable component of modern computer systems. Platforms may include Double Data Rate (DDR) modules for personal computers or servers, as well as Low Power Double Data Rate (LPDDR) chips for embedded ARM architectures.

[0003] The basic storage unit of LPDDR is a cell. Computers and embedded systems store and read data by writing high or low voltage levels into the cells. Cells are arranged in rows and columns, and the entire column formed is called a bank. Each LPDDR chip has multiple banks.

[0004] Furthermore, current DRAM uses burst read / write for high access speeds. This means read / write operations are performed in units of burst length (BL) within a memory array, reading or writing multiple bits (e.g., 8-bit, 16-bit, or 32-bit) of column addresses at a time, accessing data consisting of 0s and 1s within each burst length. For example, if the target address is row 0 and the burst length is 8 bits, then 1 bit of data is written to each bit in the space from row 0, column 0 to row 0, column 7, for a total of 8 bits. The second burst length is from row 0, column 8 to column 15, and so on. When all the memory locations in a row are written, the memory controller (MC) locates the address of the next row and continues the same operation.

[0005] In current DRAM chip manufacturing process failures, besides single-cell memory failures, failures caused by the interaction between multiple cells also account for a high proportion and are more difficult to detect. Typical multi-cell failures include bridging faults (BF) and coupling faults (CF). Traditional detection methods for these two faults fall into two categories: one is to perform ascending and descending read / write operations on memory cells in the address space to check for data errors. However, this simple ascending and descending read / write operation is too simplistic and therefore provides low fault coverage; the other method is to increase the order and frequency of read / write operations to improve algorithm coverage, but this significantly increases the algorithm's time complexity and thus testing time. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a DRAM testing method, apparatus, computer-readable storage medium and electronic device that can improve the fault coverage when testing DRAM.

[0007] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:

[0008] A DRAM testing method includes the following steps:

[0009] The DRAM to be tested was subjected to two rounds of testing, and the first comparison result and the second comparison result were obtained respectively.

[0010] The tests include:

[0011] Preset test data is written to the DRAM to be tested until all memory cells of the DRAM to be tested have been written with data;

[0012] Based on a preset interval, the DRAM to be tested is traversed in a serpentine path in units of preset operation units until all memory cells of the DRAM to be tested have been traversed.

[0013] For each target preset operation unit traversed, data read and write operations are performed on the target preset operation unit based on the preset test data, and the read data is compared with the corresponding written data.

[0014] The preset test data for the first round of testing is the inverse of the preset test data for the second round of testing;

[0015] The test results of the DRAM to be tested are obtained based on the first comparison result and the second comparison result.

[0016] To solve the above-mentioned technical problems, another technical solution adopted by the present invention is as follows:

[0017] A DRAM testing apparatus, comprising:

[0018] The data read / write module is used to perform two rounds of testing on the DRAM under test, and obtain the first comparison result and the second comparison result respectively.

[0019] The tests include:

[0020] Preset test data is written to the DRAM to be tested until all memory cells of the DRAM to be tested have been written with data;

[0021] Based on a preset interval, the DRAM to be tested is traversed in a serpentine path in units of preset operation units until all memory cells of the DRAM to be tested have been traversed.

[0022] For each target preset operation unit traversed, data read and write operations are performed on the target preset operation unit based on the preset test data, and the read data is compared with the corresponding written data.

[0023] The preset test data for the first round of testing is the inverse of the preset test data for the second round of testing;

[0024] The testing module is used to obtain the test results of the DRAM to be tested based on the first comparison result and the second comparison result.

[0025] To solve the above-mentioned technical problems, another technical solution adopted by the present invention is as follows:

[0026] A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the DRAM testing method described above.

[0027] To solve the above-mentioned technical problems, another technical solution adopted by the present invention is as follows:

[0028] An electronic device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the DRAM testing method described above.

[0029] The beneficial effects of this invention are as follows:

[0030] By conducting two rounds of testing on the DRAM under test and comparing the results of the two rounds, the final test result is obtained. Since the proportion of multi-memory cell failures is very high, simple ascending and descending access cannot trigger multi-memory cell failures. Based on a preset interval, the DRAM under test is traversed through a serpentine path in units of preset operation units. For the target preset operation units traversed, data read and write operations are performed on them based on preset test data. This serpentine path access can reduce the time complexity of the algorithm, cover the previous test blind spots, and detect chip defects that are difficult to detect in existing technologies. This triggers multi-memory cell failures such as bridging failures and coupling failures, improves the fault coverage, enhances the reliability of test results, and thus improves product quality. Attached Figure Description

[0031] Figure 1 This is a flowchart illustrating the steps of a DRAM testing method according to an embodiment of the present invention;

[0032] Figure 2 This is a schematic diagram of the structure of a DRAM testing device according to an embodiment of the present invention;

[0033] Figure 3 This is a schematic diagram of the structure of an electronic device according to an embodiment of the present invention;

[0034] Figure 4 This is a flowchart of the DRAM testing method according to an embodiment of the present invention;

[0035] Figure 5 This is a schematic diagram of preset test data and the inverse of preset test data in the DRAM testing method of this embodiment of the invention;

[0036] Figure 6 This is a schematic diagram of the first traversal of the first round of testing in the DRAM testing method of this embodiment of the invention;

[0037] Figure 7 This is a schematic diagram of the second traversal of the first round of testing in the DRAM testing method of this embodiment of the invention;

[0038] Figure 8 (a) is a schematic diagram of background data for the first round of testing in the DRAM testing method of this embodiment of the invention;

[0039] Figure 8 (b) is a schematic diagram of the background data after the first traversal of the first round of testing in the DRAM testing method of the present invention;

[0040] Figure 8 (c) is a schematic diagram of the background data after the second traversal of the first round of testing in the DRAM testing method of the present invention;

[0041] Figure 8 (d) is a schematic diagram of the background data after the first traversal of the second round of testing in the DRAM testing method of the present invention;

[0042] Figure 8 (e) is a schematic diagram of the background data after the second traversal of the second round of testing in the DRAM testing method of the present invention. Detailed Implementation

[0043] To explain in detail the technical content, objectives, and effects of the present invention, the following description is provided in conjunction with the embodiments and accompanying drawings.

[0044] Please refer to Figure 1 This invention provides a DRAM testing method, including the following steps:

[0045] The DRAM to be tested was subjected to two rounds of testing, and the first comparison result and the second comparison result were obtained respectively.

[0046] The tests include:

[0047] Preset test data is written to the DRAM to be tested until all memory cells of the DRAM to be tested have been written with data;

[0048] Based on a preset interval, the DRAM to be tested is traversed in a serpentine path in units of preset operation units until all memory cells of the DRAM to be tested have been traversed.

[0049] For each target preset operation unit traversed, data read and write operations are performed on the target preset operation unit based on the preset test data, and the read data is compared with the corresponding written data.

[0050] The preset test data for the first round of testing is the inverse of the preset test data for the second round of testing;

[0051] The test results of the DRAM to be tested are obtained based on the first comparison result and the second comparison result.

[0052] As can be seen from the above description, the beneficial effects of the present invention are as follows: By performing two rounds of testing on the DRAM to be tested, and comparing the results of the two rounds of testing, the final test result is obtained. Since the proportion of multi-memory cell failures is very high, simple ascending and descending access cannot trigger multi-memory cell failures. Based on a preset interval, the DRAM to be tested is traversed through a serpentine path in units of preset operation units. For the target preset operation units traversed, data read and write operations are performed on them based on preset test data, realizing serpentine path access. This can reduce the time complexity of the algorithm, cover the previous test blind spots, and detect chip defects that are difficult to detect in existing technologies. This can trigger multi-memory cell failures such as bridging failures and coupling failures, improve the fault coverage, enhance the reliability of test results, and thus improve product quality.

[0053] Furthermore, writing preset test data to the DRAM under test until all memory cells of the DRAM under test have been written with data includes:

[0054] The preset test data is written starting from the low-order address of each preset read / write cell of the DRAM under test, in units of a preset burst length, until all memory cells of the DRAM under test have been written with data.

[0055] As described above, writing preset test data to the DRAM to be tested in burst length units can improve the data writing speed and has low time complexity, making it suitable for mass production testing.

[0056] Furthermore, the step of traversing the DRAM under test through a serpentine path at preset intervals and in units of preset operation units until all memory cells of the DRAM under test have been traversed includes:

[0057] Based on a preset interval, the DRAM under test is traversed alternately along a first preset direction and a second preset direction in units of preset operation units until all memory cells of the DRAM under test have been traversed.

[0058] Further, the step of traversing the DRAM under test alternately along a first preset direction and a second preset direction at preset intervals, in units of preset operation units, until all memory cells of the DRAM under test have been traversed includes:

[0059] Starting from a preset position of the DRAM to be tested, the DRAM to be tested is traversed alternately along the first preset direction and the second preset direction in units of preset operation units;

[0060] Starting from the adjacent position of the preset position, the storage units not visited in the first traversal are traversed alternately along the first preset direction and the second preset direction in units of preset operation units;

[0061] The interval between the preset operation unit in the first preset direction and the preset operation unit in the second preset direction is a preset interval.

[0062] As described above, starting from a preset position of the DRAM under test, the system performs a first traversal along the first and second preset directions, alternating between preset operation units. Then, it performs a second traversal along the first and second preset directions for memory units not reached in the first traversal. This simulates non-continuous access with a certain interval, realizing a serpentine path access to the DRAM under test. This can cover previous test blind spots and detect chip defects that are difficult to detect in the current technology, thereby activating multi-memory cell faults and improving fault coverage.

[0063] Furthermore, the step of performing data read / write operations on the target preset operation unit based on the preset test data, and comparing the read data with the corresponding written data, includes:

[0064] Read the data from the target preset operation unit and compare the read data with the corresponding written data;

[0065] Write the inverse of the preset test data to the target preset operation unit.

[0066] As described above, for the target preset operation unit that has been traversed, reading the data to be written first and then writing the inverse of the preset test data can activate a single storage unit, improve fault coverage, and ensure the reliability and accuracy of the test.

[0067] Furthermore, the second round of testing also includes the following steps:

[0068] Read the data from all preset operation units of the DRAM to be tested, and compare the read data with the corresponding written data.

[0069] As described above, reading the data from all preset operation units of the DRAM under test allows for a second check to determine whether the data in the memory cells after testing meets expectations, thus improving the accuracy of the test and enhancing the reliability of the test results.

[0070] Further, obtaining the test result of the DRAM to be tested based on the first comparison result and the second comparison result includes:

[0071] If both the first comparison result and the second comparison result are consistent, the test result is successful; otherwise, the test result is unsuccessful.

[0072] As can be seen from the above description, by obtaining the first comparison result and the second comparison result through two rounds of testing, it is possible to detect chip defects that are difficult to find, improve the fault coverage during testing, and ensure the reliability of testing.

[0073] Please refer to Figure 2 Another embodiment of the present invention provides a DRAM testing apparatus, comprising:

[0074] The data read / write module is used to perform two rounds of testing on the DRAM under test, and obtain the first comparison result and the second comparison result respectively.

[0075] The tests include:

[0076] Preset test data is written to the DRAM to be tested until all memory cells of the DRAM to be tested have been written with data;

[0077] Based on a preset interval, the DRAM to be tested is traversed in a serpentine path in units of preset operation units until all memory cells of the DRAM to be tested have been traversed.

[0078] For each target preset operation unit traversed, data read and write operations are performed on the target preset operation unit based on the preset test data, and the read data is compared with the corresponding written data.

[0079] The preset test data for the first round of testing is the inverse of the preset test data for the second round of testing;

[0080] The testing module is used to obtain the test results of the DRAM to be tested based on the first comparison result and the second comparison result.

[0081] Another embodiment of the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the various steps in the above-described DRAM testing method.

[0082] Please refer to Figure 3 Another embodiment of the present invention provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the various steps in the above-described DRAM testing method.

[0083] The DRAM testing method, apparatus, computer-readable storage medium, and electronic device described above are applicable to the testing of any type of DRAM, such as DDR and LPDDR generations of products. Specific embodiments are described below:

[0084] Example 1

[0085] Please refer to Figure 1 , 4 -8. A DRAM testing method according to this embodiment includes the following steps:

[0086] S1. Perform two rounds of testing on the DRAM to be tested, and obtain the first comparison result and the second comparison result respectively;

[0087] The tests include:

[0088] S11. Write preset test data to the DRAM to be tested until all memory cells of the DRAM to be tested have been written with data;

[0089] Specifically, the preset test data is written starting from the low address of each preset read / write cell of the DRAM under test, in units of a preset burst length, until all memory cells of the DRAM under test are written with data.

[0090] The preset read / write unit includes rows or columns, which can be flexibly set by testers according to actual needs. For example, it can be set as columns or rows, which is highly flexible.

[0091] The burst length (BL) is defined by the JEDEC standard, but it can also be set arbitrarily. This means that multiple bits (e.g., 8 bits or 16 bits) are used for reading and writing at the same time. For example, when writing data based on rows, if the address is row 0 and the burst length is 8 bits, the first 8 bits of the data to be written are written simultaneously starting at the position of row 0, column 0. Then, the second burst length is used to write bits 9-16 of the data to be written, and so on until the storage location of row 0 is completely written. Then, the address of the next row is repositioned and the operation of the previous row is continued until the data is written to the entire disk. Reading data is a similar operation.

[0092] In this embodiment, the preset read / write unit is a row;

[0093] For example, start writing preset test data from the first column of the first row. After writing the first row, start writing preset test data from the first column of the second row, and so on, until data is written to each row of the DRAM to be tested.

[0094] S12. Based on a preset interval, the DRAM to be tested is traversed in a serpentine path in units of preset operation units until all memory units of the DRAM to be tested have been traversed.

[0095] Specifically, based on a preset interval, the DRAM to be tested is traversed alternately along the first preset direction and the second preset direction in units of preset operation units until all memory cells of the DRAM to be tested have been traversed.

[0096] Wherein, the first preset direction is the diagonal direction from the upper right corner to the lower left corner or the diagonal direction from the lower left corner to the upper right corner, and the second preset direction is the diagonal direction from the lower left corner to the upper right corner or the diagonal direction from the upper right corner to the lower left corner; the lines containing the first preset direction and the second preset direction are parallel to each other.

[0097] The first and second preset directions of each traversal are different, but the preset directions of two different traversals can be the same or different. They can be flexibly set according to the actual needs. For example, the first preset direction of the first traversal is the diagonal direction from the upper right corner to the lower left corner, and the second preset direction is the diagonal direction from the lower left corner to the upper right corner. The first preset direction of the second traversal is the diagonal direction from the lower left corner to the upper right corner, and the second preset direction is the diagonal direction from the upper right corner to the lower left corner.

[0098] In this embodiment, the first preset direction for the two traversals is the diagonal direction from the upper right corner to the lower left corner, and the second preset direction is the diagonal direction from the lower left corner to the upper right corner.

[0099] For example, if the storage array has 4 rows and 4 columns, the preset operation units in the second row and fourth column, the third row and third column, and the fourth row and second column are traversed in the first preset direction, that is, in the order of the preset operation units in the second row and fourth column, the third row and third column, and the fourth row and second column. If the preset operation units in the second row and fourth column, the third row and third column, and the fourth row and second column are traversed in the second preset direction, that is, in the order of the preset operation units in the fourth row and second column, the third row and third column, and the second row and fourth column, then...

[0100] The interval between the preset operation unit in the first preset direction and the preset operation unit in the second preset direction is a preset interval;

[0101] In one optional implementation, the preset interval is one preset operation unit;

[0102] For example, the storage array has 4 rows and 4 columns. Assume that the preset operation units in the first preset direction are the preset operation units in the first row and third column, the preset operation units in the second row and second column, and the preset operation units in the third row and first column. Since each preset operation unit in the second preset direction is spaced 1 from each preset operation unit in the first preset direction, the preset operation units in the second preset direction are the preset operation units in the second row and fourth column, the preset operation units in the third row and third column, and the preset operation units in the fourth row and second column.

[0103] The step of traversing the DRAM under test along a first preset direction and a second preset direction alternately, based on a preset interval and in units of a preset operation unit, until all memory cells of the DRAM under test have been traversed, includes:

[0104] Starting from a preset position of the DRAM to be tested, the DRAM to be tested is traversed alternately along the first preset direction and the second preset direction in units of preset operation units;

[0105] Starting from the adjacent position of the preset position, the storage units not visited in the first traversal are traversed alternately along the first preset direction and the second preset direction in units of preset operation units;

[0106] For example, if the storage array has 5 rows and 5 columns, starting from the first column of the first row, first traverse along the first preset direction, that is, traverse the preset operation units of the first row and first column, then traverse along the second preset direction, that is, traverse the preset operation units of the first column of the third row, the second column of the second row, and the third column of the first row in sequence, then traverse along the first preset direction, that is, traverse the preset operation units of the fifth column of the first row, the fourth column of the second row, the third column of the third row, the second column of the fourth row, and the first column of the fifth row in sequence, then traverse along the second preset direction, that is, traverse the preset operation units of the third column of the fifth row, the fourth column of the fourth row, and the fifth column of the third row in sequence, and finally traverse along the first preset direction, that is, traverse the preset operation units of the fifth column of the fifth row, thus completing the first traversal;

[0107] The second traversal starts from the second column of the first row. First, it traverses along the first preset direction, that is, it traverses the preset operation units of the second column of the first row and the preset operation units of the first column of the second row in sequence. Then, it traverses along the second preset direction, that is, it traverses the preset operation units of the first column of the fourth row, the preset operation units of the second column of the third row, the preset operation units of the third column of the second row, and the preset operation units of the fourth column of the first row in sequence. Next, it traverses along the first preset direction, that is, it traverses the preset operation units of the fifth column of the second row, the preset operation units of the fourth column of the third row, the preset operation units of the third column of the fourth row, and the preset operation units of the second column of the fifth row in sequence. Then, it traverses along the second preset direction, that is, it traverses the preset operation units of the fourth column of the fifth row and the preset operation units of the fifth column of the fourth row in sequence. This completes the second traversal.

[0108] S13. For the target preset operation unit that has been traversed, perform data read and write operations on the target preset operation unit based on the preset test data, and compare the read data with the corresponding written data.

[0109] Specifically, the data of the target preset operation unit is read, and the read data is compared with the corresponding written data;

[0110] Write the inverse of the preset test data to the target preset operation unit;

[0111] After the first round of testing is completed, the second round of testing will be conducted. The preset test data for the first round of testing is the inverse of the preset test data for the second round of testing.

[0112] S2. Obtain the test results of the DRAM to be tested based on the first comparison result and the second comparison result;

[0113] If both the first comparison result and the second comparison result are consistent, the test result is successful; otherwise, the test result is unsuccessful.

[0114] The following is a specific implementation method to illustrate how to test DRAM:

[0115] like Figure 4 As shown, the first round of testing is performed on the DRAM to be tested:

[0116] like Figure 5 As shown, the test data to be written is defined as / D = 10101010……1010, and its inverse is D = 01010101……0101. Assuming the preset burst length is BL = 8 bits, then / D = 10101010, D = 01010101;

[0117] S1. The address is row 0, column 0. Start writing test data / D from the memory cell corresponding to row 0, column 0, following the BL instruction. After writing row 0, start writing test data / D from row 1, column 0, and so on, until the entire memory array is written with data. Figure 8 As shown in (a);

[0118] S2.1 Perform the first traversal, initialize c (column, column variable) and r (row, row variable), c = 1, r = -1, that is, (1, -1);

[0119] Determine if the sum of c and r is equal to 2 when divided by 4. If yes, increment c by 1 and decrement r by 1. If no, decrement c by 1 and increment r by 1. At this point, the sum of c and r is 0. Since the sum is not equal to 2 when divided by 4, decrement c by 1 and increment r by 1, i.e., (0, 0).

[0120] Check if c and r meet the first out-of-bounds condition, i.e., c equals -1. If yes, assign c to 0, increment r by 1, and perform data read / write operations. If no, check if c and r meet the second out-of-bounds condition, i.e., r equals -1. If yes, assign r to 0, increment c by 1, and perform data read / write operations. If no, check if c and r meet the third out-of-bounds condition, i.e., c is greater than the total number of columns minus one or r is greater than the total number of rows minus one. If yes, break out of the loop. If no, perform data read / write operations.

[0121] At this point, c and r do not meet the subsequent out-of-bounds conditions. Therefore, (0, 0) is taken as the starting position of the first traversal. Figure 6 As shown, a data read / write operation is performed on the preset operation unit on (0,0), that is, the data of the preset operation unit on (0,0) is read, the read data is compared with / D, and then D is written to the preset operation unit on (0,0).

[0122] Continuing the loop based on (0, 0), the sum of c and r is 0. Since the remainder when divided by 4 is not equal to 2, c is decremented by 1 and r is incremented by 1, resulting in (-1, 1). c = -1 satisfies the first boundary condition, so c is assigned the value 0 and r is incremented by 1, resulting in (0, 2). Figure 6 As shown, a data read / write operation is performed on the preset operation unit on (0,2), that is, the data of the preset operation unit on (0,2) is read, the read data is compared with / D, and then D is written to the preset operation unit on (0,2).

[0123] Continuing the loop based on (0, 2), the sum of c and r is 2. Taking the remainder of 4, we get 2, so c increments by 1 and r decrements by 1, resulting in (1, 1). This does not satisfy the subsequent boundary conditions. Figure 6As shown, a data read / write operation is performed on the preset operation unit on (1,1), that is, the data of the preset operation unit on (1,1) is read, the read data is compared with / D, and then D is written to the preset operation unit on (1,1).

[0124] Continuing the loop based on (1, 1), the sum of c and r is 2. Taking the remainder of 4, we get 2, so c increments by 1 and r decrements by 1, resulting in (2, 0). This does not satisfy the subsequent boundary conditions, as shown below. Figure 6 As shown, a data read / write operation is performed on the preset operation unit on (2,0), that is, the data of the preset operation unit on (2,0) is read, the read data is compared with / D, and then D is written to the preset operation unit on (2,0).

[0125] Similarly, the preset operation units on (4, 0), (3, 1), (2, 2), (1, 3), (0, 4), (0, 6), (1, 5)...(9, 9) are traversed in sequence, as follows: Figure 6 As shown;

[0126] After performing data read / write operations on the preset operation unit (9, 9), the loop continues based on (9, 9). The sum of c and r is 18, which is 2 when divided by 4. Therefore, c is incremented by 1 and r is decremented by 1, resulting in (10, 8). c = 10 is greater than the total number of columns minus one, and r = 8 is less than the maximum value of the total number of columns and the total number of rows plus one. Therefore, the loop is exited, and the first traversal ends.

[0127] After the first traversal, the background data of the DRAM to be tested is as follows: Figure 8 As shown in (b);

[0128] S2.2, Perform the second traversal, initialize c = 2, r = -1, i.e. (2, -1);

[0129] Determine if the sum of c and r is equal to 3 when divided by 4. If yes, increment c by 1 and decrement r by 1. If no, decrement c by 1 and increment r by 1. At this point, the sum of c and r is 1. Since the sum is not equal to 3 when divided by 4, decrement c by 1 and increment r by 1, i.e., (1, 0).

[0130] Check if c and r meet the first out-of-bounds condition, i.e., c equals -1. If yes, assign c to 0, increment r by 1, and perform data read / write operations. If no, check if c and r meet the second out-of-bounds condition, i.e., r equals -1. If yes, assign r to 0, increment c by 1, and perform data read / write operations. If no, check if c and r meet the third out-of-bounds condition, i.e., c is greater than the total number of columns minus one or r is greater than the total number of rows minus one. If yes, break out of the loop. If no, perform data read / write operations.

[0131] At this point, c and r do not meet the subsequent out-of-bounds conditions. Therefore, (1, 0) is taken as the starting position for the second traversal. Figure 7 As shown, a data read / write operation is performed on the preset operation unit on (1,0), that is, the data of the preset operation unit on (1,0) is read, the read data is compared with / D, and then D is written to the preset operation unit on (1,0).

[0132] Continuing the loop based on (1, 0), the sum of c and r is 1. Since the remainder when divided by 4 is not equal to 3, c is decremented by 1 and r is incremented by 1, resulting in (0, 1). This does not meet the subsequent boundary conditions. Therefore, a data read / write operation is performed on the preset operation unit at (0, 1), as follows: Figure 7 As shown, the data is read from the preset operation unit on (0,1), the read data is compared with / D, and then D is written to the preset operation unit on (0,1).

[0133] Continuing the loop based on (0, 1), the sum of c and r is 1. Since the remainder when divided by 4 is not equal to 3, c is decremented by 1 and r is incremented by 1, resulting in (-1, 2). c = -1 satisfies the first out-of-bounds condition, so c is assigned the value 0 and r is incremented by 1, resulting in (0, 3). Therefore, data read / write operations are performed on the preset operation unit at (0, 3), such as... Figure 7 As shown, the data is read from the preset operation unit on (0, 3), the read data is compared with / D, and then D is written to the preset operation unit on (0, 3).

[0134] Continuing the loop based on (0, 3), the sum of c and r is 3. Taking the remainder of 4, we get 3, so c increments by 1 and r decrements by 1, resulting in (1, 2). This does not meet the subsequent boundary conditions. Therefore, a data read / write operation is performed on the preset operation unit at (1, 2), as follows: Figure 7 As shown, the data is read from the preset operation unit on (1,2), the read data is compared with / D, and then D is written to the preset operation unit on (1,2).

[0135] Similarly, the preset operation units on (2,1), (3,0), (5,0), (4,1), (3,2), (2,3), (1,4)...(8,9) are traversed in sequence, as follows: Figure 7 As shown;

[0136] After performing data read / write operations on the preset operation unit (8, 9), the loop continues based on (8, 9). The sum of c and r is 17, which is not equal to 3 when divided by 4. Therefore, c is decremented by 1 and r is incremented by 1, i.e., (7, 10). r = 10 is greater than the total number of columns minus one, and c = 7 is less than the maximum value of the total number of columns and the total number of rows plus one. Therefore, the loop is exited and the second traversal ends.

[0137] After the second traversal, the background data of the DRAM to be tested is as follows: Figure 8 As shown in (c), the first comparison result is obtained;

[0138] S3. In the second round of testing, the test data to be written is defined as D = 10101010, and its inverse / D = 01010101. The above steps are then performed.

[0139] After the first traversal, the DRAM data to be tested is as follows: Figure 8 As shown in (d);

[0140] After the second traversal, the DRAM data to be tested is as follows: Figure 8 As shown in (e), Figure 4 As shown, read the data from all preset operation units and compare the read data with / D;

[0141] A second comparison result was obtained;

[0142] If both the first and second comparison results are consistent, the test is successful; otherwise, the test fails.

[0143] Example 2

[0144] The difference between this embodiment and Embodiment 1 is that the preset read / write unit is a column, the first preset direction for both traversals is the diagonal direction from the lower left corner to the upper right corner, and the second preset direction is the diagonal direction from the upper right corner to the lower left corner. Specifically:

[0145] The address is column 0, row 0. Start writing test data / D from the storage cell corresponding to column 0, row 0, according to BL. That is, write test data / D from column 0, row 0 to column 9, row 0. After writing, start writing test data / D from column 0, row 1. After writing all rows from column 0 to column 9, the entire storage array is now written with data.

[0146] The first traversal of the first round of testing begins at (0,0). The preset operation units on (0,0), (2,0), (1,1), (0,2), (0,4), (1,3), (2,2)...(9,9) are traversed in sequence. Data from each preset operation unit is read, the read data is compared with / D, and then D is written to each preset operation unit.

[0147] After the first traversal is completed, the second traversal is performed. (0,1) is used as the starting position of the first traversal. The preset operation units on (0,1), (1,0), (3,0), (2,1), (1,2), (0,3), (0,5)...(9,8) are traversed in turn. The data of these preset operation units are read, the read data is compared with / D, and then D is written to these preset operation units respectively.

[0148] After the second traversal, obtain the first comparison result;

[0149] In the second round of testing, the test data to be written is defined as D = 10101010, and its inverse / D = 01010101. The above steps are then performed.

[0150] After the second traversal of the second round of testing, read the data of all preset operation units and compare the read data with / D;

[0151] A second comparison result was obtained;

[0152] If both the first and second comparison results are consistent, the test is successful; otherwise, the test fails.

[0153] Example 3

[0154] Please refer to Figure 2 A DRAM testing apparatus, comprising:

[0155] The data read / write module is used to perform two rounds of testing on the DRAM under test, and obtain the first comparison result and the second comparison result respectively.

[0156] The tests include:

[0157] Preset test data is written to the DRAM to be tested until all memory cells of the DRAM to be tested have been written with data;

[0158] Based on a preset interval, the DRAM to be tested is traversed in a serpentine path in units of preset operation units until all memory cells of the DRAM to be tested have been traversed.

[0159] For each target preset operation unit traversed, data read and write operations are performed on the target preset operation unit based on the preset test data, and the read data is compared with the corresponding written data.

[0160] The preset test data for the first round of testing is the inverse of the preset test data for the second round of testing;

[0161] The testing module is used to obtain the test results of the DRAM to be tested based on the first comparison result and the second comparison result.

[0162] Example 4

[0163] A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, can implement the various steps of the DRAM testing method in Embodiment 1 or Embodiment 2.

[0164] Example 5

[0165] Please refer to Figure 3 An electronic device includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the various steps of the DRAM testing method in Embodiment 1 or Embodiment 2.

[0166] In summary, the DRAM testing method, apparatus, computer-readable storage medium, and electronic device provided by this invention perform two rounds of testing on the DRAM to be tested. During the process of writing preset test data to the DRAM to be tested, writing is performed in units of a preset burst length, which can improve the data writing speed and reduce time complexity, facilitating mass production testing. Starting from a preset position of the DRAM to be tested, two traversals are performed alternately along a first preset direction and a second preset direction, each in units of preset operation units. The interval between the preset operation units in the first preset direction and the preset operation units in the second preset direction is a preset interval, simulating non-continuous access with a certain interval. First, the data of the target preset operation unit traversed is read, and the read data is compared with the target preset operation unit. The data to be written is compared, and then the inverse of the preset test data is written, which can activate a single storage unit. After the second traversal of the second round of testing, the data of all preset operation units is read, and the read data is compared with the corresponding written data. This can once again check whether the data in the storage unit after testing meets expectations, improving the reliability and accuracy of the test. Since the proportion of multi-storage unit failures is very high, a serpentine path access is implemented on the DRAM to be tested. This reduces the time complexity of the algorithm, covers the previous test blind spots, and detects chip defects that are difficult to be found in existing technologies. This activates multi-storage unit failures such as bridging failures and coupling failures, improves the failure coverage, enhances the reliability of test results, and thus improves product quality.

[0167] In the embodiments provided in this application, it should be understood that the disclosed methods, apparatuses, computer-readable storage media, and electronic devices can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple components or modules may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices, components, or modules may be electrical, mechanical, or other forms.

[0168] The components described as separate parts may or may not be physically separate. The components shown as components may or may not be physical modules; that is, they may be located in one place or distributed across multiple network modules. Some or all of the components can be selected to achieve the purpose of this embodiment according to actual needs.

[0169] Furthermore, the functional modules in the various embodiments of the present invention can be integrated into one processing module, or each component can exist physically separately, or two or more modules can be integrated into one module. The integrated modules described above can be implemented in hardware or as software functional modules.

[0170] If the integrated module is implemented as a software functional module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0171] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that the present invention is not limited to the described order of actions, because according to the present invention, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to the present invention.

[0172] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0173] The above description is merely an embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent modifications made based on the content of the present invention specification and drawings, or direct or indirect applications in related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A DRAM testing method, characterized in that, Including the following steps: The DRAM to be tested was subjected to two rounds of testing, and the first comparison result and the second comparison result were obtained respectively. The tests include: Preset test data is written to the DRAM to be tested until all memory cells of the DRAM to be tested have been written with data; Based on a preset interval, the DRAM to be tested is traversed in a serpentine path in units of preset operation units until all memory cells of the DRAM to be tested have been traversed. For each target preset operation unit traversed, data read and write operations are performed on the target preset operation unit based on the preset test data, and the read data is compared with the corresponding written data. The preset test data for the first round of testing is the inverse of the preset test data for the second round of testing; The test results of the DRAM to be tested are obtained based on the first comparison result and the second comparison result; The step of traversing the DRAM under test through a serpentine path based on a preset interval and in units of a preset operation unit until all memory cells of the DRAM under test have been traversed includes: Based on a preset interval, the DRAM to be tested is traversed alternately along the first preset direction and the second preset direction in units of preset operation units until all memory cells of the DRAM to be tested have been traversed. The step of traversing the DRAM under test along a first preset direction and a second preset direction alternately, based on a preset interval and in units of a preset operation unit, until all memory cells of the DRAM under test have been traversed, includes: Starting from a preset position of the DRAM to be tested, the DRAM to be tested is traversed alternately along the first preset direction and the second preset direction in units of preset operation units; Starting from the adjacent position of the preset position, the storage units not visited in the first traversal are traversed alternately along the first preset direction and the second preset direction in units of preset operation units; The interval between the preset operation unit in the first preset direction and the preset operation unit in the second preset direction is a preset interval.

2. The DRAM testing method according to claim 1, characterized in that, The process of writing preset test data into the DRAM under test until all memory cells of the DRAM under test have been written with data includes: The preset test data is written starting from the low-order address of each preset read / write cell of the DRAM under test, in units of a preset burst length, until all memory cells of the DRAM under test have been written with data.

3. The DRAM testing method according to claim 1, characterized in that, The step of performing data read / write operations on the target preset operation unit based on the preset test data, and comparing the read data with the corresponding written data, includes: Read the data from the target preset operation unit and compare the read data with the corresponding written data; Write the inverse of the preset test data to the target preset operation unit.

4. A DRAM testing method according to any one of claims 1 to 3, characterized in that, The second round of testing also includes the following steps: Read the data from all preset operation units of the DRAM to be tested, and compare the read data with the corresponding written data.

5. A DRAM testing method according to any one of claims 1 to 3, characterized in that, The process of obtaining the test results of the DRAM to be tested based on the first comparison result and the second comparison result includes: If both the first comparison result and the second comparison result are consistent, the test result is successful; otherwise, the test result is unsuccessful.

6. A DRAM testing apparatus, characterized in that, include: The data read / write module is used to perform two rounds of testing on the DRAM under test, and obtain the first comparison result and the second comparison result respectively. The tests include: Preset test data is written to the DRAM to be tested until all memory cells of the DRAM to be tested have been written with data; Based on a preset interval, the DRAM to be tested is traversed in a serpentine path in units of preset operation units until all memory cells of the DRAM to be tested have been traversed. For each target preset operation unit traversed, data read and write operations are performed on the target preset operation unit based on the preset test data, and the read data is compared with the corresponding written data. The preset test data for the first round of testing is the inverse of the preset test data for the second round of testing; The testing module is used to obtain the test results of the DRAM to be tested based on the first comparison result and the second comparison result; The step of traversing the DRAM under test through a serpentine path based on a preset interval and in units of a preset operation unit until all memory cells of the DRAM under test have been traversed includes: Based on a preset interval, the DRAM to be tested is traversed alternately along the first preset direction and the second preset direction in units of preset operation units until all memory cells of the DRAM to be tested have been traversed. The step of traversing the DRAM under test along a first preset direction and a second preset direction alternately, based on a preset interval and in units of a preset operation unit, until all memory cells of the DRAM under test have been traversed, includes: Starting from a preset position of the DRAM to be tested, the DRAM to be tested is traversed alternately along the first preset direction and the second preset direction in units of preset operation units; Starting from the adjacent position of the preset position, the storage units not visited in the first traversal are traversed alternately along the first preset direction and the second preset direction in units of preset operation units; The interval between the preset operation unit in the first preset direction and the preset operation unit in the second preset direction is a preset interval.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the various steps of the DRAM testing method as described in any one of claims 1 to 5.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements each step of the DRAM testing method as described in any one of claims 1 to 5.

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