Deposition mask, and method of making and using the same

Abstract

In general, examples described herein relate to deposition masks and methods of making and using such deposition masks. Examples include methods for forming a deposition mask. A mask layer is deposited on a substrate. A mask opening is patterned through the mask layer. A central portion of the substrate is removed to define a substrate opening through a peripheral portion of the substrate. The mask layer having a mask opening through the mask layer extends across the substrate opening.

Description

Technical Field

[0001] Examples described herein relate generally to the field of semiconductor processing, and more particularly, to deposition masks used in semiconductor processing, including methods of making and using the same. Background Art

[0002] Masks (e.g., hard masks) can be used in a variety of processes in semiconductor processing. Masks are commonly used during etching processes. Masks are being developed to selectively deposit materials on substrates. In such cases, the mask may have a predetermined pattern of openings formed through the mask to allow material to be deposited on the substrate below the mask at locations corresponding to the openings. However, when using masks for selective deposition, the size of the pattern of material to be deposited may pose challenges. Given that the size of semiconductor devices may continue to decrease, these challenges may be exacerbated if they are not addressed. Summary of the invention

[0003] Some examples of the present disclosure include a method for forming a deposition mask. A mask layer is deposited on a substrate. A mask opening is patterned through the mask layer. A central portion of the substrate is removed to define a substrate opening through a peripheral portion of the substrate. The mask layer having the mask opening through the mask layer extends across the substrate opening.

[0004] Some examples of the present disclosure include a semiconductor processing structure including a deposition mask. The deposition mask includes an annular substrate and a mask layer on the annular substrate. The annular substrate has a substrate opening passing through the annular substrate. The mask layer extends across the substrate opening. The mask layer has a mask opening passing through the mask layer and aligned within the substrate opening.

[0005] Other examples of the present disclosure include methods for semiconductor processing. A device substrate and a deposition mask are fixed in a substrate carrier apparatus. The deposition mask is fixed on the device substrate. The deposition mask includes an annular substrate and a mask layer on the annular substrate. The annular substrate has a substrate having an opening through the annular substrate. The mask layer extends through the substrate opening. The mask layer has a mask opening that passes through the mask layer and is aligned within the substrate opening. The substrate carrier apparatus with the device substrate and the deposition mask fixed therein is transferred to a semiconductor processing chamber. In the semiconductor processing chamber, material is deposited on the device substrate through the substrate opening and the mask opening. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] In order that the manner in which the above-mentioned features of the present disclosure can be understood in detail, a more specific description briefly summarized above may be obtained by reference to examples, some of which are shown in the accompanying drawings. However, it should be noted that the accompanying drawings show only some examples and therefore should not be considered to limit the scope of the present disclosure, as the present disclosure may allow other equally effective examples.

[0007] Figures 1 to 5 is a process flow for forming a deposition mask according to some examples.

[0008] Figure 6 to Figure 1 FIG. 1 is another process flow for forming a deposition mask according to some examples.

[0009] Figures 11 to 13 , Fig.14A , Fig. 14B , Fig.15A , Fig. 15B , Fig.16A , Fig. 16B , Fig.17A , Fig. 17B , Fig.18A and Fig.18B is another process flow for forming a deposition mask according to some examples.

[0010] Fig.19 and Fig. 20 2 are front and back side views, respectively, of a deposition mask according to some examples.

[0011] Fig.21 is a deposition mask in a substrate carrier apparatus according to some examples.

[0012] Fig. 22 is a flow chart of a method for semiconductor processing according to some examples.

[0013] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. DETAILED DESCRIPTION

[0014] In general, examples described herein relate to deposition masks and methods of making and using such deposition masks.Example deposition masks described herein can have properties that are beneficial during a deposition process using the deposition mask.

[0015] Deposition masks are being developed for selectively depositing materials. As an example, different organic materials may be selectively deposited for different corresponding pixels in an image sensor, such as an image sensor utilizing an organic photoconductive film (OPF). Certain pixels (e.g., for sensing red light) may utilize a first organic material, while other pixels (e.g., for sensing green or blue light) may utilize a different second organic material. A deposition mask may be used during a selective deposition process to deposit a first organic material on a substrate for some pixels, while another deposition mask may be used during another selective deposition process to deposit a second organic material on a substrate for other pixels.

[0016] During deposition, challenges have been found with using a deposition mask having an opening that has a small width (e.g., for small pixel sizes) and a relatively large depth through which the deposition material is deposited. In this case, the opening through which the material is deposited has a large aspect ratio, and the material can also be deposited on the deposition mask. Due to the large aspect ratio, the material deposited on the deposition mask may cause pinch-off at the corners of the opening, which prevents the material to be deposited from reaching the substrate that is the target of the deposition.

[0017] Some examples described herein can provide a deposition mask having an opening having a lower aspect ratio by providing a relatively thin mask layer. The thin mask layer allows the opening through the mask layer to have a reduced depth and therefore a lower aspect ratio. The lower aspect ratio can reduce the risk of pinching at the opening. Therefore, the material to be deposited is more likely to reach the substrate that is the target of the deposition.

[0018] Some examples described herein may provide a deposition mask including a resistive heating element. The resistive heating element may cause a current to flow during a deposition process, which may increase the temperature of the deposition mask. The increased temperature of the deposition mask may reduce deposition of material on the deposition mask. The reduced deposition may reduce the risk of pinching at the opening. As a result, the material to be deposited is more likely to reach the substrate that is the target of the deposition.

[0019] In addition, the methods of forming a deposition mask described herein may include using processes that may be commonly used in semiconductor processing. Thus, the deposition mask may be formed using ubiquitous tools and semiconductor processes.

[0020] Various different examples are described below. Although multiple features of different examples may be described together in a process flow or system, multiple features may be implemented separately or individually and / or in different process flows or different systems. In addition, various process flows are described as being performed sequentially; other examples may implement the process flows in a different order and / or with more or fewer operations.

[0021] Some example process flows for forming a deposition mask are provided below. Figures corresponding to the process flows are provided. One of ordinary skill in the art will readily appreciate that during various processes, the deposition mask formed and / or the substrate used to form the deposition mask can be processed from both the front side and the back side of the substrate. The orientation of the substrate is shown in the figures as being the same throughout the process, although one of ordinary skill in the art will appreciate that the orientation can change between various processes. In addition, one of ordinary skill in the art will appreciate that, although not shown, a carrier substrate (e.g., in conjunction with an adhesive such as an ultraviolet (UV) glue) can be used to mechanically support the deposition mask and / or substrate during various processes.

[0022] Figures 1 to 5 A process flow for forming a deposition mask according to some examples is shown. Figure 1 The formation of layers on a substrate 100 is shown. The substrate 100 may be any substrate, such as a semiconductor (eg, silicon) substrate, a glass substrate, a sapphire substrate, a titanium nitride substrate, or any other substrate. The substrate 100 generally has a Figures 1 to 5 The process flow forms a deposition mask having a size corresponding to the size of the substrate on which the material is deposited. For example, substrate 100 may have a diameter (if circular) equal to or greater than the diameter (if circular) of the substrate on which the material is deposited using the deposition mask. In some examples, substrate 100 is a silicon wafer.

[0023] The first protective layer 102 is deposited on the substrate 100. The first protective layer 102 can provide multiple functions. The first protective layer 102 can be a seed layer for depositing subsequent layers. The first protective layer 102 can be a diffusion barrier layer for layers formed on the first protective layer 102. The first protective layer 102 can also be used as an etch stop layer by providing etching selectivity to adjacent layers and materials. The first protective layer 102 can be any suitable material. The first protective layer 102 can be or include a metal, an insulating material, or any other material. In some examples, the first protective layer 102 can be or include copper (Cu), aluminum (Al), tungsten (W), or any other suitable material. The first protective layer 102 can be deposited by any suitable deposition process (such as physical vapor deposition (PVD), chemical vapor deposition process (CVD), and / or the like).

[0024] The mask layer 104 is deposited on the first protective layer 102. The mask layer 104 may be formed with a tensile stress, which may contribute to the structural integrity of the deposition mask formed with the mask layer 104. The mask layer 104 may be any suitable material. The mask layer 104 may be or include a material that can be selectively etched relative to adjacent materials. The mask layer 104 may be a single layer of a material, or may be a multilayer of various materials. In some examples, the mask layer 104 may be or include silicon nitride (SiN), silicon oxynitride (SiON), copper (Cu), aluminum (Al), tungsten (W), or any other suitable material. The mask layer 104 may be or include a metal, an insulating material, or any other material. The mask layer 104 may be deposited by any suitable deposition process, such as PVD, CVD, and / or the like.

[0025] The second protective layer 106 is deposited on the mask layer 104. The second protective layer 106 can provide multiple functions. The second protective layer 106 can be a diffusion barrier for the mask layer 104. The second protective layer 106 can also be used as an etch stop layer by providing etching selectivity to the mask layer 104 and the upper layer. The second protective layer 106 can be any suitable material. The second protective layer 106 can be or include a metal, an insulating material, or any other material. In some examples, the second protective layer 106 can be or include copper (Cu), aluminum (Al), tungsten (W), or any other suitable material. The second protective layer 106 can be deposited by any suitable deposition process (such as PVD, CVD / or the like).

[0026] A spacer layer 108 is deposited on the second protective layer 106. The spacer layer 108 may be formed as a spacer element that may provide sufficient spacing between a deposition mask to be formed and an underlying layer on which material is deposited using the deposition mask. Thus, the spacer layer 108 may have a thickness corresponding to a target spacing. The spacer layer 108 may be any suitable material. The spacer layer 108 may be or include a metal, an insulating material, or any other material. In some examples, the spacer layer 108 may be or include silicon nitride (SiN), silicon oxide (SiO), copper (Cu), aluminum (Al), tungsten (W), or any other suitable material. The spacer layer 108 may be deposited by any suitable deposition process, such as PVD, CVD / or the like.

[0027] For ease of reference herein, the side of the substrate 100 on which the layers 102, 104, 106, 108 are deposited may be referred to as the front side of the substrate 100, and processing of the substrate 100 and the layers 102, 104, 106, 108 in a direction toward the front side (e.g., not passing through the substrate 100) may be referred to as front side processing. Figure 1 The processing of the substrate 100 and the layers 102, 104, 106, 108 may be referred to as front-side processing. Conversely, the side of the substrate 100 opposite the front side of the substrate 100 may be referred to as the back side of the substrate 100, and the processing of the substrate 100 and the layers 102, 104, 106, 108 in the direction toward the back side may be referred to as back-side processing. Similar conventions may be used to describe other processing flows.

[0028] Figure 2The central portion of the substrate 100 is shown to be removed to define a substrate opening through the substrate 100. Suitable photolithography and etching processes can be used to remove the central portion of the substrate 100. For example, reactive ion etching (RIE) can be used to etch the substrate 100. The remaining outer or peripheral portion of the substrate 100 can circumscribe the area where the deposition mask pattern is to be formed. The remaining outer or peripheral portion of the substrate 100 can also be referred to as an annular substrate. As used herein, the term annular is not limited to a circular closed shape, and may include other closed shapes (such as (for example) a rectangle, a polygon, etc.). The central portion of the substrate 100 can be removed by backside processing.

[0029] Figure 3 The spacer layer 108 is shown patterned into spacer elements. The spacer layer 108 may have portions removed in areas where the deposition mask pattern is to be formed. For example, portions of the spacer layer 108 may remain at outer portions that correspond vertically to (in the drawings) the remaining outer or peripheral portions of the substrate 100. In addition, various portions of the spacer layer 108 may remain at wide areas where mask openings for the deposition mask will not be formed. As an example, if the deposition mask has a pattern for each device or die on which material is to be deposited, the wide area may be located between each device or die (e.g., corresponding to the scribe line area) and portions of the spacer layer 108 remain at the wide area. The spacer layer 108 can be patterned using a suitable lithography and etching process (such as RIE).

[0030] Figure 4 The second protective layer 106, mask layer 104, and first protective layer 102 are shown patterned to form mask openings through the layers 102, 104, 106. The mask openings correspond to the pattern of material to be deposited using the deposition mask, and the mask openings are aligned within the substrate openings through the substrate 100. The layers 106, 104, 102 may be patterned using a suitable lithography and etching process, such as RIE, which may be performed using a front side or back side process.

[0031] Figure 5 Shown is the removal of exposed portions of the first protective layer 102 and the second protective layer 106. In some examples, during front-side processing, the exposed portions of the second protective layer 106 are removed using a dry anisotropic etching process (such as RIE), and during back-side processing, the exposed portions of the first protective layer 102 are removed using a dry anisotropic etching process (such as RIE). In some examples, the exposed portions of both the first protective layer 102 and the second protective layer 106 are removed in the same processing step, such as using an isotropic etching process, which can be a wet process or a dry process.

[0032] The deposition mask can thus be Figure 5The mask layer 104 has a through hole therethrough. Figure 4 The mask openings through the mask layer 104 may have an aspect ratio of depth (e.g., the thickness of the mask layer 104 or the dimension of the opening perpendicular to the main plane of the mask layer 104) to width (e.g., the dimension perpendicular to the depth) that is low enough to allow material to be deposited through the openings to another substrate, for example, without being pinched at the openings by material to be deposited on the mask layer 104. In some examples, the aspect ratio of the openings may be 1:1 or less. In some examples, the thickness of the mask layer 104 and therefore the depth of the openings may be in a range from about 2 μm to about 3 μm, and the width of the openings may be in a range from about 2 μm to about 3 μm. In some examples, the width of the openings may be greater than the thickness of the mask layer 104.

[0033] The remaining outer or peripheral portion of the substrate 100 surrounds the patterned portion of the mask layer 104. The remaining outer or peripheral portion of the substrate 100 can thus provide mechanical support for the mask layer 104 for handling and transporting the deposition mask. The tensile stress of the mask layer 104 can keep the mask layer 104 rigid across the substrate opening extending through the substrate 100.

[0034] Figures 6 to 10 Another process flow for forming a deposition mask according to some examples is shown. Figure 1 As stated, and as Figure 1 As shown, a first protection layer 102 , a mask layer 104 , a second protection layer 106 , and a spacer layer 108 are deposited on a substrate 100 .

[0035] exist Figure 6 and Figure 7 In the process, the front side processing continues as described above. Figure 3 As described above, the spacer layer 108 is patterned and Figure 4 As described above, the second protection layer 106 , the mask layer 104 , and the first protection layer 102 are patterned. Figure 8 Exposed portions of the second protective layer 106 are shown being removed during front-side processing, such as by using a dry anisotropic etching process such as RIE.

[0036] exist Fig. 9 In the back side processing, as mentioned above Figure 2 As described above, the central portion of the substrate 100 is removed. Fig.10 The exposed portion of the first protective layer 102 is shown removed during backside processing, such as by using a dry anisotropic etching process (such as RIE). Fig.10 The deposition mask shown may have the same Figure 5 The deposition masks have the same or similar properties and characteristics.

[0037] Figures 11 to 13 , Fig.14A , Fig. 14B , Fig.15A , Fig. 15B , Fig.16A , Fig. 16B , Fig.17A , Fig. 17B , Fig.18A and Fig.18B Another process flow for forming a deposition mask is shown according to some examples. Fig.19 shows a front side view of the formed deposition mask, and Fig. 20 A backside view of the formed deposition mask is shown. Fig.19 and Fig. 20 Cross sections AA and BB are shown perpendicular to each other. Cross section AA corresponds to the drawing ending with "A" marking during processing, while cross section BB corresponds to the drawing ending with "B" marking during processing.

[0038] Fig.11 Layers are shown formed on a substrate 200. The substrate 200 may be any substrate, as previously described with respect to the substrate 100. A first protective layer 202 is deposited on the substrate 200, as previously described with respect to the first protective layer 102.

[0039] A first conductive mask layer 204 is deposited on the first protective layer 202. An insulating mask layer 206 is deposited on the first conductive mask layer 204. A second conductive mask layer 208 is deposited on the insulating mask layer 206. Each of the first conductive mask layer 204, the insulating mask layer 206, and the second conductive mask layer 208 can be formed with a tensile stress, which can contribute to the structural integrity of the deposition mask formed with the mask layers 204, 206, 208. The first conductive mask layer 204 and the second conductive mask layer 208 can each be, for example, any suitable conductive material that can be used to form a resistive heating element. The first conductive mask layer 204 and the second conductive mask layer 208 can each be or include a material that can be selectively etched relative to an adjacent material. In some examples, the first conductive mask layer 204 and the second conductive mask layer 208 can each be or include a metal, such as copper (Cu), aluminum (Al), tungsten (W), or any other metal. The insulating mask layer 206 can be any electrically insulating material between the first conductive mask layer 204 and the second conductive mask layer 208. The insulating mask layer 206 can also be or include a material that can be selectively etched relative to the first conductive mask layer 204 and the second conductive mask layer 208. In some examples, the insulating mask layer 206 can be or include silicon nitride (SiN), silicon oxynitride (SiON), or any other insulating material. The mask layers 204, 206, 208 can be deposited by any suitable deposition process, such as PVD, CVD, and / or the like.

[0040] As will become apparent, the first conductive mask layer 204 will be formed as a resistive heating element through which current flows to generate increased temperature or heat. The first conductive mask layer 204 will be patterned so that current flows in a plane parallel to the cross-section AA. Similarly, the second conductive mask layer 208 will also be formed as a resistive heating element through which current flows to generate increased temperature or heat. The second conductive mask layer 208 will be patterned so that current flows in a plane parallel to the cross-section BB. When the conductive mask layers 204, 208 are used as respective resistive heating elements, the insulating mask layer 206 provides electrical isolation between the first conductive mask layer 204 and the second conductive mask layer 208.

[0041] As previously described for the second protective layer 106, the second protective layer 210 is deposited on the second conductive mask layer 208. As previously described for the spacer layer 108, the spacer layer 212 is deposited on the second protective layer 210.

[0042] Fig.12 The central portion of the substrate 200 is shown removed, as previously described with respect to Figure 2 The substrate 100 is described. Fig.13 The patterning of the spacer layer 212 is shown, as previously described with respect to Figure 3The spacer layer 108 is described.

[0043] Fig.14A and Fig. 14B The patterned second protection layer 210 , the second conductive mask layer 208 , and the insulating mask layer 206 are shown. Fig.14A and Fig. 14B The patterning in the patterned area forms a b-direction groove that passes through the second protective layer 210, the second conductive mask layer 208, and the insulating mask layer 206 parallel to the cross section BB (and perpendicular to the cross section AA). Therefore, the patterning forms a b-direction line of the second protective layer 210, the second conductive mask layer 208, and the insulating mask layer 206 parallel to the cross section BB in the patterned area. Fig.14A As shown, the patterning removes some lateral outer portions of the second protection layer 210, the second conductive mask layer 208, and the insulating mask layer 206 to expose the contact area 214 of the first conductive mask layer 204. Fig. 14B As shown, some other laterally outer portions of the second conductive mask layer 208 remain, which may form contact regions of the second conductive mask layer 208 .

[0044] Fig.15A and Fig. 15B The exposed portion of the second protective layer 210 is shown removed during front side processing, such as by using a dry anisotropic etching process (such as RIE). Fig. 15B As shown, the removal of the exposed portion of the second protection layer 210 exposes the contact region 216 of the second conductive mask layer 208 .

[0045] Fig.16A and Fig. 16B A patterned first protection layer 202, a first conductive mask layer 204, and an insulating mask layer 206 are shown. Fig.16A and Fig. 16B The patterning in forms an a-direction groove that passes through the first protective layer 202, the first conductive mask layer 204, and the insulating mask layer 206 parallel to the cross section AA (and perpendicular to the cross section BB). Therefore, the patterning forms an a-direction line of the first protective layer 202, the first conductive mask layer 204, and the insulating mask layer 206 parallel to the cross section AA in the patterned area. The intersection of the a-direction groove and the b-direction groove forms a mask opening for the deposition mask. As shown in the figure, no groove extends through the mask layers 204, 206, and 208 alone. At the intersection of the a-direction groove and the b-direction groove, the grooves combine to form a mask opening.

[0046] Fig.17A and Fig. 17B Exposed portions of the first protective layer 202 are shown being removed during backside processing, such as by using a dry anisotropic etching process such as RIE.

[0047] Fig.18A and Fig.18B The formation of a support matrix 218 is shown. The support matrix 218 can be formed in the substrate opening and on the first conductive mask layer 204 by backside processing. The support matrix 218 can span the substrate opening of the substrate 200, bridging between opposing sections of the outer or peripheral portion of the substrate 200, such as Fig. 20 As shown. The support matrix 218 can be formed on a wide area of ​​the first conductive mask layer 204 through which no mask opening is formed. As an example, if the deposition mask has a pattern for each device or die on which material is to be deposited, the wide area can be between each device or die (e.g., corresponding to the scribe line area) where a portion of the support matrix 218 can be disposed. Therefore, the support matrix 218 can provide additional mechanical support to the mask layers 204, 206, 208. The support layer can be deposited, such as by any suitable deposition process (such as PVD, CVD or the like), and the support matrix 218 can be patterned, such as by a suitable lithography and etching process (such as RIE).

[0048] Fig.19 and Fig. 20 The front and back views of the deposition mask are shown, respectively. Mask openings are formed through the mask layers 204, 206, 208, wherein a-direction grooves (related to Fig.16A and Fig. 16B and b-direction grooves (related to Fig.14A and Fig. 14B The openings through the mask layers 204, 206, 208 may have an aspect ratio of depth (e.g., the combined thickness of the mask layers 204, 206, 208 or the dimension of the opening perpendicular to any principal plane of the mask layers 204, 206, 208) to width (e.g., the dimension perpendicular to the depth) that is low enough to allow material to be deposited through the openings to another substrate, for example, without being pinched off at the openings by material to be deposited on the mask layers 204, 206, 208. In some examples, the aspect ratio of the openings may be 1:1 or less. In some examples, the combined thickness of the mask layers 204, 206, 208, and therefore the depth of the openings, may be in a range from about 2 μm to about 3 μm, and the width of the openings may be in a range from about 2 μm to about 3 μm. In some examples, the width of the openings may be greater than the combined thickness of the mask layers 204, 206, 208.

[0049] In some examples, the aspect ratio may be greater than 1:1. As previously described, the conductive mask layer 204, 208 may be a resistive heating element. When the conductive mask layer 204, 208 is used as a resistive heating element during a deposition process, less material deposited by the deposition process may be deposited on the conductive mask layer 204, 208, and thus pinch-off at the opening through the conductive mask layer 204, 208 may be reduced. As pinch-off is reduced, the aspect ratio of the opening may be increased.

[0050] Fig.19 and Fig. 20 The a-direction line formed by the patterned first conductive mask layer 204 and the b-direction line formed by the patterned second conductive mask layer 208 are shown. Fig.19 The contact area 214 of the first conductive mask layer 204 and the contact area 216 of the second conductive mask layer 208 on the front side of the ring-shaped substrate 200 are shown. Fig.19 The pattern of the spacer layer 212 is shown on the annular substrate 200 and along areas corresponding to the scribe lines of the device or die of the substrate on which material will be deposited using a deposition mask. Fig. 20 A support matrix 218 is shown bridging between segments of the annular substrate 200 across the substrate openings and patterned areas of the deposition mask.

[0051] Those skilled in the art will readily appreciate that various aspects of the different process flows and deposition masks formed thereby may be incorporated into other process flows and / or deposition masks. Fig.18A and Fig.18B The support matrix 218 shown may be incorporated into Figure 5 and / or Fig.10 In the deposition mask, the corresponding process flow can be modified to incorporate the formation of the support matrix. In addition, the process flow can be modified, such as by changing the order and / or by including more or fewer processes. As an example, Figures 6 to 10 The processing flow shows Figures 1 to 5 Similarly, you can modify Fig.11 Picture to Figures 18A-18B The processing flow is such that front-side processing is performed before back-side processing.

[0052] Fig.21 The substrate carrier apparatus 300 is shown in FIG. Figures 18A-18B , Fig.19 and Fig. 20 In other examples, Figure 5 and Fig.10The deposition mask can be used in similar substrate carrier devices. Although a person skilled in the art will readily appreciate that various modifications can be made, it is pointed out herein that various modifications can be made to the substrate carrier device 300 shown to implement Figure 5 and Fig.10 Deposition mask.

[0053] The deposition mask may have a carrier frame 302 attached to the deposition mask. The carrier frame 302 may be a rigid frame that provides additional mechanical support for the deposition mask. For example, the carrier frame 302 may provide additional support for handling and transporting the deposition mask. Fig.21 In the context of , the carrier frame 302 is attached to the deposition mask. The carrier frame 302 includes an outer frame 304 and an inner flange 306. The carrier frame 302 can be formed of any rigid material. In some examples, such as for Figure 5 and Fig.10 For deposition masks, the carrier frame 302 may be metal. In some examples, such as for Figures 18A-18B , Fig.19 and Fig. 20 For the deposition mask of the substrate, the carrier frame 302 may be formed of, for example, a dielectric material or a dielectric-coated metal. Figures 18A-18B , Fig.19 and Fig. 20 The carrier frame 302 of the deposition mask needs to be formed so that the first conductive mask layer 204 is not electrically connected to the second conductive mask layer 208 or the first conductive mask layer 204 is electrically isolated from the second conductive mask layer 208 when the carrier frame 302 is attached to the deposition mask. Therefore, forming the carrier frame 302 of a dielectric material or coating the carrier frame 302 with a dielectric material can prevent electrical connection between the first conductive mask layer 204 and the second conductive mask layer 208. The outer frame 304 laterally surrounds the deposition mask (e.g., laterally surrounds the annular substrate 200), and the inner flange 306 contacts the front side of the deposition mask along the lateral periphery of the deposition mask. The carrier frame 302 can be bonded or adhered to the deposition mask. For example, an adhesive can adhere the inner flange 306 to the lateral periphery of the deposition mask. The inner flange may have a certain thickness (e.g., in a direction perpendicular to the front side surface of the substrate 200 when the carrier frame 302 is attached to the deposition mask) such that the surface of the inner flange 306 opposite to the substrate 200 is substantially coplanar with the surface of the spacer element formed by the spacer layer 212 opposite to the substrate 200.

[0054] The substrate carrier apparatus 300 can fix a deposition mask (with a carrier frame 302 attached) on a device substrate 308. The substrate carrier apparatus 300 includes a carrier body 310 and a mask holder assembly 312 thereon. The carrier body 310 includes a support surface 314 to support the device substrate 308. In some examples, the carrier body 310 is formed of a non-metallic material such as alumina, silicon, etc. In some examples, the support surface 314 can be textured to minimize or substantially prevent the device substrate 308 from moving along the support surface 314 during processing of the substrate carrier apparatus 300. The mask holder assembly 312 is disposed above the support surface 314 and includes an annular frame 316 disposed atop the support surface 314. The mask holder assembly 312 also includes a flexible element 318 coupled to the annular frame 316.

[0055] The device substrate 308 is disposed on the support surface 314, and the deposition mask is disposed on the device substrate 308. The deposition mask is disposed within the annular frame 316 so that the deposition mask is directly located above the device substrate 308. The mask openings through the deposition mask are positioned to selectively allow material to pass through the mask openings and be deposited onto the device substrate 308 at locations corresponding to the mask openings. The spacing elements of the spacer layer 212 extend to the top surface of the device substrate 308 to maintain a predetermined gap between the mask layers 208, 206, 204 and the device substrate 308. Similarly, the surface of the inner flange 306 opposite the substrate 200 is located on the top surface of the device substrate 308.

[0056] The flexible element 318 couples the annular frame 316 to the deposition mask. The flexible element 318 is also coupled to the deposition mask at the end of the flexible element 318 opposite the annular frame 316. In some examples, the flexible element 318 can be welded to both the annular frame 316 and the deposition mask. In some examples, the flexible element 318 can be brazed or glued to both the annular frame 316 and the deposition mask. Fig.21 , in some examples, the flexible element 318 includes a plurality of springs 320 coupled to a corresponding plurality of coupling bodies 322 (e.g., via welding, brazing, or adhesive). In some examples, the flexible element 318 may include a spring elastomer as an alternative and / or in addition to the springs 320. The substrate (e.g., the device substrate 308) typically has a thickness variation across the substrate. The flexible element 318 can compensate for such thickness variations by allowing for the deposition mask to not be perfectly horizontal while still ensuring that the annular frame 316 is placed flush against the support surface 314.

[0057] The carrier body 310 may be a portable electrostatic chuck (ESC) configured to hold the device substrate 308 on a support surface 314 of the carrier body 310 using an electrostatic force. In some examples, the carrier body 310 may include one or more electrodes 324 and one or more corresponding electrical leads 326 configured to couple electrical power to the one or more electrodes 324 to electrostatically clamp the device substrate 308 to the support surface 314. After power is applied to the one or more electrodes 324 to clamp the device substrate 308 to the support surface 314, the electrostatic clamping force remains in the carrier body 310 and the device substrate 308 even if power is no longer supplied to the one or more electrodes 324 thereafter (e.g., during transfer of the substrate carrier apparatus 300 to / from a processing chamber). In this way, movement of the device substrate 308 during transfer of the substrate carrier apparatus 300 during processing may be prevented.

[0058] To remove the device substrate 308 from the carrier body 310, power having an opposite charge to the clamping power is provided to the one or more electrical leads 326 to allow removal of the device substrate 308. The carrier body 310 may include any structure to facilitate placement / removal of the device substrate 308 onto / from the support surface 314. For example, the carrier body 310 may include lift pin holes (not shown) to allow lift pins to lift and lower the device substrate 308 from the support surface 314 or recess (not shown) to allow an end effector to pass under the device substrate 308 to place and remove the device substrate 308.

[0059] In some examples, such as for Figures 18A-18B , Fig.19 and Fig. 20 The carrier frame 302 includes contacts 330. The contacts 330 can establish electrical connections with the corresponding contact areas 214, 216 of the first conductive mask layer 204 and the second conductive mask layer 208. As shown, the contacts 330 are embedded in the inner flange 306 of the carrier frame 302. At least four contacts 330 (two not in Fig.21302) are embedded in the inner flange 306. Each of the contacts 330 is configured to establish electrical contact with a corresponding one of the contact areas 214, 216 of the deposition mask. The contacts 330 in the carrier frame 302 are electrically connected to corresponding electrical leads 332 in the carrier body 310, and the electrical leads 332 are configured to couple electrical power to the contacts 330. The contacts 330 can be electrically connected to the leads 332 through the carrier frame 302 in contact with the carrier body 310 (e.g., via an electrical path formed through the carrier frame 302 and the carrier body 310) and / or through the carrier frame 302, the ring frame 316, and the carrier body 310 (e.g., via an electrical path formed through the carrier frame 302, the ring frame 316, and the carrier body 310).

[0060] During a deposition process, the substrate carrier apparatus 300 may be placed on a pedestal in a semiconductor processing chamber, and the electrical contacts may be located on a surface of the pedestal on which the substrate carrier apparatus 300 is placed. The leads 332 of the carrier body 310 may be placed in electrical contact with the electrical contacts of the pedestal so that power may be supplied to the contacts 330 through the pedestal, and thus, current may flow through each of the first conductive mask layer 204 and the second conductive mask layer 208. By flowing current through the first conductive mask layer 204 and the second conductive mask layer 208, an elevated temperature or heat may be generated in the deposition mask, which may reduce deposition of material on the deposition mask.

[0061] Fig. 22 4 is a flow chart of a method 400 for semiconductor processing. For example, method 400 may be performed in a cluster tool comprising a plurality of semiconductor processing chambers. During method 400, the cluster tool and the semiconductor processing chamber may be maintained under vacuum or low pressure. In some examples, the processing chamber of the cluster tool includes a holding chamber for storing one or more deposition masks. Another processing chamber may include an alignment chamber for aligning a device substrate and a deposition mask in a substrate carrier device and fixing the device substrate and the deposition mask in the substrate carrier device. Another processing chamber may include a deposition chamber (such as for evaporative deposition). A transfer chamber including a transfer robot may be connected to other processing chambers and may be configured to transfer different substrates, deposition masks and / or substrate carrier devices to and from other processing chambers and between other processing chambers.

[0062] At block 402, a device substrate and a deposition mask are secured in a substrate carrier apparatus. For example, the device substrate and the deposition mask may be secured in a substrate carrier apparatus such as Fig.21 For example, the deposition mask may be Figure 5 , Fig.10 ,as well as Figures 18A-18B , Fig.19 and Fig. 20As an example, a transfer robot of a transfer chamber may transfer a substrate carrier apparatus to an alignment chamber. The transfer robot also transfers a deposition mask (such as from a holding chamber) and a device substrate (such as from a load lock or other storage chamber) to the alignment chamber. The alignment chamber includes various optical alignment and stepping equipment to align the substrate carrier apparatus, the device substrate, and the deposition mask. Once aligned, the device substrate and the deposition mask are then secured in the substrate carrier apparatus.

[0063] In block 404, the substrate carrier apparatus (having the device substrate and deposition mask secured therein) is transported to a semiconductor processing chamber. For example, a transfer robot may transport the substrate carrier apparatus from an alignment chamber to a deposition chamber.

[0064] In block 406, in a semiconductor processing chamber, a material is deposited on a device substrate through a mask opening of a deposition mask. The material is deposited through a substrate opening of an annular substrate and a mask opening aligned within the substrate opening and through (multiple) mask layers. For example, evaporative deposition of an organic material may be performed. The organic material may be deposited through the substrate opening and the mask opening of the deposition mask. In some examples, the mask opening may have an aspect ratio of 1:1 or less, which may reduce the likelihood of pinching at the mask opening during the deposition process. In some examples, a current may flow through a conductive mask layer to generate heat at the conductive mask layer. For example, electrical power may be provided at contact regions 214, 216. Current may flow in the a direction through an a direction line formed in the first conductive mask layer 204 between the contact regions 214, and current may flow in the b direction through a b direction line formed in the second conductive mask layer 208 between the contact regions 216. The conductive mask layers 204, 208 form resistive heating elements that generate heat by a current flowing through the conductive mask layers 204, 208. Generating heat in the conductive mask layers 204, 208 may reduce deposition of material on the deposition mask.

[0065] Some examples include a method for forming a deposition mask. A mask layer is deposited on a substrate. A mask opening is patterned through the mask layer. A central portion of the substrate is removed to define a substrate opening through a peripheral portion of the substrate. The mask layer having the mask opening through the mask layer extends across the substrate opening.

[0066] In a further example of the above method, the mask openings through the mask layer may have a ratio of a depth of the corresponding mask opening to a width of the corresponding mask opening that is 1:1 or less.

[0067] In a further example of the above method, the mask layer may be deposited with a tensile stress.

[0068] In a further example, the above method may further include the following steps: depositing a first protective layer on the substrate, a mask layer being deposited on the first protective layer; depositing a second protective layer on the mask layer, patterning mask openings through the first protective layer and the second protective layer; and removing portions of the first protective layer and the second protective layer.

[0069] In a further example, the method may further include the following steps: depositing a spacer layer on the mask layer; patterning the spacer layer into spacer elements, wherein scribe areas are defined between groups of mask openings, and the spacer elements are along at least some of the scribe areas.

[0070] In a further example, the above method may further include the following steps: forming a support matrix on the mask layer and in the substrate openings, with scribe areas defined between groups of mask openings, and the support matrix along at least some of the scribe areas and contacting a peripheral portion of the substrate.

[0071] In a further example of the above method, depositing a mask layer on a substrate may include the following steps: depositing a first conductive mask layer on the substrate; depositing an insulating mask layer on the first conductive mask layer; and depositing a second conductive mask layer on the insulating mask layer. In a further example, patterning a mask opening through the mask layer may include the following steps: patterning a first trench through the second conductive mask layer; and patterning a second trench through the first conductive mask layer through the substrate opening. At least the first trench, the second trench, or a combination thereof may pass through the insulating mask layer, and the intersection of the first trench and the second trench may form a mask opening.

[0072] In a further example, the above method may further include the step of attaching a carrier frame to the mask layer and the substrate, an outer frame of the carrier frame surrounding a peripheral portion of the substrate.

[0073] Some examples include a semiconductor processing structure comprising: a deposition mask, the deposition mask comprising: an annular substrate, the annular substrate having a substrate opening passing through the annular substrate; and a mask layer, the mask layer is located on the annular substrate and extends across the substrate opening, the mask layer having a mask opening passing through the mask layer and aligned within the substrate opening.

[0074] In a further example of the foregoing semiconductor processing structure, the mask openings through the mask layer may have a ratio of a depth of the corresponding mask opening to a width of the corresponding mask opening that is 1:1 or less.

[0075] In a further example of the semiconductor processing structure described above, the deposition mask may further include spacer elements on the mask layer opposite the annular substrate, scribe areas are defined between groups of mask openings, and the spacer elements are along at least some of the scribe areas.

[0076] In a further example of the above-mentioned semiconductor processing structure, the deposition mask may further include a support matrix located on the mask layer and in the substrate openings, with scribe areas defined between groups of mask openings, and the support matrix is ​​along at least some of the scribe areas and contacts the annular substrate.

[0077] In a further example of the above-mentioned semiconductor processing structure, the mask layer may include: a first conductive mask layer on the annular substrate, the first groove passing through the first conductive mask layer; an insulating mask layer on the first conductive mask layer; and a second conductive mask layer on the insulating mask layer, the second groove passing through the second conductive mask layer; at least the first groove, the second groove or a combination thereof passes through the insulating mask layer, and the intersection of the first groove and the second groove forms a mask opening.

[0078] In a further example, the semiconductor processing structure described above may further include a carrier frame attached to the deposition mask, an outer frame of the carrier frame surrounding the annular substrate.

[0079] Some examples include a method for semiconductor processing. The method includes the following steps: fixing a device substrate and a deposition mask in a substrate carrier apparatus, the deposition mask being fixed on the device substrate, the deposition mask including: an annular substrate having a substrate opening passing through the annular substrate; and a mask layer, the mask layer being located on the annular substrate and extending across the substrate opening, the mask layer having a mask opening passing through the mask layer and aligned within the substrate opening; transporting the substrate carrier apparatus with the device substrate and the deposition mask fixed therein to a semiconductor processing chamber; and depositing a material on the device substrate through the substrate opening and the mask opening in the semiconductor processing chamber.

[0080] In a further example of the above method, the mask openings through the mask layer may have a ratio of a depth of the corresponding mask opening to a width of the corresponding mask opening that is 1:1 or less.

[0081] In a further example of the above method, depositing material through the substrate opening and the mask opening may include the step of depositing the organic material using evaporation.

[0082] In a further example of the above method, the mask layer may include a conductive mask layer, and depositing material through the substrate opening and the mask opening may include passing a current through the conductive mask layer.

[0083] In a further example of the above method, the deposition mask may include spacer elements on the mask layer, the spacer elements being disposed between the device substrate and the mask layer when the device substrate and the deposition mask are secured in the substrate carrier apparatus.

[0084] While the foregoing is directed to various examples of the present disclosure, other and further examples may be devised without departing from the basic scope of the present disclosure, the scope of which is to be determined by the claims that follow.

Claims

1. A method for forming a deposition mask for evaporative deposition, the method comprising the following steps: depositing a mask layer on the substrate; patterning a plurality of mask openings through the mask layer; and removing a central portion of the substrate to define a substrate opening through a peripheral portion of the substrate, the mask layer having the mask opening through the mask layer extending across the substrate opening, wherein the mask openings through the mask layer have a ratio of a depth of the corresponding mask opening to a width of the corresponding mask opening, the ratio being 1:1 or less, The step of depositing the mask layer on the substrate comprises: depositing a first conductive mask layer on the substrate; depositing an insulating mask layer on the first conductive mask layer; and depositing a second conductive mask layer on the insulating mask layer, The first conductive mask layer and the second conductive mask layer are formed as a resistive heating element. 2 . The method according to claim 1 , wherein the depth is in a range from 2 μm to 3 μm, and the width is in a range from 2 μm to 3 μm. The method of claim 1 , wherein the mask layer is deposited with a tensile stress.

4. The method according to claim 1, further comprising the following steps: Depositing a first protective layer on the substrate, wherein the mask layer is deposited on the first protective layer; depositing a second protective layer on the mask layer, the mask opening being patterned through the first protective layer and the second protective layer; and Portions of the first protective layer and the second protective layer are removed.

5. The method according to claim 1, further comprising the following steps: depositing a spacer layer on the mask layer; and The spacer layer is patterned into spacer elements, scribe areas are defined between groups of the mask openings, and the spacer elements are along at least some of the scribe areas.

6. The method according to claim 1, further comprising the steps of: A support matrix is ​​formed on the mask layer and in the substrate openings, a plurality of scribe areas are defined between groups of the mask openings, the support matrix is ​​along at least some of the scribe areas and contacts the peripheral portion of the substrate.

7. The method of claim 1 , wherein the step of patterning the mask opening through the mask layer comprises the steps of: patterning a plurality of first trenches through the second conductive mask layer; and A plurality of second trenches are patterned through the first conductive mask layer through the substrate opening, at least the first trench, the second trench or a combination thereof passes through the insulating mask layer, and intersections of the first trench and the second trench form the mask opening.

8. The method according to claim 1, further comprising the steps of: A carrier frame is attached to the mask layer and the substrate, an outer frame of the carrier frame surrounding the peripheral portion of the substrate.

9. A semiconductor processing structure comprising: Deposition mask for evaporative deposition, comprising: an annular substrate having a substrate opening passing through the annular substrate; and a mask layer, the mask layer being located on the annular substrate and extending across the substrate opening, the mask layer having a plurality of mask openings passing through the mask layer and aligned within the substrate opening, wherein the mask layer comprises: a first conductive mask layer located on the annular substrate; an insulating mask layer located on the first conductive mask layer; and a second conductive mask layer located on the insulating mask layer, The first conductive mask layer and the second conductive mask layer are formed as a resistive heating element, wherein the mask openings through the mask layers have a ratio of a depth of the corresponding mask opening to a width of the corresponding mask opening, the ratio being 1:1 or less.

10. The semiconductor processing structure of claim 9, wherein the depth is in a range from 2 μm to 3 μm, and the width is in a range from 2 μm to 3 μm.

11. The semiconductor processing structure of claim 9, wherein the deposition mask further comprises spacer elements on the mask layer opposite the annular substrate, scribe areas being defined between groups of the mask openings, the spacer elements being along at least some of the scribe areas.

12. A semiconductor processing structure according to claim 9, wherein the deposition mask further includes a support matrix located on the mask layer and in the substrate opening, a plurality of scribe areas are defined between groups of the mask openings, and the support matrix is ​​along at least some of the scribe areas and contacts the annular substrate.

13. The semiconductor processing structure of claim 9, wherein A plurality of first trenches pass through the first conductive mask layer; a plurality of second trenches passing through the second conductive mask layer; At least the first trench, the second trench, or a combination thereof passes through the insulating mask layer, and a plurality of intersections of the first trench and the second trench form the mask opening.

14. The semiconductor processing structure of claim 9, further comprising a carrier frame attached to the deposition mask, an outer frame of the carrier frame surrounding the annular substrate.

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