Computational optimization for low-precision machine learning operations

Abstract

The invention of this application is entitled: Computational optimization of low-precision machine learning operations. One embodiment provides a general-purpose graphics processing unit including a dynamic precision floating point unit, the dynamic precision floating point unit including a control unit having precision tracking hardware logic to track the available number of precision bits of computational data associated with a target precision, wherein the dynamic precision floating point unit includes computational logic to output data at multiple precisions.

Description

Technical Field

[0001] Embodiments relate generally to data processing, and more particularly to data processing via a general purpose graphics processing unit. Background Art

[0002] Current parallel graphics data processing includes systems and methods developed to perform specific operations on graphics data, such as, for example, linear interpolation, tessellation, rasterization, texture mapping, depth testing, etc. Traditionally, graphics processors have used fixed-function compute units to process graphics data; however, more recently, portions of graphics processors have been made programmable, enabling such processors to support a wide variety of operations for processing vertex and fragment data.

[0003] To further increase performance, graphics processors typically implement processing techniques such as pipeline operations that attempt to process as much graphics data as possible in parallel throughout different parts of the graphics pipeline. Parallel graphics processors with a single instruction multiple thread (SIMT) architecture are designed to maximize the amount of parallel processing in the graphics pipeline. In a SIMT architecture, groups of parallel threads attempt to synchronize program instructions together as often as possible to increase processing efficiency. A general overview of software and hardware for a SIMT architecture can be found in Shane Cook's CUDA Programming, Chapter 3, pages 37-51 (2013) and / or Nicholas Wilt's CUDA Handbook, A Comprehensive Guide to GPU Programming, Sections 2.6.2 to 3.1.2 (June 2013). BRIEF DESCRIPTION OF THE DRAWINGS

[0004] A more particular description of the invention may be had by reference to embodiments so that the features of the invention may be understood in detail, some of which are shown in the accompanying drawings. It should be noted, however, that the drawings illustrate only typical embodiments and are therefore not to be considered limiting the scope of all embodiments.

[0005] Figure 1 is a block diagram illustrating a computer system configured to implement one or more aspects of the embodiments described herein.

[0006] Figures 2A-2D A parallel processor component according to an embodiment is shown.

[0007] Figure 3A-3B is a block diagram of a graphics multiprocessor according to an embodiment.

[0008] Figures 4A-4F An exemplary architecture is shown in which multiple GPUs are communicatively coupled to multiple multi-core processors.

[0009] Figure 5 A graphics processing pipeline according to an embodiment is shown.

[0010] Figure 6 A machine learning software stack according to an embodiment is shown.

[0011] Figure 7 A highly parallel general purpose graphics processing unit is shown in accordance with an embodiment.

[0012] Figure 8 A multi-GPU computing system is shown in accordance with an embodiment.

[0013] Figures 9A-9B The layers of an exemplary deep neural network are shown.

[0014] Fig.10 An exemplary recurrent neural network is shown.

[0015] Fig.11 Shown is the training and deployment of a deep neural network.

[0016] Fig.12 is a block diagram illustrating distributed learning.

[0017] Fig.13 An exemplary inference system-on-chip (SOC) suitable for performing inference using a trained model is shown.

[0018] Fig.14 Components of a dynamic precision floating point unit are shown in accordance with an embodiment.

[0019] Fig.15 Additional details are provided with respect to a dynamic precision floating point unit according to an embodiment.

[0020] Fig.16 Thread assignment for a dynamic precision processing system according to an embodiment is shown.

[0021] Fig.17 Logic is shown that performs numerical operations with less precision than required, according to an embodiment.

[0022] Fig.18 Loop vectorization of a SIMD unit according to an embodiment is shown.

[0023] Fig.19 A thread processing system according to an embodiment is shown.

[0024] Fig. 20 Logic for assigning threads for computations is shown in accordance with an embodiment.

[0025] Fig.21 A deep neural network 2100 is shown that can be processed using computational logic provided by embodiments described herein.

[0026] Fig. 22 is a block diagram of logic 2200 for preventing errors or significant loss of precision when performing low-precision operations for machine learning, according to an embodiment.

[0027] Fig.23 is a block diagram of a processing system according to an embodiment.

[0028] Fig.24 is a block diagram of an embodiment of a processor having one or more processor cores, an integrated memory controller, and an integrated graphics processor.

[0029] Fig.25 is a block diagram of a graphics processor, which may be a discrete graphics processing unit or may be a graphics processor integrated with multiple processing cores.

[0030] Fig.26 is a block diagram of a graphics processing engine of a graphics processor according to some embodiments.

[0031] Fig. 27 is a block diagram of a graphics processor provided by an additional embodiment.

[0032] Fig.28 Thread execution logic is shown including an array of processing elements employed in some embodiments.

[0033] Fig.29 is a block diagram illustrating a graphics processor instruction format according to some embodiments.

[0034] Fig.30 is a block diagram of a graphics processor according to another embodiment.

[0035] Figures 31A-31B A graphics processor command format and command sequence are shown according to some embodiments.

[0036] Fig.32 An exemplary graphics software architecture for a data processing system is shown in accordance with some embodiments.

[0037] Fig.33 is a block diagram illustrating an IP core development system according to an embodiment.

[0038] Fig.34 is a block diagram illustrating an exemplary system-on-chip integrated circuit according to an embodiment.

[0039] Fig.35 is a block diagram illustrating an additional graphics processor according to an embodiment.

[0040] Fig.36 is a block diagram illustrating an additional exemplary graphics processor of a system-on-chip integrated circuit according to an embodiment. DETAILED DESCRIPTION

[0041] In some embodiments, a graphics processing unit (GPU) is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. The GPU may be communicatively coupled to the host processor / core via a bus or another interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In other embodiments, the GPU may be integrated on the same package or chip as the core and communicatively coupled to the core via an internal processor bus / interconnect (i.e., inside the package or chip). Regardless of the manner in which the GPU is connected, the processor core may assign work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. The GPU then uses dedicated circuits / logic to efficiently process these commands / instructions.

[0042] In the following description, many specific details are set forth to provide a more thorough understanding. However, it will be apparent to those skilled in the art that the embodiments described herein may be practiced without one or more of these specific details. In other instances, well-known features are not described to avoid obscuring the details of embodiments of the invention.

[0043] System Overview

[0044] Figure 1 1 is a block diagram illustrating a computing system 100 configured to implement one or more aspects of the embodiments described herein. The computing system 100 includes a processing subsystem 101 having one or more processors 102 and a system memory 104 communicating via an interconnect path, which may include a memory hub 105. The memory hub 105 may be a separate component within a chipset component, or may be integrated within the one or more processors 102. The memory hub 105 is coupled to an I / O subsystem 111 via a communication link 106. The I / O subsystem 111 includes an I / O hub 107, which may enable the computing system 100 to receive input from one or more input devices 108. Additionally, the I / O hub 107 may enable a display controller to provide output to one or more display devices 110A, which may be included in the one or more processors 102. In one embodiment, the one or more display devices 110A coupled to the I / O hub 107 may include local, internal, or embedded display devices.

[0045] In one embodiment, the processing subsystem 101 includes one or more parallel processors 112, which are coupled to the memory hub 105 via a bus or other communication link 113. The communication link 113 can be one of any number of standard-based communication link technologies or protocols (such as but not limited to PCI Express), or can be a vendor-specific communication interface or communication structure. In one embodiment, the one or more parallel processors 112 form a parallel or vector processing system in a computational concentration, which includes a large number of processing cores and / or processing clusters, such as an integrated many-core (MIC) processor. In one embodiment, the one or more parallel processors 112 form a graphics processing subsystem, which can output pixels to one of the one or more display devices 110A coupled via the I / O hub 107. The one or more parallel processors 112 may also include a display controller and display interface (not shown) to enable direct connection to one or more display devices 110B.

[0046] Within the I / O subsystem 111, a system storage unit 114 may be connected to the I / O hub 107 to provide a storage mechanism for the computing system 100. An I / O switch 116 may be used to provide an interface mechanism to enable connection between the I / O hub 107 and other components that may be integrated into the platform, such as a network adapter 118 and / or a wireless network adapter 119, and various other devices that may be added via one or more plug-in devices 120. The network adapter 118 may be an Ethernet adapter or another wired network adapter. The wireless network adapter 119 may include one or more of the following: Wi-Fi, Bluetooth, near field communication (NFC), or other network devices including one or more radio devices.

[0047] The computing system 100 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to the I / O hub 107. Any suitable protocol may be used, such as a PCI (Peripheral Component Interconnect) based protocol (e.g., PCI-Express), or any other bus or point-to-point communication interface and / or protocol(s), such as NV-Link high-speed interconnect or interconnect protocols known in the art, to implement the I / O hub 107. Figure 1 The communication paths that interconnect the various components in a

[0048] In one embodiment, the one or more parallel processors 112 are combined with circuits optimized for graphics and video processing, including, for example, video output circuits, and constitute a graphics processing unit (GPU). In another embodiment, the one or more parallel processors 112 are combined with circuits optimized for general processing while maintaining the basic computing architecture described in more detail herein. In yet another embodiment, the components of the computing system 100 can be integrated with one or more other system elements on a single integrated circuit. For example, the one or more parallel processors 112, the memory hub 105, (multiple) processors 102, and the I / O hub 107 can be integrated into a system-on-chip (SoC) integrated circuit. Alternatively, the components of the computing system 100 can be integrated into a single package to form a system-in-package (SIP) configuration. In one embodiment, at least a portion of the components of the computing system 100 can be integrated into a multi-chip module (MCM), which can be interconnected with other multi-chip modules to form a modular computing system.

[0049] It will be appreciated that the computing system 100 shown herein is illustrative and variations and modifications are possible. The connection topology, including the number and arrangement of bridges, the number of (multiple) processors 102, and the number of (multiple) parallel processors 112, can be modified as desired. For example, in some embodiments, the system memory 104 is directly connected to the (multiple) processors 102 rather than through a bridge, while other devices communicate with the system memory 104 via the memory hub 105 and the (multiple) processors 102. In other alternative topologies, the (multiple) parallel processors 112 are connected to the I / O hub 107 or directly to one of the one or more processors 102, rather than to the memory hub 105. In other embodiments, the I / O hub 107 and the memory hub 105 can be integrated into a single chip. Some embodiments may include two or more sets of (multiple) processors 102 attached via multiple sockets, which can be coupled to two or more instances of (multiple) parallel processors 112.

[0050] Some of the specific components shown herein are optional and may not be included in all implementations of computing system 100. For example, any number of plug-in cards or peripherals may be supported, or some components may be eliminated. In addition, some architectures may use different terminology for components related to the computing system 100. Figure 1 For example, in some architectures memory hub 105 may be referred to as a north bridge, while I / O hub 107 may be referred to as a south bridge.

[0051] Figure 2A200 according to an embodiment. The various components of the parallel processor 200 may be implemented using one or more integrated circuit devices such as a programmable processor, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). According to an embodiment, the parallel processor 200 shown is Figure 1 A variation of the one or more parallel processors 112 shown in FIG.

[0052] In one embodiment, parallel processor 200 includes parallel processing unit 202. The parallel processing unit includes an I / O unit 204 that enables communication with other devices including other instances of parallel processing unit 202. I / O unit 204 can be directly connected to other devices. In one embodiment, I / O unit 204 is connected to other devices via the use of a hub or switch interface such as memory hub 105. The connection between memory hub 105 and I / O unit 204 forms communication link 113. Within parallel processing unit 202, I / O unit 204 is connected to host interface 206 and memory cross switch 216, wherein host interface 206 receives commands related to performing processing operations and memory cross switch 216 receives commands related to performing memory operations.

[0053] When the host interface 206 receives the command buffer via the I / O unit 204, the host interface 206 can direct the work operations for executing those commands to the front end 208. In one embodiment, the front end 208 is coupled with a scheduler 210, which is configured to distribute commands or other work items to the processing cluster array 212. In one embodiment, the scheduler 210 ensures that the processing cluster array 212 is properly configured and in a valid state before distributing tasks to the processing clusters of the processing cluster array 212. In one embodiment, the scheduler 210 is implemented via firmware logic executed on a microcontroller. The microcontroller-implemented scheduler 210 can be configured to perform complex scheduling and work distribution operations at coarse and fine granularity, thereby enabling context switching and rapid preemption of threads executed on the processing array 212. In one embodiment, the host software can check the workload for scheduling on the processing array 212 via one of a plurality of graphics processing doorbells. The workload can then be automatically distributed across the processing array 212 by the scheduler 210 logic within the scheduler microcontroller.

[0054] The processing cluster array 212 may include up to "N" processing clusters (e.g., cluster 214A, cluster 214B to cluster 214N). Each cluster 214A-214N of the processing cluster array 212 may execute a large number of concurrent threads. The scheduler 210 may use various scheduling and / or work distribution algorithms to allocate work to the clusters 214A-214N of the processing cluster array 212, which may vary depending on the workload generated by each type of program or calculation. Scheduling may be handled dynamically by the scheduler 210, or may be partially assisted by compiler logic during the compilation of program logic configured for execution by the processing cluster array 212. In one embodiment, different clusters 214A-214N of the processing cluster array 212 may be allocated to process different types of programs or to perform different types of calculations.

[0055] Processing cluster array 212 may be configured to perform various types of parallel processing operations. In one embodiment, processing cluster array 212 is configured to perform general-purpose parallel computing operations. For example, processing cluster array 212 may include logic for performing processing tasks including filtering of video and / or audio data, performing modeling operations including physical operations, and performing data transformations.

[0056] In one embodiment, the processing cluster array 212 is configured to perform parallel graphics processing operations. In embodiments where the parallel processor 200 is configured to perform graphics processing operations, the processing cluster array 212 may include additional logic for supporting the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations and tessellation logic and other vertex processing logic. In addition, the processing cluster array 212 may be configured to execute graphics processing related shader programs, such as but not limited to vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. The parallel processing unit 202 may transmit data from the system memory via the I / O unit 204 for processing. During processing, the transmitted data may be stored in an on-chip memory (e.g., parallel processor memory 222) during processing and then written back to the system memory.

[0057] In one embodiment, when parallel processing unit 202 is used to perform graphics processing, scheduler 210 can be configured to divide the processing workload into tasks of approximately equal size to better enable the distribution of graphics processing operations to multiple clusters 214A-214N of processing cluster array 212. In some embodiments, portions of processing cluster array 212 can be configured to perform different types of processing. For example, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen space operations to produce a rendered image for display. Intermediate data generated by one or more of clusters 214A-214N can be stored in a buffer to allow the intermediate data to be transferred between clusters 214A-214N for further processing.

[0058] During operation, the processing cluster array 212 may receive processing tasks to be executed via the scheduler 210, which receives commands defining the processing tasks from the front end 208. For graphics processing operations, a processing task may include an index of data to be processed, such as surface (patch) data, primitive data, vertex data, and / or pixel data, and state parameters and commands defining how the data is to be processed (e.g., what program to execute). The scheduler 210 may be configured to obtain an index corresponding to a task or may receive an index from the front end 208. The front end 208 may be configured to ensure that the processing cluster array 212 is configured to a valid state before a workload specified by an incoming command buffer (e.g., a batch buffer, a push buffer, etc.) is initiated.

[0059] Each of the one or more instances of the parallel processing unit 202 may be coupled to a parallel processor memory 222. The parallel processor memory 222 may be accessed via a memory crossbar 216, which may receive memory requests from the processing cluster array 212 and the I / O unit 204. The memory crossbar 216 may access the parallel processor memory 222 via a memory interface 218. The memory interface 218 may include a plurality of partition units (e.g., partition unit 220A, partition unit 220B to partition unit 220N), which may each be coupled to a portion (e.g., memory unit) of the parallel processor memory 222. In one implementation, the number of partition units 220A-220N is configured to be equal to the number of memory units, such that the first partition unit 220A has a corresponding first memory unit 224A, the second partition unit 220B has a corresponding memory unit 224B, and the Nth partition unit 220N has a corresponding Nth memory unit 224N. In other embodiments, the number of partition units 220A-220N may not be equal to the number of memory devices.

[0060] In various embodiments, the memory units 224A-224N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In one embodiment, the memory units 224A-224N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). Those skilled in the art will appreciate that the specific implementation of the memory units 224A-224N may vary and may be selected from one of a variety of conventional designs. Rendering targets such as frame buffers or texture maps may be stored across the memory units 224A-224N, thereby allowing the partition units 220A-220N to write portions of each rendering target in parallel to efficiently use the available bandwidth of the parallel processor memory 222. In some embodiments, local instances of the parallel processor memory 222 may be excluded to support a unified memory design that utilizes system memory together with local cache memory.

[0061] In one embodiment, any of the clusters 214A-214N of the processing cluster array 212 can process data to be written to any of the memory units 224A-224N within the parallel processor memory 222. The memory crossbar 216 can be configured to transmit the output of each cluster 214A-214N to any partition unit 220A-220N or another cluster 214A-214N, which can perform additional processing operations on the output. Each cluster 214A-214N can communicate with the memory interface 218 through the memory crossbar 216 to read from or write to various external memory devices. In one embodiment, the memory crossbar 216 has a connection to the memory interface 218 for communicating with the I / O unit 204, as well as a connection to a local instance of the parallel processor memory 222, so that the processing units within different processing clusters 214A-214N can communicate with the system memory or other memory that is not local to the parallel processing unit 202. In one embodiment, the memory crossbar switch 216 may use virtual channels to separate traffic flows between the clusters 214A-214N and the partition units 220A-220N.

[0062] Although a single instance of parallel processing unit 202 is shown in parallel processor 200, any number of instances of parallel processing unit 202 may be included. For example, multiple instances of parallel processing unit 202 may be provided on a single plug-in card, or multiple plug-in cards may be interconnected. Even if different instances of parallel processing unit 202 have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences, the different instances may be configured to interoperate. For example and in one embodiment, some instances of parallel processing unit 202 may include floating point units with higher precision relative to other instances. Systems incorporating one or more instances of parallel processing unit 202 or parallel processor 200 may be implemented in a variety of configurations and form factors, including but not limited to desktop computers, laptop computers or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0063] Figure 2B is a block diagram of a partition unit 220 according to an embodiment. In one embodiment, the partition unit 220 is Figure 2A2 is an example of one of the partition units 220A-220N of the memory. As shown, the partition unit 220 includes an L2 cache 221, a frame buffer interface 225, and an ROP 226 (raster operation unit). The L2 cache 221 is a read / write cache configured to perform load and store operations received from the memory crossbar switch 216 and the ROP 226. The L2 cache 221 outputs read misses and emergency write-back requests to the frame buffer interface 225 for processing. Updates may also be sent to the frame buffer via the frame buffer interface 225 for processing. In one embodiment, the frame buffer interface 225 interfaces with one of the memory units in the parallel processor memory, such as the memory units 224A-224N of FIG. 2 (e.g., within the parallel processor memory 222).

[0064] In graphics applications, ROP 226 is a processing unit that performs raster operations such as stencil, z-check, blending, etc. ROP 226 then outputs processed graphics data, which is stored in graphics memory. In some embodiments, ROP 226 includes compression logic to compress depth or color data written to memory and decompress depth or color data read from memory. The compression logic can be lossless compression logic that utilizes one or more of a variety of compression algorithms. The type of compression performed by ROP 226 can vary based on the statistical characteristics of the data to be compressed. For example, in one embodiment, delta color compression is performed on depth and color data on a per-tile basis.

[0065] In some embodiments, ROP 226 is included within each processing cluster (e.g., clusters 214A-214N of FIG. 2 ) rather than within partition unit 220. In such embodiments, read and write requests for pixel data rather than pixel fragment data are transmitted through memory crossbar 216. The processed graphics data may be displayed on a display device such as a Figure 1 100 ), routed for further processing by the processor(s) 102 , or routed for processing by the processor(s) 102 . Figure 2A The processing is further processed by one of the processing entities within parallel processor 200.

[0066] Figure 2C2 is a block diagram of a processing cluster 214 within a parallel processing unit according to an embodiment. In one embodiment, the processing cluster is an instance of one of the processing clusters 214A-214N of FIG. 2. The processing cluster 214 can be configured to execute multiple threads in parallel, wherein the term "thread" refers to an instance of a specific program executed on a set of specific input data. In some embodiments, a single instruction multiple data (SIMD) instruction issuance technique is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In other embodiments, a single instruction multiple thread (SIMT) technique is used to support the parallel execution of a large number of generally synchronized threads using a common instruction unit, and the common instruction unit is configured to issue instructions to a group of processing engines within each of the processing clusters. Unlike the SIMD execution regime in which all processing engines generally execute the same instruction, SIMT execution allows different threads to more easily follow divergent execution paths through a given thread program. It will be understood by those skilled in the art that the SIMD processing regime represents a functional subset of the SIMT processing regime.

[0067] The operation of the processing cluster 214 can be controlled via a pipeline manager 232 that distributes processing tasks to the SIMT parallel processor. The pipeline manager 232 receives instructions from the scheduler 210 of Figure 2 and manages the execution of those instructions via the graphics multiprocessor 234 and / or the texture unit 236. The graphics multiprocessor 234 shown is an exemplary instance of a SIMT parallel processor. However, various types of SIMT parallel processors of different architectures can be included in the processing cluster 214. One or more instances of the graphics multiprocessor 234 can be included in the processing cluster 214. The graphics multiprocessor 234 can process data, and the data crossbar switch 240 can be used to distribute the processed data to one of multiple possible destinations including other shader units. The pipeline manager 232 can promote the distribution of processed data by specifying a destination for the processed data to be distributed via the data crossbar switch 240.

[0068] Each graphics multiprocessor 234 within a processing cluster 214 may include a set of identical function execution logic (e.g., arithmetic logic units, load-store units, etc.). The function execution logic may be configured in a pipelined manner, where a new instruction may be issued before a previous instruction is completed. The function execution logic supports a variety of operations, including integer and floating point arithmetic, comparison operations, Boolean operations, shifts, and calculations of various algebraic functions. In one embodiment, the same functional unit hardware may be utilized to perform different operations, and any combination of functional units may be present.

[0069] The instructions transmitted to the processing cluster 214 constitute threads. A collection of threads executed across a collection of parallel processing engines is a thread group. A thread group executes the same program on different input data. Each thread within a thread group can be assigned to a different processing engine within the graphics multiprocessor 234. A thread group can include fewer threads than the number of processing engines within the graphics multiprocessor 234. When a thread group includes fewer threads than the number of processing engines, one or more of the processing engines may be idle during the cycle in which the thread group is processed. A thread group can also include more threads than the number of processing engines within the graphics multiprocessor 234. When a thread group includes more threads than the number of processing engines within the graphics multiprocessor 234, processing can be performed in consecutive clock cycles. In one embodiment, multiple thread groups can be executed simultaneously on the graphics multiprocessor 234.

[0070] In one embodiment, the graphics multiprocessor 234 includes an internal cache memory for performing load and store operations. In one embodiment, the graphics multiprocessor 234 can abandon the internal cache and use the cache memory (e.g., L1 cache 308) within the processing cluster 214. Each graphics multiprocessor 234 is also able to access the L2 cache within the partition unit (e.g., partition unit 220A-220N of Figure 2) that is shared between all processing clusters 214 and can be used to transfer data between threads. The graphics multiprocessor 234 can also access off-chip global memory, which can include one or more of the local parallel processor memory and / or system memory. Any memory external to the parallel processing unit 202 can be used as global memory. In which the processing cluster 214 includes multiple instances of the graphics multiprocessor 234, embodiments can share common instructions and data that can be stored in the L1 cache 308.

[0071] Each processing cluster 214 may include an MMU 245 (memory management unit) configured to map virtual addresses to physical addresses. In other embodiments, one or more instances of the MMU 245 may reside within the memory interface 218 of FIG. 2 . The MMU 245 includes a set of page table entries (PTEs) for mapping virtual addresses to physical addresses of tiles (more on blocking) and optionally to cache line indexes. The MMU 245 may include an address translation lookaside buffer (TLB) or cache that may reside within the graphics multiprocessor 234 or L1 cache or processing cluster 214. Physical addresses are processed to distribute surface data access locality to allow efficient request interleaving between partition units. The cache line index may be used to determine whether a request for a cache line is a hit or a miss.

[0072] In graphics and computing applications, the processing clusters 214 can be configured such that each graphics multiprocessor 234 is coupled to a texture unit 236 for performing texture mapping operations, such as determining texture sample locations, reading texture data, and filtering texture data. Texture data is read from an internal texture L1 cache (not shown) or in some embodiments from an L1 cache within the graphics multiprocessor 234 and retrieved from an L2 cache, local parallel processor memory, or system memory as needed. Each graphics multiprocessor 234 outputs a processed task to a data crossbar 240 to provide the processed task to another processing cluster 214 for further processing or to store the processed task in an L2 cache, local parallel processor memory, or system memory via a memory crossbar 216. A preROP 242 (pre-raster operation unit) is configured to receive data from the graphics multiprocessor 234, directing the data to a ROP unit, which may be located with a partition unit (e.g., partition units 220A-220N of FIG. 2 ) as described herein. The preROP 242 unit may perform optimizations for color blending, organize pixel color data, and perform address translations.

[0073] It will be appreciated that the core architecture described herein is illustrative and variations and modifications are possible. Any number of processing units, such as graphics multiprocessors 234, texture units 236, preROPs 242, etc., may be included within a processing cluster 214. Further, while only one processing cluster 214 is shown, a parallel processing unit as described herein may include any number of instances of a processing cluster 214. In one embodiment, each processing cluster 214 may be configured to operate independently of other processing clusters 214 using separate and distinct processing units, L1 caches, etc.

[0074] Figure 2D A graphics multiprocessor 234 is shown according to one embodiment. In such embodiments, the graphics multiprocessor 234 is coupled to a pipeline manager 232 of a processing cluster 214. The graphics multiprocessor 234 has an execution pipeline that includes, but is not limited to, an instruction cache 252, an instruction unit 254, an address mapping unit 256, a register file 258, one or more general purpose graphics processing unit (GPGPU) cores 262, and one or more load / store units 266. The GPGPU cores 262 and the load / store units 266 are coupled to a cache memory 272 and a shared memory 270 via a memory and cache interconnect 268.

[0075] In one embodiment, the instruction cache 252 receives an instruction stream to be executed from the pipeline manager 232. The instructions are cached in the instruction cache 252 and dispatched for execution by the instruction unit 254. The instruction unit 254 can dispatch instructions into thread groups (e.g., warps), where each thread of the thread group is assigned to a different execution unit within the GPGPU core 262. Instructions can access any address space in the local, shared, or global address space by specifying an address within the unified address space. The address mapping unit 256 can be used to convert addresses in the unified address space into different memory addresses that can be accessed by the load / store unit 266.

[0076] The register file 258 provides a set of registers for the functional units of the graphics multiprocessor 324. The register file 258 provides temporary storage for operands for the data paths of the functional units (e.g., GPGPU core 262, load / store unit 266) connected to the graphics multiprocessor 324. In one embodiment, the register file 258 is divided between each of the functional units so that each functional unit is assigned a dedicated portion of the register file 258. In one embodiment, the register file 258 is divided between different warps being executed by the graphics multiprocessor 324.

[0077] The GPGPU cores 262 may each include a floating point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions of the graphics multiprocessor 324. Depending on the embodiment, the GPGPU cores 262 may be similar in architecture, or may be different in architecture. For example and in one embodiment, the first portion of the GPGPU core 262 includes a single-precision FPU and an integer ALU, while the second portion of the GPGPU core includes a double-precision FPU. In one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point arithmetic or enable variable-precision floating-point arithmetic. The graphics multiprocessor 324 may additionally include one or more fixed-function or special-function units to perform specific functions such as copying rectangles or pixel blending operations. In one embodiment, one or more of the GPGPU cores may also include fixed or special-function logic.

[0078] In one embodiment, the GPGPU core 262 includes SIMD logic capable of executing a single instruction to multiple sets of data. In one embodiment, the GPGPU core 262 can physically execute SIMD4, SIMD8 and SIMD16 instructions, and logically execute SIMD1, SIMD2 and SIMD32 instructions. SIMD instructions for the GPGPU core can be generated by the shader compiler at compile time, or can be automatically generated when executing a program written and compiled for a single program multiple data (SPMD) or SIMT architecture. Multiple threads of a program configured for a SIMT execution model can be executed via a single SIMD instruction. For example and in one embodiment, eight SIMT threads performing the same or similar operation can be executed in parallel via a single SIMD8 logic unit.

[0079] The memory and cache interconnect 268 is an interconnect network that connects each of the functional units of the graphics multiprocessor 324 to the register file 258 and the shared memory 270. In one embodiment, the memory and cache interconnect 268 is a crossbar interconnect that allows the load / store unit 266 to implement load and store operations between the shared memory 270 and the register file 258. The register file 258 can operate at the same frequency as the GPGPU core 262, so data transfers between the GPGPU core 262 and the register file 258 have very low latency. The shared memory 270 can be used to enable communication between threads executing on the functional units within the graphics multiprocessor 234. For example, the cache memory 272 can be used as a data cache to cache texture data transferred between the functional units and the texture unit 236. The shared memory 270 can also be used as a cached managed program. In addition to the automatically cached data stored in the cache memory 272, threads executing on the GPGPU core 262 can also programmatically store data in the shared memory.

[0080] Figure 3A-3B Additional graphics multiprocessors are shown according to an embodiment. The graphics multiprocessors 325, 350 shown are Figure 2C The illustrated graphics multiprocessors 325, 350 may be configured as streaming multiprocessors (SMs) capable of executing a large number of execution threads simultaneously.

[0081] Figure 3A A graphics multiprocessor 325 is shown according to an additional embodiment. The graphics multiprocessor 325 includes Figure 2DThe graphics multiprocessor 325 may include multiple additional instances of execution resource units associated with the graphics multiprocessor 234. For example, the graphics multiprocessor 325 may include multiple instances of instruction units 332A-332B, register files 334A-334B, and (multiple) texture units 344A-344B. The graphics multiprocessor 325 also includes multiple groups of graphics or compute execution units (e.g., GPGPU cores 336A-336B, GPGPU cores 337A-337B, GPGPU cores 338A-338B) and multiple groups of load / store units 340A-340B. In one embodiment, the execution resource units have a common instruction cache 330, texture and / or data cache memory 342, and shared memory 346.

[0082] The various components may communicate via the interconnect structure 327. In one embodiment, the interconnect structure 327 includes one or more crossbar switches to enable communication between the various components of the graphics multiprocessor 325. In one embodiment, the interconnect structure 327 is a separate high-speed network fabric layer on which each component of the graphics multiprocessor 325 is stacked. The components of the graphics multiprocessor 325 communicate with remote components via the interconnect structure 327. For example, the GPGPU cores 336A-336B, 337A-337B, and 3378A-338B may each communicate with the shared memory 346 via the interconnect structure 327. The interconnect structure 327 may arbitrate communications within the graphics multiprocessor 325 to ensure fair bandwidth allocation between components.

[0083] Figure 3B FIG. 3 shows a graphics multiprocessor 350 according to an additional embodiment. The graphics processor includes multiple sets of execution resources 356A-356D, wherein each set of execution resources includes multiple instruction units, register files, GPGPU cores, and load storage units, such as Figure 2D and Figure 3A . Execution resources 356A-356D may work in concert with texture unit(s) 360A-360D for texture operations while sharing instruction cache 354 and shared memory 362. In one embodiment, execution resources 356A-356D may share instruction cache 354 and shared memory 362 as well as multiple instances of texture and / or data caches 358A-358B. Various components may be communicated with via Figure 3A The interconnect structure 327 communicates with a similar interconnect structure 352 .

[0084] Those skilled in the art will understand that Figure 1 , 2AThe architectures described in Figures 2-2D and 3A-3B are illustrative and non-limiting with respect to the scope of embodiments of the present invention. Thus, the techniques described herein may be implemented on any appropriately configured processing unit, including but not limited to one or more mobile application processors, one or more desktop computer or server central processing units (CPUs) (including multi-core CPUs), one or more parallel processing units (such as parallel processing unit 202 of Figure 2), and one or more graphics processors or special purpose processing units, without departing from the scope of the embodiments described herein.

[0085] In some embodiments, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. The GPU can be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In other embodiments, the GPU can be integrated on the same package or chip as the core and communicatively coupled to the core via an internal processor bus / interconnect (i.e., inside the package or chip). Regardless of the manner in which the GPU is connected, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. The GPU then uses dedicated circuits / logic to efficiently process these commands / instructions.

[0086] Technologies for GPU to host processor interconnect

[0087] Figure 4A An exemplary architecture is shown in which multiple GPUs 410-413 are communicatively coupled to multiple multi-core processors 405-406 via high-speed links 440-443 (e.g., buses, point-to-point interconnects, etc.). In one embodiment, the high-speed links 440-443 support 4GB / s, 30GB / s, 80GB / s, or higher communication throughput, depending on the implementation. Various interconnect protocols may be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. However, the underlying principles of the invention are not limited to any particular communication protocol or throughput.

[0088] Additionally, in one embodiment, two or more of the GPUs 410-413 are interconnected via high-speed links 444-445, which may be implemented using the same or different protocols / links as those used for high-speed links 440-443. Similarly, two or more of the multi-core processors 405-406 may be connected via high-speed link 433, which may be a symmetric multiprocessor (SMP) bus operating at 20 GB / s, 30 GB / s, 120 GB / s, or higher. Alternatively, Figure 4A All communications between the various system components shown in can be accomplished using the same protocol / links (eg, through a common interconnect structure). However, as mentioned, the underlying principles of the invention are not limited to any particular type of interconnect technology.

[0089] In one embodiment, each multi-core processor 405-406 is communicatively coupled to processor memory 401-402 via memory interconnects 430-431, respectively, and each GPU 410-413 is communicatively coupled to GPU memory 420-423 via GPU memory interconnects 450-453, respectively. Memory interconnects 430-431 and 450-453 may utilize the same or different memory access technologies. By way of example and not limitation, processor memory 401-402 and GPU memory 420-423 may be volatile memory, such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or may be non-volatile memory, such as 3D XPoint or Nano-Ram. In one embodiment, a portion of the memory may be volatile memory and another portion may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0090] As described below, although the various processors 405-406 and GPUs 410-413 may be physically coupled to specific memories 401-402, 420-423, respectively, a unified memory architecture may be implemented in which the same virtual system address space (also referred to as an "effective address" space) is distributed among all of the various physical memories. For example, the processor memories 401-402 may each include 64GB of system memory address space, and the GPU memories 420-423 may each include 32GB of system memory address space (resulting in a total of 256GB of addressable memory in this example).

[0091] Figure 4B Additional details of the interconnection between the multi-core processor 407 and the graphics acceleration module 446 according to one embodiment are shown. The graphics acceleration module 446 may include one or more GPU chips integrated on a line card coupled to the processor 407 via the high-speed link 440. Alternatively, the graphics acceleration module 446 may be integrated on the same package or chip as the processor 407.

[0092] The processor 407 shown includes multiple cores 460A-460D, each with a translation lookaside buffer 461A-461D and one or more caches 462A-462D. The core may include various other components for executing instructions and processing data (e.g., instruction fetch unit, branch prediction unit, decoder, execution unit, reorder buffer, etc.), which are not shown to avoid obscuring the basic principles of the present invention. Caches 462A-462D may include level 1 (L1) and level 2 (L2) caches. In addition, one or more shared caches 426 may be included in the cache hierarchy and shared by a collection of cores 460A-460D. For example, one embodiment of the processor 407 includes 24 cores, each with its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, one of the L2 cache and the L3 cache is shared by two adjacent cores. The processor 407 and the graphics accelerator integrated module 446 are connected to the system memory 441, which may include the processor memories 401-402.

[0093] Coherence is maintained for data and instructions stored in the various caches 462A-462D, 456, and the system memory 441 via inter-core communications over the coherence bus 464. For example, each cache may have cache coherence logic / circuitry associated therewith to communicate over the coherence bus 464 in response to a detected read or write to a particular cache line. In one implementation, a cache snooping protocol is implemented over the coherence bus 464 to snoop on cache accesses. Cache snooping / coherence techniques are well understood by those skilled in the art and will not be described in detail here to avoid obscuring the underlying principles of the present invention.

[0094] In one embodiment, the proxy circuit 425 communicatively couples the graphics acceleration module 446 to the coherence bus 464, thereby allowing the graphics acceleration module 446 to participate in the cache coherence protocol as a peer of the core. Specifically, the interface 435 provides connectivity to the proxy circuit 425 via a high-speed link 440 (e.g., a PCIe bus, NVLink, etc.), and the interface 437 connects the graphics acceleration module 446 to the high-speed link 440.

[0095] In one implementation, the accelerator integrated circuit 436 provides cache management, memory access, context management, and interrupt management services on behalf of the multiple graphics processing engines 431, 432, N of the graphics acceleration module 446. The graphics processing engines 431, 432, N may each include a separate graphics processing unit (GPU). Alternatively, the graphics processing engines 431, 432, N may include different types of graphics processing engines within the GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a bit block transfer engine. In other words, the graphics acceleration module may be a GPU having multiple graphics processing engines 431-432, N, or the graphics processing engines 431-432, N may be separate GPUs integrated on a common package, line card, or chip.

[0096] In one embodiment, the accelerator integrated circuit 436 includes a memory management unit (MMU) 439 for performing various memory management functions such as virtual to physical memory translation (also known as effective to real memory translation) and memory access protocols for accessing the system memory 441. The MMU 439 may also include a translation lookaside buffer (TLB) (not shown) for caching virtual / effective to physical / actual address translations. In one implementation, the cache 438 stores commands and data for efficient access by the graphics processing engines 431-432, N. In one embodiment, the data stored in the cache 438 and the graphics memory 433-434, N is kept consistent with the core caches 462A-462D, 456 and the system memory 411. As mentioned, this may be accomplished via proxy circuitry 425, which participates in cache coherence mechanisms on behalf of cache 438 and memories 433-434, N (e.g., sending updates to cache 438 related to modifications / accesses of cache lines on processor caches 462A-462D, 456 and receiving updates from cache 438).

[0097] A set of registers 445 stores context data for threads executed by the graphics processing engines 431-432, N, and context management circuitry 448 manages thread contexts. For example, context management circuitry 448 may perform save and restore operations to save and restore contexts for various threads during context switches (e.g., where a first thread is saved and a second thread is stored so that the second thread can be executed by the graphics processing engine). For example, upon context switching, context management circuitry 448 may store current register values ​​to a specified area in memory (e.g., identified by a context pointer). It may then restore the register values ​​upon returning to that context. In one embodiment, interrupt management circuitry 447 receives and processes interrupts received from system devices.

[0098] In one implementation, the virtual / effective address from the graphics processing engine 431 is converted into a real / physical address in the system memory 411 by the MMU 439. One embodiment of the accelerator integrated circuit 436 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 446 and / or other accelerator devices. The graphics accelerator module 446 can be dedicated to a single application executed on the processor 407, or can be shared between multiple applications. In one embodiment, a virtualized graphics execution environment is presented, in which the resources of the graphics processing engines 431-432, N are shared with multiple applications or virtual machines (VMs). Resources can be subdivided into "slices", which are allocated to different VMs and / or applications based on the processing requirements and priorities associated with the VMs and / or applications.

[0099] Thus, the accelerator integrated circuit acts as a bridge to the system of the graphics acceleration module 446 and provides address translation and system memory cache services. In addition, the accelerator integrated circuit 436 can provide virtualization facilities for the host processor to manage virtualization of the graphics processing engine, interrupts, and memory management.

[0100] Because the hardware resources of the graphics processing engines 431-432, N are explicitly mapped to the actual address space seen by the host processor 407, any host processor can directly address these resources using effective address values. In one embodiment, one function of the accelerator integrated circuit 436 is the physical separation of the graphics processing engines 431-432, N so that they appear as independent units to the system.

[0101] As mentioned, in the illustrated embodiment, one or more graphics memories 433-434, M are respectively coupled to each of the graphics processing engines 431-432, N. The graphics memories 433-434, M store instructions and data being processed by each of the graphics processing engines 431-432, N. The graphics memories 433-434, M may be volatile memory, such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or may be non-volatile memory, such as 3D XPoint or Nano-Ram.

[0102] In one embodiment, in order to reduce data traffic on the high-speed link 440, biasing techniques are used to ensure that the data stored in the graphics memories 433-434, M is data that will be used most frequently by the graphics processing engines 431-432, N and that is preferably not used (at least not frequently) by the cores 460A-460D. Similarly, the biasing mechanism attempts to keep data needed by the cores (and preferably not the graphics processing engines 431-432, N) within the cores' caches 462A-462D, 456 and system memory 411.

[0103] Figure 4C Another embodiment is shown in which an accelerator integrated circuit 436 is integrated within the processor 407. In this embodiment, the graphics processing engines 431-432, N communicate directly with the accelerator integrated circuit 436 via the interface 437 and the interface 435 (again, which can utilize any form of bus or interface protocol) through the high-speed link 440. The accelerator integrated circuit 436 can perform operations related to Figure 4B The operations are the same as those described, but given their close proximity to the coherency bus 462 and caches 462A-462D, 426, the operations may be performed at a higher throughput.

[0104] One embodiment supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization). The shared programming model may include a programming model controlled by accelerator integrated circuit 436 and a programming model controlled by graphics acceleration module 446.

[0105] In one embodiment of a dedicated process model, graphics processing engines 431-432, N are dedicated to a single application or process under a single operating system. The single application can funnel other application requests to graphics engines 431-432, N, thereby providing virtualization within a VM / partition.

[0106] In a dedicated process programming model, graphics processing engines 431-432, N can be shared by multiple VM / application partitions. The shared model requires the system hypervisor to virtualize graphics processing engines 431-432, N to allow access by each operating system. For a single partition system without a hypervisor, graphics processing engines 431-432, N are owned by the operating system. In both cases, the operating system can virtualize graphics processing engines 431-432, N to provide access to each process or application.

[0107] For the shared programming model, the graphics acceleration module 446 or the separate graphics processing engines 431-432, N use the process handle to select a process element. In one embodiment, the process element is stored in the system memory 411 and can be addressed using the effective address to real address conversion technology described herein. The process handle can be an implementation-specific value provided to the host process when registering its context with the graphics processing engine 431-432, N (i.e., calling the system software to add a process element to the process element linked list). The lower 16 bits of the process handle can be the offset of the process element within the process element linked list.

[0108] Figure 4D An exemplary accelerator integrated slice 490 is shown. As used herein, a "slice" includes a specified portion of the processing resources of the accelerator integrated circuit 436. The application effective address space 482 within the system memory 411 stores process elements 483. In one embodiment, the process element 483 is stored in response to a GPU call 481 from an application 480 executed on the processor 407. The process element 483 contains a process state for the corresponding application 480. The work descriptor (WD) 484 contained in the process element 483 can be a single job requested by the application, or it can contain a pointer to a job queue. In the latter case, the WD 484 is a pointer to the job request queue in the address space 482 of the application.

[0109] Graphics acceleration module 446 and / or individual graphics processing engines 431-432, N may be shared by all or a subset of processes in the system. Embodiments of the present invention include an infrastructure for establishing process state and sending WD 484 to graphics acceleration module 446 to start a job in a virtualized environment.

[0110] In one implementation, the dedicated process programming model is implementation specific. In this model, a single process owns the graphics acceleration module 446 or a separate graphics processing engine 431. Because the graphics acceleration module 446 is owned by a single process, the hypervisor initializes the accelerator integrated circuit 436 for the owning partition, and the operating system initializes the accelerator integrated circuit 436 for the owning process when the graphics acceleration module 446 is assigned.

[0111] In operation, the WD acquisition unit 491 in the accelerator integrated slice 490 acquires the next WD 484, which includes an indication of the work to be completed by one of the graphics processing engines of the graphics acceleration module 446. The data from the WD 484 can be stored in the register 445 and used by the MMU 439, the interrupt management circuit 447, and / or the context management circuit 448 as shown. For example, one embodiment of the MMU 439 includes a segment / page walk circuitry for accessing the segment / page table 486 within the OS virtual address space 485. The interrupt management circuit 447 can handle the interrupt event 492 received from the graphics acceleration module 446. When performing graphics operations, the effective address 493 generated by the graphics processing engine 431-432, N is converted into an actual address by the MMU 439.

[0112] In one embodiment, the same set of registers 445 is replicated for each graphics processing engine 431-432, N, and / or graphics acceleration module 446 and can be initialized by a hypervisor or operating system. Each of these replicated registers can be included in an accelerator integrated slice 490. Exemplary registers that can be initialized by a hypervisor are shown in Table 1.

[0113] Table 1 - Registers initialized by the hypervisor

[0114] 1 Slice Control Register 2 Real Address (RA) dispatched process area pointer 3 Permission Mask Override Register 4 Interrupt vector table entry offset 5 Interrupt Vector Table Entry Limits 6 Status Register 7 Logical Partition ID 8 Real Address (RA) Manager Accelerator Utilizes Record Pointers 9 Storage Description Register

[0115] Example registers that may be initialized by the operating system are shown in Table 2.

[0116] Table 2 - Registers initialized by the operating system

[0117] 1 Process and thread identities 2 Effective Address (EA) context save / restore pointer 3 Virtual Address (VA) Accelerator Utilizes Record Pointers 4 Virtual Address (VA) Segment Table Pointer 5 Permission masking 6 Job Descriptor

[0118] In one embodiment, each WD 484 is specific to a particular graphics acceleration module 446 and / or graphics processing engine 431-432, N. It contains all the information needed for the graphics processing engine 431-432, N to do its work, or it may be a pointer to a memory location of a command queue where the application has set up work to be done.

[0119] Figure 4E Additional details of one embodiment of the sharing model are shown. This embodiment includes a hypervisor real address space 498 in which a process element list 499 is stored. The hypervisor real address space 498 is accessible via a hypervisor 496 that virtualizes a graphics acceleration module engine for an operating system 495.

[0120] The shared programming model allows all or a subset of processes from all or a subset of partitions in the system to use the graphics acceleration module 446. There are two programming models where the graphics acceleration module 446 is shared by multiple processes and partitions: time-sliced ​​sharing and graphics-directed sharing.

[0121] In this model, the hypervisor 496 owns the graphics acceleration module 446 and makes its functionality available to all operating systems 495. In order for the graphics acceleration module 446 to support virtualization by the hypervisor 496, the graphics acceleration module 446 may adhere to the following requirements: 1) The application's job request must be autonomous (i.e., no state needs to be maintained between jobs), or the graphics acceleration module 446 must provide a context save and restore mechanism. 2) The graphics acceleration module 446 guarantees that the application's job request is completed within a specified amount of time, including any transition failures, or the graphics acceleration module 446 provides the ability to preempt processing of jobs. 3) When operating in a directed sharing programming model, fairness of the graphics acceleration module 446 must be guaranteed between processes.

[0122] In one embodiment, for the shared model, the application 480 is required to make an operating system 495 system call using a graphics acceleration module 446 type, a work descriptor (WD), an authority mask register (AMR) value, and a context save / restore region pointer (CSRP). The graphics acceleration module 446 type describes the target acceleration function for the system call. The graphics acceleration module 446 type can be a system-specific value. The WD is formatted specifically for the graphics acceleration module 446 and can take the following forms: a graphics acceleration module 446 command, an effective address pointer to a user-defined structure, an effective address pointer to a command queue, or any other data structure used to describe the work to be done by the graphics acceleration module 446. In one embodiment, the AMR value is the AMR state for the current process. The value passed to the operating system is similar to the application that sets the AMR. If the implementation of the accelerator integrated circuit 436 and the graphics acceleration module 446 does not support the user authority mask override register (UAMOR), the operating system can apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. The hypervisor 496 may optionally apply the current permission mask overlay register (AMOR) value before placing the AMR in the process element 483. In one embodiment, the CSRP is one of the registers 445 that contains the effective address of an area in the application's address space 482 for the graphics acceleration module 446 to save and restore context state. This pointer is optional if state is not required to be saved between jobs or when a job is preempted. The context save / restore area may be pinned system memory.

[0123] Upon receiving the system call, the operating system 495 can verify that the application 480 has been registered and given permission to use the graphics acceleration module 446. The operating system 495 then calls the hypervisor 496 using the information shown in Table 3.

[0124] Table 3 - OS to hypervisor call parameters

[0125] 1 Job Descriptor (WD) 2 The (possibly masked) permission mask register (AMR) value 3 Effective Address (EA) Context Save / Restore Region Pointer (CSRP) 4 Process ID (PID) and optional thread ID (TID) 5 Virtual Address (VA) Accelerator Utilization Record Pointer (AURP) 6 Virtual address of the storage segment table pointer (SSTP) 7 Logical Interrupt Service Number (LISN)

[0126] Upon receiving the hypervisor call, the hypervisor 496 verifies that the operating system 495 has registered and been given permission to use the graphics acceleration module 446. The hypervisor 496 then places the process element 483 into a linked list of process elements for the corresponding type of graphics acceleration module 446. The process element may include the information shown in Table 4.

[0127] Table 4 - Process element information

[0128] 1 Job Descriptor (WD) 2 The (possibly masked) permission mask register (AMR) value 3 Effective Address (EA) Context Save / Restore Region Pointer (CSRP) 4 Process ID (PID) and optional thread ID (TID) 5 Virtual Address (VA) Accelerator Utilization Record Pointer (AURP) 6 Virtual address of the storage segment table pointer (SSTP) 7 Logical Interrupt Service Number (LISN) 8 Interrupt vector table derived from hypervisor call parameters 9 Status Register (SR) Value 10 Logical Partition ID (LPID) 11 Real Address (RA) Manager Accelerator Utilizes Record Pointers 12 Storage Descriptor Register (SDR)

[0129] In one embodiment, the hypervisor initializes the plurality of accelerator integrated slice 490 registers 445 .

[0130] like Figure 4F As shown in , one embodiment of the present invention employs a unified memory addressable via a common virtual memory address space for accessing physical processor memory 401-402 and GPU memory 420-423. In this implementation, operations executed on GPUs 410-413 utilize the same virtual / effective memory address space to access processor memory 401-402, and vice versa, thereby simplifying programmability. In one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 401, a second portion is allocated to second processor memory 402, a third portion is allocated to GPU memory 420, and so on. The entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of processor memory 401-402 and GPU memory 420-423, allowing any processor or GPU to access the memory using a virtual address mapped to any physical memory.

[0131] In one embodiment, bias / coherency management circuits 494A-494E within one or more of MMUs 439A-439E ensure cache coherency between caches of a host processor (e.g., 405) and GPUs 410-413 and implement biasing techniques that indicate physical memory where certain types of data should be stored. Figure 4FMultiple instances of bias / consistency management circuits 494A- 494E are shown in , but bias / consistency circuits may be implemented within an MMU of one or more host processors 405 and / or within an accelerator integrated circuit 436 .

[0132] One embodiment allows the GPU-attached memory 420-423 to be mapped as part of the system memory and accessed using shared virtual memory (SVM) technology, but without suffering from the typical performance drawbacks associated with full system cache coherence. The ability of the GPU-attached memory 420-423 to be accessed as system memory without heavy cache coherence overhead provides a favorable operating environment for GPU offloading. This arrangement allows the host processor 405 software to set operands and access calculation results without the overhead of traditional I / O DMA data copying. Such traditional copies involve driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, which are all inefficient relative to simple memory accesses. At the same time, the ability to access the GPU-attached memory 420-423 without cache coherence overhead may be critical to the execution time of the offloaded calculation. For example, in the case of a large number of streaming write memory services, the cache coherence overhead can significantly reduce the effective write bandwidth seen by the GPU 410-413. The efficiency of operand setup, the efficiency of result access, and the efficiency of GPU calculation all play a role in determining the effectiveness of GPU offloading.

[0133] In one implementation, the selection between GPU bias and host processor bias is driven by a bias tracker data structure. For example, a bias table may be used, which may be a page granular structure that includes 1 or 2 bits per GPU attached memory page (i.e., controlled at the granularity of a memory page). The bias table may be implemented in the stolen memory range of one or more GPU attached memories 420-423, with or without a bias cache in the GPUs 410-413 (e.g., to cache frequently / recently used entries of the bias table). Alternatively, the entire bias table may be maintained within the GPU.

[0134] In one implementation, the bias table entry associated with each access to the GPU attached memory 420-423 is accessed before the actual access to the GPU memory, resulting in the following operations. First, local requests from GPUs 410-413 whose pages are found in the GPU bias are forwarded directly to the corresponding GPU memory 420-423. Local requests from GPUs whose pages are found in the host bias are forwarded to processor 405 (e.g., via a high-speed link as discussed above). In one embodiment, requests from processor 405 to find the requested page in the host processor bias complete the request like a normal memory read. Alternatively, requests involving GPU bias pages can be forwarded to GPUs 410-413. If the GPU is not currently using the page, the GPU can then convert the page to the host processor bias.

[0135] The bias state of a page may be changed by a software-based mechanism, a hardware-assisted software-based mechanism, or, for a limited set of cases, a purely hardware-based mechanism.

[0136] One mechanism for changing the bias state employs an API call (e.g., OpenCL) which in turn calls the GPU's device driver which in turn sends a message (or queues a command descriptor) to the GPU directing it to change the bias state and, for certain transitions, performs a cache flush operation in the host. The cache flush operation is required for transitions from host processor 405 bias to GPU bias, but not the other way around.

[0137] In one embodiment, cache coherency is maintained by temporarily rendering GPU bias pages uncacheable by host processor 405. To access these pages, processor 405 may request access from GPU 410, which may or may not immediately grant access, depending on the implementation. Therefore, to reduce communication between processor 405 and GPU 410, it is advantageous to ensure that GPU bias pages are those pages that are needed by the GPU but not by the host processor 405, and vice versa.

[0138] Graphics processing pipeline

[0139] Figure 5 2 . A graphics processing pipeline 500 is shown according to an embodiment. In one embodiment, a graphics processor may implement the illustrated graphics processing pipeline 500. The graphics processor may be included in a parallel processing subsystem as described herein (such as parallel processor 200 of FIG. 2 ), which in one embodiment is Figure 1A variation of the parallel processor(s) 112 of FIG. Various parallel processing systems may implement the graphics processing pipeline 500 via one or more instances of a parallel processing unit (e.g., parallel processing unit 202 of FIG. 2 ) as described herein. For example, a shader unit (e.g., graphics multiprocessor 234 of FIG. 3 ) may be configured to perform the functions of one or more of a vertex processing unit 504, a tessellation control processing unit 508, a tessellation evaluation processing unit 512, a geometry processing unit 516, and a fragment / pixel processing unit 524. The functions of the data assembler 502, primitive assemblers 506, 514, 518, tessellation unit 510, rasterizer 522, and raster operation unit 526 may also be performed by other processing engines within a processing cluster (e.g., processing cluster 214 of FIG. 3 ) and corresponding partition units (e.g., partition units 220A-220N of FIG. 2 ). The graphics processing pipeline 500 may also be implemented using dedicated processing units for one or more functions. In one embodiment, one or more portions of the graphics processing pipeline 500 may be executed by parallel processing logic within a general purpose processor (e.g., a CPU). In one embodiment, one or more portions of the graphics processing pipeline 500 may access on-chip memory (e.g., such as parallel processor memory 222 in FIG. 2 ) via a memory interface 528 , which may be an example of the memory interface 218 of FIG. 2 .

[0140] In one embodiment, data assembler 502 is a processing unit that collects vertex data for surfaces and primitives. Data assembler 502 then outputs vertex data including vertex attributes to vertex processing unit 504. Vertex processing unit 504 is a programmable execution unit that executes vertex shader programs, thereby performing lighting and transformation on vertex data as specified by the vertex shader programs. Vertex processing unit 504 reads data stored in cache, local or system memory for use in processing vertex data, and can be programmed to transform vertex data from an object-based coordinate representation to a world space coordinate space or a normalized device coordinate space.

[0141] A first instance of primitive assembler 506 receives vertex attributes from vertex processing unit 504. Primitive assembler 506 reads the stored vertex attributes as needed and constructs graphics primitives for processing by tessellation control processing unit 508. Graphics primitives include triangles, line segments, points, patches, etc. as supported by various graphics processing application programming interfaces (APIs).

[0142] The tessellation control processing unit 508 treats the input vertices as control points for a geometric patch. The control points are transformed from an input representation from the patch (e.g., a basis for the patch) into a representation suitable for use in a surface evaluation performed by the tessellation evaluation processing unit 512. The tessellation control processing unit 508 may also calculate tessellation factors for the edges of the geometric patch. The tessellation factors apply to a single edge and quantify the view-dependent level of detail associated with the edge. The tessellation unit 510 is configured to receive the tessellation factors for the edges of the patch and tessellate the patch into a plurality of geometric primitives, such as lines, triangles, or quadrilateral primitives, which are transmitted to the tessellation evaluation processing unit 512. The tessellation evaluation processing unit 512 operates on the parameterized coordinates of the tessellated patch to generate vertex attributes and a surface representation for each vertex associated with the geometric primitive.

[0143] A second instance of primitive assembler 514 receives vertex attributes from tessellation evaluation processing unit 512, reads stored vertex attributes as needed, and constructs graphics primitives for processing by geometry processing unit 516. Geometry processing unit 516 is a programmable execution unit that executes geometry shader programs to transform graphics primitives received from primitive assembler 514 as specified by the geometry shader programs. In one embodiment, geometry processing unit 516 is programmed to tessellate the graphics primitives into one or more new graphics primitives and to compute parameters for rasterizing the new graphics primitives.

[0144] In some embodiments, the geometry processing unit 516 can add or delete elements in the geometry stream. The geometry processing unit 516 outputs parameters and vertices specifying new graphics primitives to the primitive assembler 518. The primitive assembler 518 receives the parameters and vertices from the geometry processing unit 516 and constructs graphics primitives for processing by the viewport scaling, cull, and clip unit 520. The geometry processing unit 516 reads data stored in the parallel processor memory or system memory for use in processing geometry data. The viewport scaling, cull, and clip unit 520 performs clipping, cull, and viewport scaling, and outputs processed graphics primitives to the rasterizer 522.

[0145] The rasterizer 522 can perform depth sorting and other depth-based optimizations. The rasterizer 522 also performs scan conversion on new graphics primitives to generate fragments and output those fragments and associated coverage data to the fragment / pixel processing unit 524. The fragment / pixel processing unit 524 is a programmable execution unit configured to execute a fragment shader program or a pixel shader program. The fragment / pixel processing unit 524 transforms the fragments or pixels received from the rasterizer 522 as specified by the fragment or pixel shader program. For example, the fragment / pixel processing unit 524 can be programmed to perform operations including but not limited to texture mapping, shading, blending, texture correction, and perspective correction to generate shaded fragments or pixels output to the raster operation unit 526. The fragment / pixel processing unit 524 can read data stored in a parallel processor memory or system memory for use in processing fragment data. The fragment or pixel shader program can be configured to shade with samples, pixels, tiles, or other granularity according to the sampling rate configured for the processing unit.

[0146] Raster operations unit 526 is a processing unit that performs raster operations including, but not limited to, stenciling, z-checking, blending, etc., and outputs pixel data as processed graphics data for storage in graphics memory (e.g., parallel processor memory 222 in FIG. 2 , and / or as Figure 1 The raster operations unit 526 may be configured to compress the z or color data written to the memory and to decompress the z or color data read from the memory.

[0147] Machine Learning Overview

[0148] A machine learning algorithm is an algorithm that can learn based on a set of data. Embodiments of machine learning algorithms can be designed to model high-level abstractions within a data set. For example, an image recognition algorithm can be used to determine which of several categories a given input belongs to; a regression algorithm can output a numerical value given an input; and a pattern recognition algorithm can be used to generate translated text or perform text-to-speech and / or speech recognition.

[0149] One exemplary type of machine learning algorithm is a neural network. There are many types of neural networks; one simple type of neural network is a feedforward network. A feedforward network can be implemented as an acyclic graph in which nodes are arranged in layers. Typically, a feedforward network topology includes an input layer and an output layer separated by at least one hidden layer. The hidden layer transforms the input received by the input layer into a representation useful for generating output in the output layer. The nodes of the network are fully connected to the nodes in the adjacent layers via edges, but there are no edges between the nodes within each layer. Data received at the nodes of the input layer of the feedforward network is propagated (i.e., "fed forward") to the nodes of the output layer via an activation function, which calculates the state of the nodes of each successive layer in the network based on coefficients ("weights"), which are respectively associated with each of the edges connecting the layers. Depending on the specific model represented by the algorithm being executed, the output from the neural network algorithm can take a variety of forms.

[0150] Before a machine learning algorithm can be used to model a particular problem, the algorithm is trained using a training data set. Training a neural network involves selecting a network topology, using a set of training data representing the problem modeled by the network, and adjusting weights until the network model performs with minimal error for all instances of the training data set. For example, during a supervised learning training process for a neural network, the output generated by the network in response to an input representing an instance in the training data set is compared to the "correct" labeled output for the instance, an error signal representing the difference between the output and the labeled output is calculated, and when the error signal is propagated back through the layers of the network, the weights associated with the connections are adjusted to minimize the error. The network is considered "trained" when the error for each output generated from an instance of the training data set is minimized.

[0151] The accuracy of a machine learning algorithm may be significantly affected by the quality of the data set used to train the algorithm. The training process can be computationally intensive and can take a significant amount of time on a conventional general-purpose processor. Therefore, many types of machine learning algorithms are trained using parallel processing hardware. This is particularly useful for optimizing the training of neural networks, as the calculations performed when adjusting the coefficients in a neural network are themselves naturally conducive to parallel implementation. In particular, many machine learning algorithms and software applications have been adapted to use parallel processing hardware within general-purpose graphics processing devices.

[0152] Figure 6600 is a generalized diagram of a machine learning software stack 600. Machine learning applications 602 may be configured to train a neural network using a training data set or to implement machine intelligence using a trained deep neural network. Machine learning applications 602 may include specialized software that may be used to train a neural network prior to deployment and / or training and inference functions for a neural network. Machine learning applications 602 may implement any type of machine intelligence, including but not limited to image recognition, mapping and localization, autonomous navigation, speech synthesis, medical imaging, or language translation.

[0153] Hardware acceleration for machine learning applications 602 can be enabled via a machine learning building block 604. The machine learning building block 604 can provide a library of machine learning primitives. Machine learning primitives are basic operations that machine learning algorithms typically perform. Without the machine learning building block 604, developers of machine learning algorithms would be required to create and optimize the main computational logic associated with the machine learning algorithm, and then re-optimize the computational logic when new parallel processors are developed. Instead, machine learning applications can be configured to use primitives provided by the machine learning building block 604 to perform necessary calculations. Demonstration primitives include tensor convolutions, activation functions, and pooling, which are computational operations performed when training convolutional neural networks (CNNs). The machine learning building block 604 can also provide primitives to implement basic linear algebra subroutines, such as matrix and vector operations, performed by many machine learning algorithms.

[0154] The machine learning brick shelf 604 may process input data received from the machine learning application 602 and generate appropriate inputs to the compute brick shelf 606. The compute brick shelf 606 may abstract the basic instructions provided to the GPGPU driver 608 so that the machine learning brick shelf 604 can take advantage of hardware acceleration via the GPGPU hardware 610 without requiring the machine learning brick shelf 604 to be intimately familiar with the architecture of the GPGPU hardware 610. In addition, the compute brick shelf 606 may enable hardware acceleration for the machine learning brick shelf 604 across multiple types and generations of GPGPU hardware 610.

[0155] GPGPU machine learning acceleration

[0156] Figure 7 A highly parallel general purpose graphics processing unit 700 is illustrated in accordance with an embodiment. In one embodiment, a general purpose processing unit (GPGPU) 700 may be configured to be particularly efficient at processing the type of computational workload associated with training deep neural networks. Additionally, a GPGPU 700 may be directly linked to other instances of a GPGPU to create a multi-GPU cluster to improve the speed of training particularly deep neural networks.

[0157] GPGPU 700 includes a host interface 702 for enabling connection to a host processor. In one embodiment, host interface 702 is a PCI Express interface. However, the host interface may also be a vendor-specific communication interface or communication structure. GPGPU 700 receives commands from the host processor and distributes execution threads associated with those commands to a set of computing clusters 706A-706H using a global scheduler 704. Computing clusters 706A-706H share a cache memory 708. Cache memory 708 may act as a high-level cache in a cache memory within a computing cluster 706A-706H.

[0158] GPGPU 700 includes memory 714A-714B coupled to computing clusters 706A-H via a set of memory controllers 712A-712B. In various embodiments, memory 714A-714B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM) (including graphics double data rate (GDDR) memory) or 3D stacked memory (including but not limited to high bandwidth memory (HBM)).

[0159] In one embodiment, each computing cluster 706A-706H includes a set of graphics multiprocessors, such as Figure 4A The graphics multiprocessor 400 of the computing cluster includes multiple types of integer and floating point logic units that can perform computational operations at a range of precisions, including precisions suitable for machine learning computations. For example and in one embodiment, at least a subset of the floating point units in each of the computing clusters 706A-H can be configured to perform 16-bit or 32-bit floating point operations, while a different subset of the floating point units can be configured to perform 64-bit floating point operations.

[0160] Multiple instances of GPGPU 700 can be configured to operate as a computing cluster. The communication mechanism used by the computing cluster for synchronization and data exchange varies across embodiments. In one embodiment, multiple instances of GPGPU 700 communicate through a host interface 702. In one embodiment, GPGPU 700 includes an I / O hub 709 that couples GPGPU 700 to a GPU link 710, which enables direct connection to other instances of GPGPU. In one embodiment, GPU link 710 is coupled to a dedicated GPU to GPU bridge, which enables communication and synchronization between multiple instances of GPGPU 700. In one embodiment, GPU link 710 is coupled to a high-speed interconnect to transmit data to other GPGPUs or parallel processors and receive data. In one embodiment, multiple instances of GPGPU 700 are located in a separate data processing system and communicate via a network device, which can be accessed via a host interface 702. In one embodiment, in addition to or as a replacement for the host interface 702, GPU link 710 can be configured to enable connection to a host processor.

[0161] Although the illustrated configuration of GPGPU 700 can be configured to train a neural network, one embodiment provides an alternative configuration of GPGPU 700 that can be configured for deployment within a high-performance or low-power inference platform. In the inference configuration, GPGPU 700 includes fewer computing clusters 706A-H relative to the training configuration. In addition, the memory technology associated with memory 714A-714B may be different between the inference configuration and the training configuration. In one embodiment, the inference configuration of GPGPU 700 can support inference-specific instructions. For example, the inference configuration can provide support for one or more 8-bit integer dot product instructions, which are typically used during inference operations for deployed neural networks.

[0162] Figure 8 A multi-GPU computing system 800 is illustrated according to an embodiment. The multi-GPU computing system 800 may include a processor 802 coupled to a plurality of GPGPUs 806A-806D via a host interface switch 804. In one embodiment, the host interface switch 804 is a PCI express switch device that couples the processor 802 to a PCI express bus, through which the processor 802 may communicate with the set of GPGPUs 806A-D. Each of the plurality of GPGPUs 806A-806D may be Figure 7GPGPU 806A-D may be interconnected via a set of high-speed point-to-point GPU-to-GPU links 816. The high-speed GPU-to-GPU links may be connected via dedicated GPU links (such as Figure 7 806D). The P2P GPU link 816 enables direct communication between each of the GPGPUs 806A-806D without requiring communication through a host interface bus to which the processor 802 is connected. In the case where GPU-to-GPU traffic involves a P2P GPU link, the host interface bus may still be used for system memory access or communication with other instances of the multi-GPU computing system 800, for example, via one or more network devices. Although in the illustrated embodiment the GPGPUs 806A-806D are connected to the processor 802 via the host interface switch 804, in one embodiment the processor 802 includes direct support for the P2P GPU link 816 and may be directly connected to the GPGPUs 806A-806D.

[0163] Machine Learning Neural Network Implementation

[0164] The computing architecture provided by the embodiments described herein can be configured to perform parallel processing of a type particularly suitable for training and deploying neural networks for machine learning. A neural network can be generalized as a network of functions with graph relationships. As is known in the art, there are many types of neural network implementations used in machine learning. One exemplary type of neural network is a feedforward network as previously described.

[0165] The second exemplary type of neural network is the convolutional neural network (CNN). CNN is a specialized feed-forward neural network for processing data with a known grid-like topology (such as image data). Therefore, CNNs are commonly used for computational vision and image recognition applications, but they can also be used for other types of pattern recognition, such as speech and language processing. The nodes in the input layer of a CNN are organized into a set of "filters" (feature detectors stimulated by the receptive fields found in the retina), and the output of each set of filters is propagated to the nodes in the successive layers of the network. The calculations for a CNN include applying a convolution mathematical operation to each filter to produce the output of the filter. Convolution is a special kind of mathematical operation performed by two functions to produce a third function, which is a modified version of one of the two original functions. In convolutional network terminology, the first function of the convolution can be called the input, and the second function can be called the convolution kernel. The output can be called a feature map. For example, the input to the convolution layer can be a multidimensional data array that defines the various color components of the input image. The convolution kernel can be a multidimensional parameter array, where the parameters are adapted by a training process for the neural network.

[0166] A recurrent neural network (RNN) is a class of feedforward neural networks that include feedback connections between layers. RNNs enable modeling of sequence data by sharing parameter data across different parts of the neural network. The architecture of an RNN includes loops. A loop represents the effect of the current value of a variable on its own value at a future time, as at least a portion of the output data from the RNN is used as feedback for processing subsequent inputs in the sequence. This feature makes RNNs particularly useful for language processing due to the mutable nature that language data can include.

[0167] The figures described below present exemplary feedforward, CNN, and RNN networks, and describe the general process for training and deploying each of those types of networks, respectively. It will be understood that these descriptions are exemplary and non-limiting with respect to any specific embodiments described herein, and that the illustrated concepts may be generally applied to deep neural networks and machine learning techniques in general.

[0168] The exemplary neural network described above can be used to perform deep learning. Deep learning is machine learning performed using a deep neural network. In contrast to shallow neural networks that include only a single hidden layer, the deep neural network used in deep learning is an artificial neural network composed of multiple hidden layers. Training deeper neural networks is generally more computationally intensive. However, the additional hidden layers of the network enable multi-step pattern recognition, which results in reduced output errors relative to shallow machine learning techniques.

[0169] The deep neural networks used in deep learning typically include a front-end network to perform feature recognition coupled to a back-end network representing a mathematical model, which can perform operations (e.g., object classification, speech recognition, etc.) based on the feature representations provided to the model. Deep learning enables machine learning to be performed without requiring handcrafted feature engineering to be performed on the model. Instead, deep neural networks can learn features based on statistical structures or correlations within the input data. The learned features can be provided to a mathematical model, which can map the detected features to outputs. The mathematical model used by the network is generally specialized for a specific task to be performed, and different models will be used to perform different tasks.

[0170] Once a neural network is structured, a learning model can be applied to the network to train the network to perform a specific task. The learning model describes how to adjust the weights within the model to reduce the network's output error. Backpropagation of errors is a common method for training neural networks. An input vector is presented to the network for processing. The output of the network is compared to the desired output using a loss function, and an error value is calculated for each neuron in the output layer. The error values ​​are then propagated backwards until each neuron has an associated error value that roughly represents its contribution to the original output. The network can then learn from those errors using an algorithm such as the stochastic gradient descent algorithm to update the weights of the neural network.

[0171] Figures 9A-9B Illustration of an example convolutional neural network. Fig.9A The diagram shows the various layers within a CNN. Fig.9A As shown in , an exemplary CNN for modeling image processing can receive an input 902, which describes the red, green, and blue (RGB) components of an input image. The input 902 can be processed by multiple convolutional layers (e.g., convolutional layer 904, convolutional layer 906). The outputs from the multiple convolutional layers can be optionally processed by a set of fully connected layers 908. The neurons in the fully connected layer have full connections to all activation functions in the previous layer, as previously described for the feedforward network. The output from the fully connected layer 908 can be used to generate output results from the network. Matrix multiplication can be used instead of convolution to calculate the activation within the fully connected layer 908. Not all CNN implementations use the fully connected layer 908. For example, in some implementations, the convolutional layer 906 can generate the output of the CNN.

[0172] The convolutional layers are sparsely connected, which is different from the traditional neural network configuration found in the fully connected layer 908. Traditional neural network layers are fully connected so that each output unit interacts with each input unit. However, the convolutional layers are sparsely connected because the output of the convolution of the domain (rather than the corresponding state value of each node in the domain) is input to the nodes of the subsequent layer, as shown. The kernel associated with the convolutional layer performs a convolution operation, the output of which is sent to the next layer. The dimensionality reduction performed within the convolutional layer is one aspect that enables CNNs to scale to process large images.

[0173] Fig. 9B An exemplary computational stage within a convolutional layer of a CNN is illustrated. An input 912 to a convolutional layer of a CNN may be processed in three stages of a convolutional layer 914. The three stages may include a convolution stage 916, a detector stage 918, and a pooling stage 920. The convolutional layer 914 may then output data to a successive convolutional layer. The final convolutional layer of the network may generate output feature map data or provide input to a fully connected layer, for example to generate a classification value for input to the CNN.

[0174] Several convolutions are performed in parallel in the convolution stage 916 to produce a set of linear activations. The convolution stage 916 may include an affine transformation, which is any transformation that can be specified as a linear transformation plus a translation. Affine transformations include rotations, translations, scaling, and combinations of these transformations. The convolution stage calculates the output of a function (e.g., a neuron) connected to a specific area in the input, which can be determined as a local area associated with the neuron. The neuron calculates the dot product between the weight of the neuron and the area in the local input to which the neuron is connected. The output from the convolution stage 916 defines a set of linear activations processed by the successive stages of the convolution layer 914.

[0175] The linear activations may be processed by the detector stage 918. In the detector stage 918, each linear activation is processed by a non-linear activation function. The non-linear activation function increases the non-linear nature of the overall network without affecting the receptive field of the convolutional layer. Several types of non-linear activation functions may be used. One particular type is the rectified linear unit (ReLU), which is defined as f(x) =max( 0 , x ) such that the activation is thresholded at zero.

[0176] The pooling stage 920 uses a pooling function that replaces the output of the convolution layer 906 with summary statistics of nearby outputs. The pooling function can be used to introduce translation invariance into the neural network so that small translations of the input do not change the pooled output. The invariance of local translations can be useful in scenarios where the presence of a feature in the input data is more important than the exact location of the feature. Various types of pooling functions can be used during the pooling stage 920, including maximum pooling, average pooling, and l2-norm pooling. In addition, some CNN implementations do not include a pooling stage. Instead, such implementations replace and additional convolution stages with an increased stride relative to the previous convolution stage.

[0177] The output from the convolutional layer 914 may then be processed by the next layer 922. The next layer 922 may be an additional convolutional layer or one of the fully connected layers 908. For example, Fig.9A The first convolution layer 904 can output to the second convolution layer 906, and the second convolution layer can output to the first layer in the fully connected layer 908.

[0178] Fig.10An exemplary recurrent neural network 1000 is illustrated. In a recurrent neural network (RNN), the previous state of the network affects the output of the current state of the network. A variety of functions can be used to establish RNNs in a variety of ways. The use of RNNs generally revolves around the use of mathematical models to predict the future based on previous input sequences. For example, RNNs can be used to perform statistical language modeling to predict upcoming words given a previous word sequence. The illustrated RNN 1000 can be described as having an input layer 1002 that receives an input vector, a hidden layer 1004 for implementing a recursive function, a feedback mechanism 1005 for enabling a 'memory' of a previous state, and an output layer 1006 for outputting a result. The RNN 1000 operates based on time steps. The state of the RNN at a given time step is affected based on the previous time step via the feedback mechanism 1005. For a given time step, the state of the hidden layer 1004 is defined by the previous state and the input at the current time step. The initial input (x1) at the first time step can be processed by the hidden layer 1004. The second input (x2) can be processed by the hidden layer 1004 using the state information determined during the processing of the initial input (x1). The given state can be calculated as s t = f ( Ux t + W t-1 ),in U and W is the parameter matrix. The function f Usually nonlinear, such as the hyperbolic tangent function (Tanh) or the modified function f (x) = max( 0 , x However, the specific mathematical function used in hidden layer 1004 may vary depending on the specific implementation details of RNN 1000.

[0179] In addition to the basic CNN and RNN networks described, variations of those networks can also be enabled. An example RNN variant is the Long Short Term Memory (LSTM) RNN. LSTM RNN is able to learn long-term dependencies that may be necessary to process longer language sequences. A variant of CNN is the Convolutional Deep Belief Network, which has a structure similar to that of a CNN and is trained in a manner similar to that of a Deep Belief Network. A Deep Belief Network (DBN) is a generative neural network consisting of multiple layers of random (stochastic) variables. A DBN can be trained layer by layer using greedy unsupervised learning. The learned weights of the DBN can then be used to provide a pre-trained neural network by determining a set of optimal initial weights for the neural network.

[0180] Fig.11 The training and deployment of a deep neural network is illustrated. Once a given network has been structured for a task, the neural network is trained using a training data set 1102. Various training building blocks 1104 have been developed to enable hardware acceleration of the training process. For example, Figure 6 The machine learning block frame 604 can be configured as a training block frame 604. The training block frame 604 can be hooked up to the untrained neural network 1106 and enable the untrained neural network to be trained using the parallel processing resources described herein to generate a trained neural network 1108.

[0181] To start the training process, initial weights can be chosen randomly or by pre-training with a deep belief network. A training cycle is then performed in a supervised or unsupervised manner.

[0182] Supervised learning is a learning method in which training is performed as a mediation operation, such as when the training data set 1102 includes an input paired with an expected output of the input, or when the training data set includes an input with a known output and the output of the neural network is manually graded. The network processes the input and compares the generated output with a set of expected or desired outputs. The error is then back-propagated through the system. The training block frame 1104 can be adjusted to adjust the weights that control the untrained neural network 1106. The training block frame 1104 can provide a tool to monitor how well the untrained neural network 1106 converges toward a model suitable for generating the correct answer based on the known input data. The training process occurs repeatedly when the weights of the network are adjusted to improve the output generated by the neural network. The training process can continue until the neural network reaches a statistically expected accuracy associated with the trained neural network 1108. The trained neural network 1108 can then be deployed to implement any number of machine learning operations.

[0183] Unsupervised learning is a learning method in which a network attempts to train itself using unlabeled data. Thus, for unsupervised learning, the training data set 1102 will include input data without any associated output data. The untrained neural network 1106 can learn groupings within the unlabeled inputs and can determine how individual inputs relate to the overall data set. Unsupervised training can be used to generate a self-organizing map, which is a type of trained neural network 1107 that is able to perform operations useful in reducing the dimensionality of the data. Unsupervised training can also be used to perform anomaly detection, which allows identification of data points in the input data set that deviate from normal data patterns.

[0184] Variations of supervised and unsupervised training may also be employed. Semi-supervised learning is a technique in which the training data set 1102 includes a mixture of labeled and unlabeled data of the same distribution. Incremental learning is a variation of supervised learning in which input data is used continuously to further train the model. Incremental learning enables a trained neural network 1108 to adapt to new data 1112 without forgetting the knowledge instilled into the network during initial training.

[0185] Whether supervised or unsupervised, the training process for particularly deep neural networks may be too computationally intensive for a single computing node. The training process can be accelerated using a distributed network of computing nodes rather than using a single computing node.

[0186] Fig.12 is a block diagram illustrating distributed learning. Distributed learning is a training model that uses multiple distributed computing nodes to perform supervised or unsupervised training of a neural network. The distributed computing nodes may each include one or more host processors and one or more general processing nodes, such as Figure 7 A highly parallel general purpose graphics processing unit 700 in FIG. 700 . As illustrated, distributed learning can perform model parallelism 1202 , data parallelism 1204 , or a combination of model and data parallelism 1204 .

[0187] In model parallelism 1202, different computing nodes in a distributed system can perform training computations for different parts of a single network. For example, each layer of a neural network can be trained by a different processing node of the distributed system. Benefits of model parallelism include the ability to scale to particularly large models. Splitting the computations associated with different layers of a neural network enables training of very large neural networks where the weights of all layers will not fit into the memory of a single computing node. In some instances, model parallelism can be particularly useful in performing unsupervised training of large neural networks.

[0188] In data parallelism 1204, different nodes of the distributed network have complete instances of the model, and each node receives a different portion of the data. The results from different nodes are then combined. Although different methods for data parallelism are possible, data parallel training methods all require techniques for combining results and synchronizing model parameters between each node. Exemplary methods for combining data include parameter averaging and update-based data parallelism. Parameter averaging trains each node on a subset of the training data, and sets global parameters (e.g., weights, biases) to the average value of the parameters from each node. Parameter averaging uses a central parameter server that maintains parameter data. Update-based data parallelism is similar to parameter averaging, except that updates to the model are transmitted instead of transmitting parameters from the node to the parameter server. In addition, update-based data parallelism can be performed in a decentralized manner, where updates are compressed and transmitted between nodes.

[0189] For example, combined model and data parallelism 1206 can be implemented in a distributed system where each computing node includes multiple GPUs. Each node can have a complete instance of the model, with separate GPUs within each node used to train different parts of the model.

[0190] Distributed training has increased overhead relative to training on a single machine. However, the parallel processors and GPGPUs described herein can each implement various techniques for reducing the overhead of distributed training, including techniques for enabling high-bandwidth GPU-to-GPU data transfer and accelerated remote data synchronization.

[0191] Demonstration of machine learning applications

[0192] Machine learning can be applied to solve a variety of technical problems, including but not limited to computer vision, autonomous driving and navigation, speech recognition, and language processing. Computer vision has traditionally been one of the most active research areas for machine learning applications. The application range of computer vision is from reproducing human visual capabilities (such as recognizing faces) to creating new categories of visual capabilities. For example, a computer vision application can be configured to recognize sound waves from vibrations induced in objects visible in a video. Parallel processor-accelerated machine learning enables the use of significantly larger training data sets than previously feasible training data sets to train computer vision applications, and enables the use of low-power parallel processors to deploy inference systems.

[0193] Parallel processor-accelerated machine learning has autonomous driving applications, including lane and road sign recognition, obstacle avoidance, navigation, and driving control. Accelerated machine learning techniques can be used to train a driving model based on a data set that defines the appropriate response to a specific training input. The parallel processors described herein can enable rapid training of increasingly complex neural networks for autonomous driving solutions and enable the deployment of low-power inference processors in mobile platforms suitable for integration into autonomous vehicles.

[0194] Deep neural networks accelerated by parallel processors have enabled machine learning methods for automatic speech recognition (ASR). ASR involves creating a function that computes the most likely speech sequence given a sequence of input sounds. Accelerated machine learning using deep neural networks has enabled the replacement of hidden Markov models (HMMs) and Gaussian mixture models (GMMs) previously used for ASR.

[0195] Parallel processor-accelerated machine learning can also be used to accelerate natural language processing. Automatic learning programs can use statistical inference algorithms to produce models that are robust to erroneous or unfamiliar inputs. Exemplary natural language processor applications include automatic machine translation between human languages.

[0196] Parallel processing platforms for machine learning can be divided into training platforms and deployment platforms. Training platforms are generally highly parallel and include optimizations to accelerate multi-GPU single-node training and multi-node multi-GPU training. Exemplary parallel processors suitable for training include Figure 7 The highly parallel general purpose graphics processing unit 700 and Figure 8 The multi-GPU computing system 800 of FIG. In contrast, the deployed machine learning platform generally includes low-power parallel processors suitable for use in products such as cameras, autonomous robots, and autonomous vehicles.

[0197] Fig.13An exemplary inference system-on-chip (SOC) 1300 suitable for performing inference using a trained model is illustrated. The SOC 1300 may integrate processing components including a media processor 1302, a visual processor 1304, a GPGPU 1306, and a multi-core processor 1308. The SOC 1300 may additionally include an on-chip memory 1305 that may enable a shared on-chip data pool accessible by each of the processing components. The processing components may be optimized for low-power operation to enable deployment to a variety of machine learning platforms, including autonomous vehicles and autonomous robots. For example, an implementation of the SOC 1300 may be used as part of a master control system for an autonomous vehicle. In the case where the SOC 1300 is configured for use in an autonomous vehicle, the SOC is designed and configured to comply with the relevant functional safety standards of the deployment jurisdiction.

[0198] During operation, the media processor 1302 and the visual processor 1304 can work in unison to accelerate computer vision operations. The media processor 1302 can enable low latency decoding of multiple high-resolution (e.g., 4K, 8K) video streams. The decoded video streams can be written to a buffer in the on-chip memory 1305. The visual processor 1304 can then parse the decoded video and perform preliminary processing operations on the frames of the decoded video in preparation for processing the frames of the decoded video using the trained image recognition model. For example, the visual processor 1304 can accelerate convolution operations for CNNs used to perform image recognition on high-resolution video data, while the back-end model calculations are performed by the GPGPU 1306.

[0199] The multi-core processor 1308 may include control logic to facilitate sequencing and synchronization of shared memory operations and data transfers performed by the media processor 1302 and the vision processor 1304. The multi-core processor 1308 may also act as an application processor to execute software applications that may use the inference computing capabilities of the GPGPU 1306. For example, at least a portion of navigation and driving logic may be implemented in software executed on the multi-core processor 1308. Such software may issue computational workloads directly to the GPGPU 1306, or may issue computational workloads to the multi-core processor 1308, which may offload at least a portion of those operations to the GPGPU 1306.

[0200] GPGPU 1306 may include a computing cluster, such as a low-power configuration of computing clusters 706A-706H within a highly parallel general-purpose graphics processing unit 700. The computing cluster within GPGPU 1306 may support instructions that are specifically optimized to perform inference calculations on trained neural networks. For example, GPGPU 1306 may support instructions for performing low-precision calculations such as 8-bit and 4-bit integer vector operations.

[0201] Dynamic floating point unit accuracy reduction for machine learning operations

[0202] The IEEE 754 single-precision binary floating-point format specifies a 32-bit binary representation with a 1-bit sign, an 8-bit exponent, and a 24-bit significand, of which 23 bits are explicitly stored. The IEEE 754 half-precision binary floating-point format specifies a 16-bit binary representation with a 1-bit sign, a 5-bit exponent, and an 11-bit significand, of which 10 bits are explicitly stored. The implicit significand bit is defined as 1 for non-zero exponent values ​​and is defined as 0 when all exponent bits are zero. Floating-point units capable of performing arithmetic operations in single and half precision are known in the art. For example, existing floating-point units can perform 32-bit single-precision floating-point operations (FP32) or dual 16-bit half-precision floating-point operations (FP16).

[0203] Embodiments described herein extend this capability by providing support for instructions and associated logic to enable variable precision operations. Floating point instructions that allow variable precision operations can dynamically increase throughput by performing operations with lower precision when possible. In one embodiment, associated logic and instruction sets are provided, wherein throughput is increased by performing floating point operations with as low precision as possible without significant data loss. In one embodiment, associated logic and instruction sets are provided, wherein floating point logic will verify the lower precision results for the results performed with higher precision to determine whether any significant data loss has occurred.

[0204] Fig.14 Components of a dynamic precision floating point unit 1400 according to an embodiment are shown. Dynamic Precision Floating Point Unit 1400 In one embodiment, the dynamic precision floating point unit 1400 includes a control unit 1402, a set of internal registers 1404, an exponent block 1406, and a significand block 1408. In addition to floating point control logic known in the art, in one embodiment, the control unit 1402 additionally includes precision tracking logic 1412 and a value conversion unit 1422.

[0205] In one embodiment, the precision tracking logic 1412 is hardware logic that is configured to track the available number of precision bits of computational data associated with a target precision. The precision tracking logic 1412 can track precision registers within the exponent block 1406 and the significand block 1408 to track precision metrics, such as the minimum number of precision bits required to store computational values ​​generated by the exponent block 1406 and the significand block 1408. In one embodiment, the precision metric includes a running average of the numerical precision required for data represented on a set of computations. In one embodiment, the precision metric includes the maximum required precision within a given set of data. In one embodiment, the dynamic precision floating point unit 1400 supports instructions for reading or resetting register data used by the precision tracking logic 1412 to generate the precision metrics described herein. In one embodiment, a computation unit housing the dynamic precision floating point unit supports instructions for setting or resetting register data used by the precision tracking logic 1412. In one embodiment, the precision tracking logic 1412 monitors an error accumulator 1434 in a set of internal registers 1404. The error accumulator can be used to track accumulated errors (e.g., rounding errors) on a set of floating point operations. In one embodiment, dynamic precision floating point unit 1400 supports an instruction set including an instruction to reset error accumulator 1434 and an instruction to read error accumulator 1434. In one embodiment, the error accumulator may be reset in response to a bit or flag supplied as an operand to the instruction.

[0206] In one embodiment, the numerical transformation unit 1422 may be used to perform intermediate numerical transformations on data when performing lower precision operations to prevent or mitigate the possibility of overflow or underflow when performing the operations. For example, when approaching the precision limit of a given data type, the numerical transformation unit 1422 may perform a multiplication or division operation using logarithms and transform the resulting value via exponentiation. Further details regarding the precision tracking logic 1412 and the numerical transformation unit 1422 are described in Fig. 22 Available in.

[0207] The internal registers 1404 include a set of operand registers 1414 that store input values ​​for the dynamic precision floating point unit 1400. In one embodiment, the operand registers 1414 include two operands (A, B). For floating point input data, the input data value can be divided into an exponent portion (EXA, EXB) and a valid digit portion (SIGA, SIGB). In various embodiments, the operand registers 1414 are not limited to supporting two floating point inputs. In one embodiment, the operand registers 1414 include three input operands, for example to support fused multiply-add, multiply-subtract, multiply-accumulate or related operations. In one embodiment, the operand registers 1414 can also store integer values, such as in one embodiment the dynamic precision floating point unit supports 32-bit, 16-bit and 8-bit integer operations. In one embodiment, the specific data type and baseline precision are configurable via input to the control unit 1402.

[0208] In one embodiment, floating point operations are performed with dynamic precision using exponent block 1406 and significand block 1408. In one embodiment, integer operations may be performed via significand block 1408. In one embodiment, dual 8-bit integer operations may be performed using exponent block 1406 and significand block 1408.

[0209] In one embodiment, exponent block 1406 includes comparator 1416 and dynamic precision exponent adder 1426. The comparator determines the difference between the exponents and determines the smaller of the two exponents. During floating point addition, the exponent of the smaller number is adjusted to match the exponent of the larger number. Dynamic precision exponent adder 1426 can be used to add exponent values ​​for FP16 or FP32 values. Significand block 1408 includes dynamic precision multiplier 1418, shift unit 1428, dynamic precision significand adder 1438, and accumulator register 1448.

[0210] In one embodiment, FP16 or FP32 data types may be specified for an operation. Where FP16 is specified, the dynamic precision floating point unit 1400 may power gate elements that are not necessary to perform FP32 operations while maintaining logic to track precision loss or errors (e.g., via error accumulator 1434). For example and in one embodiment, the error accumulator 1434 may be used to track multiple rounding operations within an instruction cycle. In one embodiment, the error accumulator maintains a value of the total accumulated rounding error over an instruction set. The dynamic precision floating point unit 1400 may enable support for instructions that clear or read the error accumulator 1434 from software. Where FP32 is specified, the dynamic precision floating point unit 1400 may attempt to perform FP32 operations at FP16 precision while powering gate elements and components that exceed those gate elements and components required to perform operations at FP16 precision. Based on input or intermediate values, in the case where the dynamic precision floating point unit 1400 is requested to perform an operation in FP32, the dynamic precision floating point unit 1400 may initially attempt to perform the operation in FP16 and expand the precision up to FP32 as needed. In the case where FP32 operations can be performed with FP16 precision, the power consumption requirements per operation are reduced, allowing a larger number of computing elements to be enabled simultaneously. For example, dynamic capacitance and / or power budget limitations for a given configuration (such as a battery-powered configuration or a passive cooling-only configuration) may not allow all floating point units or other computing elements within a GPGPU to be enabled simultaneously. By enabling dynamic lower-precision calculations to reduce the dynamic power of a set of floating point units, the overall throughput of the computing units of the GPGPU within a given power envelope can be increased because a larger number of threads can be processed on a per-cycle basis without exceeding the dynamic power limit.

[0211] Fig.15 According to an embodiment, a Fig.14 1400. In one embodiment, the dynamic precision multiplier 1418 includes a set of input buffers 1302 to store the significand data. In one embodiment, the set of input buffers includes two buffers to store two input values ​​for a multiplication or division operation. For fused operations (e.g., multiply-add, multiply-subtract), the product of the operation can be added to a third input via an adder and / or stored in an accumulator register.

[0212] In one embodiment, some configurations of dynamic precision multiplier 1418 include an input buffer that is a 24-bit input (which can explicitly store 24-bit significand data for single-precision floating point input or 11-bit significand data for half-precision floating point values). In some configurations, input buffer 1302 can also be a 32-bit buffer to enable multiplication of 32-bit integer values. In one embodiment, there is a single configuration of input buffer 1302 that is selectable or configurable between 32 bits and 24 bits. In one embodiment, output buffer 1310 is similarly configurable or selectable between 24 bits and 32 bits to selectively enable storage of 24-bit and / or 11-bit significand values ​​of 32-bit or 16-bit floating point numbers or full-precision 32-bit integers.

[0213] In one embodiment, the dynamic precision multiplier 1418 includes a multiplier 1306 and an overflow multiplier 1304. The multiplier 1306 may be configured to perform a multiplication or division operation with half precision for a data type. For example, the multiplier 1306 may perform an 11-bit multiplication operation for the effective digit of a FP16 floating point value and / or a 16-bit multiplication operation for a 16-bit integer operation. The multiplier 1306 may also perform an 8-bit multiplication operation on an INT8 integer value. For a 32-bit floating point value or a 32-bit integer value, the multiplier 1306 may perform a multiplication operation on a 24-bit effective digit with 11 bits (e.g., FP16 precision). If necessary, the multiplier 1306 may perform a multiplication value 16-bit effective digit precision on a 24-bit FP16 effective digit. In one embodiment, the precision required and obtained for the operation on a given input set may be tracked via a precision register 1308. In one embodiment, the requested and resulting precision may be represented within precision register 1308 via the loss of precision that would be incurred if the output of multiplier 1306 were output via output buffer 1310. In such embodiments, precision register 1308 may track the loss of precision associated with the use of lower precision data types and the loss of precision associated with performing operations at a precision lower than that requested.

[0214] In one embodiment, control logic associated with dynamic precision multiplier 1418 (e.g., in Fig.14 The control logic 1402 of the embodiment of the present invention can monitor the precision loss associated with the operation of performing a higher precision (e.g., FP32, INT32) operation with a lower precision (e.g., FP16, INT16, INT8). If the precision loss will be significant, the control logic can cause the overflow multiplier 1304 to perform the operation for the additional precision bits. In addition, if the control logic determines that an overflow or underflow will occur based on the current input, the overflow multiplier 1304 is enabled and the multiplication operation is performed using the overflow multiplier 1304 and the multiplier 1306.

[0215] Similar control operations are performed for the dynamic precision exponent adder 1426 and the dynamic precision significand adder 1438. The dynamic precision exponent adder 1426 includes a set of 8-bit input buffers that can store exponent data for FP32 (8-bit) and FP16 (5-bit). The 8-bit input buffer 1312 can also store an INT-8 input set. The output buffer 1320 for the dynamic precision exponent adder 1426 can be configured similarly. The dynamic precision significand adder 1438 includes a set of input buffers 1322 that can be selected from one of a set of 24-bit and 32-bit buffers, or can be dynamically configurable to store 24-bit or 32-bit input data. In one embodiment, the input buffer 1322 is only a 32-bit buffer that can also store 24-bit input data. The output buffer 1330 for the dynamic precision significand adder 1438 can be configured similarly. The precision register 1318 within the dynamic precision exponent adder 1426 and the precision register 1328 within the dynamic precision significand adder 1438 can be configured to track the loss of precision of the operations performed. The control logic can enable the overflow adder 1314 and / or the overflow adder 1324 as needed to prevent overflow or underflow conditions or to prevent the loss of precision from exceeding a threshold.

[0216] return Fig.14 In one embodiment, dual INT8 operations may be performed by the dynamic precision floating point unit 1400 using the dynamic precision exponent adder 1426 and the dynamic precision significand adder 1438. For example, instead of disabling the exponent block 1406 during integer operations, the exponent block 1406 may be configured to perform operations on a first set of 8-bit integer operands, while the significand block 1408 may be configured to perform operations on a second set of 8-bit operands. To enable support for dual 8-bit multiplication, dual fused multiply-add, dual fused multiply-subtract, and / or other multiplication-based operations, in one embodiment, the exponent block 1406 may include an additional multiplier 1436. The multiplier may be a fixed 8-bit multiplier to enable simultaneous dual 8-bit multiplication operations using the exponent block 1406 and the significand block 1408.

[0217] Fig.16Thread assignment of a dynamic precision processing system 1600 according to an embodiment is shown. In one embodiment, the dynamic precision processing system 1600 includes a set of dynamic floating point units 1608A-1608D. The dynamic floating point units 1608A-1608D can execute a set of operation threads 1606A-1606D, which can perform mixed precision operations and generate output data with variable precision. In one embodiment, a first operation (e.g., addition, subtraction, multiplication, division, etc.) can be performed on the first dynamic floating point unit 1608A by a first operation thread 1606A, where the first operation thread 1606A accepts two 16-bit floating point values ​​1602A-1602B as input and outputs a 16-bit floating point value FP16. The first operation can be performed as a dual operation, where a single instruction executed by the GPGPU allows for mixed precision FP16 / FP32 dual operations. The second operation of the dual operation may be performed by a second operation thread 1606B, which is performed by a second dynamic floating point unit 1608B, which may generate a second output 1612 as a 32-bit floating point output. The second operation thread 1606B configures the second dynamic floating point unit 1608B to receive two 32-bit floating point input values ​​1603A-1603B. In one embodiment, the operation of the two 32-bit floating point operations may be performed with 16-bit precision if the operation can be performed without excessive loss of precision, underflow, or overflow by performing the operation with lower precision.

[0218] In one embodiment, the dynamic precision processing system 1600 may execute a single instruction with a 16-bit operand 1604A and a 32-bit operand 1604B. The operation thread 1606C may be executed on the dynamic floating point unit 1608C. The dynamic floating point unit 1608C will attempt to perform mixed precision 16-bit / 32-bit operations with 16-bit precision unless a significant loss of precision or error will occur. In one embodiment, the dynamic precision processing system 1600 may also be configured to perform integer operations. For example, an operation on a pair of 8-bit integer inputs 1605A-1605B may be performed via the operation thread 1606D with the aid of the dynamic floating point unit 1608D to generate an 8-bit integer output 1616. In one embodiment, the dynamic floating point unit 1608D may be configured to perform dual 8-bit integer operations, where two 8-bit integer operations may be performed in a single cycle.

[0219] Fig.17 1700 is shown for performing numerical operations with less precision than requested according to an embodiment. In one embodiment, logic 1700 is implemented via an integrated Fig.14 In one embodiment, logic 1700 is implemented in part via hardware within dynamic precision floating point unit 1400. Fig.14The control unit 1402 within the dynamic precision floating point unit 1400 executes.

[0220] In one embodiment, logic 1700 may receive a request to perform a numerical operation with a first precision, as shown in block 1702. The numerical operation may be a floating point operation or an integer operation. The first precision may be, for example, 32-bit precision. In one embodiment, the numerical operation may be an operation with a first precision that is performed on an operation with mixed precision. Logic 1700 may then perform the numerical operation using a plurality of bits associated with a second precision lower than the first precision, as shown in block 1704. For example and in one embodiment, the number of bits used to perform the operation may be a plurality of bits associated with a 16-bit operation, while the first precision is 32-bit precision. At block 1706, logic 1700 may generate an intermediate result with a second precision. Logic 1700 may then determine the precision loss of the intermediate result associated with the first precision. The precision loss may be read from a register that stores a precision loss indicator stored during the operation.

[0221] At block 1709, the logic 1700 may determine whether the loss of precision is less than a threshold. In one embodiment, the threshold associated with the loss of precision may be software configurable, although in some embodiments a hardware default threshold is used. In one embodiment, the extent of the loss of precision may also be determined via performing full-precision operations in parallel on unused computational units. The reduced precision result may then be compared to the full-precision result. If the loss of precision is less than the threshold, the logic 1700 may output the result at the second precision, as shown at block 1712. If at block 1709 the loss of precision is not less than the threshold, then at block 1710 the logic 1700 may calculate the remaining bits of the result and output the result at the first precision, as shown at block 1714. In one embodiment, the overflow logic unit (such as, for example, at Fig.15 The overflow multiplier 1304, the overflow adder 1314 and / or the overflow adder 1324 in block 1710 are used to perform the calculation on the remaining bits of the result.

[0222] Vertical stacking of 16-bit floating point operations

[0223] When performing single instruction multiple thread (SIMT) operations with lower precision, in some cases, it may be difficult to maintain full utilization of the underlying single instruction multiple data (SIMD) logic due to the large number of elements required to fill all SIMD channels. For example, a SIMD logic unit configured for FP32 operations on 128-bit input registers can perform a single operation on four sets of input data. If the logic unit is configured to perform FP16 operations on the same four sets of input data, the underlying throughput of the operation may increase due to the lower operation precision, but the SIMD utilization is halved. One solution to SIMD underutilization is to perform operations on eight sets of input data. However, the software executed on the logic unit may not require as much parallelism as the underlying hardware can provide.

[0224] For example, a loop that performs iterative operations on an input array can be vectorized so that each iteration of the array is executed in parallel as a separate SIMT thread. A separate SIMT thread can be executed on the underlying SIMD / vector logic within the computing unit in a single operation. When executing parallel instructions derived via the compiler loop vectorization logic, loops shorter than 8 iterations will not fill all eight SIMD channels that can be used to execute threads generated for those operations, reducing the overall utilization of the computing unit. In addition, in the case where the underlying hardware has N SIMD channels, any number of non-N multiples of vectorized iterations will require the execution of remainder iterations on less than full SIMD units. In addition, vectorization may require the execution of a peel loop separately before executing the body of the vectorized operation.

[0225] Some embodiments described herein can increase SIMD utilization by stacking multiple unrelated FP16 operations into a single SIMD unit for execution. In the case where a SIMD unit has 8 channels available for execution, the thread scheduling logic can dispatch threads in units of N / 2 or N / 4 and allow unrelated collection threads to perform the same or compatible operations to share a single SIMD unit. In addition, one embodiment enables SIMD channel scheduling, which allows a mix of dynamically assembled SIMT thread groups and vector SIMD threads.

[0226] Fig.18Loop vectorization for SIMD units according to an embodiment is shown. In one embodiment, software logic may include loops automatically vectorized by compiler software executed on a data processing system. The loop may include a stripping loop 1802, a vectorized main loop 1804, and a remainder loop 1806. In some configurations, loop vectorization is most effective when executed on data accessing aligned memory. For example, a GPGPU may be configured so that vector memory access may be most effectively performed in 64-byte chunks 1801A-1801F. In such configurations, a stripping loop 1802 includes a subset of loop iterations stripped from the main loop so that unaligned memory accesses can be separated from the main loop. The vectorized main loop 1804 includes most of the iterations of the loop. Each iteration of the vectorized main loop may be executed in parallel, and the memory accesses to each element are aligned on a specific memory boundary. The remainder loop 1806 includes a set of iterations after the vectorized main loop 1804. The iterations in the remainder loop 1806 may not generally be executed in parallel as effectively as the main loop.

[0227] In one embodiment, the stripping loop 1802 and the remainder loop 1806 can also be vectorized. In one embodiment, each of the stripping loop 1802, the main loop 1804, and the remainder loop 1806 can be executed on an FP16 SIMD8 unit, where eight instances of the same operation can be executed in parallel. The loop iterations can be executed in parallel on SIMD hardware (e.g., FP16 SIMD8 units 1801A-1808C) using execution masks 1812, 1814, and 1816 (each enabling and disabling SIMD channels for the operation cycle). For the stripping loop 1802 and the remainder loop 1806 shown, a subset of elements is selected in the execution mask 1812 and the execution mask 1816. All channels are selected in the execution mask 1814 of the vectorized main loop 1804.

[0228] In one embodiment, SIMD units with inactive channels may be configured to perform other operations on those inactive channels. For a given cycle, where the scheduling logic configures a set of inactive channels for a SIMD unit (e.g., FP16 SIMD8 1808A, FP16SIMD8 108C), instead of idling those channels during the cycle, the scheduler may stack other multi-element SIMD threads or assign SIMT threads to otherwise idle SIMD channels.

[0229] Fig.19A thread processing system 1900 according to an embodiment is shown. In one embodiment, the thread processing system 1900 includes a SIMD computing unit, such as a SIMD8 floating point unit 1920 including multiple dynamic floating point units 1922A-1922H. Depending on the operation, the SIMD8 floating point unit 1920 can perform eight or more identical or similar operations in a single cycle. For example and in one embodiment, each of the eight dynamic floating point units 1922A-1922H can perform a single operation with FP16 precision. In one embodiment, each of the eight dynamic floating point units 1922A-1922H can perform two paired INT8 operations in a single cycle.

[0230] In some cases, such as with Fig.18 In the stripping or remainder loop shown in , not all channels of the SIMD floating point unit will be active during the cycle. In order to increase utilization, SIMD slots can be assigned with smaller granularity to enable otherwise unused SIMD channels to be utilized. For example, SIMD8 floating point unit 1920 will generally be assigned threads or operations with eight operation granularities, wherein less than eight operations present potential computational efficiency losses. In one embodiment, a SIMD channel can be occupied by a single vector SIMD thread, which includes an execution mask that selects at least eight elements or a SIMT thread group with at least eight elements.

[0231] In order to increase SIMD utilization, one embodiment divides eight SIMD channels into two SIMD4 slots (e.g., SIMD4 slot 1910, SIMD4 slot 1912). SIMD4 slots can be filled in a variety of ways. In one embodiment, two separate SIMD threads (SIMD thread 1902, SIMD thread 1904) combined to cover a total of four SIMD channels are assigned to SIMD4 slots (e.g., SIMD4 slot 1910). In one embodiment, SIMT thread group 1906 can be assigned to SIMD4 slot 1912. SIMT thread group 1906 may include any number of threads that are multiples of four threads (e.g., 4, 8, 12, 16, etc.). Threads within SIMT thread group 1906 can be processed four threads at a time, where the number of cycles required to process all threads within SIMT thread group 1906 depends on the number of threads in the group.

[0232] Fig. 20 2000 is shown for assigning threads for computation according to an embodiment. In one embodiment, the logic 2000 is implemented as follows: Fig.19In one embodiment, the logic 2000 may receive a first set of threads at a SIMD unit having a first number of lanes, as shown at block 2002. The logic 2000 may then determine whether the first set of threads fills all SIMD lanes of the SIMD unit, as shown at block 2003. If the first set of threads includes enough SIMT threads or the threads of the first set of threads include enough SIMD vector elements to fill all SIMD lanes, the logic 2000 may assign the first set of threads to the SIMD unit, as shown at block 2004.

[0233] As determined in block 2003, if the first set of threads does not fill all SIMD channels, then in block 2006 logic 2000 can assign the first set of threads to a second number of channels, which is less than the first number of channels. The assignment can be performed by assigning SIMD threads to SIMD units and masking out inactive channels. The assignment can also be performed by assigning SIMD thread sets to SIMD units. As shown in block 2008, the logic can then stack one or more additional thread sets to fill all SIMD channels. The additional thread sets can specify active SIMD channels that occupy channels not occupied by the initial threads.

[0234] A system that enables normalization and transformation of low-precision data

[0235] When performing operations with low-precision data types, care must be taken to avoid overflow or underflow of data during numerical operations. This responsibility usually falls on the data scientist who develops the low-precision algorithms. Due to the restrictive nature of low-precision arithmetic, many neural networks have been adapted to use binary and / or ternary values ​​(occupying only one or two bits per element). However, there is a need for integer and floating-point arithmetic logic units that can enable N-bit low-precision arithmetic with protection logic that can warn or attempt to prevent significant precision loss during arithmetic operations. In one embodiment, the dynamic precision floating-point unit described herein includes logic to warn when a numerical calculation approaches the limits of low-precision calculations.

[0236] like Fig.14As shown in , the dynamic precision floating point unit 1400 may include precision tracking logic 1412 and a numerical transformation unit 1422. In one embodiment, the precision tracking logic 1412 tracks the available bits of precision reserved for the calculated data related to the target precision. The available bits of precision can be tracked for intermediate data to determine whether the intermediate value (which is calculated with a higher precision related to the input data or output data in one embodiment) can be stored at the output precision without significant loss of precision or rounding error. For example and in one embodiment, a specific low-precision operation can be effectively performed with higher precision, and the precision tracking logic 1412 can determine whether the result of the calculation will overflow the given output precision. In one embodiment, the logic unit described herein can output status information indicating the degree of loss of precision due to rounding error. In one embodiment, the logic unit can perform intermediate numerical transformations on the data to prevent significant data loss. The logic unit can then output the transformed value. In one embodiment, a full-precision or near-full-precision output value can be programmatically derived based on the output and status information provided with the output.

[0237] Fig.21 A deep neural network 2100 is shown that can be processed using computational logic provided by the embodiments described herein. A deep neural network (DNN) is an artificial neural network that includes multiple neural network layers 2102A-2102N. Each layer represents a set of non-linear computational operations to perform feature extraction and transformation in a manner consistent with the machine learning neural network described herein. Each successive layer uses the output from the previous layer as input. In the case of a convolutional neural network, fused multiply-add logic (e.g., FMA logic 2104A, 2104B) can be used to calculate the dot product between the feature map and the filter data to generate activation map data provided as input to the successive layers.

[0238] Low-precision neural networks may be implemented using binary or ternary weights combined with binary, ternary, or N-bit feature maps. Some neural networks may still benefit from the added computational precision of using N-bit feature maps and N-bit filters. In some implementations, the N-bit features and weights of a neural network may be processed at low precision without significantly reducing output error. However, data scientists implementing low-precision N-bit neural networks (e.g., FP16, INT8) should generally be aware of rounding errors or out-of-bounds data that may occur due to successive computations at low precision. If the precision tracking logic in the FMA logic 2104A-2106B (e.g., Fig.14If the precision tracking logic 1412 of the FMA logic 2104A-2015B determines that the weight or feature map data is approaching the limit of the available precision for the data type, the status bit may be set by the FMA logic 2104A-2015B. The status bit may serve as an indicator to the data scientist who is developing the neural network model present in the neural network layer 2102A-2012N that the model may require optimization or higher numerical precision may be alerted.

[0239] In one embodiment, the normalization and transformation logic 2106A-2106B may be enabled to perform weight normalization or value transformation on the feature map data before providing it to the next neural network layer for input. The application of the normalization and transformation logic 2106A-2106B is optional at each stage and may be performed only when significant loss of precision, overflow or underflow conditions are likely during processing of the upcoming layer. In one embodiment, the weights or feature maps output from a layer of a neural network may be automatically normalized via instances of the normalization and transformation logic 2106A-2106B.

[0240] In one embodiment, the normalization and transformation logic 2106A-2106B may use Fig.14 The numerical transformation unit 1422 is used to transform the feature map data or weight data. The feature map data output from the neural layer can be based on the data set output from the function set. In such embodiments, a specific set of low-precision instructions is provided, which enables automatic adjustment of N-bit neural network data to prevent catastrophic precision loss. Exemplary transformations or normalizations that can be performed by the normalization and transformation logic 2106A-2016B include weight normalization of continuous and reversible feature data transformation sets or value ranges. In one embodiment, weight normalization can be performed to compress the dynamic range of the filter weight set to a predetermined range. The weight data can be normalized, for example, in the range of [-1,1], which can retain the relative differences between the weight values ​​while reducing the overall magnitude of the weight values. In one embodiment, the neural network weights or feature map data can be normalized by means of the average value of the data set.

[0241] In one embodiment, neural network calculations using data that is close to the range limit of the data type can be transformed before the data is used in the calculation. For example, a multiplication operation using a large value that may cause overflow can be performed as an addition of logarithms rather than a multiplication operation. Although such a transformation may cause a certain degree of precision loss, the calculation will be able to be performed without overflowing the number of bits allocated to perform the operation. For example, a series of operations can be presented as in equation (1).

[0242]

[0243] If the precision tracking logic within the computational unit determines that such an operation may overflow or underflow, then the operation may be transformed into equation (2).

[0244]

[0245] Equation (2) may be executed to produce a result without triggering overflow of the data type. In one embodiment, normalization and transformation logic 2106A-2016B may transform the output values ​​into logarithmic values ​​for storage and transform the values ​​by exponentiation before using the values ​​for machine learning calculations described herein.

[0246] Fig. 22 2200 is a flow chart of logic 2200 for preventing errors or significant precision loss when performing low-precision operations for machine learning according to an embodiment. In one embodiment, the logic 2200 may be implemented as follows: Fig.14 This is achieved by the numerical conversion unit 1422 and the precision tracking logic 1412 within the dynamic precision floating point unit 1400.

[0247] In one embodiment, the logic 2200 may calculate activation maps based on filters and feature map data associated with a layer of a neural network, as shown at block 2202. The logic 2200 may then track the loss of precision that occurs during the calculation of the activation map for the neural network layer. The logic 2200 may then determine at block 2205 whether the loss of precision is approaching a threshold. If the loss of precision is not approaching a default or configured threshold at block 2205, the logic 2200 may continue to calculate activation maps (and apply activation functions) for successive layers until and unless a loss of precision approaches the threshold at block 2205. When the loss of precision approaches the threshold, the logic 2200 may determine at block 2207 whether automatic numerical transformation is enabled. If automatic transformation is enabled at block 2207, such as via instructions for performing a set of numerical operations, the logic 2200 may transform the neural network data to reduce errors due to the loss of precision at block 2208. The logic 2200 may perform any numerical transformation described herein, including normalization of data by means of an average or range. Regardless of whether automatic conversion is enabled at block 2207, the logic 2200 may output a status indicating that the loss of precision is approaching a threshold at block 2210. The status may be output as a status flag output from the computing unit as a result of the executed operation. The programmer may configure the software logic to respond to such status by performing algorithmic adjustments to the executing program or adjusting the neural network model used to perform machine learning.

[0248] Additional Demonstration Graphics Processing Systems

[0249] Details of the embodiments described above may be incorporated into the graphics processing systems and devices described below. Figures 23 to 36The graphics processing systems and devices of exemplify alternative systems and graphics processing hardware that may implement any and all of the techniques described above.

[0250] Additional Demonstration Graphics Processing System Overview

[0251] Fig.23 2300 is a block diagram of a processing system 2300 according to an embodiment. In various embodiments, the system 2300 includes one or more processors 2302 and one or more graphics processors 2308, and may be a single processor desktop system, a multi-processor workstation system, or a server system with a large number of processors 2302 or processor cores 2307. In one embodiment, the system 2300 is a processing platform incorporated into a system-on-chip (SoC) integrated circuit for use in a mobile device, handheld device, or embedded device.

[0252] Embodiments of system 2300 may include a server-based game platform, a game console, including a game and media console, a mobile game console, a handheld game console or an online game console, or are combined therein. In some embodiments, system 2300 is a mobile phone, a smart phone, a tablet computing device or a mobile Internet device. Data processing system 2300 may also include a wearable device (such as a smart watch wearable device, a smart glasses device, an augmented reality device or a virtual reality device), coupled to the wearable device, or integrated in the wearable device. In some embodiments, data processing system 2300 is a television or set-top box device having one or more processors 2302 and a graphical interface generated by one or more graphics processors 2308.

[0253] In some embodiments, each of the one or more processors 2302 includes one or more processor cores 2307 for processing instructions, which, when executed, implement operations for system and user software. In some embodiments, each of the one or more processor cores 2307 is configured to process a specific instruction set 2309. In some embodiments, the instruction set 2309 can facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or computing via very long instruction words (VLIW). Multiple processor cores 2307 can each process different instruction sets 2309, and the instruction set 2309 may include instructions for facilitating the simulation of other instruction sets. The processor core 2307 may also include other processing devices, such as a digital signal processor (DSP).

[0254] In some embodiments, the processor 2302 includes a cache memory 2304. Depending on the architecture, the processor 2302 may have a single internal cache or multiple internal cache levels. In some embodiments, the cache memory is shared between various components of the processor 2302. In some embodiments, the processor 2302 also uses an external cache (e.g., a level 3 (L3) cache or a last level cache (LLC)) (not shown), which may be shared between processor cores 2307 using known cache coherence techniques. A register file 2306 is additionally included in the processor 2302, which may include different types of registers (e.g., integer registers, floating point registers, status registers, and instruction pointer registers) for storing different types of data. Some registers may be general purpose registers, while other registers may be specific to the design of the processor 2302.

[0255] In some embodiments, the processor 2302 is coupled to a processor bus 2310 to transmit communication signals, such as address, data, or control signals, between the processor 2302 and other components in the system 2300. In one embodiment, the system 2300 uses an exemplary 'hub' system architecture, including a memory controller hub 2316 and an input-output (I / O) controller hub 2330. The memory controller hub 2316 facilitates communication between memory devices and other components of the system 2300, while the I / O controller hub (ICH) 2330 provides connections to I / O devices via a local I / O bus. In one embodiment, the logic of the memory controller hub 2316 is integrated within the processor.

[0256] The memory device 2320 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or some other memory device having suitable performance to act as a process memory. In one embodiment, the memory device 2320 may operate as a system memory of the system 2300 to store data 2322 and instructions 2321 for use when the one or more processors 2302 execute applications or processes. The memory controller hub 2316 is also coupled to an optional external graphics processor 2312, which may communicate with the one or more graphics processors 2308 in the processor 2302 to perform graphics and media operations.

[0257] In some embodiments, the ICH 2330 enables peripheral devices to be connected to the memory device 2320 and the processor 2302 via a high-speed I / O bus. The I / O peripherals include, but are not limited to, an audio controller 2346, a firmware interface 2328, a wireless transceiver 2326 (e.g., Wi-Fi, Bluetooth), a data storage device 2324 (e.g., a hard drive, flash memory, etc.), and a legacy I / O controller 2340 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the system. One or more Universal Serial Bus (USB) controllers 2342 connect input devices, such as a keyboard and mouse 2344 combination. A network controller 2334 may also be coupled to the ICH 2330. In some embodiments, a high-performance network controller (not shown) is coupled to the processor bus 2310. It will be appreciated that the illustrated system 2300 is exemplary and not limiting, as other types of data processing systems configured differently may also be used. For example, the I / O controller hub 2330 may be integrated within the one or more processors 2302 , or the memory controller hub 2316 and the I / O controller hub 2330 may be integrated into a discrete external graphics processor, such as the external graphics processor 2312 .

[0258] Fig.24 is a block diagram of an embodiment of a processor 2400 having one or more processor cores 2402A- 2402N, an integrated memory controller 2414 , and an integrated graphics processor 2408 . Fig.24 Those elements having the same reference number (or name) as the elements of any other figure in this article can operate or function in any manner similar to the manner described elsewhere in this article, but are not limited to such. The processor 2400 may include additional cores up to and including the additional core 2402N represented by the dashed block. Each of the processor cores 2402A-2402N includes one or more internal cache units 2404A-2404N. In some embodiments, each processor core is also able to access one or more shared cache units 2406.

[0259] Internal cache units 2404A-2404N and shared cache unit 2406 represent a cache memory hierarchy within processor 2400. The cache memory hierarchy may include at least one level of instruction and data cache within each processor core and one or more levels of shared mid-level cache, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, where the highest level of cache before external memory is classified as LLC. In some embodiments, cache coherency logic maintains coherency between the various cache units 2406 and 2404A-2404N.

[0260] In some embodiments, the processor 2400 may also include a system agent core 2410 and a set of one or more bus controller units 2416. The one or more bus controller units 2416 manage a set of peripheral buses, such as one or more peripheral component interconnect buses (e.g., PCI, PCI Express). The system agent core 2410 provides management functions for various processor components. In some embodiments, the system agent core 2410 includes one or more integrated memory controllers 2414 for managing access to various external memory devices (not shown).

[0261] In some embodiments, one or more of the processor cores 2402A-2402N include support for simultaneous multithreading. In such embodiments, the system agent core 2410 includes components for coordinating and operating the processor cores 2402A-2402N during multithreaded processing. The system agent core 2410 may additionally include a power control unit (PCU) that includes logic and components for regulating the power state of the processor cores 2402A-2402N and the graphics processor 2408.

[0262] In some embodiments, the processor 2400 additionally includes a graphics processor 2408 for performing graphics processing operations. In some embodiments, the graphics processor 2408 is coupled to a set of shared cache units 2406 and a system agent core 2410, the system agent core 2410 including the one or more integrated memory controllers 2414. In some embodiments, a display controller 2411 is coupled to the graphics processor 2408 to drive the graphics processor output to one or more coupled displays. In some embodiments, the display controller 2411 can be a separate module coupled to the graphics processor via at least one interconnect, or can be integrated within the graphics processor 2408 or the system agent core 2410.

[0263] In some embodiments, a ring-based interconnect unit 2412 is used to couple the internal components of the processor 2400. However, alternative interconnect units may be used, such as point-to-point interconnects, switched interconnects, or other technologies, including those known in the art. In some embodiments, the graphics processor 2408 is coupled to the ring interconnect 2412 via an I / O link 2413.

[0264] Exemplary I / O link 2413 represents at least one of a variety of I / O interconnects, including an on-package I / O interconnect that facilitates communication between various processor components and a high-performance embedded memory module 2418, such as an eDRAM module. In some embodiments, each of processor cores 2402A-2402N and graphics processor 2408 use embedded memory module 2418 as a shared last-level cache.

[0265] In some embodiments, the processor cores 2402A-2402N are homogeneous cores that execute the same instruction set architecture. In another embodiment, the processor cores 2402A-2402N are heterogeneous in terms of instruction set architecture (ISA), wherein one or more of the processor cores 2402A-2402N execute a first instruction set, and at least one of the other cores executes a subset of the first instruction set or a different instruction set. In one embodiment, the processor cores 2402A-2402N are heterogeneous in terms of microarchitecture, wherein one or more cores with relatively high power consumption are coupled with one or more power cores with lower power consumption. In addition, the processor 2400 may be implemented on one or more chips or as a SoC integrated circuit having the components shown in addition to other components.

[0266] Fig.25 25 is a block diagram of a graphics processor 2500, which may be a discrete graphics processing unit or may be a graphics processor integrated with multiple processing cores. In some embodiments, the graphics processor communicates via a memory-mapped I / O interface to registers on the graphics processor and using commands placed into processor memory. In some embodiments, the graphics processor 2500 includes a memory interface 2514 for accessing memory. The memory interface 2514 may be an interface to local memory, one or more internal caches, one or more shared external caches, and / or to system memory.

[0267] In some embodiments, the graphics processor 2500 also includes a display controller 2502 for driving display output data to a display device 2520. The display controller 2502 includes hardware for one or more overlapping planes of the display and composition of multiple layers of video or user interface elements. In some embodiments, the graphics processor 2500 includes a video codec engine 2506 for encoding, decoding, or transcoding media to, from, or between one or more media encoding formats, including but not limited to Moving Picture Experts Group (MPEG) formats (such as MPEG-2), Advanced Video Coding (AVC) formats (such as H.264 / MPEG-4 AVC), and Society of Motion Picture & Television Engineers (SMPTE) 421 M / VC-1 and Joint Photographic Experts Group (JPEG) formats (such as JPEG, and Motion JPEG (MJPEG) formats).

[0268] In some embodiments, graphics processor 2500 includes a block image transfer (BLIT) engine 2504 for performing two-dimensional (2D) rasterizer operations including, for example, bit boundary block transfers. However, in one embodiment, 2D graphics operations are performed using one or more components of a graphics processing engine (GPE) 2510. In some embodiments, GPE 2510 is a compute engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.

[0269] In some embodiments, GPE 310 includes a 3D pipeline 2512 for performing 3D operations, such as rendering three-dimensional images and scenes using processing functions that operate on 3D primitive shapes (e.g., rectangles, triangles, etc.). 3D pipeline 2512 includes programmable and fixed functional elements that perform various tasks within the element and / or spawn execution threads to 3D / media subsystem 2515. While 3D pipeline 2512 can be used to perform media operations, embodiments of GPE 2510 also include a media pipeline 2516 that is particularly used to perform media operations, such as video post-processing and image enhancement.

[0270] In some embodiments, the media pipeline 2516 includes fixed function or programmable logic units to perform one or more specialized media operations, such as video decoding acceleration, video deinterlacing, and video encoding acceleration, instead of, or on behalf of the video codec engine 2506. In some embodiments, the media pipeline 2516 additionally includes a thread spawning unit to spawn threads for execution on the 3D / media subsystem 2515. The spawned threads perform computations for media operations on one or more graphics execution units included in the 3D / media subsystem 2515.

[0271] In some embodiments, the 3D / media subsystem 2515 includes logic for executing threads generated in large quantities by the 3D pipeline 2512 and the media pipeline 2516. In one embodiment, the pipeline sends a thread execution request to the 3D / media subsystem 2515, and the 3D / media subsystem 2515 includes thread dispatch logic for arbitrating various requests and dispatching various requests to available thread execution resources. The execution resources include an array of graphics execution units for processing 3D and media threads. In some embodiments, the 3D / media subsystem 2515 includes one or more internal caches for thread instructions and data. In some embodiments, the subsystem also includes shared memory (including registers and addressable memory) to share data between threads and store output data.

[0272] Demonstration of additional graphics processing engine

[0273] Fig.26 is a block diagram of a graphics processing engine 2610 of a graphics processor in accordance with some embodiments. In one embodiment, the graphics processing engine (GPE) 2610 is Fig.25 A version of the GPE 2510 is shown in FIG. Fig.26 Elements having the same reference number (or name) as elements of any other figure in this document may operate or function in any manner similar to that described elsewhere in this document, but are not limited to such. For example, Fig.25 2512 and media pipeline 2516. The media pipeline 2516 is optional in some embodiments of the GPE 2610 and may not be explicitly included in the GPE 2610. For example and in at least one embodiment, separate media and / or image processors are coupled to the GPE 2610.

[0274] In some embodiments, the GPE 2610 is coupled to or includes a command streamer 2603 that provides a command stream to the 3D pipeline 2512 and / or the media pipeline 2516. In some embodiments, the command streamer 2603 is coupled to a memory, which may be a system memory, or one or more of an internal cache memory and a shared cache memory. In some embodiments, the command streamer 2603 receives commands from the memory and sends the commands to the 3D pipeline 2512 and / or the media pipeline 2516. The commands are instructions obtained from a ring buffer storing commands for the 3D pipeline 2512 and the media pipeline 2516. In one embodiment, the ring buffer may further include a batch command buffer storing batches of multiple commands. The commands for the 3D pipeline 2512 may also include references to data stored in the memory, such as, but not limited to, vertex and geometry data for the 3D pipeline 2512 and / or image data and memory objects for the media pipeline 2516. The 3D pipeline 2512 and the media pipeline 2516 process commands and data by performing operations via logic within the respective pipelines or by dispatching one or more execution threads to the graphics core array 2614 .

[0275] In various embodiments, the 3D pipeline 2512 can execute one or more shader programs, such as vertex shaders, geometry shaders, pixel shaders, fragment shaders, compute shaders, or other shader programs, by processing instructions and dispatching execution threads to the graphics core array 2614. The graphics core array 2614 provides a unified execution resource block. The multi-purpose execution logic (e.g., execution unit) within the graphics core array 2614 includes support for various 3D API shader languages ​​and can execute multiple simultaneous execution threads associated with multiple shaders.

[0276] In some embodiments, graphics core array 2614 also includes execution logic for performing media functions such as video and / or image processing. In one embodiment, in addition to graphics processing operations, the execution unit additionally includes general logic that can be programmed to perform parallel general computing operations. The general logic can be used with Fig.23 (multiple) processor cores 2307 or Fig.24 The processor cores 2402A-2402N in or the general logic within any processor described herein perform processing operations in parallel or in combination.

[0277] Output data generated by threads executing on the graphics core array 2614 can output data to memory in a unified return buffer (URB) 2618. URB 2618 can store data for multiple threads. In some embodiments, URB 2618 can be used to send data between different threads executing on the graphics core array 2614. In some embodiments, URB 2618 can also be used for synchronization between fixed function logic within shared function logic 2620 and threads on the graphics core array.

[0278] In some embodiments, graphics core array 2614 is scalable such that the array includes a variable number of graphics cores, each with a variable number of execution units based on the target power and performance level of GPE 2610. In one embodiment, execution resources are dynamically scalable such that execution resources can be enabled or disabled as needed.

[0279] The graphics core array 2614 is coupled to a shared function logic 2620, which includes a plurality of resources shared between the graphics cores in the graphics core array. The shared functions within the shared function logic 2620 are hardware logic units that provide specialized supplementary functions to the graphics core array 2614. In various embodiments, the shared function logic 2620 includes, but is not limited to, a sampler 2621, a math 2622, and an inter-thread communication (ITC) 2623 logic. In addition, some embodiments implement one or more caches 2625 within the shared function logic 2620. The shared functions are implemented in the case where the demand for a given specialized function is insufficient to be included within the graphics core array 2614. Alternatively, a single instantiation of the specialized function is implemented as an independent entity in the shared function logic 2620 and shared between execution resources within the graphics core array 2614. The precise set of functions shared between the graphics core array 2614 and included within the graphics core array 2614 varies between embodiments.

[0280] Fig. 27 is a block diagram of another embodiment of a graphics processor 2700 . Fig. 27 Elements having the same reference number (or name) as elements of any other figure herein may operate or function in any manner similar to that described elsewhere herein, but are not limited to such.

[0281] In some embodiments, graphics processor 2700 includes ring interconnect 2702, pipeline front end 2704, media engine 2737, and graphics cores 2780A-2780N. In some embodiments, ring interconnect 2702 couples the graphics processor to other processing units, including other graphics processors or one or more general-purpose processor cores. In some embodiments, the graphics processor is one of many processors integrated into a multi-core processing system.

[0282] In some embodiments, the graphics processor 2700 receives batches of commands via a ring interconnect 2702. Incoming commands are interpreted by a command streamer 2703 in a pipeline front end 2704. In some embodiments, the graphics processor 2700 includes scalable execution logic for performing 3D geometry processing and media processing via (multiple) graphics cores 2780A-2780N. For 3D geometry processing commands, the command streamer 2703 supplies the commands to a geometry pipeline 2736. For at least some media processing commands, the command streamer 2703 supplies the commands to a video front end 2734, which is coupled to a media engine 2737. In some embodiments, the media engine 2737 includes a video quality engine (VQE) 2730 for video and image post-processing and a multi-format encoding / decoding (MFX) 2733 engine for providing hardware accelerated media data encoding and decoding. In some embodiments, the geometry pipeline 2736 and the media engine 2737 each generate execution threads for thread execution resources provided by at least one graphics core 2780A.

[0283] In some embodiments, the graphics processor 2700 includes scalable thread execution resources featuring modular cores 2780A-2780N (sometimes referred to as core slices), each of which has multiple sub-cores 2750A-550N, 2760A-2760N (sometimes referred to as core sub-slices). In some embodiments, the graphics processor 2700 can have any number of graphics cores 2780A to 2780N. In some embodiments, the graphics processor 2700 includes a graphics core 2780A, which has at least a first sub-core 2750A and a second sub-core 2760A. In other embodiments, the graphics processor is a low-power processor with a single sub-core (e.g., 2750A). In some embodiments, the graphics processor 2700 includes multiple graphics cores 2780A-2780N, each of which includes a group of first sub-cores 2750A-2750N and a group of second sub-cores 2760A-2760N. Each sub-core in the group of first sub-cores 2750A-2750N includes at least a first group of execution units 2752A-2752N and a media / texture sampler 2754A-2754N. Each sub-core in the group of second sub-cores 2760A-2760N includes at least a second group of execution units 2762A-2762N and a sampler 2764A-2764N. In some embodiments, each sub-core 2750A-2750N, 2760A-2760N shares a group of shared resources 2770A-2770N. In some embodiments, the shared resources include a shared cache memory and a pixel operation logic. Other shared resources may also be included in various embodiments of the graphics processor.

[0284] Demonstration of additional execution units

[0285] Fig.28 Thread execution logic 2800 is shown, comprising an array of processing elements employed in some embodiments of a GPE. Fig.28 Elements having the same reference number (or name) as elements of any other figure herein may operate or function in any manner similar to that described elsewhere herein, but are not limited to such.

[0286] In some embodiments, thread execution logic 2800 includes a shader processor 2802, a thread dispatcher 2804, an instruction cache 2806, a scalable execution unit array including a plurality of execution units 2808A-2808N, a sampler 2810, a data cache 2812, and a data port 2814. In one embodiment, the scalable execution unit array can be dynamically scaled by enabling or disabling one or more execution units (e.g., any of execution units 2808A, 2808B, 2808C, 2808D to 2808N-1 and 2808N) based on the computational requirements of the workload. In one embodiment, the included components are interconnected via an interconnect structure that links to each of the components. In some embodiments, thread execution logic 2800 includes one or more connections to a memory (such as a system memory or cache memory) through one or more of the instruction cache 2806, the data port 2814, the sampler 2810, and the execution units 2808A-2808N. In some embodiments, each execution unit (e.g., 2808A) is an independently programmable general-purpose computing unit capable of executing multiple simultaneous hardware threads while processing multiple data elements in parallel for each thread. In various embodiments, the array of execution units 2808A-2808N is scalable to include any number of separate execution units.

[0287] In some embodiments, execution units 2808A-2808N are primarily used to execute shader programs. Shader processor 2802 can process various shader programs and dispatch execution threads associated with the shader programs via thread dispatcher 2804. In one embodiment, thread dispatcher includes logic for arbitrating thread initiation requests from graphics and media pipelines and instantiating the requested threads on one or more execution units in execution units 2808A-2808N. For example, the geometry pipeline (e.g., Fig. 27 2736) can dispatch vertex, tessellation or geometry shaders to thread execution logic 2800 ( Fig.28 ) for processing. In some embodiments, thread dispatcher 2804 may also handle runtime thread spawning requests from executing shader programs.

[0288] In some embodiments, execution units 2808A-2808N support an instruction set including native support for many standard 3D graphics shader instructions, so that shader programs from graphics libraries (e.g., Direct 3D and OpenGL) are executed with minimal conversion. The execution unit supports vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders), and general processing (e.g., compute and media shaders). Each of the execution units 2808A-2808N has the ability of multi-issue single instruction multiple data (SIMD) execution, and multi-threaded operation enables efficient execution environment in the face of high latency memory access. Each hardware thread within each execution unit has a dedicated high-bandwidth register file and associated independent thread state. For pipelines with integer, single and double precision floating point operations, SIMD branching capabilities, logical operations, transcendental operations, and other miscellaneous operation capabilities, execution is multiple releases per clock. While waiting for data from memory or one of the shared functions, dependency logic within execution units 2808A-2808N puts the waiting thread to sleep until the requested data has returned. While the waiting thread is sleeping, hardware resources may be dedicated to processing other threads. For example, during a delay associated with a vertex shader operation, an execution unit may execute operations of a pixel shader, a fragment shader, or another type of shader program including a different vertex shader.

[0289] Each of the execution units 2808A-2808N operates on an array of data elements. The number of data elements is the "execution size," or number of lanes for an instruction. An execution lane is a logical unit used for the execution of data element access, masking, and flow control within an instruction. The number of lanes may be independent of the number of physical arithmetic logic units (ALUs) or floating point units (FPUs) for a particular graphics processor. In some embodiments, the execution units 2808A-2808N support integer and floating point data types.

[0290] The execution unit instruction set includes SIMD instructions. Various data elements can be stored in registers as compressed data types, and the execution unit will process various elements based on the data size of the element. For example, when a 256-bit wide vector is operated, the 256-bit vector is stored in a register and the execution unit operates on the vector according to four separate 64-bit compressed data elements (data elements of quadruple word length (QW) size), eight separate 32-bit compressed data elements (data elements of double word (DW) size), sixteen separate 16-bit compressed data elements (data elements of word (W) size), or thirty-two separate 8-bit data elements (data elements of byte (B) size). However, different vector widths and register sizes are possible.

[0291] One or more internal instruction caches (e.g., 2806) are included in the thread execution logic 2800 to cache thread instructions for the execution unit. In some embodiments, one or more data caches (e.g., 2812) are included to cache thread data during thread execution. In some embodiments, a sampler 2810 is included to provide texture sampling for 3D operations and media sampling for media operations. In some embodiments, the sampler 2810 includes a dedicated texture or media sampling function to process the texture or media data during the sampling process before providing the sampled data to the execution unit.

[0292] During execution, the graphics and media pipeline sends thread initiation requests to the thread execution logic 2800 via thread mass generation and dispatch logic. Once a set of geometric objects has been processed and rasterized into pixel data, the pixel processor logic (e.g., pixel shader logic, fragment shader logic, etc.) within the shader processor 2802 is called to further calculate output information and cause the results to be written to the output surface (e.g., color buffer, depth buffer, stencil printing buffer, etc.). In some embodiments, the pixel shader or fragment shader calculates the values ​​of various vertex attributes to be interpolated across the rasterized object. In some embodiments, the pixel processor logic within the shader processor 2802 then executes the pixel or fragment shader program supplied by the application programming interface (API). In order to execute the shader program, the shader processor 2802 dispatches the thread to the execution unit (e.g., 2808A) via the thread dispatcher 2804. In some embodiments, the pixel shader 2802 uses the texture sampling logic in the sampler 2810 to access the texture data in the texture map stored in the memory. Arithmetic operations on texture data and input geometry data compute pixel color data for each geometry fragment, or discard one or more pixels from further processing.

[0293] In some embodiments, data port 2814 provides a memory access mechanism for thread execution logic 2800 to output processed data to memory for processing on the graphics processor output pipeline. In some embodiments, data port 2814 includes or is coupled to one or more cache memories (e.g., data cache 2812) to cache data for memory access via the data port.

[0294] Fig.292900 is a block diagram illustrating a graphics processor instruction format 2900 according to some embodiments. In one or more embodiments, a graphics processor execution unit supports an instruction set having instructions in multiple formats. Solid line blocks illustrate components that are generally included in an execution unit instruction, while dashed lines include components that are optional or included only in a subset of instructions. In some embodiments, the instruction format 2900 described and illustrated are macroinstructions because they are instructions supplied to the execution unit, as opposed to micro-operations caused by instruction decoding once the instruction is processed.

[0295] In some embodiments, the graphics processor execution unit natively supports instructions in 128-bit instruction format 2910. Based on the selected instruction, instruction options, and the number of operands, a 64-bit compressed instruction format 2930 may be used for some instructions. The native 128-bit instruction format 2910 provides access to all instruction options, while some options and operations are restricted to 64-bit format 2930. The native instructions available in 64-bit format 2930 vary from embodiment to embodiment. In some embodiments, instructions are partially compressed using a set of index values ​​in index field 2913. The execution unit hardware references a set of compression tables based on the index values ​​and uses the compression table output to reconstruct native instructions in 128-bit instruction format 2910.

[0296] For each format, the instruction opcode 2912 defines the operation to be performed by the execution unit. The execution unit executes each instruction in parallel across multiple data elements of each operand. For example, in response to an add instruction, the execution unit performs a simultaneous add operation across each color channel, each color channel representing a texture element or a picture element. By default, the execution unit executes each instruction across all data channels of the operand. In some embodiments, the instruction control field 2914 enables control of certain execution options, such as channel selection (e.g., prediction) and data channel sorting (e.g., mixing). For instructions using the 128-bit instruction format 2910, the execution size field 2916 limits the number of data channels that will be executed in parallel. In some embodiments, the execution size field 2916 is not available for use in the 64-bit compressed instruction format 2930.

[0297] Some execution unit instructions have up to three operands, including two source operands - src0 2920, src1 2922 and a destination 2918. In some embodiments, the execution unit supports dual destination instructions, where one of the destinations is implicit. Data manipulation instructions may have a third source operand (e.g., SRC2 2924), where the instruction opcode 2912 determines the number of source operands. The last source operand of an instruction may be an immediate (e.g., hard-coded) value passed with the instruction.

[0298] In some embodiments, the 128-bit instruction format 2910 includes an access / addressing mode field 2926 that specifies, for example, whether direct register addressing mode or indirect register addressing mode is used. When direct register addressing mode is used, the register address of one or more operands is provided directly by bits in the instruction.

[0299] In some embodiments, the 128-bit instruction format 2910 includes an access / addressing mode field 2926, which specifies the addressing mode and / or access mode of the instruction. In one embodiment, the access mode is used to define the data access alignment for the instruction. Some embodiments support access modes including 16-byte aligned access modes and 1-byte aligned access modes, wherein the byte alignment of the access mode determines the access alignment of the instruction operands. For example, when in the first mode, the instruction can use byte-aligned addressing for source operands and destination operands, and when in the second mode, the instruction can use 16-byte aligned addressing for all source operands and destination operands.

[0300] In one embodiment, the addressing mode portion of the access / addressing mode field 2926 determines whether the instruction uses direct addressing or indirect addressing. When direct register addressing mode is used, the bits in the instruction directly provide the register address of one or more operands. When indirect register addressing mode is used, the register address of one or more operands can be calculated based on the address register value and the address immediate field in the instruction.

[0301] In some embodiments, instructions are grouped based on the opcode 2912 bit field to simplify opcode decoding 2940. For 8-bit opcodes, bits 4, 5, and 6 allow the execution unit to determine the type of opcode. The precise opcode grouping shown is exemplary only. In some embodiments, the move and logic opcode group 2942 includes data movement and logic instructions (e.g., move (mov), compare (cmp)). In some embodiments, the move and logic group 2942 shares five most significant bits (MSBs), where the move (mov) instruction takes the form of 0000xxxxb and the logic instruction takes the form of 0001xxxxb. The flow control instruction group 2944 (e.g., call, jump (jmp)) includes instructions in the form of 0010xxxxb (e.g., 0x20). The miscellaneous instruction group 2946 includes a mixture of instructions, including synchronization instructions (e.g., wait, send) in the form of 0011xxxxb (e.g., 0x30). The parallel math instruction group 2948 includes component-wise arithmetic instructions (e.g., add, multiply (mul)) in the form of 0100xxxxb (e.g., 0x40). The parallel math group 2948 performs arithmetic operations in parallel across data lanes. The vector math group 2950 includes arithmetic instructions (e.g., dp4) in the form of 0101xxxxb (e.g., 0x50). The vector math group performs arithmetic on vector operands, such as dot product calculations.

[0302] Demonstrating additional graphics pipeline

[0303] Fig.30 is a block diagram of another embodiment of a graphics processor 3000 . Fig.30 Elements having the same reference number (or name) as elements of any other figure herein may operate or function in any manner similar to that described elsewhere herein, but are not limited to such.

[0304] In some embodiments, the graphics processor 3000 includes a graphics pipeline 3020, a media pipeline 3030, a display engine 3040, a thread execution logic 3050, and a rendering output pipeline 3070. In some embodiments, the graphics processor 3000 is a graphics processor within a multi-core processing system that includes one or more general-purpose processing cores. The graphics processor is controlled by register writes to one or more control registers (not shown) or via commands issued to the graphics processor 3000 through the ring interconnect 3002. In some embodiments, the ring interconnect 3002 couples the graphics processor 3000 to other processing components, such as other graphics processors or general-purpose processors. Commands from the ring interconnect 3002 are interpreted by a command streamer 3003, which supplies instructions to separate components of the graphics pipeline 3020 or the media pipeline 3030.

[0305] In some embodiments, command streamer 3003 directs the operation of vertex fetcher 3005, which reads vertex data from memory and executes vertex processing commands provided by command streamer 3003. In some embodiments, vertex fetcher 3005 provides vertex data to vertex shader 3007, which performs coordinate space transformation and lighting operations on each vertex. In some embodiments, vertex fetcher 3005 and vertex shader 3007 execute vertex processing instructions by dispatching execution threads to execution units 3052A-3052B via thread dispatcher 3031.

[0306] In some embodiments, execution units 3052A-3052B are arrays of vector processors with instruction sets for performing graphics and media operations. In some embodiments, execution units 3052A-3052B have an attached L1 cache 3051 that is specific to each array or shared between arrays. The cache can be configured as a data cache, an instruction cache, or a single cache that is partitioned to contain data and instructions in different partitions.

[0307] In some embodiments, the graphics pipeline 3020 includes a tessellation component for performing hardware-accelerated tessellation of 3D objects. In some embodiments, the programmable hull shader 811 configures the tessellation operation. The programmable domain shader 817 provides back-end evaluation of the tessellation output. The tessellation 3013 operates at the direction of the hull shader 3011 and contains dedicated logic for generating a set of detailed geometric objects based on a coarse geometric model, which are provided as input to the graphics pipeline 3020. In some embodiments, if tessellation is not used, the tessellation components (e.g., the hull shader 3011, the tessellation 3013, and the domain shader 3017) can be bypassed.

[0308] In some embodiments, the complete geometric object may be processed by the geometry shader 3019 via one or more threads dispatched to the execution units 3052A-3052B, or may proceed directly to the clipper 3029. In some embodiments, the geometry shader operates on the entire geometric object rather than on vertices or vertex patches as in previous stages of the graphics pipeline. If tessellation is disabled, the geometry shader 3019 receives input from the vertex shader 3007. In some embodiments, the geometry shader 3019 may be programmed by a geometry shader program to perform geometry tessellation when the tessellation unit is disabled.

[0309] Before rasterization, the clipper 3029 processes the vertex data. The clipper 3029 can be a fixed function clipper or a programmable clipper with clipping and geometry shader functions. In some embodiments, the rasterizer and depth test component 3073 in the render output pipeline 3070 dispatches a pixel shader to convert the geometric object into its per-pixel representation. In some embodiments, the pixel shader logic is included in the thread execution logic 3050. In some embodiments, the application can bypass the rasterizer and depth test component 3073 and access the unrasterized vertex data via the outflow unit 3023.

[0310] Graphics processor 3000 has an interconnect bus, interconnect structure, or some other interconnect mechanism that allows data and messages to be passed between the main components of the processor. In some embodiments, execution units 3052A-3052B and associated cache(s) 3051, texture and media samplers 3054, and texture / sampler cache 3058 are interconnected via data ports 3056 to perform memory accesses and communicate with the rendering output pipeline components of the processor. In some embodiments, samplers 3054, caches 3051, 3058, and execution units 3052A-3052B each have separate memory access paths.

[0311] In some embodiments, the rendering output pipeline 3070 includes a rasterizer and depth test component 3073, which converts vertex-based objects into associated pixel-based representations. In some embodiments, the rasterizer logic includes a windower / masker unit for performing fixed-function triangle and line rasterization. An associated rendering cache 3078 and depth cache 3079 are also available in some embodiments. The pixel operation component 3077 performs pixel-based operations on data, but in some instances, pixel operations associated with 2D operations (e.g., using mixed bit block image transfer) are performed by the 2D engine 3041, or replaced by the display controller 3043 using overlapping display planes at display time. In some embodiments, a shared L3 cache 3075 can be used for all graphics components, allowing data to be shared without using main system memory.

[0312] In some embodiments, the graphics processor media pipeline 3030 includes a media engine 3037 and a video front end 3034. In some embodiments, the video front end 3034 receives pipeline commands from the command streamer 3003. In some embodiments, the media pipeline 3030 includes a separate command streamer. In some embodiments, the video front end 3034 processes the media commands before sending them to the media engine 3037. In some embodiments, the media engine 3037 includes a thread spawning function to spawn threads for dispatching to the thread execution logic 3050 via the thread dispatcher 3031.

[0313] In some embodiments, the graphics processor 3000 includes a display engine 3040. In some embodiments, the display engine 3040 is external to the processor 3000 and is coupled to the graphics processor via the ring interconnect 3002 or some other interconnect bus or structure. In some embodiments, the display engine 3040 includes a 2D engine 3041 and a display controller 3043. In some embodiments, the display engine 3040 contains dedicated logic that can operate independently of the 3D pipeline. In some embodiments, the display controller 3043 is coupled to a display device (not shown), which can be a system integrated display device (such as in a laptop computer), or an external display device attached via a display device connector.

[0314] In some embodiments, graphics pipeline 3020 and media pipeline 3030 can be configured to perform operations based on multiple graphics and media programming interfaces and are not specific to any application programming interface (API). In some embodiments, driver software for graphics processor converts API calls specific to specific graphics or media libraries into commands that can be processed by graphics processor. In some embodiments, support is provided for Open Graphics Library (OpenGL), Open Computing Language (OpenCL) and / or Vulkan graphics and computing APIs all from Khronos Group. In some embodiments, support can also be provided for Direct3D library from Microsoft. In some embodiments, a combination of these libraries can be supported. Support can also be provided for open source computer vision library (OpenCV). If a mapping can be made from the pipeline of a future API to the pipeline of a graphics processor, a future API with a compatible 3D pipeline will also be supported.

[0315] Graphics pipeline programming

[0316] Fig.31A is a block diagram illustrating a graphics processor command format 3100 according to some embodiments. Fig.31B is a block diagram illustrating a graphics processor command sequence 3110 according to an embodiment. Fig.31AThe solid line blocks in show components that are generally included in a graphics command, while the dashed lines include components that are optional or included only in a subset of the graphics command. Fig.31A The exemplary graphics processor command format 3100 includes a data field for identifying the target client 3102 of the command, a command operation code (opcode) 3104, and associated data 3106 of the command. Some commands also include a sub-opcode 3105 and a command size 3108.

[0317] In some embodiments, client 3102 specifies the client unit of the graphics device that processes the command data. In some embodiments, the graphics processor command parser checks the client field of each command to adjust the further processing of the command and routes the command data to the appropriate client unit. In some embodiments, the graphics processor client unit includes a memory interface unit, a rendering unit, a 2D unit, a 3D unit, and a media unit. Each client unit has a corresponding processing pipeline for processing the command. Once the command is received by the client unit, the client unit reads the opcode 3104 and the sub-opcode 3105 (if present) to determine the operation to be performed. The client unit uses the information in the data field 3106 to execute the command. For some commands, an explicit command size 3108 is expected to specify the size of the command. In some embodiments, the command parser automatically determines the size of at least some of the commands in the command based on the command opcode. In some embodiments, the commands are aligned via multiples of double words.

[0318] Fig.31B An exemplary graphics processor command sequence 3110 is shown in the flow chart in FIG. 31. In some embodiments, software or firmware of a data processing system featuring an embodiment of a graphics processor uses a version of the command sequence shown to establish, execute, and terminate a set of graphics operations. The sample command sequence is shown and described for purposes of example only, as embodiments are not limited to these particular commands or this command sequence. Moreover, the commands may be issued as a batch of commands in a command sequence so that the graphics processor will process the sequence of commands at least partially simultaneously.

[0319] In some embodiments, the graphics processor command sequence 3110 may begin with a pipeline dump clear command 3112 to cause any active graphics pipeline to complete currently pending commands for that pipeline. In some embodiments, the 3D pipeline 3122 and the media pipeline 3124 do not operate simultaneously. The pipeline dump clear is performed to cause the active graphics pipeline to complete any pending commands. In response to the pipeline dump clear, the command parser for the graphics processor will suspend command processing until the active drawing engine completes pending operations and the associated read cache is invalid. Optionally, any data marked as 'dirty' in the rendering cache can be dumped to memory. In some embodiments, the pipeline dump clear command 3112 can be used for pipeline synchronization or before the graphics processor is placed in a low power state.

[0320] In some embodiments, when a command sequence requires the graphics processor to explicitly switch between pipelines, a pipeline select command 3113 is used. In some embodiments, a pipeline select command 3113 is only required once within an execution context before issuing pipeline commands unless the context is to issue commands for both pipelines. In some embodiments, a pipeline flush command 3112 is required immediately prior to a pipeline switch via a pipeline select command 3113.

[0321] In some embodiments, pipeline control commands 3114 configure the graphics pipeline for operation and are used to program the 3D pipeline 3122 and the media pipeline 3124. In some embodiments, pipeline control commands 3114 configure pipeline states for the active pipeline. In one embodiment, pipeline control commands 3114 are used for pipeline synchronization and for clearing data from one or more cache memories within the active pipeline before processing a batch of commands.

[0322] In some embodiments, return buffer state commands 3116 are used to configure a set of return buffers for the corresponding pipeline to write data. Some pipeline operations require the allocation, selection, or configuration of one or more return buffers into which intermediate data is written during processing. In some embodiments, the graphics processor also uses one or more return buffers to store output data and perform cross-thread communication. In some embodiments, return buffer state 3116 includes selecting the size and number of return buffers to be used for a set of pipeline operations.

[0323] The remaining commands in the command sequence differ based on the active pipeline for operation. Based on pipeline determination 3120 , the command sequence is suitable for either 3D pipeline 3122 starting with 3D pipeline state 3130 or media pipeline 3124 starting in media pipeline state 3140 .

[0324] The commands for configuring the 3D pipeline state 3130 include 3D state setting commands for vertex buffer state, vertex element state, constant color state, depth buffer state, and other state variables to be configured before processing 3D primitive commands. The values ​​of these commands are determined at least in part based on the specific 3D API in use. In some embodiments, the 3D pipeline state 3130 commands can also selectively disable or bypass certain pipeline elements if those elements are not to be used.

[0325] In some embodiments, 3D primitive 3132 commands are used to submit 3D primitives to be processed by the 3D pipeline. The commands and associated parameters passed to the graphics processor via the 3D primitive 3132 commands are forwarded to the vertex acquisition function in the graphics pipeline. The vertex acquisition function uses the 3D primitive 3132 command data to generate a vertex data structure. The vertex data structure is stored in one or more return buffers. In some embodiments, the 3D primitive 3132 commands are used to perform vertex operations on the 3D primitives via a vertex shader. In order to process the vertex shader, the 3D pipeline 3122 dispatches the shader execution thread to the graphics processor execution unit.

[0326] In some embodiments, the 3D pipeline 3122 is triggered via an execution 3134 command or event. In some embodiments, a register write triggers the command execution. In some embodiments, the execution is triggered via a 'go' or 'kick' command in a command sequence. In one embodiment, a pipeline synchronization command is used to trigger the command execution to dump and clear the command sequence through the graphics pipeline. The 3D pipeline will perform geometry processing for 3D primitives. Once the operation is completed, the resulting geometric objects are rasterized and the pixel engine shades the resulting pixels. Additional commands for controlling pixel shading and pixel backend operations may also be included for those operations.

[0327] In some embodiments, when performing media operations, the graphics processor command sequence 3110 follows the media pipeline 3124 path. Generally, the specific use and manner of programming for the media pipeline 3124 depends on the media or computing operations to be performed. During media decoding, specific media decoding operations can be offloaded to the media pipeline. In some embodiments, the media pipeline can also be bypassed, and resources provided by one or more general processing cores can be used to perform media decoding in whole or in part. In one embodiment, the media pipeline also includes elements for general purpose graphics processor unit (GPGPU) operations, where the graphics processor is used to perform SIMD vector operations using compute shader programs that are not explicitly related to rendering graphics primitives.

[0328] In some embodiments, the media pipeline 3124 is configured in a similar manner to the 3D pipeline 3122. A set of commands for configuring the media pipeline state 3140 is dispatched or placed into the command queue, before the media object commands 3142. In some embodiments, the media pipeline state commands 3140 include data for configuring the media pipeline elements that will be used to process the media objects. This includes data for configuring the video decoding and video encoding logic within the media pipeline, such as encoding or decoding formats. In some embodiments, the media pipeline state commands 3140 also support the use of one or more pointers to "indirect" state elements that contain a batch of state settings.

[0329] In some embodiments, media object commands 3142 supply pointers to media objects for processing by the media pipeline. The media object includes a memory buffer that contains video data to be processed. In some embodiments, all media pipeline states must be valid before issuing media object commands 3142. Once the pipeline states are configured and media object commands 3142 are queued, media pipeline 3124 is triggered via an execution command 3144 or an equivalent execution event (e.g., a register write). The output from media pipeline 3124 can then be post-processed by operations provided by 3D pipeline 3122 or media pipeline 3124. In some embodiments, GPGPU operations are configured and executed in a manner similar to media operations.

[0330] Graphics software architecture

[0331] Fig.32 An exemplary graphics software architecture of a data processing system 3200 according to some embodiments is shown. In some embodiments, the software architecture includes a 3D graphics application 3210, an operating system 3220, and at least one processor 3230. In some embodiments, processor 3230 includes a graphics processor 3232 and one or more general purpose processor cores 3234. Graphics application 3210 and operating system 3220 are each executed in a system memory 3250 of the data processing system.

[0332] In some embodiments, the 3D graphics application 3210 includes one or more shader programs including shader instructions 3212. The shader language instructions may be in a high-level shader language, such as High Level Shader Language (HLSL) or OpenGL Shader Language (GLSL). The application also includes executable instructions 3214 in a machine language suitable for execution by the general purpose processor core 3234. The application also includes graphics objects 3216 defined by vertex data.

[0333] In some embodiments, the operating system 3220 is a Microsoft® Windows® operating system from Microsoft Corporation, a proprietary UNIX-like operating system, or an open source UNIX-like operating system using a variant of the Linux kernel. The operating system 3220 can support graphics APIs 3222, such as Direct3D API, OpenGL API, or Vulkan API. When the Direct3D API is in use, the operating system 3220 uses a front-end shader compiler 3224 to compile any shader instructions 3212 in HLSL into a lower-level shader language. The compilation can be a just-in-time (JIT) compilation, or the application can perform shader precompilation. In some embodiments, during the compilation of the 3D graphics application 3210, a high-level shader is compiled into a low-level shader. In some embodiments, shader instructions 3212 are provided in an intermediate form, such as a version of the standard portable intermediate representation (SPIR) used by the Vulkan API.

[0334] In some embodiments, the user mode graphics driver 3226 includes a backend shader compiler 3227 for converting shader instructions 3212 into hardware specific representations. When the OpenGL API is in use, the shader instructions 3212 in the GLSL high level language are passed to the user mode graphics driver 3226 for compilation. In some embodiments, the user mode graphics driver 3226 uses the operating system kernel mode functions 3228 to communicate with the kernel mode graphics driver 3229. In some embodiments, the kernel mode graphics driver 3229 communicates with the graphics processor 3232 to dispatch commands and instructions.

[0335] IP Core Implementation

[0336] One or more aspects of at least one embodiment may be implemented by representative code stored on a machine-readable medium, which represents and / or defines logic within an integrated circuit such as a processor. For example, a machine-readable medium may include instructions representing various logic within a processor. When read by a machine, the instructions may cause the machine to manufacture logic for performing the techniques described herein. Such representations (referred to as "IP cores") are reusable units of logic for an integrated circuit that may be stored on a tangible, machine-readable medium as a hardware model describing the structure of the integrated circuit. The hardware model may be supplied to various consumers or manufacturing facilities that load the hardware model on a manufacturing machine that manufactures the integrated circuit. The integrated circuit may be manufactured so that the circuit performs the operations described in association with any of the embodiments described herein.

[0337] Fig.3333 is a block diagram showing an IP core development system 3300 that can be used to manufacture an integrated circuit to perform operations according to an embodiment. The IP core development system 3300 can be used to generate modular, reusable designs that can be incorporated into a larger design or used to build an entire integrated circuit (e.g., a SOC integrated circuit). The design facility 3330 can generate a software simulation 3310 of the IP core design in a high-level programming language (e.g., C / C++). The software simulation 3310 can be used to design, test, and verify the behavior of the IP core using a simulation model 3312. The simulation model 3312 can include functional, behavioral, and / or timing simulations. A register transfer level (RTL) design 3315 can then be created or synthesized from the simulation model 3312. The RTL design 3315 is an abstraction of the behavior of an integrated circuit that models the flow of digital signals between hardware registers, including associated logic that is executed using the modeled digital signals. In addition to the RTL design 3315, a lower level design at the logic level or transistor level can also be created, designed, or synthesized. Therefore, the specific details of the initial design and simulation may vary.

[0338] The RTL design 3315 or equivalent can be further synthesized by the design facility into a hardware model 3320, which can be in hardware description language (HDL) or some other representation of physical design data. The HDL can be further simulated or tested to verify the IP core design. Non-volatile memory 3340 (e.g., hard disk, flash memory, or any non-volatile storage medium) can be used to store the IP core design for delivery to a third-party manufacturing facility 3365. Alternatively, the IP core design can be transmitted (e.g., via the Internet) via a wired connection 3350 or a wireless connection 3360. The manufacturing facility 3365 can then manufacture an integrated circuit based at least in part on the IP core design. The manufactured integrated circuit can be configured to perform operations in accordance with at least one embodiment described herein.

[0339] Demonstration System-on-Chip Integrated Circuit

[0340] Figure 34-36 An exemplary integrated circuit and associated graphics processor that can be manufactured using one or more IP cores according to various embodiments described herein are shown. In addition to what is shown, other logic and circuits may also be included, including additional graphics processors / cores, peripheral interface controllers, or general purpose processor cores.

[0341] Fig.3434 is a block diagram illustrating an exemplary system-on-chip integrated circuit 3400 that can be manufactured using one or more IP cores according to an embodiment. The exemplary integrated circuit 3400 includes one or more application processors 3405 (e.g., CPUs), at least one graphics processor 3410, and may additionally include an image processor 3415 and / or a video processor 3420, any of which may be modular IP cores from the same or multiple different design facilities. The integrated circuit 3400 includes peripheral or bus logic, which includes a USB controller 3425, a UART controller 3430, an SPI / SDIO controller 3435, and an I 2 S / I 2 C controller 3440. In addition, the integrated circuit may include a display device 3445 coupled to one or more of a high-definition multimedia interface (HDMI) controller 3450 and a mobile industry processor interface (MIPI) display interface 3455. Storage may be provided by a flash subsystem 3460 including flash memory and a flash controller. A memory interface may be provided via a memory controller 3465 for access to SDRAM or SRAM memory devices. Some integrated circuits additionally include an embedded security engine 3470.

[0342] Fig.35 is a block diagram illustrating an exemplary graphics processor 3510 of a system-on-chip integrated circuit that may be fabricated using one or more IP cores according to an embodiment. The graphics processor 3510 may be Fig.34 A variation of the graphics processor 3410 of FIG. The graphics processor 3510 includes a vertex processor 3505 and one or more fragment processors 3515A-3515N (e.g., 3515A, 3515B, 3515C, 3515D to 3515N-1 and 3515N). The graphics processor 3510 can execute different shader programs via separate logic, so that the vertex processor 3505 is optimized to perform operations for vertex shader programs, while the one or more fragment processors 3515A-3515N perform fragment (e.g., pixel) shading operations for fragment or pixel shader programs. The vertex processor 3505 performs the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. (Multiple) fragment processors 3515A-3515N use the primitives and vertex data generated by the vertex processor 3505 to generate a frame buffer displayed on a display device. In one embodiment, the fragment processor(s) 3515A-3515N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform similar operations as pixel shader programs as provided in the Direct3D API.

[0343] The graphics processor 3510 additionally includes one or more memory management units (MMUs) 3520A-3520B, caches 3525A-3525B, and circuit interconnects 3530A-3530B. The one or more MMUs 3520A-3520B provide virtual to physical address mappings for the graphics processor 3510, including for the vertex processor 3505 and / or fragment processor(s) 3515A-3515N, which may reference vertex or image / texture data stored in memory in addition to vertex or image / texture data stored in the one or more caches 3525A-3525B. In one embodiment, the one or more MMUs 3520A-3520B may be synchronized with other MMUs within the system, including with Fig.34 One or more MMUs associated with the one or more application processors 3405, image processors 3415, and / or video processors 3420 enable each processor 3405-3420 to participate in a shared or unified virtual memory system. According to an embodiment, the one or more circuit interconnects 3530A-3530B enable the graphics processor 3510 to interface with other IP cores within the SoC via an internal bus of the SoC or via a direct connection.

[0344] Fig.36 is a block diagram illustrating an additional exemplary graphics processor 3610 of a system-on-chip integrated circuit that may be fabricated using one or more IP cores in accordance with an embodiment. The graphics processor 3610 may be Fig.34 A variant of the graphics processor 3410. The graphics processor 3610 includes Fig.35 The one or more MMUs 3520A-3520B, caches 3525A-3525B, and circuit interconnects 3530A-3530B of the integrated circuit 3500.

[0345] Graphics processor 3610 includes one or more shader cores 3615A-3615N (e.g., 3615A, 3615B, 3615C, 3615D, 3615E, 3615F through 3615N-1 and 3615N) that provide a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. The exact number of shader cores present may vary among embodiments and implementations. In addition, the graphics processor 3610 includes an inter-core task manager 3605, which acts as a thread dispatcher for dispatching execution threads to one or more shader cores 3615A-3615N, and a tile unit 3618 for accelerating tile operations for tile-based rendering, wherein rendering operations for a scene are subdivided in image space, for example, for exploiting local spatial coherence within a scene or for optimizing use of internal caches.

[0346] The present invention also provides a set of technical solutions as follows:

[0347] 1. A general-purpose graphics processing unit, comprising:

[0348] A dynamic precision floating point unit includes a control unit having precision tracking hardware logic to track an available number of precision bits of computational data relative to a target precision, wherein the dynamic precision floating point unit includes computational logic to output data at multiple precisions.

[0349] 2. A general purpose graphics processing unit as described in technical solution 1, wherein the dynamic precision floating point unit includes a register set to store input data and intermediate data with multiple precisions.

[0350] 3. A general purpose graphics processing unit as described in technical solution 2, wherein the register set includes an error accumulator to track accumulated errors on a floating point operation set.

[0351] 4. In the general graphics processing unit as described in Technical Solution 1, the dynamic precision floating-point unit includes a valid digit block to perform the valid digit part of the floating-point calculation, and the valid digit block includes a dynamic precision adder, which can be configured to add or subtract input data with multiple precisions.

[0352] 5. In the general purpose graphics processing unit as described in Technical Solution 4, the effective bit number block includes a dynamic precision multiplier, which can be configured to add, multiply or divide the input data with multiple precisions.

[0353] 6. In the general graphics processing unit as described in Technical Solution 5, the dynamic precision floating-point unit includes an exponent block to perform the exponent part of the floating-point calculation, and the exponent block includes a dynamic precision adder, which can be configured to add or subtract the exponent of the input data with multiple precisions.

[0354] 7. In the general graphics processing unit as described in Technical Solution 6, the exponent block and the valid bit block are used to perform a first floating-point operation to output a first output value with 16-bit precision.

[0355] 8. In the general graphics processing unit as described in Technical Solution 7, the exponent block and the valid digit block are used to perform a second operation to output a second output value with 32-bit precision.

[0356] 9. In the general graphics processing unit as described in Technical Solution 8, the exponent block and the valid bit block are used to perform a third floating-point operation on input data having a 32-bit value to output a third output value having a 32-bit data type, and the third output value is generated with 16-bit precision.

[0357] 10. In the general purpose graphics processing unit as described in technical solution 9, the exponent block includes an 8-bit multiplier, and wherein the exponent block and the significand block can be configured to perform dual 8-bit integer operations.

[0358] 11. A method for performing variable precision operations in hardware of a general purpose graphics processing unit, the method comprising:

[0359] receiving a request to perform a numerical operation with a first precision;

[0360] performing the numerical operation using a number of bits associated with a second precision lower than the first precision;

[0361] generating an intermediate result with the second precision;

[0362] determining a loss of precision of the intermediate result; and

[0363] When the precision loss of the intermediate result is lower than a threshold, the result is outputted with the second precision.

[0364] 12. A method as described in technical solution 11, wherein the threshold is configurable via software logic.

[0365] 13. A method as described in technical solution 11, wherein the threshold is a default hardware value.

[0366] 14. The method according to technical solution 11 additionally comprises:

[0367] calculating remaining bits of a result when the loss of precision of the intermediate result is greater than the threshold; and

[0368] The result is outputted at the first precision.

[0369] 15. A method as described in technical solution 14, wherein performing the numerical operation using multiple bits associated with the second precision lower than the first precision includes performing the numerical operation using a first set of logic units and calculating the remaining bits of the result, and when the precision loss of the intermediate result is greater than the threshold, includes calculating the remaining bits of the result using a second set of logic units.

[0370] 16. A data processing system comprising:

[0371] a non-transitory machine-readable medium for storing instructions for execution by one or more processors of the data processing system; and

[0372] A general purpose graphics processing unit including a dynamic precision floating point unit including a control unit having precision tracking hardware logic to track an available number of precision bits of computational data relative to a target precision, wherein the dynamic precision floating point unit includes computational logic to output data at multiple precisions.

[0373] 17. A data processing system as described in technical solution 16, wherein the dynamic precision floating-point unit includes a register set to store input data and intermediate data with multiple precisions.

[0374] 18. A data processing system as described in technical solution 17, wherein the register set includes an error accumulator to track accumulated errors on a floating-point operation set.

[0375] 19. As a data processing system as described in technical solution 16, the dynamic precision floating-point unit includes a valid digit block to perform the valid digit part of the floating-point calculation, and the valid digit block includes a dynamic precision adder, which can be configured to add or subtract input data with multiple precisions.

[0376] 20. In the data processing system as described in Technical Solution 19, the effective bit number block includes a dynamic precision multiplier, which can be configured to add, multiply or divide the input data with multiple precisions.

[0377] The following clauses and / or examples relate to specific embodiments or examples thereof. Specific details in the examples may be used anywhere in one or more embodiments. Various features of different embodiments or examples may be combined in various ways with some features included and other features excluded to accommodate a wide variety of different applications. Examples may include subject matter such as methods, components for performing the actions of methods, and at least one machine-readable medium including instructions that, when executed by a machine, cause the machine to perform the actions of a method or device or system according to the embodiments and examples described herein. Various components may be components for performing the described operations or functions.

[0378] The embodiments described herein refer to a specific configuration of hardware (e.g., an application specific integrated circuit (ASIC)) configured to perform certain operations or have predetermined functionality. Such electronic devices typically include a collection of one or more processors coupled to one or more other components, such as one or more storage devices (non-temporary machine-readable storage media), user input / output devices (e.g., keyboards, touch screens, and / or displays), and network connections. The coupling of the processor collection and its other components is typically through one or more buses and bridges (also referred to as bus controllers). The storage devices and signals carrying network traffic represent one or more machine-readable storage media and machine-readable communication media, respectively. Therefore, the storage device of a given electronic device typically stores code and / or data for execution on a collection of one or more processors of the electronic device.

[0379] Of course, one or more parts of the embodiment can be implemented using different combinations of software, firmware and / or hardware. Throughout this detailed description, for the purpose of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that embodiments can be put into practice without some of these specific details. In some instances, well-known structures and functions are not described in detail to avoid obscuring the subject matter of the invention of the embodiment. Accordingly, the scope and spirit of the present invention should be judged according to the claims that follow.

Claims

1. An accelerator on a multi-chip module, the accelerator comprising: A stacked memory comprising a plurality of memory dies; as well as A graphics processing unit (GPU), the GPU being coupled to the stacked memory via one or more memory controllers, the GPU comprising a plurality of multiprocessors having a single instruction multiple thread (SIMT) architecture, the multiprocessors being configured to execute at least one single instruction, the at least one single instruction being configured to accelerate a linear algebra subroutine associated with a machine learning framework; The at least one single instruction is used to cause at least a portion of the GPU to perform a floating point operation on inputs having different precisions, the floating point operation being a two-dimensional matrix multiplication operation; wherein at least a portion of the plurality of multiprocessors comprises a mixed precision core, the mixed precision core being configured to execute the at least one single instruction thread, the mixed precision core comprising a floating point unit, the floating point unit being configured to execute a first operation of the thread with a first precision and a second operation of the thread with a second precision; wherein the first operation is a multiplication with two or more 16-bit floating point inputs and the second operation is an accumulation with 32-bit floating point inputs; The stacked memory is located on the same physical package as the GPU.

2. The accelerator of claim 1, wherein the stacked memory comprises a high bandwidth memory. 3 . The accelerator of claim 1 , wherein the mixed-precision core is configured to perform the first operation with 16-bit precision and the second operation with 32-bit precision.

4. The accelerator of claim 1, the mixed precision core being configurable to output a 16-bit floating point value from the two-dimensional matrix multiplication operation.

5. A method for accelerating a machine learning operation, the method comprising: decoding a single instruction on a graphics processing unit (GPU), the GPU having a single instruction multiple thread (SIMT) architecture, the GPU being coupled to a stacked memory via one or more memory controllers; and executing, via one or more multiprocessors within the GPU, the single instruction for causing at least a portion of the GPU to perform a two-dimensional matrix multiplication operation to accelerate a linear algebra subroutine associated with a machine learning framework, wherein executing the single instruction comprises executing a thread of the single instruction on a mixed precision core of the one or more multiprocessors, the mixed precision core comprising a floating point unit, the floating point unit being configured to perform a first operation of the thread at a first precision and a second operation of the thread at a second precision, wherein the first operation is a multiplication having at least one 16-bit floating point input and the second operation is an accumulation having a 32-bit floating point input; The stacked memory includes high bandwidth memory and is located on the same physical package as the GPU. The method of claim 5 , wherein the first precision is 16-bit precision and the second precision is 32-bit precision.

7. The method of claim 5, further comprising generating a 16-bit floating point output of the two-dimensional matrix multiplication operation.

8. A data processing system comprising: A stacked memory, the stacked memory comprising a plurality of memory dies, the stacked memory comprising a high bandwidth memory; as well as A graphics processing unit (GPU), the GPU being coupled to the stacked memory via one or more memory controllers, the GPU comprising a plurality of multiprocessors having a single instruction multiple thread (SIMT) architecture, wherein at least a portion of the plurality of multiprocessors comprises a mixed precision core, the mixed precision core being used to execute at least one thread of a single instruction, the at least one single instruction being used to accelerate a linear algebra subroutine associated with a machine learning framework, the mixed precision core comprising a floating point unit, the floating point unit being used to execute a first operation of the thread with a first precision and to execute a second operation of the thread with a second precision; as well as wherein the at least one single instruction is used to cause the mixed precision core to perform a thread of a two-dimensional matrix multiplication floating point operation on inputs having different precisions, the two-dimensional matrix multiplication operation comprising the first operation and the second operation, the first operation being a multiplication with two or more 16-bit floating point inputs and the second operation being an accumulation with 32-bit floating point inputs; The stacked memory is located on the same physical package as the GPU.

9. The data processing system of claim 8, wherein the mixed precision core is configured to perform the first operation with 16-bit precision and the second operation with 32-bit precision.

10. The data processing system of claim 8, the mixed precision core being configurable to output a 16-bit floating point value from the two-dimensional matrix multiplication operation.

11. A device for accelerating a machine learning operation, the device comprising: Means for decoding a single instruction on a graphics processing unit (GPU) having a single instruction multiple thread (SIMT) architecture, the GPU being coupled to a stacked memory via one or more memory controllers; and means for executing the single instruction via one or more multiprocessors within the GPU, the single instruction for causing at least a portion of the GPU to perform a two-dimensional matrix multiplication operation to accelerate a linear algebra subroutine associated with a machine learning framework, wherein the means for executing the single instruction comprises means for executing a thread of the single instruction on a mixed precision core of the one or more multiprocessors, the mixed precision core comprising a floating point unit, the floating point unit for executing a first operation of the thread at a first precision and a second operation of the thread at a second precision, wherein the first operation is a multiplication having at least one 16-bit floating point input and the second operation is an accumulation having a 32-bit floating point input; The stacked memory includes high bandwidth memory and is located on the same physical package as the GPU.

12. The apparatus of claim 11, wherein the first precision is 16-bit precision and the second precision is 32-bit precision.

13. The apparatus of claim 11, further comprising means for generating a 16-bit floating point output of the two-dimensional matrix multiplication operation.

14. A computer readable medium having stored thereon instructions which, when executed, cause a computing device to perform the method according to any one of claims 5 to 7.

Images