Integrated circuit device and method of manufacturing the same

Abstract

The invention is titled "Bitcell with multiple read bitlines." Various implementations described herein relate to an apparatus having a bitcell. The apparatus can include a horizontal bitline coupled to the bitcell. The horizontal bitline can include a plurality of first read bitlines disposed in a horizontal direction relative to the bitcell. The apparatus can include a vertical bitline coupled to the bitcell. The vertical bitline can include a plurality of second read bitlines disposed in a vertical direction relative to the bitcell.

Description

Background Technology

[0001] This section aims to provide information relevant to understanding the various techniques described herein. As the title of this section suggests, this is a discussion of related techniques and should in no way imply that they are prior art. Generally speaking, related techniques may or may not be considered prior art. Therefore, it should be understood that any statement in this section should be interpreted in this sense and does not constitute any endorsement of prior art.

[0002] In conventional computing architectures, some multipliers are typically designed to handle the large amounts of computation required by applications. This can lead to significant latency in complex multiplier processing when dealing with large numbers in cross-modal computations, such as matrices. These complex multiplier computations are used in machine learning applications, and some types of conventional multiplier designs are typically implemented using multi-bit logic built to handle large numbers. Additionally, other multiplier designs may utilize various other multi-bit symbolic logics built to handle large numbers. However, these types of complex multipliers often exhibit failure and latency issues due to complex and inefficient memory designs. Therefore, improvements are needed in the physical design implementation of some multiplier circuits to provide more efficient binary multiplication operations. Attached Figure Description

[0003] This document describes specific implementations of various techniques with reference to the accompanying drawings. However, it should be understood that the drawings merely illustrate the various specific implementations described herein and are not intended to limit the implementation methods of the various techniques described herein.

[0004] Figure 1 A diagram is shown illustrating memory circuitry associated with bit cells according to various specific implementations described herein.

[0005] Figure 2 A diagram of the bit cell structure according to various specific embodiments described herein is shown.

[0006] Figure 3 A diagram is shown of a memory array circuit having bit cells arranged in a 1×8 array, according to a specific embodiment described herein.

[0007] Figure 4 A diagram is shown of a memory array circuit having bit cells arranged in a 16×8 array, according to a specific embodiment described herein.

[0008] Figure 5 A diagram is shown of a memory array circuit having bit cells arranged in a 32×16 array, according to a specific embodiment described herein.

[0009] Figure 6A diagram is shown of a memory array circuit having bit cells arranged in a plurality of 32×16 array blocks, according to a specific embodiment described herein.

[0010] Figure 7 A diagram is shown of a memory array circuit having bit cells arranged in multiple 128×16 array groups according to a specific embodiment described herein.

[0011] Figure 8 A diagram is shown of a memory array circuit having bit cells arranged in an interleaved 64×16 array block, according to a specific embodiment described herein.

[0012] Figure 9 A diagram is shown of a memory array circuit having bit cells arranged in an interleaved 32×16 array block, according to a specific embodiment described herein.

[0013] Figures 10A to 10B A diagram is shown of a memory array circuit having bit cells arranged in multiple 128×16 array groups, according to a specific embodiment described herein. Detailed Implementation

[0014] The various specific implementations described herein refer to memory architectures with bit cell circuitry having multiple read bit lines. For example, the various schemes and techniques described herein can provide ultrafast, high-density memory architectures that can be used as custom memories for in-core matrix accelerators. Some aspects of the various schemes and techniques described herein provide sixteen (16) entries, each entry having 64 bytes, and one (1) read or one (1) write per cycle. Additionally, the various schemes and techniques described herein can provide write operations that can be configured to update all 64 bytes of an entry in a single cycle. Furthermore, the various schemes and techniques described herein can also provide multiple modes for read operations, such as, for example, single-entry reads and block reads. For example, a single-entry read can refer to reading all 64 bytes of an entry in a single cycle (i.e., reading 512 bits), and a block read can refer to reading the same 4 bytes for all 16 entries in a single cycle (i.e., reading 512 bits).

[0015] In some implementations, the various schemes and techniques described herein can provide write operations, such as updating all 64 bytes of an entry in a single cycle by writing data to four (4) 128×16-bit cell groups via activating a single write word line (WWL), where the technique is used to write 512 bits in a single cycle. Additionally, in some implementations, the various schemes and techniques described herein can provide entry read operations, such as reading all 64 bytes of an entry in a single cycle by reading data from four (4) 128×16-bit cell groups via activating a single read word line (RWL), where the technique is used to read 512 bits in a single cycle. Furthermore, in some implementations, the various schemes and techniques described herein can provide block read operations, such as reading a 32×16-bit cell array in a single cycle by reading data from a 512-bit block in a single cycle.

[0016] This article will refer to Figures 1 to 9 and Figures 10A to 10B A more detailed description of the various specific implementations of high-density memory architectures.

[0017] Figure 1 Figure 100 shows a memory circuit 102 associated with a bit cell according to various specific embodiments described herein.

[0018] In various specific implementations, memory circuitry 102 can be implemented as a system or device having various integrated circuit (IC) components arranged and coupled together as an assembly or combination of parts providing physical circuit design and associated structures. In some cases, a method of designing, providing, and constructing memory circuitry 102 as an integrated system or device may involve using the various IC circuit components described herein to implement various memory array architectures associated therewith. Memory circuitry 102 can be integrated with computing circuitry and associated components on a single chip, and memory circuitry 102 can be implemented in embedded systems for electronic, mobile, and Internet of Things (IoT) applications, including sensor nodes.

[0019] like Figure 1As shown, memory circuitry 102 can be associated with a memory architecture implemented as a bit cell or memory cell. In some cases, bit cell 104 can refer to a device or structure having a single bit cell configured to store data bits accessible via multiple word lines and multiple bit lines. Bit cell 104 may utilize multiple word lines coupled to the bit cell, including write word lines (WWL), read word lines (RWL), and global read word lines (GRWL). Bit cell 104 may utilize multiple horizontal bit lines coupled to the bit cell (WBL, NWBL, RBL_H0, RBL_H1, RBL_H2, RBL_H3). Bit cell 104 may utilize multiple vertical bit lines coupled to the bit cell (RBL_V0, RBL_V1, RBL_V2, RBL_V3, RBL_V4, RBL_V5, RBL_V6, RBL_V7, RBL_V8). This article describes in more detail the various aspects and structural features associated with the layout design of the memory array architecture associated with the bit cell 104 of the memory circuit 102, as well as the various schemes and techniques associated therewith.

[0020] Figure 2 Figure 200 illustrates bit cell structure 204 according to various specific embodiments described herein. In some specific embodiments, Figure 2 The bit unit structure 204 and Figure 1 The bit unit 104 is associated with it.

[0021] In various specific implementations, bit cell structure 204 can be implemented as a memory device having various IC components arranged and coupled together as an assembly or combination of parts that allow for physical layout design and related structures. In some cases, a method of designing, providing, and manufacturing bit cell structure 204 as an integrated device may involve using the various IC circuit components described herein to implement various memory array architectures associated therewith. Bit cell structure 204 can be integrated with computing circuitry and related components on a single chip, and additionally, bit cell structure 204 can be used in embedded systems for electronic, mobile, and Internet of Things (IoT) applications.

[0022] like Figure 2As shown, bit cell structure 204 can refer to a device having a single bit cell with multiple transistors arranged and configured to store data bits accessible via multiple word lines and multiple bit lines. In some specific implementations, bit cell structure 204 may include eight transistors arranged and configured to provide a single 8-transistor (8T) bit cell. For example, bit cell structure 204 may include transistors (T1, T2) arranged as a first inverter, transistors (T3, T4) arranged as a second inverter, write access transistors (T5, T6), and read transistors (T7, T8). Additionally, bit cell structure 204 may include multiple word lines, including write word lines (WWL), read word lines (RWL), and global read word lines (GRWL). The write word lines (WWL) may be coupled to the gates of transistors (T5, T6), and the read word lines (RWL) may be coupled to the gates of transistor (T7). Additionally, the first write bit line (WBL) can be coupled to transistor (T6), and the second write bit line (NWBL) can be coupled to transistor (T5).

[0023] In some specific implementations, the bit cell structure 204 may have multiple horizontal bit lines (WBL, NWBL, RBL_H0, RBL_H1, RBL_H2, RBL_H3) coupled to the bit cell. The multiple horizontal bit lines may include a first read bit line (RBL_H0, RBL_H1, RBL_H2, RBL_H3) positioned horizontally relative to the bit cell, and may also include a first write bit line (WBL) and a second write bit line (NWBL) as a complement to the first write bit line (WBL). Therefore, the horizontal bit lines may include six horizontal bit lines positioned horizontally relative to the bit cell, comprising four (4) horizontal read bit lines (RBL_H0, RBL_H1, RBL_H2, RBL_H3) and two horizontal write bit lines (WBL, NWBL).

[0024] In some specific implementations, the bit cell structure 204 may have a plurality of vertical bit lines (RBL_V0, RBL_V1, RBL_V2, RBL_V3, RBL_V4, RBL_V5, RBL_V6, RBL_V7, RBL_V8) coupled to the bit cell. The plurality of vertical bit lines may refer to a plurality of second read bit lines (RBL) arranged vertically relative to the bit cell, and additionally, the second read bit lines may include eight (8) vertical read bit lines arranged vertically relative to the bit cell.

[0025] Figure 3 Figure 300 shows a memory array circuit 302 having bit cells 204 arranged in a 1×8 array, according to a specific embodiment described herein.

[0026] like Figure 3 As shown, the memory array circuit 302 may include a 1×8 array of bit cells 204, which are arranged in a single row of eight bit cells 204. The 1×8 array of bit cells 204 may be arranged in a single row of bit cells 204 and may include a first bit cell BC[0], a second bit cell BC[1], a third bit cell BC[2], a fourth bit cell BC[3], a fifth bit cell BC[4], a sixth bit cell BC[5], a seventh bit cell BC[6], and an eighth bit cell BC[7], which are coupled to corresponding write word lines (WWL) and read word lines (RWL). In some cases, the first write word line WWL[0] and the first read word line RWL[0] may be coupled to the first bit cell BC[0], the second write word line WWL[1] and the second read word line RWL[1] may be coupled to the second bit cell BC[1], and so on, until the eighth write word line WWL[7] and the eighth read word line RWL[8] are coupled to the eighth bit cell BC[7]. Additionally, in some cases, each bit cell 204 may have eight transistors, which are arranged and configured to provide an 8-transistor (8T) bit cell in a row of 8 bit cells 204.

[0027] In some implementations, the horizontal bit lines (RBL_H0, RBL_H1, RBL_H2, RBL_H3) may be coupled to bit cells 204 in a 1×8 array, and the horizontal bit lines (RBL_H0, RBL_H1, RBL_H2, RBL_H3) may include a first read bit line arranged horizontally relative to the bit cell array. The first read bit lines (RBL_H0, RBL_H1, RBL_H2, RBL_H3) include four (4) horizontal read bit lines arranged horizontally relative to the bit cells 204. In some cases, the first read bit line (RBL_H0) may be coupled to the fourth bit cell BC[3] and the eighth bit cell BC[7], and the second read bit line (RBL_H1) may be coupled to the third bit cell BC[2] and the seventh bit cell BC[6]. In addition, the third read bit line (RBL_H2) can be coupled to the second bit unit BC[1] and the sixth bit unit BC[5], and the fourth read bit line (RBL_H3) can be coupled to the first bit unit BC[0] and the fifth bit unit BC[4].

[0028] In some specific implementations, the horizontal bit line may also include a first write bit line (WBL) and a second write bit line (NWBL) as a supplement to the first write bit line (WBL). For example... Figure 3As shown, the write bit lines (WBL, NWBL) are coupled to each bit cell in bit cell 204 of the 1×8 bit cell array. Therefore, as shown, the 1×8 array of bit cells 204 may include eight (8) bit cells arranged in a single row of eight (8) columns, and at least four (4) bit cells 204 in the 1×8 array may be read in a single cycle, such as a read cycle (“read”) during a read operation. Additionally, in some cases, the 1×8 bit cell array may be configured to allow at least four (4) word lines to be activated and read in a single cycle, such as a read cycle (“read”) during a read operation.

[0029] In addition, in some specific implementations, refer to Figure 2 The publicly disclosed multiple vertical bit lines (RBL_V0, RBL_V1, RBL_V2, RBL_V3, RBL_V4, RBL_V5, RBL_V6, RBL_V7, RBL_V8) can be coupled to Figure 3 The bit cell 204 in the 1×8 array, and the vertical bit line may refer to a second read bit line arranged in the vertical direction relative to the bit cell 294 in the 1×8 array. In addition, in some cases, the second read bit line may include eight (8) vertical read bit lines (RBL_V0, RBL_V1, RBL_V2, RBL_V3, RBL_V4, RBL_V5, RBL_V6, RBL_V7, RBL_V8) arranged in the vertical direction relative to the bit cell 204 in the 1×8 array.

[0030] Furthermore, in some specific implementations, such as Figure 3 The 1×8 array of bit cells 204 shown can be modified to include additional rows of bit cells 204 in a larger array. For example, the 1×8 array can be modified to provide an 8×8 array of bit cells 204, for example, by expanding the 1×8 bit cell array to include eight copies of the 1×8 bit cell array to include eight rows of bit cells 204. In this case, Figure 3 The memory circuit 302 shown can be adapted to provide an 8×8 array of bit cells 204, which may include sixty-four (64) bit cells arranged in eight (8) rows and eight (8) columns, and additionally, thirty-two (32) bit cells of the bit cells 204 in the 8×8 array can be read in a single cycle, such as a read cycle (“read”) during a read operation. Additionally, in some cases, the 8×8 bit cell array can be configured to allow at least four (4) word lines to be activated and read in a single cycle, such as a read cycle (“read”) during a read operation.

[0031] Figure 4Figure 400 shows a memory array circuit 402 having bit cells 204 arranged in a 16×8 array, according to a specific embodiment described herein.

[0032] like Figure 4 As shown, the memory array circuit 402 may include multiple 8×8 arrays of bit cells 204, which are arranged as multiple blocks or groups of 8×8 bit cell arrays 412A, 412B. The memory array circuit 402 may also include multiple logic arrays 418A, 418B coupled to the multiple 8×8 bit cell arrays 412A, 412B, wherein the multiple logic arrays 418A, 418B are configured to access data stored in the bit cells 204 of the multiple 8×8 bit cell arrays 412A, 412B. For example, the first logic array 418A can be coupled to the first 8×8 bit cell array 412A via multiple logic gates (LG0A, LG1A, …, LG7A), and the data stored in the bit cell 204 of the first 8×8 bit cell array 412A can be accessed using multiple read word lines (RWL[0], RWL[1], …, RWL[7]) and multiple global read word lines (GWRL[0], GRWL[1], …, GWRL[7]).

[0033] In some cases, referring to the first logic array 418A, the first write word line signal (WLA_EN[0]) and the global read enable signal can be provided to the first logic gate (LG0A, LG1A, LG2A, LG3A) via the global read word lines (GWRL[0], GRWL[1], GRWL[2], GWRL[3]) to select one or more corresponding read word lines (RWL[0], RWL[1], RWL[2], RWL[3]) in the first 8×8 bit cell array 412A. Additionally, the second write word line signal (WLB_EN[0]) along with the global read enable signal can be provided to the second logic gate (LG4A, LG5A, LG6A, LG7A) via the global read word lines (GWRL[4], GRWL[5], GRWL[6], GWRL[7]) to select one or more corresponding read word lines (RWL[4], RWL[5], RWL[6], RWL[7]) in the first 8×8 bit array 412A. Furthermore, in some cases, the first logic array 418A can be coupled to sixty-four (64) bits in the first block of the 8×8 bit array 412A to access data stored in the first block.

[0034] In some cases, referring to the second logic array 418B, the first write word line signal (WLA_EN[1]) and the global read enable signal can be provided to the second logic gate (LG0B, LG1B, LG2B, LG3B) via the global read word lines (GWRL[0], GRWL[1], GRWL[2], GWRL[3]) to select one or more corresponding read word lines (RWL[0], RWL[1], RWL[2], RWL[3]) in the second 8×8 bit cell array 412B. Additionally, the second write word line signal (WLB_EN[1]) along with the global read enable signal can be provided to the second logic gates (LG4B, LG5B, LG6B, LG7B) via global read word lines (GWRL[4], GRWL[5], GRWL[6], GWRL[7]) to select one or more corresponding read word lines (RWL[4], RWL[5], RWL[6], RWL[7]) in the second 8×8 bit array 412B. Furthermore, the second logic array 418B can be coupled to sixty-four (64) bit cells in the second block of the 8×8 bit array 412B to access data stored in the second block.

[0035] Furthermore, in some specific implementations, such as Figure 3 The illustrated 1×8 bit cell array can be expanded or modified to include multiple 8×8 arrays 412A, 412B. For example, the 1×8 array can be modified so that each 8×8 bit cell array 412A, 412B includes eight copies of the 1×8 bit cell array, thereby providing multiple 8×8 arrays of bit cell 204. In this case, Figure 4 The illustrated memory circuit 402 can be adapted to provide a 16×8 memory array of bit cells 204, which may include two copies of an 8×8 memory array having one hundred and twenty-eight (128) bit cells arranged in two (2) blocks of eight (8) rows and eight (8) columns. Additionally, sixty-four (64) bit cells in a first block of the 8×8 array 412A can be read in a first single cycle, such as, for example, during a first read cycle (“read”) of a read operation. Additionally, sixty-four (64) bit cells in a second block of the 8×8 array 412A can be read in a second single cycle, such as, for example, during a second read cycle (“read”) of a read operation. Thus, a double-pulse read operation can be used to read 128 bits in two cycles, with 64 bit cells read in the first read cycle and 64 additional bit cells read in the second read cycle. In addition, multiple blocks of the 8×8-bit cell arrays 412A and 412B can be configured to allow at least four (4) word lines to be activated and read in each read cycle of a double-pulse read cycle (“read”) during a read operation.

[0036] Figure 5 Figure 500 shows a memory array circuit 502 having bit cells 204 arranged in a 32×16 array, according to a specific embodiment described herein.

[0037] like Figure 5 As shown, the memory array circuit 502 may include a 32×16 array having multiple 16×8 arrays (514A, 514B, 514C, 514D) blocks, each block including multiple 8×8 arrays (512A, 512B, …, 512H). For example, the 32×16 array 502 may include a first 16×8 array 514A having multiple 8×8 arrays 512A, 512B, and additionally, the 32×16 array 502 may include a second 16×8 array 514B having multiple 8×8 arrays 512C, 512D. Furthermore, the 32×16 array 502 may include a third 16×8 array 514C having multiple 8×8 arrays 512E, 512F, and additionally, the 32×16 array 502 may include a fourth 16×8 array 514D having multiple 8×8 arrays 512G, 512H. Additionally, in some cases, each 8×8 array (512A, 512B, …, 512H) may have, as shown in the diagram... Figure 4 The corresponding logic arrays (518A, 518B, …, 518H) function and operate in the manner described.

[0038] In some cases, the memory array circuitry 502 may include control circuitry for each bit cell array block or group, such as, for example, an upper or top group (514A, 514C) and a lower or bottom group (514B, 514D). For example, a first sense amplifier and driver logic (SA+driver) 530A and a first multiplexer and input-output logic (Mux+IO) 540A may be provided as shared control circuitry for the upper group having a first 16×8 array 514A and a third 16×8 array 514C. Additionally, a second sense amplifier and driver logic (SA+driver) 530B and a second multiplexer and input-output logic (Mux+IO) 540B may be provided as shared control circuitry for the lower group having a second 16×8 array 514B and a fourth 16×8 array 514D. In some cases, the memory array circuitry 502 may include other shared control circuitry, such as, for example, a first word line driver circuit (WDX) 520A for the first 16×8 array 514A and the second 16×8 array 514B, and a second word line driver circuit (WDX) 520B for the third 16×8 array 514C and the fourth 16×8 array 514D. Additionally, in some cases, the memory array circuitry 502 may include a clock circuit (CLK) 524 and an input-output clock circuit (IO CLK) 528 shared among the four 16×8 arrays (514A, 514B, 514C, 514D).

[0039] Furthermore, in some specific implementations, such as Figure 3 The illustrated 1×8 bit cell array can be expanded or modified to include a 32×16 memory array 502 having multiple 16×8 arrays 514A, 514B, 514C, 514D. For example, the 1×8 array can be modified so that each 16×8 bit cell array 514A, 514B, 514C, 514D includes eight copies of the 8×8 bit cell array, thereby providing a 32×16 memory array 502 for bit cells 204. In this case, Figure 5The 32×16 memory circuit 502 shown can be adapted to provide a 32×16 memory array of bit cells 204, which may include four copies of a 16×8 memory array having 512 (512) bit cells arranged in four (4) blocks of sixteen (16) rows and eight (8) columns. Additionally, 256 (256) bit cells in the first and second blocks of the 16×8 arrays 512A and 512B can be read in a first single cycle, such as, for example, during a first read cycle (“read”) of a read operation. Additionally, 256 (256) bit cells in the third and fourth blocks of the 16×8 arrays 512C and 512D can be read in a second single cycle, such as, for example, during a second read cycle (“read”) of a read operation. Thus, a double-pulse read operation can be used to read 512 bits in blocks over two cycles, with 256 bit cells read in the first read cycle and an additional 256 bit cells read in the second read cycle. In addition, multiple 16×8-bit cell arrays 514A, 514B, 514C, 514D blocks can be configured to allow at least eight (8) word lines to be activated and read in each read cycle of a double-pulse read cycle (“read”) during a read operation.

[0040] Figure 6 Figure 600 illustrates a memory array circuit 602 having bit cells arranged in multiple interleaved blocks of 32×16 bit cells, according to various specific embodiments described herein. In some embodiments, the multiple blocks of 32×16 bit cells can be interleaved to allocate pins during write operations, wherein block reads can be performed on the same 4 bytes from all 16 entries.

[0041] like Figure 6 As shown, the memory array circuit 602 includes a plurality of 32×16 array blocks, wherein each 32×16 array block has a plurality of 16×8 array blocks, and each 16×8 array block has a plurality of 8×8 arrays. For example, the plurality of 32×16 array blocks may include a first 32×16 block [0] array having eight (8) 8×8 arrays, and additionally, the plurality of 32×16 array blocks may include a second 32×16 block [1] array having eight (8) 8×8 arrays. Furthermore, the plurality of 32×16 array blocks may include a third 32×16 block [2] array having eight (8) 8×8 arrays, and additionally, the plurality of 32×16 array blocks may include a fourth 32×16 block [3] array having eight (8) 8×8 arrays. In addition, in some cases, each 32×16 array (block [0], block [1], block [2], block [3]) may be as follows Figure 5 The method described works and operates.

[0042] Furthermore, in some specific implementations, such as Figure 3The 1×8 bit cell array shown can be expanded or modified to include four (4) 32×16 memory block arrays (block [0], block [1], block [2], block [3]), where each memory block array has eight (8) 8×8 arrays. For example, the 1×8 array can be modified so that each 32×16 bit cell block array (block [0], block [1], block [2], block [3]) includes eight copies of the 8×8 bit cell array, thus providing four blocks of the 32×16 memory array 602 for bit cell 204. In this case, as Figure 5 The 32×16 memory circuit 502 shown can be adapted to provide four 32×16 memory bit cell array blocks, each block comprising four copies of the 32×16 memory array having 512 (512) bit cells arranged and interleaved in four (4) blocks of thirty-two (32) rows and sixteen (16) columns. Additionally, 512 (512) bit cells in the first and second blocks (block [0], block [1]) of the 32×16 array can be read in a first single cycle, such as, for example, during a first read cycle (“read”) of a read operation. Additionally, 512 (512) bit cells in the third and fourth blocks (block [2], block [3]) of the 32×16 array can be read in a second single cycle, such as, for example, during a second read cycle (“read”) of a read operation. Therefore, a 1024-bit block can be read in two cycles using a double-pulse read operation, wherein 512 bit cells are read in the first read cycle and an additional 512 bit cells are read in the second read cycle. Furthermore, multiple 32×16-bit cell block arrays (block [0], block [1], block [2], block [3]) can be adapted and configured to allow at least eight (8) word lines (e.g., eight vertical word lines) to be activated and read in each read cycle of the double-pulse read cycle (“read”) during the read operation.

[0043] Figure 7 Figure 700 illustrates a memory array circuit 702 having bit cells arranged in multiple 128×16 array groups according to various specific embodiments described herein. In some embodiments, the multiple 128×16 bit cell array blocks may include four (4) 128×16 memory array groups (group_0, group_1, group_2, group_3), wherein an entry read can be performed with reference to 16 entries, each entry having 64 bytes, where 64 bytes refers to 512 bits. Alternatively, a block read can be performed with reference to 16 32×16 array blocks, wherein during a block read operation, 512 bit cells can be read in two cycles using a single 32×16 block read.

[0044] like Figure 7As shown, the memory array circuit 702 includes multiple 128×16 array groups (group_0, group_1, group_2, group_3), wherein each group has multiple 32×16 array blocks (block[0], block[1], block[2], …], block

[15] ), which are based on multiple 8×8 arrays. For example, the multiple 128×16 array groups include a first 128×16 group[0] array having four (4) 32×16 array blocks (block[0], block[1], block[2], block[3]), and additionally, the multiple 128×16 array groups may include a second 128×16 group[1] array having four (4) 32×16 array blocks (block[4], block[5], block[6], block[7]). Furthermore, multiple 128×16 array groups may include a third 128×16 group [2] array having four (4) 32×16 array blocks (block [8], block [9], block

[10] , block

[11] ), and additionally, multiple 128×16 array groups may include a fourth 128×16 group [3] array having four (4) 32×16 array blocks (block

[12] , block

[13] , block

[14] , block

[15] ). Additionally, in some cases, each 128×16 group array (group [0], group [1], group [2], group [3]) may be as described in reference. Figure 6 The method described works and operates.

[0045] Furthermore, in some specific implementations, such as Figure 3 The 1×8 bit cell array shown can be expanded or modified to include four (4) 128×16 memory group arrays (group [0], group [1], group [2], group [3]), where each memory group array has four (4) 32×16 arrays. For example, the 1×8 array can be modified so that each 128×16 bit cell group array (group [0], group [1], group [2], group [3]) includes 32 copies of the 8×8 bit cell array, thus providing four groups of the 128×16 memory array 702 for bit cell 204. In this case, as Figure 6 The illustrated 128×16 memory circuit 602 can be adapted to provide four groups of 128×16 memory bit cell arrays, each group comprising four copies of the 128×16 memory array, wherein each copy has 512 (512) bit cells arranged in four (4) blocks of 32 (32) rows and 16 (16) columns. Additionally, 512 (512) bit cells in the first and second blocks of the 32×16 array in each group can be read in a first single cycle, such as, for example, during a first read cycle (“read”) of a read operation. Additionally, 512 (512) bit cells in the third and fourth blocks of the 32×16 array in each group can be read in a second single cycle, such as, for example, during a second read cycle (“read”) of a read operation.

[0046] Therefore, a 2048-bit block can be read in two cycles using a double-pulse read operation, wherein 1024 bit cells are read in the first read cycle and an additional 1024 bit cells are read in the second read cycle. Furthermore, multiple 128×16 bit cell group arrays (group [0], group [1], group [2], group [3]) can be adapted and configured to allow at least eight (8) word lines (e.g., eight vertical word lines) to be activated and read in each read cycle of the double-pulse read cycle (“read”) during the read operation.

[0047] Figure 8 Figure 800 illustrates a memory array circuit 802 having bit cells arranged in a plurality of interleaved blocks in a 64×16 bit cell array according to various specific embodiments described herein. In some specific embodiments, the plurality of blocks in the 64×16 bit cell array may be interleaved with eight (8) 16×8 replica blocks, and a block read may be performed on 512 bit cells in a single cycle. When writing, column addresses (CA) may be interleaved based on the corresponding row address (RA) of the plurality of blocks in each block or group. Furthermore, each block in the plurality of blocks in each group may be interleaved during a write operation, for example by interleaving column addresses (CA) based on the row address (RA) of the plurality of blocks in each block or group.

[0048] like Figure 8 As shown, the memory array circuit 802 includes a 64×16 bit cell array with multiple interleaved 16×8 blocks, each block having multiple 4×8 arrays. For example, the multiple 16×8 array blocks may include a first 4×8 block array (block [0]) with sixteen (16) 8×8 arrays, and the multiple 16×8 array blocks may include a second 4×8 block array (block [1]) with sixteen (16) 8×8 arrays. Furthermore, each 4×8 array (block [0], block [1]) may be interleaved during a write operation. In addition, in some specific implementations, 512 (512) bit cells may be read in a single cycle, such as, for example, in a first read cycle (“read”) during a read operation. Additionally, the multiple 4×8 bit cell array blocks (block [0], block [1]) may be adapted and configured to allow at least eight (8) word lines (e.g., eight vertical word lines) to be activated and read in each read cycle of a single-pulse read cycle (“read”) during a read operation.

[0049] Figure 9 Figure 900 illustrates a memory array circuit 902 having bit cells arranged in multiple interleaved 32×16-bit cell array blocks according to various specific embodiments described herein. In some specific embodiments, multiple 16×8-bit cell array blocks can be interleaved to allocate pins during write operations, wherein block reads can be performed on the same 4 bytes from all 16 entries.

[0050] like Figure 9 As shown, the memory array circuit 602 includes a plurality of 32×16 array blocks, wherein each 32×16 array block has a plurality of interleaved 16×8 array blocks, and each 16×8 array block has two 8×8 arrays. For example, the plurality of 32×16 array blocks may include a first 32×16 block [0] array having eight (8) interleaved 8×8 arrays, and additionally, the plurality of 32×16 array blocks may include a second 32×16 block [1] array having eight (8) interleaved 8×8 arrays. Furthermore, the plurality of 32×16 array blocks may include a third 32×16 block [2] array having eight (8) interleaved 8×8 arrays, and additionally, the plurality of 32×16 array blocks may include a fourth 32×16 block [3] array having eight (8) interleaved 8×8 arrays. In addition, in some cases, each interleaved 32×16 array (block [0], block [1], block [2], block [3]) may be as follows Figures 5 to 6 The method described works and operates.

[0051] Furthermore, in some specific implementations, 512 (512) bit cells in the first and second blocks (block [0], block [1]) of the 32×16 array can be read in a first single read cycle (“read”) during a read operation. Additionally, 512 (512) bit cells in the third and fourth blocks (block [2], block [3]) of the 32×16 array can be read in a second single read cycle (“read”) during a read operation. Thus, a block read of 1024 bits can be performed in two cycles using a double-pulse read operation, with 512 bit cells read in the first read cycle and 512 additional bit cells read in the second read cycle. Furthermore, multiple 32×16 bit cell block array blocks (block [0], block [1], block [2], block [3]) can be adapted and configured to allow activation and reading of at least eight (8) word lines (e.g., eight vertical word lines) in each read cycle of the double-pulse read cycle.

[0052] Figures 10A to 10BFigures 1000A and 1000B illustrate memory array circuits 1002A and 1002B having bit cells in multiple 128×16 array groups according to specific embodiments described herein. In some embodiments, each of the multiple 128×16 array groups is arranged as multiple interleaved 32×16 bit cell array blocks, and multiple 16×8 bit cell array blocks can be interleaved to allocate pins during write operations, wherein block reads can be performed on the same 4 bytes from all 16 entries. Additionally, in some embodiments, memory array circuits 1002A and 1002B may include four (4) 128×16 memory array groups, wherein 16 entries can be read during an entry read operation, wherein each entry has 64 bytes (512 bits). Furthermore, referring to a block read operation, 16 32×16 bit cell blocks can be read in two cycles, wherein a single 32×16 (512 bit) block can be read in two cycles.

[0053] like Figures 10A to 10B As shown, the multiple memory array circuits 1000A and 1000B include multiple 128×16 array groups (group [0], group [1], group [2], group [3]), wherein each group has multiple interleaved 32×16 array blocks (block [0], block [1], block [2], …, block

[15] ), which are based on multiple interleaved 16×8 arrays. For example, the multiple 128×16 array groups include a first 128×16 group [0] array having four (4) interleaved 32×16 array blocks (block [0], block [1], block [2], block [3]), and additionally, the multiple 128×16 array groups may include a second 128×16 group [1] array having four (4) interleaved 32×16 array blocks (block [4], block [5], block [6], block [7]). Furthermore, multiple 128×16 array groups may include a third 128×16 group [2] array having four (4) interleaved 32×16 array blocks (block [8], block [9], block

[10] , block

[11] ), and additionally, multiple 128×16 array groups may include a fourth 128×16 group [3] array having four (4) interleaved 32×16 array blocks (block

[12] , block

[13] , block

[14] , block

[15] ). Furthermore, in various cases, each 128×16 group array (group [0], group [1], group [2], group [3]) may be as referenced. Figures 6 to 9 The manner described works and operates and / or behaves.

[0054] Furthermore, in some specific implementations, such as Figure 3The 1×8 bit cell array shown can be extended or modified to include four (4) 128×16 memory group arrays (group [0], group [1], group [2], group [3]), wherein each memory group array has four (4) interleaved 32×16 bit cell arrays. For example, the 1×8 array can be modified so that each 128×16 bit cell group array (group [0], group [1], group [2], group [3]) includes 32 copies of the interleaved 8×8 bit cell array, thereby providing four groups of the 128×16 memory array 702 of bit cell 204. In this case, as Figures 10A to 10B The 128×16 memory circuits 1002A and 1002B shown can be adapted to provide four groups of 128×16 memory bit cell arrays, each group comprising four copies of a 128×16 memory array, each copy having 512 (512) bit cells arranged in four (4) interleaved blocks of thirty-two (32) rows and sixteen (16) columns. Additionally, during a read operation, 512 (512) bit cells in the first and second blocks of the 32×16 array in each group can be read in a first single read cycle. Furthermore, during a read operation, 512 (512) bit cells in the third and fourth blocks of the 32×16 array in each group can be read in a second single read cycle.

[0055] Therefore, a 1024-bit block can be read in two cycles using a double-pulse read operation, wherein 512 bit cells are read in the first read cycle and an additional 512 bit cells are read in the second read cycle. Furthermore, multiple 128×16 bit cell group arrays (group [0], group [1], group [2], group [3]) can be adapted and configured to allow at least eight (8) word lines (e.g., eight vertical word lines) to be activated and read in each read cycle of the double-pulse read cycle (“read”) during the read operation.

[0056] It should be anticipated that the subject matter of the claims is not limited to the specific embodiments and illustrations provided herein, but includes modifications of those embodiments according to the claims, including portions of the embodiments and combinations of elements from different embodiments. It should be understood that in the development of any such embodiment, as in any engineering or design project, many embodiment-specific decisions will be made to achieve the developer's specific objectives, such as compliance with system-related and business-related constraints, which may vary between different embodiments. Furthermore, it should be understood that such development work can be complex and time-consuming; however, it remains a routine task of design, manufacture, and production for those skilled in the art who benefit from this disclosure.

[0057] This document describes various specific embodiments of a device. The device may include bit cells. The device may include horizontal bit lines coupled to the bit cells, and the horizontal bit lines may include a plurality of first read bit lines disposed horizontally relative to the bit cells. The device may include vertical bit lines coupled to the bit cells, and the vertical bit lines may include a plurality of second read bit lines disposed vertically relative to the bit cells.

[0058] This document describes various specific embodiments of a device. The device may include a bit cell array. The device may include horizontal bit lines coupled to the bit cells in the array, and the horizontal bit lines may include first read bit lines disposed horizontally relative to the bit cell array. The device may include vertical bit lines coupled to the bit cells in the array, and the vertical bit lines may include second read bit lines disposed vertically relative to the bit cell array.

[0059] This document describes various specific embodiments of a device. The device may include a bit cell array arranged in multiple groups, each group having multiple blocks. The device may include horizontal bit lines coupled to the bit cells in the array, and the horizontal bit lines may include first read bit lines disposed horizontally relative to the bit cell array. The device may include vertical bit lines coupled to the bit cells in the array, and the vertical bit lines may include second read bit lines disposed vertically relative to the bit cell array.

[0060] Various specific implementations have been referenced in detail, examples of which are shown in the accompanying drawings and illustrations. Numerous specific details are set forth in the following detailed description to provide a thorough understanding of the disclosure provided herein. However, the disclosure provided herein can be practiced without these specific details. In some other instances, well-known methods, procedures, components, circuits, and networks have not been described in detail so as not to unnecessarily obscure the details of the implementation.

[0061] It should also be understood that while the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. Both the first and second elements are elements, but they are not considered the same element.

[0062] The terminology used in the description of this disclosure provided herein is for the purpose of describing particular specific embodiments and is not intended to limit the scope of the disclosure provided herein. As used in the disclosure provided herein and in the description of the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. As used herein, the term “and / or” means and covers any and all possible combinations of one or more of the associated listed items. When used in this specification, the terms “comprising,” “including,” and / or “containing” specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0063] As used herein, depending on the context, the term "if" can be interpreted as meaning "when," "at," "in response to determination," or "in response to detection." Similarly, depending on the context, the phrase "if it is determined..." or "if [the condition or event] is detected" can be interpreted as meaning "in response to determination..." or "in response to detection of [the condition or event]." The terms "up" and "down"; "upper part" and "lower part"; "upward" and "downward"; "below" and "above"; and other similar terms indicating the relative position above or below a given point or element may be used in conjunction with some specific implementations of the various techniques described herein.

[0064] While the foregoing relates to specific implementations of the various technologies described herein, other and additional specific implementations can be conceived based on the disclosure herein, which can be defined by the appended claims.

[0065] Although the subject matter has been described in language specific to structural features and / or methodological actions, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are disclosed as exemplary forms for implementing the claims.

Claims

1. An integrated circuit device, the device comprising: an array of bitcells; horizontal bitlines coupled to the array of bitcells, the horizontal bitlines comprising a plurality of first read bitlines, a first write bitline, and a second write bitline, wherein the horizontal bitlines are disposed in a horizontal direction relative to the array of bitcells, wherein the first read bitlines are different from the first write bitline and the second write bitline; vertical bitlines coupled to the array of bitcells, the vertical bitlines comprising a plurality of second read bitlines disposed in a vertical direction relative to the array of bitcells; and a plurality of wordlines coupled to the array of bitcells, wherein the plurality of wordlines comprises a write wordline and a read wordline corresponding to each bitcell in the array of bitcells.

2. The device of claim 1, wherein each bitcell in the array of bitcells is a single bitcell with 8 transistors arranged and configured to provide an 8-transistor bitcell.

3. The device of claim 1, wherein the second write bitline is in addition to the first write bitline.

4. The device of claim 1, wherein the first read bitlines comprise 4 horizontal read bitlines disposed in the horizontal direction relative to the array of bitcells.

5. The device of claim 1, wherein the second read bitlines comprise 8 vertical read bitlines disposed in the vertical direction relative to the array of bitcells.

6. The device of claim 1, wherein the plurality of wordlines further comprises a global read wordline.

7. The device of claim 1, wherein: the array of bitcells comprises 8 bitcells arranged in a single row of eight columns, and 4 bitcells in the array of bitcells are read in a single cycle.

8. The device of claim 1, wherein: the array of bitcells comprises 64 bitcells arranged in 8 rows of 8 columns, and 32 bitcells in the array of bitcells are read in a single cycle.

9. The device of claim 1, wherein: the array of bitcells comprises 128 bitcells arranged in two blocks of 8 rows of 8 columns, 64 bitcells in a first block of the two blocks are read in a first cycle, and 64 bitcells in a second block of the two blocks are read in a second cycle.

10. The device of claim 9, wherein: the device comprises a first logic array coupled to the 64 bitcells in the first block for accessing data stored in the first block, and the device comprises a second logic array coupled to the 64 bitcells in the second block for accessing data stored in the second block.

11. The device of claim 1, wherein: the array of bitcells comprises 512 bitcells arranged in four blocks of 16 rows of 8 columns, 256 bitcells in a first block and a second block of the four blocks are read in a first cycle, and 256 bitcells in a third block and a fourth block of the four blocks are read in a second cycle. In a second cycle, 256 of the bit cells in a third and fourth of the four blocks are read.

12. The device of claim 1, wherein: the array of bit cells includes 2048 bit cells arranged into four 32 row by 16 column blocks, In a first cycle, 512 of the bit cells in a first and second of the four blocks are read, and In a second cycle, 512 of the bit cells in a third and fourth of the four blocks are read.

13. A method of manufacturing an integrated circuit device, the method comprising: providing an array of bit cells; coupling horizontal bit lines to bit cells in the array of bit cells, the horizontal bit lines including a first read bit line, a first write bit line, and a second write bit line, wherein the horizontal bit lines are disposed in a horizontal direction relative to the array of bit cells, wherein the first read bit line is different from the first write bit line and the second write bit line; coupling vertical bit lines to bit cells in the array of bit cells, the vertical bit lines including a second read bit line disposed in a vertical direction relative to the array of bit cells; and coupling a plurality of word lines to the array of bit cells, wherein the plurality of word lines includes a write word line and a read word line corresponding to each bit cell in the array of bit cells.

14. The method of claim 13, wherein the horizontal bit lines are coupled to each bit cell in the array of bit cells, and wherein each bit cell has 8 transistors arranged and configured to provide an 8 transistor bit cell.

15. The method of claim 13, wherein: the first read bit line includes 4 horizontal read bit lines disposed in the horizontal direction relative to the array of bit cells, and the second read bit line includes 8 vertical read bit lines disposed in the vertical direction relative to the array of bit cells.

16. The method of claim 13, wherein: the second write bit line is in addition to the first write bit line, and the plurality of word lines further includes a global read word line.

17. An integrated circuit device, the device comprising: an array of bit cells arranged into a plurality of groups, wherein each group of the plurality of groups has a plurality of blocks; horizontal bit lines coupled to the bit cells in the array, the horizontal bit lines including a first read bit line, a first write bit line, and a second write bit line, wherein the horizontal bit lines are disposed in a horizontal direction relative to the array of bit cells, wherein the first read bit line is different from the first write bit line and the second write bit line; vertical bit lines coupled to the bit cells in the array, the vertical bit lines including a second read bit line disposed in a vertical direction relative to the array of bit cells; and a plurality of word lines coupled to the array of bit cells, wherein the plurality of word lines includes a write word line and a read word line corresponding to each bit cell in the array of bit cells. ​ 18. The apparatus of claim 17, wherein the horizontal bit line is coupled to each of the bit cells in the array, and wherein each bit cell has 8 transistors arranged and configured to provide an 8 transistor bit cell.

19. The apparatus of claim 17, wherein the plurality of groups comprises four groups, and wherein the plurality of blocks comprises four blocks within each group, and wherein: each of the four blocks comprises 512 bit cells arranged into 32 rows of 16 columns, 512 of the bit cells in each of the four blocks are read in a first cycle in a first block and a second block of the four blocks in each group, and 512 of the bit cells in each of the four blocks are read in a second cycle in a third block and a fourth block of the four blocks in each group.

20. The apparatus of claim 17, wherein each of the plurality of blocks of each group is interleaved during a write operation by interleaving column addresses based on row addresses for each block or the plurality of blocks of each group. ​ ​ ​

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