Semiconductor device

Abstract

Provided is a semiconductor device including: a semiconductor substrate; a transistor portion provided over the semiconductor substrate and having an emitter region of a first conductivity type on a top surface side of the semiconductor substrate and a collector region of a second conductivity type on a bottom surface side of the semiconductor substrate; a diode portion provided over the semiconductor substrate and having a cathode region of the first conductivity type on the bottom surface side of the semiconductor substrate; an emitter electrode provided over the top surface of the semiconductor substrate; and a protective film provided at least partially over the emitter electrode, the cathode region not overlapping with the protective film in a plane parallel to the top surface of the semiconductor substrate.

Description

[0001] This application is a divisional application of the application filed on December 15, 2017, with international application number PCT / JP2017 / 045173, Chinese application number 201780033306.9, and entitled "Semiconductor Device and Manufacturing Method". Technical Field

[0002] This invention relates to semiconductor devices and manufacturing methods. Background Technology

[0003] In semiconductor devices in which the transistor portion and diode portion of an insulated gate bipolar transistor (IGBT) are formed on the same substrate, it is known that a technique is used to control the carrier lifetime by irradiating helium ions to a predetermined depth position on the semiconductor substrate (for example, see Patent Document 1).

[0004] Patent Document 1: Japanese Patent Application Publication No. 2015-185742 Summary of the Invention

[0005] Technical issues

[0006] In semiconductor devices, it is desirable to minimize losses during reverse recovery. Additionally, it is desirable to suppress fluctuations in the threshold voltage of the transistor.

[0007] Technical solution

[0008] In a first aspect of the present invention, a semiconductor device comprising a semiconductor substrate, a transistor portion, a diode portion, and a boundary portion is provided. The transistor portion may be disposed on the semiconductor substrate and have an emitter region of a first conductivity type on the upper surface side of the semiconductor substrate and a collector region of a second conductivity type on the lower surface side of the semiconductor substrate. The transistor portion may have one or more gate trench portions extending from the upper surface of the semiconductor substrate to a depth greater than the emitter region, and on which a gate potential is applied. The diode portion may be disposed on the semiconductor substrate and have a cathode region of a first conductivity type on the lower surface side of the semiconductor substrate. The boundary portion may be disposed on the semiconductor substrate between the transistor portion and the diode portion, having no emitter region on the upper surface side of the semiconductor substrate and a collector region on the back side side of the semiconductor substrate. An upper surface-side lifetime control body may be provided on the upper surface side of the semiconductor substrate in a portion of the diode portion and the boundary portion, while no upper surface-side lifetime control body may be provided in the region overlapping the gate trench portion of the transistor portion on a surface parallel to the upper surface of the semiconductor substrate.

[0009] The upper surface-side lifetime control unit may not be disposed in the region overlapping with the transistor portion on a surface parallel to the upper surface of the semiconductor substrate. The transistor portion and the diode portion may be alternately arranged on the upper surface of the semiconductor substrate along a predetermined arrangement direction. The end of the upper surface-side lifetime control unit in the arrangement direction may be positioned closer to the diode portion than the gate trench portion in the transistor portion that is closest to the diode portion, and positioned closer to the transistor portion than the cathode region.

[0010] Both the diode portion and the boundary portion may have one or more dummy trench portions, which are provided from the upper surface of the semiconductor substrate to the interior of the semiconductor substrate and are applied with a potential different from the gate potential.

[0011] The semiconductor substrate may have multiple mesa sections sandwiched between two trench sections, and the boundary section may have an upper surface-side lifetime control body on at least one mesa section and no upper surface-side lifetime control body on at least one mesa section.

[0012] The upper surface-side lifetime control unit can be disposed on a surface parallel to the upper surface of the semiconductor substrate in a manner that covers a wider area than the cathode region of the diode section.

[0013] The diode portion may have a base region of a second conductivity type disposed in a region sandwiched between dummy trench portions, exposed on the upper surface of the semiconductor substrate. The upper surface-side lifetime control unit may be disposed on a surface parallel to the upper surface of the semiconductor substrate, covering an area wider than the base region of the diode portion.

[0014] The semiconductor device may also include a second conductivity type well region disposed inside the semiconductor substrate, located further outward from the base region along the long side of the dummy trench. The region where the upper surface-side lifetime control body is disposed may have a portion overlapping the well region on a surface parallel to the upper surface of the semiconductor substrate.

[0015] The semiconductor device may also include a gate channel portion formed of a semiconductor material with added impurities, located on the upper surface of the semiconductor substrate, further outward from the base region in the long side direction of the dummy trench portion. The area where the upper surface-side lifetime control body is located may not overlap with the gate channel portion on a plane parallel to the upper surface of the semiconductor substrate.

[0016] The upper surface-side lifetime control unit can also be disposed on a surface parallel to the upper surface of the semiconductor substrate in the region between the gate channel portion and the outer peripheral end of the semiconductor substrate.

[0017] The semiconductor device may have an emitter electrode disposed above the upper surface of a semiconductor substrate. The semiconductor device may also have a protective film disposed at least partially above the emitter electrode. The cathode region may not overlap with the protective film on a surface parallel to the upper surface of the semiconductor substrate.

[0018] The upper surface-side lifetime control body can overlap the entire cathode region on a surface parallel to the upper surface of the semiconductor substrate, without overlapping the protective film.

[0019] In a second aspect of the present invention, a semiconductor device comprising a semiconductor substrate is provided. The semiconductor device includes a semiconductor device, a diode portion, and a transistor portion. The transistor portion may have an emitter region of a first conductivity type disposed on the semiconductor substrate and having such a region on the upper surface of the semiconductor substrate. The transistor portion may have a collector region of a second conductivity type on the lower surface of the semiconductor substrate. The diode portion may be disposed on the semiconductor substrate and have a cathode region of a first conductivity type on the lower surface of the semiconductor substrate. The semiconductor device may include an emitter electrode disposed above the upper surface of the semiconductor substrate. The semiconductor device may include a protective film at least partially disposed above the emitter electrode. The cathode region may not overlap with the protective film on a surface parallel to the upper surface of the semiconductor substrate.

[0020] In the diode section, an upper surface-side lifetime control element can be provided on the upper surface side of the semiconductor substrate. The upper surface-side lifetime control element overlaps with the entire cathode region on a plane parallel to the upper surface of the semiconductor substrate, but does not overlap with the protective film.

[0021] On a surface parallel to the upper surface of the semiconductor substrate, the distance between the protective film and the lifetime control body on the upper surface side can be 10 μm or more.

[0022] The semiconductor device may have a gate channel portion disposed between element regions, including at least one of a transistor portion and a diode portion, on a surface parallel to the upper surface of the semiconductor substrate. A protective film may also be disposed above the gate channel portion. The upper surface-side lifetime control unit may be on a surface parallel to the upper surface of the semiconductor substrate and may not overlap with the protective film above the gate channel portion.

[0023] In a third aspect of the present invention, a manufacturing method is provided, which is a manufacturing method for manufacturing the semiconductor device of the first aspect, wherein a lifetime control body is introduced from the upper surface side of a semiconductor substrate to form an upper surface-side lifetime reduction region.

[0024] After the emitter electrode is formed above the upper surface of the semiconductor substrate, a lifetime control body can be introduced from the upper surface side of the semiconductor substrate. After the lifetime control body is introduced, a plating layer can be formed on the upper surface of the emitter electrode.

[0025] The above description of the invention does not list all the features of the invention. Sub-combinations of these feature groups can also constitute an invention. Attached Figure Description

[0026] Figure 1 This is a diagram showing the structure of the upper surface of a semiconductor device 100 according to one embodiment of the present invention.

[0027] Figure 2 It means Figure 1 A top view of an example of region 130 of the semiconductor device 100 shown.

[0028] Figure 3 It means Figure 2 A diagram of an example of a-a' cross-section of the semiconductor device 100 shown.

[0029] Figure 4 It means Figure 2 A diagram showing an example of a b-b' cross-section of the semiconductor device 100.

[0030] Figure 5 This is a diagram showing the position of the cathode region 82 on a surface parallel to the upper surface of the semiconductor substrate 10.

[0031] Figure 6 This is another example of a diagram showing the range of the upper surface side life reduction zone 92.

[0032] Figure 7 This is another example of a diagram showing the range of the upper surface side life reduction zone 92.

[0033] Figure 8 It means Figure 6 A diagram of an example of section a-a' in the figure.

[0034] Figure 9 This is a diagram showing an example of the configuration of the upper surface-side lifetime reduction region 92 on the upper surface of the semiconductor substrate 10.

[0035] Figure 10 This is a diagram showing another example of a structure on the upper surface of the semiconductor substrate 10.

[0036] Figure 11 This is a diagram showing another configuration example of the upper surface side life reduction zone 92.

[0037] Figure 12 It means Figure 11 A diagram of an example of section a-a' in the figure.

[0038] Figure 13 This is a diagram showing another configuration example of the upper surface side life reduction zone 92.

[0039] Figure 14 It means Figure 13 A diagram of an example of section a-a' in the figure.

[0040] Figure 15 It means Figure 1 A diagram of another example of section a-a' in the figure.

[0041] Figure 16 This is a diagram showing the structure of the upper surface of the semiconductor device 300 according to an embodiment of the present invention.

[0042] Figure 17A It means Figure 16 A diagram of an example of the c-c' section.

[0043] Figure 17B This is a cross-sectional view of the semiconductor device 500 in an intermediate step of the manufacturing process of the comparative example.

[0044] Figure 17C This is a cross-sectional view of the semiconductor device 300 in an intermediate step of the manufacturing process in this example.

[0045] Figure 18 This is a diagram showing another structure of the upper surface of the semiconductor device 300.

[0046] Figure 19 It means manufacturing Figure 1-Figure 2 A diagram showing a portion of the manufacturing process of the semiconductor device 100 or semiconductor device 300 described in section 7.

[0047] Figure 20 This is another example of a method for manufacturing a semiconductor device.

[0048] Symbol Explanation

[0049] 10 Semiconductor substrate, 12 Emitter region, 14 Base region, 15 Contact region, 16 Accumulation region, 17 Well region, 18 Drift region, 20 Buffer zone, 21 Upper surface, 22 Collector region, 23 Lower surface, 24 Collector electrode, 26 Interlayer insulating film, 30 Dummy trench, 32 Dummy insulating film, 34 Dummy conductive portion, 40 Gate trench, 42 Gate insulating film, 44 Gate conductive portion, 50 Gate metal layer, 51 Gate channel, 52 Emitter electrode, 54 Contact hole, 55 Contact hole, 56 Contact hole, 57 Connector, 59 Insulating film, 60 End, 62 Contact region, 70 Transistor portion, 80 Diode portion, 82 Cathode region, 90 Boundary portion, 92 Upper surface-side lifetime reduction region, 93 Lower surface-side lifetime reduction region, 94 Mesa portion, 95 Top surface lifetime reduction region, 100 semiconductor device, 116 gate pad, 120 active area, 130 region, 140 outer perimeter, 150 edge termination structure, 200 mask, 300 semiconductor device, 400 protective film, 401 opening, 500 semiconductor device Detailed Implementation

[0050] The present invention will now be described through embodiments thereof, but these embodiments do not limit the invention as defined in the claims. Furthermore, not all combinations of the features described in the embodiments are necessarily necessary for the technical solution of the invention.

[0051] In this specification, one side parallel to the depth direction of the semiconductor substrate is referred to as "upper," and the other side as "lower." One of the two main surfaces of the substrate, layer, or other component is referred to as the upper surface, and the other as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity.

[0052] In various embodiments, examples are shown where the first conductivity type is set to n-type (sometimes described as N-type) and the second conductivity type is set to p-type (sometimes described as P-type), but it is also possible to set the first conductivity type to p-type and the second conductivity type to n-type. In this case, the conductivity types of the substrate, layer, region, etc., in each embodiment become opposite polarities.

[0053] In this specification, orthogonal coordinate axes of X, Y, and Z are sometimes used to describe technical content. In this specification, the plane parallel to the upper surface of the semiconductor substrate is designated as the XY plane, and the depth direction perpendicular to the upper surface of the semiconductor substrate is designated as the Z axis.

[0054] In this specification, doping concentration refers to the concentration of donor- or acceptor-modified impurities. Sometimes, the concentration difference between donors and acceptors is used as the doping concentration. Furthermore, when the doping concentration distribution in the doped region has a peak, the peak value can be used as the doping concentration in that doped region. When the doping concentration in the doped region is almost uniform, the average doping concentration in that doped region can be used as the doping concentration.

[0055] Figure 1 This diagram illustrates the structure of the upper surface of a semiconductor device 100 according to one embodiment of the present invention. The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, or a nitride semiconductor substrate such as gallium nitride. In this example, the semiconductor substrate 10 is a silicon substrate. In this specification, the outer periphery of the semiconductor substrate 10 as viewed from its upper surface is designated as the outer periphery end 140. Viewing from the upper surface refers to viewing the semiconductor substrate 10 from its upper surface side parallel to the Z-axis.

[0056] The semiconductor device 100 includes an active portion 120, a gate current channel portion 51, and an edge termination structure portion 150. The active portion 120 is a region in which a main current flows between the upper and lower surfaces of the semiconductor substrate 10 when the semiconductor device 100 is controlled to be in a conducting state. In other words, it is a region in which current flows along the depth direction inside the semiconductor substrate 10, either from the upper surface to the lower surface or from the lower surface to the upper surface.

[0057] At least a portion of the gate channel portion 51 is disposed between the active portion 120 and the outer peripheral end 140 on a surface parallel to the upper surface of the semiconductor substrate 10. The gate channel portion 51 is formed of a conductive material such as polysilicon or metal, and supplies a gate voltage to the device disposed in the active portion 120. The gate channel portion 51 is formed above or inside the semiconductor substrate 10, and the semiconductor substrate 10 and the gate channel portion 51 are insulated from each other by an insulating film. The gate channel portion 51 may be disposed surrounding the active portion 120 on a surface parallel to the upper surface of the semiconductor substrate 10. A portion of the gate channel portion 51 may also be formed in the active portion 120. A portion of the gate channel portion 51 may be disposed transversely through the active portion 120 along the X-axis direction.

[0058] The gate flow channel 51 is electrically connected to the gate pad 116 disposed outside the active section 120. The gate pad 116 may be disposed between the active section 120 and the outer peripheral end 140. Pads such as emitter pads electrically connected to the emitter electrode may be disposed between the active section 120 and the outer peripheral end 140.

[0059] A transistor section 70 and a diode section 80 are provided in the active portion 120. A boundary section 90 may also be provided between the transistor section 70 and the diode section 80. In this specification, the transistor section 70, the diode section 80, and the boundary section 90 are sometimes referred to as a component section or a component region, respectively. The region where the component section is provided can be regarded as the active portion 120. It should be noted that when the semiconductor substrate 10 is viewed from the top surface, the region sandwiched between the two component sections is also the active portion 120.

[0060] exist Figure 1 In the example, the region where the gate flow channel 51 is located, sandwiched between the component sections, is also included in the active section 120. The active section 120 can also be the region where an emitter electrode is located when the semiconductor substrate 10 is viewed from the top surface, and the region sandwiched between the regions where the emitter electrode is located. Figure 1 In this example, an emission electrode is provided above the transistor section 70, the diode section 80, and the boundary section 90.

[0061] The transistor section 70 includes transistors such as IGBTs. Diode sections 80 are arranged alternately with the transistor sections 70 on the upper surface of the semiconductor substrate 10 in a predetermined first direction. The first direction is... Figure 1 The X-axis direction. In this specification, the first direction is sometimes referred to as the arrangement direction.

[0062] In each diode section 80, an N+ type cathode region 82 is provided in the area in contact with the lower surface of the semiconductor substrate 10. The diode section 80 is the area on the lower surface of the semiconductor substrate 10 in which the cathode region 82 is provided. In the semiconductor device 100 of this example, the area in contact with the lower surface of the semiconductor substrate, excluding the cathode region 82, is a P+ type collector region.

[0063] The diode section 80 is the region formed by projecting the cathode region 82 along the Z-axis direction. However, as... Figure 1 As shown by the dashed line, the region formed by projecting the cathode region 82 along the Z-axis direction extends along the Y-axis direction to the end of the active section 120 (for example, the position where it is connected to the gate channel section 51), which is also the diode section 80.

[0064] The transistor section 70 is a region on the lower surface of the semiconductor substrate 10 in which a collector region is formed, and on the upper surface of the semiconductor substrate 10, a unit structure containing an N+ type emitter region is periodically formed. The boundary section 90 is the region on the lower surface of the semiconductor substrate 10 in which the collector region is formed, excluding the transistor section 70.

[0065] Transistor sections 70 may be provided at both ends of the active section 120 in the X-axis direction. The active section 120 may be divided by the gate channel section 51 in the Y-axis direction. In each divided region of the active section 120, transistor sections 70 and diode sections 80 are alternately arranged in the X-axis direction.

[0066] An edge termination structure 150 is disposed on the upper surface of the semiconductor substrate 10 between the active portion 120 and the outer peripheral end 140 of the semiconductor substrate 10. In this example, the edge termination structure 150 is disposed between the gate channel portion 51 and the outer peripheral end 140. The edge termination structure 150 can be arranged in a ring shape on the upper surface of the semiconductor substrate 10 to surround the active portion 120. In this example, the edge termination structure 150 is disposed along the outer peripheral end 140 of the semiconductor substrate 10. The edge termination structure 150 mitigates the electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure 150 has, for example, a protective ring, a field plate, a surface resurf mechanism, and a combination of these.

[0067] Figure 2 It means Figure 1 This is a top view of an example of region 130 of the semiconductor device 100 shown. The semiconductor device 100 in this example is a semiconductor chip having a transistor section 70, which includes transistors such as IGBTs, disposed on a semiconductor substrate, and a diode section 80, which includes diodes such as FWDs (Free Wheel Diodes).

[0068] A boundary portion 90 is provided between the transistor portion 70 and the diode portion 80 on the upper surface of the semiconductor substrate. The upper surface of the semiconductor substrate refers to one of the two opposing main surfaces on the semiconductor substrate. Figure 2 The image shows the upper surface of the chip around the edge of the chip, omitting other areas.

[0069] in addition, Figure 2 The active region of the semiconductor substrate of the semiconductor device 100 is shown, but as Figure 1 As shown, the semiconductor device 100 may have an edge terminal structure 150 in a manner that surrounds the active region.

[0070] The semiconductor device 100 of this example includes a gate trench 40, a dummy trench 30, a well region 17, an emitter region 12, a base region 14, and a contact region 15 formed inside the upper surface side of a semiconductor substrate. Furthermore, the semiconductor device 100 of this example includes an emitter electrode 52 and a gate metal layer 50 disposed above the upper surface of the semiconductor substrate. The emitter electrode 52 and the gate metal layer 50 are disposed separately from each other.

[0071] An interlayer insulating film is formed between the emitter electrode 52 and the gate metal layer 50 and the upper surface of the semiconductor substrate, but Figure 2 (The text is omitted.) In this example, the interlayer insulating film has contact holes 54, 55, and 56 formed through it.

[0072] The emitter electrode 52 is electrically connected to the emitter region 12, contact region 15, and base region 14 on the upper surface of the semiconductor substrate through the contact hole 54. Additionally, the emitter electrode 52 is connected to a dummy conductive portion within the dummy trench portion 30 through the contact hole 56. A connection portion 57, formed of a conductive material such as polysilicon doped with impurities, may be provided between the emitter electrode 52 and the dummy conductive portion. The connection portion 57 is formed on the upper surface of the semiconductor substrate.

[0073] The gate metal layer 50 contacts the gate flow channel portion 51 through the contact hole 55. The gate flow channel portion 51 is formed of a semiconductor such as polysilicon doped with impurities. The gate flow channel portion 51 is connected to the gate conductive portion within the gate trench portion 40 on the upper surface of the semiconductor substrate. In other words, the gate flow channel portion 51 is formed on the upper surface of the semiconductor substrate in such a way that it extends across a portion of the gate trench portion 40 and the contact hole 55.

[0074] The emitter electrode 52 and the gate metal layer 50 are formed of a metal-containing material. For example, at least a portion of each electrode is formed of aluminum or an aluminum-silicon alloy. Each electrode may have a barrier metal formed of titanium, titanium compounds, or the like in the layer beneath the region formed of aluminum, or it may have a plug formed of tungsten or the like in the contact hole.

[0075] In the transistor section 70, one or more gate trench sections 40 are arranged at predetermined intervals along the short side direction of each trench. The gate conductive portion inside the gate trench section 40 is electrically connected to the gate metal layer 50 and is given a gate potential. In the transistor section 70, one or more dummy trench sections 30 may be arranged at predetermined intervals along the short side direction. The dummy conductive portion inside the dummy trench section 30 is given a potential different from the gate potential. In this example, the dummy conductive portion is electrically connected to the emitter electrode 52 and is given an emitter potential.

[0076] In the transistor section 70, one or more gate trench sections 40 and one or more dummy trench sections 30 may be formed alternately along the short side direction. In addition, the dummy trench sections 30 are arranged at predetermined intervals along the short side direction in the diode section 80 and the boundary section 90.

[0077] The gate trench portion 40 and the dummy trench portion 30 are formed extending along a predetermined long side direction on the upper surface of the semiconductor substrate. In this example, a portion of the dummy trench portion 30 in the transistor portion 70 has a straight shape and is formed extending along a long side direction perpendicular to the aforementioned short side direction. The dummy trench portion 30 may also have a U-shape formed by connecting the front ends of two straight portions. Figure 2 In the example, the dummy trench portion 30 of the transistor portion 70 has a straight shape, while the dummy trench portions 30 in the diode portion 80 and the boundary portion 90 have a U-shape. However, the shape of the dummy trench portion 30 is not limited to... Figure 2 Examples include: at least a portion of the dummy trench portion 30 in the transistor portion 70 may have a U-shape, or at least a portion of the dummy trench portion 30 in the diode portion 80 and the boundary portion 90 may have a straight line shape.

[0078] exist Figure 2 The X-axis direction is defined as the short side direction of the trench portion. The Y-axis direction is defined as the long side direction of the trench portion. The X and Y axes are axes orthogonal to each other on a plane parallel to the upper surface of the semiconductor substrate. The Z-axis is defined as an axis orthogonal to both the X and Y axes. In this specification, the Z-axis direction is sometimes referred to as the depth direction.

[0079] Figure 2 In the example, the gate trench 40 has a straight portion and a connecting portion connecting two straight portions. The straight portions are formed extending along the aforementioned long side direction. The straight portions of each trench are formed in parallel. The connecting portion may have a curved shape on the upper surface of the semiconductor substrate.

[0080] At the connection portion at the front end of the gate trench portion 40, the gate conductive portion and the gate flow channel portion 51 within the gate trench portion 40 are connected. The gate trench portion 40 may be provided in a manner that protrudes further towards the gate flow channel portion 51 than the dummy trench portion 30 in the long side direction (Y-axis direction). This protruding portion of the gate trench portion 40 is connected to the gate flow channel portion 51.

[0081] Emitter electrode 52 is formed above gate trench 40, dummy trench 30, well region 17, emitter region 12, base region 14, and contact region 15. Well region 17 is formed within a predetermined range from the end of the active region on the side where gate metal layer 50 is disposed. In this example, the end of well region 17 in the Y-axis direction is connected to the end of base region 14. The diffusion depth of well region 17 can be deeper than the depth of gate trench 40 and dummy trench 30. A portion of the gate trench 40 and dummy trench 30 on the gate metal layer 50 side is formed in well region 17. The bottom of one end of the long side of dummy trench 30 can be covered by well region 17.

[0082] The semiconductor substrate has a first conductivity type, and the well region 17 has a second conductivity type different from that of the semiconductor substrate. In this example, the semiconductor substrate is N-type, and the well region 17 is P+ type. A base region 14 is formed on the mesa portion, which is the area sandwiched between the trench portions. The base region 14 has a second conductivity type with a lower doping concentration than the well region 17. In this example, the base region 14 is P-type. It should be noted that for the + and - signs on the conductivity type, + indicates a relatively high doping concentration, and - indicates a relatively low doping concentration.

[0083] On the upper surface of the base region 14 in each mesa, a contact region 15 of a second conductivity type with a higher doping concentration than the base region 14 can be selectively formed. In this example, the contact region 15 is P+ type. Additionally, in the transistor section 70, an emitter region 12 of a first conductivity type with a higher doping concentration than the semiconductor substrate is selectively formed on the upper surface of the base region 14. In this example, the emitter region 12 is N+ type. In this example, the emitter region 12 is not formed on the mesa sections of the diode section 80 and the boundary section 90.

[0084] Both the contact region 15 and the emitter region 12 are formed from one adjacent trench portion to another. One or more contact regions 15 and one or more emitter regions 12 of the transistor portion 70 are formed in such a way that they are alternately exposed on the upper surface of the mesa portion along the long side direction of the trench portion.

[0085] In the mesa-shaped portion of the diode portion 80 and the boundary portion 90, a contact region 15 is formed in a region opposite to at least one contact region 15 in the transistor portion 70. Figure 2 In the example, in the mesa of the diode section 80 and the boundary section 90, a contact region 15 is formed in the region opposite to the contact region 15 closest to the gate metal layer 50 in the transistor section 70, and a base region 14 is formed in other regions.

[0086] In the transistor section 70, contact holes 54 are formed above each region of the contact region 15 and the emitter region 12. Contact holes 54 are not formed in the regions corresponding to the base region 14 and the well region 17. Within the contact hole 54, on the surface of the contact region 15 that contacts the emitter electrode 52, a second contact region 62 (see reference) may exist that has a higher concentration and is shallower than that of the contact region 15. Figure 8 The second contact area 62 is of type P+.

[0087] In the diode section 80 and the boundary section 90, contact holes 54 are formed above the contact region 15 and the base region 14. In this example, the contact holes 54 of the transistor section 70, the diode section 80, and the boundary section 90 have the same length in the long side direction of each trench section. In the contact hole 54, on the surface layer of the contact region 15 or the base region 14 that contacts the emitter electrode 52, a second contact region 62 may exist with a higher concentration and a shallower location than that of the contact region 15.

[0088] In this example, transistor section 70 refers to a region where a first conductivity type emitter region is provided on the mesa portion of the upper surface of the semiconductor substrate, and a second conductivity type collector region is provided on the lower surface of the semiconductor substrate. Similarly, boundary section 90 refers to a region where a first conductivity type emitter region is not provided on the mesa portion of the upper surface of the semiconductor substrate, but a collector region is provided on the lower surface of the semiconductor substrate. Diode section 80 refers to a region where a first conductivity type emitter region is not provided on the mesa portion of the upper surface of the semiconductor substrate, but a first conductivity type cathode region is provided on the lower surface of the semiconductor substrate. It should be noted that... Figure 2 The cathode region 82, which is disposed on the lower surface side of the semiconductor substrate, is shown in the case where it is projected onto the upper surface side.

[0089] In a portion of the diode section 80 and the boundary section 90, an upper surface-side lifetime reduction region 92 is provided on the upper surface side of the semiconductor substrate. The region in the boundary section 90 where the upper surface-side lifetime reduction region 92 is provided is adjacent to the diode section 80. On the other hand, the upper surface-side lifetime reduction region 92 is not provided in the transistor section 70. The upper surface-side lifetime reduction region 92 is selectively formed at a predetermined depth position between the center of the semiconductor substrate in the depth direction and the upper surface of the semiconductor substrate. The upper surface-side lifetime reduction region 92 is a region where a lifetime control body is intentionally introduced by injecting impurities or the like into the interior of the semiconductor substrate 10. The lifetime value of the electron or hole carriers in the region where a lifetime control body is intentionally introduced is smaller than the lifetime of the carriers in the region where a lifetime control body is not intentionally introduced. The lifetime control body is a carrier recombination center, which can be a crystal defect, a vacancy, a double vacancy, a dangling bond formed by a vacancy, etc., which recombine with elements constituting the semiconductor substrate 10, dislocations, rare gas elements such as helium and neon, metal elements such as platinum, etc. As an example, the upper surface-side lifetime reduction region 92 is formed by irradiating this depth location with ions such as helium.

[0090] By providing an upper surface-side lifetime reduction region 92 in the diode section 80, the carrier lifetime in the diode section 80 can be adjusted, thereby reducing losses during reverse recovery. Furthermore, since a boundary section 90 is provided, and the upper surface-side lifetime reduction region 92 is also provided in the boundary section 90, the lifetime of holes flowing from the transistor section 70 to the diode section 80 can be controlled even if the upper surface-side lifetime reduction region 92 is not provided in the transistor section 70. Since the upper surface-side lifetime reduction region 92 is not provided in the transistor section 70, even if ions such as helium are irradiated from the upper surface of the semiconductor substrate, damage to the gate insulating film or the like in the transistor section 70 will not occur. Therefore, fluctuations in the threshold voltage or the like in the transistor section 70 can be suppressed. Additionally, since ions such as helium can be irradiated from the upper surface of the semiconductor substrate, the ion irradiation position can be made shallower, and the depth of the upper surface-side lifetime reduction region 92 can be precisely controlled.

[0091] Furthermore, compared to irradiating helium ions from the back side of a semiconductor substrate, the acceleration energy of the irradiated helium ions can be reduced, thus reducing the cost of masks and the like. The acceleration energy of the irradiated helium ions can be a value at which the irradiated ions do not pass through the semiconductor substrate.

[0092] Conventionally, an energy absorber is placed between the accelerator that accelerates ions and the semiconductor substrate, and irradiation is performed at high acceleration energies (above 10 MeV) to the extent that the irradiated ions can penetrate the semiconductor substrate. In this case, the location (depth) where the ions stop within the semiconductor substrate is adjusted by absorbing the energy of the ions through the thickness of the energy absorber. For ion irradiation based on such high acceleration energies, in addition to causing excessive damage to the semiconductor substrate, the full width at half maximum (FWHM) of the ions becomes on the order of 10 μm, and the distribution width of lattice defects relative to the thickness of the semiconductor substrate also becomes wider. In contrast, if ions such as helium are irradiated with acceleration energies that stop inside the semiconductor substrate without using an energy absorber, excessive damage is avoided, and the desired low-lifetime region can be formed in a narrower area.

[0093] The acceleration energy of helium ions irradiating a semiconductor substrate without using an energy absorber can be described as follows. In the case of silicon semiconductor substrate, for the range Rp (the position of the helium concentration peak) of helium ions in semiconductor substrate and the acceleration energy E of helium ions, if the logarithm of the range Rp of helium ions log(Rp) is set as x and the logarithm of the acceleration energy E of helium ions log(E) is set as y, the following relationship (1) can be satisfied.

[0094] y = -0.0169x 4 +0.1664x 3 -0.6161x 2 +1.6157x+5.2681 (1)

[0095] It should be noted that when using the above-described fitting formula to calculate the acceleration energy E (referred to as the calculated value E) of helium ion irradiation based on the desired average range Rp of helium ions, and when helium ions are implanted into a silicon substrate with this calculated acceleration energy E, the relationship between the actual acceleration energy E' and the actual average range Rp' (helium ion peak position) obtained by methods such as secondary ion mass analysis (SIMS) can be considered as follows. If the actual acceleration energy E' is within approximately ±10% of the calculated acceleration energy E, then the actual average range Rp' is also within approximately ±10% of the desired average range Rp, which is within the range of measurement error. Therefore, the deviation of the actual average range Rp' from the desired average range Rp has a very small impact on the electrical characteristics of IGBTs, diodes, etc., and is negligible.

[0096] Therefore, if the actual acceleration energy E' is within ±5% of the calculated value E, it can be determined that the actual average range Rp' is essentially the same as the set average range Rp. Alternatively, for the average range Rp calculated by substituting the value of E' relative to the actual acceleration energy E' into the above equation (1), if the actual average range Rp' is within ±10% of that average range Rp, there is no problem. In an actual accelerator, since both the acceleration energy E and the average range Rp can be within the above range (±10%), it is assumed that the actual acceleration energy E' and the actual average range Rp' conform to the above fitting formula expressed by the desired average range Rp and the calculated value E, and there is no problem at all.

[0097] Furthermore, the deviation or error range relative to the average range Rp can be less than ±10% as described above. Preferably, if it is within ±5%, it can be considered to fully conform to the above formula (1). By using the above formula (1), the acceleration energy E of the helium ions required to obtain the desired range Rp of the helium ions can be calculated.

[0098] Figure 3 It means Figure 2 A diagram showing an example of an a-a' cross-section of the semiconductor device 100. The a-a' cross-section is parallel to the XZ plane and passes through the emitter region 12 of the transistor section 70. Figure 3 The mask 200 used in the manufacture of the semiconductor device 100 is also shown in the figure.

[0099] In this example, the semiconductor device 100 has a semiconductor substrate 10, an interlayer insulating film 26, an emitter electrode 52, and a collector electrode 24 in this cross-section. The emitter electrode 52 is formed on the upper surface of the semiconductor substrate 10 and the interlayer insulating film 26.

[0100] The collector electrode 24 is formed on the lower surface 23 of the semiconductor substrate 10. The lower surface refers to the surface opposite to the upper surface. The emitter electrode 52 and the collector electrode 24 are formed of a conductive material such as metal. In this specification, the surface or end of the emitter electrode 52 side of each component such as the substrate, layer, and region is referred to as the upper surface or upper end, and the surface or end of the collector electrode 24 side is referred to as the lower surface or lower end. The direction connecting the emitter electrode 52 and the collector electrode 24 is referred to as the Z-axis direction (depth direction).

[0101] The semiconductor substrate 10 can be a silicon substrate, a silicon carbide substrate, or a gallium nitride semiconductor substrate, etc. A P-type base region 14 is formed on the upper surface 21 side of the semiconductor substrate 10.

[0102] In this cross-section, an N+ type emitter region 12 and a P- type base region 14 are sequentially formed from the upper surface 21 side of the semiconductor substrate 10 on the upper surface side of each mesa 94 of the transistor section 70. An N+ type accumulation region 16 may also be further formed below the base region 14.

[0103] In this cross-section, a P-type base region 14 is formed on the upper surface side of each mesa 94 of the diode portion 80 and the boundary portion 90. The emitter region 12 may not be formed on each mesa 94 of the diode portion 80 and the boundary portion 90. Furthermore, the accumulation region 16 may not be formed on each mesa 94 of the diode portion 80 and the boundary portion 90.

[0104] In the transistor section 70, an N-type drift region 18 is formed on the lower surface of the accumulation region 16. By providing an accumulation region 16 with a higher concentration than the drift region 18 between the drift region 18 and the base region 14, the carrier injection enhancement effect (IE effect) can be improved, thereby reducing the turn-on voltage.

[0105] In both the diode section 80 and the boundary section 90, a drift region 18 is formed on the lower surface of the base region 14. In both the transistor section 70 and the diode section 80, an N-type buffer zone 20 is formed on the lower surface of the drift region 18.

[0106] Buffer 20 is formed on the lower surface side of drift region 18. The doping concentration of buffer 20 is higher than that of drift region 18. Buffer 20 can function as a field termination layer to prevent the depletion layer from diffusing from the lower surface side of base region 14 to the P+ type collector region 22 and the N+ type cathode region 82.

[0107] Buffer 20 can have multiple peaks in the doping concentration distribution along the depth direction. Figure 3 In the example, the doping concentration distribution of buffer 20 has four peaks. The peaks of the doping concentration in buffer 20 could be concentration peaks of hydrogen donors formed through proton implantation and thermal treatment.

[0108] In the transistor section 70 and the boundary section 90, a P+ type collector region 22 is formed on the lower surface of the buffer zone 20. In the diode section 80, an N+ type cathode region 82 is formed on the lower surface of the buffer zone 20.

[0109] On the upper surface 21 side of the semiconductor substrate 10, one or more gate trench portions 40 and one or more dummy trench portions 30 are formed. Each trench portion extends from the upper surface 21 of the semiconductor substrate 10 through the base region 14 to reach the drift region 18. In regions where at least one of the emitter region 12, contact region 15 and accumulation region 16 is provided, each trench portion also extends through these regions to reach the drift region 18.

[0110] The gate trench portion 40 has a gate trench formed on the upper surface 21 side of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is formed to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is formed inside the gate trench at a position closer to the inside than the gate insulating film 42. In other words, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon with added impurities.

[0111] The gate conductive portion 44 includes at least a region opposite to the adjacent base region 14 in the Z-axis direction. The gate trench portion 40 is covered by an interlayer insulating film 26 on the upper surface 21 of the semiconductor substrate 10. In this example, in Figure 2 At the front end of the gate trench portion 40 shown, the gate conductive portion 44 is electrically connected to the gate metal layer 50 via the gate flow channel portion 51. If a predetermined voltage is applied to the gate conductive portion 44, a channel is formed on the surface of the interface in the base region 14 that is in contact with the gate trench portion 40.

[0112] The dummy trench portion 30 can have the same structure as the gate trench portion 40 in this cross-section. The dummy trench portion 30 has a dummy trench formed on the upper surface 21 side of the semiconductor substrate 10, a dummy insulating film 32, and a dummy conductive portion 34. The dummy insulating film 32 is formed to cover the inner wall of the dummy trench. The dummy conductive portion 34 is formed inside the dummy trench, and is formed closer to the inner side than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 can be formed of the same material as the gate conductive portion 44. The dummy trench portion 30 can have the same length in the depth direction as the gate trench portion 40.

[0113] The dummy trench 30 is covered by an interlayer insulating film 26 on the upper surface 21 of the semiconductor substrate 10. In this example, as... Figure 2The dummy conductive part 34 shown is electrically connected to the emitting electrode 52 via the contact hole 56 and the connecting part 57.

[0114] The upper surface-side lifetime reduction region 92 is provided in the cross-section of a portion of the diode section 80 adjacent to the boundary section 90. The boundary section 90 may have the upper surface-side lifetime reduction region 92 in at least one mesa 94 adjacent to the diode section 80, but may not have the upper surface-side lifetime reduction region 92 in at least one mesa 94 adjacent to the transistor section 70. The upper surface-side lifetime reduction region 92 may terminate below either a trench section or below either mesa 94.

[0115] By providing the boundary portion 90, the distance between the N+ type cathode region 82 and the transistor portion 70 can be increased. Furthermore, by forming an upper surface-side lifetime reduction region 92 on a portion of the boundary portion 90, the lifetime of holes injected from the transistor portion 70 into the diode portion 80 can be appropriately controlled, thereby reducing losses during reverse recovery.

[0116] Since the upper surface-side lifetime reduction region 92 is formed throughout the entire diode portion 80 and a portion of the boundary portion 90, it is formed over a wider area in the X-axis direction than the cathode region 82. The upper surface-side lifetime reduction region 92 can be formed over more than half of the boundary portion 90 in the X-axis direction.

[0117] Alternatively, the length in the X-axis direction of the region in the boundary portion 90 where the upper surface-side lifetime reduction region 92 is formed can be longer than the length in the X-axis direction of the region in the boundary portion 90 where the upper surface-side lifetime reduction region 92 is not formed. For example, the upper surface-side lifetime reduction region 92 can be formed in the region of the boundary portion 90 other than a mesa 94 adjacent to the transistor portion 70. This allows for easy control of the lifetime of holes injected from the transistor portion 70 into the diode portion 80.

[0118] Furthermore, by not forming the upper surface-side lifetime reduction region 92 on a mesa 94 adjacent to the transistor section 70, it is possible to prevent the gate trench section 40 from being irradiated with helium ions, etc., even if the irradiation position of helium ions, etc., is shifted due to manufacturing deviations, etc. Thus, fluctuations in the threshold voltage, etc., in the transistor section 70 can be suppressed.

[0119] The mask 200 is used in the process of forming the upper surface-side lifetime reduction region 92. In this example, the upper surface-side lifetime reduction region 92 is formed by irradiating helium ions from the upper surface side of the semiconductor substrate 10 using the mask 200. The mask 200 can be formed by coating a resist or the like and patterning it into a predetermined shape. The upper surface-side lifetime reduction region 92 is not formed in the area covered by the mask 200.

[0120] The mask 200, formed by coating with a photoresist or similar material, can be formed to be in contact with a structure formed on the upper surface 21 of the semiconductor substrate 10. In this example, the structure formed on the upper surface 21 of the semiconductor substrate 10 is the emitter electrode 52. A hard mask formed from raw materials such as metal or silicon needs to be formed further outward (in the +Z axis direction) from the emitter electrode 52 to avoid damage or defects to structures such as electrodes, protective films, and interlayer insulating films formed on the upper surface 21 of the semiconductor substrate 10. Therefore, precise alignment with surface structures located inside or outside the upper surface 21 of the semiconductor substrate 10 becomes difficult. As shown in this example, by forming the mask 200 in contact with a structure formed on the upper surface 21 of the semiconductor substrate 10, it is easy to align with extremely fine surface structures.

[0121] The upper surface-side lifetime reduction region 92 can be formed before the emitter electrode 52. In this example, the upper surface-side lifetime reduction region 92 is formed after the formation of each trench, base region 14, accumulation region 16 and emitter region 12.

[0122] In this example, since helium ions are irradiated from the upper surface of the semiconductor substrate 10, the depth of the upper surface-side lifetime reduction region 92 can be controlled with greater precision compared to irradiating helium ions from the back surface. Furthermore, since the transistor portion 70 is covered by the mask 200, damage to the gate trench portion 40 caused by helium ion irradiation can be prevented. Additionally, since helium ions are irradiated to a shallow depth, a hard mask can be eliminated. Therefore, costs can be reduced.

[0123] It should be explained that Figure 3 The diagram shows the concentration distribution of recombination centers, net doping concentration distribution, and carrier lifetime distribution along the Z-axis in the upper surface-side lifetime reduction region 92 of the mm cross-section. In this example, the upper surface-side lifetime reduction region 92 is formed by irradiating helium ions from the upper surface side of the semiconductor substrate 10.

[0124] The concentration of the lifetime control element (recombination center) in the upper surface-side lifetime reduction region 92 reaches a peak concentration Np at a predetermined depth location. This depth location is located in the drift region 18, which is closer to the upper surface 21 side than the center in the depth direction of the semiconductor substrate 10. The region of the upper surface-side lifetime reduction region 92 can be defined as a region of the lifetime control element having a concentration higher than half the peak concentration Np (0.5Np).

[0125] When helium ions or the like are irradiated from the upper surface 21, lifetime control molecules with a concentration lower than the peak concentration Np are distributed in a downward-sloping manner from the peak position to the upper surface 21 of the semiconductor substrate 10. On the other hand, the concentration of lifetime control molecules closer to the lower surface 23 of the semiconductor substrate 10 than the peak position decreases sharply compared to the concentration of lifetime control molecules closer to the upper surface 21 of the semiconductor substrate 10 than the peak position. The concentration distribution in the upper surface-side lifetime reduction region 92 may not reach the lower surface 23.

[0126] Furthermore, if the distribution from the upper surface 21 to the peak concentration Np is a continuous downward stretch, the depth of the peak concentration Np can also be located closer to the lower surface 23 than the middle position in the depth direction of the semiconductor substrate 10. It should be noted that when irradiated with helium ions or the like from the lower surface 23, lifetime control molecules with a concentration lower than the peak concentration Np can be distributed in a downward stretch manner at a position closer to the lower surface 23 than the peak position.

[0127] It should be explained that Figure 3 The concentration distribution of recombination centers shown can be helium concentration as described above, or it can be the density of crystal defects formed by helium irradiation. Crystal defects can be interstitial helium, vacancies, double vacancies, etc., or dangling bonds formed through vacancies. These crystal defects form recombination centers for charge carriers. The energy levels (trap energy levels) of the formed recombination centers promote carrier recombination. The concentration of recombination centers corresponds to the density of trap energy levels.

[0128] In buffer 20, the multiple regions indicated by diagonal lines (four regions in this example) are regions that include the locations of peak concentrations that constitute the doping concentration distribution of buffer 20. As an example, the width of each of the multiple regions indicated by diagonal lines in the depth direction can be equivalent to the full width at half maximum (FWHM) of the peak doping concentration, centered on the peak location.

[0129] Peak position x of the complex center concentration in the upper surface lifetime reduction region 92 l The peak position x closest to the upper surface 21 can be selected from among the multiple peak positions on the upper surface 21 side and the buffer zone 20. m Separation. When buffer zone 20 includes hydrogen donors, there exists a situation where hydrogen terminates vacancies and dangling bonds at the peak position representing the maximum value of hydrogen donor concentration, thus reducing the concentration of recombination centers. Therefore, the peak position of the recombination center concentration in the upper surface lifetime reduction region 92 can be separated from the peak position in buffer zone 20, thereby reducing the effect of hydrogen-induced termination. Furthermore, the peak position of the recombination center concentration in the upper surface lifetime reduction region 92 can be formed among multiple peak positions in buffer zone 20. This also has the effect of reducing the effect of hydrogen-induced termination.

[0130] Figure 3The carrier lifetime distribution shown has a minimum value τ at a position that roughly corresponds to the peak concentration position of the recombination center. min In the base region 14 near the upper surface 21, the carrier lifetime distribution can have a higher than τ. min The large value τ1. In regions without an introduced lifetime control volume in other depth directions, the carrier lifetime distribution can be distributed with almost the same value (denoted as τ0) in regions deeper than the peak concentration location of the recombination center. In buffer 20, due to the vacancies and dangling bond termination effects brought by hydrogen, the carrier lifetime can be distributed with a value around τ0. The position x where the carrier lifetime begins to decrease from τ0. n The peak position x, which can be located on the side closest to the upper surface 21, is one of the multiple peak concentrations in buffer 20. m The position is closer to the upper surface 21. It should be noted that the carrier lifetime near the upper surface 21 and the lower surface 23 can be smaller than τ0 due to the high doping concentration.

[0131] Figure 4 It means Figure 2 A diagram showing an example of a b-b' cross-section of the semiconductor device 100. The b-b' cross-section is parallel to the YZ plane and passes through the contact hole 54 at the boundary 90. It should be noted that in... Figure 4 The diagram shows a cross-section of the boundary portion 90, but the diode portion 80 may also have the same cross-section. The boundary portion 90 has a collector region 22 on the lower surface 23 side of the semiconductor substrate 10, but the diode portion 80 has a cathode region 82 in at least a portion of the area on the lower surface 23 side of the semiconductor substrate 10.

[0132] The boundary portion 90 has a base region 14, a contact region 15, and a well region 17 on the upper surface 21 side of the semiconductor substrate 10. The contact region 15 is selectively formed in the base region 14. The well region 17 is closer to the outer side of the trench portion than the base region 14 in the long side direction, and is formed to a depth deeper than the base region 14.

[0133] In this cross-section, a dummy trench portion 30 is formed in the well region 17. The lower end of the dummy trench portion 30 is shallower than the lower end of the well region 17. The dummy conductive portion of the dummy trench portion 30 is connected to the emitter electrode 52 via a connecting portion 57 and a contact hole 56. An insulating film 59, such as an oxide film, may be formed between the connecting portion 57 and the semiconductor substrate 10.

[0134] The gate flow channel portion 51 is disposed on the long side of the trench portion, closer to the outer side than the base region 14. The gate flow channel portion 51 may be disposed in the region overlapping with the well region 17. At least a portion of the gate flow channel portion 51 is disposed below the gate metal layer 50. The gate flow channel portion 51 is connected to the gate metal layer 50 via a contact hole 55. An insulating film 59, such as an oxide film, may be formed between the gate flow channel portion 51 and the semiconductor substrate 10.

[0135] The upper surface-side lifetime reduction region 92 is formed at a position closer to the lower side than the base region 14. The upper surface-side lifetime reduction region 92 can be formed at a position closer to the lower side than the dummy trench portion 30. The upper surface-side lifetime reduction region 92 can be formed at a position closer to the lower side than the lower end of the well region 17, or it can be formed at a position closer to the upper side than the lower end of the well region 17.

[0136] In this cross-section, the upper surface-side lifetime reduction region 92 extends to a position closer to the outer side than the base region 14 of the diode portion 80 and the boundary portion 90. In other words, the end position Yb of the upper surface-side lifetime reduction region 92 is positioned further outward in the Y-axis direction compared to the end position Yd of the base region 14. In this example, the region where the upper surface-side lifetime reduction region 92 is provided has a portion overlapping the well region 17 on a plane parallel to the upper surface 21 of the semiconductor substrate 10. As a result, the lifetime of holes injected from below the well region 17 to below the base region 14 can be appropriately controlled, and the injection of holes from the well region 17, which has a higher concentration than the base region 14, can be suppressed.

[0137] However, the region where the upper surface-side lifetime reduction region 92 is provided is preferably on a surface parallel to the upper surface 21 of the semiconductor substrate 10 and does not overlap with the gate flow channel portion 51. Therefore, damage to the insulating film 59 by the gate flow channel portion 51 can be prevented when irradiated with helium ions, etc. That is, leakage current generated between the gate metal layer 50 and the emitter electrode 52 can be suppressed, and damage to the gate insulation can be prevented.

[0138] When the end position of the gate channel portion 51 on the base region 14 side is set to Yc, the end position Yb of the upper surface-side lifetime reduction region 92 is preferably disposed between the end position Yd of the base region 14 and the end position Yc of the gate channel portion 51. Furthermore, the position of the dummy trench portion 30 in this cross-section is set to Ye, and the end position of the connection portion 57 on the base region 14 side is set to Ya. The end position Yb can be disposed between position Ye and position Yd, or between position Ya and position Yd. By disposing the end position Yb between position Ya and position Yd, damage to the connection portion 57 can also be suppressed.

[0139] In this example, the end position Yb is positioned between position Yc and position Ye. An edge termination structure is located closer to the outer periphery than the gate channel portion 51. During reverse recovery of the diode portion 80, excess carriers that have leaked into the edge termination structure concentrate at the end 60 of the contact hole 54 in the diode portion 80 or the boundary portion 90. The dummy trench portion 30 acts as a physical barrier against excess carrier leakage to the outer periphery and towards the end of the contact hole during reverse recovery. This suppresses the concentration of excess carriers at the end of the contact hole 54. Furthermore, by positioning the end position Yb of the upper surface-side lifetime reduction region 92 closer to the outer periphery (position Yc side) than the position Ye of the dummy trench portion 30, the leakage of excess carriers to the outer periphery and their concentration at the end of the contact hole 54 are further suppressed.

[0140] Figure 5 It means in Figure 2 This diagram shows the position of the cathode region 82 on a plane parallel to the upper surface 21 of the semiconductor substrate 10 in the semiconductor device 100. The cathode region 82 is disposed within the region of the diode portion 80. In the short-side direction (X-axis direction) of the trench portion, the cathode region 82 is formed over the entire diode portion 80. In the long-side direction (Y-axis direction) of the trench portion, the cathode region 82 is formed in a portion of the mesa portion. For example, the cathode region 82 is formed closer to the inner side than the outermost (gate channel portion 51 side) contact region 15.

[0141] The upper surface-side lifetime reduction region 92 is provided on a surface parallel to the upper surface 21 of the semiconductor substrate 10, in a manner that covers a wider area than the cathode region 82 of the diode portion 80. For example... Figures 3-5 As shown, the lifetime reduction region 92 on the upper surface is set over a wider area than the cathode region 82 in both the X-axis and Y-axis directions. This allows for appropriate control of the lifetime of holes injected from the outside of the cathode region 82.

[0142] The upper surface-side lifetime reduction region 92 is located on a surface parallel to the upper surface 21 of the semiconductor substrate 10, and can be provided in a manner that covers a wider area than the base region 14 of the diode portion 80. For example... Figure 3 as well as Figure 4 As shown, the upper surface side lifetime reduction region 92 is also formed in the boundary portion 90 in the X-axis direction and in the well region 17 in the Y-axis direction.

[0143] Figure 6This diagram illustrates another example of the area where the upper surface-side lifetime reduction region 92 is provided. It should be noted that in this example, the boundary portion 90 has a boundary mesa portion 94-3 and a pull-out portion 94-4. As an example, the boundary mesa portion 94-3 is located in the region adjacent to the diode portion 80, and the pull-out portion 94-4 is located in the region adjacent to the transistor portion 70. In other examples, the boundary mesa portion 94-3 may be located in the region adjacent to the transistor portion 70, and the pull-out portion 94-4 may be located in the region adjacent to the diode portion 80.

[0144] A contact area 15 is provided on the extraction surface 94-4, which has an area larger than that of the contact area 15 on the surface 94-1 of the transistor section 70. The area of ​​the contact area 15 on the extraction surface 94-4 is larger than that of the contact area 15 on the surface 94-2 of the diode section 80. The emitter area 12 may not be provided on the extraction surface 94-4.

[0145] On the boundary mesa 94-3, a base region 14 and a contact region 15 are provided in the same configuration as the mesa 94-2 of the diode section 80. However, a collector region 22 is provided on the lower surface of the boundary mesa 94-3 of the semiconductor substrate 10.

[0146] In this example, the position in the X-axis direction of the end of the gate trench portion 40 closest to the diode portion 80 in the gate trench portion 40 of the transistor portion 70 is designated as Xg. The position in the X-axis direction of the end of the pull-out surface portion 94-4 closest to the transistor portion 70 is designated as Xd. Position Xd can be the boundary position between the pull-out surface portion 94-4 and the dummy trench portion 30. The position in the X-axis direction of the end of the boundary mesa portion 94-3 closest to the transistor portion 70 is designated as Xf. Position Xf can be the boundary position between the boundary mesa portion 94-3 and the dummy trench portion 30. In the X-axis direction, the position of the end of the cathode region 82 is designated as Xc. In the X-axis direction, the position of the end of the upper surface-side lifetime reduction region 92 is designated as Xb.

[0147] The end position Xb of the upper surface-side lifetime reduction region 92 in the X-axis direction is positioned closer to the diode section 80 than the gate trench section 40 (position Xg) positioned closest to the diode section 80 in the transistor section 70, and is positioned closer to the transistor section 70 than the cathode region 82 (position Xc). Figure 6 The upper surface-side lifetime reduction region 92 shown may also be formed in a part of the transistor section 70. However, the upper surface-side lifetime reduction region 92 is not provided in the region that overlaps with the gate trench section 40 of the transistor section 70 on the surface parallel to the upper surface 21 of the semiconductor substrate 10.

[0148] In this example, the end position Xb of the upper surface-side lifetime reduction region 92 is disposed on the mesa 94-1 in the transistor section 70, closest to the diode section 80. However, the end position Xb of the upper surface-side lifetime reduction region 92 is disposed on the diode section 80 side compared to the end position Xg of the gate trench section 40. The distance between the end position Xb and the end position Xg is preferably larger in the X-axis direction than the width of the channel region formed in the base region 14 when a conduction voltage is applied to the gate trench section 40. This reduces the impact of the upper surface-side lifetime reduction region 92 on the threshold voltage of the transistor. As an example, the distance between the end position Xb and the end position Xg can be 0.1 μm or more, or 0.2 μm or more. In addition, the distance between the end position Xb and the end position Xg can be less than half the width of the mesa 94-1 in the X-axis direction. With this configuration, the influence on the channel can be suppressed, and the upper surface-side lifetime reduction region 92 can be disposed over a wide range.

[0149] Figure 7 This is another example of a diagram showing the range of the upper surface side life reduction zone 92. Figure 7 The area near the boundary portion 90 is shown magnified. The end position Xb of the upper surface-side lifetime reduction region 92 in the X-axis direction can be configured between the end position Xd of the extracted mesa portion 94-4 and the end position Xc of the cathode region 82. Therefore, when the transistor is in the conducting state, the concentration of holes flowing through the mesa portion 94 adjacent to the gate trench portion 40 can be prevented from decreasing due to the upper surface-side lifetime reduction region 92, thus preventing an increase in the on-state voltage. Furthermore, by providing the upper surface-side lifetime reduction region 92 on the mesa portion 94-4 when viewed from the upper surface, the injection of high-concentration holes from the mesa portion 94-4 towards the cathode region 82 can be suppressed when the diode portion 80 is in the conducting state.

[0150] The end position Xb of the upper surface-side lifetime reduction region 92 in the X-axis direction can be positioned between the end position Xd and the end position Xf of the boundary mesa 94-3 closest to the transistor section 70. Therefore, when the transistor section 70 is turned on, it is possible to further prevent the hole concentration from decreasing due to the upper surface-side lifetime reduction region 92, and to prevent an increase in the turn-on voltage.

[0151] The end position Xb of the upper surface-side lifetime reduction region 92 in the X-axis direction can also be configured between the end position Xf and the end position Xc of the cathode region 82 (e.g., position Xb1). For mask position offset during selective implantation of lifetime control bodies, it is possible to prevent the lifetime control bodies from reaching the gate trench portion 40.

[0152] Additionally, the end position Xb of the upper surface-side lifetime reduction region 92 in the X-axis direction can also be positioned near the end position Xc of the cathode region 82 (e.g., position Xb2). As an example, the distance between the end position Xb and the end position Xc in the X-axis direction can be smaller than the width of the dummy trench portion 30 in the X-axis direction. This further prevents the lifetime control body from reaching the gate trench portion 40 during selective implantation of the mask position offset.

[0153] The end position Yb of the upper surface side lifetime reduction region 92 in the Y-axis direction can be as follows: Figure 4 and Figure 6 The shown configuration is located between the end position Yc of the gate channel portion 51 and the position Ye of the dummy trench portion 30. In other examples, such as... Figure 7 As shown, the end position Yb of the upper surface-side lifetime reduction region 92 in the Y-axis direction is positioned between the end position Ya of the connecting portion 57 and the end position Yf of the contact region 15 in the Y-axis direction. The end position Yf is the end position on the negative side of the contact region 15 in the Y-axis direction at the end of the diode portion 80. This prevents the lifetime control body from reaching the gate channel portion 51 due to mask position shift during selective implantation of the lifetime control body.

[0154] The end position Yb of the upper surface-side lifetime reduction region 92 in the Y-axis direction can be positioned between the end position Ya of the connector 57 and the end position Yd of the base region 14 (e.g., end position Yb1). When viewed from the upper surface, the upper surface-side lifetime reduction region 92 overlaps with the well region 17, thereby preventing high-concentration holes from being injected from the well region 17 toward the cathode region 82.

[0155] The end position Yb of the upper surface-side lifetime reduction region 92 in the Y-axis direction can also be configured between the end position Yd and the end position Yf of the base region 14 (e.g., end position Yb2). For mask position offset when selectively injecting lifetime control bodies, it is possible to more reliably prevent the lifetime control bodies from reaching the gate flow channel 51.

[0156] Figure 8 It means Figure 6 A diagram of an example of section a-a' in the figure. Figure 8 The mask 200 used in the manufacture of the semiconductor device 100 is also shown. It should be noted that, in this example, the diode portion 80 and the boundary portion 90, which are exposed through contact holes 54 on the upper surface of each stage 94, have contact areas 62. Contact areas 62 are regions with a higher concentration than contact areas 15.

[0157] like Figure 6As shown, the end position Xb of the upper surface-side lifetime reduction region 92 in the X-axis direction is located between the end position Xg of the gate trench portion 40 closest to the diode portion 80 of the transistor portion 70 and the end position Xd of the extraction surface portion 94-4. The end position Xb is separated from the end position Xg by a predetermined distance towards the extraction surface portion 94-4. This distance is larger than the width of the channel region formed in the base region 14 in the X-axis direction.

[0158] The upper surface-side lifetime reduction region 92 is located in the drift region 18 at a depth position closer to the upper surface 21 than the middle position in the depth direction of the semiconductor substrate 10. The upper surface-side lifetime reduction region 92 is a region that includes crystal defects. As described above, crystal defects can be defects that become recombination centers, such as vacancies, double vacancies, dislocations, interstitial atoms, helium atoms, metal atoms, etc.

[0159] The upper surface-side lifetime reduction region 92 can be formed in the X-axis direction on the entire diode portion 80 and the entire boundary portion 90, and further formed on one or more mesa portions 94-1 of the transistor portion 70. Alternatively, the upper surface-side lifetime reduction region 92 can also be configured to cover the entire dummy trench portion 30 in the Y-axis direction, at least including the end of the dummy trench portion 30 extending in the Y-axis direction.

[0160] Figure 9 This diagram illustrates an example of the configuration of the upper surface-side lifetime reduction region 92 on the upper surface of the semiconductor substrate 10. (See diagram for example.) Figure 1 As shown, the active section 120 is provided with a transistor section 70, a diode section 80 and a boundary section 90.

[0161] In the active portion 120, the upper surface-side lifetime reduction region 92 is configured to cover the entire cathode region 82. In the X-axis direction, the upper surface-side lifetime reduction region 92 extends across the entire diode portion 80 and the entire boundary portion 90. In the Y-axis direction, the upper surface-side lifetime reduction region 92 is configured separately from the gate channel portion 51. The distance between the upper surface-side lifetime reduction region 92 and the gate channel portion 51 in the Y-axis direction can be 10 μm or more and 30 μm or less.

[0162] The upper surface-side lifetime reduction region 92 can also be disposed in a portion of the transistor section 70. The upper surface-side lifetime reduction region 92 is disposed in a manner that does not overlap with the gate insulating film 42. This suppresses damage to the gate insulating film 42 caused by irradiation from helium ions or the like. Alternatively, the upper surface-side lifetime reduction region 92 can be disposed overlapping with the dummy insulating film 32.

[0163] It should be noted that the upper surface-side lifetime reduction region 92 is preferably configured not to overlap with the gate pad 116. This protects the insulating film disposed between the gate pad 116 and the semiconductor substrate 10.

[0164] Additionally, the upper surface-side lifetime reduction region 92 can also be disposed on a plane parallel to the upper surface 21 of the semiconductor substrate 10, between the gate flow channel portion 51 and the outer peripheral end 140 of the semiconductor substrate 10. In this example, the upper surface-side lifetime reduction region 92 is disposed to cover the entire edge termination structure portion 150. This ensures that the upper surface-side lifetime reduction region 92 covering the edge termination structure portion 150 and the upper surface-side lifetime reduction region 92 disposed on the active portion 120 are separated when viewed from the upper surface, and do not overlap with the gate flow channel portion 51 and the gate metal layer 50 when viewed from the upper surface. By also providing the upper surface-side lifetime reduction region 92 on the edge termination structure portion 150, it is possible to suppress the movement of charge carriers from the edge portion of the semiconductor substrate 10 to the active portion 120 during reverse recovery, thereby improving reverse recovery tolerance.

[0165] Figure 10 This diagram shows another structural example on the upper surface of the semiconductor substrate 10. In this example, on a surface parallel to the upper surface of the semiconductor substrate 10, the diode portion 80 and the boundary portion 90 are surrounded by the transistor portion 70. More specifically, the diode portion 80 is surrounded by the boundary portion 90, and the boundary portion 90 is surrounded by the transistor portion 70. It should be noted that the range of the diode portion 80 in this example is the same as the range where the cathode region 82 is provided.

[0166] In this example, the upper surface-side lifetime reduction region 92 is configured to cover the entire diode section 80 and the entire boundary section 90. The upper surface-side lifetime reduction region 92 can also be configured in a part of the transistor section 70. The upper surface-side lifetime reduction region 92 can be configured separately, corresponding to the individual diode sections 80 that are separately configured when viewed from the upper surface.

[0167] Figure 11 This diagram illustrates another configuration example of the upper surface-side lifetime reduction region 92. In this example, the upper surface-side lifetime reduction region 92 is provided on a plurality of mesa sections 94-1 disposed at the ends of the transistor section 70 in the X-axis direction. The upper surface-side lifetime reduction region 92 is configured not to overlap with the gate trench section 40. In other words, when viewed from the upper surface, the upper surface-side lifetime reduction region 92 is provided on one or more mesa sections 94-1 sandwiched between adjacent gate trench sections 40, and the upper surface-side lifetime reduction region 92 is separated from the gate trench section when viewed from the upper surface. Between the upper surface-side lifetime reduction region 92 and the gate trench section, there are mesa sections 94-1 where the upper surface-side lifetime reduction region 92 is not provided.

[0168] The upper surface-side lifetime reduction region 92 can be disposed in the transistor section 70 overlapping with the dummy trench section 30. In this example, the upper surface-side lifetime reduction region 92 spans the dummy trench section 30 in the X-axis direction and is disposed from the vicinity of one gate trench section 40 to the vicinity of another gate trench section 40. As described above, the upper surface-side lifetime reduction region 92 is greater than the width of the channel region separated from the gate trench section 40.

[0169] It should be noted that at least one tabletop surface 94-1 does not have a top surface life reduction zone 92. The number of tabletop surfaces 94-1 without a top surface life reduction zone 92 can be greater than the number of tabletop surfaces 94-1 with a top surface life reduction zone 92.

[0170] The Y-axis end position of the upper surface-side lifetime reduction region 92 in the transistor section 70 can be the same as the Y-axis end position of the upper surface-side lifetime reduction region 92 in the diode section 80. The upper surface-side lifetime reduction region 92 in the transistor section 70 can be disposed overlapping with the emitter region 12, contact region 15, base region 14, and well region 17 in the Y-axis direction. The upper surface-side lifetime reduction region 92 is configured so as not to overlap with the gate channel section 51 and the gate metal layer 50. This protects the insulating film formed beneath the gate channel section 51 and the gate metal layer 50.

[0171] The end position of the upper surface side life reduction region 92 in the Y-axis direction can be compared with Figures 1-10 The same applies to any of the examples described herein. As an example, the upper surface-side lifetime reduction region 92 is provided in the transistor section 70 in such a way that it covers the entirety of at least one dummy trench section 30.

[0172] Figure 12 It means Figure 11 A diagram of an example of section a-a' in the figure. Figure 12 The mask 200 used in the manufacture of the semiconductor device 100 is also shown. In this example, a mask 200 is provided for one or more gate trench portions 40 at the end of the transistor portion 70, but no mask 200 is provided for one or more mesa portions 94-1 and one or more dummy trench portions 30. The mask 200 is configured such that the upper surface-side lifetime reduction region 92 is separated from the gate trench portion 40 by more than the channel width. The width of the mask 200 disposed above the gate trench portion 40 in the X-axis direction is greater than the sum of the width of the gate trench portion 40 and twice the channel width in the X-axis direction (e.g., about 0.1 μm).

[0173] Figure 13 This is a diagram illustrating another configuration example of the upper surface-side lifetime reduction region 92. In this example, the upper surface-side lifetime reduction region 92 is... Figure 11The difference between the example shown and the example shown is that the dummy trench portion 30 is not covered. In other words, the upper surface-side lifetime reduction region 92 in this example is provided on a plurality of mesa portions 94-1 at the end of the transistor portion 70 disposed in the X-axis direction. The upper surface-side lifetime reduction region 92 is configured not to overlap with the gate trench portion 40 and the dummy trench portion 30.

[0174] In this example, the upper surface-side lifetime reduction region 92 of the mesa 94-1 of the transistor section 70 is arranged in a ring shape when viewed from the upper surface. A dummy trench portion 30 is arranged in the area surrounded by the ring-shaped upper surface-side lifetime reduction region 92, and a gate trench portion 40 is arranged on the outer side of the ring.

[0175] It should be noted that the lifetime reduction region 92 on the upper surface side of the diode portion 80 and the boundary portion 90 can be related to... Figures 1-12 The example shown is similarly configured to cover the dummy trench 30, and can also be used with... Figure 13 The transistor section 70 shown is also arranged in a manner that does not cover the dummy trench section 30. Figure 13 The upper surface-side lifetime reduction region 92 of the diode portion 80 and the boundary portion 90 shown is provided in a manner that does not cover the dummy trench portion 30. The distance in the X-axis direction between the dummy trench portion 30 and the upper surface-side lifetime reduction region 92 can be the same as the distance in the X-axis direction between the gate trench portion 40 and the upper surface-side lifetime reduction region 92.

[0176] Figure 14 It means Figure 13 A diagram of an example of section a-a' in the figure. Figure 14 The mask 200 used in the manufacture of the semiconductor device 100 is also shown. In this example, masks 200 are provided for each trench portion. Masks 200 are not provided for one or more mesa portions 94-1 located at the ends of the transistor portion 70 in the X-axis direction. In addition, masks 200 are not provided for each mesa portion 94 of the diode portion 80 and the boundary portion 90. The mask 200 is arranged such that the surface-side lifetime reduction region 92 is greater than or equal to the trench width of each trench portion.

[0177] Figure 15 It means Figure 1 A diagram of another example of section a-a' in the figure. In this example, the semiconductor device 100 is relative to... Figures 1 to 14 The semiconductor device 100 shown also includes a lower surface-side lifetime reduction region 93a and a lower surface-side lifetime reduction region 93b. Other structures can be combined with... Figures 1 to 14 The semiconductor device 100 shown is identical in any of the manner described.

[0178] The lower surface-side lifetime reduction region 93a is positioned closer to the lower surface 23 than the center in the depth direction of the semiconductor substrate 10. The lower surface-side lifetime reduction region 93a can be set in the same range as the upper surface-side lifetime reduction region 92 when viewed from the upper surface, or it can be set in a different range.

[0179] The lower surface-side lifetime reduction region 93a can be formed by irradiating helium or the like from the upper surface 21 side of the semiconductor substrate 10. In this case, the concentration distribution of the recombination centers in the lower surface-side lifetime reduction region 93a has a shape that extends downwards from the depth position of the peak concentration Np2 to the upper surface 21 of the semiconductor substrate 10. The width of the lower surface-side lifetime reduction region 93a in the depth direction can be larger than the width of the upper surface-side lifetime reduction region 92 in the depth direction.

[0180] The lower surface-side lifetime reduction region 93b is positioned closer to the lower surface 23 side of the semiconductor substrate 10 in the depth direction than the lower surface-side lifetime reduction region 93a. The lower surface-side lifetime reduction region 93b can be set to the same extent as the upper surface-side lifetime reduction region 92 when viewed from the upper surface, or it can be set to a different extent. In this example, the lower surface-side lifetime reduction region 93b is set to cover the cathode region 82 when viewed from the upper surface within a narrower range than the upper surface-side lifetime reduction region 92.

[0181] The lower surface-side lifetime reduction region 93b can be formed by irradiating helium or the like from the lower surface 23 side of the semiconductor substrate 10. In this case, the concentration distribution of the recombination centers in the lower surface-side lifetime reduction region 93b has a shape that extends downwards from the depth position of the peak concentration Np3 to the lower surface 23 of the semiconductor substrate 10. The width of the lower surface-side lifetime reduction region 93b in the depth direction can be smaller than the width of the lower surface-side lifetime reduction region 93a in the depth direction.

[0182] The lower surface-side lifetime reduction region 93b can be formed inside the buffer zone 20 along the depth direction (Z-axis direction) of the semiconductor substrate 10. The peak position of the peak concentration Np3 of the lower surface-side lifetime reduction region 93b can be configured so that it does not overlap with multiple concentration peaks of the buffer zone 20.

[0183] Only one of the lower surface-side lifetime reduction regions 93a and 93b can be provided, or both can be provided. Multiple lower surface-side lifetime reduction regions 93a can be provided in the depth direction of the semiconductor substrate 10. Multiple lower surface-side lifetime reduction regions 93b can be provided in the depth direction of the semiconductor substrate 10. In this example, one lower surface-side lifetime reduction region 93a and one lower surface-side lifetime reduction region 93b are provided.

[0184] By providing the lower surface-side lifetime reduction region 93a, the carrier lifetime over a wide range in the depth direction measured from the upper surface 21 can be reduced according to the thickness of the semiconductor substrate 10, thereby reducing the reverse recovery current or reverse recovery charge. Furthermore, by providing the lower surface-side lifetime reduction region 93b, the tail current at the end of reverse recovery can be reduced, thus suppressing reverse recovery losses.

[0185] Figure 16 This is a diagram showing the structure of the upper surface of a semiconductor device 300 according to an embodiment of the present invention. The semiconductor device 300 is relative to... Figures 1-15 The semiconductor device 100 described herein also includes a protective film 400. The protective film 400 is formed of an insulating material such as polyimide. The protective film 400 may be formed of a material different from the gate insulating film 42 and the interlayer insulating film 26. At least a portion of the protective film 400 is disposed above the emitter electrode 52. The protective film 400 may or may not be connected to the semiconductor substrate 10. In this example, the protective film 400 is connected to the semiconductor substrate 10.

[0186] The protective film 400 is disposed on a surface parallel to the upper surface of the semiconductor substrate 10, such that it covers at least a portion of the gate flow channel portion 51. The protective film 400 may be disposed to cover the entire gate flow channel portion 51. In this example, the protective film 400 is continuously formed from the outer peripheral end 140 of the semiconductor substrate 10 to a position overlapping a portion of the active portion 120. The protective film 400 may be configured to cover the entire edge termination structure portion 150, the entire gate flow channel portion 51, and a portion of the active portion 120.

[0187] Additionally, the protective film 400 is configured to cover at least a portion of the gate pad 116. The protective film 400 is also configured to cover the gate flow channel portion 51 that is provided in a manner that surrounds a portion of the gate pad 116. An opening 401 is provided in the protective film 400 covering the gate pad 116 to expose a portion of the gate pad 116.

[0188] The cathode region 82 is disposed on a surface parallel to the upper surface of the semiconductor substrate 10 at a position that does not overlap with the protective film 400. In this example, the protective film 400 is configured to surround a portion of the active portion 120, and the cathode region 82 is disposed in the area of ​​the active portion 120 surrounded by the protective film 400.

[0189] This configuration makes it easy to arrange the upper surface-side lifetime reduction region 92, which covers the entire cathode region 82, so that it does not overlap with the protective film 400. In this example, the upper surface-side lifetime reduction region 92 is configured to overlap with the entire cathode region 82 on a surface parallel to the upper surface of the semiconductor substrate 10, but not with the protective film 400.

[0190] In the active portion 120 covered by the protective film 400, components such as transistors are disposed. If helium ions or the like are irradiated from the upper surface side of the protective film 400, forming an upper surface-side lifetime reduction region 92, the depth of helium ion implantation differs between the area covered by the protective film 400 and the area not covered by the protective film 400. For example, in the area covered by the protective film 400, helium ions are implanted more superficially compared to the area without the protective film 400, affecting the characteristics of components such as diodes and transistors.

[0191] In contrast, according to the semiconductor device 300, the upper surface-side lifetime reduction region 92 can be implanted to a uniform depth. Therefore, the characteristics of the semiconductor device 300 can be controlled with high precision. Furthermore, since helium ions or the like used to form the upper surface-side lifetime reduction region 92 can be irradiated from the upper surface of the semiconductor substrate 10, a localized upper surface-side lifetime reduction region 92 can be formed using a mask such as a photoresist without using a hard mask such as a metal. Therefore, the positional deviation of the upper surface-side lifetime reduction region 92 can be reduced. Because the positional deviation of the upper surface-side lifetime reduction region 92 can be reduced, the positional margin during design can be reduced. In addition, since the upper surface-side lifetime reduction region 92 is arranged to cover the entire cathode region 82, the peak current during reverse recovery of the diode section 80 can be suppressed.

[0192] The distances LX2 between the protective film 400 and the cathode region 82 in the X-axis direction and LY2 between the protective film 400 and the cathode region 82 in the Y-axis direction can both be 50 μm or more and 400 μm or less. This ensures the distance between the upper surface-side lifetime reduction region 92 and the protective film 400, and maintains the area of ​​the cathode region 82 at a certain level. At least one of the distances LX2 and LY2 can be 100 μm or more and 300 μm or less. At least one of the distances LX2 and LY2 can be a thickness ts or more and 2ts or less in the Z-axis direction of the semiconductor substrate 10. The distances LX2 and LY2 can be the same or different distances.

[0193] The distance LX1 between the protective film 400 and the upper surface lifetime reduction region 92 in the X-axis direction and the distance LY1 between the protective film 400 and the upper surface lifetime reduction region 92 in the Y-axis direction can both be 10 μm or more and 50 μm or less. This ensures that the distance from the edge of the protective film 400 to the end of the resist can be precisely controlled, even if the resist is formed near the edge of the protective film 400. At least one of the distances LX1 and LY1 can be 20 μm or more and 40 μm or less. The distances LX1 and LY1 can be the same or different. The distance LX1 can be smaller than the distance LX2, and the distance LY1 can be smaller than the distance LY2.

[0194] The Y-axis end of the gate trench portion 40 in the transistor portion 70 is located at a position overlapping with the protective film 400. In this example, the gate trench portion 40 is connected to the gate channel portion 51 at the position overlapping with the protective film 400.

[0195] The end of the dummy trench portion 30 in the diode portion 80 in the Y-axis direction can be located at a position overlapping with the protective film 400, or at a position not overlapping with the protective film 400. The end of the dummy trench portion 30 in the Y-axis direction can also be located at a position overlapping with the upper surface-side lifetime reduction region 92.

[0196] Furthermore, the overlap between the upper surface-side lifetime reduction region 92 and the transistor portion 70 in the X-axis direction can be 50 μm or more and 200 μm or less. The proportion of the area covered by the upper surface-side lifetime reduction region 92 relative to the entire transistor portion 70 can be 50% or less, 20% or less, or 10% or less. The arrangement of the upper surface-side lifetime reduction region 92 in the transistor portion 70 can be... Figures 1-15 Any of the methods described herein.

[0197] Figure 17A It means Figure 16 A diagram of an example of the c-c' section. (See diagram below.) Figure 16 As shown, the protective film 400 covers a portion of the transistor section 70 in the X-axis direction. The protective film 400 may not cover the boundary section 90 and the diode section 80 in the X-axis direction.

[0198] The upper surface-side lifetime reduction region 92 is provided in the X-axis direction to cover the entire diode section 80. The X-axis end position Xb of the upper surface-side lifetime reduction region 92 is disposed between the X-axis end position Xp of the protective film 400 and the X-axis end position Xc of the diode section 80.

[0199] The end position Xb can be configured between the boundary position Xt and the end position Xc of the boundary portion 90 and the transistor portion 70. In other words, the upper surface-side lifetime reduction region 92 can terminate at a position overlapping with the boundary portion 90 in the X-axis direction.

[0200] The end position Xb can be configured between the boundary position Xt and the end position Xp. In other words, the upper surface-side lifetime reduction region 92 can be configured as follows: Figure 16 The configuration shown overlaps with a portion of the transistor section 70.

[0201] Figure 17B This is a cross-sectional view of the semiconductor device 500 in an intermediate step of the manufacturing process of the comparative example. A transistor section 70, a boundary section 90, and a diode section 80 are provided in the active section 120 covered by a protective film 400. The protective film 400 extends from the transistor section 70 to the boundary section 90 and the diode section 80, with one end Xp' of the protective film 400 located within the diode section 80.

[0202] If a lifetime reduction region 92 is formed by irradiating helium ions or the like from the upper surface side of the protective film 400, the depth of helium ion implantation or the like differs between the area covered by the protective film 400 and the area not covered by the protective film 400. For example, if one end position Xp' of the protective film 400 is located inside the diode section 80 when viewed from the upper surface, and one end position Xr of the mask 200 is located closer to the outer periphery (-X-axis direction) of the semiconductor substrate 10 than position Xp', then the region between position Xr and position Xp' becomes an area that extends beyond the mask 200 and exposes the protective film 400.

[0203] If helium ions are irradiated from the upper surface 21 side of the semiconductor substrate 10 in this state, the upper surface 21 of the semiconductor substrate 10 is covered by the mask 200 at a position closer to the -X axis direction than the position Xr. As a result, the helium ions are blocked by the mask 200 and do not reach the protective film 400 and the semiconductor substrate 10.

[0204] On the other hand, in the region between position Xr and position Xp', only the protective film 400 blocks helium ions. Since the thickness of the protective film 400 is not sufficient to adequately block helium ions, helium ions penetrate the protective film 400 and reach the upper surface 21 of the semiconductor substrate 10. However, the helium ions are blocked by the protective film 400 to some extent. Therefore, compared to the position closer to the interior (+X-axis direction) than position Xp', a shallower upper surface-side lifetime reduction region 95 is formed on the upper surface 21 side. That is, in the same lifetime control (helium ions in this example) introduction process, the helium ions in the region where the protective film 400 is provided are injected shallower than in the region where the protective film 400 is not provided, affecting the characteristics of components such as diodes and transistors.

[0205] Figure 17C This is a cross-sectional view of the semiconductor device 300 in an intermediate step of the manufacturing process in this example. In the manufacturing process of this example, the mask 200 is formed such that one end Xr of the mask 200 is located closer to the interior (+X-axis direction) of the semiconductor substrate 10 than one end Xp of the protective film 400. In particular, one end Xp of the protective film 400 is located within the transistor portion 70 or the boundary portion 90 when viewed from the top surface, and one end Xr of the mask 200 is located within the diode portion 80 when viewed from the top surface. As a result, the lifetime reduction region 92 on the top surface side can be injected to a uniform depth. Therefore, the characteristics of the semiconductor device 300 can be controlled with high precision.

[0206] In this example, the mask 200 is in contact with the protective film 400 and, when viewed from the top surface, covers the protective film 400 and is also in contact with the emitter electrode 52. Therefore, since helium ions or the like used to form the top surface-side lifetime reduction region 92 can be irradiated from the top surface side of the semiconductor substrate 10, a localized top surface-side lifetime reduction region 92 can be formed using a mask such as a photoresist without using a hard mask such as a metal. Thus, the positional deviation of the top surface-side lifetime reduction region 92 can be reduced. Because the positional deviation of the top surface-side lifetime reduction region 92 can be reduced, the positional margin during design can be reduced. Furthermore, since the top surface-side lifetime reduction region 92 is arranged to cover the entire cathode region 82, the peak current during reverse recovery of the diode section 80 can be suppressed.

[0207] Figure 18 This is a diagram showing another structure of the upper surface of the semiconductor device 300. It should be noted that... Figure 18 Gate pad 116 is omitted from the diagram. In the semiconductor device 300 of this example, a portion (51-a) of the gate channel portion 51 is disposed within the active portion 120. In this example, the region of the active portion 120 including at least one of the transistor portion 70 and the diode portion 80 is referred to as the device region. The gate channel portion 51-a is disposed between the device regions (in other words, between the transistor portions 70, between the diode portions 80, and between the transistor portions 70 and the diode portions 80). It should be noted that in this example, the boundary portion 90 is also included within the device region.

[0208] A protective film 400 is also disposed above the gate flow channel portion 51-a. The protective film 400 is disposed in such a way that it covers the entire gate flow channel portion 51-a. Alternatively, a well region 17 may be formed along the gate flow channel portion 51-a. In this case, the protective film 400 may be disposed in such a way that it covers the entire well region 17. By providing the protective film 400, the insulating film disposed below the gate flow channel portion 51-a can be protected. In addition, the upper surface-side lifetime reduction region 92 is configured such that it does not overlap with the protective film 400 above the gate flow channel portion 51-a on a surface parallel to the upper surface of the semiconductor substrate 10. The distance in the Y-axis direction between the protective film 400 above the gate flow channel portion 51-a and the upper surface-side lifetime reduction region 92 can be [missing information]. Figure 16 The distance LY1 described in the text can be the same or different.

[0209] Figure 19 It means manufacturing Figures 1 to 17C A diagram illustrating a portion of the manufacturing process of semiconductor device 100 or semiconductor device 300 as described herein. Figure 19 Prior to the process shown, trenches, insulating films, and doped regions are formed on the upper surface of the N-type semiconductor substrate 10. These doped regions include emitter region 12, base region 14, contact region 15, well region 17, accumulation region 16, etc. In this example, drift region 18 is a region remaining in the semiconductor substrate 10 where no doped regions are formed. The process of forming the doped regions may include an implantation process for implanting impurities and a heat treatment process for activating the impurities.

[0210] Next, emitter electrode 52 and gate metal layer 50 are formed on the upper surface side of semiconductor substrate 10 (S1900). After forming the upper surface side electrodes, a protective film 400 with a predetermined pattern is formed. Next, the thickness of semiconductor substrate 10 is adjusted to a thickness corresponding to the desired withstand voltage by grinding or the like (S1902).

[0211] Next, doped regions such as collector region 22 and cathode region 82 are formed on the lower surface side of semiconductor substrate 10 (S1904). Buffer zone 20 may also be formed in S1906.

[0212] Next, a lifetime reduction region 92 on the upper surface side is formed by irradiating helium ions or the like from the upper surface side of the semiconductor substrate 10 (S1908). In S1908, a predetermined mask pattern formed of photoresist can be formed on the upper surface side of the semiconductor substrate 10. In S1908, the mask pattern of photoresist or the like is formed to cover the entire protective film 400. After irradiation with helium ions or the like, heat treatment is performed under predetermined conditions (S1910).

[0213] Next, a lower surface-side electrode, such as a collector electrode 24, is formed on the lower surface of the semiconductor substrate 10 (S1912). Next, at least the upper surface of the upper surface-side electrode is plated. During the plating process, the lower surface of the lower surface-side electrode may also be plated. By performing the plating process, the connection resistance between the copper lead frames, bonding wires, etc., and each electrode can be reduced.

[0214] It should be noted that in the process of forming the upper surface-side lifetime reduction region 92 (S1908), helium ions or the like are irradiated from the upper surface side to appropriately form unevenness on the upper surface of the upper surface-side electrode of aluminum or the like. By performing a plating process (S1914) after this process, the contact area between the upper surface of the upper surface-side electrode of the substrate and the plating layer can be increased. This improves the adhesion between the upper surface-side electrode and the plating layer, and also reduces the connection resistance. Furthermore, since the plating process (S1914) is performed after the heat treatment process (S1910), oxidation of the plating layer due to the heat treatment process S1910 can be prevented.

[0215] Figure 20 This diagram illustrates another example of a semiconductor device manufacturing method. The steps from S1900 to S1906 in this example are... Figure 19 The example is the same. In this example, after the S1906 process, the electrode on the lower surface side is formed (S1912).

[0216] Next, a plating process (S1914) is performed, after which a lifetime reduction region on the upper surface is formed (S1908). Then, a heat treatment process (S1910) is performed. Semiconductor devices can also be manufactured through such processes.

[0217] The present invention has been described above using embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be clear to those skilled in the art that various modifications or improvements can be made to the above embodiments. It is also clear that various modifications or improvements made according to the claims are included within the technical scope of the present invention.

[0218] The execution order of the actions, sequence, processes, and steps in the methods shown in the claims, specification, and drawings, even if described using terms such as "firstly," "nextly," etc. for convenience, does not mean that they must be performed in that order.

Claims

1. A semiconductor device, characterized by comprising: Possessing: a semiconductor substrate; a transistor section provided to the semiconductor substrate and having an emitter region of a first conductivity type on the upper surface side of the semiconductor substrate and a collector region of a second conductivity type on the lower surface side of the semiconductor substrate; a diode section provided to the semiconductor substrate and not having the emitter region on the upper surface side of the semiconductor substrate and having a cathode region of the first conductivity type on the lower surface side of the semiconductor substrate; a boundary section provided between the transistor section and the diode section and not having the emitter region on the upper surface side of the semiconductor substrate and having the collector region on the lower surface side of the semiconductor substrate; an emitter electrode provided above the upper surface of the semiconductor substrate; a protective film provided at least in part above the emitter electrode; and an upper surface side lifetime reduction region provided on the upper surface side of the semiconductor substrate in the entire diode section and a part region adjacent to the diode section in the boundary section in the arrangement direction and not provided in the transistor section, the cathode region not overlapping the protective film in a plane parallel to the upper surface of the semiconductor substrate, the protective film being provided only above a part of the transistor via the emitter electrode and not above the boundary section, the transistor section and the diode section being alternately arranged along a predetermined arrangement direction on the upper surface of the semiconductor substrate, the upper surface side lifetime reduction region overlapping the entire cathode region in a plane parallel to the upper surface of the semiconductor substrate and not overlapping the protective film, the upper surface side lifetime reduction region being provided in a manner of covering the entire cathode region in the arrangement direction, an end position of the arrangement direction of the diode section coinciding with an end position of the arrangement direction of the cathode region, an end position of the arrangement direction of the upper surface side lifetime reduction region being located in the boundary section and being arranged between an end position of the arrangement direction of the protective film and an end position of the arrangement direction of the diode section in a manner of not coinciding with the end position of the arrangement direction of the protective film and the end position of the arrangement direction of the diode section.

2. The semiconductor device according to claim 1, wherein The distance between the protective film and the upper surface side lifetime reduction region in a plane parallel to the upper surface of the semiconductor substrate is 10 μ or more.

3. The semiconductor device according to claim 2, wherein further possessing a gate flow channel section arranged between element regions including at least one of the transistor section and the diode section in a plane parallel to the upper surface of the semiconductor substrate, the protective film being further provided above the gate flow channel section, the upper surface side lifetime reduction region not overlapping the protective film above the gate flow channel section in a plane parallel to the upper surface of the semiconductor substrate.

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