Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a semiconductor channel layer, a gate structure, a composite region, a source terminal, and a drain terminal. The gate structure is disposed on the semiconductor channel layer. The source terminal and the drain terminal are disposed on the semiconductor channel layer. The composite region is disposed between the source terminal and the semiconductor channel layer, and between the drain terminal and the semiconductor channel layer, respectively.

Description

Technical Field

[0001] Embodiments of the present application relate to a semiconductor device and a method for manufacturing the same. Background Art

[0002] With the development of semiconductor manufacturing technology, more and more semiconductor devices and electronic components are integrated together, resulting in high integration density. Summary of the Invention

[0003] Some embodiments of the present application provide a semiconductor device, comprising: a semiconductor channel layer; a gate structure, disposed on the semiconductor channel layer; a source terminal and a drain terminal, disposed on the semiconductor channel layer; and a composite region, disposed between the source terminal and the semiconductor channel layer and between the drain terminal and the semiconductor channel layer, respectively, wherein the material of the semiconductor channel layer comprises indium gallium zinc oxide (IGZO), indium tin oxide (ITO), indium tungsten oxide (IWO), indium zinc oxide (IZO), zinc tin oxide (ZTO) or a combination thereof, and the composite region comprises a hydrogen-doped composite of the material of the semiconductor channel layer.

[0004] Other embodiments of the present application provide a semiconductor device, comprising: a semiconductor material layer; a gate layer, disposed above the semiconductor material layer; a gate dielectric layer, disposed between the gate layer and the semiconductor material layer; and a source and a drain, disposed on the semiconductor material layer, wherein the semiconductor material layer includes a composite region, and the composite region is in direct contact with the source and the drain.

[0005] Still other embodiments of the present application provide a method for manufacturing a semiconductor device, comprising: forming a gate structure and forming a semiconductor layer; forming an insulating layer above the gate structure and the semiconductor layer; forming a contact opening in the insulating layer that exposes a portion of the semiconductor layer; performing a process on the exposed portion of the semiconductor layer to form a composite region; and forming a source terminal and a drain terminal on the composite region. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figures 1 to 6 are schematic cross-sectional views of various stages in a method of manufacturing a semiconductor device according to some embodiments of the present invention.

[0008] Figure 7 and Figure 8 is a schematic cross-sectional view illustrating a semiconductor device according to some embodiments of the present invention.

[0009] Figure 9 are schematic cross-sectional views illustrating portions of structures and semiconductor devices therein according to some embodiments of the present invention.

[0010] Figures 10 to 16 are schematic cross-sectional views of various stages in a method of manufacturing a semiconductor device according to some embodiments of the present invention.

[0011] Figure 17 and Figure 18 is a schematic cross-sectional view illustrating a semiconductor device according to some embodiments of the present invention.

[0012] Figure 19 is a schematic perspective view illustrating a semiconductor device according to some embodiments of the present invention.

[0013] Figure 20 and Figure 21 is a schematic cross-sectional view illustrating a semiconductor device according to some embodiments of the present invention. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components, values, operations, materials, and arrangements, etc. are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. Other components, values, operations, materials, arrangements, etc. can be considered. For example, in the following description, forming a first component above or on a second component can include an embodiment in which the first component and the second component are directly in contact with each other, and can also include an embodiment in which additional components can be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention can repeat reference numerals and / or characters in various examples. This repetition is for simplicity and clarity purposes and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0015] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," and "upper" may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0016] In addition, for the sake of convenience in description, terms such as "first", "second", "third", "fourth", etc. may be used herein to describe similar or different elements or components as shown in the figures, and can be used interchangeably according to the order of existence or the context of description.

[0017] It should be understood that the following embodiments of the present invention provide applicable concepts that can be embodied in many specific contexts. The specific embodiments discussed herein are merely illustrative and relate to integrated structures that include more than one type of semiconductor device and are not intended to limit the scope of the invention. The embodiments of the present invention describe exemplary manufacturing processes for forming integrated structures having one or more semiconductor devices (such as transistors) and the integrated structures manufactured thereby. Certain embodiments of the present invention relate to structures that include semiconductor transistors and other semiconductor devices. The substrate and / or wafer may include one or more types of integrated circuits or electronic components therein. Semiconductor devices may be formed on bulk semiconductor substrates or silicon / germanium on insulator substrates. The embodiments are intended to provide further explanation but are not intended to limit the scope of the invention.

[0018] Figures 1 to 6 Schematic cross-sectional views of various stages in a method for manufacturing a semiconductor device according to some embodiments of the present invention. Figures 1 to 6 , showing a schematic cross-sectional view of the device region DR of the integrated structure. Figure 9 are schematic cross-sectional views illustrating portions of structures and semiconductor devices therein according to some embodiments of the present invention.

[0019] refer to Figure 1 In some embodiments, a substrate 100 having one or more connection structures 102 therein is provided. Figure 1 As shown, in some embodiments, a connection structure 102 (only one is shown) is formed in the substrate 100 within the device region DR. It should be understood that the number of connection structures 102 may be more than one, and the number or configuration of the connection structures 102 should not be limited by the exemplary embodiments or drawings of the present invention. Figures 1 to 6 , for illustration purposes, only a portion of the device region DR of the substrate 100 is shown. In some embodiments, the substrate 100 also includes one or more active components (such as transistors, diodes, optoelectronic devices) and / or one or more passive components (such as capacitors, inductors, and resistors). Figure 9 , the integrated structure 90 includes a substrate 900 and a semiconductor device 960 formed on the substrate 900. In some embodiments, the substrate 900 is substantially similar to Figure 1 substrate 100.

[0020] refer to Figure 1 and Figure 9In some embodiments, either substrate 100 or substrate 900 includes a semiconductor substrate. In one embodiment, substrate 100 or 900 includes a crystalline silicon substrate or a doped semiconductor substrate (e.g., a p-type semiconductor substrate or an n-type semiconductor substrate). In certain embodiments, depending on design requirements, substrate 100 or 900 includes one or more doped regions or doped regions of various types. In some embodiments, the doped regions are doped with p-type and / or n-type dopants. For example, the p-type dopant is boron or BF2, and the n-type dopant is phosphorus or arsenic. The doped regions can be configured for n-type metal oxide semiconductor (MOS) transistors or p-type MOS (PMOS) transistors. In some optional embodiments, substrate 100 or 900 includes a semiconductor substrate made of other suitable elemental semiconductors (such as diamond or germanium); suitable compound semiconductors (such as gallium arsenide, silicon carbide, indium arsenide, or indium phosphide); or suitable alloy semiconductors (such as silicon germanium carbide, gallium arsenide phosphide, or indium gallium phosphide).

[0021] In some embodiments, as Figure 9 As shown, substrate 900 includes transistors such as NMOS 902 and PMOS 904 formed in a semiconductor substrate 901. In one embodiment, NMOS 902 and / or PMOS 904 are formed after a complementary MOS (CMOS) process. Figure 9 As shown, in some embodiments, more than one isolation structure 906 is formed in the semiconductor substrate 901. In some embodiments, the isolation structure 906 is a trench isolation structure. In other embodiments, the isolation structure 906 includes a local oxidation of silicon (LOCOS) structure. In some embodiments, the insulating material of the isolation structure 906 includes silicon oxide, silicon nitride, silicon oxynitride, a spin-on dielectric material, or a low-k dielectric material. In one embodiment, the insulating material can be formed by CVD such as high-density plasma chemical vapor deposition (HDP-CVD) and sub-atmospheric pressure CVD (SACVD), or by spin coating. In some embodiments, transistors such as NMOS 902 and PMOS 904 and the isolation structure 906 are formed in the substrate 900 during the front-end of the line (FEOL) process.

[0022] In some embodiments, the substrate 900 includes a metallization structure 908 embedded in an insulating layer 910. Figure 9As shown, an insulating layer 910 and a metallization structure 908 are located above the transistors formed in the semiconductor substrate 901. In some embodiments, the insulating layer 910 includes one or more dielectric layers. In some embodiments, the material of the insulating layer 910 includes silicon oxide, a spin-on dielectric material, a low-k dielectric material, or a combination thereof. The formation of the insulating layer 910 includes, for example, one or more processes by chemical vapor deposition (CVD) or by spin coating. In some embodiments, the metallization structure 908 includes interconnect structures such as metal lines, vias, and contact plugs. In certain embodiments, the material of the metallization structure 908 includes aluminum (Al), an aluminum alloy, copper (Cu), a copper alloy, tungsten (W), or a combination thereof. In an exemplary embodiment, transistors such as NMOS 902 and PMOS 904 are electrically connected to the metallization structure 908, and some of the transistors are further electrically interconnected through the metallization structure 908. The metallization structure 908 shown herein is for illustrative purposes only, and the metallization structure 908 may include other configurations and may include one or more vias and / or damascene structures.

[0023] Reference again Figure 1 In some embodiments, the connection structure 102 embedded in the substrate 100 may be a part of a metallization structure in the substrate 100 for electrical connection and interconnection, and the metallization structure in the substrate 100 is similar to Figure 9 The metallization structure 908 is depicted. In one embodiment, the connection structure 102 includes a conductive via. Here, the connection structure 102 may be optional and is shown representatively for electrical connection purposes. Figure 1 In the embodiment of the present invention, a gate material layer 110 is blanket formed over the substrate 100 covering the connection structure. In one embodiment, the gate material layer 110 is in direct contact with the connection structure 102. In some embodiments, the gate material layer 110 includes one or more metal material layers. In some embodiments, the formation of the gate material layer 110 includes one or more deposition processes selected from chemical vapor deposition (CVD) (such as plasma-enhanced CVD (PECVD) and laser-assisted CVD), atomic layer deposition (ALD), and physical vapor deposition (PVD) (such as sputtering and electron beam evaporation). In some embodiments, the formation of the gate material layer 110 includes a plating process. In some embodiments, the gate material layer 110 is formed to have a thickness ranging from about 5 nm to about 100 nm. In some embodiments, the material of the gate material layer 110 includes aluminum (Al), titanium (Ti), tungsten (W), tantalum (Ta), their nitrides, combinations thereof, and / or alloys thereof. For example, the gate material layer 110 may include one or more stacked layers of TiN, TaN, W / TiN, TiN / TiAl / TiN, or TiN / TiAl / TaN.

[0024] exist Figure 1 In some embodiments, a gate dielectric material layer 120 is formed globally over the gate material layer 110. In some embodiments, the gate dielectric material layer 120 includes one or more high-k dielectric materials such as ZrO2, Gd2O3, HfO2, BaTiO3, Al2O3, LaO2, TiO2, Ta2O5, Y2O3, STO, BTO, BaZrO, HfZrO, HfLaO, HfTaO, HfTiO, or combinations thereof. In some embodiments, the gate dielectric material layer 120 includes one or more materials selected from aluminum oxide, hafnium oxide, tantalum oxide, and zirconium oxide. In some embodiments, the formation of the gate dielectric material layer 120 includes one or more deposition processes selected from CVD (such as PECVD and laser-assisted CVD), ALD, and PVD (such as sputtering and electron beam evaporation). In some embodiments, the gate dielectric material layer 120 is formed to have a thickness ranging from about 1 nm to about 20 nm. In some embodiments, the gate dielectric material layer 120 includes aluminum oxide, hafnium oxide, or a combination thereof. For example, the gate dielectric material layer 120 may be formed by depositing a composite layer of HfO 2 / Al 2 O 3 by ALD.

[0025] In some embodiments, after forming the gate dielectric material layer 120, a semiconductor material layer 130 and an optional barrier material layer 140 are sequentially formed over the gate dielectric material layer 120 to form the stacked structure 10. In some embodiments, the material of the semiconductor material layer 130 includes a metal oxide material. In some embodiments, the material of the barrier material layer 140 includes a semiconductor material or a metal oxide material. In some embodiments, the formation of the semiconductor material layer 130 and the barrier material layer 140 includes one or more deposition processes selected from CVD (such as PECVD and laser-assisted CVD), ALD, and PVD (such as sputtering, pulsed laser deposition (PLD), and electron beam evaporation). Optionally, when the formation of the semiconductor material layer 130 includes a CVD process or an ALD process, an annealing process may be included. In some embodiments, the semiconductor material layer 130 and the barrier material layer 140 are sequentially but continuously formed in the same PVD process or within the same reaction tool. In some embodiments, a semiconductor material layer 130 is blanket deposited over the gate dielectric material layer 120 using the same deposition process, and then a barrier material layer 140 is blanket formed over the top surface of the semiconductor material layer 130 as a barrier layer. In some embodiments, the semiconductor material layer 130 and the barrier material layer 140 are formed separately using different processes. In one embodiment, the semiconductor material layer 130 is formed to have a thickness ranging from approximately 1 nm to approximately 50 nm, and the barrier material layer 140 is formed to have a thickness substantially equal to or less than approximately 5 nm. In some embodiments, the semiconductor material layer 130 has a thickness greater than that of the barrier material layer 140. In some embodiments, the material of the semiconductor material layer 130 includes indium gallium zinc oxide (IGZO) or a similar conductive oxide semiconductor material, such as indium tin oxide (ITO), indium tungsten oxide (IWO), indium zinc oxide (IZO), or zinc tin oxide (ZTO), or a combination thereof. In some embodiments, the material of the barrier material layer 140 includes silicon (e.g., polysilicon), silicon-doped ITO or IGZO, a mixture thereof, or a combination thereof. In some embodiments, the material of barrier material layer 140 includes polysilicon or silicon-doped IGZO, a mixture thereof, or a combination thereof. In some embodiments, semiconductor material layer 130 is deposited using an ALD process, and barrier material layer 140 is also formed using an ALD process, and the reactants used in the ALD process can be adjusted or moved. In one embodiment, the material of barrier material layer 140 is different from that of semiconductor material layer 130. For example, the formation of barrier material layer 140 protects the surface of semiconductor material layer 130 (such as IGZO or other suitable materials).

[0026] refer to Figure 1 and Figure 2In some embodiments, a patterning process is performed on the stack structure 10 of the gate material layer 110, the gate dielectric material layer 120, the semiconductor material layer 130, and the barrier material layer 140, so that the stack structure 10 is patterned to form a stack structure 12 having a gate layer 111, a gate dielectric layer 121, a semiconductor layer 131, and a barrier layer 141 stacked sequentially from bottom to top. In some embodiments, the stack structure 10 of the gate material layer 110, the gate dielectric material layer 120, the semiconductor material layer 130, and the barrier material layer 140 is patterned into the stack structure 12 in one continuous patterning process. In some embodiments, the gate material layer 110, the gate dielectric material layer 120, the semiconductor material layer 130, and the barrier material layer 140 are patterned sequentially through multiple patterning processes. Figure 2 As shown, in an exemplary embodiment, the patterned stack structure 12 is disposed on the connection structure 102 , thereby exposing the substrate 100 . Figure 2 The sidewalls of the stacked structure 12 in the embodiment of the present invention can be shown as being vertically aligned or coplanar, and the stacked structure 12 can be shown as being patterned into substantially the same pattern design or configuration. However, it should be understood that the various layers of the stacked structure 12 can have different patterns or configurations depending on the product design. In some embodiments, the patterning and formation of the stacked structure 12 includes performing a photolithography process and an anisotropic etching process. In some embodiments, a photoresist pattern (not shown) can be used as an etching mask so that portions of the stacked structure 10 not covered by the photoresist pattern are removed during the etching process, and the photoresist pattern is then removed by a stripping process.

[0027] refer to Figure 3 An interlayer dielectric (ILD) layer 150 having a contact opening 155 is formed over the substrate 100. In some embodiments, the material of the ILD layer 150 includes silicon oxide, silicon nitride, silicon oxynitride, or one or more low-k dielectric materials. Examples of low-k dielectric materials include silicate glass (such as fluorosilicate glass (FSG), phosphosilicate glass (PSG), and borophosphosilicate glass (BPSG)), The ILD layer 150 may be formed of hydrogen silsesquioxane (HSQ), silicon oxyfluoride (SiOF), amorphous fluorinated carbon, parylene, BCB (bisbenzocyclobutene), or a combination thereof. It should be understood that the ILD layer 150 may include one or more dielectric materials or one or more dielectric layers. In some embodiments, the ILD layer 150 is formed to a suitable thickness by CVD (such as flowable CVD (FCVD), PECVD, high-density plasma CVD (HDPCVD), sub-atmospheric pressure CVD (SACVD), and low-pressure CVD (LPCVD)), spin coating, or other suitable methods. For example, the ILD layer 150 may be formed by PECVD to cover the exposed substrate 100 and the stacked structure 12 having the gate layer 111, the gate dielectric layer 121, the semiconductor layer 131, and the barrier layer 141. Subsequently, a contact opening 155 is formed in the ILD layer 150 that exposes the semiconductor layer 131. For example, forming the contact opening 155 includes forming a patterned mask layer (not shown) over the ILD layer 150 ; and anisotropically etching the ILD layer 150 and the barrier layer 141 using the patterned mask layer as a mask to form the contact opening 155 exposing the semiconductor layer 131 .

[0028] exist Figure 3 In the embodiment, the remaining portion of the barrier layer 141 is located between the contact openings 155. Figure 3 As shown, the contact opening 155 is shown as having substantially vertical sidewalls. It should be understood that the contact opening can be formed to have sloped sidewalls, if applicable.

[0029] exist Figure 4In the embodiment of the present invention, a process PT is performed on the semiconductor layer 131 exposed by the contact opening 155, and a composite region 135 is formed in the semiconductor layer 131. In some embodiments, the process PT includes performing an argon plasma treatment and a subsequent hydrogen annealing process. Optionally, in some embodiments, the process PT further includes performing an oxygen annealing process after the hydrogen annealing process. In one embodiment, the argon plasma treatment is performed in a plasma chamber with a process time ranging from about 1 second to 1 minute, a power between 100 W and 1500 W, and a base pressure of about 1 mT to about 150 mT. In some embodiments, the hydrogen annealing process is performed in a plasma chamber or using hydrogen plasma in an ambient air of hydrogen (H2) or a mixture of hydrogen and nitrogen (H2 / N2), with a process time ranging from about 1 minute to 1 hour, and at a temperature ranging from room temperature to about 450 degrees Celsius. In one embodiment, an oxygen annealing process is performed in a plasma chamber or using oxygen plasma in an ambient atmosphere of oxygen (O2) or a mixture of oxygen and nitrogen (O2 / N2) with a process time ranging from about 1 minute to 1 hour at a temperature ranging from room temperature to about 450 degrees Celsius. During the argon plasma treatment, more oxygen vacancies are generated in the semiconductor layer 131 by bombarding the exposed surface 131a of the semiconductor layer 131 with plasma or charges. At the oxygen vacancies (where there are no oxygen atoms in the crystal lattice), negative charge carriers withdraw to the vacancies and increase the local charge density. In a subsequent hydrogen annealing process, hydrogen is trapped in the oxygen vacancies, and hydrogen passivation stabilizes the oxygen vacancies, so that stable hydrogen-containing complexes are formed at these locations to form complex regions 135. In some embodiments, the complex regions 135 have a higher doping level than the untreated semiconductor layer 131. In some embodiments, the complex regions 135 are formed at locations corresponding to the locations of contacts to be formed later. In one embodiment, the complex regions 135 have a higher electron doping level (e.g., having a doping level of from 1E19 cm -3 to 1E21cm -3 The stable complex formed in the complex region 135 can serve as a shallow donor. Figure 4 In the embodiment of the present invention, the remaining barrier layer 141 can serve as a hydrogen barrier to prevent H from entering the semiconductor layer 131 at undesirable locations (i.e., locations other than the contact opening locations) during the PT process, particularly during the hydrogen annealing process. In some embodiments, the oxygen annealing process can further stabilize unpassivated oxygen vacancies and reduce oxygen vacancies in the semiconductor layer 131.

[0030] In some embodiments, during process PT, the exposed portion of the top surface 131a of the semiconductor layer 131 is bombarded and damaged during the plasma treatment, and the subsequently formed composite region 135 extends further into the semiconductor layer 131 from the treated surface 135a. In some embodiments, the treated surface 135a has a surface roughness that is higher than the surface roughness of the untreated top surface 131a of the semiconductor layer 131. In certain embodiments, recessing may occur in the exposed portion of the top surface 131a of the semiconductor layer 131, and the composite region 135 may have a dished or bowl-shaped surface. The composite region 135 formed in the semiconductor layer 131 and exposed by the contact opening 155 may have a thickness that varies at different locations (i.e., the depth extends vertically from the top surface 135a into the semiconductor layer 131 along the thickness direction). For example, the composite region 135 may be shaped like a disk having varying depths at different locations. Alternatively, the composite region 135 may be shaped like a disk having a uniform depth.

[0031] refer to Figure 4 In the partial enlarged view of the left portion of FIG, the composite region 135 formed in the semiconductor layer 131 can be damaged to have a dish-shaped or bowl-shaped surface 135a, and the composite region 135 extends vertically (along the thickness direction) from the top surface 135a into the semiconductor layer 131, with a maximum depth Dp at the periphery and a smaller depth Dc at the center (i.e., the center is shallower and the periphery is thicker). For example, the composite region 135 can be shaped like a concave disk with a shallower center and a thicker periphery. In one embodiment, the maximum depth Dp ranges from about 2 nm to about 10 nm, and the depth Dc ranges from about 1 nm to about 5 nm. That is, for example, the maximum depth is approximately twice the smaller depth of the composite region 135. Alternatively, the composite region 135 can be shaped like a disk with a thicker center and a shallower periphery. It should be understood that the shapes or contours of the composite regions shown in the drawings are merely exemplary and are not intended to limit the scope of the present application.

[0032] Afterwards, in Figure 5 In the embodiment, a contact terminal 160 is formed in the contact opening 155 to directly contact the composite region 135. In some embodiments, a barrier layer 162 is deposited over the contact opening 155 to conformally cover the sidewalls of the contact opening 155 and cover the top surface 135a of the composite region 135. In some embodiments, a seed layer 164 is formed over the contact opening 155 and on the barrier layer 162. In some embodiments, the barrier layer 162 is formed before the seed layer 164 is formed to prevent the material of the seed layer 164 from diffusing outward. After the seed layer 164 is formed to cover the sidewalls and bottom of the contact opening 155, a metal contact 166 is then formed on the seed layer 164 within the contact opening 155 to fill the contact opening 155. Figure 5 As shown, the contact terminal 160 is formed directly on the composite region 135 having the rough surface 135a. Since the composite region 135 has a higher electron doping level and increased conductivity, the contact resistance between the contact terminal 160 and the composite region 135 becomes lower. Figure 5 In the embodiment shown in FIG. 1 , the remaining portion of the barrier layer 141 is sandwiched between the contact terminals 160 and is located between the ILD layer 150 and the underlying semiconductor layer 131 .

[0033] In some embodiments, a barrier material (not shown) and a seed material (not shown) are sequentially formed over contact opening 155 to conformally cover the exposed surface of composite region 135 and the sidewalls of contact opening 155, and then a metal material (not shown) is filled into contact opening 155 and onto the seed material to form metal contact 166. The barrier material, seed material, and metal material may each include, for example, one or more materials selected from tungsten (W), ruthenium (Ru), molybdenum (Mo), tantalum (Ta), titanium (Ti), alloys thereof, and nitrides thereof. In some embodiments, the barrier material is formed by CVD or PVD. In some embodiments, the seed material is formed by CVD or PVD. In some embodiments, the metal material is formed by CVD or PVD. In alternative embodiments, the formation of the metal material may include performing a plating process (such as electrochemical plating (ECP)). In some embodiments, the barrier material includes titanium nitride (TiN) formed by a metal organic CVD (MOCVD) process, the seed material includes tungsten formed by CVD, and the metal material includes tungsten formed by a CVD process (particularly a tungsten CVD process). For example, the metal contact 166 includes a tungsten contact, and the barrier layer 162 includes a titanium nitride barrier layer.

[0034] In some embodiments, the additional barrier material, additional seed material, and additional metal material may be removed by performing a planarization process, an etching process, or other suitable process. In some embodiments, the planarization process may include performing a chemical mechanical polishing (CMP) process. In some embodiments, the barrier layer 162, the seed layer 164, and the metal contact 166 constitute the contact terminal 160. Figure 5 As shown, the top surface 150t of the ILD layer 150 is substantially flush with the top surface 160t of the contact terminal 160. In some embodiments, the contact terminal 160 serves as the source terminal and the drain terminal of the transistor. Figure 5, a transistor structure 50 is obtained. Transistor structure 50 includes a stacked structure 12 having a gate layer 111, a gate dielectric layer 121, a semiconductor layer 131, and a barrier layer 141 stacked sequentially from bottom to top, and a contact terminal 160 located on stacked structure 12. Semiconductor layer 131 serves as a channel layer, and the composite region between contact terminal 160 and semiconductor layer 131 becomes a composite interface, which helps reduce the contact resistance of the source terminal and the drain terminal. In some embodiments, transistor structure 50 is a bottom-gated transistor structure or a back-gated transistor structure.

[0035] refer to Figure 6 In some embodiments, an interconnect structure 170 is formed on the ILD layer 150 and above the contact terminal 160, and the semiconductor device structure 60 is formed. In one embodiment, the interconnect structure 170 is in direct contact with the contact terminal 160 and electrically connected to the contact terminal 160 of the transistor structure 50, so that the transistor structure 50 is further electrically connected to other components or devices. In some embodiments, the interconnect structure 170 includes a first metal line 172 formed on a first liner layer 174 and a first metal via 176 surrounded by a second liner layer 178. In some embodiments, a first liner material (not shown) is directly formed on the ILD layer 150 and on the top surface 160t of the contact terminal 160, a first metal layer (not shown) is formed on the first liner material, and then the first liner material and the first metal layer are patterned into the first metal line 172 and the first liner layer 174 using photolithography and etching techniques. The first liner material can be formed by, for example, PVD (such as sputtering) or CVD. In some embodiments, the first liner material includes, for example, tantalum, tantalum nitride, titanium, titanium nitride, tungsten, tungsten nitride, combinations thereof, or other suitable materials. In some embodiments, first liner layer 174 can prevent outdiffusion of the material of first metal line 172 and / or improve adhesion of first metal line 172. In some embodiments, the first metal layer can be formed by performing a plating process such as electrochemical plating (ECP) or electroless plating, a PVD process, or a CVD process. In some embodiments, the first metal layer includes, for example, copper, a copper-aluminum alloy, tantalum, titanium, tungsten, alloys thereof, or other suitable metal materials.

[0036] In some embodiments, as Figure 6 As shown, the first metal line 172 is in direct contact with and electrically connected to the contact terminal 160. For example, the first metal line 172 may include copper or a copper alloy and may be formed by implementing a PVD process and a CVD process. In one embodiment, the thickness of the first metal line 172 may be adjusted according to design requirements. Figure 6As shown, in some embodiments, another ILD layer 180 is formed over the ILD layer 150 and the first metal line 172. The material and formation method of the ILD layer 180 may be similar to the material and formation method of the ILD layer 150, and for simplicity, a detailed description thereof will be omitted herein. Subsequently, a via opening V is formed in the ILD layer 180 to partially expose the first metal line 172 below. The method for forming the via opening V is similar to the method for forming the contact opening 155. Figure 6 As shown, the via opening V is shown as having sloped sidewalls. It should be understood that the via opening can be formed with substantially vertical sidewalls, if feasible.

[0037] In some embodiments, Figure 6 In the embodiment of the present invention, a second liner layer 178 is formed in the via opening V, covering the sidewalls and bottom of the via opening V, and then a first metal via 176 is formed on the second liner layer 178 and within the via opening V. In some embodiments, a second liner material (not shown) is formed over the via opening V, conformally covering the exposed surface of the via opening V, and then a second metal layer (not shown) is formed over the ILD layer 180 to fill the opening V. The formation method and material of the second liner layer 178 are similar to the formation method and material of the first liner layer 174. The formation method and material of the first metal via 176 are similar to the formation method and material of the first metal line 172. For simplicity, a detailed description will be skipped here. However, it should be understood that the material of the first metal line 172 can be different from the material of the first metal via 176, and the material of the first liner layer 174 can be different from the material of the second liner layer 178.

[0038] Figure 6 The number and configuration of the metal lines and / or metal vias of the interconnect structure 170 shown are for illustration only. In some alternative embodiments, more than two metal lines or metal vias may be formed according to actual design requirements. In addition, a multi-layer interconnect structure may be formed for electrical connection and interconnection.

[0039] The semiconductor device structure 60 illustrates an integrated circuit or a portion thereof. In some embodiments, the semiconductor device structure 60 includes active devices such as oxide semiconductor thin film transistors, high voltage transistors, and / or other suitable components. In some embodiments, the semiconductor device structure 60 additionally includes passive components such as resistors, capacitors, inductors, and / or fuses. In some embodiments, for other embodiments of the method, the semiconductor device structure 60 may be configured as follows: Figures 1 to 6 Additional steps may be provided before, during, and after the process steps shown, and some of the steps described above may be replaced or eliminated.

[0040] In the illustrated embodiment, the described method and structure can be formed compatible with existing semiconductor manufacturing processes. In an exemplary embodiment, the described method and structure are formed during a back-end-of-line (BEOL) process. In some embodiments, the described method and structure can be formed during a mid-line process. In one embodiment, the transistor structure 50 includes an IGZO thin-film transistor.

[0041] In an exemplary embodiment, the composite region joining the channel layer (e.g., semiconductor layer) and the source and drain terminals results in more oxygen vacancies and a higher doping level in the channel layer directly below the contact terminals (in the contact region of the channel layer), which reduces the contact resistance between the channel layer and the source and drain terminals. Overall, this enhances the performance of the semiconductor device.

[0042] In the above-described embodiments, a composite region is formed in the semiconductor channel layer directly below the contact terminal in a self-aligned manner by performing a process through the contact opening, maintaining contact between the contact terminal and the channel layer. In some embodiments, the composite region formed in the semiconductor layer modifies the surface properties of the semiconductor layer in contact with the contact terminal and reduces the contact resistance between the semiconductor layer and the source and drain terminals.

[0043] Figure 7 Schematic cross-sectional views of semiconductor devices according to some embodiments of the present invention are shown. Figures 1 to 6 The process steps described in the previous embodiment shown in FIG. Figure 7 The exemplary structures shown are shown, but it should be understood that any other compatible process steps or methods can be utilized and that understandable modifications or adjustments can be made to form the exemplary structures of the present invention. Figure 7In some embodiments, semiconductor device structure 70 includes a stacked structure of a gate layer 710, a gate dielectric layer 720, a semiconductor layer 730, and a barrier layer 740, stacked sequentially from bottom to top. In some embodiments, semiconductor device structure 70 includes a source terminal 760A and a drain terminal 760B located above semiconductor layer 730, and a composite region 735 is located between source terminal 760A and semiconductor layer 730 and between drain terminal 760B and semiconductor layer 730, respectively. In some embodiments, source terminal 760A and drain terminal 760B are separated from each other by an interlayer dielectric (ILD) layer 750 located therebetween. In some embodiments, source terminal 760A includes a barrier layer 762A, and drain terminal 760B also includes a barrier layer 762B. In some embodiments, composite region 735 is in direct contact with source terminal 760A and drain terminal 760B. In one embodiment, the composite region 735 has a rougher or coarser rough surface 735a than the top surface 730t of the semiconductor layer 730. In one embodiment, the composite region 735 may have a slightly concave surface 735a relative to the top surface 730t of the semiconductor layer 730. In some embodiments, the portion of the barrier layer 740 located between the ILD layer 750 and the semiconductor layer 730 is sandwiched between the source terminal 760A and the drain terminal 760B. Figure 7 , composite region 735 is sandwiched between semiconductor layer 730 and barrier layer 762B. In one embodiment, bottom surfaces 760p of source terminal 760A and drain terminal 760B are substantially flush with bottom surface 740b of barrier layer 740. In one embodiment, bottom surfaces 760p of source terminal 760A and drain terminal 760B are slightly lower than bottom surface 740b of barrier layer 740. Suitable materials for various layers or elements are described in previous embodiments and will not be repeated here.

[0044] Figure 8 Schematic cross-sectional views of semiconductor devices according to some embodiments of the present invention are shown. Figures 1 to 6 Similar process steps as described in the previous embodiment shown are used to produce Figure 8 However, in some embodiments, the formation of the barrier material layer is skipped. Figure 8 The structure shown is Figure 7 The structures shown are similar but different, and the main structural differences are in the Figure 8 The semiconductor device structure 80 is shown without the optional barrier layer. Figure 8In some embodiments, the semiconductor device structure 80 includes a stacked structure of a gate layer 810, a gate dielectric layer 820, and a semiconductor layer 830 stacked sequentially from bottom to top. In some embodiments, the structure 80 includes a source terminal 860A and a drain terminal 860B located above the semiconductor layer 830 of the stacked structure, with a composite region 835 therebetween. In some embodiments, the source terminal 860A and the drain terminal 860B are separated from each other by an interlayer dielectric (ILD) layer 850. In some embodiments, the source terminal 860A and the drain terminal 860B are physically separated from the underlying semiconductor layer 830 by the composite region 835 located therebetween. In some embodiments, the composite region 835 is located only directly below the source terminal 860A and the drain terminal 860B and between the semiconductor layer 830 and the source terminal 860A and the drain terminal 860B. In some embodiments, the ILD layer 850 located between the source terminal 860A and the drain terminal 860B is in direct contact with the semiconductor layer 830. Figure 8 , source terminal 860A includes blocking layer 862A, and drain terminal 860B also includes blocking layer 862B.

[0045] In exemplary embodiments, the formation of the composite region between the channel layer (eg, semiconductor layer) and the source and drain terminals reduces contact resistance between the channel layer and the source and drain terminals, thereby improving performance of the semiconductor device.

[0046] Figures 10 to 16 are schematic cross-sectional views of various stages in a method of manufacturing a semiconductor device according to some embodiments of the present invention.

[0047] refer to Figure 10 In some embodiments, a substrate 300 is provided. Figures 10 to 16 , for illustration purposes, only a portion of the device region DR of the substrate 300 is shown. In some embodiments, the substrate 300 is similar to the substrates 100 and 900 in the previous embodiments, and the substrate 300 may include one or more active components (such as transistors, diodes, optoelectronic devices) and / or one or more passive components (such as capacitors, inductors, and resistors). In some embodiments, as Figure 10As shown, a semiconductor material layer 330 is formed over substrate 300. In one embodiment, semiconductor material layer 330 is formed to have a thickness ranging from about 1 nm to about 50 nm. In some embodiments, the material of semiconductor material layer 330 includes indium gallium zinc oxide (IGZO) or a similar conductive oxide semiconductor material, such as indium tin oxide (ITO), indium tungsten oxide (IWO), indium zinc oxide (IZO), or zinc tin oxide (ZTO). In some embodiments, the formation of semiconductor material layer 330 and barrier material layer 340 includes one or more deposition processes selected from CVD, ALD, and PVD. In one embodiment, semiconductor material layer 330 is made of IGZO formed by PVD.

[0048] refer to Figure 10 and Figure 11 In some embodiments, the semiconductor material layer 330 is patterned into a semiconductor layer 331 on the substrate 300, and the active region AR is defined by a patterning process. Subsequently, an isolation structure 305 is formed in the non-active region NAR surrounding the active region AR for isolation. Figure 11 As shown, in some embodiments, more than one isolation structure 305 is formed on the substrate 300. In some embodiments, the isolation structure 305 is a trench isolation structure, and the insulating material of the isolation structure 305 includes silicon oxide, silicon nitride, silicon oxynitride, spin-on dielectric material, or low-k dielectric material.

[0049] refer to Figure 12 , a gate dielectric layer 321, a gate layer 311, and a barrier layer 341 are sequentially formed and stacked on the semiconductor layer 331. In some embodiments, a gate dielectric material layer (not shown), a gate material layer (not shown), and a barrier material layer (not shown) are sequentially formed over the semiconductor layer 331 and the isolation structure 305, and then patterned into a stack of the gate dielectric layer 321, the gate layer 311, and the barrier layer 341 by photolithography and etching processes. Figure 12 As shown, in an exemplary embodiment, a stack structure 310 of a gate dielectric layer 321, a gate layer 311, and a barrier layer 341 is disposed on a semiconductor layer 331. In some embodiments, the stack structure 310 partially covers the underlying semiconductor layer 331, thereby exposing a portion of the semiconductor layer 331.

[0050] In some embodiments, as Figure 12 As shown, a stack structure 310 of a gate dielectric layer 321, a gate layer 311, and a barrier layer 341 is located within the active region AR. For example, the stack structure 310 can be considered as a gate structure with a barrier layer thereon. Figure 12The sidewalls of the stack structure 310 of the gate dielectric layer 321, the gate layer 311, and the barrier layer 341 may be shown as being vertically aligned or coplanar, and the semiconductor layer 331 may have a pattern different from the pattern of the stack structure 310 of the gate dielectric layer 321, the gate layer 311, and the barrier layer 341. However, it should be understood that the individual layers of the stack structure may have different patterns or configurations depending on product design.

[0051] exist Figure 13 In the embodiment, an ILD layer 350 having contact openings 355 and 356 is formed over the substrate 300 to cover the stacked structure 310 of the gate dielectric layer 321, the gate layer 311, and the barrier layer 341, the exposed semiconductor layer 331, and the isolation structure 305. The material and formation method of the ILD layer 350 are similar to those of the ILD layer described in the above paragraphs, and for simplicity, the details will be omitted here.

[0052] refer to Figure 13 , contact openings 355 and 356 are formed in the ILD layer 350 to expose portions of the semiconductor layer 331 and the barrier layer 341, respectively. In some embodiments, the contact opening 355 exposes a portion of the top surface 331a of the semiconductor layer 331. In some embodiments, the contact opening 356 exposes the barrier layer 341. Figure 13 As shown, contact openings 355 and 356 are shown as having substantially vertical sidewalls. It should be understood that, if feasible, the contact openings can be formed to have inclined sidewalls. The number or size of the contact openings is not limited to the number or size shown in the drawings.

[0053] In some embodiments, when the optional barrier layer is omitted, a contact opening (such as contact opening 356 ) exposing the gate structure may be subsequently formed in the ILD layer after processing is performed.

[0054] Afterwards, in Figure 14In the embodiment, a PT process is performed on the semiconductor layer 331 exposed by the contact opening 355, and a composite region 335 is formed in the semiconductor layer 331. During the PT process, the barrier layer 341 protects the gate dielectric layer 321 and the underlying gate structure of the gate layer 311 from damage at the locations exposed by the opening 356. In some embodiments, the PT process includes an argon plasma treatment followed by a hydrogen annealing process. Optionally, in some embodiments, the PT process also includes an oxygen annealing process. Suitable reactants and conditions are utilized, and the details are similar to those provided in the above embodiments. During the argon plasma treatment, the exposed surface 331a of the semiconductor layer 331 is bombarded with plasma or charges, generating more oxygen vacancies in the semiconductor layer 331. During the subsequent hydrogen annealing process, hydrogen is trapped in the oxygen vacancies, forming stable hydrogen-containing composites at these locations to form the composite region 335. In some embodiments, the composite region 335 includes an n-type composite. In one embodiment, the composite region 335 has a higher doping level and increased conductivity. In one embodiment, the composite region 335 has a higher electron doping level (eg, from 1E18 cm -3 to 1E21cm -3 The stable complex formed in the complex region 135 can serve as a shallow donor. Figure 14 Although exposed by the contact opening 356 , the barrier layer 341 may function as a barrier layer to block H from entering underlying layers of the gate structure or to prevent underlying layers from being damaged during the process PT.

[0055] In some embodiments, Figure 14 In the embodiment of the present invention, during the process PT, during the plasma treatment, the exposed portion of the top surface 331a of the semiconductor layer 331 is bombarded and damaged, and the subsequently formed composite region 335 extends further into the semiconductor layer 331 from the damaged surface 335a. In some embodiments, the treated surface 335a has a surface roughness higher than the surface roughness of the untreated top surface 331a of the semiconductor layer 331. In certain embodiments, recessing may occur in the exposed portion of the top surface 331a of the semiconductor layer 331, and the composite region 335 may have a dished or bowl-shaped surface. The composite region 335 formed in the semiconductor layer 331 and exposed by the contact opening 355 may have a dished or bowl-shaped surface 335a, and the composite region 335 may have a thickness that varies at different locations (i.e., the depth extends vertically from the top surface 335a into the semiconductor layer 331 along the thickness direction).

[0056] refer to Figure 15Contact terminals 360 are formed in contact openings 355 and contact openings 356. In some embodiments, contact terminals 360 formed in contact openings 355 are connected to composite regions 335, respectively. In some embodiments, contact terminals 360 are formed directly on damaged (or even concave) surfaces 335a of composite regions 335, and bottom surfaces 360b of contact terminals 360 are in direct contact with composite regions 335 formed in contact openings 355. In some embodiments, when barrier layer 341 is made of a conductive material, contact terminals 360 formed in contact openings 356 are connected to barrier layer 341. In some embodiments, barrier layer 362 is deposited over contact openings 355, 356, conformally covering the sidewalls and bottoms of contact openings 355, 356. Similar materials and formation methods used to form contact terminals 160 can be used to form contact terminals 360, and contact terminals 360 can be formed with a seed layer and / or adhesion layer, but for simplicity, the details will be omitted here. In an alternative embodiment, when barrier layer 341 is not made of a conductive material, barrier layer 341 exposed by contact opening 356 may be further etched to expose gate layer 311 , and contact terminal 360 formed in contact opening 356 is directly connected to gate layer 311 .

[0057] refer to Figure 15 In some embodiments, a transistor structure 30 is obtained, and the contact terminals 360 serve as source and drain terminals of the transistor. Figure 15 In the embodiment, transistor structure 30 includes a semiconductor layer 331, a stacked structure 310 (having a gate layer 311 stacked on a gate dielectric layer 321 and a barrier layer 341 located on gate layer 311), and a contact terminal 360 (located on semiconductor layer 331 and connected to a composite region 335). Semiconductor layer 331 serves as a channel layer, and composite region 335 located between contact terminal 360 and semiconductor layer 331 helps reduce the contact resistance between the source terminal and the drain terminal. In some embodiments, transistor structure 30 is a top-gated transistor structure or a gate-first transistor structure.

[0058] refer to Figure 16In some embodiments, an interconnect structure 370 and another ILD layer 380 are formed on the ILD layer 350, and a semiconductor device structure 40 is formed. In some embodiments, an interconnect structure 370 electrically connected to the contact terminal 360 of the transistor structure 30 is formed on and in direct contact with the contact terminal 360, so that the transistor structure 30 is further electrically connected to other components or devices. In some embodiments, the interconnect structure 370 includes a metal line 372 and a metal via 376 connected to the metal line 372. Similar materials and formation methods used to form the interconnect structure 170 can be used to form the interconnect structure 370, and the interconnect structure 370 can be formed together with a liner layer, a seed layer, and / or a barrier layer / adhesion layer, and a multi-layer interconnect structure can be formed for electrical connection and interconnection.

[0059] Although the steps of the method are shown and described as a series of steps or events, it should be understood that the order of such steps or events should not be interpreted in a limiting sense. In addition, not all shown processes or steps are required to implement one or more embodiments of the present invention.

[0060] Figure 17 1 is a schematic cross-sectional view illustrating a semiconductor device according to some embodiments of the present invention. Figure 17 In some embodiments, semiconductor device structure 42 includes a gate structure 1700 including a barrier layer 1740, a gate layer 1710, and a gate dielectric layer 1720 stacked sequentially (from top to bottom) on semiconductor layer 1730. In some embodiments, semiconductor device structure 42 includes a source terminal 1760A and a drain terminal 1760B directly located on composite region 1735. In some embodiments, source terminal 1760A and drain terminal 1760B are located on opposite sides of gate structure 1700 and are separated from gate structure 1700 by an interlayer dielectric (ILD) layer 1750 located therebetween. In some embodiments, source terminal 1760A and drain terminal 1760B may further include a seed layer and / or an adhesion / barrier layer. In some embodiments, the composite region 1735 may have a concave surface 1735a that is concave to the top surface 1730t of the semiconductor layer 1730, and the composite region 1735 is in direct contact with the source terminal 1760A and the drain terminal 1760B, respectively. In some embodiments, the ILD layer 1750 sandwiched between the source terminal 1760A and the drain terminal 1760B is directly located on the semiconductor layer 1730. Figure 17 In the embodiment, a composite region 1735 is formed between the semiconductor layer 1730 and bottom surfaces 1760p of the source terminal 1760A and the drain terminal 1760B.

[0061] Figure 18 is a schematic cross-sectional view illustrating a semiconductor device according to some embodiments of the present invention. Figure 18 The structure shown is Figure 17 The structures shown are similar but different, and the main structural differences are in the Figure 18 The semiconductor device structure 44 is shown without the barrier layer. Figure 18 In some embodiments, semiconductor device structure 44 includes a gate structure 1800 having a gate layer 1810 and a gate dielectric layer 1820 stacked on a semiconductor layer 1830. In some embodiments, structure 44 includes a source terminal 1860A and a drain terminal 1860B located on semiconductor layer 1830 with a composite region 1835 therebetween. In some embodiments, source terminal 1860A and drain terminal 1860B are physically separated from (but electrically connected to) the underlying semiconductor layer 1830 by composite region 1835. In some embodiments, gate structure 1800 is covered by an ILD layer 1850, and gate dielectric layer 1820 is in direct contact with semiconductor layer 1830.

[0062] Figure 19 is a schematic perspective view illustrating a semiconductor device according to some embodiments of the present invention. Figure 20 and Figure 21 The diagrams along lines AA' and BB' are respectively shown according to some embodiments of the present invention. Figure 19 Schematic cross-sectional view of a semiconductor device.

[0063] refer to Figure 19 In some embodiments, the semiconductor device structure 46 includes a semiconductor layer 1930 and a composite region 1935 located between the source and drain terminals 1960 and the semiconductor layer 1930. Figure 19 、 Figure 20 and Figure 21 It can be seen that the composite region 1935 occupies the interface between the source terminal 1960 and the drain terminal 1960 and the semiconductor layer 1930, and extends not only above the top surface 1930t of the semiconductor layer 1930 but also above the two opposite side surfaces 1930s of the semiconductor layer 1930. In some embodiments, the inverted U-shaped composite region 1935 has a damaged surface 1935a opposite to the top surface 1930t and the two opposite side surfaces 1930s of the semiconductor layer 1930. That is, the composite region 1935 covers at least three sides of the semiconductor layer 1930 and is surrounded by the source / drain terminals 1960. In one embodiment, the surface 1935a at the top side of the inverted U-shaped composite region 1935 is more damaged or concave than the other surfaces 1935a at the outer sidewalls of the inverted U-shaped composite region 1935. Figure 19 and Figure 20, the gate structure 1900 of the gate layer 1910 and the gate dielectric layer 1920 is disposed on and surrounds the top side and two opposite sides of the semiconductor layer 1930. Figure 19 In some embodiments, the gate structure 1900 may be shaped as an inverted U-shape that wraps around the semiconductor layer 1930. In some embodiments, the semiconductor device structure 46 includes source and drain terminals 1960 directly on the composite region 1935, and each of the source and drain terminals 1960 may be shaped as an inverted U-shape that wraps around the composite region 1935 and the semiconductor layer 1930. In some embodiments, the source and drain terminals 1960 are located at two opposite sides of the gate structure 1900 and are separated from the gate structure 1900 by an interlayer dielectric (ILD) layer (not shown) located therebetween. Figure 19 、 Figure 20 and Figure 21 For simplicity, the ILD layer is not shown. In some embodiments, source and drain terminals 1960 may further include a seed layer and / or an adhesion / barrier layer. In some embodiments, composite region 1935 is in direct contact with source and drain terminals 1960 and with semiconductor layer 1930, but no composite region is formed between gate dielectric layer 1920 and semiconductor layer 1930. In some embodiments, semiconductor device structure 46 comprises a dual-gate transistor structure.

[0064] In exemplary embodiments, the formation of a composite region between a channel layer (e.g., a semiconductor layer) and source and drain terminals reduces the contact resistance between the channel layer and the source and drain terminals. Overall, this enhances the performance of the semiconductor device. In some embodiments, the composite region formed in the semiconductor layer modulates the surface properties of the semiconductor layer and reduces the contact resistance between the semiconductor layer and the source and drain terminals.

[0065] In some embodiments of the present invention, a semiconductor device is described. The semiconductor device includes a semiconductor channel layer, a gate structure, a composite region, a source terminal, and a drain terminal. The gate structure is disposed on the semiconductor channel layer. The source terminal and the drain terminal are disposed on the semiconductor channel layer. The composite region is disposed between the source terminal and the semiconductor channel layer, and between the drain terminal and the semiconductor channel layer, respectively.

[0066] In some embodiments, the gate structure is located on a first side of the semiconductor channel layer, while the source and drain terminals are located on a second side of the semiconductor channel layer opposite the first side. In some embodiments, the semiconductor device further comprises a barrier layer extending over a top surface of the semiconductor channel layer and extending laterally between the source and drain terminals. In some embodiments, the barrier layer is made of polysilicon, silicon-doped indium tin oxide, indium gallium zinc oxide, or a combination thereof. In some embodiments, the gate structure and the source and drain terminals are located on the same side of the semiconductor channel layer, and the source and drain terminals are located on opposite sides of the gate structure. In some embodiments, the semiconductor device further comprises a barrier layer located on a surface of the gate structure. In some embodiments, the barrier layer is made of polysilicon, silicon-doped indium tin oxide, indium gallium zinc oxide, or a combination thereof. In some embodiments, the source and drain terminals are located on opposite sides of the gate structure, and the gate structure and the source and drain terminals surround the semiconductor channel layer. In some embodiments, the composite region extends over three sides of the semiconductor channel layer.

[0067] In some embodiments of the present invention, a semiconductor device is described. The semiconductor device includes a semiconductor material layer, a gate layer, a gate dielectric layer, a source electrode, and a drain electrode. The gate layer is disposed above the semiconductor material layer. The gate dielectric layer is disposed between the gate layer and the semiconductor material layer. The source electrode and the drain electrode are disposed on the semiconductor material layer. The semiconductor material layer includes a composite region, and the composite region is in direct contact with the source electrode and the drain electrode.

[0068] In some embodiments, the material of the semiconductor material layer includes indium gallium zinc oxide (IGZO), indium tin oxide (ITO), indium tungsten oxide (IWO), indium zinc oxide (IZO), zinc tin oxide (ZTO), or a combination thereof, and the composite region includes a hydrogen-doped composite of the material of the semiconductor material layer. In some embodiments, the source and the drain surround the semiconductor material layer, and the source and the drain are connected to the semiconductor material layer via the composite region extending over three sides of the semiconductor material layer. In some embodiments, the composite region has a curved surface, and the source and the drain in contact with the composite region have a curved surface. In some embodiments, the semiconductor device further includes: a metal contact connected to the gate layer.

[0069] In some embodiments of the present invention, a method for forming a semiconductor device is described. A gate structure and a semiconductor layer are formed. An insulating layer is formed over the gate structure and the semiconductor layer. A contact opening is formed in the insulating layer, exposing a portion of the semiconductor layer. The exposed portion of the semiconductor layer is processed to form a composite region. A source terminal and a drain terminal are formed on the composite region.

[0070] In some embodiments, forming a gate structure and forming a semiconductor layer includes forming a semiconductor material layer and patterning the semiconductor material layer into the semiconductor layer, and after patterning the semiconductor material layer, then forming the gate structure on the semiconductor layer. In some embodiments, forming a gate structure and forming a semiconductor layer includes: forming a gate material layer; forming a gate dielectric material layer; and sequentially forming a semiconductor material layer, and patterning the semiconductor material layer, the gate dielectric material layer, and the gate material layer into the semiconductor layer and the gate structure having the gate dielectric layer and the gate layer. In some embodiments, performing a process treatment includes performing an argon plasma treatment and performing a hydrogen annealing process. In some embodiments, performing a process treatment includes performing an argon plasma treatment, performing a hydrogen annealing process, and then performing an oxygen annealing process. In some embodiments, the method further includes forming a barrier layer on the semiconductor layer.

[0071] The features of several embodiments have been summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art will appreciate that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present invention, and that they may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device comprising: a semiconductor channel layer; a gate structure, disposed on a side of the semiconductor channel layer; a source terminal and a drain terminal disposed on the same side of the semiconductor channel layer as or on a different side from the gate structure; as well as a first complex region and a second complex region, the first complex region being disposed directly beneath the source terminal between the source terminal and the semiconductor channel layer, and the second complex region being disposed directly beneath the drain terminal between the drain terminal and the semiconductor channel layer, and wherein the first complex region is defined between outer sidewalls of the source terminal, wherein the material of the semiconductor channel layer comprises indium gallium zinc oxide (IGZO), indium tin oxide (ITO), indium tungsten oxide (IWO), indium zinc oxide (IZO), zinc tin oxide (ZTO) or a combination thereof, and the first composite region and the second composite region comprise hydrogen-doped composites of the materials of the semiconductor channel layer, wherein the first composite region and the second composite region have a concave shape in which the thickness of the central portion is less than the thickness of the peripheral portion and have a disk-shaped or bowl-shaped surface, wherein the peripheral portion surrounds the central portion, and the source terminal and the drain terminal are in contact with the disk-shaped or bowl-shaped surfaces of the first composite region and the second composite region, respectively.

2. The semiconductor device according to claim 1, wherein The gate structure is located on a first side of the semiconductor channel layer, and the source terminal and the drain terminal are located on a second side of the semiconductor channel layer opposite the first side.

3. The semiconductor device according to claim 2, further comprising: A barrier layer extends over a top surface of the semiconductor channel layer and extends laterally between the source terminal and the drain terminal.

4. The semiconductor device according to claim 3, wherein The material of the barrier layer includes polysilicon, silicon-doped indium tin oxide, indium gallium zinc oxide, or a combination thereof. The semiconductor device according to claim 1 , wherein The gate structure and the source and drain terminals are located on a same side of the semiconductor channel layer, and the source and drain terminals are located on two opposite sides of the gate structure.

6. The semiconductor device according to claim 5, further comprising: A blocking layer is located on the surface of the gate structure.

7. The semiconductor device according to claim 6, wherein The material of the barrier layer includes polysilicon, silicon-doped indium tin oxide, indium gallium zinc oxide, or a combination thereof.

8. The semiconductor device according to claim 1, wherein The source terminal and the drain terminal are located at two opposite sides of the gate structure, and the gate structure and the source terminal and the drain terminal surround the semiconductor channel layer.

9. The semiconductor device according to claim 8, wherein The first composite region extends over three sides of the semiconductor channel layer.

10. A semiconductor device comprising: a semiconductor material layer; a gate layer, disposed above the semiconductor material layer; a gate dielectric layer, disposed between the gate layer and the semiconductor material layer; as well as A source and a drain are arranged on the semiconductor material layer and separated by a barrier layer extending from the source to the drain in a first direction, wherein the semiconductor material layer includes a first composite region and a second composite region, wherein the first composite region is in direct contact with the source and the second composite region is in direct contact with the drain, and in the first direction, in a second direction perpendicular to the first direction, and in a third direction perpendicular to the first direction and the second direction, the first composite region is defined between outer side walls of the source, wherein the first composite region and the second composite region have a concave shape in which the thickness of the central portion is less than the thickness of the peripheral portion and have a dish-shaped or bowl-shaped surface, wherein the peripheral portion surrounds the central portion, and the source and the drain are in contact with the dish-shaped or bowl-shaped surfaces of the first composite region and the second composite region, respectively. The semiconductor device according to claim 10 , wherein: The material of the semiconductor material layer includes indium gallium zinc oxide (IGZO), indium tin oxide (ITO), indium tungsten oxide (IWO), indium zinc oxide (IZO), zinc tin oxide (ZTO) or a combination thereof, and the composite region includes a hydrogen-doped composite of the material of the semiconductor material layer.

12. The semiconductor device according to claim 10, wherein The source electrode and the drain electrode surround the semiconductor material layer, and the source electrode and the drain electrode are connected to the semiconductor material layer through the composite region extending over three sides of the semiconductor material layer.

13. The semiconductor device according to claim 10, wherein The composite region has a curved surface, and the source electrode and the drain electrode contacting the composite region have curved surfaces.

14. The semiconductor device according to claim 10, further comprising: A metal contact is connected to the gate layer.

15. A method for manufacturing a semiconductor device, comprising: forming a gate structure and forming a semiconductor layer; forming an insulating layer over the gate structure and the semiconductor layer; forming a contact opening in the insulating layer that exposes a portion of the semiconductor layer; performing a process on the exposed portion of the semiconductor layer to form a composite region within the exposed portion of the semiconductor layer; as well as A source terminal and a drain terminal are formed on the composite region, wherein the composite region has a concave shape in which a thickness of a central portion is smaller than a thickness of a peripheral portion and has a dish-shaped or bowl-shaped surface, wherein the peripheral portion surrounds the central portion, and the source terminal and the drain terminal are in contact with the dish-shaped or bowl-shaped surface of the composite region.

16. The method according to claim 15, wherein Forming the gate structure and forming the semiconductor layer includes forming a semiconductor material layer and patterning the semiconductor material layer into the semiconductor layer, and then forming the gate structure on the semiconductor layer after patterning the semiconductor material layer.

17. The method according to claim 15, wherein: Forming a gate structure and forming a semiconductor layer includes: forming a gate material layer; forming a gate dielectric material layer; and forming semiconductor material layers in sequence, and patterning the semiconductor material layer, the gate dielectric material layer and the gate material layer into the semiconductor layer and the gate structure having the gate dielectric layer and the gate layer.

18. The method according to claim 15, wherein The performing of the process treatment includes performing an argon plasma treatment and performing a hydrogen annealing process.

19. The method according to claim 15, wherein The performing of the process treatment includes performing an argon plasma treatment, performing a hydrogen annealing process, and then performing an oxygen annealing process.

20. The method of claim 15, further comprising forming a barrier layer on the semiconductor layer.

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