Queuing system to avoid head-of-line blocking

Abstract

A queuing system that avoids head-of-line blocking is disclosed. A control logic circuitry stores packets in a queue in an order in which the packets are received. A head entry of the queue corresponds to an earliest packet in the order. The control logic circuitry receives flow control information corresponding to a plurality of destination devices including at least a first destination device and a second destination device. The control logic circuitry determines, using the flow control information, whether the earliest packet stored in the head entry can be transmitted to the first destination device, and in response to determining that the earliest packet stored in the head entry cannot be transmitted to the first destination device, i) selects, in accordance with the order, another entry having another packet behind the head entry, and ii) transmits the another packet to the second destination device before transmitting the earliest packet in the head entry to the first destination device.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 008,523, filed April 10, 2020, entitled “Head-of-Line Block Avoidance While Preserving SRC-DEST Pair Packet Ordering,” and U.S. Provisional Patent Application No. 63 / 008,532, filed April 10, 2020, entitled “Head-of-Line Block Avoidance While Preserving SRC-DEST Pair Packet Ordering.” Both of the above-cited applications are incorporated herein by reference in their entirety. TECHNICAL FIELD

[0003] The present disclosure relates generally to computer processors, and more specifically, to systems for distributing data to multiple subsystems within a computer processor. BACKGROUND

[0004] Some data processing systems, such as parallel processing systems, image processors, machine learning (ML) systems, etc., include multiple processing subsystems (or cores), each including one or more processors, memory, etc., and data is distributed to the multiple processing subsystems by a data distribution system so that the multiple processing subsystems can process the data. As an illustrative example, the data distribution system distributes data retrieved from a main memory to multiple cores, and the data is stored in respective local memories of the cores. The cores then retrieve the data from the respective local memories and process the data.

[0005] Some such data distribution systems include routers with first-in-first-out (FIFO) queues to maintain the order of data packets distributed among the cores. However, if the destination is not ready to receive the data packet at the head of the FIFO queue, all other data packets in the FIFO queue cannot be transmitted, which is sometimes referred to as “head-of-line blocking.” Head-of-line blocking can result in processing delays and / or reduced throughput.

[0006] Some processing systems include routers that do not use FIFO queues so that packets can be sent in a different order than the order in which the packets were received, and thus avoid head-of-line blocking, but such routers require additional metadata to be allocated in the processing system, as well as additional logic and buffers at the destination to allow the order of the packets to be reconstructed at the destination. As an example, each data packet includes a source identifier and a packet identifier, the packet identifier indicating the order of the packet in a stream of packets from a source node corresponding to the source identifier. The data packets are stored in a reordering buffer at the destination node, and reordering logic at the destination node uses the source identifier and the packet identifier to reconstruct the order of the data packets received from the source node. The need to distribute such metadata, as well as the need for additional buffering and reordering logic at the destination, significantly increases the cost of the data processing system, particularly when the number of cores is high. SUMMARY

[0007] In one embodiment, an apparatus includes a queue comprising a plurality of entries, the plurality of entries comprising a head entry, and control logic circuitry configured to store, in the queue, packets received by the apparatus in an order in which the packets are received until the packets can be transmitted to a plurality of target devices, wherein the head entry corresponds to an earliest packet in the order. The control logic circuitry is further configured to receive flow control information corresponding to the plurality of target devices, the plurality of target devices comprising at least a first target device and a second target device, determine, using the flow control information, whether the earliest packet stored in the head entry can be transmitted to the first target device, and in response to determining that the earliest packet stored in the head entry cannot be transmitted to the first target device, i) select, in accordance with the order, another entry following the head entry, the other entry storing another packet that can be transmitted to the second target device, and ii) transmit the other packet to the second target device prior to transmitting the earliest packet in the head entry to the first target device.

[0008] In another embodiment, a method for transmitting packets to a set of multiple target devices includes receiving a plurality of packets; storing the plurality of packets in respective entries of a queue in an order in which the plurality of packets are received, wherein a head entry of the queue corresponds to an earliest packet in the order; receiving flow control information corresponding to the set of multiple target devices, the flow control information indicating whether one or more target devices of the set of multiple target devices are available to receive a packet; determining, using the flow control information, whether any target device to which the earliest packet is destined is available to receive the earliest packet; and in response to determining that no target device to which the earliest packet is destined is available to receive the earliest packet, selecting another entry following the head entry in the order, the other entry storing another packet destined to at least one target device that is available to receive the other packet, and transmitting the other packet in the other entry following the head entry in the order to the at least one target device to which the other packet is destined before transmitting the earliest packet in the head entry to the target device to which the earliest packet is destined. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 is a simplified diagram of an example data distribution node including head-of-line blocking avoidance logic according to an embodiment.

[0010] Figure 2 is a simplified diagram of an example queue having head-of-line blocking avoidance logic according to an embodiment, which is used in a data distribution node of Figure 1 .

[0011] Figures 3A-3B is a simplified diagram of a data packet queue of Figure 2 , which shows an example scenario involving updating a head pointer of the data packet queue according to an embodiment.

[0012] Figure 4 is a simplified diagram of another example queue having head-of-line blocking avoidance logic according to another embodiment, which is used in a data distribution node of Figure 1 .

[0013] Figure 5 is a flow diagram of an example method for maintaining flow control information in an example queue of Figure 4 according to an embodiment.

[0014] Figure 6 is a flow diagram of an example method for transmitting data packets from an example queue of Figure 4 according to an embodiment.

[0015] Figure 7 is a simplified diagram of a data distribution node of Figure 1 , Figure 2 a queue of Figure 4 , and / orThe flowchart illustrates an example method for implementing a queue, used to send packets to a collection of multiple target devices.

[0016] Figure 8 According to one embodiment, it utilizes Figure 1 Data distribution nodes Figure 2 queues and / or Figure 4 A simplified diagram of an example grid architecture for queues.

[0017] Figure 9 According to one embodiment, it includes Figure 8 A simplified diagram of an example processing subsystem in an example grid architecture. Detailed Implementation

[0018] The following description discloses numerous different embodiments or examples for implementing various features of this subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition is for the purpose of brevity and clarity and does not in itself prescribe a relationship between the various embodiments and / or configurations discussed.

[0019] Before describing the various embodiments in more detail, it should be understood that these embodiments are not limiting, as the elements in these embodiments can vary. It should also be understood that the particular embodiments described and / or illustrated herein have elements that can be readily separated from the particular embodiment and may optionally be combined with or substitute for elements in any of the other embodiments described herein. It should also be understood that the terminology used herein is for the purpose of describing certain concepts and is not intended to be limiting. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood in the art to which the embodiments pertain.

[0020] In the various embodiments described below, the processing system utilizes head-of-queue blocking avoidance systems and / or techniques that allow nodes to transmit data packets in an order different from the order in which they were received, while still maintaining the corresponding order of data packets between source and destination pairs. For example, in some embodiments, nodes include queues, and incoming data packets are stored in the queues in the order they were received. Furthermore, in some embodiments, nodes monitor the respective states of multiple destinations regarding whether each destination is ready to receive data packets. According to some embodiments, when a data packet arrives at the head of the queue and the destination of that packet is not ready to receive it, the node (according to the order in which the data packets were stored in the queue) selects another data packet from the queue intended for another destination to be ready to receive the data packet and sends that other data packet to that other destination.

[0021] Figure 1 is a simplified diagram of an exemplary data distribution node (sometimes referred to herein as a "router") 100 that can be included in a data processing system having multiple processing subsystems (or cores), each including one or more processors, memory, etc., in accordance with an embodiment. Router 100 distributes data packets from one or more sources (which can include, for example, one or more cores, one or more other routers, direct memory access (DMA) devices, etc.) in the data processing system to multiple targets 104 (which can include, for example, one or more cores, one or more other routers, DMA devices, etc.) in the data processing system.

[0022] In some embodiments, router 100 operates as a queuing system that receives data packets and stores the data packets in queues until the packets can be distributed to the multiple targets. In accordance with an embodiment, router 100 includes a first-in-first-out (FIFO) queue 108 (sometimes referred to herein as a "FIFO queue 108" for brevity) having head-of-line blocking avoidance logic that allows data packets to be output in an order that is different from the order in which the data packets are received at FIFO queue 108 while still preserving the respective order of data packets between source-destination pairs.

[0023] FIFO queue 108 receives data packets from a particular source and stores the data packets in the order in which the data packets are received from the source. In one embodiment, router 100 includes one or more other FIFO queues (not shown in FIG. 1 for the sake of clarity) that are the same as or similar to FIFO queue 108, and data packets received from one or more other sources are stored in the one or more other FIFO queues, respectively. In another embodiment, router 100 does not include any other FIFO queues that are the same as or similar to FIFO queue 108, and data packets received from one or more other sources are also stored in FIFO queue 108. In another embodiment, router 100 receives data packets only from a single source, and does not include any other FIFO queues that are the same as or similar to FIFO queue 108. Figure 1

[0024] ​The FIFO queue 108 is communicatively coupled to the plurality of targets 104. For example, in various embodiments, the FIFO queue 108 is communicatively coupled to the plurality of targets 104 via conductive traces and buffer circuitry. In some embodiments in which the router 100 receives data packets from one or more other sources, the router 100 includes data distribution and / or arbitration logic 112 (sometimes referred to herein for brevity as "data distribution logic 112") that communicatively couples the FIFO queue 108 with the plurality of targets 104. In an embodiment, the data distribution logic 112 includes crossbar circuitry configured to communicatively couple a plurality of inputs of the data distribution logic 112 (e.g., coupled to outputs of respective FIFO queues such as the FIFO queue 108) to a plurality of outputs of the data distribution logic 112 (e.g., communicatively coupled to inputs of respective targets 104). In some embodiments, each data packet includes or is associated with target identifier information (e.g., an address, a bitmap, etc.) that indicates one or more targets 104 to which the data packet is destined.

[0025] In some embodiments in which the data distribution logic 112 includes crossbar circuitry, the data distribution logic 112 includes arbitration circuitry that selects which of a plurality of data packets from a plurality of FIFO queues is routed to a single target 104 during a clock cycle when the plurality of data packets are destined for the single target 104 during the clock cycle.

[0026] In some embodiments in which the router 100 includes only a single FIFO queue 108, the data distribution logic 112 does not include arbitration logic and includes a multiplexer that routes data packets from the FIFO queue 108 to the targets 104. In some embodiments, target identifier information of data packets provided to inputs of the multiplexer is used to control the multiplexer such that the multiplexer routes data packets to intended targets 104.

[0027] FIFO queue 108 receives flow control information from targets 104, where the flow control information from each target 104 indicates whether the target 104 can accept packets from FIFO queue 108. For example, in some embodiments, target 104 includes an input queue in which incoming data packets are stored, and target 104 retrieves data packets from the input queue for processing. When the input queue of target 104 becomes full, target 104 cannot accept incoming data packets, and so target 104 indicates to FIFO queue 108 via flow control information that target 104 cannot accept incoming data packets. Similarly, when the input queue is no longer full, target 104 can again be used to accept incoming data packets, and so target 104 indicates to FIFO queue 108 via flow control information that target 104 is ready to accept incoming data packets.

[0028] In one embodiment, the flow control information from targets 104 includes credits that indicate how much buffer storage is available at target 104 (at least for FIFO queue 108), and FIFO queue 108 tracks the credits received from each target 104. When FIFO queue 108 transmits a data packet to a particular target 104, FIFO queue 108 decrements the credit for that target 104. If the credit for a particular target 104 is zero, it indicates that the target is not available to receive packets, so FIFO queue 108 does not allow the data packet to be transmitted to that target 104, and must wait until FIFO queue 108 receives additional credits from that target 104.

[0029] In another embodiment, the flow control information from targets 104 includes a stall signal that, when asserted, indicates that target 104 is not ready to receive data packets from FIFO queue 108; on the other hand, when the stall signal is not asserted, this indicates that target 104 is ready to receive data packets from FIFO queue 108.

[0030] In some embodiments in which data distribution logic 112 includes arbitration logic, FIFO queue 108 receives grant information from the arbitration logic, where the grant information indicates for each target 104 whether data distribution logic 112 will distribute a data packet from FIFO queue 108 to the target 104. Grant information is an example of transmit acknowledgement information that indicates whether a data packet was transmitted to a target.

[0031] In other embodiments, such as embodiments in which the data distribution logic 112 does not include arbitration logic, the FIFO queue 108 does not receive authorization information from the data distribution logic 112. In some embodiments in which the data distribution logic 112 does not include arbitration logic, the FIFO queue 108 receives transmit confirmation information from each of the destinations 104, the transmit confirmation information indicating whether the destination 104 received a data packet transmitted from the FIFO queue 108. In other embodiments in which the data distribution logic 112 does not include arbitration logic, the FIFO queue 108 does not receive transmit confirmation information. For example, in some embodiments, when the FIFO queue 108 outputs a data packet, the FIFO queue 108 assumes that the data packet was transmitted to the intended destination 104.

[0032] In operation, the router 100 receives data packets and stores the data packets in the FIFO queue 108 in the order in which the router 100 receives the data packets (the order in which the packets are received is sometimes referred to herein as the "receive order"). Generally, the router 100 stores the data packets until the packets can be transmitted to the multiple destinations 104. The FIFO queue 108 uses the flow control information received from the destinations 104 to determine whether the oldest data packet stored in a head entry of the FIFO queue 108 can be transmitted to the intended destination 104 of the oldest packet. In response to determining that the oldest data packet stored in the head entry cannot be transmitted to the intended destination, the FIFO queue 108 i) selects another entry following the head entry in the receive order, the other entry storing another data packet that can be transmitted to another destination 104, and ii) transmits the other data packet to the other destination before transmitting the oldest data packet in the head entry to the intended destination 104 of the oldest data packet. The other entry is considered to be "following the head entry" when the other entry stores a packet that was received by the FIFO queue 108 after the packet in the head entry. The other entry can immediately follow the head entry (i.e., there are no other entries between the head entry and the other entry), or there can be one or more other entries between the head entry and the other entry.

[0033] In other words, the FIFO queue 108 uses the flow control information from the destinations 104 to select which entry in the FIFO queue 108 is output to the data distribution logic 112. For example, if the intended destination 104 of the data packet in the head entry of the FIFO queue 108 is ready to receive the data packet, the FIFO queue 108 provides the data packet in the head entry to the data distribution logic 112. On the other hand, if the intended destination 104 of the data packet in the head entry of the FIFO queue 108 is not ready to receive the data packet, the FIFO queue 108 selects another data packet in another entry and provides the other data packet to the data distribution logic 112.

[0034] Figure 2is a simplified diagram of an example FIFO queue 200 (sometimes referred to herein as "FIFO queue 200" for brevity) having head-of-line blocking avoidance logic according to an embodiment. According to an embodiment, FIFO queue 200 is included in example router 100 as FIFO queue 108. In other embodiments, router 100 includes another suitable FIFO queue 108 that is different from FIFO queue 200. In some embodiments, FIFO queue 200 is included in another suitable queuing system that is different from router 100. Figure 1

[0035] FIFO queue 200 includes a data packet queue 204 having a plurality of entries 208 arranged in order (sometimes referred to herein as "entry order"). Although eight entries 208 are shown in Figure 2

[0036] In some embodiments, each entry 208 is associated with a respective memory address, and the memory addresses of entries 208 indicate the ordering of entries 208, i.e., the entry order. According to one illustrative embodiment, data packet queue 204 is included in a register set, each entry 208 corresponds to a respective register in the register set, and each memory address is an address of a respective register in the register set. In another example embodiment, data packet queue 204 is included in a random access memory (RAM), each entry 208 corresponds to a respective set of one or more memory locations in the RAM, and each memory address is an address of a respective memory location in the RAM.

[0037] The head pointer indicates a memory address of an entry 208 (sometimes referred to herein as "head entry") in which an earliest received data packet is stored, and the tail pointer indicates a memory address of an entry 208 in which a next incoming data packet should be stored.

[0038] ​​The pointer control logic 212 generates a head pointer and a tail pointer. For example, in conjunction with storing a new data packet (or a payload of a new data packet) in the queue 204, the pointer control logic 212 updates the tail pointer to point to the next entry 208 (according to the order of entries) in the data packet queue 204. Similarly, in conjunction with transmitting an oldest data packet (or a payload of a new data packet) from the data packet queue 204, the pointer control logic 212 updates the head pointer to point to the next entry 208 (according to the order of entries) in the queue. In some embodiments, the pointer control logic 212 is configured to increment (in a modulo fashion) the tail pointer in conjunction with storing a new data packet (or a payload of a new data packet) in the data packet queue 204, such that the tail pointer points to the next entry 208 in the data packet queue 204, and to increment (in a modulo fashion) the head pointer in conjunction with transmitting an oldest data packet (or a payload of a new data packet) from the data packet queue 204, such that the head pointer points to the next entry 208 in the data packet queue 204 that holds a new oldest entry. In other embodiments, the pointer control logic 212 is configured to decrement (in a modulo fashion) the tail pointer in conjunction with storing a new data packet (or a payload of a new data packet) in the data packet queue 204, such that the tail pointer points to the next entry 208 in the data packet queue 204, and to decrement (in a modulo fashion) the head pointer in conjunction with transmitting an oldest data packet (or a payload of a new data packet) from the queue 204, such that the head pointer points to the next entry 208 in the data packet queue 204 that holds a new oldest entry. In an embodiment, data packets are stored in the queue 204 such that the order of reception corresponds to the order of entries. For example, when the pointer control logic 212 updates the head pointer to point to the next entry 208 according to the order of entries, the head pointer will point to the next oldest data packet according to the order of reception.

[0039] In some embodiments, the pointer control logic 212 receives transmission acknowledgement information from the destination 104 Figure 1 ), and / or the data distribution logic 112 Figure 1 ), indicating when a data packet has been transmitted to the intended destination 104, and the pointer control logic 212 is configured to update (e.g., decrement, increment, etc.) the head pointer in response to transmission acknowledgement information indicating that the intended destination 104 received data stored in the head entry of the queue 204. In some embodiments in which the data distribution logic 112 Figure 1 ) includes arbitration logic, the pointer control logic 212 receives authorization information (an example of transmission acknowledgement information) from the arbitration logic indicating when a data packet has been transmitted to the intended destination 104, and the pointer control logic 212 is configured to update (e.g., decrement, increment, etc.) the head pointer in response to authorization information indicating that the intended destination 104 received data stored in the head entry of the queue 204.

[0040] FIFO queue 200 also includes a local destination information generator 214. When a data packet is received, local destination information generator 214 receives destination information in the data packet, or associated with the data packet. The destination information indicates one or more destinations to which the data packet is intended. In one embodiment, the destination information includes a bitmap, where each bit corresponds to a respective destination, and the bit is set to 1 to indicate that the corresponding destination is intended for the data packet, and the bit is set to 0 to indicate that the corresponding destination is not intended for the data packet. In another embodiment, the destination information includes an address corresponding to one or more destinations (e.g., a unicast address corresponding to a single destination, a multicast address corresponding to a set of multiple destinations, etc.).

[0041] In some embodiments, the destination information associated with each data packet (sometimes referred to herein as "system-level destination information") is used to identify a destination among a plurality of destinations of a larger system, where the plurality of destinations includes the destinations 104 that are locally coupled to router 100 Figure 1 ) as well as other destinations (e.g., destinations other than destinations 104) that are not locally coupled to router 100 Figure 1 ). Thus, in at least some such embodiments, the system-level destination information associated with each data packet has a length (in bits) that is longer than necessary to identify a destination among the destinations 104 that are locally coupled to router 100. Accordingly, in accordance with some embodiments, local destination information generator 214 is configured to generate local destination information that identifies a destination among destinations 104 using the system-level destination information, where the local destination information has a shorter length (in bits) than the system-level destination information.

[0042] In some embodiments, the local destination information generated by local destination information generator 214 includes a bitmap, where each bit corresponds to a respective destination 104, and the bit is set to 1 to indicate that the corresponding destination is intended for the data packet, and the bit is set to 0 to indicate that the corresponding destination is not intended for the data packet. In another embodiment, the local destination information includes an address corresponding to one or more destinations 104 (e.g., a unicast address corresponding to a single destination 104, a multicast address corresponding to a set of multiple destinations 104, etc.).

[0043] Local destination information generator is coupled to a control information queue 216 having entries 220, each of which corresponds to a respective entry 208 in data packet queue 204. For example, in accordance with one embodiment, entries 220 are arranged in the same or similar order as the order in which entries 208 of data packet queue 204 are arranged. Although control information queue 216 is shown as being separate from data packet queue 204, in other embodiments, control information queue 216 is integrated with data packet queue 204. Figure 2The local destination information for a received data packet is stored in an entry 220 of the control information queue corresponding to the entry 208 in the data packet queue 204 in which the data packet is stored. Thus, the local destination information stored in each entry 220 of the control information queue 216 indicates the destination 104 to which the corresponding data packet in the data packet queue 204 is to be transmitted.

[0044] The local destination information for a received data packet is stored in an entry 220 of the control information queue corresponding to the entry 208 in the data packet queue 204 in which the data packet is stored. Thus, the local destination information stored in each entry 220 of the control information queue 216 indicates the destination 104 to which the corresponding data packet in the data packet queue 204 is to be transmitted.

[0045] The FIFO queue 200 also includes a multiplexer 232 coupled to the data packet queue 204. The multiplexer 232 selects one of the entries 208 of the data packet queue 204 for output based on control information generated by entry selection logic 236.

[0046] The entry selection logic 236 receives flow control information from the destinations 104 Figure 1 ), local destination information from the control information queue 216, and the head pointer generated by the pointer control logic 212, and uses the flow control information, the local destination information, and the head pointer to generate control information provided to the multiplexer 232. The control information generated by the entry selection logic 236 controls the multiplexer 232 to select one of the entries 208 of the data packet queue 204 for output.

[0047] In one embodiment, the flow control information received by the entry selection logic 236 includes credits indicating how many buffers are available at the destination 104 (at least for the FIFO queue 200), and the entry selection logic 236 tracks the credits received from each destination 104. When the FIFO queue 200 transmits a data packet to a particular destination 104, the entry selection logic 236 decrements the credit for that destination 104. If the credit for a particular destination 104 is zero, the entry selection logic 236 determines that the destination 104 is not available to receive data packets from the FIFO queue 200.

[0048] In another embodiment, the flow control information from the destinations 104 includes a pause signal that, when asserted, indicates that the destination 104 is not ready to receive data packets from the FIFO queue 108; on the other hand, when the pause signal is not asserted, it indicates that the destination 104 is ready to receive data packets from the FIFO queue 108.

[0049] According to an embodiment, in response to determining using the flow control information that the intended destination of the data packet in the head entry is available to receive the data packet, the entry selection logic 236 controls the multiplexer 232 to select the head entry in the data packet queue 204 for output. Along with the multiplexer 232 outputting the head entry in the data packet queue 204, the pointer control logic 212 updates the head pointer to point to another entry 208 in the data packet queue 204 (according to the entry order and according to the receive order) that is after the head entry. The other entry 208 is considered to be "after" the head entry 208 according to the receive order when the other entry 208 includes another packet received by the data packet queue 204 after the data packet in the head entry 208 is received. The other entry 208 can immediately follow the head entry 208 (i.e., there are no other entries 208 between the head entry 208 and the other entry 208), or there can be one or more other entries 208 between the head entry 208 and the other entry 208.

[0050] On the other hand, in response to determining using the flow control information that the intended destination of the data packet in the head entry is not available to receive the data packet, the entry selection logic 236 controls the multiplexer 232 to select another entry 208 in the data packet queue 204 (according to the receive order) that is after the head entry for output. In some embodiments, when the entry selection logic 236 i) selects the other entry 208 (according to the receive order) that is after the head entry for output by the multiplexer 232, and ii) receives delivery acknowledgement information indicating that the packet stored in the other entry 208 was delivered to the intended destination, the entry selection logic 236 stores information in a corresponding entry 220 in the control information queue 216 indicating that the data packet stored in the other entry 208 was delivered to the intended destination. When the entry selection logic 236 is to select the other entry 208 (according to the receive order) that is after the head entry in the data packet queue 204 to be delivered, the entry selection logic 236 uses the control information in the control information queue 216 to select the entry 208 that stores a data packet that has not yet been delivered.

[0051] In one embodiment, when the intended destination of the data packet in the head entry is not available to receive the data packet, the entry selection logic 236 controls the multiplexer 232 to select (according to the receive order) another entry 208 following the head entry 208 that stores a data packet i) that has not yet been transmitted to the intended destination (e.g., determined using the control information in the control information queue 216), and ii) that is destined for a destination that is available to receive the data packet (e.g., determined using the flow control information in the control information queue 216). For example, in one embodiment, when the intended destination of the data packet in the head entry is not available to receive the data packet, the entry selection logic 236 selects (determined according to the receive order) the next entry 208 following the head entry 208 that stores i) a data packet that has not yet been transmitted to the intended destination, and ii) a data packet that is destined for a destination that is available to receive the data packet.

[0052] According to one embodiment, in connection with the data packet in the head entry being transmitted to the intended destination, the pointer control logic 212 uses the control information in the control information queue 216 to determine the next entry 208 (according to the entry order) that has not yet been transmitted to the intended destination, and updates the head pointer to point to the determined next entry 208. As an illustrative example, if the control information in the control information queue 216 determines that two entries immediately following the head entry have already been transmitted to the intended destination, according to one embodiment, in connection with the data packet in the head entry being transmitted to the intended destination, the pointer control logic 212 updates the head pointer to point to (according to the entry order) the third entry following the two entries.

[0053] Figures 3A-3B is a simplified diagram of the data packet queue 204 showing an example scenario involving updating of the head pointer by the pointer control logic 212 according to one embodiment. The entries 208 are arranged in entry order. For example, entry 208-2 follows entry 208-1, entry 208-3 follows entry 208-2, and so on. In one embodiment, the entry order is a circular order or a modulo order. For example, entry 208-1 follows entry 208-8 in entry order.

[0054] In Figure 3AIn the example scenario shown in FIG. 8, the head pointer points to entry 208-2 and the tail pointer points to entry 208-7. Entries 208-3, 208-4, and 208-6 are cross-hatched to indicate that the data packets in entries 208-3, 208-4, and 208-6 have already been delivered to the intended destination, while the data packet in the head entry 208-2 has not yet been delivered to the intended destination. For example, when the intended destination 204 of the first data packet in the head entry 208-2 is not available to receive the first data packet, the entry selection logic 236 controls the multiplexer 232 to deliver the second data packet in entry 208-3, the third data packet in entry 208-4, and the fourth data packet in entry 208-6. For example, the entry selection logic 236 determines that the intended destinations 204 of the second data packet, the third data packet, and the fourth data packet are available to receive the data packets. Thus, even though the intended destination of the first data packet in the head entry 208-2 is not ready to receive the first data packet, the first data packet in the head entry 208-2 does not prevent the second data packet in entry 208-3, the third data packet in entry 208-4, and the fourth data packet in entry 208-6 from being delivered to the other destinations 204.

[0055] Figure 3B The data packet queue 204 is shown after the first data packet in the head entry 208-2 has been delivered to the intended destination. In the example scenario shown in FIG. 8, the head pointer points to entry 208-5 and the tail pointer points to entry 208-7. Entries 208-3, 208-4, and 208-6 are cross-hatched to indicate that the second data packet and the third data packet in entries 208-3 and 208-4, respectively, have already been delivered to the intended destination; thus, when the head pointer is updated, the pointer control logic 212 "skips" entries 208-3 and 208-4. Figure 3A Figures 3A-3B

[0056] Figure 4 is a simplified diagram of another example FIFO queue 400 having head-of-line blocking avoidance logic (sometimes referred to herein as "FIFO queue 400" for brevity) in accordance with another embodiment. In accordance with an embodiment, the FIFO queue 400 is included in the example router 100 as the FIFO queue 108. In other embodiments, the router 100 includes another suitable FIFO queue 108 that is different from the FIFO queue 400. In some embodiments, the FIFO queue 400 is included in another suitable queuing system that is different from the router 100. Figure 1

[0057] ​​​The FIFO queue 400 allows data packets to be transmitted to multiple targets 104, such as multicasting data packets to multiple targets 104, broadcasting data packets to all targets 104, etc.

[0058] FIFO queue 400 includes queue 404, which has multiple entries 408 arranged in sequence (i.e., entry order). Although Figure 4 Eight entries 408 are shown, but queue 404 includes another suitable number of entries 408, different from the eight in other embodiments. At least the payload (or data portion) of an incoming data packet is stored in the corresponding entry 408 of queue 404 in the order in which the data packets are received at FIFO queue 400 (i.e., the receiving order). When a data packet is stored in entry 408 of queue 404, a bit in entry 408 (referred to herein as the "Entry_Valid bit") is set to 1 to indicate that the data packet needs to be transmitted to at least one destination 104. As described below, when FIFO queue 400 has transmitted the data packet in entry 408 to all the destinations 104 to which the data packet is intended, the Entry_Valid bit in entry 408 is then set to zero.

[0059] In one embodiment, each entry 408 is associated with a respective memory address, and the memory address of entry 408 indicates the order of the entries, i.e., the entry sequence. Queue 404 is included in a register set, each entry 408 corresponding to a corresponding register in the register set, and according to one embodiment, each memory address is the address of the corresponding register in the register set. In another embodiment, queue 404 is included in RAM, each entry 408 corresponding to a corresponding set of one or more memory locations in RAM, and each memory address is the address of the corresponding memory location in RAM.

[0060] The head pointer indicates the memory address where the earliest received data packet entry 408 (sometimes referred to herein as the "head entry") is stored, and the tail pointer indicates the memory address where the next incoming data packet entry 408 should be stored.

[0061] The pointer control logic 412 generates a head pointer and a tail pointer. For example, in conjunction with storing a new data packet (or a payload of a new data packet) in the queue 404, the pointer control logic 412 updates the tail pointer to point to the next entry 408 in the queue 404 (according to the order of entries). Similarly, in conjunction with transmitting the oldest data packet (or a payload of the oldest data packet) to all intended destinations of the oldest data packet, the pointer control logic 412 updates the head pointer to point to the next entry 408 in the queue (according to the order of entries and the order of reception). In some embodiments, the pointer control logic 412 is configured to increment (in a modulo fashion) the tail pointer in conjunction with storing a new data packet (or a payload of a new data packet) in the queue 404 such that the tail pointer points to the next entry 408 in the queue 404, and to increment (in a modulo fashion) the head pointer in conjunction with transmitting the oldest data packet (or a payload of the oldest data packet) from the queue 404 such that the head pointer points to the next entry 408 that holds a new oldest entry in the queue 404. In other embodiments, the pointer control logic 412 is configured to decrement (in a modulo fashion) the tail pointer in conjunction with storing a new data packet (or a payload of a new data packet) in the queue 404 such that the tail pointer points to the next entry 408 in the queue 404, and to decrement (in a modulo fashion) the head pointer in conjunction with transmitting the oldest data packet (or a payload of the oldest data packet) from the queue 404 such that the head pointer points to the next entry 408 that holds a new oldest entry in the queue 404.

[0062] In an embodiment, the data packets are stored in the queue 404 such that the order of reception corresponds to the order of entries. For example, when the pointer control logic 412 updates the head pointer to point to the next entry 408 according to the order of entries, the head pointer will point to the next oldest data packet according to the order of reception.

[0063] The FIFO queue 400 also includes a local destination information generator 414. When a data packet is received, the local destination information generator 414 receives destination information in the data packet, or destination information associated with the data packet. The destination information indicates one or more destinations that are to receive the data packet. In an embodiment, the destination information includes a bitmap, where each bit corresponds to a respective destination, and a bit is set to one to indicate that the corresponding destination is where the data packet is intended to go, and a bit is set to zero to indicate that the corresponding destination is not where the data packet is intended to go. In another embodiment, the destination information includes an address that corresponds to one or more destinations (e.g., a unicast address that corresponds to a single destination, a multicast address that corresponds to a set of multiple destinations, etc.).

[0064] In some embodiments, the destination information associated with each data packet (sometimes referred to herein as "system-level destination information") is used to identify a destination among a plurality of destinations of a larger system, where the plurality of destinations includes the destination 104 that is locally coupled to the router 100 (Figure 1 ) and not locally coupled to router 100 ( Figure 1 Other targets, such as targets other than target 104. Therefore, in at least some such embodiments, the length (in bits) of the system-level target information associated with each data packet is longer than the length necessary to identify targets in target 104 locally coupled to router 100. Therefore, according to some embodiments, the local target information generator 414 is configured to use the system-level target information to generate local target information that identifies targets in target 104, wherein the local target information has a shorter length (in bits) compared to the system-level target information.

[0065] The local target information generated by the local target information generator 414 includes a bitmap (referred to herein as "Local_Target_Vector"), where each bit corresponds to a corresponding target 104, and bits are set to 1 to indicate that the data packet is destined for the corresponding target 104, while bits are set to 0 to indicate that the data packet is not intended to go to the corresponding target 104. The local target information generator is coupled to queue 404 and stores the local target information (e.g., Local_Target_Vector) of the received data packets in entry 408, where the data packets are stored.

[0066] The FIFO queue 400 also includes a multiplexer 432 coupled to the queue 404. The multiplexer 432 selects one entry from the entries 408 of the queue 404 for output based on control information generated by the entry selection logic 436.

[0067] FIFO queue 400 also includes flow control logic 440, which receives data from target 104 ( Figure 1 The flow control logic 440 receives flow control information and uses it to maintain credit information for target 104 in memory 444. In one embodiment, the credit information for a particular target indicates how much buffer storage is available at the particular target 104 (at least for FIFO queue 400). In response to receiving credit update information (e.g., an example of flow control information) from the particular target 104, the flow control logic 440 increments the credit (an example of credit information) for the particular target 104 stored in memory 444 by the amount indicated by the received credit update information. As an illustrative example only, if the credit for the particular target 104 stored in memory 444 is equal to three credits, and if the flow control logic 440 receives credit update information for the particular target 104 indicating two new credits, then the flow control logic 440 increments the credit for the particular target 104 stored in memory 444 to five credits.

[0068] In some embodiments, the flow control logic 440 maintains information indicating whether there are any credits available to each target 104 (e.g., whether the credit for a target 104 is non-zero). In one embodiment, the information indicating whether there are any credits available to each target 104 includes a bitmap (referred to herein as a "Credit_Available_Vector") stored in the memory 444. Each bit of the Credit_Available_Vector corresponds to a respective target 104, with a bit value of 1 indicating that there is a non-zero number of credits available to the respective target 104 and a bit value of 0 indicating that there are zero credits available to the respective target 104.

[0069] Figure 5 is a flowchart of an example method 500 for maintaining flow control information in a queuing system, according to an embodiment. The method 500 is implemented by the flow control logic 440 according to an embodiment, and the method 500 is described with reference to the Figure 4 queuing system 100 of FIG. 1 for purposes of explanation. However, in other embodiments, the method 500 is implemented in another suitable queuing system, and / or the flow control logic 440 implements another suitable method for maintaining flow control information.

[0070] In some embodiments, the method 500 is implemented periodically by the queuing system (e.g., by the flow control logic 440). In other embodiments, the method 500 (or at least a portion of the method 500) is implemented by the queuing system (e.g., by the flow control logic 440) in response to an event, such as the queuing system receiving flow control information from one or more targets 104 and / or the queuing system transmitting data packets to one or more targets 104.

[0071] At block 504, the queuing system receives (e.g., the flow control logic 440 receives) flow control information from one or more targets 104. For example, the queuing system receives (e.g., the flow control logic 440 receives) credit update information from one or more targets 104.

[0072] At block 508, the queuing system updates (e.g., the flow control logic 440 updates) credit information maintained by the queuing system (e.g., the flow control logic 440) for the targets 104 using the flow control information received at block 504. For example, the flow control logic 440 uses the credit update information received from one or more of the targets 104 to update the credit information in the memory 444. As an illustrative example only, if the credit stored in the memory 444 for a particular target 104 equals one credit, and if the flow control logic 440 receives credit update information for the particular target 104 indicating one new credit, the flow control logic 440 increments the credit stored in the memory 444 for the particular target 104 to two credits.

[0073] At block 512, in response to the queuing system transferring a packet to a target 104, the queuing system updates (e.g., the flow control logic 440 updates) credit information for the target 104. For example, as will be further described below, when a data packet is transferred to a particular target 104, the entry selection logic 436 can decrement the credit in the memory 444 for the particular target 104.

[0074] At block 516, the queuing system updates (e.g., the flow control logic 440 updates) information indicating whether there are any credits available for each of the targets 104 (e.g., whether the credit for a target 104 is non-zero). For example, the flow control logic 440 updates the Credit_Available_Vector in the memory 444. As an example, if the credit for a particular target 104 is changed, e.g., at block 508, from zero to a non-zero value, the flow control logic 440 updates the bit in the Credit_Available_Vector corresponding to the particular target 104 from 0 to 1. In addition, in some embodiments, as an example, the flow control logic 440 also updates the Credit_Available_Vector when the credit for a particular target 104 changes from a non-zero value to zero; specifically, the flow control logic 440 updates the bit in the Credit_Available_Vector corresponding to the particular target 104 from 1 to 0. Thus, in some embodiments, block 516 is also performed in response to the FIFO queue 400 transferring data packets to one or more of the targets 104 and / or in response to the FIFO queue 400 receiving transfer acknowledgement information from the data distribution logic 112, e.g., indicating that data packets were transferred to one or more of the targets 104.

[0075] Referring again to Figure 4The entry selection logic 436 receives from the queue 404 i) the local target information (e.g., Local_Target_Vectors), ii) the head pointer generated by the pointer control logic 412, and iii) the credit information in the memory 444, and uses such information to generate control information provided to the multiplexer 432, the control information generated by the entry selection logic 436 controlling the multiplexer 432 to select one of the entries 408 of the queue 404 for output.

[0076] The entry selection logic 436 determines whether any of the intended targets 104 of the data packet in the head entry 408 are available to receive the packet. For example, according to an embodiment, the entry selection logic 436 performs a bitwise logical AND operation on the Local_Target_Vectors in the head entry 408 and the Credit_Available_Vectors in the memory 444 to generate a Transfer_Vector for the head entry 408 (e.g., a respective bit of the Transfer_Vector corresponding to a respective target 104 is generated by performing a bitwise AND operation on a respective bit of the Local_Target_Vector corresponding to the respective target 104 and a respective bit of the Credit_Available_Vector corresponding to the respective target 104). Each bit of the Transfer_Vector for the entry 408 corresponds to a respective target 104 and indicates i) whether the data packet in the entry 408 is intended for the respective target 104, and ii) whether the respective target 104 is available to receive the data packet.

[0077] If at least one bit of the Transfer_Vector is set to one for the head entry 408, this indicates that at least one of the intended targets 104 of the data packet in the head entry 408 is available to receive the packet. Accordingly, the entry selection logic 436 generates a control signal to control the multiplexer 432 to select the head entry for output to the crossbar switch. In addition, the entry selection logic 436 outputs the Transfer_Vector to the crossbar switch, the Transfer_Vector controlling the crossbar switch to direct the data packet in the head entry to the targets 104 indicated by the Transfer_Vector, e.g., the targets 104 that are both i) intended to receive the data packet, and ii) available to receive the data packet.

[0078] In response to outputting i) the data packet in the head entry 408 and ii) the Transfer Vector to the crossbar, the entry selection logic 436 receives transfer acknowledgement information regarding the data packet in the head entry 408. The transfer acknowledgement information indicates the destination(s) 104 to which the data packet in the head entry 408 was successfully transferred. In an embodiment, the transfer acknowledgement information includes grant information from arbitration logic associated with the crossbar. The grant information includes a bitmap (referred to herein as a "Grant Vector") in which each bit corresponds to a respective destination 104. When the arbitration logic grants the FIFO queue 400 access to a particular destination 104, the arbitration logic sets the corresponding bit in the Grant Vector to 1, and when the arbitration does not grant the FIFO queue 400 access to a particular destination 104, the arbitration logic sets the corresponding bit in the Grant Vector to 0.

[0079] When the transfer acknowledgement information (e.g., the Grant Vector) is received, the entry selection logic 436 uses the acknowledgement information to modify the Local Target Vector in the head entry 408 to indicate that the data packet in the head entry 408 has been transferred to the destinations 104 indicated by the transfer acknowledgement information. As an example, for each bit in the Grant Vector that is set to 1, the entry selection logic 436 sets the corresponding bit in the Local Target Vector to 0. If all bits in the Local Target Vector are zero, this indicates that the data packet in the head entry 408 has been transferred to all intended destinations 104, and the entry selection logic 436 sets the Entry Valid bit in the head entry 408 to zero. On the other hand, if at least one bit in the Local Target Vector is not zero, this indicates that there is at least one destination 104 to which the packet in the head entry 408 still needs to be transferred, and the entry selection logic 436 leaves the Entry Valid bit in the head entry 408 set to 1.

[0080] If, on the other hand, the entry selection logic 436 determines that there is no intended recipient 104 of the data packet available to receive the data packet in the head entry 408 (e.g., all bits in the Transfer Vector of the head entry 408 are zero), the entry selection logic 436 selects the next entry 408 (in the receive order) behind the head entry for which i) the data packet still needs to be sent to at least one intended recipient 104, and ii) there is at least one intended recipient 104 available to receive the data packet. According to an embodiment, for example, the entry selection logic 436 selects the next entry 408 (in the receive order) behind the head entry for which i) the Entry_Valid bit is set to one, and ii) at least one bit in the Transfer Vector of the entry 408 is set to one. According to an embodiment, the entry selection logic 436 performs a bitwise logical AND operation on the Local Target Vector of the entry 408 and the Credit Available Vector in the memory 444 to generate the Transfer Vector of the entry 408 (e.g., a bitwise AND operation on the respective bit in the Local Target Vector corresponding to a respective target 104 and the respective bit in the Credit Available Vector corresponding to the respective target 104 to generate the respective bit in the Transfer Vector corresponding to the respective target 104). Each bit in the Transfer Vector of the entry 408 corresponds to a respective target 104 and indicates i) whether the data packet in the entry 408 is intended for the respective target 104, and ii) whether the respective target 104 is available to receive the data packet.

[0081] Accordingly, the entry selection logic 436 generates control signals to control the multiplexer 432 to select (in the receive order) the next entry 408 behind the head entry for which i) the data packet still needs to be sent to at least one intended recipient 104, and ii) there is at least one intended recipient 104 available to receive the data packet. In addition, the entry selection logic 436 outputs the Transfer Vector of the selected entry 408 to the crossbar, which controls the crossbar to direct the data packet in the selected entry 408 to the targets 104 indicated by the Transfer Vector, e.g., the targets 104 that are both i) intended to receive the data packet and ii) available to receive the data packet.

[0082] In response to outputting i) the data packet in the selected entry 408 and ii) the Transfer Vector to the crossbar, the entry selection logic 436 receives transfer acknowledgement information regarding the data packet in the selected entry 408, the transfer acknowledgement information indicating the destination(s) 104 to which the data packet in the selected entry 408 was successfully transferred. In an embodiment, the transfer acknowledgement information includes grant information from arbitration logic associated with the crossbar. According to an embodiment, the grant information includes the Grant Vector discussed above.

[0083] When receiving the transfer acknowledgement information (e.g., the Grant Vector), the entry selection logic 436 uses the acknowledgement information to update credit information in the memory 444 for the destination(s) to which the data packet was transferred. As an example, for each bit in the Grant Vector that is set to one, the entry selection logic 436 decrements the credit in the memory 444 for the corresponding destination 104. As an illustrative example, if the credit in the memory for a particular destination 104 is set to four, and a bit in the Grant Vector corresponding to the particular destination 104 is set to one, the entry selection logic 436 decrements the credit in the memory for the particular destination 104 to three.

[0084] Also, when receiving the transfer acknowledgement information (e.g., the Grant Vector), the entry selection logic 436 uses the acknowledgement information to modify the Local Target Vector in the selected entry 408 to indicate that the packet in the selected entry 408 has been transferred to the destination 104 indicated by the transfer acknowledgement information. As an example, for each bit in the Grant Vector that is set to one, the entry selection logic 436 sets the corresponding bit in the Local Target Vector to zero. If all bits in the Local Target Vector are zero, this indicates that the data packet in the selected entry 408 has been transferred to all intended destinations 104, and the entry selection logic 436 sets the Entry Valid bit in the selected entry 408 to zero. On the other hand, if at least one bit in the Local Target Vector is not zero, this indicates that there is at least one destination 104 to which the data packet in the selected entry 408 still needs to be transferred, and the entry selection logic 436 leaves the Entry Valid bit in the selected entry 408 set to one.

[0085] Figure 6 is a flowchart of an example method 600 for transferring a data packet from a queue according to an embodiment. The method 600 is implemented by the entry selection logic 436 of the queue manager 400 Figure 4 for purposes of explanation, with reference to the queue manager 400 Figure 4The method 600 is described with respect to the queue system 400. However, in other embodiments, the method 600 is implemented in another suitable queuing system, and / or the entry selection logic 436 implements another suitable method for transferring data packets from a queue.

[0086] At block 604, the queuing system determines (e.g., the entry selection logic 436 determines) whether at least one intended target of the data packet in the head entry of the queue is available to receive the data packet. For example, the entry selection logic 436 performs a bitwise logical AND operation on the Local_Target_Vector in the head entry 408 and the Credit_Available_Vector in the memory 444 to generate a Transfer_Vector for the head entry 408, and determines whether at least one bit in the Transfer_Vector is set to 1. If at least one bit in the Transfer_Vector for the head entry is set to 1, this indicates that at least one intended target 104 of the data packet in the head entry 408 is available to receive the packet. On the other hand, if none of the bits in the Transfer_Vector for the head entry are set to 1, this indicates that the intended target 104 of the data packet in the head entry 408 is not available to receive the packet.

[0087] If the queuing system determines (e.g., the entry selection logic 436 determines) at block 604 that at least one intended target of the data packet in the head entry is available to receive the data packet, then flow proceeds to block 608. At block 608, the queuing system selects (e.g., the entry selection logic 436 selects) the head entry in the queue.

[0088] On the other hand, if the queuing system determines (e.g., the entry selection logic 436 determines) at block 604 that the intended target of the data packet in the head entry is not available to receive the data packet, then flow proceeds to block 612.

[0089] At block 612, the queuing system selects (e.g., the entry selection logic 436 selects) the next entry in the queue (according to the order in which packets are received and stored in the queue (i.e., the receive order), which corresponds to the order of entries in the queue (i.e., the entry order)) for which i) the data packet in the entry still needs to be transferred to at least one intended target, and ii) at least one intended target for the data packet in the entry is available to receive the data packet. For example, the entry selection logic 436 selects the next entry 408 (according to the receive order) for which the Entry_Valid bit is set to 1, and performs a bitwise logical AND operation on the Local_Target_Vector in the selected entry 408 and the Credit_Available_Vector in the memory 444 to generate the Transfer_Vector for the selected entry 408, and determines whether at least one bit in the Transfer_Vector is set to 1. If at least one bit in the Transfer_Vector for the selected entry 408 is set to 1, then the entry selection logic 436 selects the entry 408. On the other hand, if none of the bits in the Transfer_Vector for the selected entry 408 is set to 1, then this indicates that the intended target 104 for the data packet in the selected entry 408 is not available to receive the packet, and the entry selection logic 436 selects the next entry 408 (according to the receive order) for which the Entry_Valid bit is set to 1. Similarly, the entry selection logic 436 performs a bitwise logical AND operation on the Local_Target_Vector in the next selected entry 408 and the Credit_Available_Vector in the memory 444 to generate the Transfer_Vector for the next selected entry 408, and determines whether at least one bit in the Transfer_Vector is set to 1. If at least one bit in the Transfer_Vector for the next selected entry 408 is set to 1, then the entry selection logic 436 selects the entry 408. On the other hand, if none of the bits in the Transfer_Vector for the selected entry 408 is set to 1, then this indicates that the intended target 104 for the data packet in the selected entry 408 is not available to receive the packet, and the entry selection logic 436 selects the next entry 408 (according to the receive order) for which the Entry_Valid bit is set to 1, and so on.

[0090] At block 616, the entry selection logic 436 generates control signals to control the multiplexer 432 to select to output the entry selected at block 608 or block 612 to the crossbar. In addition, according to some embodiments, the entry selection logic 436 outputs the Transfer Vector of the selected entry to the crossbar, the Transfer Vector controls the crossbar to direct the data packets in the selected entry to the destination 104 indicated by the Transfer Vector, e.g., the destination 104 both i) intended to receive the data packets and ii) available to receive the data packets.

[0091] At block 620, the entry selection logic 436 updates the credit information in the memory 444 for the destination to which the packets in the selected entry 408 are transferred. For example, upon receiving the transfer acknowledgement information (e.g., Grant Vector), the entry selection logic 436 uses the acknowledgement information to update the credit information in the memory 444 for the destination to which the data packets are transferred. As an illustrative example, if the credit in the memory for a particular destination 104 is set to 3, and a bit in the Grant Vector corresponding to the particular destination 104 is set to 1, the entry selection logic 436 decrements the credit in the memory for the particular destination 104 to 2.

[0092] At block 624, the entry selection logic 436 updates the indication of the intended destination(s) to which the data packets in the entry selected at block 608 or block 612 need to be transferred. For example, if the data packets are transferred (in connection with block 616) to a particular destination 104, the indication of the intended destination of the selected entry is updated to indicate that the data packets need not be transferred to the particular destination 104. For example, upon receiving the transfer acknowledgement information (e.g., Grant Vector), the entry selection logic 436 uses the acknowledgement information to modify the Local Target Vector in the selected entry 408 to indicate that the packets in the selected entry 408 have been transferred to the destination 104 indicated by the transfer acknowledgement information. As an example, for each bit in the Grant Vector that is set to 1, the entry selection logic 436 sets the corresponding bit in the Local Target Vector to 0.

[0093] At block 628, the entry selection logic 436 determines when the data packet in the entry selected at block 608 or block 612 still needs to be transmitted to at least one intended target. For example, the entry selection logic 436 processes the Local_Target_Vector of the selected entry 408 to determine whether any bits in the Local_Target_Vector are set to one. If all bits in the Local_Target_Vector are set to zero, this indicates that the data packet in the selected entry 408 has already been transmitted to all intended targets 104. On the other hand, if at least one bit in the Local_Target_Vector is not zero, this indicates that there is at least one target 104 to which the data packet in the selected entry 408 still needs to be transmitted.

[0094] If at block 628 the entry selection logic 436 determines that the data packet in the entry selected at block 608 or block 612 does not need to be transmitted to any more intended targets, flow proceeds to block 632. At block 632, the entry selection logic 436 sets the Entry_Valid bit in the selected entry 408 to zero to indicate that the data packet in the selected entry 408 does not need to be transmitted to any more intended targets.

[0095] According to an embodiment, referring again to Figure 4 In conjunction with the data packet in the head entry that has already been transmitted to all intended targets, the pointer control logic 412 uses the Entry_Valid bits in the queue 404 to determine the next entry 408 (according to the order of the entries 408, i.e., entry order) that has not yet been transmitted to all intended targets, and updates the head pointer to point to the determined next entry 408. As an illustrative example, in response to the pointer control logic 412 determining that the Entry_Valid bit of the entry 408 currently pointed to by the head pointer has been changed to zero, the pointer control logic 412 changes the head pointer to point to the next entry (according to the order of the entries 408, i.e., entry order) whose Entry_Valid bit is set to one, according to an embodiment.

[0096] Although the setting of bits to particular values (e.g., zero or one) is described above, in other embodiments, similar operations are performed by setting the bits to different values, and the associated logic is modified accordingly.

[0097] Referring now to Figures 1-6Although a queuing system for storing and transmitting data packets has been described above, according to some embodiments, in addition to storing and transmitting data packets, or as an alternative to storing and transmitting data packets, similar queuing systems store and transmit other suitable types of packets, such as instruction packets. In one embodiment, an instruction packet includes information corresponding to machine-readable instructions, which, when executed by a processor, cause the processor to perform various actions corresponding to the machine-readable instructions.

[0098] Figure 7 This is a flowchart of an example method 700 for transmitting packets to a set of multiple target devices according to an embodiment. According to various embodiments, method 700 is comprised of… Figure 1 Router 100 Figure 2 FIFO queue 200 and / or Figure 4 The FIFO queue 400 is implemented, and for illustrative purposes, refer to [reference needed]. Figure 1 , Figure 2 and Figure 4 Method 500 is described. However, in other embodiments, method 700 is implemented in another suitable queuing system, and / or Figure 1 Router 100 Figure 2 FIFO queue 200 and / or Figure 4 The FIFO queue 400 implements another suitable method for transmitting packets to a set of multiple target devices. In some embodiments, method 700 optionally includes performing method 500 ( Figure 5 ) and / or method 600 ( Figure 6 One or both of them.

[0099] At box 704, the queuing system receives multiple packets. In one embodiment, for example, router 100 receives multiple packets. As another example, FIFO queue 200 receives multiple packets in another embodiment. As yet another example, FIFO queue 400 receives multiple packets in yet another embodiment. In some embodiments, the multiple packets are received from a single source device. In other embodiments, multiple packets are received from multiple source devices.

[0100] At box 708, the queuing system stores the packets received at box 704 in corresponding entries of the queue according to the order in which they were received (i.e., the "receive order"). The head entry of the queue corresponds to the earliest packet in the receive order.

[0101] For example, in one embodiment, multiple packets are stored in FIFO queue 108. As another example, in another embodiment, multiple packets are stored in queue 204. As yet another example, in yet another embodiment, multiple packets are stored in queue 404.

[0102] At block 712, the queuing system receives flow control information corresponding to the set of multiple target devices, the flow control information indicating whether one or more target devices of the set of multiple target devices are available to receive packets from the queuing system. In some embodiments, the flow control information received at block 712 includes credit information corresponding to one or more target devices. In some embodiments, the flow control information received at block 712 includes credit update information corresponding to one or more target devices. In some embodiments, the flow control information received at block 712 includes one or more respective stall signals corresponding to one or more target devices.

[0103] In one embodiment, for example, the FIFO queue 108 receives the flow control information. As another example, in another embodiment, the entry selection logic 236 receives the flow control information. As yet another example, in yet another embodiment, the entry selection logic 436 receives the flow control information.

[0104] At block 716, the queuing system uses the flow control information received at block 712 to determine whether any target device for which the earliest packet is stored in the head entry is available to receive the earliest packet. In one embodiment, for example, the FIFO queue 108 uses the flow control information to determine whether any target device for which the earliest packet is stored in the head entry is available to receive the earliest packet. As another example, in another embodiment, the entry selection logic 236 uses the flow control information to determine whether any target device for which the earliest packet is stored in the head entry is available to receive the earliest packet. As yet another example, in another embodiment, the entry selection logic 436 uses the flow control information to determine whether any target device for which the earliest packet is stored in the head entry is available to receive the earliest packet.

[0105] If at block 716 it is determined that at least one target device is available to receive the earliest packet stored in the head entry, flow proceeds to block 720. At block 720, the earliest packet stored in the head entry is transmitted to at least one intended target of the data packet that is available to receive the data packet. In accordance with one embodiment, for example, transmitting the earliest packet at block 720 includes the FIFO queue 108 transmitting the earliest packet to one or more targets via the data distribution logic 112.

[0106] As another example, according to another embodiment, transmitting the oldest packet at block 720 includes the entry selection logic 236 controlling the multiplexer 232 to select the head entry for output and / or the FIFO queue 200 transmitting the oldest packet to one or more targets via the data distribution logic 112. As yet another example, according to yet another embodiment, transmitting the oldest packet at block 720 includes the entry selection logic 436 controlling the multiplexer 432 to select the head entry for output and / or the FIFO queue 400 transmitting the oldest packet to one or more targets via the data distribution logic 112.

[0107] On the other hand, if it is determined at block 716 that no target device of the oldest packet stored in the head entry is available to receive the oldest packet, then flow proceeds to block 724. At block 724, the queuing system selects another entry behind the head entry according to the order of receipt, the other entry storing another packet that can be transmitted to a target available to receive the other packet. In one embodiment, selecting another entry behind the head entry at block 724 includes selecting another entry that includes a data packet that i) still needs to be transmitted to at least one intended target, and ii) at least one intended target of the data packet is available to receive the data packet.

[0108] As an example, according to one embodiment, selecting another entry behind the head entry at block 724 includes the FIFO queue 108 selecting another entry behind the head entry. As another example, according to another embodiment, selecting another entry behind the head entry at block 724 includes the entry selection logic 236 controlling the multiplexer 232 to select another entry behind the head entry. As yet another example, according to yet another embodiment, selecting another entry behind the head entry at block 724 includes the entry selection logic 436 controlling the multiplexer 432 to select another entry behind the head entry.

[0109] At block 728, the queuing system transmits the other packet in the entry selected at block 724 to at least one intended target of the data packet that is available to receive the data packet. According to one embodiment, for example, transmitting the packet at block 728 includes the FIFO queue 108 transmitting the packet to one or more targets via the data distribution logic 112. As another example, according to another embodiment, transmitting the packet at block 728 includes the FIFO queue 200 transmitting the packet to one or more targets via the data distribution logic 112. As another example, according to another embodiment, transmitting the packet at block 728 includes the FIFO queue 400 transmitting the packet to one or more targets via the data distribution logic 112.

[0110] Figure 8 is a diagram of an exemplary mesh architecture 800 according to one embodiment, in which the above-referenced Figures 1-7The queuing system and method described herein. The exemplary grid architecture 800 is merely one example of a processing system utilizing the queuing system and method described herein. The above references are made according to various other embodiments. Figures 1-7 The queuing system and method described can be used in a variety of different systems that require sending packets to multiple target devices.

[0111] The mesh architecture 800 includes a plurality of target devices 804 communicatively coupled together via a plurality of routers 808. According to one embodiment, each of the one or more target devices 804 includes a processing node. Additionally or alternatively, according to another embodiment, each of the one or more target devices 804 includes a memory device such as a DMA device.

[0112] In some embodiments where one or more target devices 804 include processing nodes, each processing node includes at least on-chip memory (OCM) and one or more processing units of the same type (in one embodiment) or different type (in another embodiment). In embodiments where one or more target devices 804 include OCM and one or more processing units, each OCM includes one or more storage banks, and each OCM is configured to receive and maintain data in a streaming manner for access by the processing units for various operations performed by the processing units. In such embodiments, the OCM enables the processing units to have efficient local access to data.

[0113] Although target device 804 is referred to as "target", each of at least some of the devices in target device 804 can also serve as a source for groups of other target devices 804.

[0114] Each router 808 is associated with one or more target devices 804. Although Figure 8 The illustration shows each router 808 associated with four target devices 804, but in various other embodiments, each router 808 is associated with another suitable number of target devices 804, such as one, two, three, five, six, etc. Although Figure 8 Each router 808 is shown to be associated with the same number of target devices 804 (e.g., four), but in various other embodiments, at least some of the routers 808 are associated with a different number of target devices 804.

[0115] In some embodiments, each router 808 has a connection to... Figure 1 The router 100 has the same or similar structure, or another suitable structure. In various embodiments, each router 808 includes, for example, Figure 2 queuing system 200 or Figure 4The queuing system 400 is a queuing system. In other embodiments, each router 808 includes another suitable queuing system.

[0116] although Figure 8 Four routers 808 are shown, but the mesh architecture 800 includes other suitable numbers of routers 808 in various other embodiments.

[0117] Each router 808 is coupled to its associated target 804, and also to one or more other routers 808. For example, router 808-1 is coupled to targets 804-1, 804-2, 804-3, and 804-4, as well as routers 808-2 and 808-3. In some embodiments, router 808-1 is also coupled to router 808-4.

[0118] Figure 9 This is a diagram of an exemplary processing subsystem 900 including an example router 904 according to an embodiment. The processing subsystem 900 is included according to an embodiment. Figure 8 In the example mesh architecture 800, and for illustrative purposes refer to Figure 8 describe Figure 9 In other embodiments, the processing subsystem 900 is used for another suitable processing system, such as another machine learning system, a parallel processing system, an image processing system, etc.

[0119] According to one embodiment, router 904 is a reference Figure 8 Examples of at least some of the described routers 808. Router 904 is coupled to a plurality of source / destination devices 908. According to one embodiment, the source / destination devices 908 correspond to reference... Figure 8 At least some of the target devices 804 described.

[0120] Router 904 is also coupled to one or more other routers. Figure 9 (Not shown in the image) and / or one or more other source / target devices 916. According to some embodiments, one or more (or none) of the other routers 916 have the same or similar structure as router 904. According to various embodiments, one or more other routers or source / target devices 916 correspond to reference... Figure 8 The router 808 described, and / or corresponding to the reference Figure 8 At least some of the target devices 804 associated with the other routers 808 described.

[0121] Router 904 includes a plurality of FIFO queues 912, each FIFO queue 912 having head-of-line blocking avoidance logic (each FIFO queue 912 having head-of-line blocking avoidance logic is referred to as a "FIFO queue 912" for brevity). In various embodiments, each FIFO queue 912 corresponds to FIFO queue 108 Figure 1 ), FIFO queue 200 Figure 2 ), and / or FIFO queue 400 Figure 4 ). In various embodiments, at least one FIFO queue 912 is configured to implement at least one of the methods described with reference to Figures 5-7

[0122] FIFO queues 912-1, 912-3, 912-5, and 912-7 are coupled to source / destination devices 908-1, 908-2, 908-3, and 908-4, respectively. FIFO queues 912-2, 912-4, 912-6, and 912-8 are coupled to respective other routers or source / destination devices 916. Source / destination device 908-1 acts as a source for FIFO queue 912-1, source / destination device 908-2 acts as a source for FIFO queue 912-3, source / destination device 908-3 acts as a source for FIFO queue 912-5, and source / destination device 908-1 acts as a source for FIFO queue 912-7. Another router (or source / destination device) 916-1 acts as a source for FIFO queue 912-2, another router (or source / destination device) 916-2 acts as a source for FIFO queue 912-4, another router (or source / destination device) 916-3 acts as a source for FIFO queue 912-6, and another router (or source / destination device) 916-4 acts as a source for FIFO queue 912-8.

[0123] Source / destination devices 908-2, 908-3, 908-4, and other routers (or source / destination devices) 916 act as targets for FIFO queue 912-1. Source / destination devices 908-1, 908-3, 908-4, and other routers (or source / destination devices) 916 act as targets for FIFO queue 912-3. Source / destination devices 908-1, 908-2, 908-4, and other routers (or source / destination devices) 916 act as targets for FIFO queue 912-5. Source / destination devices 908-1, 908-2, 908-3, and other routers (or source / destination devices) 916 act as targets for FIFO queue 912-7.

[0124] ​The source / target device 908 and the other routers (or source / target devices) 916-2, 916-3, and 916-4 act as targets for the FIFO queue 912-2. The source / target device 908 and the other routers (or source / target devices) 916-1, 916-3, and 916-4 act as targets for the FIFO queue 912-4. The source / target device 908 and the other routers (or source / target devices) 916-1, 916-2, and 916-4 act as targets for the FIFO queue 912-6. The source / target device 908 and the other routers (or source / target devices) 916-1, 916-2, and 916-3 act as targets for the FIFO queue 912-8.

[0125] Embodiment 1 : An apparatus comprising: a queue comprising a plurality of entries, the plurality of entries comprising a head entry; and control logic circuitry configured to: store, in the queue, packets received by the apparatus in an order in which the packets are received until the packets can be transmitted to a plurality of target devices, wherein the head entry corresponds to an earliest packet in the order, receive flow control information corresponding to the plurality of target devices, the plurality of target devices comprising at least a first target device and a second target device, determine, using the flow control information, whether the earliest packet stored in the head entry can be transmitted to the first target device, and in response to determining that the earliest packet stored in the head entry cannot be transmitted to the first target device, i) select, in accordance with the order, another entry following the head entry, the other entry storing another packet that can be transmitted to the second target device, and ii) transmit the other packet to the second target device before transmitting the earliest packet in the head entry to the first target device.

[0126] Embodiment 2: The apparatus of any of Embodiment 1, wherein: the control logic circuitry comprises a multiplexer having i) a plurality of inputs coupled to the plurality of entries of the queue, respectively; and the control logic circuitry is configured to control the multiplexer to select an input of the multiplexer coupled to the other entry following the head entry to output from the multiplexer.

[0127] Embodiment 3: The apparatus of any of Embodiments 1 and 2, wherein the control logic circuitry is configured to: determine, among a set of the plurality of target devices, one or more target devices to which the earliest packet stored in the head entry is destined, the one or more target devices comprising the first target device; determine, using the flow control information, whether at least one of the one or more target devices is available to receive the earliest packet; and in response to determining that none of the one or more target devices is available to receive the earliest packet, i) select the other entry following the head entry, and ii) transmit the other packet to the second target device before transmitting the earliest packet in the head entry to any of the one or more target devices.

[0128] Embodiment 4: The apparatus of embodiment 3, wherein the control logic circuitry is configured to: responsive to determining that at least the first target device is available to receive the earliest packet, i) select the head entry, and ii) transmit the earliest packet to at least the first target device before transmitting another packet to the second target device.

[0129] Embodiment 5: The apparatus of embodiment 4, wherein the control logic circuitry is configured to: in conjunction with transmitting the earliest packet to at least the first target device, determine whether the earliest packet is still to be transmitted to one or more additional target devices; responsive to determining that the earliest packet is still to be transmitted to one or more additional target devices, maintain the head pointer pointing to the head entry corresponding to the earliest packet; and responsive to determining that the earliest packet need not be transmitted to any additional target devices, update the head pointer to point to a different entry corresponding to a different packet subsequent to the earliest packet according to the order.

[0130] Embodiment 6: The apparatus of any of embodiments 1-5, wherein the control logic circuitry is configured to: responsive to determining that the earliest packet stored in the head entry is available to be transmitted to the first target device, transmit the earliest packet to the first target before transmitting another packet in another entry to the second target.

[0131] Embodiment 7: The apparatus of embodiment 6, wherein the control logic circuitry is configured to: in conjunction with transmitting the earliest packet to the first target device, update the head pointer to point to a different entry corresponding to a different packet subsequent to the earliest packet according to the order.

[0132] Embodiment 8: The apparatus of embodiment 7, wherein the control logic circuitry is configured, as part of updating the head pointer: to determine a next entry according to the order, the next entry comprising a packet that still needs to be transmitted to at least one target device; and to update the head pointer to point to the determined next entry.

[0133] Embodiment 9: The apparatus of embodiment 8, wherein the control logic circuitry is configured, as part of determining the next entry according to the order, the next entry comprising a packet that still needs to be transmitted to at least one target device: to skip one or more entries according to the order, the one or more entries comprising packets that need not be transmitted to any target device.

[0134] Embodiment 10: The apparatus of any of embodiments 1-9, further comprising: a crossbar communicatively coupled to the queue; wherein the control circuitry is configured to: provide the another packet to the crossbar, and provide destination information to the crossbar, the destination information controlling the crossbar to transmit the another packet to the second target device.

[0135] Embodiment 11: A method for transmitting packets to a set of multiple target devices, the method comprising: receiving a plurality of packets; storing the plurality of packets in respective entries of a queue in an order in which the plurality of packets are received, wherein a head entry of the queue corresponds to an earliest packet in the order; receiving flow control information corresponding to the set of multiple target devices, the flow control information indicating whether one or more target devices of the set of multiple target devices are available to receive a packet; determining, using the flow control information, whether any target device to which the earliest packet is destined is available to receive the earliest packet; and in response to determining that no target device to which the earliest packet is destined is available to receive the earliest packet, selecting another entry following the head entry in the order, the other entry storing another packet destined to at least one target device that is available to receive the other packet, and transmitting the other packet in the other entry following the head entry in the order to the at least one target device to which the other packet is destined before transmitting the earliest packet in the head entry to the target device to which the earliest packet is destined.

[0136] Embodiment 12: The method of any of Embodiments 11, wherein transmitting the other packet in the other entry following the head entry in the order comprises: transmitting the other packet in the other entry while maintaining a head pointer of the queue pointing to the head entry.

[0137] Embodiment 13: The method of any of Embodiments 11 and 12, further comprising: in response to determining that the at least one target device to which the earliest packet is directed is available to receive the earliest packet, transmitting the earliest packet to the at least one target device to which the earliest packet is destined before transmitting the other packet in the other entry to the target device to which the other packet is destined.

[0138] Embodiment 14: The method of Embodiment 13, further comprising: in conjunction with transmitting the earliest packet to the at least one target device to which the earliest packet is destined, determining whether the earliest packet is still to be transmitted to one or more additional target devices; in response to determining that the earliest packet is still to be transmitted to the one or more additional target devices, maintaining the head pointer pointing to the head entry corresponding to the earliest packet; and in response to determining that the earliest packet does not need to be transmitted to any additional target devices, updating the head pointer to point to a different entry corresponding to a different packet following the earliest packet in the order.

[0139] Embodiment 15: The method of embodiment 14, wherein updating the head pointer comprises: determining, along with transmitting the oldest packet to the at least one destination device to which the oldest packet is destined, whether the oldest packet is still to be transmitted to one or more additional destination devices; responsive to determining that the oldest packet is still to be transmitted to one or more additional destination devices, maintaining the head pointer pointing to the head entry corresponding to the oldest packet; and responsive to determining that the oldest packet does not need to be transmitted to any additional destination devices, updating the head pointer to point to a different entry corresponding to a different packet that is after the oldest packet according to the order.

[0140] Embodiment 16: The method of embodiment 15, wherein updating the head pointer comprises: determining a next entry according to the order, the next entry comprising a packet that still needs to be transmitted to at least one destination device; and updating the head pointer to point to the determined next entry.

[0141] Embodiment 17: The method of embodiment 16, wherein updating the head pointer comprises: skipping, according to the order, one or more entries comprising packets that do not need to be transmitted to any destination device.

[0142] Embodiment 18: The method of any one of embodiments 11-17, wherein: receiving flow control information corresponding to the set of destination devices comprises receiving flow control credit update information corresponding to the set of destination devices; the method further comprises maintaining flow control credits for the set of destination devices; and determining whether any destination device to which the oldest packet is destined is available to receive the oldest packet comprises: for each destination device to which the oldest packet is destined, determining whether there is a non-zero amount of credit for the destination device, and responsive to determining that all destination devices to which the oldest packet is destined have zero credit, determining that no destination device to which the oldest packet is destined is available to receive the oldest packet.

[0143] Embodiment 19: The method of any one of embodiments 11-18, further comprising: generating control information indicating one or more destination devices that i) are both intended to receive another packet and ii) are available to receive the other packet; wherein transmitting the other packet comprises transmitting the other packet to the one or more destination devices that i) are both intended to receive the other packet and ii) are available to receive the other packet using the control information.

[0144] Embodiment 20: The method of embodiment 19, wherein transmitting the other packet comprises: providing the other packet to a crossbar coupled to the set of destination devices; and providing the control information to the crossbar to control the crossbar to transmit the other packet to the one or more destination devices that i) are both intended to receive the other packet and ii) are available to receive the other packet.

[0145] At least some of the various blocks, operations, and techniques described above can be implemented utilizing hardware, a processor executing firmware instructions, a processor executing software instructions, or any combination thereof. When implemented utilizing a processor executing software or firmware instructions, the software or firmware instructions can be stored in any computer-readable memory such as on a RAM, ROM, flash memory, integrated circuits, or the like. The software or firmware instructions can include machine readable instructions that, when executed by the processor, cause the processor to perform various acts.

[0146] When implemented in hardware, the hardware can comprise one or more of discrete components, one or more ICs, application- specific integrated circuits (ASICs), programmable logic devices (PLDs), and the like.

[0147] While the present application has been described with reference to specific examples, which are intended to be illustrative only and not limiting of the application, changes, additions and / or deletions can be made to the disclosed embodiments without departing from the scope of the application.

Claims

1. An electronic device comprising: A queue comprising multiple entries, wherein the multiple entries include a head entry; as well as The control logic circuit device is configured as follows: Packets received by the device are stored in the queue in the order they were received, until the packets can be transmitted to multiple target devices, wherein the header entry corresponds to the earliest packet in the order, and wherein the multiple target devices include a first target device, a second target device, and a third target device. The earliest group is determined to go to several target devices among the plurality of target devices, including the first target device and the second target device. Receive flow control information corresponding to the plurality of target devices. The flow control information is used to determine whether the earliest packet stored in the header entry can be transmitted to any of the plurality of target devices, and In response to determining that the earliest packet stored in the header entry can be transmitted to the first target device but not to the second target device, the earliest packet is transmitted to the first target device, and the earliest packet is maintained as the header entry. In response to determining that the earliest packet stored in the header entry cannot be transmitted to any of the plurality of target devices, i) another entry following the header entry is selected according to the order, the other entry storing another packet that can be transmitted to the third target device, and ii) the other packet is transmitted to the third target device before transmitting the earliest packet in the header entry to any of the plurality of target devices.

2. The apparatus according to claim 1, wherein the control logic is configured to: Maintain a corresponding target vector for each packet in the queue, each target vector indicating one or more expected target devices for the packet; The target vector corresponding to the earliest group is used to determine the destination of the earliest group to the plurality of target devices; and Along with transmitting the earliest packet to the first target device, the target vector corresponding to the earliest packet is modified to indicate that the earliest packet should no longer go to the first target device.

3. The apparatus according to claim 1, wherein: The control logic circuitry device includes a multiplexer having multiple inputs coupled to the plurality of entries of the queue; as well as The control logic circuitry is configured to control the multiplexer to select an input to the multiplexer, the input of which is coupled to another entry following the header entry for output from the multiplexer.

4. The apparatus of claim 1, wherein the control logic circuitry is configured as follows: Determine the target devices to which the earliest packet stored in the header entry is to be sent; The flow control information is used to determine whether at least one of the target devices is capable of receiving the earliest packet; and In response to determining that none of the target devices is capable of receiving the earliest packet, i) select the other entry following the header entry, and ii) transmit the other packet to the second target device before transmitting the earliest packet in the header entry to any one of the one or more target devices.

5. The apparatus of claim 4, wherein the control logic circuitry is configured to: In response to determining that at least the first target device is capable of receiving the earliest packet, i) select the header entry, and ii) transmit the earliest packet to at least the first target device before transmitting the other packet to the second target device.

6. The apparatus of claim 5, wherein the control logic circuitry is configured to: Along with transmitting the earliest packet to at least the first target device, determine whether the earliest packet still needs to be transmitted to one or more additional target devices; In response to determining that the earliest packet still needs to be transmitted to one or more additional target devices, after transmitting the earliest packet to at least the first target device, the header pointer pointing to the header entry corresponding to the earliest packet is maintained; as well as In response to determining that the earliest packet does not need to be transmitted to any additional target device, the header pointer is updated to point to different entries corresponding to different packets following the earliest packet in the order.

7. The apparatus of claim 6, wherein the control logic circuitry is configured to: In response to determining that the earliest packet stored in the header entry can be transmitted to the first target device, the earliest packet is transmitted to the first target device before transmitting the other packet in the other entry to the third target device.

8. The apparatus of claim 7, wherein the control logic circuitry is configured to: Along with transmitting the earliest packet to all of the plurality of target devices, the head pointer is updated to point to different entries corresponding to different packets following the earliest packet in the order stated.

9. The apparatus of claim 8, wherein the control logic circuitry is configured as part of updating the head pointer: The next entry is determined according to the order, the next entry including packets that still need to be transmitted to at least one target device; and Update the head pointer to point to the determined next entry.

10. The apparatus of claim 9, wherein the control logic circuitry is configured as part of determining, in accordance with the order, the next entry comprising the packet that still needs to be transmitted to at least one target device: Skip one or more entries in the order stated, including packets that do not need to be transmitted to any target device.

11. The apparatus according to any one of claims 1 to 10, further comprising: A crossbar switch is communicatively coupled to the queue; The control logic circuit device is configured as follows: Provide the other group to the cross switch, and Destination information is provided to the cross switch, which controls the cross switch to transmit the other packet to the second target device.

12. A method for transmitting packets to multiple target devices, the method comprising: Receive multiple packets; The multiple packets are stored in corresponding entries of a queue in the order in which they are received, wherein the head entry of the queue corresponds to the earliest packet in the order. Receive flow control information corresponding to the plurality of target devices, wherein the flow control information indicates whether one or more of the plurality of target devices can be used to receive packets, wherein the plurality of target devices includes a first target device, a second target device, and a third target device; The earliest group is to be directed to several target devices among the plurality of target devices, the plurality of target devices including the first target device and the second target device; The flow control information is used to determine whether any of the plurality of target devices is capable of receiving the earliest packet; as well as In response to determining i) that the first target device is capable of receiving the earliest packet and ii) that the second target device is not capable of receiving the earliest packet, the earliest packet is transmitted to the first target device and the earliest packet is maintained as the header entry; In response to determining that none of the target devices is capable of receiving the earliest packet, According to the order, another entry following the header entry is selected, the other entry storing the other packet destined for at least the third target device capable of receiving the other packet, and Before transmitting the earliest packet in the header entry to any of the plurality of target devices, the other packet in the other entry following the header entry is transmitted to at least the third target device in the order stated.

13. The method of claim 12, further comprising: Maintain a corresponding target vector for each packet in the queue, each target vector indicating one or more expected target devices for the packet; Determining that the earliest group should go to the plurality of target devices includes using a target vector corresponding to the earliest group; as well as The method further includes: along with transmitting the earliest packet to the first target device, modifying the target vector corresponding to the earliest packet to indicate that the earliest packet is no longer destined for the first target device.

14. The method of claim 12, wherein transmitting the other group in the other entry following the header entry in the said order comprises: Transmit the other packet from the other entry while keeping the head pointer of the queue pointing to the head entry.

15. The method according to claim 12, wherein: The earliest packet is transmitted to the first target device before the header entry for the other packet is included in the other entry for the target device to which the other packet is to be sent.

16. The method of claim 15, further comprising: Along with transmitting the earliest packet to the first target device, determine whether the earliest packet still needs to be transmitted to one or more additional target devices; In response to determining that the earliest packet still needs to be transmitted to one or more additional target devices, maintain the header pointer pointing to the header entry corresponding to the earliest packet; as well as In response to determining that the earliest packet does not need to be transmitted to any additional target device, the header pointer is updated to point to different entries corresponding to different packets following the earliest packet in the order.

17. The method of claim 16, wherein updating the head pointer comprises: The next entry is determined according to the order, and the next entry includes packets that still need to be transmitted to at least one target device; as well as Update the head pointer to point to the determined next entry.

18. The method of claim 17, wherein updating the head pointer comprises: Skip one or more entries, including packets that do not need to be transmitted to any target device, according to the stated order.

19. The method according to claim 12, wherein: Receiving flow control information corresponding to the plurality of target devices includes: receiving flow control credit update information corresponding to the plurality of target devices; The method also includes maintaining the flow control credit of the plurality of target devices; and Determining whether any of the plurality of target devices is capable of receiving the earliest packet includes: For each of the plurality of target devices, determine whether there exists a non-zero amount of credit for that target device, and In response to determining that all of the plurality of target devices have zero credit, it is determined that none of the plurality of target devices is capable of receiving the earliest packet.

20. The method according to any one of claims 12 to 19, further comprising: Generate control information instructing one or more target devices, which are both i) intended to receive the other packet and ii) capable of receiving the other packet; The transmission of the other packet includes: using the control information to transmit the other packet to the one or more target devices, the one or more target devices being both i) intended to receive the other packet and ii) capable of receiving the other packet.

21. The method of claim 20, wherein transmitting the other packet comprises: Provide the additional grouping to the cross switches coupled to the plurality of target devices; as well as The control information is provided to the cross switch to control the cross switch to transmit the other packet to the one or more target devices, the one or more target devices being both i) intended to receive the other packet and ii) capable of receiving the other packet.

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