In-memory computing method and device

Abstract

The present invention discloses an in-memory operation method and device, which is suitable for a processor to perform MAC operation on a memory. In the method, the format of the binary data is converted from a floating point format to a quantized format by truncating at least a portion of the fractional bits of the binary data of the weight and calculating the complement of the remaining bits, and the converted binary data is programmed into a unit of the memory. An adjustment procedure is performed by iteratively inputting the binary data of the input signal into the memory, integrating the output of the memory, and adjusting the weight programmed into the unit based on the integrated output. The binary data of the weight is reshaped based on reducing the probability of a bit with a value of one in the binary data of each weight. The adjustment procedure is repeated until an end condition is met.

Description

Technical Field

[0001] The present invention relates to a computing method and a computing device, and more particularly, to an in-memory computing method and a computing device. Background Art

[0002] Compared to traditional machine learning methods, recurrent neural networks (RNNs) have demonstrated their ability to achieve greater accuracy in several areas such as image recognition and speech enhancement. However, several challenges have arisen when implementing RNNs on current Von-Neumann architectures. For example, in fully connected neural networks, excessive data movement between processing units and off-chip memory units when implementing RNNs will lead to performance limitations and high power consumption.

[0003] To bridge the gap between computing units and memory units, the concept of in-memory computing has been widely proposed, and memristors with resistive random-access memory (ReRAM) are one of the most intensively researched solutions. ReRAM (one of the emerging non-volatile memories (NVM)) stores data by changing the resistance of the unit and has been proven to have both computing and storage capabilities. Specifically, memristors perform digital RNN operations on analog patterns, namely multiply-and-accumulate (MAC) operations, by setting different input voltages and resistance values ​​to represent input values ​​and weight values ​​respectively.

[0004] For example, Figure 1 An example of a calculation using a memristor to perform a MAC operation is shown. This example aims to calculate ∑(V n ×G n ) result. In this example, each word line is connected to each bit line through a ReRAM cell located at a cross point in 3D space. By Kirchhoffs current law (KCL), given the voltages V1 and V2 of the corresponding word lines, the currents I1, I2, I3, I4 induced by the conductances G1, G2, G3, G4 of each ReRAM cell are instantaneously added to the currents I5 and I6 of the corresponding bit lines. The result of the MAC operation is captured simultaneously by sensing the current of each bit line, where the value of I5 is equal to V1×G1+V2×G2 and the value of I6 is equal to V1×G3+V2×G4.

[0005] However, due to the overlapping distribution of the total current in the memristors, the accuracy of the RNN is significantly reduced.

[0006] For example, Figure 2 The distribution of the output current of all cells in the memristor is plotted. The possible distribution of the output current of all cells when a predefined voltage is applied to the input line is plotted with the x-axis indicating the current and the y-axis indicating the frequency. Figure 2 When more units are used for MAC operations, the distribution becomes wider. Figure 2 As shown in FIG. 1 , when 16 units are used for MAC operation, Figure 2 The distribution shown in , will present 17 possible combinations of input values, of which Figure 2 The distribution 22 on the left side may represent a zero value, and this distribution becomes wider as the total current becomes larger. Therefore, the probability of overlap variation error becomes higher. Summary of the invention

[0007] In view of the above, the present invention provides an in-memory computing method and an in-memory computing device capable of reducing overlap change errors and increasing calculation accuracy.

[0008] The present invention provides a method for in-memory operation, which is suitable for a processor to perform multiplication and addition (MAC) operation on a memory with a cross switch architecture. The memory includes a plurality of input lines and a plurality of output lines that cross each other, a plurality of cells are respectively arranged at the intersection of the input lines and the output lines, and a plurality of sense amplifiers are respectively connected to the output lines. In the method, the format of the binary data is converted from a floating point format to a quantized format by truncating at least a portion of the fractional bits of the binary data of a plurality of weights and calculating the complement of the remaining bits of the binary data, and the converted binary data of the plurality of weights are programmed into a plurality of cells. Then, an adjustment procedure is performed, which includes iteratively inputting the binary data of a plurality of input signals into a plurality of input lines, integrating the outputs sensed by the sense amplifiers, and adjusting the binary data of a plurality of weights programmed into the cells based on the integrated outputs, for a plurality of iterations. After the plurality of iterations, the binary data of the plurality of weights are reshaped based on reducing the probability of the bit having a value of one in the binary data of each weight, and the adjustment procedure is repeated until an end condition is met.

[0009] In one embodiment of the present invention, the step of calculating the complement of the remaining bits of the binary data includes calculating the 2's complement of the remaining bits and inverting the value of the calculated 2's complement.

[0010] In one embodiment of the present invention, the step of adjusting the binary data of multiple weights programmed into the cell based on the integrated output includes calculating the difference between the integrated output and a reference signal of the input signal, and adjusting the transformed binary data of multiple weights to be programmed into the cell according to the difference.

[0011] In one embodiment of the present invention, the step of reshaping the binary data of multiple weights based on reducing the probability of a bit with a value of one in the binary data of each weight includes calculating an accuracy based on a difference between the integrated output and a reference signal of the input signal, and reshaping in advance in response to the calculated accuracy being greater than a first threshold.

[0012] In one embodiment of the present invention, the step of reshaping the binary data of multiple weights based on reducing the probability of bits with a value of one in the binary data of each weight includes calculating the ratio of bits with a value of one to bits with a value of zero in the binary data of the multiple weights, and reshaping in advance in response to the calculated ratio being greater than a second threshold.

[0013] In one embodiment of the present invention, the step of reshaping the binary data of multiple weights based on reducing the probability of bits with a value of one in the binary data of each weight includes shifting the decimal value of each weight by an arbitrary number to maximize the quotient of the reduction of bits with a value of one in the binary data of the weight and the shifted number, and dividing the quotient by a factor determined based on the data distribution of the multiple weights to calculate a rate, and shifting the decimal value of each weight according to the calculated probability in response to the quotient being greater than or equal to a threshold.

[0014] The present invention provides an in-memory computing device, which includes a memory and a processor. The memory has a crossbar switch architecture, including a plurality of input lines and a plurality of output lines that cross each other, a plurality of units respectively configured at the intersection of the input lines and the output lines, and a plurality of sense amplifiers respectively connected to the output lines. The processor is coupled to the memory and configured to convert the format of the binary data from the floating point format to the quantized format by truncating at least a portion of the fractional bits of the binary data of the plurality of weights and calculating the complement of the remaining bits of the binary data, and programming the converted binary data of the plurality of weights into the plurality of units, and performing an adjustment procedure, including iteratively inputting the binary data of the plurality of input signals into the plurality of input lines, integrating the outputs sensed by the sense amplifiers, and adjusting the binary data of the plurality of weights programmed into the units based on the integrated outputs, continuing for a plurality of iterations, and after the plurality of iterations, reshaping the binary data of the plurality of weights based on reducing the probability of the bit with a value of one in the binary data of each weight, and repeating the adjustment procedure until an end condition is met.

[0015] In one embodiment of the present invention, the processor calculates the 2's complement of the remaining bits and inverts the value of the calculated 2's complement.

[0016] In one embodiment of the present invention, the processor calculates the difference between the integrated output and a reference signal of the input signal, and adjusts the transformed binary data of the plurality of weights to be programmed into the cell according to the difference.

[0017] In one embodiment of the present invention, the processor calculates accuracy according to a difference between the integrated output and a reference signal of the input signal, and performs early reshaping in response to the calculated accuracy being greater than a first threshold.

[0018] In one embodiment of the present invention, the processor calculates a ratio of bits having a value of one to bits having a value of zero in binary data of the plurality of weights, and performs early reshaping in response to the calculated ratio being greater than a second threshold.

[0019] In one embodiment of the present invention, the processor shifts the decimal value of each weight by an arbitrary number to maximize the quotient of the reduction of bits with a value of one in the binary data of the weight and the shifted number, and divides the quotient by a factor determined based on the data distribution of multiple weights, and shifts the decimal value of each weight according to the calculated probability in response to the quotient being greater than or equal to a threshold to calculate the calculator rate.

[0020] In one embodiment of the present invention, the adjustment procedure includes training of a neural network, wherein binary data of multiple input signals are set as inputs of the neural network, multiple weights are set as weights in multiple computing layers in the neural network, and the integrated output is set as the output of the neural network.

[0021] In one embodiment of the present invention, the binary data of each weight in a floating point format includes one sign bit, eight exponent bits, and twenty-three fraction bits in 32-bit binary data.

[0022] In order to make the aforementioned features and advantages of the present invention more comprehensible, embodiments of the present invention will be described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 An example of calculation by using a memristor to perform a MAC operation is shown.

[0024] Figure 2 The distribution of output current of all cells in the memristor is shown.

[0025] Figure 3 Schematic diagram of a computing device in a memory according to an embodiment of the present invention.

[0026] Figure 4 Flow chart of a method for operating in a memory according to an embodiment of the present invention.

[0027] Figure 5 is a floating point format for binary data according to an embodiment of the present invention.

[0028] Fig. 6A and Figure 6BSchematic diagrams respectively illustrate the ratio of bit “0” to bit “1” in quantized 9-bit binary data and inverted quantized 9-bit binary data according to an embodiment of the present invention.

[0029] Figure 7 A schematic diagram illustrating the training of a neural network according to an embodiment of the present invention.

[0030] Figure 8 A schematic diagram illustrating data reshaping according to an embodiment of the present invention.

[0031] Fig. 9 Flow chart of a method for operating in a memory according to an embodiment of the present invention.

[0032]

Explanation of symbols

[0033] 20: Figure

[0034] 22: Distribution

[0035] 30: Computing Devices

[0036] 32: Memory

[0037] 34: Processor

[0038] 50: floating point format

[0039] 52: Sign bit

[0040] 54: Exponent bit

[0041] 56: Fractional digit

[0042] 70: Neural Networks

[0043] 72: Voice signal

[0044] 74: Enhance speech signal

[0045] 76: Clean speech signal

[0046] G1, G2, G3, G4: Conductivity

[0047] I1, I2, I3, I4, I5, I6, I j : Current

[0048] IL i : Input line

[0049] OL j : Output line

[0050] R ij :resistance

[0051] S402, S404, S406, S902, S904, S906, S908, S910, S912, S914, S916: Steps

[0052] SA: Sense Amplifier

[0053] V1, V2: voltage

[0054] X: Threshold DETAILED DESCRIPTION

[0055] Due to the variation in resistance programming, the memristor suffers from overlap variation errors when it converts the output current into digital output in each MAC operation. Figure 2 As shown in , when the output current becomes larger, the distribution of the output current becomes wider, and thus the probability of overlapping variation errors becomes higher. Therefore, it is better to reduce the output current in order to make the distributions more distinguishable from each other. One way to reduce the output current is to increase the number of bits "0" (or reduce the number of bits "1") to be programmed into the cell of the memristor.

[0056] Based on the above content, in an embodiment of the present invention, an adaptive computing method is proposed to transform the format of the binary data of the weights to be programmed into the memristor from a floating-point format to a quantized format, and further reshape the binary data of the weights after executing multiple iterative weight adjustment procedures to reduce the number of bits "1" in the binary data of each weight and significantly reduce overlapping change errors.

[0057] Figure 3 Schematic diagram of a computing device in a memory according to an embodiment of the present invention. Figure 3 The computing device 30 of the embodiment is, for example, a memristor, which is configured to implement process-in-memory (PIM) so as to reduce the total current output by the cells of the memristor. The computing device 30 includes a memory 32 and a processor 34.

[0058] The memory 32 is, for example, a NAND flash memory, a NOR flash memory, a phase change memory (PCM), a spin-transfer torque random-access memory (STT-RAM), or a 2D or 3D structured resistive random access memory (ReRAM), which is not limited in the present invention. In some embodiments, various volatile memories (such as static random access memory (RAM), dynamic RAM) and various non-volatile memories (such as ReRAM, PCM, flash, magnetoresistive RAM, ferroelectric RAM) can be integrated to perform in-memory operations, which is not limited in the present invention.

[0059] The memory 32 includes a plurality of input lines IL that cross each other. i And multiple output lines OL j , respectively configured on the input line IL i With output line OL j The multiple units at the intersection of ij ), and are connected to the output line OL j For sensing the output line OL j Output current I j In some embodiments, the input line IL i Output line OL for word line j is a bit line, and in some embodiments, the input line IL i Output line OL for bit line j The word line is not limited in the present invention.

[0060] The processor 34 is, for example, a central processing unit (CPU) or other programmable general-purpose or special-purpose microprocessor, microcontroller (MCU), programmable controller, application specific integrated circuit (ASIC), programmable logic device (PLD), or other similar device or combination of such devices, which is not limited in the present embodiment. In the present embodiment, the processor 34 is configured to execute instructions for performing in-memory operations, as described below. In-memory operations can be implemented in various artificial intelligence (AI) applications, such as fully connected layers, convolution layers, multi-layer perception, support vector machines, or other applications implemented using memristors, which are not limited in the present invention.

[0061] Figure 4 FIG. 1 is a flow chart of a method for performing operations in a memory according to an embodiment of the present invention. Figure 3 and Figure 4 The method of this embodiment is suitable for the above-mentioned computing device 30, and the detailed steps of the in-memory operation method of this embodiment will be described below with reference to various devices and elements of the computing device 30.

[0062] First, in step S402, the processor 34 converts the format of the binary data from the floating point format to the quantized format by truncating at least a portion of the fraction bits of the binary data of the plurality of weights and calculating the complement of the remaining bits of the binary data, and programs the converted binary data of the plurality of weights into the plurality of cells. In some embodiments, the binary data of each weight in the floating point format includes a sign bit, eight exponent bits, and twenty-three fraction bits in the 32-bit binary data, and the processor 34 may truncate all twenty-three fraction bits or only a portion of the fraction bits to reduce the number of bit "1".

[0063] In some embodiments, the processor 34 may calculate the 2's complement of the remaining bits after truncation and invert the value of the calculated 2's complement so as to reduce the number of bits "1" and maximize the number of bits "0", and thereby reduce the overlap variation error.

[0064] For example, Figure 5 is a floating point format for binary data according to an embodiment of the present invention. Figure 5, the floating point format 50 of the 32-bit binary data X is a format standardized by the IEEE organization, and includes a sign bit 52, eight exponent bits 54, and twenty-three fraction bits 56. In detail, the sign of the 32-bit binary data is represented by a single bit, where bit "0" indicates a negative number, and bit "1" indicates a positive number. The exponent of the 32-bit binary data is stored as an 8-bit unsigned integer with a bias of 127. The floating point number (mantissa) of the 32-bit binary data is stored as a 23-bit unsigned integer. Taking the number 1.101×25 as an example, the sign is positive, the floating point number is "1.101", and the exponent is "5".

[0065] In some embodiments, in full precision training, the ratio of bit "0" is close to the ratio of bit "1". When the binary data is quantized to 9 bits (i.e., all fractional bits are truncated), the ratio of bit "0" decreases, while the ratio of bit "1" increases, but the training error is not significantly affected by quantization. Since the ratio of bit "1" increases when quantizing binary data, a method for flipping the value of bit "1" is proposed to reduce the number of bit "1" and maximize the number of bit "0" in order to reduce the overlap change error and increase the accuracy of training.

[0066] In some embodiments, a method called "inverting 2's complement" is performed, in which the 2's complement of an 8-bit exponent in binary data in a floating point format is calculated and the value of the calculated 2's complement is inverted. For example, for a decimal value "-1", the 2's complement of the exponent of "-1" is "01111110", and the inverted 2's complement is "00000001", which includes fewer bits "1".

[0067] Fig. 6A and Figure 6B Schematic diagrams respectively illustrate the ratio of bit “0” to bit “1” in quantized 9-bit binary data and inverted quantized 9-bit binary data according to an embodiment of the present invention. Fig. 6A The ratio of bit "0" to bit "1" of each bit in the quantized 9-bit binary data is shown, wherein the ratio of bit "1" is greater than the ratio of bit "0" in most bits of the quantized 9-bit binary data, especially in bits 2 to 5. Figure 6B ,because Fig. 6A The bits of the quantized 9-bit binary data in are inverted, so the ratio of bit "0" becomes greater than the ratio of bit "1", especially in bits 2 to 5. Regarding bits 6 to 8, the embodiment of the present invention proposes a method of data reshaping to further reduce the ratio of bit "1", which will be shown later.

[0068] return Figure 4 In step S404, the processor 34 performs the adjustment process by iteratively inputting the binary data of the plurality of input signals to the plurality of input lines ILi The output sensed by the sense amplifier SA (ie, the current I j ) for integration; and adjusting the binary data of multiple weights programmed into the cell based on the output of the integration, for multiple iterations.

[0069] In some embodiments, the adjustment procedure includes training of a neural network, wherein binary data of multiple input signals are set as inputs of the neural network, multiple weights are set as weights in multiple computing layers in the neural network, and the integrated output is set as the output of the neural network.

[0070] For example, Figure 7 Schematic diagram showing the training of a neural network according to an embodiment of the present invention. Figure 7 , the present embodiment creates a fully connected neural network 80, such as a recurrent neural network (RNN), a deep neural network (DNN) or a fully convolutional network (FCN), which includes setting multiple intermediate layers between the input layer and the output layer, and setting multiple weights for these layers. According to the calculation method shown above, the format of the weights in the neural network 80 is transformed into a quantized format and then programmed into the cells of the memory. A plurality of noisy speech signals 82 serving as input signals are input to the input line of the memory for forward propagation in the neural network. The speech signal 82 processed by the neural network 80 is output as an enhanced speech signal 84 and compared with a clean speech signal 86 serving as a reference signal of the speech signal 82 to calculate a loss function, such as a mean square error (MSE). Then, back propagation is performed in the neural network 80 to adjust the weights in the computational layer of the neural network 80. The adjusted weights are programmed into the cells of the memory for training in the next iteration. In some embodiments, training will continue for many iterations so that the enhanced speech signal 84 output by the neural network 80 is close to the clean speech signal 86, and the trained neural network 80 can be used to perform noise filtering on any speech signal input to the neural network 80 in actual implementation.

[0071] Back to Figure 4 In step S406, the processor 34 reshapes the binary data of the plurality of weights after a plurality of iterations based on reducing the probability of the bit having a value of one in the binary data of each weight, and repeats the adjustment procedure until the termination condition is met.

[0072] In some embodiments, processor 34 calculates the probability by shifting the decimal value of each weight by an arbitrary number to maximize the quotient of the reduction in bits with a value of one in the binary data of the weight and the shifted number, and dividing the quotient by a factor determined based on the data distribution of the plurality of weights, and shifting the decimal value of the weight in response to the calculated probability of the weight being greater than a threshold.

[0073] For example, Figure 8 FIG. 1 is a schematic diagram showing data reshaping according to an embodiment of the present invention. Figure 8 , assuming that the decimal value 120 is the exponent value of the weight obtained after the iteration of the adjustment procedure, the exponent value may be shifted by an arbitrary number (e.g., an integer less than the threshold value X) to obtain a shift value such as 117 or 123. Therefore, the number of reductions r of the bit "1" in the binary data of the shifted exponent value and the number of shifts x of the exponent value in the decimal are calculated respectively, and the quotient y of the number of reductions r of the bit "1" in the binary data of the weight and the number of shifts x is calculated as follows.

[0074] y=r / x. (1)

[0075] For example, for a threshold value X equal to 3, the exponent value 120 ("00000110" in binary) can be shifted to 122 ("00000100" in binary). The number of "1" bits reduced r is equal to 1 and the number of exponent shifts x is equal to 2, so the quotient y is equal to "1 / 2".

[0076] In order to reduce the bit "1" as much as possible, the quotient y should be maximized and compared with the threshold to determine whether to trigger data reshaping. In some embodiments, data reshaping is performed as follows based on the probability P calculated by dividing the calculated quotient y by a factor α determined based on the data distribution of multiple weights.

[0077] P = y × 100% / α (2)

[0078] For the above example of shifting the index value 120 ("00000110" in binary) to 122 ("00000100" in binary), the quotient y is equal to 1 / 2, and the probability P = 0.5×100% / 5 = 10%, which means that the probability of performing data reshaping is 10% and the probability of not performing data reshaping is 90%. When data reshaping is performed based on probability, the performance and accuracy of the neural network can be well balanced.

[0079] Fig. 9 FIG. 1 is a flow chart of a method for performing operations in a memory according to an embodiment of the present invention. Figure 3 and Fig. 9The method of this embodiment is suitable for the above-mentioned computing device 30, and the detailed steps of the in-memory operation method of this embodiment will be described below with reference to various devices and elements of the computing device 30.

[0080] In step S1002 , the processor 34 creates a neural network having a plurality of layers and sets weights having the quantization format as shown in the above-described embodiment to the layers.

[0081] In step S1004 , the processor 34 inputs the noisy or clean speech signal to the neural network by converting the speech signal into digital data and inputting the converted digital data to the input line ILi of the memory 32 .

[0082] In step S1006, the processor 34 enhances the speech signal by performing forward propagation of the neural network. The transformed digital data input to the input line ILi of the memory 32 is multiplied by the unit programmed into the memory 32 (connected by the resistor R ij represents the weight of the signal), and outputs the total current sensed by the sense amplifier SA of the memory 32 and converts it into an enhanced voice signal.

[0083] In step S1008, the processor 34 fine-tunes the neural network by performing back propagation of the neural network. In some embodiments, the processor 34 adjusts the weights programmed into the cells of the memory 32 based on a comparison between the enhanced speech signal and a reference clean speech signal.

[0084] In step S1010 , processor 34 determines whether the quotient y calculated by using equation (1) shown above is greater than or equal to a threshold value.

[0085] In response to the quotient y being greater than or equal to the threshold, in step S1012 , processor 34 reshapes the weights programmed into the cells of memory 32 using the likelihood calculated by equation (2) shown above.

[0086] In response to the quotient y not being greater than or equal to the threshold or the reshaping of the weights being completed, in step S1014, the processor 34 will determine whether the fine-tuning is completed. In response to determining that the fine-tuning is not completed, the processor returns to step S1004 and continues to input the speech signal to train the neural network. On the other hand, in response to determining that the fine-tuning is completed, the processor proceeds to step S1016 to end the training.

[0087] In some embodiments, the processor 34 may determine whether the fine-tuning is completed according to the number of iterations currently being performed, and determine that the fine-tuning is completed when the number of iterations reaches a predetermined number. In some embodiments, the processor 34 may determine whether the fine-tuning is completed according to the accuracy calculated based on the difference between the output enhanced speech signal and the reference clean speech signal, and determine that the fine-tuning is completed when the calculated accuracy reaches a predetermined threshold.

[0088] In some embodiments, the processor 34 may reshape in advance in response to satisfying some conditions. In some embodiments, the processor 34 may calculate the accuracy based on the difference between the integrated output and the reference signal of the input signal, and reshape in advance in response to the calculated accuracy being greater than a first threshold. In some embodiments, the processor 34 may calculate the ratio of the bit "1" to the bit "0" in the binary data of the plurality of weights, and reshape in advance in response to the calculated ratio being greater than a second threshold.

[0089] Through the methods described above, the probability of overlap variation errors can be reduced with limited impact on model accuracy.

[0090] In summary, according to an embodiment of the present invention, an in-memory computing method is proposed to balance the performance, accuracy, and data format of a neural network or other applications implementing a memristor. Therefore, the model size of the neural network or the calculation of the application can be reduced, so that the neural network or these applications can be more implementable on edge devices or other hardware with limited resources.

[0091] So far, the embodiments of the present disclosure have been described in detail with reference to the accompanying drawings.

[0092] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for performing in-memory operations, suitable for a processor to perform multiplication and addition operations on a memory having a crossbar switch architecture, wherein: The memory includes a plurality of input lines and a plurality of output lines crossing each other, a plurality of cells are respectively arranged at intersections of the input lines and the output lines, and a plurality of sense amplifiers are respectively connected to the output lines, and the method includes: Converting the format of the binary data from a floating point format to a quantized format by truncating at least a portion of fractional bits of the binary data of a plurality of weights and calculating the complement of the remaining bits of the binary data, and programming the converted binary data of the plurality of weights into the plurality of cells; performing an adjustment procedure including iteratively inputting binary data of a plurality of input signals into the plurality of input lines, integrating outputs sensed by the sense amplifiers, and adjusting the binary data of the plurality of weights programmed into the cells based on the integrated outputs, for a plurality of iterations; and After the plurality of iterations, the binary data of the plurality of weights are reshaped based on reducing the probability of a bit having a value of one in the binary data of each of the weights, and the adjustment procedure is repeated until a termination condition is met.

2. The in-memory operation method according to claim 1, wherein: The step of calculating the complement of the remaining bits of the binary data comprises: A 2's complement of the remaining bits is calculated and the value of the calculated 2's complement is inverted.

3. The in-memory operation method according to claim 1, wherein: The adjustment procedure includes training of a neural network, wherein the binary data of the multiple input signals are set as inputs of the neural network, the multiple weights are set as weights in multiple computing layers in the neural network, and the integrated output is set as the output of the neural network.

4. The in-memory operation method according to claim 3, wherein: The step of adjusting the binary data programmed into the plurality of weights in the cell based on the integrated output comprises: A difference between the integrated output and a reference signal of the input signal is calculated, and the transformed binary data of the plurality of weights to be programmed into the cell is adjusted according to the difference.

5. The in-memory operation method according to claim 4, wherein: The step of reshaping the binary data of the plurality of weights based on reducing the probability of the bit having a value of one in the binary data of each of the weights comprises: calculating an accuracy based on the difference between the integrated output and a reference signal of the input signal; and The reshaping is advanced in response to the calculated accuracy being greater than a first threshold.

6. The in-memory operation method according to claim 1, wherein: The step of reshaping the binary data of the plurality of weights based on reducing the probability of the bit having a value of one in the binary data of each of the weights comprises: calculating a ratio of the bits having a value of one to the bits having a value of zero in the binary data of the plurality of weights; and The reshaping is advanced in response to the calculated ratio being greater than a second threshold.

7. The in-memory operation method according to claim 1, wherein: The step of reshaping the binary data of the plurality of weights based on reducing the probability of the bit having a value of one in the binary data of each of the weights comprises: Calculating the probability by shifting the decimal value of each of the weights by an arbitrary number to maximize the quotient of the reduction of bits having a value of one in the binary data of the weight and the shifted number, and dividing the quotient by a factor determined based on the data distribution of the plurality of weights; and In response to the quotient being greater than or equal to a threshold, the decimal value of each of the weights is shifted according to the calculated probability.

8. The in-memory operation method according to claim 1, wherein: The binary data of each of the weights in the floating point format includes one sign bit, eight exponent bits, and twenty-three fraction bits in 32-bit binary data.

9. An in-memory computing device, wherein: include: A memory having a crossbar switch architecture, the memory comprising: A plurality of input lines and a plurality of output lines crossing each other; A plurality of units are respectively arranged at the intersections of the input line and the output line; and a plurality of sense amplifiers, connected to the output lines respectively; a processor coupled to the memory and configured to: Converting the format of the binary data from a floating point format to a quantized format by truncating at least a portion of fractional bits of the binary data of a plurality of weights and calculating the complement of the remaining bits of the binary data, and programming the converted binary data of the plurality of weights into the plurality of cells; performing an adjustment procedure including iteratively inputting binary data of a plurality of input signals into the plurality of input lines, integrating outputs sensed by the sense amplifiers, and adjusting the binary data of the plurality of weights programmed into the cells based on the integrated outputs, for a plurality of iterations; and After the plurality of iterations, the binary data of the plurality of weights are reshaped based on reducing the probability of a bit having a value of one in the binary data of each of the weights, and the adjustment procedure is repeated until a termination condition is met.

10. The in-memory computing device according to claim 9, wherein: The processor calculates a 2's complement of the remaining bits and inverts a value of the calculated 2's complement.

11. The in-memory computing device according to claim 9, wherein: The adjustment procedure includes training of a neural network, wherein the binary data of the multiple input signals are set as inputs of the neural network, the multiple weights are set as weights in multiple computing layers in the neural network, and the integrated output is set as the output of the neural network.

12. The in-memory computing device according to claim 11, wherein: The processor calculates a difference between the integrated output and a reference signal of the input signal, and adjusts the transformed binary data of the plurality of weights to be programmed into the cell according to the difference.

13. The in-memory computing device according to claim 12, wherein: The processor calculates an accuracy based on the difference between the integrated output and a reference signal of the input signal, and advances the reshaping in response to the calculated accuracy being greater than a first threshold.

14. The in-memory computing device according to claim 9, wherein: The processor calculates a ratio of the bits having a value of one to the bits having a value of zero in the binary data of the plurality of weights, and advances the reshaping in response to the calculated ratio being greater than a second threshold.

15. The in-memory computing device according to claim 9, wherein: The processor calculates the probability by shifting the decimal value of each of the weights by an arbitrary number to maximize the quotient of the reduction of bits with a value of one in the binary data of the weight and the shifted number, and dividing the quotient by a factor determined based on the data distribution of the multiple weights, and shifting the decimal value of each of the weights according to the calculated probability in response to the quotient being greater than or equal to a threshold.

16. The in-memory computing device according to claim 9, wherein: The binary data of each of the weights in the floating point format includes one sign bit, eight exponent bits, and twenty-three fraction bits in 32-bit binary data.

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