Storage units, storage devices and related identification labels

Abstract

The present invention discloses a memory cell comprising a latch, a first programmable fuse, and a second programmable fuse. The latch is powered by a first reference voltage and a second reference voltage different from the first reference voltage, and has a first connection terminal and a second connection terminal. The first programmable fuse has a first terminal coupled to the first connection terminal and a second terminal coupled to the second reference voltage. The second programmable fuse has a first terminal coupled to the second connection terminal and a second terminal coupled to the second reference voltage.

Description

Technical Field

[0001] The present invention relates to a storage unit, a storage device and an identification tag, and more particularly to a storage unit, a storage device and an identification tag for receiving and / or transmitting identification information. Background Art

[0002] Radio-frequency identification (RFID) is now being used across various industries to automatically identify and track RFID tags attached to objects using electromagnetic fields generated by radio-frequency (RF) interfaces, without the need for mechanical or optical contact. RFID tags are programmed to sense or respond to a specific frequency specific to their device. Upon sensing an electromagnetic interrogation pulse of a predetermined frequency generated by an RFID reader, they transmit an RF signal containing the tag's protocol, RFID management authority, asset information, and an identification serial number. However, RFID tags require significant time and energy to access information stored in their non-volatile memory, such as the embedded electrically erasable programmable read-only memory (EEPROM), resulting in significant energy consumption and transaction times. Furthermore, a typical RFID tag uses only 96 bits of non-volatile memory to store the identification code, which requires relatively large area and energy consumption, such as peripheral read / write circuits such as charge pumps. This limits the cost and sensitivity of the RFID tag.

[0003] Considering the authenticity and security of information, some RFID tags can be reprogrammed and rewritten by connecting them to a programmable logic controller (PLC) or computer's RFID transceiver. Therefore, current RFID tags may still have defects. Non-volatile memory is fragile in high temperature or radiation environments, affecting the reliability of the information stored on such RFID tags. Summary of the Invention

[0004] The Summary of the Invention introduces a series of simplified concepts that will be further described in the Detailed Description of the Invention. The Summary of the Invention is not intended to limit the key features and essential features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0005] According to one aspect of the present invention, a storage unit, a storage device and an identification tag are provided to receive and / or transmit identification information. One embodiment of the present invention provides a storage device for maintaining identification information, wherein the storage unit is composed of at least one programmable fuse electrically connected to a dedicated latch, and the storage unit exhibits an electrical characteristic according to the way the programmable fuse is programmed. Relatively speaking, the size of the storage unit is small and the sensing time of the electrical characteristic is short. Secondly, the reliability of information in extreme environments can be improved. The programmable fuse can be programmed by laser or layout breaking to irreversibly write identification information. Preferably, it can be performed in the wafer level testing process in semiconductor manufacturing equipment, and thus the authenticity of the information, the security of the information and the writing throughput can be improved.

[0006] According to one aspect of the present invention, a memory cell in one embodiment includes a latch, a first programmable fuse, and a second programmable fuse. The latch is powered by a first reference voltage and a second reference voltage different from the first reference voltage, and has a first connection terminal and a second connection terminal. The first programmable fuse has a first end coupled to the first connection terminal and a second end coupled to the second reference voltage, and the second programmable fuse has a first end coupled to the second connection terminal and a second end coupled to the second reference voltage.

[0007] Exemplarily, one of the first reference voltage and the second reference voltage is a power supply voltage, and the other of the first reference voltage and the second reference voltage is a ground voltage.

[0008] Exemplarily, the first programmable fuse and the second programmable fuse are laser programmable fuses.

[0009] Illustratively, one of the first programmable fuse and the second programmable fuse has been pre-programmed.

[0010] Exemplarily, the storage unit further includes: a first limiting circuit, coupling the second end of the first programmable fuse to the second reference voltage according to a first control signal; and a second limiting circuit, coupling the second end of the second programmable fuse to the reference voltage according to a second control signal.

[0011] Exemplarily, the first control signal and the second control signal are the first reference voltage.

[0012] Exemplarily, the first control signal and the second control signal are the second reference voltage.

[0013] Exemplarily, the first control signal is the first reference voltage, and the second control signal is the second reference voltage.

[0014] Exemplarily, the first limiting circuit includes: a first transistor having a first connection terminal, a second connection terminal and a control terminal, the first connection terminal is coupled to the second terminal of the first programmable fuse, the second connection terminal is coupled to the second reference voltage, and the control terminal is coupled to the first control signal; and the second limiting circuit includes: a second transistor having a first connection terminal, a second connection terminal and a control terminal, the first connection terminal is coupled to the second terminal of the first programmable fuse, the second connection terminal is coupled to the second reference voltage, and the control terminal is coupled to the second control signal.

[0015] Exemplarily, the first transistor and the second transistor are metal-oxide-semiconductor field-effect transistors (MOSFETs), and the first control signal and the second control signal are the first reference voltage.

[0016] Exemplarily, the first transistor and the second transistor are native MOSFETs, and the first control signal and the second control signal are the second reference voltage.

[0017] Illustratively, one of the first programmable fuse and the second programmable fuse is programmable to form an open circuit.

[0018] Exemplarily, one of the first control signal and the second control signal is a power supply voltage, and the power supply voltage is turned on when reading the memory cell.

[0019] According to another aspect of the present invention, a memory cell in one embodiment includes a latch, a first programmable fuse, and a second programmable fuse. The latch is powered by a first reference voltage and a second reference voltage different from the first reference voltage, and has a connection terminal. The first programmable fuse has a first terminal coupled to the connection terminal and a second terminal coupled to the first reference voltage. The second programmable fuse has a first terminal coupled to the connection terminal and a second terminal coupled to the second reference voltage.

[0020] Exemplarily, one of the first reference voltage and the second reference voltage is a power supply voltage, and the other of the first reference voltage and the second reference voltage is a ground voltage.

[0021] Illustratively, one of the first programmable fuse and the second programmable fuse has been pre-programmed.

[0022] Exemplarily, the first programmable fuse and the second programmable fuse are laser programmable fuses.

[0023] Exemplarily, the storage unit further includes: a first limiting circuit, coupling the second end of the first programmable fuse to the first reference voltage according to a first control signal; and a second limiting circuit, coupling the second end of the second programmable fuse to the second reference voltage according to a second control signal.

[0024] Exemplarily, the first control signal is the second reference voltage, and the second control signal is the first reference voltage.

[0025] Exemplarily, the first limiting circuit includes: a first transistor having a first connection terminal, a second connection terminal and a control terminal, the first connection terminal being coupled to the second terminal of the first programmable fuse, the second connection terminal being coupled to the first reference voltage, and the control terminal being coupled to the first control signal; and the second limiting circuit includes: a second transistor having a first connection terminal, a second connection terminal and a control terminal, the first connection terminal being coupled to the second terminal of the first programmable fuse, the second connection terminal being coupled to the second reference voltage, and the control terminal being coupled to the second control signal; wherein the first control signal is the second reference voltage, and the second control signal is the first reference voltage.

[0026] Exemplarily, the first transistor is a P-type MOSFET, and the second transistor is an N-type MOSFET.

[0027] Illustratively, one of the first programmable fuse and the second programmable fuse is programmed to form an open circuit.

[0028] Exemplarily, one of the first control signal and the second control signal is a power supply voltage, and the power supply voltage is turned on when reading the memory cell.

[0029] According to another aspect of the present invention, an identification tag of one embodiment includes a storage device for storing identification information. The storage device includes a storage block, and the storage block includes a plurality of storage cells. At least one storage cell includes a latch, a first programmable fuse, and a second programmable fuse. The latch is powered by a first reference voltage and a second reference voltage different from the first reference voltage, and has a first connection end and a second connection end. The first programmable fuse has a first end coupled to the first connection end and a second end coupled to the second reference voltage, and the second programmable fuse has a first end coupled to the second connection end and a second end coupled to the second reference voltage. One of the first programmable fuse and the second programmable fuse is programmed to form an open circuit.

[0030] According to another aspect of the present invention, a memory device for storing identification information includes a memory block and a sensing circuit. The memory block includes a plurality of memory cells, each of which has a latch and a plurality of programmable fuses. The programmable fuses are electrically connected to the latch and exhibit an electrical characteristic depending on how the programmable fuses are programmed. The sensing circuit is electrically connected to the memory block to sense the electrical characteristics of the memory cells, and the electrical characteristics of the memory cells collectively represent the identification information.

[0031] Exemplarily, the electrical characteristic is a voltage level.

[0032] Illustratively, in at least one of the memory cells, the programmable fuses form a programmable fuse pair.

[0033] Exemplarily, in at least one of the memory cells, the latch includes two back gates, and the programmable fuses of the programmable fuse pair are electrically connected to a connection end of one of the back gates and a connection end of the other of the back gates, respectively.

[0034] Exemplarily, in at least one of the memory cells, the latch includes two back gates, and the programmable fuses in the programmable fuse pair are simultaneously electrically connected to a connection end of one of the back gates and a connection end of the other of the back gates.

[0035] Illustratively, in at least one of the memory cells, a programmable fuse pair is programmed.

[0036] Illustratively, in at least one of the memory cells, one of the first programmable fuse and the second programmable fuse has been pre-programmed. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The following drawings of the present invention are incorporated herein as part of the present invention for understanding the present invention. The drawings show embodiments of the present invention and the description thereof is used to explain the principle of the present invention.

[0038] In the attached figure:

[0039] Figure 1 An exemplary functional block diagram of an identification tag according to a first embodiment of the present invention is shown;

[0040] Figure 2 An exemplary functional block diagram of a protocol processing and control unit according to a first embodiment of the present invention is shown;

[0041] Figure 3 An exemplary functional block diagram showing a sensor circuit of an identification tag according to a first embodiment of the present invention;

[0042] Figure 4 Five exemplary circuit structures of a memory cell according to a first embodiment of the present invention are shown;

[0043] Figure 5 An exemplary circuit structure of a programmable fuse according to a first embodiment of the present invention is shown;

[0044] Figures 6 to 9 Shows an exemplary circuit structure of a memory cell according to the second, third, fourth and fifth embodiments of the present invention; and

[0045] Figure 10 An example table showing information representative of a situation in which a programmable fuse is blown according to the first embodiment of the present invention is shown. DETAILED DESCRIPTION

[0046] In the following description, numerous specific details are provided to provide a more thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without one or more of these details. In other instances, certain technical features well known in the art are not described to avoid confusion with the present invention.

[0047] To provide a thorough understanding of the present invention, the following description provides a detailed explanation of the memory cell, storage device, and related identification tag apparatus and method of the present invention. Obviously, the present invention is not limited to the specific details familiar to those skilled in the semiconductor field. Preferred embodiments of the present invention are described below in detail, but in addition to these detailed descriptions, the present invention may also have other embodiments.

[0048] It should be noted that the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit exemplary embodiments according to the present invention. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should also be understood that when the terms "comprise" and / or "include" are used in this specification, they indicate the presence of the features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof.

[0049] Now, exemplary embodiments according to the present invention will be described in more detail with reference to the accompanying drawings. However, these exemplary embodiments may be implemented in a variety of different forms and should not be construed as being limited to the embodiments set forth herein. It should be understood that these embodiments are provided to make the disclosure of the present invention thorough and complete and to fully convey the concepts of these exemplary embodiments to those of ordinary skill in the art. In the accompanying drawings, for clarity, identical reference numerals are used to represent identical elements, and their descriptions will be omitted.

[0050] The present application provides examples of a memory cell, a storage device for storing identification information, and an identification tag. One embodiment of a memory cell may include a latch, a first programmable fuse, and a second programmable fuse. The latch may be powered by a first reference voltage and a second reference voltage different from the first reference voltage, and may have a first connection terminal and a second connection terminal. The first programmable fuse may have a first end coupled to the first connection terminal and a second end coupled to the second reference voltage. The second programmable fuse may have a first end coupled to the second connection terminal and a second end coupled to the second reference voltage.

[0051] One embodiment of a memory cell may include a latch, a first programmable fuse, and a second programmable fuse. The latch may be powered by a first reference voltage and a second reference voltage different from the first reference voltage, and may have a connection terminal. The first programmable fuse may have a first terminal coupled to the connection terminal and a second terminal coupled to the first reference voltage, and the second programmable fuse may have a first terminal coupled to the connection terminal and a second terminal coupled to the second reference voltage.

[0052] One embodiment of an identification tag may include a memory device that stores identification information. The memory device may include a memory block, which may include a plurality of memory cells. At least one memory cell may include a latch, a first programmable fuse, and a second programmable fuse. The latch may be powered by a first reference voltage and a second reference voltage different from the first reference voltage, and may have a first connection end and a second connection end. The first programmable fuse may have a first end coupled to the first connection end and a second end coupled to the second reference voltage, and the second programmable fuse may have a first end coupled to the second connection end and a second end coupled to the second reference voltage. One of the first programmable fuse and the second programmable fuse may be programmed to form an open circuit.

[0053] One embodiment of a memory device for storing identification information may include a memory block and a sensing circuit. The memory block may include a plurality of memory cells, each of which may have a latch and a plurality of programmable fuses. The programmable fuses may be electrically connected to the latch to exhibit an electrical characteristic depending on how the programmable fuses are programmed. The sensing circuit may be electrically connected to the memory block to sense the electrical characteristics of the memory cells, and the electrical characteristics of the memory cells may collectively represent the identification information.

[0054] Please refer to Figures 1 to 5 and Figure 10 . Figure 1 An exemplary functional block diagram of an identification tag according to a first embodiment of the present invention is shown. Figure 2 An exemplary functional block diagram of a protocol processing and control unit according to a first embodiment of the present invention is shown. Figure 3 An exemplary functional block diagram of a sensor circuit of an identification tag according to a first embodiment of the present invention is shown. Figure 4 Five exemplary circuit structures of a memory cell according to the first embodiment of the present invention are shown. Figure 5 An exemplary circuit structure of a programmable fuse according to the first embodiment of the present invention is shown. Figure 10 An example table showing information representative of a situation in which a programmable fuse is blasted according to the first embodiment of the present invention is shown.

[0055] like Figure 1As shown, an identification tag 100 of the present invention may include a protocol processing and control unit 110, a storage device 120 and a non-volatile memory 130. The protocol processing and control unit 110 is electrically connected to the storage device 120 and the non-volatile memory 130, and may transmit a signal including identification information stored in the storage device 120 to an identification reader (not shown) in accordance with a communication standard. In this embodiment, the communication standard may be implemented using a radio-frequency (RF) interface, and in this case, the identification reader may be a radio-frequency identification reader (RFID reader), and the identification tag 100 may be used to replace an RFID tag to implement radio frequency identification. The aforementioned signal may be a radio frequency signal. When the protocol processing and control unit 110 uses a predetermined frequency and data packet protocol to complete a handshaking process with the identification reader, it may output another signal including identification information to the identification reader. As Figure 2 As shown, the exemplary protocol processing and control unit 110 may include a control logic 111, a demodulator 112, a rectifier 113, a regulator 114, a reference voltage generator 115, a modulator 116, and an antenna 117. The control logic 111 may control the operation of the storage device 120 and the non-volatile memory 130. The modulator 116 may modulate the signal before the antenna 117 transmits the signal wirelessly. The signal received from the antenna 117 may be processed in one of the following two ways: one is to be demodulated by the demodulator 112 and then transmitted to the control logic 111; the other is to be rectified by the rectifier 113, cut off the DC voltage when it exceeds a predetermined limit value, and regulated by the regulator 114 that receives at least one fixed voltage from the reference voltage generator 115 to generate at least one reference voltage. This reference voltage is, for example, V DD , which may then be transmitted to the control logic 111 .

[0056] The storage device 120 may include a sensing circuit 122 and a storage block 124. Figure 3As shown, the sensing circuit 122 electrically connected to the memory block 124 may implement, but is not limited to, a sense amplifier comprised of three positive channel metal oxide semiconductors (PMOS) P1, P2, and P3 and three negative channel metal oxide semiconductors (NMOS) N1, N2, and N3. The sensing circuit 122 may be multiplexed to sense multiple bits, or may be configured to sense a specific bit of the identification information stored in the memory block 124. In the latter case, sensing time may be shortened.

[0057] The memory block 124 may include a plurality of memory cells, each of which may have a latch and a plurality of programmable fuses electrically connected to the latch. The number of memory cells may vary depending on the needs, but the context of the RFID tag used in this embodiment is 96 bits, thereby storing an RFID serial number. The figure shows an example memory cell 126. Two reference voltages V DD and V SS The latch that provides power is composed of two inverting gates that are electrically connected in opposite directions or cross-coupled. One inverting gate includes an NMOS M1 and a PMOS M3, and the other inverting gate includes an NMOS M2 and a PMOS M4. DD is a power supply voltage, and V S is a ground voltage. Preferably, V DD Only when reading the memory cell 126, V DD The reverse gate can be a NOT gate, a NAND gate, a NOR gate, etc. Here, both reverse gates are NOT gates. Two connection terminals O1 and O2 are provided. An output voltage level outputted by one connection terminal O1 / O2 of the NOT gate can be a voltage level outputted from a high level reference voltage V at a connection terminal I1 / I2. DD For example, the high voltage level input at the connection terminal I1 is inverted to generate a low voltage level output at the connection terminal O1.

[0058] like Figure 5As shown, the programmable fuses F1 and F2 can be laser programmable fuses, that is, they can be laser blasted or opened to form an open circuit. Specifically, each programmable fuse F1 and F2 can be composed of a programmable portion 127 and its two ends. The programmable portion 127 can be laser blasted, and the two ends of the programmable portion 127 can form a conductive through-hole 128 for connection. Preferably, after the material constituting the programmable portion 127 is laser blasted, a programming window (or an exposure opening) 129 can be formed on the programmable portion 127. The laser beam can blast the programmable portion 127 through the programming window 129 to form an open circuit between the two through-holes 128. As shown in FIG. Figure 4 As shown, two programmable fuses F1 and F2 form a programmable fuse pair, wherein each programmable fuse is electrically connected to the connection terminal I1 / I2 of one of the back gates and the connection terminal O2 / O1 of the other back gate. The other terminals F1T2 and F2T2 of the programmable fuses F1 and F2 are electrically connected to a limiting device L1 / L2, respectively, such as a current limiting device implemented by a transistor, which can be a metal-oxide-semiconductor field-effect transistor (MOSFET), NMOS, etc. Specifically, the programmable fuse F1 can have a terminal F1T1 coupled to the connection terminal O1 and coupled to the reference voltage V through the limiting device L1. S The other end F1T2 of the programmable fuse F2 may have a terminal F2T1 coupled to the connection terminal O2 and a terminal F2T2 coupled to the reference voltage V through the limiting device L2. S The limiting device L1 / L2 can provide a connection terminal L1T1 / L2T1 coupled to the F1T2 / F2T2 terminal of the programmable fuse F1 / F2, coupled to the reference voltage V SS The other connection end L1T2 / L2T2 is coupled to a control signal V DD A control terminal L1T3 / L2T3 is provided, so the limiting devices L1 and L2 can be arranged to control the control signal V DD , couple the F1T2 and F2T2 terminals of the programmable fuses F1 and F2 to the reference voltage V S In this example, the control signal V DD is the reference voltage V DDThe same. Preferably, the programmable fuses F1 and F2 can be implemented in a semiconductor chip having a size much smaller than a non-volatile memory having conventional non-volatile memory cells therein. The identification information can be written into the programmable fuse of each memory cell 126 by programming the programmable fuses F1 and F2 using a laser. The electrical characteristics exhibited by the connection terminal O2 can be affected by the programming of the programmable fuses F1 and F2, and this electrical characteristic can be sensed by the sensing circuit 122. In this embodiment, the electrical characteristic can be a voltage level. The writing process can be performed during the wafer level testing process in semiconductor manufacturing equipment to improve writing throughput. After the laser is written once, the memory cell can only be read. In other words, because the identification information is fixed to the content written to the memory cell and cannot be changed, this provides strong information authenticity and security.

[0059] Please refer to Figure 10 , which shows an example of displaying a bit value based on the way the programmable fuse is programmed. When the programmable fuse F1 is programmed by the laser beam, but the programmable fuse F2 is not programmed, a high voltage level can be sensed at the connection terminal O1, and thus a bit value of 1 is read from the memory cell 126. Conversely, when the programmable fuse F1 is not programmed and the programmable fuse F2 is programmed, a low voltage level can be sensed at the connection terminal O1, and thus a bit value of 0 is read from the memory cell 126. Sensing the bit value only requires very low power-up energy and does not require a special power-up procedure, which can simplify the circuit design of the sensing circuit 122 and speed up the sensing time. Secondly, the limiting device L1 and / or the limiting device L2 can be an optional device. In other embodiments, the F1T2 terminal and / or the F2T2 terminal can be directly connected to the reference voltage V SS .

[0060] The non-volatile memory 130 can store configuration information, such as process settings related to transistor threshold / leakage or resistor sheet resistance, which can be related to trimming. In some embodiments of the present invention, a non-volatile memory may not be present in an identification tag.

[0061] Figures 6 to 9 Various exemplary designs of a memory cell are shown. In each exemplary memory cell, there is a latch, which is controlled by two reference voltages, V DD and V SSPower is provided, and there are multiple programmable fuses electrically connected to the latch. Preferably, two programmable fuses F1 and F2 form a programmable fuse pair. The programmable fuses F1 and F2 can be implemented in a semiconductor chip that is significantly smaller than a non-volatile memory device having conventional non-volatile memory cells. Identification information can be written into the programmable fuses of each memory cell 126 by laser programming the programmable fuses F1 and F2. The programming of the programmable fuses F1 and F2 can affect the electrical characteristics exhibited by the connection terminal O2, which can be sensed by the sensing circuit 122. In this embodiment, the electrical characteristic can be a voltage level. The writing process can be performed during wafer-level testing in semiconductor manufacturing equipment to improve writing throughput. After the laser is written once, the memory cell can only be read. In other words, because the identification information is fixed to the content written to the memory cell and cannot be changed, this provides robust information authenticity and security.

[0062] Figure 6 The design of a storage unit 126 in a second embodiment of the present invention is shown. Figure 4 Similarly, a latch is formed by two reverse gates electrically connected in reverse directions, wherein one reverse gate includes an NMOS M1 and a PMOS M3, and the other reverse gate includes an NMOS M2 and a PMOS M4. An output voltage level presented at a connection terminal O1 / O2 of the NOT gate can be a voltage level at a connection terminal I1 / I2 from a high level reference voltage V DD The signal is obtained by inverting. For example, by inverting the high voltage level input at the connection terminal I1, a low voltage level can be generated at the connection terminal O1. The programmable fuses F1 and F2 are electrically connected to the connection terminals I1 / I2 of one of the back gates and the connection terminal O2 / O1 of the other back gate, respectively. The other terminals F1T2 and F2T2 of the programmable fuses F1 and F2 are respectively coupled to the reference voltage V through a limiting device L3 / L4. S The limiting devices L3 and L4 can be, for example, a zero-threshold voltage device implemented by a transistor (zero-V t device), here taking native MOSFET as an example, a connection terminal L3T1 / L4T1 coupled to the F1T2 / F2T2 terminal of the programmable fuse F1 / F2, a connection terminal L3T1 / L4T1 coupled to the reference voltage V SS The other connection end L3T2 / L4T2 is coupled to a control signal V SS A control terminal L3T3 / L4T3 is provided, so the limiting devices L3 and L4 can be set to control the control signal V SS The F1T2 and F2T2 terminals of the programmable fuses F1 and F2 are coupled to the reference voltage V S , control signal VSS For example, with the reference voltage V S same.

[0063] In this embodiment, when the programmable fuse F1 is programmed and the programmable fuse F2 is not programmed, a high voltage level can be sensed at the connection terminal O1, and thus a bit value of 1 is read from the memory cell 126. Conversely, when the programmable fuse F1 is not programmed and the programmable fuse F2 is programmed, a low voltage level can be sensed at the connection terminal O1, and thus a bit value of 0 is read from the memory cell 126. Sensing the bit value only requires very low power-up energy and does not require a special power-up procedure, which can simplify the circuit design of the sensing circuit 122 and speed up the sensing time. Secondly, the limiting device L3 and / or the limiting device L4 can be an optional device. In other embodiments, the F1T2 terminal and / or the F2T2 terminal can be directly connected to the reference voltage V SS .

[0064] Figure 7 The design of a storage unit 126 in a third embodiment of the present invention is shown. Figure 4 Similarly, there are two reference voltages, V DD and V SS A latch that provides power is composed of two reverse gates electrically connected to each other in reverse directions, wherein one reverse gate includes an NMOS M1 and a PMOS M3, and the other reverse gate includes an NMOS M2 and a PMOS M4. An output voltage level presented at a connection terminal O1 / O2 of the reverse gate can be a voltage level at a connection terminal I1 / I2 from a high level reference voltage V DD The signal is obtained by inverting. For example, by inverting the high voltage level input at the connection terminal I1, a low voltage level can be generated at the connection terminal O1. The programmable fuses F1 and F2 are both electrically connected to the connection terminal I1 including the back gate of NMOS M1 and PMOS M3 and the connection terminal O2 including the other back gate of NMOS M2 and PMOS M4. The other ends F1T2 and F2T2 of the programmable fuses F1 and F2 are respectively coupled to the reference voltage V through a limiting device L5 / L6. DD / V S The limiting devices L5 and L6 can be implemented by a transistor, for example, NMOS and PMOS, which can provide a connection terminal L5T1 / L6T1 coupled to the F1T2 / F2T2 terminal of the programmable fuse F1 / F2, and a connection terminal L5T1 / L6T1 coupled to the reference voltage V DD / V SS The other connection end L5T2 / L6T2 is coupled to a control signal V SS / V DD A control terminal L5T3 / L6T3 can be set to limit the device L5, L6 according to the control signal VSS / V DD The F1T2 and F2T2 terminals of the programmable fuses F1 and F2 are coupled to the reference voltage V DD / V S , control signal V SS / V DD For example, with the reference voltage V SS / V DD same.

[0065] In this embodiment, when the programmable fuse F1 is programmed and the programmable fuse F2 is not programmed, a high voltage level can be sensed at the connection terminal O1, and thus a bit value of 1 is read from the memory cell 126. Conversely, when the programmable fuse F1 is not programmed and the programmable fuse F2 is programmed, a low voltage level can be sensed at the connection terminal O1, and thus a bit value of 0 is read from the memory cell 126. Sensing the bit value only requires very low power-up energy and does not require a special power-up procedure, which can simplify the circuit design of the sensing circuit 122 and speed up the sensing time. Secondly, the limiting device L5 and / or the limiting device L6 can be an optional device. In other embodiments, the F1T2 terminal and / or the F2T2 terminal can be directly connected to the reference voltage V SS .

[0066] Figure 8 The design of a storage unit 126 in a fourth embodiment of the present invention is shown. Figure 4 Similarly, with two reference voltages, V DD and V SS A latch that provides power is formed by two reverse gates electrically connected to each other in reverse directions, wherein one reverse gate includes an NMOS M1 and a PMOS M3, and the other reverse gate includes an NMOS M2 and a PMOS M4. An output voltage level presented at a connection terminal O1 / O2 of the NOT gate can be a voltage level at a connection terminal I1 / I2 from a high level reference voltage V DD The signal is obtained by inverting. For example, by inverting the high voltage level input at the connection terminal I1, a low voltage level can be output at the connection terminal O1. The programmable fuses F1 and F2 are both electrically connected to the connection terminal I1 including the back gate of NMOS M1 and PMOS M3 and the connection terminal O2 including the other back gate of NMOS M2 and PMOS M4. The other ends F1T2 and F2T2 of the programmable fuses F1 and F2 are respectively coupled to the reference voltage V through a limiting device L7 / L8. DD / V SThe limiting devices L7 and L8 can be, for example, current limiting devices or zero threshold voltage devices implemented by a transistor. Here, depletion mode NMOS and PMOS are used as examples. They can provide a connection terminal L7T1 / L8T1 coupled to the F1T2 / F2T2 terminal of the programmable fuse F1 / F2, and a connection terminal L7T1 / L8T1 coupled to the reference voltage V DD / V SS The other connection end L7T2 / L8T2 is coupled to a control signal V SS / V DD A control terminal L7T3 / L8T3 can be set to limit the device L7, L8 according to the control signal V SS / V DD The F1T2 and F2T2 terminals of the programmable fuses F1 and F2 are coupled to the reference voltage V DD / V S , control signal V SS / V DD For example, with the reference voltage V SS / V DD same.

[0067] In this embodiment, when the programmable fuse F1 is programmed and the programmable fuse F2 is not programmed, a high voltage level can be sensed at the connection terminal O1, and thus a bit value of 1 is read from the memory cell 126. Conversely, when the programmable fuse F1 is not programmed and the programmable fuse F2 is programmed, a low voltage level can be sensed at the connection terminal O1, and thus a bit value of 0 is read from the memory cell 126. Sensing the bit value only requires very low power-up energy and does not require a special power-up procedure, which can simplify the circuit design of the sensing circuit 122 and speed up the sensing time. Secondly, the limiting device L7 and / or the limiting device L8 can be an optional device. In other embodiments, the F1T2 terminal and / or the F2T2 terminal can be directly connected to the reference voltage V SS .

[0068] Figure 9 The fifth embodiment of the present invention shows the design of a storage unit 126. Figure 4 Similarly, there are two reference voltages, V DD and V SS A latch that provides power is composed of two reverse gates electrically connected to each other in reverse directions, wherein one reverse gate includes an NMOS M1 and a PMOS M3, and the other reverse gate includes an NMOS M2 and a PMOS M4. An output voltage level presented at a connection terminal O1 / O2 of the reverse gate can be a voltage level at a connection terminal I1 / I2 from a high level reference voltage V DDThe signal is obtained by inverting. For example, by inverting the high voltage level input at the connection terminal I1, a low voltage level can be generated at the connection terminal O1. The programmable fuses F1 and F2 are electrically connected to the connection terminals I1 / I2 of one back gate and O2 / O2 of the other back gate, respectively. The other terminals F1T2 and F2T2 of the programmable fuses F1 and F2 are respectively coupled to the reference voltage V through a limiting device L9 / L10. DD The limiting devices L9 and L10 can be current limiting devices implemented by a transistor, for example, a PMOS, which can provide a connection terminal L9T1 / L10T1 coupled to the F1T2 / F2T2 terminal of the programmable fuse F1 / F2, and a connection terminal L9T1 / L10T1 coupled to the reference voltage V DD The other connection end L9T2 / L10T2 is coupled to a control signal V SS A control terminal L9T3 / L10T3 is provided, so the limiting device L9, L10 can be set to control the control signal V SS The F1T2 and F2T2 terminals of the programmable fuses F1 and F2 are coupled to the reference voltage V DD , control signal V SS For example, with the reference voltage V SS same.

[0069] In this embodiment, when the programmable fuse F1 is programmed and the programmable fuse F2 is not programmed, a high voltage level can be sensed at the connection terminal O2, and thus a bit value of 1 is read from the memory cell 126. Conversely, when the programmable fuse F1 is not programmed and the programmable fuse F2 is programmed, a low voltage level can be sensed at the connection terminal O2, and thus a bit value of 0 is read from the memory cell 126. Sensing the bit value only requires very low power-up energy and does not require a special power-up procedure, which can simplify the circuit design of the sensing circuit 122 and speed up the sensing time. Secondly, the limiting device L9 and / or the limiting device L10 can be an optional device. In other embodiments, the F1T2 terminal and / or the F2T2 terminal can be directly connected to the reference voltage V DD .

[0070] The storage unit 126 designed according to a sixth embodiment of the present invention is shown in FIG. Figure 4 and Figure 6-10In a memory cell 126, one of the programmable fuses F1 and F2 can be pre-programmed by designing a disconnected wiring. That is, one of the programmable fuses F1 and F2 is manufactured to be open. Preferably, some of the die in the mask can be pre-programmed to reduce programming time, while other die can be unpre-programmed. Specifically, the pre-programmable die can have a serial number that increases by 1 each time. Then, only the common bits of the majority of the die in the mask need to be programmed by the laser.

[0071] According to the present invention, in the limiting devices L1-L10, the threshold voltage of the transistor is not limited to Figure 4 and Figure 6-9 As shown, the threshold voltage of the transistor can be designed to have multiple customized threshold voltages to optimize the performance of each memory cell.

[0072] As previously described, in an embodiment of the present invention, a storage device, an identification tag, and an identification information receiving and transmitting system that receive and / or transmit identification information store identification information in a well-designed and novel storage unit, each of which is formed by at least a programmable fuse, which is electrically connected to a latch and exhibits an electrical characteristic according to the way the programmable fuse is programmed. Compared to conventional methods, the size of the storage unit is smaller and the time it takes to sense the electrical characteristic is also shorter. Secondly, the reliability of information in extreme environments can be improved. The identification information can be irreversibly written by programming the programmable fuse by laser or layout breaking. Preferably, this can be performed in a wafer level testing process in semiconductor manufacturing equipment, and thus the authenticity of the information, the security of the information, and the writing throughput can be improved.

[0073] The present invention has been described through the above-described embodiments. However, it should be understood that the above-described embodiments are for illustrative and illustrative purposes only and are not intended to limit the present invention to the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the above-described embodiments and that various variations and modifications may be made based on the teachings of the present invention, all of which fall within the scope of the present invention. The scope of protection of the present invention is defined by the appended claims and their equivalents.

Claims

1. A storage unit, characterized in that: include: a latch powered by a first reference voltage and a second reference voltage different from the first reference voltage, and having a first connection end and a second connection end; a first programmable fuse having a first end coupled to the first connection end and a second end coupled to the second reference voltage; a second programmable fuse having a first end coupled to the second connection end and a second end coupled to the second reference voltage; a first limiting circuit, coupling the second end of the first programmable fuse to the second reference voltage according to a first control signal, the first limiting circuit comprising: a first transistor having a first connection terminal, a second connection terminal, and a control terminal, wherein the first connection terminal is coupled to the second terminal of the first programmable fuse, the second connection terminal is coupled to the second reference voltage, and the control terminal is coupled to the first control signal; and a second limiting circuit, coupling the second end of the second programmable fuse to the second reference voltage according to a second control signal, the second limiting circuit comprising: a second transistor having a first connection terminal, a second connection terminal, and a control terminal, wherein the first connection terminal is coupled to the second terminal of the first programmable fuse, the second connection terminal is coupled to the second reference voltage, and the control terminal is coupled to the second control signal; The first transistor and the second transistor are metal oxide semiconductor field effect transistors, and the first control signal and the second control signal are the first reference voltage.

2. The storage unit according to claim 1, wherein One of the first reference voltage and the second reference voltage is a power supply voltage, and the other of the first reference voltage and the second reference voltage is a ground voltage.

3. The storage unit according to claim 1, wherein The first programmable fuse and the second programmable fuse are laser programmable fuses.

4. The storage unit according to claim 1, wherein One of the first programmable fuse and the second programmable fuse has been pre-programmed.

5. The storage unit according to claim 1, wherein One of the first programmable fuse and the second programmable fuse is programmable to form an open circuit.

6. A storage unit, characterized in that: include: a latch powered by a first reference voltage and a second reference voltage different from the first reference voltage, and having a first connection end and a second connection end; a first programmable fuse having a first end coupled to the first connection end and a second end coupled to the second reference voltage; a second programmable fuse having a first end coupled to the second connection end and a second end coupled to the second reference voltage; a first limiting circuit, coupling the second end of the first programmable fuse to the second reference voltage according to a first control signal, the first limiting circuit comprising: a first transistor having a first connection terminal, a second connection terminal, and a control terminal, wherein the first connection terminal is coupled to the second terminal of the first programmable fuse, the second connection terminal is coupled to the second reference voltage, and the control terminal is coupled to the first control signal; and a second limiting circuit, coupling the second end of the second programmable fuse to the second reference voltage according to a second control signal, the second limiting circuit comprising: a second transistor having a first connection terminal, a second connection terminal, and a control terminal, wherein the first connection terminal is coupled to the second terminal of the first programmable fuse, the second connection terminal is coupled to the second reference voltage, and the control terminal is coupled to the second control signal; The first transistor and the second transistor are native metal oxide semiconductor field effect transistors, and the first control signal and the second control signal are the second reference voltage.

7. The storage unit according to claim 6, wherein: One of the first control signal and the second control signal is a power supply voltage, and the power supply voltage is turned on when reading the memory cell.

8. A storage unit, characterized in that: include: a latch powered by a first reference voltage and a second reference voltage different from the first reference voltage, and having a connection terminal; a first programmable fuse having a first end coupled to the connection end and a second end coupled to the first reference voltage; and a second programmable fuse having a first end coupled to the connection end and a second end coupled to the second reference voltage; a first limiting circuit coupling the second end of the first programmable fuse to the first reference voltage according to a first control signal; a second limiting circuit coupling the second end of the second programmable fuse to the second reference voltage according to a second control signal; The first control signal is the second reference voltage, and the second control signal is the first reference voltage.

9. The storage unit according to claim 8, wherein One of the first reference voltage and the second reference voltage is a power supply voltage, and the other of the first reference voltage and the second reference voltage is a ground voltage.

10. The storage unit according to claim 8, wherein One of the first programmable fuse and the second programmable fuse has been pre-programmed.

11. The storage unit according to claim 8, wherein The first programmable fuse and the second programmable fuse are laser programmable fuses.

12. The storage unit according to claim 8, wherein: The first limiting circuit includes: a first transistor having a first connection terminal, a second connection terminal, and a control terminal, wherein the first connection terminal is coupled to the second terminal of the first programmable fuse, the second connection terminal is coupled to the first reference voltage, and the control terminal is coupled to the first control signal; and The second limiting circuit includes: A second transistor has a first connection terminal, a second connection terminal and a control terminal, wherein the first connection terminal is coupled to the second terminal of the first programmable fuse, the second connection terminal is coupled to the second reference voltage, and the control terminal is coupled to the second control signal.

13. The storage unit according to claim 12, wherein: The first transistor is a P-type metal oxide semiconductor field effect transistor, and the second transistor is an N-type metal oxide semiconductor field effect transistor.

14. The storage unit according to claim 8, wherein One of the first programmable fuse and the second programmable fuse is programmed to form an open circuit.

15. The storage unit according to claim 8, wherein One of the first control signal and the second control signal is a power supply voltage, and the power supply voltage is turned on when reading the memory cell.

16. An identification tag, characterized in that: include: A storage device for storing identification information, comprising: A storage block includes a plurality of storage units, and at least one of the storage units includes: a latch powered by a first reference voltage and a second reference voltage different from the first reference voltage, and having a first connection end and a second connection end; a first programmable fuse having a first end coupled to the first connection end and a second end coupled to the second reference voltage; a second programmable fuse having a first end coupled to the second connection end and a second end coupled to the second reference voltage; a first limiting circuit, coupling the second end of the first programmable fuse to the first reference voltage according to a first control signal, the first limiting circuit comprising: A first transistor having a first connection terminal, a second connection terminal and a control The first connection end is coupled to the second end of the first programmable fuse, The second connection terminal is coupled to the second reference voltage, and the control terminal is coupled to the first control signal; and a second limiting circuit, coupling the second end of the second programmable fuse to the second reference voltage according to a second control signal, the second limiting circuit comprising: A second transistor having a first connection terminal, a second connection terminal and a control The first connection end is coupled to the second end of the first programmable fuse, The second connection terminal is coupled to the second reference voltage, and the control terminal is coupled to the second control signal; One of the first programmable fuse and the second programmable fuse is programmed to form an open circuit, the first transistor and the second transistor are metal oxide semiconductor field effect transistors, and the first control signal and the second control signal are the first reference voltage.

17. The identification label according to claim 16, wherein: One of the first reference voltage and the second reference voltage is a power supply voltage, and the other of the first reference voltage and the second reference voltage is a ground voltage.

18. The identification tag according to claim 16, wherein: The first programmable fuse and the second programmable fuse are laser programmable fuses.

19. The identification tag according to claim 18, wherein In at least one of the memory cells, the latch includes two back gates having the first connection end and the second connection end.

20. A storage unit, characterized in that: include: a latch powered by a first reference voltage and a second reference voltage different from the first reference voltage, and having a connection terminal; a first programmable fuse having a first end coupled to the connection end and a second end coupled to the first reference voltage; and a second programmable fuse having a first end coupled to the connection end and a second end coupled to the second reference voltage; a first limiting circuit, coupling the second end of the first programmable fuse to the first reference voltage according to a first control signal, the first limiting circuit comprising: a first transistor having a first connection terminal, a second connection terminal, and a control terminal, wherein the first connection terminal is coupled to the second terminal of the first programmable fuse, the second connection terminal is coupled to the first reference voltage, and the control terminal is coupled to the first control signal; a second limiting circuit, coupling the second end of the second programmable fuse to the second reference voltage according to a second control signal, the second limiting circuit comprising: a second transistor having a first connection terminal, a second connection terminal, and a control terminal, wherein the first connection terminal is coupled to the second terminal of the first programmable fuse, the second connection terminal is coupled to the second reference voltage, and the control terminal is coupled to the second control signal; and The first transistor and the second transistor are native metal oxide semiconductor field effect transistors, and the first control signal and the second control signal are the second reference voltage.

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