Nonvolatile memory system using strap cells in source line pull-down circuit

Abstract

The present invention relates to a flash memory device that uses strap cells in a memory array of nonvolatile memory cells as source line pull-down circuits. In one embodiment, the strap cells are erase gate strap cells. In another embodiment, the strap cells are source line strap cells. In another embodiment, the strap cells are control gate strap cells. In another embodiment, the strap cells are word line strap cells.

Description

Technical Field

[0001] The present invention relates to a non-volatile memory device that utilizes existing strap cells in an array in a source line pull-down circuit. Background Art

[0002] Non-volatile memory cells are well known in the art. Figures 1 to 6 An example of a non-volatile memory cell known in the art is shown in .

[0003] Figure 1 A stacked-gate nonvolatile memory cell 110 is depicted. Each memory cell 110 includes a source region (also referred to as a source line terminal) 14 and a drain region 16 formed in a semiconductor substrate 12 with a channel region 18 therebetween. A floating gate 20 is formed over and insulated from (and controls the conductivity of) the channel region 18, and is formed over a portion of each of the drain region 16 and the source region 14. A control gate terminal 22 (here coupled to a word line) is disposed over and insulated from the floating gate 20. The floating gate 20 and the control gate terminal 22 are insulated from each other and from the substrate 12 by a gate oxide. A bit line terminal 24 is coupled to the drain region 16.

[0004] Programming is performed using hot electron injection from the channel 18 into the floating gate 20 in the channel region next to the drain region 16 .

[0005] Erasure is performed using Fowler-Nordheim electrons tunneling from the floating gate 20 to the substrate 12 .

[0006] Reading is performed by placing a positive read voltage across drain region 16 and control gate terminal 22 (which turns on channel region 18). If floating gate 20 is positively charged (i.e., electrons are erased), channel region 18 beneath floating gate 20 is also turned on, and current will flow through channel region 18, which is sensed as an erased state or a "1" state. If floating gate 20 is negatively charged (i.e., programmed with electrons), most or all of the channel region beneath floating gate 20 is turned off, and no current (or very little current) will flow through channel region 18, which is sensed as a programmed state or a "0" state.

[0007] Table 1 depicts typical voltage ranges that may be applied to the terminals of the memory cell 110 and substrate 12 to perform read, erase, and program operations:

[0008] Table 1: Figure 1 Operation of the stacked-gate nonvolatile memory cell 110

[0009] CG BL SL substrate Read 1 0-5V 0.1-2V 0V-2V 0V Read 2 0.5-2V 0V-2V 2-0.1V 0V Erase -8 to -10V / 0V FLT FLT 8-10V / 15-20V programming 8-12V 3-5V / 0V 0V / 3-5V 0V

[0010] "Read 1" is a read mode in which the cell current is output on the bit line. "Read 2" is a read mode in which the cell current is output on the source line terminal 14. In the program mode, the bit line terminal is set to VDD (typically 3-5V) and the source line terminal is set to 0V to inhibit programming of the cell, and the bit line terminal is set to 0V and the source line terminal is set to VDD (typically 3-5V) to program the cell.

[0011] Figure 2 A split-gate nonvolatile memory cell 210 is depicted. Each memory cell 210 includes a source region (source line terminal) 14 and a source region 16 formed in a semiconductor substrate 12 with a channel region 18 therebetween. A floating gate 20 is formed over and insulated from (and controls the electrical conductivity of) a first portion of the channel region 18, and is formed over a portion of the source region 14. A word line terminal 22 (which is typically coupled to a word line) has a first portion disposed over and insulated from (and controls the electrical conductivity of) a second portion of the channel region 18, and a second portion extending upward and over the floating gate 20. The floating gate 20 and word line terminal 22 are insulated from the substrate 12 by a gate oxide. A bit line terminal 24 is coupled to the drain region 16.

[0012] Memory cell 210 is erased (where electrons are removed from the floating gate) by placing a high positive voltage on wordline terminal 22 , which causes the electrons on floating gate 20 to tunnel through the intervening insulator via Fowler-Nordheim tunneling from floating gate 20 to wordline terminal 22 .

[0013] Memory cell 210 is programmed by placing a positive voltage on wordline terminal 22 and a positive voltage on source region 14 (where electrons are placed on the floating gate). Electron current will flow from drain region 16 to source region 14 (source line terminal). When electrons reach the gap between wordline terminal 22 and floating gate 20, they will accelerate and become excited (heated). Due to the electrostatic attraction from floating gate 20, some of the heated electrons will be injected through the gate oxide onto floating gate 20.

[0014] Memory cell 210 is read by placing a positive read voltage across drain region 16 and wordline terminal 22 (which turns on the portion of channel region 18 below the wordline terminal). If floating gate 20 is positively charged (i.e., electrons are erased), the portion of channel region 18 below floating gate 20 is also turned on, and current will flow through channel region 18, which is sensed as an erased state or a "1" state. If floating gate 20 is negatively charged (i.e., programmed by electrons), the portion of the channel region below floating gate 20 is mostly or completely turned off, and no current (or very little current) flows through channel region 18, which is sensed as a programmed state or a "0" state.

[0015] Table 2 depicts typical voltage ranges that may be applied to the terminals of the memory cell 210 for performing read, erase, and program operations:

[0016] Table 2: Figure 2 The operation of the nonvolatile memory unit 210

[0017] WL BL SL Read 1 0.5-3V 0.1-2V 0V Read 2 0.5-3V 0V-2V 2-0.1V Erase ～11-13V 0V 0V programming 1-2V 1-3μA 9-10V

[0018] “Read 1” is a read mode in which the cell current is output on the bit line. “Read 2” is a read mode in which the cell current is output on the source line terminal 14 .

[0019] Figure 3 A split gate non-volatile memory cell 310 is depicted. The memory cell 310 is similar to Figure 2 The memory cell 210 is configured such that a control gate (CG) terminal 28 is added. The control gate terminal 28 is biased at a high positive voltage (e.g., 10V) during programming, at a low voltage or negative voltage (e.g., 0V / -8V) during erasing, and at a low voltage or medium voltage (e.g., 0V / 2.5V) during reading. The other terminals are similar to Figure 2 That's biased.

[0020] Figure 4 A split-gate nonvolatile memory cell 410 is depicted. Memory cell 410 includes a source region (source line terminal) 14, a drain region 16, a floating gate 20 over a first portion of a channel region 18, a select gate 22 (typically coupled to a word line (WL)) over a second portion of the channel region 18, a control gate 28 over the floating gate 20, and an erase gate 30 over the source region 14. Here, all gates except the floating gate 20 are non-floating, meaning they are electrically connected or capable of being electrically connected to a voltage source. Programming is performed by heated electrons from the channel region 18 that inject themselves into the floating gate 20. Erasing is performed by electrons tunneling from the floating gate 20 to the erase gate 30.

[0021] Table 3 depicts typical voltage ranges that may be applied to the terminals of the memory cell 410 for performing read, erase, and program operations:

[0022] Table 3: Figure 4 Operation of the nonvolatile memory unit 410

[0023] WL / SG BL CG EG SL Read 1 0.5-2V 0.1-2V 0V-2.6V 0V-2.6V 0V Read 2 0.5-2V 0V-2V 0V-2.6V 0V-2.6V 2-0.1V Erase -0.5V / 0V 0V 0V / -8V 8-12V 0V programming 1V 1μA 8-11V 4.5-9V 4.5-5V

[0024] "Read 1" is a read mode in which the cell current is output on the bit line. "Read 2" is a read mode in which the cell current is output on the source line terminal.

[0025] Figure 5 A split gate non-volatile memory cell 510 is depicted. The memory cell 510 is similar to Figure 4 Memory cell 410, except that memory cell 510 does not have an erase gate EG terminal. Programming is performed by heated electrons from the channel region 18 injecting themselves into the floating gate 20. Erasing is performed by biasing the substrate 12 to a high voltage and biasing the control gate CG terminal 28 to a low or negative voltage, causing electrons to tunnel from the floating gate 20 to the channel region 18. Alternatively, erasing is performed by biasing the word line terminal 22 to a positive voltage and biasing the control gate terminal 28 to a negative voltage, causing electrons to tunnel from the floating gate 20 to the word line terminal 22. Programming and reading are similar to Figure 4 Like that.

[0026] Figure 6 A split gate non-volatile memory cell 610 is depicted. The memory cell 610 is connected to Figure 4 The memory cell 410 is the same as the memory cell 610 except that the memory cell 610 does not have a separate control gate terminal. Except that no control gate bias is applied, the erase operation (erasing by using the erase gate terminal) and the read operation are similar to Figure 4 The programming operation is also accomplished without a control gate bias, and as a result, a higher voltage must be applied to the source line terminal 14 during the programming operation to compensate for the lack of control gate bias.

[0027] Table 4 depicts typical voltage ranges that may be applied to the terminals of the memory cell 610 for performing read, erase, and program operations:

[0028] Table 4: Figure 6 Operation of the nonvolatile memory unit 610

[0029] WL / SG BL EG SL Read 1 0.5-2.2V 0.1-2V 0V-2.6V 0V Read 2 0.5-2.2V 0V-2V 0V-2.6V 2-0.1V Erase -0.5V / 0V 0V 11.5V 0V programming 1V 2-3μA 4.5V 7-9V

[0030] "Read 1" is a read mode in which the cell current is output on the bit line. "Read 2" is a read mode in which the cell current is output on the source line terminal.

[0031] Figures 1 to 6 Memory cells of the type shown in are typically arranged in rows and columns to form an array. Because each word line controls a row of memory cells and is coupled to the word line terminal 22 of each cell in the row, and the erase gate line (when present) is shared by pairs of rows of memory cells and is coupled to the erase gate terminal 30 of each cell in these pairs of rows, an erase operation is performed on entire rows or pairs of rows at a time. The source line is typically coupled to the source line terminals 14 of a row of memory cells or two adjacent rows of memory cells. The bit line is typically coupled to the bit line terminals 24 of a column of memory cells 24.

[0032] for Figures 1 to 6Each of the prior art memory cells, and as can be seen from the above table, it is often necessary to pull the source line to ground (ie, 0 volts), and to do so relatively quickly.

[0033] Figure 7 A typical prior art technique for achieving this is depicted. Memory system 700 includes memory cell 710, word line 722, control gate line 726, erase gate line 728, bit line 720, and source line 714. Memory cell 710 may be Figures 1 to 6 , i.e., memory cell 110, memory cell 210, memory cell 310, memory cell 410, memory cell 510, memory cell 610, or another type of memory cell. Source line 714 is coupled to a pull-down transistor 730, which here comprises a single NMOS transistor. When the gate of pull-down transistor 730 is activated, source line 714 is pulled down to ground. In a flash memory system, many pull-down circuits will be required, and depending on the capacitance of source line 714, more than one pull-down circuit may be required for each source line 714. Pull-down transistor 714 requires an operating voltage of approximately 0-1.2V for low-voltage operation and an operating voltage of 4-5-11.5V for high-voltage operation, as shown in Tables 1-4. This means that pull-down transistor 730 requires one or both of a high-voltage transistor type (e.g., an 11.5V transistor) or an IO transistor type (e.g., a 2.5V or 3V transistor), which takes up die space and increases the overall cost and complexity of the system. Where both types are present, they are typically connected to ground at one end and to a multiplexer at the other end which connects one of the transistors to the source line in response to a control signal. Additionally, the pull-down transistors can be subject to overvoltage and malfunction when the memory cell 710 is being programmed.

[0034] Applicant proposed improvements to memory system 700 in PCT Publication No. WO 2017 / 044251A1, entitled “Flash Memory System Using Dummy Memory Cell As Source Line Pull Down Circuit,” which is incorporated herein by reference. Figure 8 and Figure 9 Such a memory system is depicted in .

[0035] refer to Figure 8, a flash memory system 800 includes an exemplary memory cell 710 and an exemplary dummy memory cell 810. The dummy memory cell 810 has the same structure as the memory cell 710, except that the dummy memory cell 810 is not used to store data. The source line 714 of the memory cell 710 is coupled to the source line 814 of the dummy memory cell 810, which is typically the case if the memory cell 710 and the dummy memory cell 810 are in the same row within the array. The word line 722 is coupled to the word line 822, and the bit line 720 is shared between the memory cells 800 in a column.

[0036] In the example shown, memory unit 710 and virtual memory unit 810 follow Figure 4 It should be understood that the memory unit 710 and the virtual memory unit 810 can also follow Figure 3 Memory cell 310 or Figure 5 Memory cell 510 in (in which case erase gates 728 and 828 will not be present), Figure 6 memory cell 610 in (in which case control gates 726 and 826 would not be present), or Figure 1 Memory cell 110 or Figure 2 8. The design of the memory cell 210 in FIG. 2 (in this case, the erase gates 728 and 828 and the control gates 726 and 826 would not be present).

[0037] When memory cell 710 is in read mode or erase mode, source line 814 is coupled to ground through dummy memory cell 810 and dummy bit line 820, which is switchably coupled to ground, causing source line 714 and source line 814, as well as anything else electrically connected to bit line 820, to be pulled to ground. Dummy memory cell 810 needs to be erased before a read operation.

[0038] When the memory cell 710 is in programming mode, the dummy bit line 820 can be switchably coupled to an inhibit voltage (such as VDD). This places the dummy memory cell 810 in a program inhibit mode, which maintains the dummy memory cell 810 in an erased state. There can be multiple dummy memory cells 810 for each memory cell 710 to enhance the pull-down of the source line 714 to ground.

[0039] Figure 9A flash memory system 900 is depicted that includes an exemplary memory cell 920 and an exemplary dummy memory cell circuit 910. Dummy memory cell circuit 910 includes a plurality of dummy memory cells coupled to each other. In this example, source line 930 (also labeled SL0) and source line 940 (also labeled SL1) from memory cell 920 are coupled to source line terminals of dummy memory cell circuit 910. In this example, source line 930SL0 and source line 940SL1 are connected together.

[0040] Thus, source lines for an entire sector (or sectors) of memory cells 920 may be coupled together to source lines of a dummy memory cell circuit 910 that includes dummy memory cells from the same row of cells that are part of that sector (or sectors).

[0041] When memory cell 920 is in read mode or erase mode, dummy memory cell circuit 910 is coupled to ground via a dummy bit line. The dummy memory cell must be erased before a read operation. The erased dummy memory cell, when coupled to ground via the dummy bit line, pulls source lines 930 and 940 to ground.

[0042] When the memory cell 920 is in programming mode, the dummy bit line of the dummy memory cell circuit 910 is coupled to an inhibit voltage (such as VDD). This puts the dummy memory cells of the dummy memory cell circuit 910 into a program inhibit mode, which keeps the dummy memory cells in an erased state.

[0043] Optionally, during read or standby mode, word line 950 (also labeled WL_rdcellpdwn, which is separate from the word line of memory cell 920) and control gate 960 (also labeled CG_rdcellpdwn, which is separate from the control gate of memory cell 920) are biased at a voltage different from the voltage of memory cell 920 (such as VDD or higher) to minimize current drop across the dummy memory cells of dummy memory cell circuit 910.

[0044] and Figure 7 Compared with the existing technology system, Figure 8 and Figure 9This system offers numerous benefits. First, the source line pull-down current is distributed across many dummy memory cells and metal paths, resulting in lower electromagnetic interference and fewer decoded interconnects. Second, compared to prior art pull-down high-voltage transistors, the dummy memory cells experience lower power consumption. Third, compared to high-voltage transistor pull-down solutions, this embodiment requires less die space. Fourth, the biasing and logic control of this embodiment are simpler than prior art pull-down transistors. This results in fewer overvoltages and malfunctions during programming mode.

[0045] However, Figure 8 and Figure 9 The implementation of dummy memory cells requires additional die space for the dummy memory cell circuits, which increases die size, complexity, and manufacturing cost.

[0046] Prior art memory systems also contain strap cells. Figure 10A 、 Figure 10B 、 Figure 10C and Figure 10D Memory systems 1000-1, 1000-2, 1000-3, and 1000-4 of the prior art are depicted, each including an exemplary memory cell 1010 and an exemplary strap cell 1020 (i.e., exemplary strap cells 1020-1, 1020-2, 1020-3, and 1020-4). A strap cell 1020 is part of a strap row or strap column, which typically exists in an array as an area where physical connections can be made between one or more of the erase gate line, source line, control gate line, and word line and another structure external to the array, such as a driver, low-voltage decoder, or high-voltage decoder. A strap cell 1020 contains some, but not always all, of the same components as a memory cell 1010.

[0047] exist Figure 10A 、 Figure 10B 、 Figure 10C and Figure 10D In each of the examples shown in FIG, the memory cell 1010 includes a first bit line terminal 1011, a first word line terminal 1012, a first control gate terminal 1013, a first erase gate terminal 1014, and a first source line terminal 1015. If the memory cell 1010 follows Figure 4 This will be the case for the design of memory cell 410 in FIG. 1. The strap cell 1020 can be one of four different types of strap cells: an erase gate strap cell 1020-1 (e.g., Figure 10A ), source line strap unit 1020-2 (as shown in Figure 10B ), control gate strip unit 1020-3 (as shown in Figure 10C ) and word line strap unit 1020-4 (as shown in Figure 10D ).

[0048] 1. Erase gate strip cell

[0049] refer to Figure 10A , strap cell 1020 may be an erase gate strap cell 1020-1, which includes a second bit line terminal 1021, a second word line terminal 1022, a second control gate terminal 1023, a second erase gate terminal 1024, a second source line terminal 1025, and an erase gate contact 1034, wherein the erase gate contact 1034 connects the second erase gate terminal 1024 to a structure (such as a low voltage or high voltage decoder) external to the array containing the memory cells 1010 and strap cell 1020-1, which drives the erase gate line 1104 connected to the second erase gate terminal 1024 as needed during programming, erasing, and reading operations. The second erase gate terminal 1024 is further connected to the erase gate line 1104 because it is in the same row as the memory cells 1010. The memory cell 1010 includes a first word line terminal 1012 , a first control gate terminal 1013 , a first erase gate terminal 1014 , a first source line terminal 1015 , and a first bit line terminal 1011 .

[0050] Figure 11A An example of an array containing erase gate strap cells 1020-1 is depicted. Array 1100-1 includes bit lines 1101, word lines 1102a and 1102b, control gate lines 1103a and 1103b, erase gate lines 1104, and source lines 1105. Source lines 1105 are located below erase gate lines 1104 and therefore appear to be the same line from this view, even though they are separated in three dimensions.

[0051] Depicted is an exemplary memory cell 1010. A word line terminal of cell 1010 (such as first word line terminal 1012 in FIG. 10 ) is coupled to word line 1102 a, a control gate terminal of memory cell 1010 (such as first control gate terminal 1013 in FIG. 10 ) is coupled to control gate line 1103 a, an erase gate terminal of cell 1010 (such as first erase gate terminal 1014 in FIG. 10 ) is coupled to erase gate line 1104, and a source line terminal of memory cell 1010 (such as first source line terminal 1015 in FIG. 10 ) is coupled to source line 1105.

[0052] The bit lines 1101 are coupled to structures external to the array 1100 through bit line contacts 1106 located at either end of each bit line.

[0053] Array 1100 also includes erase gate straps 1110, which include exemplary erase gate strap cells 1020-1. Erase gate straps 1110 are coupled to erase gate lines 1104 because the erase gate lines are in the same row, and therefore erase gate lines 1104 and erase gate terminals 1014 of memory cells 1010 are coupled to erase gate contacts 1034. Strap cells 1020-1 and erase gate straps 1110 are not connected to any bit line contacts and, therefore, are not connected to their corresponding bit lines in structures external to array 1100. As a result, strap cells 1020-1 and erase gate straps 1110 do not have a pull-down function as in the prior art.

[0054] 2. Source line strip unit

[0055] refer to Figure 10B , strap cell 1020 may be source line strap cell 1020-2. Source line strap cell 1020-2 includes a second bit line terminal 1021, a second word line terminal 1022, a second control gate terminal 1023, a second source line terminal 1025, and a source line contact 1035, and does not include an erase gate terminal (to provide room for source line contact 1035). Source line contact 1035 is connected to a structure external to the array containing memory cells 1010 and strap cell 1020-2 (such as a low voltage or high voltage decoder) that drives the source line connected to second source line terminal 1025 as needed during programming, erasing, and reading operations. Memory cell 1010 includes a first word line terminal 1012, a first control gate terminal 1013, a first erase gate terminal 1014, a first source line terminal 1015, and a first bit line terminal 1011.

[0056] Figure 11B An example of an array containing source line strap cells 1020-2 is depicted. Array 1100-2-2 is similar to Figure 11A Array 1100-1, except that erase gate straps 1110 are replaced by source line straps 1120 including exemplary source line strap cells 1020-2.

[0057] Source line strap 1120 is coupled to source line 1105 because the source lines are in the same row, and therefore source line 1105 and source line terminal 1015 of memory cell 1010 are coupled to source line contact 1035. Source line strap cell 1020-2 and source line strap 1120 are not connected to any bit line contacts and therefore have no structure connected to the outside of array 1100-2 via their associated bit lines. As a result, in the prior art, source line strap cell 1020-2 and source line strap 1120 do not perform a pull-down function.

[0058] 3. Control gate strip unit

[0059] refer to Figure 10C , strap cell 1020 may be control gate strap cell 1020-3. Control gate strap cell 1020-3 includes a second bit line terminal 1021, a second word line terminal 1022, a second control gate terminal 1023, a second source line terminal 1025, a control gate contact 1033, and a source line contact 1035, and does not include an erase gate terminal (to provide space for source line contact 1035), wherein control gate contact 1033 and source line contact 1035 are connected to a structure (such as a low voltage or high voltage decoder) external to the array containing memory cells 1010 and strap cell 1020-3, which drives control gate line 1103a and source line 1105 connected to second control gate terminal 1023 and source line terminal 1025, respectively, as needed during programming, erasing, and reading operations. The memory cell 1010 includes a first word line terminal 1012 , a first control gate terminal 1013 , a first erase gate terminal 1014 , a first source line terminal 1015 , and a first bit line terminal 1011 .

[0060] Figure 11C Depicts an example of an array containing control gate line strap cells 1130. Arrays 1100-3 are similar to Figure 11A and Figure 11B Arrays 1100-1 and 1100-2 in FIG. 1 and 2 are shown in FIG. 1 , except that the erase gate strip 1110 or source line strip 1120 is replaced by a control gate line strip 1130 including an exemplary control gate stripe unit 1020-3. The control gate line strips 1130, and in particular the control gate stripe unit 1020-3 (one of which is extracted), are coupled to control gate lines 1103a and 1103b, respectively, because they are in the same row, and thus the control gate lines 1103a, 1103b and the control gate terminal 1013 of the memory cell 1010 are coupled to control gate line contacts 1033a and 1033b, respectively. The source line 1105 is coupled to the second source line terminal 1025 because they are in the same row, and thus the source line 1105 is coupled to the source line contact 1035. Control gate strap unit 1020-3 and control gate strap 1130 are not connected to any bit line contacts and therefore have no structure connected to the outside of array 1100-3 via their associated bit lines. As a result, control gate strap unit 1020-3 and control gate strap 1130 do not perform a pull-down function in the prior art.

[0061] 4. Word line strap unit

[0062] refer to Figure 10D, strap cell 1020 may be word line strap cell 1020-4. Word line strap cell 1020-4 includes a second bit line terminal 1021, a second word line terminal 1022, a second control gate terminal 1023, a second source line terminal 1025, a word line contact 1032, and a source line contact 1035, and does not include an erase gate terminal (to provide space for source line contact 1035), wherein word line contact 1032 and source line contact 1035 are connected to a structure (such as a low voltage or high voltage decoder) external to the array including memory cells 1010 and strap cell 1020-4, which drives the word line and source line connected to word line contact 1032 and source line contact 1035, respectively, as needed during programming, erasing, and reading operations. The memory cell 1010 includes a first word line terminal 1012 , a first control gate terminal 1013 , a first erase gate terminal 1014 , a first source line terminal 1015 , and a first bit line terminal 1011 .

[0063] Figure 11D An example of an array containing word line strap cells 1020-4 is depicted. Arrays 1100-4 are similar to Figure 11A Array 1100-1, Figure 11B Array 1100-2 and Figure 11C Array 1100 - 3 of FIG. 1 , except that erase gate strap 1110 , source line strap 1120 , or control gate line strap 1130 are each replaced by word line strap 1140 including exemplary word line strap cell 1020 - 4 .

[0064] Wordline strap 1140, specifically wordline strap cell 1020-4 (one of which is pulled out), is coupled to wordlines 1102a and 1102b, respectively, because they are in the same row. Therefore, wordlines 1102a and 1102b, as well as wordline terminal 1012 of memory cell 1010, are coupled to wordline contacts 1032a and 1032b, respectively. Source line 1105 is coupled to second source line terminal 1025 because they are in the same row. Therefore, source line 1105 is coupled to source line contact 1035. Strap cell 1020-4 and wordline strap 1140 are not connected to any bitline contacts and, therefore, have no connection to structures external to array 1100-4 via their associated bitlines. Therefore, wordline strap cell 1020-4 and wordline strap 1140 do not perform a pull-down function as in the prior art.

[0065] Reference again 10A to 10D and 11A to 11D, and as noted, because memory cell 1010 and strap cell 1020 are located in the same row, first source line terminal 1015 of memory cell 1010 is coupled to the same source line as second source line terminal 1025 of strap cell 1020, first word line terminal 1012 of memory cell 1010 is coupled to the same word line as second word line terminal 1022 of strap cell 1020, first control gate terminal 1013 of memory cell 1010 is coupled to the same control gate line as second control gate terminal 1023 of strap cell 1020, and first erase gate terminal 1014 of memory cell 1010 is coupled to the same erase gate line as second erase gate terminal 1024 (if present) of strap cell 1020.

[0066] exist 10A to 10D and 11A to 11D In the example shown in FIG, the memory unit 1010 and the strap unit 1020 follow Figure 4 The design of the memory unit 410 in FIG. 4 is different from the design of the stripe units 1020-2, 1020-3 and 1030-4 described above. The memory unit 1010 and the stripe unit 1020 may also follow Figure 3 Memory cell 310 or Figure 5 Memory cell 510 in (in this case, the first erase gate terminal 1014 and the second erase gate terminal 1024 will not exist), Figure 6 Memory cell 610 in (in which case the first control gate terminal 1013 and the second control gate terminal 1023 will not exist), or Figure 1 Memory cell 110 or Figure 2 The design of the memory cell 210 in FIG. 1 (in this case, the first and second erase gate terminals 1014 and 1024 and the first and second control gate terminals 1013 and 1023 will not exist) is shown.

[0067] Therefore, a strap cell is a cell that is not used to store data and includes at least one of an erase gate contact, a control gate contact, a source line contact, and a word line contact connected to a structure external to the array including the memory cells (such as a low voltage decoder or a high voltage decoder). Each of the erase gate contact, the control gate contact, the source line contact, and the word line contact is a vertical contact connected to a metal line that is connected to a structure external to the array including the memory cells (such as a low voltage decoder or a high voltage decoder).

[0068] What is needed is a new technique for pulling the source line to ground in a flash memory system that utilizes a technique better than that disclosed by applicants and referenced above. Figures 8 and 9 The previous designs discussed had less die space. Summary of the Invention

[0069] In the embodiments described below, a flash memory device utilizes existing strap cells in the array in source line pull-down circuits.

[0070] In one embodiment, a memory system includes: a memory cell including a first bit line terminal and a first source line terminal; a strap cell including a second bit line terminal and a second source line terminal; a source line coupled to the first source line terminal and the second source line terminal; and a pull-down circuit that selectively couples the second bit line terminal to ground when the memory cell is being read or erased, and selectively couples the second bit line terminal to a voltage source when the memory cell is being programmed.

[0071] In some embodiments, the memory cell includes a first word line terminal and the strap cell includes a second word line terminal. In some embodiments, the memory cell includes a first control gate terminal and the strap cell includes a second control gate terminal. In some embodiments, the memory cell includes a first erase gate terminal and the strap cell includes a second erase gate terminal.

[0072] In some embodiments, the strap cell is a source line strap cell, wherein the second source line terminal is connected to the source line contact. In some embodiments, the strap cell is a word line strap cell, wherein the second word line terminal is connected to the word line contact. In some embodiments, the strap cell is a control gate strap cell, wherein the second control line terminal is connected to the control gate contact. In some embodiments, the strap cell is an erase gate strap cell, wherein the second erase gate terminal is connected to the erase gate contact. BRIEF DESCRIPTION OF THE DRAWINGS

[0073] Figure 1 is a cross-sectional view of a prior art stacked-gate nonvolatile memory cell to which the present invention can be applied.

[0074] Figure 2 is a cross-sectional view of a prior art split-gate non-volatile memory cell to which the present invention may be applied.

[0075] Figure 3 is a cross-sectional view of a prior art split-gate non-volatile memory cell to which the present invention may be applied.

[0076] Figure 4 is a cross-sectional view of a prior art split-gate non-volatile memory cell to which the present invention may be applied.

[0077] Figure 5 is a cross-sectional view of a prior art split-gate non-volatile memory cell to which the present invention may be applied.

[0078] Figure 6 is a cross-sectional view of a prior art split-gate non-volatile memory cell to which the present invention may be applied.

[0079] Figure 7 A prior art memory cell having a pull-down transistor coupled to a source line is depicted.

[0080] Figure 8 A design previously disclosed by the applicant is depicted in which a dummy memory cell is used as a pull-down circuit for the source line.

[0081] Figure 9 Another design previously disclosed by the applicant is depicted in which multiple dummy memory cells are used as pull-down circuits for the source line.

[0082] Figure 10A A prior art memory cell and erase gate strap cell are depicted.

[0083] Figure 10B A prior art memory cell and source line strap cell are depicted.

[0084] Figure 10C A prior art memory cell and control gate strap cell are depicted.

[0085] Figure 10D Prior art memory cells and word line strap cells are described.

[0086] Figure 11A A prior art memory array including erase gate straps is depicted.

[0087] Figure 11B A prior art memory array including source line straps is depicted.

[0088] Figure 11C A prior art memory array including control gate straps is depicted.

[0089] Figure 11D A prior art memory array including word line straps is depicted.

[0090] Figure 12 An embodiment with a strap cell used as a source line pull-down circuit is depicted.

[0091] Figure 13 Depicted is a layout diagram of an embodiment of a memory array including an erase gate strap for use in a source line pull-down circuit.

[0092] Figure 14 A layout diagram of another embodiment of a memory array including an erase gate strap for use in a source line pull-down circuit is depicted.

[0093] Figure 15A layout diagram of another embodiment of a memory array including an erase gate strap for use in a source line pull-down circuit is depicted.

[0094] Figure 16 Depicted is a layout diagram of an embodiment of a memory array including source line straps for use in source line pull-down circuits.

[0095] Figure 17 Depicted is a layout diagram of an embodiment of a memory array including control gate straps for use in source line pull-down circuits.

[0096] Figure 18 Depicted are layout diagrams of embodiments of a memory array including word line straps for use in source line pull-down circuits. DETAILED DESCRIPTION

[0097] Figure 12 An embodiment of a strap cell with a pull-down circuit used as a source line is depicted. The memory system 1200 includes a memory cell 1010 that includes the same 10A to 10D The memory cell 1010 has the same components as those described above, in particular, the memory cell 1010 includes a first word line terminal 1012, a first control gate terminal 1013, a first erase gate terminal 1014, a first source line terminal 1015, and a first bit line terminal 1011. The memory system 1200 also includes a strap cell 1020, which may be a strap cell previously described with reference to FIG. 10A to 10D and 11A to 11D Any of the described strip units 1020-1, 1020-2, 1020-3, and 1020-4.

[0098] Unlike the prior art, the second bit line terminal 1021 of the strap cell 1020 is connected to a pull-down circuit contact 1201 (which may include, for example, a via between layers), which in turn connects the outside of the memory array to a pull-down circuit 1210. The pull-down circuit 1210 includes a switch 1211 that selectively connects to ground or a voltage source (such as VDD) in response to a control signal.

[0099] When the memory cell 1010 is in a read mode or an erase mode, the first source line terminal 1015 is coupled to the source line 1105, which is coupled to the strap cell 1020 and couples the pull-down circuit 1210 to ground. Thus, the first source line terminal 1015, the source line 1105, and the second source line terminal 1025 are pulled down to ground via the strap cell 1020. Optionally, more than one strap cell 1020 may be coupled to the first source line terminal 1015 to strengthen the pull-down of the first source line terminal 1015 and the source line 1105 to ground, so that the first source line terminal 1015 and the source line 1105 are pulled to ground more quickly.

[0100] When the memory cell 1010 is in programming mode, the second bit line terminal 1021 is coupled to an inhibit voltage source (such as VDD) through a switch 1211 in the pull-down circuit 1210. This places the strap cell 1020 in a program inhibit mode, which keeps the strap cell 1020 in an erased state even while the memory cell 1010 is being programmed.

[0101] Strap cell 1020 is generated in a neutral state in which it conducts current (equivalent to an erased state). When memory cell 1010 is erased, strap cell 1020 similarly experiences an erase potential and thus remains in the erased state, or alternatively, is not erased and remains in a neutral state in which current flows because strap cell 1020 experiences a program inhibit potential in response to pull-down circuit 1210 when memory cell 1010 is programmed.

[0102] Figures 13 to 18 Exemplary layouts for embodiments using four types of strap cells (erase gate strap cell 1020-1, source line strap cell 1020-2, control gate strap cell 1020-3, and word line strap cell 1020-4) for strap cell 1020 are depicted, respectively.

[0103] Figure 13 An array 1300 is depicted that is similar to array 1100-1, except that the bit line terminals 1021 in the erase gate straps 1310 (not shown, but in the example embodiment) are removed. 10A to 10D ) are connected to pull-down circuit contacts 1201 on both ends of the bit line, which in turn are connected to corresponding pull-down circuits 1210 (not shown here, but in FIG. Figure 12 The cell 1010 and the erase gate strap cell 1020-1 share a source line 1105, and the source line 1105 is pulled down to ground through the pull-down circuit contact 1201 and the corresponding pull-down circuit 1210 during the read mode or the erase mode, and is pulled to VDD through the pull-down circuit contact 1201 in response to the pull-down circuit 1210 during the programming mode, as previously described with reference to FIG. Figure 12 discussed.

[0104] Figure 14Array 1400 is depicted, which is similar to array 1300, except that erase gate straps 1410 are wider than erase gate straps 1310, and in this example, erase gate strap cell 1020-2 is twice as wide in array 1400 as in array 1300. This increases the pull-down capability. Cell 1010 and erase gate strap cell 1020-2 share source line 1105, and source line 1105 is pulled down to ground during read mode or erase mode through pull-down circuit contact 1201 relative to pull-down circuit 1210, and is pulled to VDD during programming mode through pull-down circuit contact 1201 in response to pull-down circuit 1210, as previously described with reference to FIG. Figure 12 discussed.

[0105] Figure 15 Depicts something like Figure 14 Array 1500 is similar to array 1400, except that (1) erase gate strap 1410 has been replaced by erase gate strap 1510, which includes two columns of erase gate strap cells, each column of erase gate strap cells being similar in size to a column of memory cells, (2) there are two erase gate strap cells 1020-2 instead of one, and (3) erase gate strap 1510 has four pull-down circuit contacts 1201, each connected to a corresponding bit line terminal, instead of two. Array 1500 may be easier to manufacture than array 1400 due to the relative uniformity between the columns of normal cells and the two columns of erase gate strap cells.

[0106] Figure 16 An array 1600 including source line straps 1610 is depicted. Array 1600 is similar to Figure 11B 1100-2, except that the bit line terminals in the source line strap 1610 are connected to pull-down circuit contacts 1201 on both ends of the bit line, which in turn are connected to switchable contacts of corresponding pull-down circuits 1210 (not shown here, but in FIG. Figure 12 10). Cell 1010 and source line strap cell 1020-2 share source line 1105, and shared source line 1105 is pulled down to ground through pull-down circuit contact 1201 in response to pull-down circuit 1210 during read or erase mode, and is pulled to VDD through pull-down circuit contact 1201 in response to pull-down circuit 1210 during program mode, as previously described with reference to FIG. Figure 12 discussed.

[0107] Figure 17 An array 1700 including control grid line strips 1710 is depicted. Array 1700 is similar to Figure 11C 1100-3, except that the bit line terminals in the control gate line strip 1710 are connected to the pull-down circuit contacts 1201 on both ends of the bit line, which are in turn connected to the switchable contacts of the corresponding pull-down circuit 1210 (not shown here, but Figure 12 ). Cell 1010 and control gate strap cell 1020-3 share source line 1105, and source line 1105 is pulled down to ground through pull-down circuit contact 1201 relative to pull-down circuit 1210 during read mode or erase mode, and is pulled to VDD through pull-down circuit contact 1201 in response to pull-down circuit 1210 during programming mode, as previously described with reference to FIG. Figure 12 discussed.

[0108] Figure 18 An array 1800 including word line straps 1810 is depicted. Array 1800 is similar to Figure 11D 1100-4, except that the bit line terminals in the word line strap 1810 are respectively connected to the pull-down circuit contacts 1201 on both ends of the bit line, which are in turn connected to the switchable contacts of the corresponding pull-down circuit 1210 (not shown here, but Figure 12 ). Cell 1010 and word line strap cell 1020-4 share source line 1105, and source line 1105 is pulled down to ground through pull-down circuit contact 1201 relative to pull-down circuit 1210 during read mode or erase mode, and is pulled to VDD through pull-down circuit contact 1201 in response to pull-down circuit 1210 during programming mode, as previously described with reference to FIG. Figure 12 discussed.

[0109] and Figure 8 and Figure 9 Compared to prior art systems, the above embodiments utilize less die space, which is a significant improvement that will reduce manufacturing complexity and cost.

[0110] It should be noted that, as used herein, the terms "above" and "on" both inclusively include "directly on" (no intervening material, element, or space between the two) and "indirectly on" (intervening material, element, or space between the two). Similarly, the term "adjacent" includes "directly adjacent" (no intervening material, element, or space between the two) and "indirectly adjacent" (intervening material, element, or space between the two), and "coupled" includes "directly coupled to" (no intervening material or element electrically connecting the elements together) and "indirectly coupled to" (intervening material or element electrically connecting the elements together). For example, forming an element "above a substrate" may include directly forming the element on the substrate without an intervening material / element therebetween, as well as indirectly forming the element on the substrate with one or more intervening materials / elements therebetween.

Claims

1. A memory system comprising: a memory cell comprising a first bit line terminal and a first source line terminal; a first bit line coupled to the first bit line terminal; a strap unit including a second bit line terminal and a second source line terminal; a first pull-down circuit contact; a second pull-down circuit contact; a second bit line coupled to the second bit line terminal, the first pull-down circuit contact, and the second pull-down circuit contact, wherein the first pull-down circuit contact is at one end of the second bit line and the second pull-down circuit contact is at an opposite end of the second bit line; a source line coupled to the first source line terminal and the second source line terminal; and A pull-down circuit is coupled to the first pull-down circuit contact and the second pull-down circuit contact, the pull-down circuit selectively coupling the second bit line terminal to ground when the memory cell is being read or erased, and selectively coupling the second bit line terminal to a voltage source when the memory cell is being programmed. 2 . The system of claim 1 , wherein the memory cell comprises a first wordline terminal and the strap cell comprises a second wordline terminal. 3 . The system of claim 2 , wherein the memory cell comprises a first control gate terminal and the strap cell comprises a second control gate terminal. 4 . The system of claim 3 , wherein the memory cell comprises a first erase gate terminal and the strap cell comprises a second erase gate terminal. 5 . The system of claim 4 , wherein the strap cell is a source line strap cell, wherein the second source line terminal is connected to a source line contact. 6 . The system of claim 4 , wherein the strap cell is a wordline strap cell, wherein the second wordline terminal is connected to a wordline contact.

7. The system of claim 4, wherein the strap cell is a control gate strap cell, wherein the second control gate terminal is connected to a control gate contact.

8. The system of claim 4, wherein the strap cell is an erase gate strap cell, wherein the second erase gate terminal is connected to an erase gate contact.

9. The system of claim 3, wherein the strap cell is a source line strap cell, wherein the second source line terminal is connected to a source line contact.

10. The system of claim 3, wherein the strap cell is a wordline strap cell, wherein the second wordline terminal is connected to a wordline contact.

11. The system of claim 3, wherein the strap cell is a control gate strap cell, wherein the second control gate terminal is connected to a control gate contact.

12. The system of claim 2, wherein the strap cell is a source line strap cell, wherein the second source line terminal is connected to a source line contact.

13. The system of claim 2, wherein the strap cell is a wordline strap cell, wherein the second wordline terminal is connected to a wordline contact.

14. The system of claim 1, wherein the strap cell is a source line strap cell, wherein the second source line terminal is connected to a source line contact.

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