Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, the method comprising: providing a substrate, the substrate comprising a core region for forming a core device; forming a dummy gate on the substrate; forming source-drain doping regions in the substrate on both sides of the dummy gate; forming an interlayer dielectric layer covering the source-drain doping regions on both sides of the dummy gate; removing the dummy gate and forming a gate opening in the interlayer dielectric layer; ion doping the interlayer dielectric layer in the core region, suitable for improving the etching resistance of the interlayer dielectric layer in the core region; after forming the gate opening and after ion doping, forming a gate filling the gate opening. The embodiments of the present invention are conducive to improving the production yield and the performance of semiconductor structures.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] In semiconductor manufacturing, with the development trend of ultra-large-scale integrated circuits, the feature size of integrated circuits continues to decrease. In order to adapt to smaller feature sizes, the channel length of metal-oxide-semiconductor field-effect transistors (MOSFETs) is also shortened accordingly. However, as the channel length of the device shortens, the distance between the source and drain of the device also shortens, so the control ability of the gate structure over the channel becomes worse, and the difficulty of pinching off the channel by the gate voltage becomes increasingly greater, making subthreshold leakage, the so-called short-channel effects (SCE), more likely to occur.

[0003] Therefore, in order to reduce the impact of the short channel effect, semiconductor processes have gradually begun to transition from planar MOSFETs to three-dimensional transistors with higher efficiency, such as fin field effect transistors (FinFETs). In FinFETs, the gate structure can control the ultra-thin body (fin) from at least two sides. Compared with planar MOSFETs, the gate structure has a stronger control over the channel and can effectively suppress the short channel effect; and FinFETs have better compatibility with existing integrated circuit manufacturing than other devices.

[0004] In addition, in the field of semiconductor integrated circuit devices, as the size of transistors continues to shrink, high-K metal gate (HKMG) technology has gradually been widely used. At present, the process of forming HKMG structure transistors can be divided into the gate-first process and the gate-last process. Among them, the gate-last process usually forms the metal gate after the source and drain doping regions are formed and the subsequent high-temperature annealing process is completed, and generally before the metal gate is formed, a dummy gate is formed first, and then the dummy gate is removed to form a metal gate. Summary of the invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which are beneficial to improving the production yield and the performance of the semiconductor structure.

[0006] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a core area for forming a core device; forming a dummy gate on the substrate; forming source-drain doped areas in the substrate on both sides of the dummy gate; forming an interlayer dielectric layer covering the source-drain doped areas on both sides of the dummy gate; removing the dummy gate and forming a gate opening in the interlayer dielectric layer; ion doping the interlayer dielectric layer in the core area to improve the etching resistance of the interlayer dielectric layer in the core area; after forming the gate opening and after ion doping, forming a gate filling the gate opening.

[0007] Correspondingly, an embodiment of the present invention also provides a semiconductor structure, comprising: a substrate, the substrate comprising a core region for forming a core device; a gate opening located on the substrate; a source-drain doped region located in the substrate on both sides of the gate opening; an interlayer dielectric layer located on both sides of the gate opening and covering the source-drain doped region, wherein the interlayer dielectric layer in the core region is doped with ions, and the ions are suitable for improving the etching resistance of the interlayer dielectric layer in the core region.

[0008] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0009] In the method for forming a semiconductor structure provided by an embodiment of the present invention, ion doping is performed on the interlayer dielectric layer in the core area, which is suitable for improving the etching resistance of the interlayer dielectric layer in the core area. In the semiconductor field, subsequent steps generally include the step of performing an etching or planarization process, for example, removing the gate oxide layer at the bottom of the gate opening in the core area. In the embodiment of the present invention, the ion doping is performed to improve the etching resistance of the interlayer dielectric layer in the core area, which is beneficial to reducing the probability of the interlayer dielectric layer in the core area being mistakenly etched in the subsequent etching step or planarization process, thereby facilitating improving the height consistency of the interlayer dielectric layer in the core area and reducing the probability of a depression problem on the top surface of the interlayer dielectric layer; moreover, the process of forming the gate generally includes the steps of forming a gate material layer filling the gate opening on the interlayer dielectric layer, and removing the gate material layer higher than the interlayer dielectric layer by a planarization process. The top surface of the interlayer dielectric layer has a high height consistency, which correspondingly improves the height consistency of the gate, and the probability of a depression problem on the top surface of the interlayer dielectric layer is low, which is beneficial to reducing the probability of gate material residue on the top surface of the interlayer dielectric layer, which is beneficial to improving the performance of the core device, and further beneficial to improving the production yield and the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figures 1 to 4 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure;

[0011] Figures 5 to 15is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention;

[0012] Fig.16 It is a schematic structural diagram corresponding to each step in another embodiment of the method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0013] The devices currently formed still have the problem of poor performance and low production yield. The reasons for the poor device performance and low production yield are now analyzed in combination with a method for forming a semiconductor structure.

[0014] refer to Figures 1 to 4 , showing a structural schematic diagram corresponding to each step in a method for forming a semiconductor structure.

[0015] refer to Figure 1 , providing a substrate 1, including a core area i for forming a core device, and a peripheral area ii for forming an input / output device; forming a dummy gate structure 2 on the substrate 1, the dummy gate structure 2 including a gate oxide layer 21 and a dummy gate layer 22 located on the gate oxide layer 21; forming source and drain doped regions (not shown) in the substrate 1 on both sides of the dummy gate structure 2; and forming an interlayer dielectric layer 3 covering the source and drain doped regions on the substrate 1.

[0016] refer to Figure 2 , the dummy gate layer 22 is removed, and a gate opening 4 is formed in the interlayer dielectric layer 3 , wherein the bottom of the gate opening 4 exposes the gate oxide layer 21 .

[0017] refer to Figure 3 , remove the gate oxide layer 21 at the bottom of the gate opening 4 of the core region i.

[0018] refer to Figure 4 After removing the gate oxide layer 21 at the bottom of the gate opening 4 in the core region i, a gate 5 filling the gate opening 4 is formed.

[0019] The inventors found that the device formed by the above method has poor performance and low production yield. Specifically, the height consistency of the gate 5 is poor, and the probability of gate material residue on the top surface of the interlayer dielectric layer 3 is high, which easily reduces the production yield.

[0020] Through further research by the inventors, it was found that the reason for the above-mentioned problem is that in the semiconductor field, the material of the interlayer dielectric layer 3 is usually the same as the material of the gate oxide layer 21, and the material of the interlayer dielectric layer 3 is usually silicon oxide. In the above-mentioned formation method, in the step of removing the gate oxide layer 21 at the bottom of the gate opening 4 of the core area i, the top surface of the interlayer dielectric layer 3 of the core area i is also easily etched by mistake, which easily leads to poor consistency of the top surface height of the interlayer dielectric layer 3 of the core area i, and also easily leads to the problem of depression of the top surface of the interlayer dielectric layer 3 of the core area i, and the subsequent formation The process of forming the gate 5 generally includes the steps of forming a gate material layer filling the gate opening 4 on the interlayer dielectric layer 3, and removing the gate material layer above the interlayer dielectric layer 3 by a chemical mechanical polishing process, which easily leads to poor height consistency of the gate 5. Moreover, the gate material layer located in the depression on the top surface of the interlayer dielectric layer 3 is difficult to be polished and removed by the chemical mechanical polishing process, and thus it is easy to produce gate material residue on the interlayer dielectric layer 3 with the depression on the top surface, which easily reduces the yield of the semiconductor process and leads to poor performance of the formed semiconductor structure, especially poor performance of the core device.

[0021] In order to solve the technical problem, in the method for forming a semiconductor structure provided by an embodiment of the present invention, ion doping is performed on the interlayer dielectric layer of the core area, which is suitable for improving the etching resistance of the interlayer dielectric layer of the core area. In the semiconductor field, the subsequent steps usually also include the steps of performing etching or planarization processes, such as: removing the gate oxide layer at the bottom of the gate opening of the core area, etc. The embodiment of the present invention improves the etching resistance of the interlayer dielectric layer of the core area by performing ion doping, which is beneficial to reducing the probability of the interlayer dielectric layer of the core area being mistakenly etched in the subsequent etching steps or planarization processes, thereby facilitating the core area to improve the interlayer dielectric The height consistency of the layer is improved, and the probability of the top surface of the interlayer dielectric layer being depressed is reduced; moreover, the process of forming the gate generally includes the steps of forming a gate material layer filling the gate opening on the interlayer dielectric layer, and removing the gate material layer higher than the interlayer dielectric layer by a planarization process. The top surface height consistency of the interlayer dielectric layer is high, which correspondingly improves the height consistency of the gate, and the probability of the top surface of the interlayer dielectric layer being depressed is low, which is correspondingly beneficial to reducing the probability of gate material residue on the top surface of the interlayer dielectric layer, which is beneficial to improving the performance of the core device, and further beneficial to improving the production yield and the performance of the semiconductor structure.

[0022] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0023] Figures 5 to 15 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0024] refer to Figure 5 , providing a substrate 100, wherein the substrate 100 includes a core region I for forming a core device.

[0025] In this embodiment, the substrate 100 further includes a peripheral region II for forming an input / output device.

[0026] The substrate 100 is used to provide a process platform for forming transistors.

[0027] In this embodiment, the substrate 100 is used to form a fin field effect transistor (FinFET) as an example, and the substrate 100 includes a substrate (not labeled) and a fin (not labeled) protruding from the substrate (not labeled). In other embodiments, the substrate may also be a planar substrate, and the substrate may correspondingly only include a substrate.

[0028] In this embodiment, the substrate is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as a silicon on insulator substrate or a germanium on insulator substrate.

[0029] The fin is used to provide a conductive channel when the device is working. In this embodiment, the material of the fin is the same as the material of the substrate, and the material of the fin is silicon. In other embodiments, the material of the fin can also be a semiconductor material suitable for forming a fin, such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the material of the fin can also be different from the material of the substrate.

[0030] In this embodiment, the substrate 100 includes a core region I for forming a core device and a peripheral region II for forming an input / output device.

[0031] Among them, core devices mainly refer to devices used inside the chip, which usually use lower voltages, and the operating frequency of core devices is usually higher; input / output devices are devices used when the chip interacts with external interfaces. The operating voltage of such devices is generally higher, and the operating frequency of input / output devices is usually lower.

[0032] In this embodiment, an isolation structure (not shown) is further formed on the substrate 100 between the core region I and the peripheral region II. The isolation structure is used to isolate the core region I from the peripheral region II.

[0033] The material of the isolation structure includes one or more of silicon oxide, silicon nitride and silicon oxynitride.

[0034] Subsequent steps further include: forming a dummy gate on the substrate 100. In this embodiment, after providing the substrate 100 and before forming the dummy gate, the method for forming the semiconductor structure further includes: forming a gate oxide layer 110 on the substrate 100 in the core region I and the peripheral region II.

[0035] Accordingly, in the subsequent step of forming a dummy gate, the dummy gate is formed on the gate oxide layer 110 .

[0036] The gate oxide layer 110 can be used as a stop layer in the subsequent process of removing the dummy gate, thereby protecting the substrate 100. Specifically, in this embodiment, the gate oxide layer 110 is used to protect the fin.

[0037] The gate oxide layer 110 located in the peripheral region II is retained in subsequent processes. After the gate is formed subsequently, the gate oxide layer 110 located in the peripheral region II is used to isolate the gate from the substrate 100 .

[0038] The material of the gate oxide layer 110 may be silicon oxide or silicon oxynitride. In this embodiment, the material of the gate oxide layer 110 is silicon oxide.

[0039] The process of forming the gate oxide layer 110 includes a deposition process or an oxidation process. Specifically, the deposition process may be an atomic layer deposition process, and the oxidation process includes a dry oxygen oxidation process or a wet oxygen oxidation process.

[0040] In this embodiment, the gate oxide layer 110 covers the surface of the fin.

[0041] Continue to refer Figure 5 , a dummy gate 120 is formed on the substrate 100 .

[0042] The dummy gate 120 is used to occupy a space for the subsequent formation of a gate.

[0043] In this embodiment, the dummy gate 120 spans across the fin and covers a portion of the top and a portion of the sidewall of the fin.

[0044] In this embodiment, the dummy gate 120 includes a dummy gate layer, and the material of the dummy gate layer includes polysilicon.

[0045] In this embodiment, the step of forming the dummy gate 120 includes: forming a dummy gate material layer (not shown) covering the substrate 100 ; and patterning the dummy gate material layer, with the remaining dummy gate material layer being used as the dummy gate 120 .

[0046] In this embodiment, in the process of patterning the dummy gate material layer, the gate oxide layer 110 located at the bottom of the dummy gate material layer is also patterned, and accordingly, after the dummy gate 120 is formed, the gate oxide layer 110 is only located at the bottom of the dummy gate 120. In other embodiments, in the process of patterning the dummy gate material layer, the gate oxide layer may not be patterned, and accordingly, after the dummy gate is formed, the dummy gate oxide layer is still located on the surface of the substrate.

[0047] In this embodiment, after forming the dummy gate 120 , the method for forming the semiconductor structure further includes: forming a spacer (not shown) on the sidewall of the dummy gate 120 .

[0048] The sidewall spacer is used to protect the sidewall of the dummy gate 120 , and is also used to define the formation position of the source and drain doping regions.

[0049] In this embodiment, the side wall is a single-layer structure, and the material of the side wall is silicon nitride.

[0050] Continue to refer Figure 5 , source and drain doped regions (not shown) are formed in the substrate 100 on both sides of the dummy gate 120 .

[0051] The source and drain doping regions are used to provide stress to the channel when the device is working, thereby improving the carrier mobility in the channel region. Specifically, in this embodiment, the source and drain doping regions are formed in the fins on both sides of the dummy gate 120 .

[0052] In this embodiment, source and drain doping regions are formed by epitaxy and doping processes, and the material of the source and drain doping regions includes a stress layer doped with ions. When forming a PMOS transistor, the material of the stress layer is Si or SiGe, and the stress layer is used to provide compressive stress to the channel region of the PMOS transistor, and the doped ions in the stress layer are P-type ions, such as B ions, Ga ions, or In ions; when forming an NMOS transistor, the material of the stress layer is Si or SiC, and the stress layer is used to provide tensile stress to the channel region of the NMOS transistor, and the doped ions in the stress layer are N-type ions, such as P ions, As ions, or Sb ions.

[0053] Continue to refer Figure 5 An interlayer dielectric layer 130 covering the source and drain doped regions is formed on both sides of the dummy gate 120 .

[0054] The interlayer dielectric layer 130 is used to isolate adjacent devices.

[0055] Therefore, the material of the interlayer dielectric layer 130 is an insulating material. In this embodiment, the material of the interlayer dielectric layer 130 is the same as the material of the gate oxide layer 110, and the material of the interlayer dielectric layer 130 is silicon oxide. In other embodiments, the material of the interlayer dielectric layer can also be other insulating materials such as silicon oxynitride.

[0056] In this embodiment, after forming the source and drain doping regions and before forming the interlayer dielectric layer 130 , the method for forming the semiconductor structure further includes: forming an etching stop layer 140 conformally covering the surface of the source and drain doping regions and the sidewalls of the dummy gate 120 .

[0057] The etch stop layer 140 is a contact etch stop layer (CESL). In the subsequent process of etching the interlayer dielectric layer 140 to form contact holes exposing the source and drain doped regions, the etch stop layer 140 is used to define the etching stop position, which is beneficial to reduce the damage of the etching process to the source and drain doped regions.

[0058] Correspondingly, in this embodiment, the interlayer dielectric layer 130 covers the etching stop layer 140 .

[0059] In this embodiment, the material of the etching stop layer 140 is silicon nitride.

[0060] refer to Figure 6 , the dummy gate 120 is removed, and a gate opening 10 is formed in the interlayer dielectric layer 130 .

[0061] The gate opening 10 is used to provide a space for the subsequent formation of a gate.

[0062] In this embodiment, the gate oxide layer 110 is exposed at the bottom of the gate opening 10 , and the gate opening 10 is also used to prepare for the subsequent removal of the gate oxide layer 110 in the core region I.

[0063] In this embodiment, the step of removing the dummy gate 120 includes: removing a portion of the dummy gate 120 by dry etching; and removing the remaining dummy gate 120 by wet etching to form a gate opening 10 .

[0064] In this embodiment, the etching solution of the wet etching process includes NH4OH solution and tetramethylammonium hydroxide (TMAH) solution.

[0065] It should be noted that, in this embodiment, a natural oxide layer (not shown) is usually formed on the top surface of the dummy gate layer, and the material of the natural oxide layer is silicon oxide.

[0066] Therefore, in this embodiment, in the step of removing the dummy gate 120, the method for forming a semiconductor structure further includes: removing the natural oxide layer. By removing the natural oxide layer, the top surface of the dummy gate 120 is exposed, and the natural oxide layer is prevented from covering the dummy gate 120, which is conducive to reducing the probability of residual dummy gate 120.

[0067] refer to Figures 8 to 10, ion doping is performed on the interlayer dielectric layer 130 of the core area I, which is suitable for improving the etching resistance of the interlayer dielectric layer 130 of the core area I.

[0068] In the semiconductor field, the subsequent steps generally include steps of performing etching or planarization processes, such as removing the gate oxide layer 110 at the bottom of the gate opening 10 of the core region I, and ion doping the interlayer dielectric layer 130 of the core region I is suitable for improving the etching resistance of the interlayer dielectric layer 130 of the core region I, which is beneficial to reducing the probability of the interlayer dielectric layer 130 being mistakenly etched in the subsequent etching steps, thereby improving the height consistency of the interlayer dielectric layer 130 and reducing the probability of the top surface of the interlayer dielectric layer 130 being concave; and, the subsequent formation The gate process generally includes the steps of forming a gate material layer filling the gate opening 10 on the interlayer dielectric layer 130, and removing the gate material layer higher than the interlayer dielectric layer 130 by a planarization process. The top surface height consistency of the interlayer dielectric layer 130 is high, which correspondingly improves the height consistency of the gate, and the probability of a depression problem on the top surface of the interlayer dielectric layer 130 is low, which is correspondingly beneficial to reducing the probability of gate material residue on the top surface of the interlayer dielectric layer 130, which is correspondingly beneficial to improving the performance of the core device, and further beneficial to improving the production yield and the performance of the semiconductor structure.

[0069] In this embodiment, the ions doped into the interlayer dielectric layer 130 of the core region I include silicon ions. By doping the interlayer dielectric layer 130 of the core region I with silicon ions, it is beneficial to increase the silicon content in the interlayer dielectric layer 130, thereby facilitating the improvement of the hardness of the interlayer dielectric layer 130, and further facilitating the improvement of the etching resistance of the interlayer dielectric layer 130.

[0070] In the step of ion doping the interlayer dielectric layer 130 of the core region I, the doping depth of the ions in the interlayer dielectric layer 130 of the core region I should not be too small, otherwise the interlayer dielectric layer 130 doped with ions is easily consumed prematurely in the subsequent etching process or planarization process, which may easily lead to the ion doping being used to reduce the damage to the top surface of the interlayer dielectric layer 130 of the core region I. The doping depth of the ions in the interlayer dielectric layer 130 of the core region I should not be too large, otherwise it is easy to increase the risk of doping ions into other film layers and reduce process compatibility. For this reason, in this embodiment, the doping depth of the ions in the interlayer dielectric layer 130 of the core region I is 5nm to 8nm.

[0071] As an example, in this embodiment, after forming the gate opening 10 and before removing the gate oxide layer 110 at the bottom of the gate opening 10 in the core area I, ion doping is performed on the interlayer dielectric layer 130 in the core area I.

[0072] By performing ion doping after forming the gate opening 10 and before removing the gate oxide layer 110 at the bottom of the gate opening 10 in the core area I, it is beneficial to reduce the impact of other process steps between ion doping and removing the bottom gate oxide layer 110 of the gate opening 10 in the core area I, and thus it is beneficial to accurately control the effect of the ion doping, which correspondingly helps to significantly improve the thickness uniformity of the interlayer dielectric layer 130.

[0073] As an example, specifically, in this embodiment, the step of ion doping the interlayer dielectric layer 130 of the core region I includes:

[0074] like Figures 8 to 9 As shown, a shielding layer 160 (such as Fig. 9 As shown), the shielding layer 160 exposes the interlayer dielectric layer 130 of the core region I.

[0075] The shielding layer 160 is used as a mask for ion doping the interlayer dielectric layer 130 of the core region I.

[0076] The shielding layer 160 also fills the gate opening 10 , thereby protecting the gate oxide layer 110 at the bottom of the gate opening 10 .

[0077] In this embodiment, the material of the shielding layer 160 is BARC (Bottom Anti-reflective coating) material. In other embodiments, the material of the shielding layer can also be other suitable organic materials, such as Spin-On-Carbon (SOC).

[0078] In this embodiment, the steps of forming the shielding layer 160 include: Figure 8 As shown, a filling material layer 155 is formed on the interlayer dielectric layer 130 to fill the gate opening 10; Fig. 9 As shown, the filling material layer 155 located on the top surface of the interlayer dielectric layer 130 in the core area I and above the gate opening 10 is removed, and the remaining filling material layer 155 located in the gate opening 10 and on the top surface of the interlayer dielectric layer 130 in the peripheral area II is used as a shielding layer 160.

[0079] The filling material layer 155 is used to form the shielding layer 160 .

[0080] In this embodiment, the process of forming the filling material layer 155 includes a spin coating process.

[0081] It should be noted that, in this embodiment, after forming the filling material layer 155, before removing the filling material layer 155 located on the top surface of the interlayer dielectric layer 130 in the core region I and above the gate opening 10, the method for forming the semiconductor structure further includes: forming a pattern layer 101 (such as Figure 8 As shown), a graphic opening 20 is formed in the graphic layer 101 and is located above the interlayer dielectric layer 130 in the core area I.

[0082] The pattern layer 101 is used as a mask for etching the filling material layer 155 to form the shielding layer 160 .

[0083] In this embodiment, the material of the pattern layer 101 is photoresist. The pattern layer 101 can be formed by photolithography processes such as exposure and development, which will not be described in detail in this embodiment.

[0084] Accordingly, in this embodiment, the pattern layer 101 is used as a mask to remove the filling material layer 155 located on the top surface of the interlayer dielectric layer 130 in the core area I and above the gate opening 10 along the pattern opening 20 .

[0085] In this embodiment, a dry etching process is adopted to etch and remove the filling material layer 155 located on the top surface of the interlayer dielectric layer in the core area I and above the gate opening 10 along the pattern opening 20 .

[0086] like Fig.10 As shown, the interlayer dielectric layer 130 of the core region I is ion doped using the shielding layer 160 as a mask.

[0087] In this embodiment, the process of ion doping includes an ion implantation process, and the parameters of the ion implantation process include: an implantation energy of 0.25 KeV to 5 KeV, an implantation dose of 1.6E15 atom / cm 2 to 1.6E17atom / cm 2 , the injection angle is 0°.

[0088] The injection energy of the ion implantation process should not be too small, otherwise it will easily lead to a too small doping depth of the ion doping; the injection energy of the ion implantation process should not be too large, otherwise it will easily lead to a too large doping depth of the ion doping. Therefore, in this embodiment, in order to ensure that the doping depth of the ions in the interlayer dielectric layer 130 of the core region I meets the process requirements, the injection energy of the ion implantation process is 0.25KeV to 5KeV.

[0089] The implantation dose of the ion implantation process should not be too small, otherwise it is easy to cause the ion doping to have an insignificant effect on improving the etching resistance of the interlayer dielectric layer 130; the implantation dose of the ion implantation process should not be too large, otherwise it is easy to increase the process risk. Therefore, in this embodiment, the implantation dose of the ion implantation process is 1.6E15atom / cm 2 to 1.6E17atom / cm 2 .

[0090] The injection angle of the ion injection process refers to the angle between the injection angle and the surface normal of the substrate 100. In this embodiment, the injection angle of the ion injection process is 0°, so that the ions can be injected into the interlayer dielectric layer 130 along a direction perpendicular to the surface of the substrate 100, which helps to reduce the risk of injecting ions into other film layer structures.

[0091] Combined with reference Figure 7 In this embodiment, after removing the dummy gate 120 and before forming the filling material layer 155, the method for forming the semiconductor structure also includes: forming a sacrificial oxide layer 150 that conformally covers the bottom and side walls of the gate opening 10 and the top surface of the interlayer dielectric layer 130.

[0092] Subsequent steps also include: removing the gate oxide layer 110 at the bottom of the gate opening 10 in the core area I. In this embodiment, a sacrificial oxide layer 150 is formed before removing the gate oxide layer 110 at the bottom of the gate opening 10 in the core area I, so that the sacrificial oxide layer 150 can protect the gate oxide layer 110 at the bottom of the gate opening 10 in the peripheral area II during the process of removing the gate oxide layer 110 at the bottom of the gate opening 10 in the core area I. In addition, the sacrificial oxide layer 150 can also protect the top surface of the interlayer dielectric layer 130, which is beneficial to reduce the probability of damage to the interlayer dielectric layer 130.

[0093] In this embodiment, the sacrificial oxide layer 150 is made of the same material as the interlayer dielectric layer 130 and the gate oxide layer 110 , and the material of the sacrificial oxide layer 150 is silicon oxide.

[0094] In this embodiment, the sacrificial oxide layer 150 is formed by using an atomic layer deposition process.

[0095] The subsequent steps also include: forming a gate filling the gate opening 10. Fig.11 In this embodiment, after ion doping and before removing the gate oxide layer 110 at the bottom of the gate opening 10 of the core area I, the method for forming the semiconductor structure also includes: removing the blocking layer 160 located in the gate opening 10 of the core area I to expose the bottom and side walls of the gate opening 10 of the core area I.

[0096] By exposing the bottom and side walls of the gate opening 10, preparation is made for the subsequent removal of the gate oxide layer 110 located at the bottom of the gate opening 10 in the core area I; moreover, after removing the shielding layer 160 in the gate opening 10 of the core area I in this embodiment, the remaining shielding layer 160 can be used as an etching mask for the subsequent removal of the gate oxide layer 110 at the bottom of the gate opening 10 in the core area I, thereby integrating the step of performing the ion doping with the step of removing the gate oxide layer 110 at the bottom of the gate opening 10 in the core area I, which is beneficial to improving process integration and process compatibility, and is also beneficial to simplifying process steps.

[0097] Specifically, the sacrificial oxide layer 150 is also formed on the bottom and side walls of the gate opening 10 and the top surface of the interlayer dielectric layer 130. Therefore, after removing the blocking layer 160 located in the gate opening 10 in the core area I, the sacrificial oxide layer 150 located at the bottom and side walls of the gate opening 10 in the core area I is exposed.

[0098] In this embodiment, the process of removing the shielding layer 160 located in the gate opening 10 of the core region I includes a dry etching process, for example, an anisotropic dry etching process. The anisotropic dry etching process has the characteristic of anisotropic etching, which is conducive to reducing the probability of lateral etching of the shielding layer 160. Accordingly, in the step of removing the shielding layer 160 located in the gate opening 10 of the core region I, the probability of causing damage to the shielding layer 160 located in the interlayer dielectric layer 130 and the gate opening 10 of the peripheral region II is low, so that the remaining shielding layer 160 can be used as a mask to remove the gate oxide layer 110 located at the bottom of the gate opening 10 of the core region I in the subsequent step.

[0099] Combined with reference Fig.12 In this embodiment, after forming the gate opening 10 and performing the ion doping and before forming the gate, the method for forming the semiconductor structure further includes: removing the gate oxide layer 110 at the bottom of the gate opening 10 in the core area I.

[0100] In this embodiment, the substrate 100 includes a core region I for forming a core device and a peripheral region II for forming an input / output device. In the semiconductor field, the operating voltage of the input / output device is usually much greater than the operating voltage of the core device. To ensure the performance of the input / output device (for example, to prevent breakdown and other problems), the thickness of the gate dielectric layer of the input / output device is usually greater than the thickness of the gate dielectric layer of the core device.

[0101] The gate formed subsequently to fill the gate opening 10 is a metal gate structure, and the gate generally includes a high-k gate dielectric layer located at the bottom and sidewalls of the gate opening 10. In this embodiment, by removing the gate oxide layer 110 of the core region I, the gate dielectric layer of the core device only includes the high-k gate dielectric layer, and the gate dielectric layer of the input / output device includes the gate oxide layer 110 and the high-k gate dielectric layer located on the gate oxide layer 110, thereby making the thickness of the gate dielectric layer of the core region I greater than the thickness of the gate dielectric layer of the peripheral region II.

[0102] In this embodiment, the interlayer dielectric layer 130 is made of the same material as the gate oxide layer 110, and in this embodiment, ion doping is performed on the interlayer dielectric layer 130 of the core area I, which is suitable for improving the etching resistance of the interlayer dielectric layer 130 of the core area I. Therefore, in the process of removing the gate oxide layer 110 at the bottom of the gate opening 10 of the core area I, the probability of damage to the interlayer dielectric layer 130 of the core area I is low, which is correspondingly beneficial to improving the height consistency of the interlayer dielectric layer 130 and reducing the probability of a dishing problem on the top surface of the interlayer dielectric layer 130.

[0103] Specifically, in this embodiment, after the shielding layer 160 located in the gate opening 10 of the core region I is removed, the gate oxide layer 110 at the bottom of the gate opening 10 of the core region I is removed.

[0104] Therefore, in this embodiment, in the step of removing the gate oxide layer 110 at the bottom of the gate opening 10 in the core area I, the remaining blocking layer 160 is used as a mask to remove the gate oxide layer 110 at the bottom of the gate opening 10 in the core area I, thereby integrating the process of performing the ion doping with the process of removing the gate oxide layer 110 at the bottom of the gate opening 10 in the core area I, and there is no need to additionally form a mask for removing the gate oxide layer 110 at the bottom of the gate opening 10 in the core area I, which is not only beneficial to simplifying the process steps and improving the process integration, but also beneficial to saving process costs.

[0105] In this embodiment, in the step of removing the gate oxide layer 110 at the bottom of the gate opening 10 in the core area I, the sacrificial oxide layer 150 located at the bottom and side walls of the gate opening 10 in the core area I and the top surface of the interlayer dielectric layer 130 exposed by the blocking layer 160 is also removed.

[0106] In this embodiment, the process for removing the gate oxide layer 110 at the bottom of the core region I gate opening 10 includes a Certas etching process. The Certas process is an isotropic etching process, which is conducive to completely removing the sacrificial oxide layer 110 located on the sidewall and bottom of the core region I gate opening 10, and the gate oxide layer 110 located at the bottom of the core region I gate opening 10. In other embodiments, other suitable processes can also be used to remove the gate oxide layer of the gate oxide layer at the bottom of the core region gate opening, for example: a wet etching process, and the etching solution of the wet etching process can be a diluted hydrofluoric acid (DHF) solution.

[0107] Combined with reference Fig.13 In this embodiment, after removing the gate oxide layer 110 at the bottom of the gate opening 10 of the core region I, the method for forming the semiconductor structure further includes: removing the blocking layer 160.

[0108] The blocking layer 160 is removed to expose the gate opening 10 in the peripheral region II, in preparation for the subsequent formation of a gate filled in the gate opening 10 .

[0109] In this embodiment, during the process of removing the shielding layer 160 , the graphic layer 101 is also removed.

[0110] In this embodiment, an ashing process is used to remove the shielding layer 160 .

[0111] Combined with reference Fig.14 In this embodiment, after removing the blocking layer 160 , the method for forming the semiconductor structure further includes: removing the remaining sacrificial oxide layer 150 .

[0112] By removing the remaining sacrificial oxide layer 150 , the gate oxide layer 110 at the bottom of the gate opening 10 in the peripheral region II and the sidewalls of the gate opening 10 in the peripheral region II are exposed, so as to prepare for the subsequent formation of a gate filling the gate opening 10 .

[0113] In this embodiment, since the interlayer dielectric layer 130 of the core area I is doped with silicon ions, the etching resistance of the interlayer dielectric layer 130 of the core area I is relatively high. Therefore, in the process of removing the remaining sacrificial oxide layer 150, the probability of damage to the interlayer dielectric layer 130 of the core area I is relatively low, which is beneficial to improving the top surface height consistency of the interlayer dielectric layer 130 and reducing the probability of depression on the top surface of the interlayer dielectric layer 130.

[0114] In this embodiment, a wet etching process is used to remove the remaining sacrificial oxide layer 150. The etching solution of the wet etching process may be a diluted hydrofluoric acid solution.

[0115] refer to Fig.15 After forming the gate opening 10 and performing ion doping, a gate 170 is formed to fill the gate opening 10. Specifically, in this embodiment, after removing the gate oxide layer 110 at the bottom of the gate opening 10 of the core region I, the gate 170 is formed.

[0116] The gate 170 is used to control the opening or closing of the conductive channel.

[0117] In this embodiment, the step of forming the gate 170 includes: forming a gate material layer (not shown) filling the gate opening 10 on the interlayer dielectric layer 130; using a planarization process to remove the gate material layer higher than the interlayer dielectric layer 130, and the remaining gate material layer located in the gate opening 10 is used as the gate 170.

[0118] As can be seen from the foregoing, the interlayer dielectric layer 130 has a high consistency in height, and the probability of a depression problem occurring on the top surface of the interlayer dielectric layer 130 is low; the process of forming the gate 170 adopts a planarization process to remove the gate material layer higher than the interlayer dielectric layer 130, and the top surface height consistency of the interlayer dielectric layer 130 is high, which correspondingly improves the height consistency of the gate 170, and the probability of a depression problem occurring on the top surface of the interlayer dielectric layer 130 is low, which is correspondingly beneficial to reducing the probability of residual gate 170 material occurring on the top surface of the interlayer dielectric layer 130, and is further beneficial to improving the production yield and the performance of the semiconductor structure.

[0119] In this embodiment, a chemical mechanical polishing process is used to remove the gate material layer higher than the interlayer dielectric layer 130 .

[0120] In this embodiment, the gate 170 is a metal gate structure, and the gate 170 includes a high-k gate dielectric layer (not shown) located at the bottom and sidewalls of the gate opening 10, and a gate electrode layer (not shown) located on the high-k gate dielectric layer and filling the gate opening 10.

[0121] The material of the high-k gate dielectric layer is a high-k gate dielectric material, and the high-k gate dielectric material may be HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2 or Al2O3. In this embodiment, the material of the high-k gate dielectric layer is HfO2.

[0122] In this embodiment, the high-k gate dielectric layer of the core region I constitutes the gate dielectric layer of the core device, and the gate oxide layer 110 of the peripheral region II and the high-k gate dielectric layer located on the gate oxide layer 110 constitute the gate dielectric layer of the input / output device, so that the thickness of the gate dielectric layer of the core device is less than the thickness of the gate dielectric layer of the input / output device.

[0123] In this embodiment, the material of the gate electrode layer is W.

[0124] Fig.16 1 is a schematic diagram of the structure corresponding to each step in another embodiment of the method for forming a semiconductor structure of the present invention. The similarities between the embodiment of the present invention and the aforementioned embodiment are not repeated here. The difference between the embodiment of the present invention and the aforementioned embodiment is that after forming the interlayer dielectric layer 230 and before removing the dummy gate 220, the interlayer dielectric layer 230 of the core area A is ion doped.

[0125] By ion doping the interlayer dielectric layer 230 of the core area A before removing the dummy gate 220, it is suitable to improve the etching resistance of the interlayer dielectric layer 230 of the core area A, thereby helping to reduce the probability of damage to the interlayer dielectric layer 230 of the core area A during the subsequent removal of the dummy gate 220.

[0126] Specifically, in the present embodiment, ion doping is also performed on the interlayer dielectric layer 230 of the peripheral region B, which is correspondingly beneficial to reduce the probability of damage of the interlayer dielectric layer 230 of the peripheral region B during subsequent etching processes or planarization processes, for example, during the subsequent removal of the pseudo gate 220, thereby helping to improve the height consistency of the interlayer dielectric layer 230.

[0127] Moreover, in this embodiment, after the interlayer dielectric layer 230 is formed and before the dummy gate 220 is removed, the interlayer dielectric layer 230 of the core area A and the peripheral area B is ion doped. During the ion doping process, it is not necessary to form a mask, which is beneficial to saving costs and simplifying the process.

[0128] In this embodiment, the ions used for ion doping the interlayer dielectric layer 230 in the core region A include silicon ions.

[0129] In this embodiment, ion doping is performed by ion implantation process. For the specific description of ion doping in this embodiment, reference can be made to the relevant description of ion doping in the above embodiment, which will not be repeated in this embodiment.

[0130] The subsequent process steps are the same as those in the previous embodiment, and will not be described in detail in this embodiment.

[0131] Accordingly, the present invention also provides a semiconductor structure. Fig.10 , showing a schematic structural diagram of an embodiment of a semiconductor structure of the present invention.

[0132] The semiconductor structure comprises: a substrate 100, wherein the substrate 100 comprises a core region I for forming a core device and a peripheral region II for forming an input / output device; a gate opening 10 (such as Figure 7As shown in the figure), it is located on the substrate 100; the source-drain doped region (not shown) is located in the substrate 100 on both sides of the gate opening 10; the interlayer dielectric layer 130 is located on both sides of the gate opening 10 and covers the source-drain doped region, wherein the interlayer dielectric layer 130 of the core region I is doped with ions, and the ions are suitable for improving the etching resistance of the interlayer dielectric layer 130 of the core region I.

[0133] In the semiconductor structure provided by the embodiment of the present invention, the interlayer dielectric layer 130 of the core region I is further doped with ions, and the ions are suitable for improving the etching resistance of the interlayer dielectric layer 130 of the core region I. In the semiconductor field, the subsequent steps generally include the steps of performing etching or planarization processes, for example, removing the gate oxide layer 110 at the bottom of the gate opening 10 of the core region I, etc. By improving the etching resistance of the interlayer dielectric layer 130 of the core region I, it is beneficial to reduce the probability of the interlayer dielectric layer 130 of the core region I being mistakenly etched in the subsequent etching steps, thereby facilitating improving the high consistency of the interlayer dielectric layer 130 and reducing The probability of a depression on the top surface of the low interlayer dielectric layer 130 is reduced; moreover, the subsequent process of forming a gate generally includes the steps of forming a gate material layer filling the gate opening 10 on the interlayer dielectric layer 130, and removing the gate material layer higher than the interlayer dielectric layer 130 by a planarization process. The top surface height consistency of the interlayer dielectric layer 130 is high, which correspondingly improves the height consistency of the gate, and the probability of a depression on the top surface of the interlayer dielectric layer 130 is low, which is correspondingly beneficial to reducing the probability of gate material residue on the top surface of the interlayer dielectric layer 130, thereby facilitating improving the production yield and the performance of the semiconductor structure.

[0134] The substrate 100 is used to provide a process platform for forming transistors.

[0135] In this embodiment, the substrate 100 is used to form a fin field effect transistor (FinFET) as an example, and the substrate 100 includes a substrate (not labeled) and a fin portion (not labeled) protruding from the substrate (not labeled). In this embodiment, the substrate is a silicon substrate.

[0136] The fin is used to provide a conductive channel when the device is working.

[0137] In this embodiment, the material of the fin is silicon.

[0138] In this embodiment, the substrate 100 includes a core region I for forming a core device and a peripheral region II for forming an input / output device.

[0139] In this embodiment, an isolation structure (not shown) is further formed on the substrate 100 between the core region I and the peripheral region II. The material of the isolation structure includes one or more of silicon oxide, silicon nitride and silicon oxynitride.

[0140] The gate opening 10 is used to provide a space for the subsequent formation of a gate.

[0141] The gate opening 10 is formed by removing the dummy gate.

[0142] The semiconductor structure further includes a gate oxide layer 110 located at the bottom of the gate opening 10 in the core region I and the peripheral region II. The gate oxide layer 110 is used as a stop layer in the process of removing the dummy gate to form the gate opening 10, thereby protecting the substrate 100.

[0143] The gate oxide layer 110 located in the peripheral region II is retained in the subsequent process. After the gate that fills the gate opening 10 is subsequently formed, the gate oxide layer 110 located in the peripheral region II is also used to isolate the gate from the substrate 100. The material of the gate oxide layer 110 includes silicon oxide or silicon oxynitride. In this embodiment, the material of the gate oxide layer 110 is silicon oxide.

[0144] The source and drain doping regions are used to provide stress to the channel when the device is working, thereby improving the carrier mobility in the channel region. In this embodiment, the material of the source and drain doping regions includes a stress layer doped with ions. When a PMOS transistor is formed, the material of the stress layer is Si or SiGe, and the stress layer is used to provide compressive stress to the channel region of the PMOS transistor, and the doped ions in the stress layer are P-type ions, such as B ions, Ga ions or In ions; when an NMOS transistor is formed, the material of the stress layer is Si or SiC, and the stress layer is used to provide tensile stress to the channel region of the NMOS transistor, and the doped ions in the stress layer are N-type ions, such as P ions, As ions or Sb ions.

[0145] The semiconductor structure further includes an etching stop layer 140 conformally covering the surface of the source and drain doping regions. Moreover, in this embodiment, the sidewall of the gate opening 10 exposes the etching stop layer 140 .

[0146] The etching stop layer 140 is used to define the stop position of etching in the subsequent step of etching the interlayer dielectric layer 130 to form contact holes exposing the source and drain doped regions, thereby reducing the probability of damaging the source and drain doped regions.

[0147] In this embodiment, the material of the etching stop layer 140 is silicon nitride.

[0148] The interlayer dielectric layer 130 is used to isolate adjacent devices. In this embodiment, the interlayer dielectric layer 130 covers the etching stop layer 140 .

[0149] Therefore, the material of the interlayer dielectric layer 130 is an insulating material. In this embodiment, the material of the interlayer dielectric layer 130 is the same as that of the gate oxide layer 110, and the material of the interlayer dielectric layer 130 is silicon oxide. In other embodiments, the material of the interlayer dielectric layer can also be other insulating materials such as silicon oxynitride.

[0150] The doping ions in the interlayer dielectric layer 130 of the core region I include silicon ions. By doping the interlayer dielectric layer 130 of the core region I with silicon ions, it is beneficial to increase the silicon content in the interlayer dielectric layer 130, thereby facilitating the improvement of the hardness of the interlayer dielectric layer 130, and further improving the etching resistance of the interlayer dielectric layer 130.

[0151] The doping depth of ions in the interlayer dielectric layer 130 of the core region I should not be too small, otherwise the interlayer dielectric layer 130 doped with ions is easily consumed prematurely in the subsequent etching process or planarization process, which may lead to the effect of the doped ions in reducing the damage to the top surface of the interlayer dielectric layer 130 of the core region I being not obvious; the doping depth of ions in the interlayer dielectric layer 130 of the core region I should not be too large, otherwise it may easily increase the risk of doping ions into other film layers and reduce process compatibility. For this reason, in this embodiment, the doping depth of ions in the interlayer dielectric layer 130 of the core region I is 5nm to 8nm.

[0152] The semiconductor structure further includes a sacrificial oxide layer 150 conformally covering the bottom and sidewalls of the gate opening 10 and the top surface of the interlayer dielectric layer 130 .

[0153] Subsequent steps also include: removing the gate oxide layer 110 at the bottom of the gate opening 10 in the core area I. The sacrificial oxide layer 150 can protect the gate oxide layer 110 at the bottom of the gate opening 10 in the peripheral area II during the process of removing the gate oxide layer 110 at the bottom of the gate opening 10 in the core area I. In addition, the sacrificial oxide layer 150 can also protect the top surface of the interlayer dielectric layer 130, which is beneficial to reduce the probability of damage to the interlayer dielectric layer 130.

[0154] In this embodiment, the material of the sacrificial oxide layer 150 is silicon oxide.

[0155] In this embodiment, the semiconductor structure further includes a blocking layer 160 filling the gate opening 10 and covering the interlayer dielectric layer 130 in the peripheral region II. The blocking layer 160 exposes the interlayer dielectric layer 130 in the core region I.

[0156] The shielding layer 160 is used as a mask for ion doping the interlayer dielectric layer 130 of the core region I.

[0157] The shielding layer 160 also fills the gate opening 10, thereby protecting the gate oxide layer 110 at the bottom of the gate opening 10. In this embodiment, the shielding layer 160 is made of a BARC material.

[0158] In this embodiment, the semiconductor structure further includes: a pattern layer 101 located on the shielding layer 160 .

[0159] The shielding layer 160 is usually formed by etching the filling material layer, and the pattern layer 101 is used as a mask for etching the filling material layer 155 to form the shielding layer 160. In this embodiment, the material of the pattern layer 101 is photoresist.

[0160] The semiconductor structure can be formed by the formation method described in the above embodiment, or by other formation methods. For the specific description of the semiconductor structure described in this embodiment, reference can be made to the corresponding description in the above embodiment, and this embodiment will not be repeated here.

[0161] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a core region for forming a core device, the substrate further comprising a peripheral region for forming an input / output device; A dummy gate is formed on the substrate. After providing the substrate and before forming the dummy gate on the substrate, the method for forming the semiconductor structure further comprises: forming a gate oxide layer on the substrate in the peripheral region and the core region; forming source-drain doped regions in the substrate on both sides of the dummy gate; forming an interlayer dielectric layer covering the source and drain doped regions on both sides of the dummy gate; Removing the dummy gate, forming a gate opening in the interlayer dielectric layer, wherein in the step of forming the gate opening, the bottom of the gate opening exposes the gate oxide layer; After removing the dummy gate, forming a sacrificial oxide layer conformally covering the bottom and sidewalls of the gate opening and the top surface of the interlayer dielectric layer; After forming the sacrificial oxide layer, ion doping is performed on the interlayer dielectric layer of the core area, which is suitable for improving the etching resistance of the interlayer dielectric layer of the core area; After forming the gate opening and performing ion doping, a gate filling the gate opening is formed; after forming the gate opening and performing the ion doping and before forming the gate, the method for forming the semiconductor structure further includes: removing the gate oxide layer at the bottom of the gate opening in the core area.

2. The method for forming a semiconductor structure according to claim 1, wherein: After forming the gate opening and before removing the gate oxide layer at the bottom of the gate opening in the core region, ion doping is performed on the interlayer dielectric layer in the core region.

3. The method for forming a semiconductor structure according to claim 2, wherein: The step of ion doping the interlayer dielectric layer in the core area comprises: forming a shielding layer filling the gate opening and covering the interlayer dielectric layer in the peripheral area, wherein the shielding layer exposes the interlayer dielectric layer in the core area; using the shielding layer as a mask, ion doping the interlayer dielectric layer in the core area; After ion doping and before removing the gate oxide layer at the bottom of the gate opening of the core region, the method for forming the semiconductor structure further includes: removing a blocking layer located in the gate opening of the core region to expose the bottom and sidewalls of the gate opening of the core region; In the step of removing the gate oxide layer at the bottom of the gate opening of the core region, the gate oxide layer at the bottom of the gate opening of the core region is removed by using the remaining shielding layer as a mask.

4. The method for forming a semiconductor structure according to claim 3, wherein: The step of forming the shielding layer includes: forming a filling material layer filling the gate opening on the interlayer dielectric layer; removing the filling material layer located on the top surface of the interlayer dielectric layer in the core area and above the gate opening, and the remaining filling material layer located in the gate opening and on the top surface of the interlayer dielectric layer in the peripheral area is used as the shielding layer.

5. The method for forming a semiconductor structure according to claim 4, wherein: A dry etching process is adopted to remove the filling material layer located on the top surface of the interlayer dielectric layer in the core area and above the gate opening.

6. The method for forming a semiconductor structure according to claim 3, wherein: The process of removing the shielding layer in the core region gate opening includes a dry etching process.

7. The method for forming a semiconductor structure according to claim 1, wherein: The material of the gate oxide layer includes silicon oxide or silicon oxynitride; the material of the interlayer dielectric layer includes silicon oxide or silicon oxynitride.

8. The method for forming a semiconductor structure according to claim 1, wherein: In the step of performing ion doping on the interlayer dielectric layer of the core region, the ion doping depth in the interlayer dielectric layer of the core region is 5 nm to 8 nm.

9. The method for forming a semiconductor structure according to claim 1, wherein: The ions used to dope the interlayer dielectric layer in the core region include silicon ions.

10. The method for forming a semiconductor structure according to claim 9, wherein: The ion doping process includes an ion implantation process, wherein the parameters of the ion implantation process include: an implantation energy of 0.25 KeV to 5 KeV, an implantation dose of 1.6E15 atom / cm 2 to 1.6E17atom / cm 2 , the injection angle is 0°.

11. The method for forming a semiconductor structure according to claim 1, wherein: A natural oxide layer is also formed on the top surface of the dummy gate; In the step of removing the dummy gate, the method for forming a semiconductor structure further includes: removing the natural oxide layer.

12. The method for forming a semiconductor structure according to claim 1, wherein: The step of forming the gate includes: forming a gate material layer filling the gate opening on the interlayer dielectric layer; using a planarization process to remove the gate material layer higher than the interlayer dielectric layer, and the remaining gate material layer located in the gate opening is used as the gate.

13. A semiconductor structure, characterized in that: The method for forming a semiconductor structure according to any one of claims 1 to 12 is used, comprising: A substrate, the substrate comprising a core region for forming a core device; the substrate further comprising a peripheral region for forming an input / output device; A gate opening is located on the substrate; Source and drain doping regions are located in the substrate on both sides of the gate opening; An interlayer dielectric layer, located at both sides of the gate opening and covering the source and drain doped regions, wherein the interlayer dielectric layer in the core region is doped with ions, and the ions are suitable for improving the etching resistance of the interlayer dielectric layer in the core region; The semiconductor structure further includes: a gate oxide layer located at the bottom of the gate opening in the peripheral region; The gate is located in the gate openings of the core region and the peripheral region.

14. The semiconductor structure according to claim 13, wherein: The doping depth of ions in the interlayer dielectric layer of the core region is 5 nm to 8 nm.

15. The semiconductor structure according to claim 13, wherein: The doping ions in the interlayer dielectric layer of the core region include silicon ions.

16. The semiconductor structure according to claim 13, wherein: The material of the gate oxide layer includes silicon oxide or silicon oxynitride; the material of the interlayer dielectric layer includes silicon oxide or silicon oxynitride.

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