Semiconductor package including decoupling capacitor

Abstract

Semiconductor package including decoupling capacitors. A semiconductor package includes a substrate and a semiconductor chip disposed above the substrate. The substrate includes: a base layer including an upper surface facing the semiconductor chip; an upper ground electrode plate disposed above the upper surface of the base layer and configured to transmit a ground voltage to the semiconductor chip; and a dummy power pattern disposed in the upper ground electrode plate and having a side surface surrounded by and spaced apart from the upper ground electrode plate, and having an insulating material between the dummy power pattern and the upper ground electrode plate. A ground voltage transmission path from the upper ground electrode plate to the semiconductor chip is spaced apart from the dummy power pattern.

Description

Technical Field

[0001] The present patent document relates to a semiconductor package, and more particularly, to a semiconductor package including a decoupling capacitor. Background Art

[0002] Recently, there is an increasing demand for high-speed operation and large-capacity data processing of semiconductor devices. For this reason, it is necessary to increase the number of signals transmitted to the semiconductor devices at the same time or the signal transmission speed.

[0003] However, there is a problem that power / ground noise increases as semiconductor devices operate at higher speeds and the number of signals transmitted simultaneously increases. To solve this problem, a method of stabilizing power / ground supply by adding a decoupling capacitor is currently widely used. Summary of the invention

[0004] In an embodiment, a semiconductor package may include a substrate and a semiconductor chip disposed above the substrate. The substrate includes: a base layer including an upper surface facing the semiconductor chip; an upper ground electrode plate disposed above the upper surface of the base layer and configured to transmit a ground voltage to the semiconductor chip; and a dummy power pattern disposed in the upper ground electrode plate and having a side surface surrounded by and spaced apart from the upper ground electrode plate, and having an insulating material between the dummy power pattern and the upper ground electrode plate. A ground voltage transmission path from the upper ground electrode plate to the semiconductor chip is spaced apart from the dummy power pattern.

[0005] In another embodiment, a semiconductor package may include a substrate and a semiconductor chip disposed above the substrate. The substrate includes: a base layer including an upper surface facing the semiconductor chip; an upper power electrode plate disposed above the upper surface of the base layer and configured to transmit a power supply voltage to the semiconductor chip; and a dummy ground pattern disposed in the upper power electrode plate and having a side surface surrounded by the upper power electrode plate and spaced apart from the upper power electrode plate, and having an insulating material between the dummy ground pattern and the upper power electrode plate. A power supply voltage transmission path from the upper power electrode plate to the semiconductor chip is spaced apart from the dummy ground pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1A and Figure 1B is a plan view illustrating upper and lower wiring layers of a substrate of a semiconductor package according to an embodiment of the present disclosure.

[0007] Figure 1C is a plan view illustrating a semiconductor chip of a semiconductor package according to an embodiment of the present disclosure.

[0008] Figure 2 It is a reference Figure 1A and Figure 1B A cross-sectional view taken along line AA'.

[0009] Figure 3 It is a reference Figure 1A and Figure 1B A cross-sectional view taken along line BB'.

[0010] Figure 4 It is a reference Figure 1A and Figure 1B A cross-sectional view taken along line CC'.

[0011] Figure 5 It is a reference Figure 1A and Figure 1B A cross-sectional view taken along line D-D'.

[0012] Figure 6 It is a reference Figure 1A and Figure 1B A cross-sectional view taken along line EE'.

[0013] Figure 7 is a plan view illustrating shapes of a dummy power pattern and a ground electrode plate according to another embodiment of the present disclosure.

[0014] Figure 8 A block diagram illustrating an electronic system employing a memory card including a semiconductor package according to an embodiment is shown.

[0015] Fig. 9 A block diagram illustrating another electronic system including a semiconductor package according to an embodiment is shown. DETAILED DESCRIPTION

[0016] Hereinafter, various examples of embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0017] The drawings may not necessarily be to scale, and in some cases, the scale of at least some structures in the drawings may have been exaggerated in order to clearly illustrate specific features of the described examples or implementations. When a specific example in a drawing or description having two or more layers is presented as a multilayer structure, the relative positional relationship of these layers or the order in which the layers are arranged as shown reflects the specific implementation of the described or illustrated example, and different relative positional relationships or orders of arrangement of layers may be possible. In addition, the described or illustrated examples of multilayer structures may not reflect all layers present in the particular multilayer structure (for example, one or more additional layers may exist between the two illustrated layers). As a specific example, when the first layer in the described or illustrated multilayer structure is referred to as being "on" or "above" the second layer or "on" or "above" the substrate, the first layer may be formed directly on the second layer or substrate, but it may also represent a structure in which one or more other intermediate layers may exist between the first layer and the second layer or substrate.

[0018] Below, we will refer to Figures 1A to 6 A semiconductor package according to an embodiment of the present disclosure is described.

[0019] Figure 1A and Figure 1B is a plan view showing an upper wiring layer and a lower wiring layer of a substrate of a semiconductor package according to an embodiment of the present disclosure, Figure 1C is a plan view showing a semiconductor chip of a semiconductor package according to an embodiment of the present disclosure. For reference, for convenience of description, Figure 1A A semiconductor chip is also shown. Figure 1A and Figure 1B A via between an upper wiring layer and a lower wiring layer is shown in FIG. Figure 1C The lower surface of the semiconductor chip is shown. Figures 2 to 5 is a cross-sectional view showing a semiconductor package according to an embodiment of the present disclosure. Figure 2 It is a reference Figure 1A and Figure 1B A cross-sectional view taken along line A-A', Figure 3 It is a reference Figure 1A and Figure 1B A cross-sectional view taken along line BB' of Figure 4 It is a reference Figure 1A and Figure 1B The cross-sectional view taken along the line C-C', Figure 5 It is a reference Figure 1A and Figure 1B A cross-sectional view taken along line D-D', Figure 6 It is a reference Figure 1A and Figure 1B A cross-sectional view taken along line EE' of FIG. A direction parallel to line A-A' and line BB' will be referred to as a first direction, and a direction parallel to line CC' and line D-D' and perpendicular to the first direction will be referred to as a second direction. If necessary, description will be made with reference to all or part of the drawings.

[0020] First, refer to Figures 2 to 6 The semiconductor package of the present embodiment may include a substrate 100 and a semiconductor chip 200 disposed above the substrate 100 .

[0021] Here, the substrate 100 may have a circuit and / or wiring structure for connecting the semiconductor chip 200 to the external connection terminals described below (see Figure 3 As an example, the substrate 100 may be a printed circuit board (PCB).

[0022] The semiconductor chip 200 may overlap a portion of the substrate 100 over the substrate 100. Figure 1A and Figure 1CThe semiconductor chip 200 may include a first region 200A and a second region 200B arranged in the second direction. The first region 200A may be a region overlapping with an upper ground electrode plate 120A (to be described later), and the second region 200B may be a region overlapping with an upper power electrode plate 120B (to be described later).

[0023] In addition, the semiconductor chip 200 may receive various power supplies or signals from the substrate 100 and perform various operations accordingly. Figure 1C , the semiconductor chip 200 may include a plurality of connection terminals 210 for connecting to the substrate 100 and receiving power or signals from the substrate 100. As an example, the connection terminal 210 may be a conductive bump formed above the lower surface of the semiconductor chip 200 facing the substrate 100. The connection terminal 210 may include a first connection terminal 210A disposed in the first region 200A and a second connection terminal 210B disposed in the second region 200B. As an example, the number of the first connection terminals 210A and the number of the second connection terminals 210B may be the same. In addition, as an example, the first connection terminal 210A may be arranged in a row along the first direction, and the second connection terminal 210B may be arranged in a row along the first direction. However, the shape, arrangement, number, etc. of the connection terminals 210 in the first region 200A and the second region 200B may be modified differently. The first connection terminal 210A may include a first power terminal 212A to which a power voltage is applied, a first signal terminal 213A to which a signal is applied, and a first ground terminal 214A to which a ground voltage is applied. In addition, the second connection terminal 210B may include a second power terminal 212B to which a power voltage is applied, a second signal terminal 213B to which a signal is applied, and a second ground terminal 214B to which a ground voltage is applied.

[0024] The semiconductor chip 200 may be a memory chip, which includes a nonvolatile memory such as a NAND flash memory, a phase change random access memory (PRAM), a magnetoresistive random access memory (MRAM), etc., or a volatile memory such as a dynamic random access memory (DRAM), a static random access memory (SRAM), etc. However, the present disclosure is not limited thereto, and the semiconductor chip 200 may include various active elements, passive elements, logic circuits, etc.

[0025] The substrate 100 may have a wiring structure for transmitting a power supply voltage, a ground voltage, and a signal to the semiconductor chip 200. As an example, the substrate 100 includes a base layer 110, an upper wiring layer L1 and an upper insulating layer 140 formed over an upper surface 111 of the base layer 110, and a lower wiring layer L2 and a lower insulating layer 150 formed over a lower surface 112 of the base layer 110.

[0026] The base layer 110 may have a plate shape including an upper surface 111 facing the semiconductor chip 200, a lower surface 112 disposed opposite to the upper surface 111, and a side surface connecting the upper surface 111 and the lower surface 112. The base layer 110 may form a body or core of the substrate 100, and may include an insulating material such as epoxy, polyimide, or the like.

[0027] The upper wiring layer L1 may be formed above the upper surface 111 of the base layer 110. The upper wiring layer L1 may have various shapes and may include a plurality of conductive patterns receiving various power supplies or signals. The conductive patterns may include various conductive materials such as metals, metal nitrides, etc. As an example, further reference is made to Figure 1A , the upper wiring layer L1 may include an upper ground electrode plate 120A and an upper power electrode plate 120B formed adjacent to each other while being spaced apart from each other. Specifically, the upper ground electrode plate 120A may be disposed on one side (e.g., the left side) in the second direction, and the upper power electrode plate 120B may be disposed on the other side (e.g., the right side) in the second direction.

[0028] The upper ground electrode plate 120A may be used to transmit a ground voltage to the semiconductor chip 200 and may have a plate shape. Figure 1A and Figure 1C , the upper ground electrode plate 120A may overlap the first region 200A of the semiconductor chip 200 and be connected to the first ground terminal 214. For convenience of description, the connection between the upper ground electrode plate 120A and the first ground terminal 214A will be described after describing the first upper power pattern 122A and the first upper signal pattern 123A.

[0029] Refer to Figure 1A , Figure 1C and Figure 5 , a first upper power pattern 122A may be formed in the upper ground electrode plate 120A.

[0030] The first upper power pattern 122A can be used to transmit the power supply voltage to the semiconductor chip 200. Specifically, the first upper power pattern 122A can overlap with the first region 200A of the semiconductor chip 200 and be connected to the first power terminal 212A. The reason for forming the first upper power pattern 122A in the upper ground electrode plate 120A is because the first power terminal 212A is arranged in the first region 200A of the semiconductor chip 200 overlapping with the upper ground electrode plate 120A. If the first upper power pattern 122A does not exist in the upper ground electrode plate 120A, a power supply path should be formed from the upper power electrode plate 120B to the first power terminal 212A that does not overlap with the upper power electrode plate 120B. Therefore, in this case, the problem that the length of the power supply path is long and the formation process of the power supply path is difficult may occur. However, in the present embodiment, this problem can be solved.

[0031] In a plan view, the first upper power pattern 122A may have an island shape. Here, the island shape may mean an isolated shape that is not connected to other components. The first upper power pattern 122A may be in a state where the side surface is surrounded by the upper ground electrode plate 120A and is spaced apart from the upper ground electrode plate 120A. Since the first upper power pattern 122A and the upper ground electrode plate 120A are insulated from each other, the space between the first upper power pattern 122A and the upper ground electrode plate 120A may be filled by the upper insulating layer 140.

[0032] The lower surface of the first upper power pattern 122A may be connected to the first power through-hole 162A (to be described later), and the upper surface of the first upper power pattern 122A may be connected to the first power terminal 212A. Specifically, in order to connect the first upper power pattern 122A and the first power terminal 212A, a portion of the upper surface of the first upper power pattern 122A may be exposed through an opening formed in the upper insulating layer 140. The portion of the upper surface of the first upper power pattern 122A exposed through the opening will be referred to as the first upper power pad 122A-P. The first power terminal 212A may contact the first upper power pad 122A-P through the opening formed in the upper insulating layer 140. In a plan view, the first upper power pattern 122A may have a strip shape that is longer in the second direction and shorter in the first direction. Specifically, as Figure 1A As shown in the plan view of , the first upper power pattern 122A may include a line portion and an end portion. The line portion may extend in the second direction and have a relatively narrow width. The end portion may be located at both ends of the line portion and have a relatively large width compared to the line portion. In this case, one end portion (e.g., the left end portion) may overlap and / or connect with the first power through hole 162A, and the other end portion (e.g., the right end portion) may overlap and / or connect with the first power terminal 212A.

[0033] In addition, refer to Figure 1A , Figure 1C and Figure 4 , the first upper signal pattern 123A may be formed in the upper ground electrode plate 120A.

[0034] The first upper signal pattern 123A can be used to transmit a signal to the semiconductor chip 200. Specifically, the first upper signal pattern 123A may overlap with the first region 200A of the semiconductor chip 200 and be connected to the first signal terminal 213A. The reason for forming the first upper signal pattern 123A in the upper ground electrode plate 120A is because the first signal terminal 213A is disposed in the first region 200A of the semiconductor chip 200 that overlaps with the upper ground electrode plate 120A. If the first upper signal pattern 123A does not exist in the upper ground electrode plate 120A, a signal transmission path should be formed via another place. Therefore, in this case, there may be a problem that the length of the signal transmission path is long and the formation process of the signal transmission path is difficult. However, in the present embodiment, this problem can be solved.

[0035] The first upper signal pattern 123A may have the same or similar shape as the first upper power pattern 122A. The first upper signal pattern 123A may have an island shape, and the side surface of the first upper signal pattern 123A may be surrounded by the upper ground electrode plate 120A. However, since the first upper signal pattern 123A and the upper ground electrode plate 120A are insulated from each other, the first upper signal pattern 123A and the upper ground electrode plate 120A may be spaced apart from each other, and the space between the first upper signal pattern 123A and the upper ground electrode plate 120A may be filled by the upper insulating layer 140.

[0036] The lower surface of the first upper signal pattern 123A may be connected to the first signal via 163A (to be described later), and the upper surface of the first upper signal pattern 123A may be connected to the first signal terminal 213A. Specifically, in order to connect the first upper signal pattern 123A and the first signal terminal 213A, a portion of the upper surface of the first upper signal pattern 123A may be exposed through an opening formed in the upper insulating layer 140. The portion of the upper surface of the first upper signal pattern 123A exposed through the opening will be referred to as the first upper signal pad 123A-P. The first signal terminal 213A may contact the first upper signal pad 123A-P through the opening formed in the upper insulating layer 140. In a plan view, the first upper signal pattern 123A may have a strip shape that is longer in the second direction and shorter in the first direction. Specifically, as Figure 1AAs shown in the plan view of , the first upper signal pattern 123A may include a line portion and an end portion. The line portion may extend in the second direction and have a relatively narrow width. The end portion may be located at both ends of the line portion and have a relatively large width compared to the line portion. One end portion (e.g., the left end portion) may overlap and / or be connected to the first signal via 163A, and the other end portion (e.g., the right end portion) may overlap and / or be connected to the first signal terminal 213A.

[0037] In addition, refer to Figure 1A , Figure 1C and Figure 6 , since the upper ground electrode plate 120A overlaps with the first ground terminal 214A, it is not necessary to form an additional ground pattern in the upper ground electrode plate 120A. However, in order to connect the upper ground electrode plate 120A and the first ground terminal 214A, a portion of the upper surface of the upper ground electrode plate 120A may be exposed through an opening formed in the upper insulating layer 140. The portion of the upper surface of the upper ground electrode plate 120A exposed through the opening will be referred to as the first upper ground pad 124A-P. The lower surface of the upper ground electrode plate 120A may be connected to the first ground through hole 164A (to be described later). For convenience of description, a virtual area having an island shape and overlapping both the first upper ground pad 124A-P and the first ground through hole 164A is indicated by a solid line and will be referred to as the first upper ground pattern 124A. The first upper ground pattern 124A is a portion of the upper ground electrode plate 120A and is shown as the same shape as the first upper power pattern 122A and / or the first upper signal pattern 123A.

[0038] The first upper power pattern 122A, the first upper signal pattern 123A, and the first upper ground pattern 124A may overlap the first region 200A of the semiconductor chip 200 and be arranged in a row along the first direction, as shown in FIG. Figure 1A As shown. Both ends of the first upper power pattern 122A, both ends of the first upper signal pattern 123A, and both ends of the first upper ground pattern 124A may be aligned with each other. Therefore, the first upper power pads 122A-P, the first upper signal pads 123A-P, and the first upper ground pads 124A-P may be arranged in a row along the first direction and connected to Figure 1C The first power terminal 212A, the first signal terminal 213A, and the first ground terminal 214A of the semiconductor chip 200. As an example, the first power via 162A, the first signal via 163A, and the first ground via 164A may be arranged in a row along the first direction.

[0039] In addition, refer to Figure 1A , Figure 2 , Figure 4 , Figure 5 and Figure 6, a dummy power pattern 121A may be further formed in the upper ground electrode plate 120A. The dummy power pattern 121A may be electrically connected to a power supply portion (e.g., a lower power pattern 135A to be described later). The dummy power pattern 121A may not be used to transmit the power voltage to the semiconductor chip 200, but may be used together with the upper ground electrode plate 120A to implement a decoupling capacitor. Therefore, it is referred to as a dummy power pattern 121A to distinguish it from a power electrode plate and / or a power pattern for transmitting the power voltage. The lower surface of the dummy power pattern 121A may be connected to a dummy power through hole 161A. The upper surface of the dummy power pattern 121A may be covered by an upper insulating layer 140.

[0040] The dummy power pattern 121A may have an island shape, and the side surface of the dummy power pattern 121A may be surrounded by the upper ground electrode plate 120A. However, since the dummy power pattern 121A and the upper ground electrode plate 120A are insulated from each other, the dummy power pattern 121A and the upper ground electrode plate 120A may be spaced apart from each other, and the space between the dummy power pattern 121A and the upper ground electrode plate 120A may be filled by the upper insulating layer 140. The dummy power pattern 121A, the upper ground electrode plate 120A, and the upper insulating layer 140 therebetween may form a decoupling capacitor. The dummy power pattern 121A may have a strip shape having a relatively short length in the first direction and a relatively long length in the second direction. This is to improve the capacitance of the decoupling capacitor by increasing the area of ​​the side surface of the dummy power pattern 121A. Specifically, as Figure 1A As shown in the plan view of , the dummy power pattern 121A may have a line portion and an end portion. The line portion may extend in the second direction and have a relatively narrow width. The end portion may be located at both ends of the line portion and have a relatively large width compared to the line portion. In this case, the end portions of the dummy power pattern 121A may overlap and / or be connected to the two dummy power through holes 161A, respectively. As an example, one of the two dummy power through holes 161A may be omitted.

[0041] In the present embodiment, the plurality of dummy power patterns 121A may be spaced apart from each other so that the capacitance of the decoupling capacitor may be further increased. In addition, the plurality of dummy power patterns 121A may be arranged in the first direction and may be aligned with each other. This is to increase the number of dummy power patterns 121A to improve the capacitance of the decoupling capacitor while reducing the area of ​​the region where the plurality of dummy power patterns 121A are formed.

[0042] The dummy power pattern 121A may be formed in an area other than the area where the first upper power pattern 122A, the first upper signal pattern 123A, and the first upper ground pattern 124A are formed. This is to allow the dummy power pattern 121A to avoid the power voltage transmission path through the first upper power pattern 122A, the signal transmission path through the first upper signal pattern 123A, and the ground voltage transmission path through the first upper ground pattern 124A. When the dummy power pattern 121A is located in the power voltage transmission path, the signal transmission path, or the ground voltage transmission path, it may interrupt the transmission of the power voltage, the signal, or the ground voltage. As an example, the dummy power pattern 121A may be set in an area of ​​the upper ground electrode plate 120A that does not overlap with the semiconductor chip 200.

[0043] Let’s refer to it together Figure 1A and Figure 1C , the upper power electrode plate 120B may be used to transmit the power supply voltage to the semiconductor chip 200, and may have a plate shape. Specifically, the upper power electrode plate 120B may overlap with the second region 200B of the semiconductor chip 200 and be connected to the second power terminal 212B. For convenience of description, the connection between the upper power electrode plate 120B and the second power terminal 212B will be described after describing the second upper ground pattern 124B and the second upper signal pattern 123B.

[0044] Refer to Figure 1A , Figure 1C and Figure 5 , the second upper ground pattern 124B may be formed in the upper power electrode plate 120B.

[0045] The second upper ground pattern 124B may be used to transmit a ground voltage to the semiconductor chip 200. Specifically, the second upper ground pattern 124B may overlap with the second region 200B of the semiconductor chip 200 and be connected to the second ground terminal 214B. The reason why the second upper ground pattern 124B is formed in the upper power electrode plate 120B is because the second ground terminal 214B overlaps with the upper power electrode plate 120B.

[0046] The second upper ground pattern 124B may have an island shape, and a side surface of the second upper ground pattern 124B may be surrounded by the upper power electrode plate 120B. The second upper ground pattern 124B and the upper power electrode plate 120B may be spaced apart from each other, and a space between the second upper ground pattern 124B and the upper power electrode plate 120B may be filled by the upper insulating layer 140.

[0047] The lower surface of the second upper ground pattern 124B may be connected to a second ground via 164B (to be described later), and the upper surface of the second upper ground pattern 124B may be connected to the second ground terminal 214B. A portion of the upper surface of the second upper ground pattern 124B exposed through an opening formed in the upper insulating layer 140 for connection between the second upper ground pattern 124B and the second ground terminal 214B will be referred to as a second upper ground pad 124B-P. The second ground terminal 214B may contact the second upper ground pad 124B-P through an opening formed in the upper insulating layer 140. In a plan view, the second upper ground pattern 124B may have a strip shape that is longer in the second direction and shorter in the first direction. Specifically, as shown in FIG. Figure 1A As shown in the plan view of , the second upper ground pattern 124B may include a line portion and an end portion. The line portion may extend in the second direction and have a relatively narrow width. The end portion may be located at both ends of the line portion and have a relatively large width compared to the line portion. In this case, one end portion (e.g., the left end portion) may overlap and / or be connected to the second ground terminal 214B, and the other end portion (e.g., the right end portion) may overlap and / or be connected to the second ground through hole 164B.

[0048] In addition, refer to Figure 1A , Figure 1C and Figure 4 , the second upper signal pattern 123B may be formed in the upper power electrode plate 120B.

[0049] The second upper signal pattern 123B may be used to transmit a signal to the semiconductor chip 200. Specifically, the second upper signal pattern 123B may overlap with the second region 200B of the semiconductor chip 200 and be connected to the second signal terminal 213B. The reason why the second upper signal pattern 123B is formed in the upper power electrode plate 120B is because the second signal terminal 213B overlaps with the upper power electrode plate 120B.

[0050] The second upper signal pattern 123B may have an island shape, and a side surface of the second upper signal pattern 123 may be surrounded by the upper power electrode plate 120B. The second upper signal pattern 123B and the upper power electrode plate 120B may be spaced apart from each other, and a space between the second upper signal pattern 123B and the upper power electrode plate 120B may be filled with the upper insulating layer 140.

[0051] The lower surface of the second upper signal pattern 123B may be connected to the second signal via 163B (to be described later), and the upper surface of the second upper signal pattern 123B may be connected to the second signal terminal 213B. Specifically, a portion of the upper surface of the second upper signal pattern 123B exposed through an opening formed in the upper insulating layer 140 for connection between the second upper signal pattern 123B and the second signal terminal 213B will be referred to as a second upper signal pad 123B-P. The second signal terminal 213B may contact the second upper signal pad 123B-P through an opening formed in the upper insulating layer 140. In a plan view, the second upper signal pattern 123B may have a strip shape that is longer in the second direction and shorter in the first direction. Specifically, as Figure 1A As shown in the plan view of , the second upper signal pattern 123B may include a line portion and an end portion. The line portion may extend in the second direction and have a relatively narrow width. The end portion may be located at both ends of the line portion and have a relatively large width compared to the line portion. In this case, one end portion (e.g., the left end portion) may overlap and / or be connected to the second signal terminal 213B, and the other end portion (e.g., the right end portion) may overlap and / or be connected to the second signal via 163B.

[0052] Refer to Figure 1A , Figure 1C and Figure 6 , since the upper power electrode plate 120B overlaps with the second power terminal 212B, it is not necessary to form an additional power pattern in the upper power electrode plate 120B. In order to connect the upper power electrode plate 120B and the second power terminal 212B, a portion of the upper surface of the upper power electrode plate 120B may be exposed through an opening formed in the upper insulating layer 140. The portion of the upper surface of the upper power electrode plate 120B exposed through the opening will be referred to as the second upper power pad 122B-P. The lower surface of the upper power electrode plate 120B may be connected to the second power through hole 162B (to be described later). For ease of description, a virtual area having an island shape and overlapping both the second upper power pad 122B-P and the second power through hole 162B is represented by a solid line and will be referred to as the second upper power pattern 122B. The second upper power pattern 122B may be a portion of the upper power electrode plate 120B and is shown as the same shape as the second upper ground pattern 124B and / or the second upper signal pattern 123B.

[0053] The second upper power pattern 122B, the second upper signal pattern 123B, and the second upper ground pattern 124B may overlap the second region 200B of the semiconductor chip 200 and be arranged in a row along the first direction, such as Figure 1AAs shown. Both ends of the second upper power pattern 122B, both ends of the second upper signal pattern 123B, and both ends of the second upper ground pattern 124B may be aligned with each other. Therefore, the second upper power pad 122B-P, the second upper signal pad 123B-P, and the second upper ground pad 124B-P may be arranged in a row along the first direction and connected to Figure 2 The second power terminal 212B, the second signal terminal 213B, and the second ground terminal 214B of the semiconductor chip 200. As an example, the second power via 162B, the second signal via 163B, and the second ground via 164B may be arranged in a row along the first direction.

[0054] In addition, refer to Figure 1A , Figure 1C , Figure 4 , Figure 5 and Figure 6 , a dummy ground pattern 121B may be further formed in the upper power electrode plate 120B. The dummy ground pattern 121B may be electrically connected to a ground voltage supply portion (e.g., a lower ground pattern 135B to be described later). The dummy ground pattern 121B may not be used to transmit the ground voltage to the semiconductor chip 200, but may be used together with the upper power electrode plate 120B to realize a decoupling capacitor. Therefore, it is referred to as a dummy ground pattern 121B in order to distinguish it from a ground electrode plate and / or a ground pattern for transmitting a ground voltage. The lower surface of the dummy ground pattern 121B may be connected to a dummy ground via 161B. The upper surface of the dummy ground pattern 121B may be covered by an upper insulating layer 140.

[0055] The dummy ground pattern 121B may have an island shape, and a side surface of the dummy ground pattern 121B may be surrounded by the upper power electrode plate 120B. The dummy ground pattern 121B and the upper power electrode plate 120B may be spaced apart from each other, and a space between the dummy ground pattern 121B and the upper power electrode plate 120B may be filled by the upper insulating layer 140. The dummy ground pattern 121B, the upper power electrode plate 120B, and the upper insulating layer 140 therebetween may form a decoupling capacitor. The dummy ground pattern 121B may have a strip shape having a relatively short length in a first direction and a relatively long length in a second direction. In addition, as Figure 1A As shown in the plan view of , the dummy ground pattern 121B may include a line portion and an end portion. The line portion may extend in the second direction and have a relatively narrow width. The end portion may be located at both ends of the line portion and have a relatively large width compared to the line portion. In this case, the ends of the dummy ground pattern 121B may overlap and / or be connected to the two dummy ground vias 161B, respectively. As an example, one of the two dummy ground vias 161B may be omitted.

[0056] In the present embodiment, the plurality of dummy ground patterns 121B may be arranged to be spaced apart from each other. In addition, the plurality of dummy ground patterns 121B may be arranged in the first direction and may be aligned with each other.

[0057] The dummy ground pattern 121B is formed in an area other than an area where the second upper power pattern 122B, the second upper signal pattern 123B, and the second upper ground pattern 124B are formed. Therefore, the dummy ground pattern 124B can avoid a voltage or signal transmission path passing through the second upper power pattern 122B, the second upper signal pattern 123B, or the second upper ground pattern 124B. As an example, the dummy ground pattern 121B can be disposed in an area of ​​the upper power electrode plate 120B that does not overlap with the semiconductor chip 200.

[0058] The lower wiring layer L2 may be formed over the lower surface 112 of the base layer 110 and may include a plurality of conductive patterns receiving various power supplies or signals. Figure 1B , the lower wiring layer L2 may include a lower ground electrode plate 130A and a lower power electrode plate 130B formed adjacent to each other while being spaced apart from each other. The lower ground electrode plate 130A may be disposed on one side (e.g., the left side) in the second direction, and the lower power electrode plate 130B may be disposed on the other side (e.g., the right side) in the second direction.

[0059] Refer to Figure 1A and Figure 1B , the lower ground electrode plate 130A may be used to transmit the ground voltage to the upper ground electrode plate 120A (specifically, the first upper ground pattern 124A). To this end, the upper surface of the lower ground electrode plate 130A may be connected to the first ground through hole 164A. The lower ground electrode plate 130A may have a plate shape and may be disposed to overlap with the upper ground electrode plate 120A and face the upper ground electrode plate 120A.

[0060] Refer to Figure 1B , Figure 2 , Figure 3 , Figure 4 , Figure 5 and Figure 6 , a lower power pattern 135A may be formed in the lower ground electrode plate 130A.

[0061] The lower power pattern 135A can be used to transmit the power voltage to Figure 1AThe first upper power pattern 122A and the dummy power pattern 121A shown. To this end, the upper surface of the lower power pattern 135A may be connected to the dummy power through hole 161A and the first power through hole 162A. The lower power pattern 135A may include a plate portion and a protruding portion. The plate portion may overlap with a plurality of dummy power through holes 161A at the same time. The protruding portion may protrude in a direction toward the first power through hole 162A (e.g., in the right direction) for connection with the first power through hole 162A.

[0062] The lower power pattern 135A may have a side surface surrounded by the lower ground electrode plate 130A. The lower power pattern 135A and the lower ground electrode plate 130A may be spaced apart from each other, and a space therebetween may be filled with the lower insulating layer 150.

[0063] In addition, refer to Figure 1B and Figure 4 , the first lower signal pattern 133A may be formed in the lower ground electrode plate 130A.

[0064] The first lower signal pattern 133A can be used to transmit signals to Figure 1A The first upper signal pattern 123A shown. To this end, the upper surface of the first lower signal pattern 133A may be connected to the first signal through hole 163A. The first lower signal pattern 133A may include one end for connecting to the first signal through hole 163A, a line portion extending from the one end in a predetermined direction, and the other end disposed opposite to the one end while being connected to the line portion. The first lower signal pattern 133A may extend in any direction within the lower ground electrode plate 130A except for the area occupied by the lower power pattern 135A and the first ground through hole 164A.

[0065] The side surface of the first lower signal pattern 133A may be surrounded by the lower ground electrode plate 130A. The first lower signal pattern 133A and the lower ground electrode plate 130A may be spaced apart from each other, and a space therebetween may be filled with the lower insulating layer 150.

[0066] In addition, refer to Figure 1B and Figure 3, the lower surfaces of the lower ground electrode plate 130A, the lower power pattern 135A, and the first lower signal pattern 133A may be connected to the external connection terminal 300. For the connection between the lower ground electrode plate 130A and the external connection terminal 300, a portion of the lower surface of the lower ground electrode plate 130A may be exposed through an opening formed in the lower insulating layer 150. The portion of the lower surface of the lower ground electrode plate 130A exposed through the opening will be referred to as a first lower ground pad 130A-P. In addition, a portion of the lower surface of the lower power pattern 135A exposed through an opening formed in the lower insulating layer 150 for connection between the lower power pattern 135A and the external connection terminal 300 will be referred to as a first lower power pad 135A-P. In addition, a portion of the lower surface of the first lower signal pattern 133A exposed through an opening formed in the lower insulating layer 150 for connection between the first lower signal pattern 133A and the external connection terminal 300 will be referred to as a first lower signal pad 133A-P.

[0067] The first lower ground pads 130A-P, the first lower signal pads 133A-P, and the first lower power pads 135A-P may have a much larger Figure 1A The pads 122A-P, 123A-P and 124A-P of the upper wiring layer L1 have a large plane area. This is because the first lower ground pads 130A-P, the first lower signal pads 133A-P and the first lower power pads 135A-P are used as ball pads for connection with solder balls used as external connection terminals 300.

[0068] Therefore, refer to Figures 1A to 1C , a current path for transmitting a ground voltage may be formed from the external connection terminal 300 connected to the first lower ground pad 130A-P to the first ground terminal 214A of the semiconductor chip 200 (see arrow ①). Specifically, the current path ① may be formed to pass through the external connection terminal 300 connected to the first lower ground pad 130A-P, the lower ground electrode plate 130A, the first ground via 164A, the first upper ground pattern 124A, and the first ground terminal 214A connected to the first upper ground pad 124A-P. Here, the current path ① is generally formed to have the shortest length. This is because the current flows in the path with the lowest resistance (i.e., the shortest path). Therefore, the current path ① in the lower ground electrode plate 130A may be shifted from the lower power pattern 135A or the first lower signal pattern 133A, and may have the shortest path from the first lower ground pad 130A-P to the first ground via 164A. The first lower ground pad 130A-P may be located anywhere in the lower ground electrode plate 130A.

[0069] In addition, a current path (see arrow ②) for transmitting a signal may be formed from the external connection terminal 300 connected to the first lower signal pads 133A-P to the first signal terminal 213A of the semiconductor chip 200. Specifically, the current path ② may be formed to pass through the external connection terminal 300 connected to the first lower signal pads 133A-P, the first lower signal pattern 133A, the first signal via 163A, the first upper signal pattern 123A, and the first signal terminal 213A connected to the first upper signal pads 123A-P.

[0070] In addition, a current path for transmitting a power supply voltage may be formed from the external connection terminal 300 connected to the first lower power supply pad 135A-P to the first power supply terminal 212A of the semiconductor chip 200 (see arrow ③). Specifically, the current path ③ may be formed to pass through the external connection terminal 300 connected to the first lower power supply pad 135A-P, the lower power supply pattern 135A, the first power supply through hole 162A, the first upper power supply pattern 122A, and the first power supply terminal 212A connected to the first upper power supply pad 122A-P. Generally, the current path ③ may be formed to have the shortest length. Therefore, the current path ③ in the lower power supply pattern 135A may have a straight path connecting the first lower power supply pad 135A-P and the first power supply through hole 162A.

[0071] In addition, as described above, the area where the dummy power pattern 121A is formed should avoid the current path for transmitting the power supply voltage, the ground voltage and the signal. The current path ① and the current path ② cannot meet the area where the dummy power pattern 121A is formed. However, the current path ③ can meet the area where the dummy power pattern 121A is formed. This is because the dummy power through hole 161A connected to the dummy power pattern 121A and the first power through hole 162A connected to the first upper power pattern 122A both overlap and connect with the lower power pattern 135A. Therefore, when the area surrounding all the multiple dummy power through holes 161A is referred to as the dummy power area DP, the first lower power pad 135A-P may be located outside the dummy power area DP. In addition, the current path ③ in the lower power pattern 135A may be located outside the dummy power area DP.

[0072] Refer to Figure 1A and Figure 1B , the lower power electrode plate 130B can be used to transmit the power voltage to the upper power electrode plate 120B (specifically, the second upper power pattern 122B). To this end, the upper surface of the lower power electrode plate 130B can be connected to the second power through hole 162B. The lower power electrode plate 130B can have a plate shape and can be arranged to overlap with the upper power electrode plate 120B and face the upper power electrode plate 120B.

[0073] Refer to Figure 1B , Figure 4 , Figure 5 and Figure 6 , a lower ground pattern 135B may be formed in the lower power electrode plate 130B.

[0074] The lower ground pattern 135B can be used to transmit the ground voltage to Figure 1A The second upper ground pattern 124B and the dummy ground pattern 121B are provided. To this end, the upper surface of the lower ground pattern 135B may be connected to the dummy ground via 161B and the second ground via 164B. The lower ground pattern 135B may include a plate portion and a protruding portion. The plate portion may overlap with a plurality of dummy ground vias 161B at the same time. The protruding portion may protrude in a direction toward the second ground via 164B (e.g., in a left direction) for connection with the second ground via 164B.

[0075] The lower ground pattern 135B may have a side surface surrounded by the lower power electrode plate 130B. The lower ground pattern 135B and the lower power electrode plate 130B may be spaced apart from each other, and a space therebetween may be filled with the lower insulating layer 150.

[0076] In addition, refer to Figure 1B and Figure 4 , the second lower signal pattern 133B may be formed in the lower power electrode plate 130B.

[0077] The second lower signal pattern 133B can be used to transmit signals to Figure 1A The second upper signal pattern 123B is formed by a second grounding pattern 135B and a second power supply through hole 162B. To this end, the upper surface of the second lower signal pattern 133B may be connected to the second signal through hole 163B. The second lower signal pattern 133B may include one end for connecting to the second signal through hole 163B, a line portion extending from the one end in a predetermined direction, and the other end disposed opposite to the one end while being connected to the line portion. The second lower signal pattern 133B may extend in any direction in the lower power electrode plate 130B except for the area occupied by the lower ground pattern 135B and the second power supply through hole 162B.

[0078] The side surface of the second lower signal pattern 133B may be surrounded by the lower power electrode plate 130B. The second lower signal pattern 133B and the lower power electrode plate 130B may be spaced apart from each other, and a space therebetween may be filled with the lower insulating layer 150.

[0079] In addition, refer to Figure 1B and Figure 3, the lower surfaces of the lower power electrode plate 130B, the lower ground pattern 135B, and the second lower signal pattern 133B may be connected to the external connection terminal 300. A portion of the lower surface of the lower power electrode plate 130B exposed through an opening formed in the lower insulating layer 150 for connection between the lower power electrode plate 130B and the external connection terminal 300 will be referred to as a second lower power pad 130B-P. In addition, a portion of the lower surface of the lower ground pattern 135B exposed through an opening formed in the lower insulating layer 150 for connection between the lower ground pattern 135B and the external connection terminal 300 will be referred to as a second lower ground pad 135B-P. In addition, a portion of the lower surface of the second lower signal pattern 133B exposed through an opening formed in the lower insulating layer 150 for connection between the second lower signal pattern 133B and the external connection terminal 300 will be referred to as a second lower signal pad 133B-P.

[0080] Therefore, refer to Figures 1A to 1C , a current path for transmitting a power supply voltage may be formed from the external connection terminal 300 connected to the second lower power supply pad 130B-P to the second power supply terminal 212B of the semiconductor chip 200 (see arrow ④).

[0081] In addition, a current path for transmitting a signal may be formed from the external connection terminal 300 connected to the second lower signal pad 133B-P to the second signal terminal 213B of the semiconductor chip 200 (see arrow ⑤).

[0082] In addition, a current path for transmitting a ground voltage may be formed from the external connection terminal 300 connected to the second lower ground pad 135B-P to the second ground terminal 214B of the semiconductor chip 200 (see arrow ⑥). Specifically, when the area surrounding all the plurality of dummy ground vias 161B is referred to as a dummy ground area DG, the second lower ground pad 135B-P may be located outside the dummy ground area DG. In addition, the current path ⑥ in the lower ground pattern 135B may be located outside the dummy ground area DG.

[0083] The upper wiring layer L1 and the lower wiring layer L2 may be connected to each other through a conductive via that penetrates the base layer 110. The conductive via may be formed of a conductive material such as metal. Figure 1A , Figure 1B and Figure 6 , the upper ground electrode plate 120A and the lower ground electrode plate 130A may be connected via the first grounding through hole 164A. Figure 1A , Figure 1B , Figure 2 , Figure 4 , Figure 5 and Figure 6, the dummy power pattern 121A and the lower power pattern 135A may be connected via a dummy power through hole 161A. Figure 1A , Figure 1B and Figure 5 , the first upper power pattern 122A and the lower power pattern 135A may be connected through the first power through hole 162A. Figure 1A , Figure 1B and Figure 4 , the first upper signal pattern 123A and the first lower signal pattern 133A may be connected through the first signal via 163A. Figure 1A , Figure 1B and Figure 6 , the upper power electrode plate 120B and the lower power electrode plate 130B may be connected via the second power through hole 162B. Figure 1A , Figure 1B and Figure 4 , the second upper signal pattern 123B and the second lower signal pattern 133B may be connected through the second signal via 163B. Figure 1A , Figure 1B , Figure 4 , Figure 5 and Figure 6 , the dummy ground pattern 121B and the lower ground pattern 135B may be connected via a dummy ground via 161B. Figure 1A , Figure 1B and Figure 5 , the second upper ground pattern 124B and the lower ground pattern 135B may be connected through the second ground via 164B.

[0084] Refer to Figures 2 to 6 The upper insulating layer 140 and the lower insulating layer 150 may include various openings to expose necessary portions of the upper wiring layer L1 and the lower wiring layer L2. The upper insulating layer 140 and the lower insulating layer 150 may include various insulating materials such as solder resist.

[0085] In addition, refer to Figure 3 , the semiconductor package of the present disclosure may further include an external connection terminal 300 .

[0086] The external connection terminal 300 may include a solder ball, but the present disclosure is not limited thereto, and conductive patterns of various shapes and materials may be used as the external connection terminal 300. In addition, an interface layer 310 may be further formed between the external connection terminal 300 and the lower wiring layer L2 to improve the adhesive properties therebetween and mitigate thermal and mechanical shocks. The interface layer 310 may include a metal such as nickel (Ni) or gold (Au).

[0087] Refer to Figures 2 to 6, the semiconductor package of the present embodiment may further include a sealant 400. The sealant 400 may be formed over the substrate 100 to surround the semiconductor chip 200. The sealant 400 may include various molding materials such as EMC (Epoxy Molding Compound) or the like.

[0088] The above-mentioned semiconductor package has the following advantages.

[0089] First, a dummy power pattern independent of power supply can be formed in the ground electrode plate of the substrate. Therefore, a decoupling capacitor formed by the ground electrode plate, the dummy power pattern and the insulating material therebetween can be realized. In addition, a dummy ground pattern independent of ground supply can be formed in the ground electrode plate of the substrate. Therefore, a decoupling capacitor formed by the power electrode plate, the dummy ground pattern and the insulating material therebetween can be realized. As a result, the power supply / ground voltage supply characteristics of the semiconductor chip can be improved.

[0090] Furthermore, by arranging the dummy power pattern and / or the dummy ground pattern separately from the current path between the semiconductor chip and the substrate, the dummy power pattern and / or the dummy ground pattern cannot interfere with current transfer between the semiconductor chip and the substrate.

[0091] In addition, a power pattern and a signal pattern overlapping with the semiconductor chip can be additionally formed in the ground electrode plate, and a ground pattern and a signal pattern overlapping with the semiconductor chip can be additionally formed in the power electrode plate. Therefore, current transmission between the semiconductor chip and the substrate can be more efficient.

[0092] Figure 7 is a plan view illustrating shapes of a dummy power pattern and a ground electrode plate according to another embodiment of the present disclosure.

[0093] Reference Figure 7 The dummy power pattern 121A' of the present embodiment may include a line portion LP1 and end portions E1 and E2. The line portion LP1 may extend in the second direction. The end portions E1 and E2 may be located at both ends of the line portion LP1 and overlap the dummy power via 161A'.

[0094] Here, in the line portion LP1 of the dummy power pattern 121A', both side surfaces in the first direction may have an uneven shape. Figure 7 As shown, the line portion LP1 may include a convex portion L1 - 1 protruding toward the upper ground electrode plate 120A′ and a concave portion L1 - 2 recessed toward the opposite side of the upper ground electrode plate 120A′.

[0095] The upper ground electrode plate 120A' may be formed to be spaced apart from the dummy power pattern 121A', and may be formed along the side profile of the dummy power pattern 121A'. Therefore, the side surface of the upper ground electrode plate 120A' may have an uneven shape. That is, a portion of the upper ground electrode plate 120A' corresponding to the concave portion L1-2 may protrude toward the line portion LP1, and another portion of the upper ground electrode plate 120A' corresponding to the convex portion L1-1 may be recessed away from the line portion LP1.

[0096] Unlike shown, the number or shape of the convex portion L1-1 and the concave portion L1-2 of the line portion LP1 may be modified differently. In addition, in the present embodiment, both sides of the line portion LP1 in the first direction have uneven shapes, but one of the two sides may have an uneven shape and the other may have a straight shape.

[0097] According to the present embodiment, since the opposing area between the side surface of the dummy power pattern 121A′ and the side surface of the upper ground electrode plate 120A′ increases, the capacitance of the decoupling capacitor formed thereby may be further increased.

[0098] Although not shown, the upper power electrode plate and the dummy ground pattern formed therein may have shapes similar to those of the upper ground electrode plate 120A' and the dummy power pattern 121A', respectively.

[0099] According to an embodiment of the present disclosure, decoupling capacitors are implemented in a substrate of a semiconductor package in vertical and horizontal directions to facilitate power supply.

[0100] Figure 8 A block diagram illustrating an electronic system including a memory card 7800 employing at least one of the semiconductor packages according to the embodiments is shown. The memory card 7800 includes a memory 7810 such as a nonvolatile memory device and a memory controller 7820. The memory 7810 and the memory controller 7820 may store data or read out stored data. At least one of the memory 7810 and the memory controller 7820 may include at least one of the semiconductor packages according to the described embodiments.

[0101] The memory 7810 may include a nonvolatile memory device to which the technology of the embodiments of the present disclosure is applied. The memory controller 7820 may control the memory 7810 so that stored data is read out or data is stored in response to a read / write request from the host 7830 .

[0102] Fig. 9A block diagram illustrating an electronic system 8710 including at least one of the semiconductor packages according to the described embodiments is shown. The electronic system 8710 may include a controller 8711, an input / output device 8712, and a memory 8713. The controller 8711, the input / output device 8712, and the memory 8713 may be connected to each other through a bus 8715 that provides a path for data movement.

[0103] In an embodiment, the controller 8711 may include one or more microprocessors, digital signal processors, microcontrollers, and / or logic devices capable of performing the same functions as these components. The controller 8711 or the memory 8713 may include one or more of the semiconductor packages according to the embodiments of the present disclosure. The input / output device 8712 may include at least one selected from a keypad, a keyboard, a display device, a touch screen, etc. The memory 8713 is a device for storing data. The memory 8713 may store data and / or commands to be executed by the controller 8711, etc.

[0104] The memory 8713 may include a volatile memory device such as a DRAM and / or a non-volatile memory device such as a flash memory. For example, the flash memory may be installed in an information processing system such as a mobile terminal or a desktop computer. The flash memory may constitute a solid state disk (SSD). In this case, the electronic system 8710 may stably store a large amount of data in the flash memory system.

[0105] The electronic system 8710 may also include an interface 8714 configured to send data to and receive data from a communication network. The interface 8714 may be of a wired or wireless type. For example, the interface 8714 may include an antenna or a wired or wireless transceiver.

[0106] The electronic system 8710 may be implemented as a mobile system, a personal computer, an industrial computer, or a logic system that performs various functions. For example, the mobile system may be any one of a personal digital assistant (PDA), a portable computer, a tablet computer, a mobile phone, a smart phone, a wireless phone, a laptop computer, a memory card, a digital music system, and an information transmission / reception system.

[0107] If the electronic system 8710 represents a device capable of performing wireless communications, the electronic system 8710 can be used in a communication system using technology such as CDMA (Code Division Multiple Access), GSM (Global System for Mobile Communications), NADC (North American Digital Cellular), E-TDMA (Enhanced Time Division Multiple Access), WCDMA (Wideband Code Division Multiple Access), CDMA2000, LTE (Long Term Evolution), or Wibro (Wireless Broadband Internet).

[0108] Although various embodiments have been described for purposes of illustration, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the present disclosure as defined in the following claims.

[0109] CROSS-REFERENCE TO RELATED APPLICATIONS

[0110] This application claims priority to Korean Patent Application No. 10-2020-0045885, filed on Apr. 16, 2020, which is hereby incorporated by reference in its entirety.

Claims

1. A semiconductor package, comprising: substrate; as well as a semiconductor chip disposed above the substrate, Wherein, the substrate comprises: a base layer, the base layer comprising an upper surface facing the semiconductor chip; an upper ground electrode plate disposed over the upper surface of the base layer and configured to transmit a ground voltage to the semiconductor chip; and a dummy power pattern disposed in the upper ground electrode plate and having a side surface surrounded by and spaced apart from the upper ground electrode plate, with an insulating material between the dummy power pattern and the upper ground electrode plate, and Wherein, a ground voltage transmission path from the upper ground electrode plate to the semiconductor chip is spaced apart from the dummy power pattern.

2. The semiconductor package according to claim 1, wherein The dummy power pattern includes a plurality of dummy power patterns spaced apart from each other, and The ground voltage transmission path is spaced apart from a region surrounding the plurality of dummy power patterns.

3. The semiconductor package according to claim 1, wherein: The dummy power pattern has a bar shape having a relatively short length in a first direction and a relatively long length in a second direction perpendicular to the first direction in a plan view.

4. The semiconductor package according to claim 3, wherein: The dummy power pattern includes a plurality of dummy power patterns spaced apart from each other, and The plurality of dummy power patterns are arranged in a row in the first direction.

5. The semiconductor package according to claim 3, wherein: The side surface of the dummy power pattern includes a concave portion and a convex portion.

6. The semiconductor package according to claim 1, wherein The semiconductor chip includes a first ground terminal provided on a lower surface of the semiconductor chip facing the substrate, The first ground terminal overlaps and connects with a portion of the upper surface of the upper ground electrode plate, and The dummy power pattern is disposed in a region not overlapping the semiconductor chip.

7. The semiconductor package according to claim 1, wherein: The substrate further comprises: a first upper signal pattern and a first upper power pattern, each of which is disposed in the upper ground electrode plate and has a side surface surrounded by the upper ground electrode plate and spaced apart from the upper ground electrode plate by an insulating material, and wherein the first upper signal pattern is configured to transmit a signal to the semiconductor chip, The first upper power pattern is configured to transmit a power voltage to the semiconductor chip, and A signal transmission path from the first upper signal pattern to the semiconductor chip and a power supply voltage transmission path from the first upper power supply pattern to the semiconductor chip are spaced apart from the dummy power supply pattern.

8. The semiconductor package according to claim 7, wherein: The semiconductor chip includes a first signal terminal and a first power terminal provided on a lower surface of the semiconductor chip facing the substrate, The first signal terminal overlaps and connects with a portion of an upper surface of the first upper signal pattern, The first power terminal overlaps and connects with a portion of an upper surface of the first upper power pattern, and The dummy power pattern is disposed in a region not overlapping the semiconductor chip.

9. The semiconductor package according to claim 1, wherein: The substrate further comprises: a lower grounding electrode plate disposed on a lower surface of the base layer disposed opposite to the upper surface of the base layer and overlapping the upper grounding electrode plate; a first grounding through hole penetrating the base layer and having two ends connected to the upper grounding electrode plate and the lower grounding electrode plate, respectively, the first grounding through hole being configured to transmit the grounding voltage from the lower grounding electrode plate to the upper grounding electrode plate; a lower power pattern disposed in the lower ground electrode plate and having a side surface surrounded by and spaced apart from the lower ground electrode plate, and having an insulating material between the lower power pattern and the lower ground electrode plate; and A dummy power via penetrates the base layer and has two ends respectively connected to the dummy power pattern and the lower power pattern, the dummy power via being configured to transfer a power voltage from the lower power pattern to the dummy power pattern.

10. The semiconductor package according to claim 9, wherein The dummy power pattern includes a plurality of dummy power patterns spaced apart from each other, The dummy power via includes a plurality of dummy power vias respectively connected to the plurality of dummy power patterns, and The lower power pattern has a plate shape overlapping all of the plurality of dummy power vias.

11. The semiconductor package according to claim 9, wherein: The substrate further comprises: a first upper power pattern disposed in the upper ground electrode plate and having a side surface surrounded by and spaced apart from the upper ground electrode plate, and having an insulating material therebetween; and a first power via hole penetrating the base layer and having two ends connected to the first upper power pattern and the lower power pattern, respectively, the first power via hole being configured to transmit the power voltage from the lower power pattern to the first upper power pattern, Wherein, a power voltage transmission path from the lower power pattern to the first power via is spaced apart from the dummy power via.

12. The semiconductor package according to claim 9, wherein: The substrate further comprises: a first upper signal pattern disposed in the upper ground electrode plate and having a side surface surrounded by and spaced apart from the upper ground electrode plate, and having an insulating material between the first upper signal pattern and the upper ground electrode plate; a first lower signal pattern disposed in the lower ground electrode plate and having a side surface surrounded by and spaced apart from the lower ground electrode plate, and having an insulating material therebetween; and A first signal via penetrates the base layer and has two ends respectively connected to the first upper signal pattern and the first lower signal pattern.

13. The semiconductor package according to claim 1, wherein The substrate further comprises: an upper power electrode plate disposed on the upper surface of the base layer to be spaced apart from the upper ground electrode plate and configured to transmit a power supply voltage to the semiconductor chip; and a dummy ground pattern disposed in the upper power electrode plate and having a side surface surrounded by and spaced apart from the upper power electrode plate, and having an insulating material between the dummy ground pattern and the upper power electrode plate, Wherein, a power supply voltage transmission path from the upper power supply electrode plate to the semiconductor chip is spaced apart from the dummy ground pattern.

14. The semiconductor package according to claim 13, wherein: The dummy ground pattern includes a plurality of dummy ground patterns spaced apart from each other, and The power voltage transmission path is spaced apart from a region surrounding the plurality of dummy ground patterns.

15. The semiconductor package according to claim 13, wherein: The dummy ground pattern has a bar shape having a relatively short length in a first direction and a relatively long length in a second direction perpendicular to the first direction in a plan view.

16. The semiconductor package according to claim 15, wherein: The dummy ground pattern includes a plurality of dummy ground patterns spaced apart from each other, and The plurality of dummy ground patterns are arranged in a row in the first direction.

17. The semiconductor package according to claim 15, wherein: The side surface of the dummy ground pattern includes a concave portion and a convex portion.

18. The semiconductor package according to claim 13, wherein: The semiconductor chip includes a second power supply terminal provided on a lower surface of the semiconductor chip facing the substrate, The second power terminal overlaps and connects with a portion of the upper surface of the upper power electrode plate, and The dummy ground pattern is disposed in a region not overlapping the semiconductor chip.

19. The semiconductor package according to claim 13, wherein: The substrate further comprises: a second upper signal pattern and a second upper ground pattern, each of the second upper signal pattern and the second upper ground pattern being disposed in the upper power electrode plate and having a side surface surrounded by the upper power electrode plate and spaced apart from the upper power electrode plate by an insulating material, and wherein the second upper signal pattern is configured to transmit a signal to the semiconductor chip, The second upper ground pattern is configured to transmit the ground voltage to the semiconductor chip, and A signal transmission path from the second upper signal pattern to the semiconductor chip and a ground voltage transmission path from the second upper ground pattern to the semiconductor chip are spaced apart from the dummy ground pattern.

20. The semiconductor package according to claim 19, wherein The semiconductor chip includes a second signal terminal and a second ground terminal provided on a lower surface of the semiconductor chip facing the substrate, The second signal terminal overlaps and is connected to a portion of an upper surface of the second upper signal pattern, The second ground terminal overlaps and is connected to a portion of an upper surface of the second upper ground pattern, and The dummy ground pattern is disposed in a region not overlapping the semiconductor chip.

21. A semiconductor package, comprising: substrate; as well as a semiconductor chip disposed above the substrate, Wherein, the substrate comprises: a base layer, the base layer comprising an upper surface facing the semiconductor chip; an upper power electrode plate disposed over the upper surface of the base layer and configured to transmit a power voltage to the semiconductor chip; and a dummy ground pattern disposed in the upper power electrode plate and having a side surface surrounded by and spaced apart from the upper power electrode plate, and having an insulating material between the dummy ground pattern and the upper power electrode plate, and Wherein, a power supply voltage transmission path from the upper power supply electrode plate to the semiconductor chip is spaced apart from the dummy ground pattern.

22. The semiconductor package according to claim 21, wherein The dummy ground pattern includes a plurality of dummy ground patterns spaced apart from each other, and The power voltage transmission path is spaced apart from a region surrounding the plurality of dummy ground patterns.

23. The semiconductor package according to claim 21, wherein The dummy ground pattern has a bar shape having a relatively short length in a first direction and a relatively long length in a second direction perpendicular to the first direction in a plan view.

24. The semiconductor package according to claim 23, wherein: The dummy ground pattern includes a plurality of dummy ground patterns spaced apart from each other, and The plurality of dummy ground patterns are arranged in a row in the first direction.

25. The semiconductor package according to claim 23, wherein The side surface of the dummy ground pattern includes a concave portion and a convex portion.

26. The semiconductor package according to claim 21, wherein The semiconductor chip includes a second power supply terminal provided on a lower surface of the semiconductor chip facing the substrate, The second power terminal overlaps and connects with a portion of the upper surface of the upper power electrode plate, and The dummy ground pattern is disposed in a region not overlapping the semiconductor chip.

27. The semiconductor package according to claim 21, wherein The substrate further comprises: a second upper signal pattern and a second upper ground pattern, each of the second upper signal pattern and the second upper ground pattern being disposed in the upper power electrode plate and having a side surface surrounded by the upper power electrode plate and spaced apart from the upper power electrode plate by an insulating material, and wherein the second upper signal pattern is configured to transmit a signal to the semiconductor chip, The second upper ground pattern is configured to transmit a ground voltage to the semiconductor chip, and A signal transmission path from the second upper signal pattern to the semiconductor chip and a ground voltage transmission path from the second upper ground pattern to the semiconductor chip are spaced apart from the dummy ground pattern.

28. The semiconductor package according to claim 27, wherein The semiconductor chip includes a second signal terminal and a second ground terminal provided on a lower surface of the semiconductor chip facing the substrate, The second signal terminal overlaps and is connected to a portion of an upper surface of the second upper signal pattern, The second ground terminal overlaps and is connected to a portion of an upper surface of the second upper ground pattern, and The dummy ground pattern is disposed in a region not overlapping the semiconductor chip.

29. The semiconductor package according to claim 21, wherein The substrate further comprises: a lower power electrode plate disposed on a lower surface of the base layer that is disposed opposite to the upper surface of the base layer and overlaps the upper power electrode plate; a second power through hole, the second power through hole passing through the base layer and having two ends connected to the upper power electrode plate and the lower power electrode plate, respectively, the second power through hole being configured to transmit the power voltage from the lower power electrode plate to the upper power electrode plate; a lower ground pattern disposed in the lower power electrode plate and having a side surface surrounded by and spaced apart from the lower power electrode plate, and having an insulating material between the lower ground pattern and the lower power electrode plate; and A dummy ground via, which penetrates the base layer and has two ends respectively connected to the dummy ground pattern and the lower ground pattern, is configured to transfer a ground voltage from the lower ground pattern to the dummy ground pattern.

30. The semiconductor package according to claim 29, wherein The dummy ground pattern includes a plurality of dummy ground patterns spaced apart from each other, The dummy ground via includes a plurality of dummy ground vias respectively connected to the plurality of dummy ground patterns, and The lower ground pattern has a plate shape overlapping all of the plurality of dummy ground vias.

31. The semiconductor package according to claim 29, wherein The substrate further comprises: a second upper ground pattern disposed in the upper power electrode plate and having a side surface surrounded by and spaced apart from the upper power electrode plate, and having an insulating material therebetween; and a second ground via that penetrates the base layer and has two ends connected to the second upper ground pattern and the lower ground pattern, respectively, the second ground via being configured to transfer the ground voltage from the lower ground pattern to the second upper ground pattern, Wherein, a ground voltage transmission path from the lower ground pattern to the second ground via is spaced apart from the dummy ground via.

32. The semiconductor package according to claim 29, wherein The substrate further comprises: a second upper signal pattern disposed in the upper power electrode plate and having a side surface surrounded by and spaced apart from the upper power electrode plate, and having an insulating material between the second upper signal pattern and the upper power electrode plate; a second lower signal pattern disposed in the lower power electrode plate and having a side surface surrounded by and spaced apart from the lower power electrode plate, and having an insulating material therebetween; and A second signal via penetrates the base layer and has two ends respectively connected to the second upper signal pattern and the second lower signal pattern.

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