Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, wherein the structure comprises: a substrate, the substrate surface having a gate structure; source and drain openings in the substrate respectively located on both sides of the gate structure; a first stress layer located in the source and drain openings, wherein the first stress layer is doped with a first ion; a protective layer located on the first stress layer, wherein the protective layer is doped with a second ion; an inversion layer located between the first stress layer and the protective layer, wherein the inversion layer is doped with a third ion, wherein the conductivity type of the third ion is opposite to that of the second ion. The semiconductor structure can improve the short channel effect and has high performance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] With the rapid development of integrated circuit manufacturing technology, the size of semiconductor devices in the integrated circuit is continuously reduced, so that the operating speed of the entire integrated circuit can be effectively improved.

[0003] In a very large scale integrated circuit, stress is usually formed on a transistor to increase the carrier mobility of the transistor and thus increase the driving current of the transistor.

[0004] However, the performance of semiconductor devices formed by the prior art needs to be improved. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, which can improve the short channel effect and help improve the performance of the formed semiconductor structure.

[0006] To solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, including: a substrate, a surface of the substrate having a gate structure; source and drain openings in the substrate respectively located on both sides of the gate structure; a first stress layer located in the source and drain openings, and the first stress layer is doped with first ions; a protective layer located on the first stress layer, and the protective layer is doped with second ions; an inversion layer located between the first stress layer and the protective layer, and the inversion layer is doped with third ions, and the conductivity type of the third ions is opposite to the conductivity type of the second ions.

[0007] Optionally, a groove is provided in the first stress layer, and the inversion layer is located on the sidewall surface and the bottom surface of the groove.

[0008] Optionally, the protective layer is located on the surface of the inversion layer, and the protective layer is in contact with the inversion layer.

[0009] Optionally, the method further includes: a second stress layer located on the surface of the inversion layer, and the second stress layer is in contact with the inversion layer and the protective layer.

[0010] Optionally, the inversion layer has a thickness ranging from 2 nanometers to 5 nanometers.

[0011] Optionally, the concentration range of the third ion doped in the inversion layer is 1e19atm / cm 3 To 5e19atm / cm 3 .

[0012] Optionally, the first ion and the second ion have the same conductivity type, and the first ion and the second ion are N-type ions or P-type ions; the N-type ions include phosphorus ions or arsenic ions; the P-type ions include boron ions, indium ions or BF2 + .

[0013] Optionally, the third ion is an N-type ion or a P-type ion; the N-type ion includes a phosphorus ion or an arsenic ion; the P-type ion includes a boron ion, an indium ion or a BF 2+ .

[0014] Optionally, it also includes: a third stress layer located on the side wall surfaces and the bottom surface of the source / drain opening, and the first stress layer is located on the third stress layer.

[0015] Optionally, fourth ions are doped in the third stress layer, and the fourth ions have the same conductivity type as the first ions.

[0016] Optionally, a portion of the protection layer, the inversion layer and the first stress layer is further doped with fifth ions, and the conductivity type of the fifth ions is the same as the conductivity type of the first ions.

[0017] Optionally, it also includes: a stop barrier layer located on the surface of the protective layer and the side wall surface of the gate structure; a dielectric layer located on the surface of the stop barrier layer, and the top surface of the dielectric layer is higher than or flush with the top surface of the gate structure; an opening located in the dielectric layer, and the bottom of the opening exposes the top surface of the protective layer; and a conductive plug located in the opening.

[0018] Optionally, the gate structure includes: a gate dielectric layer located on the surface of the substrate, a gate electrode layer located on the surface of the gate dielectric layer, and sidewalls located on sidewall surfaces of the gate dielectric layer and the gate electrode layer.

[0019] Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, including: providing a substrate, the surface of the substrate having a pseudo gate structure; forming source and drain openings in the substrate on both sides of the pseudo gate structure respectively; forming a first stress layer in the source and drain openings, and the first stress layer is doped with first ions; forming a protective layer on the first stress layer, and the protective layer is doped with second ions; forming an inversion layer between the first stress layer and the protective layer, and the inversion layer is doped with third ions, and the conductivity type of the third ions is opposite to the conductivity type of the second ions.

[0020] Optionally, a groove is provided in the first stress layer; and the inversion layer is formed on the sidewall surface and the bottom surface of the groove.

[0021] Optionally, the inversion layer is formed before forming the protection layer.

[0022] Optionally, after forming the first stress layer, the inversion layer is formed on the surface of the first stress layer; and the protection layer is formed on the surface of the inversion layer.

[0023] Optionally, the method further includes: forming a second stress layer on the surface of the inversion layer after forming the inversion layer and before forming the protective layer; and forming the protective layer on the surface of the second stress layer.

[0024] Optionally, the process for forming the inversion layer includes: a selective epitaxial growth process; and doping third ions in the protective layer using an in-situ ion doping process.

[0025] Optionally, it also includes: after forming the source and drain openings and before forming the first stress layer, forming a third stress layer on the side wall surfaces and bottom surfaces of the source and drain openings; after forming the third stress layer, forming a first stress layer in the source and drain openings, the first stress layer being located on the third stress layer.

[0026] Optionally, it also includes: forming a stop barrier layer on the surface of the protective layer and the side wall surface of the pseudo gate structure; forming a dielectric layer on the surface of the stop barrier layer, and the top surface of the dielectric layer is higher than or flush with the top surface of the pseudo gate structure; forming an opening in the dielectric layer, and the bottom of the opening exposes the top surface of the protective layer; forming a conductive plug in the opening.

[0027] Optionally, it also includes: after forming the opening and before forming the conductive plug, performing an ion implantation process on the bottom of the opening to dope fifth ions in part of the protective layer, the inversion layer and the first stress layer, wherein the conductivity type of the fifth ions is the same as the conductivity type of the first ions.

[0028] Optionally, it also includes: removing the dummy gate structure and forming a dummy gate opening in the dielectric layer; forming a gate structure in the dummy gate opening; the gate structure includes: a gate dielectric layer located at the bottom and side wall surface of the dummy gate opening, a gate electrode layer located on the surface of the gate dielectric layer, and side walls located on the side wall surfaces of the gate dielectric layer and the gate electrode layer.

[0029] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0030] In the semiconductor structure provided by the technical solution of the present invention, an inversion layer is provided between the first stress layer and the protective layer, and at the same time, the inversion layer is doped with a third ion, the protective layer is doped with a second ion, and the conductivity type of the third ion is opposite to the conductivity type of the second ion. Since the conductivity type of the inversion layer is opposite to that of the protective layer, the inversion layer can block the doped ions of the protective layer, thereby reducing the diffusion of the doped ions in the protective layer into the area at the bottom of the gate structure, that is, it can effectively reduce the influence of the doped ions on the channel width, thereby improving the short channel effect, which is conducive to improving the performance of the formed semiconductor structure.

[0031] Furthermore, the semiconductor structure further includes: a second stress layer located on the surface of the inversion layer, and the inversion layer is located between the first stress layer and the second stress layer. The inversion layer has a larger area, and thus the inversion layer can better block the doped ions in the protective layer, thereby better reducing the diffusion of the doped ions in the protective layer into the bottom area of ​​the gate structure, that is, it can effectively reduce the influence of the doped ions on the channel width, thereby improving the short channel effect, which is beneficial to improving the performance of the formed semiconductor structure.

[0032] Furthermore, a fifth ion is doped in part of the protective layer, the inversion layer, and the first stress layer. The conductivity type of the fifth ion is the same as that of the first ion, and the doped fifth ion is beneficial to reducing the resistivity and improving the conductivity. At the same time, since the ion concentration of the doped first stress layer at the bottom of the opening is relatively high, that is, the ion doping with a relatively high concentration in a relatively small range is not easy to diffuse into the channel at the bottom of the gate structure. In summary, it is beneficial to further improve the performance of the formed semiconductor structure.

[0033] In the method for forming a semiconductor structure provided by the technical solution of the present invention, an inversion layer is formed between the first stress layer and the protective layer, the inversion layer is doped with a third ion, the protective layer is doped with a second ion, and the conductivity type of the third ion is opposite to the conductivity type of the second ion. Since the conductivity type of the inversion layer is opposite to that of the protective layer, the inversion layer can block the ions doped in the protective layer, thereby reducing the diffusion of the ions doped in the protective layer into the area at the bottom of the gate structure, that is, it can effectively reduce the influence of the doped ions on the channel width, thereby improving the short channel effect, which is conducive to improving the performance of the formed semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figures 1 to 4 It is a structural schematic diagram of each step of a method for forming a semiconductor structure;

[0035] Figures 5 to 14is a schematic structural diagram of each step of a method for forming a semiconductor structure in one embodiment of the present invention;

[0036] Figures 15 to 19 It is a structural schematic diagram of each step of a method for forming a semiconductor structure in another embodiment of the present invention. DETAILED DESCRIPTION

[0037] As described in the background art, the performance of existing semiconductor structures is poor.

[0038] The following is a detailed description of the reasons for the poor performance of the semiconductor structure with reference to the accompanying drawings. Figures 1 to 4 The present invention is a structural schematic diagram of each step of a semiconductor structure forming method.

[0039] Please refer to Figure 1 , providing a substrate 100 , wherein a dummy gate structure 110 is provided on a surface of the substrate 100 , and sidewalls 120 are provided on both sides of the dummy gate structure 110 .

[0040] Please refer to Figure 2 , source and drain openings 130 are formed in the substrate 100 on both sides of the dummy gate structure 110 and the spacer 120 .

[0041] Please refer to Figure 3 A first stress layer 140 is formed on the bottom and sidewall surface of the source / drain opening 130 ; and a third stress layer 150 is formed on the surface of the first stress layer 140 .

[0042] Please refer to Figure 4 , a protection layer 160 is formed on the surface of the second stress layer 150 .

[0043] In the above method, the first stress layer 140 and the second stress layer 150 together form a source-drain doped region. The protective layer 160 located on the surface of the second stress layer 150 can effectively reduce the release of stress caused by heating the source-drain doped region, especially the second stress layer 150, in the subsequent thermal process. Therefore, the protective layer 160 is conducive to maintaining the stress of the source-drain doped region.

[0044] However, the formation process of the protective layer 160 is a selective epitaxial growth process, and an in-situ ion doping process is used to dope ions in the protective layer 160. Specifically, the material of the formed protective layer 160 is silicon germanium, and the concentration of germanium in the silicon germanium material is low, and the doped ions are easy to diffuse in the protective layer 160 with a low germanium concentration, and then easily diffuse into the channel under the pseudo gate structure 110, causing a short channel effect, so that the performance of the semiconductor structure is poor.

[0045] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, wherein an inversion layer is formed between the first stress layer and the protective layer, and the inversion layer is doped with third ions, and the conductivity type of the third ions is opposite to the conductivity type of the second ions. The inversion layer can block the doped ions of the protective layer, thereby reducing the diffusion of the doped ions in the protective layer into the area at the bottom of the gate structure, that is, it can effectively reduce the impact on the channel width, thereby improving the short channel effect, which is beneficial to improving the performance of the formed semiconductor structure.

[0046] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0047] Figures 5 to 14 It is a structural schematic diagram of each step of a method for forming a semiconductor structure in one embodiment of the present invention.

[0048] Please refer to Figure 5 , providing a substrate 200, wherein a dummy gate structure 210 is provided on a surface of the substrate.

[0049] In this embodiment, the base 200 includes a substrate and a fin located on a surface of the substrate. The dummy gate structure 210 spans across the fin and covers a portion of the top surface and sidewall surface of the fin.

[0050] In other embodiments, the substrate has no fins thereon.

[0051] In this embodiment, the method for forming the base 200 includes: providing an initial substrate (not shown); the initial substrate has a first patterned layer, and the first patterned layer exposes a portion of the surface of the initial substrate; using the first patterned layer as a mask, etching the initial substrate to form the substrate 201 and the fin located on the surface of the substrate.

[0052] In this embodiment, the material of the initial substrate is silicon. Accordingly, the material of the substrate and the fin is silicon.

[0053] In other embodiments, the material of the initial substrate includes: germanium, silicon germanium, silicon on insulator or germanium on insulator. Correspondingly, the material of the substrate includes: germanium, silicon germanium, silicon on insulator or germanium on insulator. The material of the fin includes: germanium, silicon germanium, silicon on insulator or germanium on insulator.

[0054] In this embodiment, the dummy gate structure 210 includes: a dummy gate dielectric layer 211 located on the surface of the substrate 200 , a dummy gate electrode layer 212 located on the surface of the dummy gate dielectric layer 211 , and a sidewall 213 located on the sidewall surface of the dummy gate dielectric layer 211 and the dummy gate electrode layer 212 .

[0055] The material of the dummy gate dielectric layer 211 includes: one or a combination of low-K dielectric material (dielectric constant greater than or equal to 2.5 and less than 3.9) and ultra-low-k dielectric material (dielectric constant less than 2.5). In this embodiment, the material of the dummy gate dielectric layer 211 is silicon oxide.

[0056] The material of the dummy gate electrode layer 212 includes: polycrystalline silicon or polycrystalline germanium. In this embodiment, the material of the dummy gate dielectric layer 212 is polycrystalline silicon.

[0057] The material of the sidewall 213 includes: insulating material. The insulating material includes: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide or silicon oxycarbonitride. In this embodiment, the material of the sidewall 213 is silicon nitride.

[0058] In other embodiments, the dummy gate structure does not include the spacer.

[0059] The method for forming the pseudo gate structure 210 includes: forming a pseudo gate dielectric film (not shown in the figure) on the surface of the substrate; forming a pseudo gate electrode film (not shown in the figure) on the surface of the pseudo gate dielectric film; patterning the pseudo gate dielectric film and the pseudo gate electrode film until the substrate surface is exposed, so that the pseudo gate dielectric film forms a pseudo gate dielectric layer 211, and the pseudo gate electrode film forms a pseudo gate electrode 212; forming a sidewall material film on the top surface and sidewall surface of the pseudo gate electrode layer 212, and on the sidewall surface of the pseudo gate dielectric layer 211; etching back the sidewall material film until the substrate surface is exposed, and forming sidewalls 213 on the sidewall surfaces of the pseudo gate dielectric layer 211 and the pseudo gate electrode layer 212.

[0060] In this embodiment, the method for forming the semiconductor structure further includes: forming a blocking layer (not shown in the figure) on the top surface of the dummy gate structure 210 .

[0061] In this embodiment, the material of the barrier layer is silicon oxide.

[0062] The barrier layer is used to protect the surface of the dummy gate structure 210 from being affected by the process in subsequent process steps, thereby maintaining a good morphology.

[0063] Please refer to Figure 6 , source and drain openings 220 are respectively formed in the substrate 200 on both sides of the dummy gate structure 210 .

[0064] The source / drain openings 220 provide space for the subsequent formation of a first stress layer, an inversion layer, and a third stress layer.

[0065] Specifically, in this embodiment, the source-drain openings 220 are located in the fins on both sides of the dummy gate structure 210 .

[0066] The method for forming the source-drain opening 220 includes: using the dummy gate structure as a mask, etching the substrate 200 to form the source-drain opening 220 .

[0067] In this embodiment, the process of etching the substrate includes: anisotropic dry etching.

[0068] Please refer to Figure 7 A third stress layer 230 is formed on the sidewall surface and the bottom surface of the source / drain opening 220 .

[0069] The formation process of the third stress layer 230 includes: a selective epitaxial growth process; and an in-situ ion doping process to dope fourth ions in the third stress layer 230 .

[0070] The conductivity type of the fourth ions is the same as the conductivity type of the first ions subsequently doped into the first stress layer.

[0071] When the semiconductor to be formed is a P-type device, the material of the third stress layer 230 includes: silicon germanium; when the semiconductor to be formed is an N-type device, the material of the third stress layer 230 includes: carbon germanium.

[0072] The fourth ion is an N-type ion or a P-type ion; the N-type ion includes a phosphorus ion or an arsenic ion; the P-type ion includes a boron ion, an indium ion or a BF 2+ .

[0073] In this embodiment, the semiconductor to be formed is a P-type device, the material in the third stress layer 230 is silicon germanium, the fourth ion doped is boron ion, and the concentration of germanium in the silicon germanium material is 0.1-0.3, and the concentration of the boron ion is 1e18 atm / cm 3 ~1e19atm / cm 3 .

[0074] It should be noted that the concentration refers to the ratio of the amount of germanium element to the amount of silicon element in the material.

[0075] Since the germanium concentration in the silicon germanium material of the third stress layer 230 is relatively low, the stress of the third stress layer 230 is relatively small, and thus a good buffering effect can be provided between the substrate 200 and the subsequently formed first stress layer having a relatively large stress.

[0076] Please refer to Figure 8 After the third stress layer 230 is formed, a first stress layer 240 is formed on the surface of the third stress layer 230 , and the first stress layer 240 is doped with first ions.

[0077] The first stress layer 240 and the third stress layer 230 are used together as source and drain doping regions.

[0078] In this embodiment, the first stress layer 240 and the third stress layer 230 do not completely fill the source / drain openings 220 .

[0079] In other embodiments, the first stress layer and the third stress layer completely fill the source / drain openings.

[0080] Specifically, in this embodiment, a groove 241 is defined in the first stress layer 240 .

[0081] The method for forming the first stress layer 240 and the groove 241 includes: forming an initial first stress layer (not shown in the figure) on the surface of the third stress layer 230 in the source / drain opening 220 ; etching the initial first stress layer to form a first stress layer 240 and a groove 241 located in the first stress layer 240 .

[0082] In this embodiment, the initial first stress layer completely fills the source / drain openings 220 .

[0083] The process for forming the initial first stress layer includes: a selective epitaxial growth process; and doping the initial first stress layer with first ions using an in-situ ion doping process.

[0084] When the semiconductor to be formed is a P-type device, the material of the first stress layer 240 includes: silicon germanium; when the semiconductor to be formed is an N-type device, the material of the first stress layer 240 includes: carbon germanium.

[0085] The first ion is an N-type ion or a P-type ion; the N-type ion includes a phosphorus ion or an arsenic ion; the P-type ion includes a boron ion, an indium ion or a BF 2+ .

[0086] The first ion and the fourth ion are the same or different. In this embodiment, the first ion and the fourth ion are the same, that is, boron ions.

[0087] In this embodiment, the material of the first stress layer 240 is silicon germanium, the first doped ions are boron ions, and the concentration of germanium in the silicon germanium material is 0.4-0.6, and the concentration of the boron ions is 1e20 atm / cm 3 ~1e21atm / cm 3The germanium concentration in the silicon germanium material of the first stress layer 240 is relatively high, and the first stress layer 240 occupies the main volume of the source-drain opening 220. The first stress layer 240 exerts a relatively large stress on the channel, so that the first stress layer 240 and the third stress layer 230 located in the source-drain opening 220, together as source-drain doping regions, exert a relatively large stress on the channel, which is beneficial to enhancing the carrier migration rate, improving the driving current of the semiconductor device, and improving the response speed of the circuit.

[0088] Please refer to Fig. 9 , an inversion layer 250 is formed on the surface of the first stress layer 240 , and the inversion layer 250 is doped with third ions.

[0089] In this embodiment, the inversion layer 250 is located on the sidewall surface and the bottom surface of the groove 241 in the first stress layer 240 .

[0090] The formation process of the inversion layer 250 includes: a selective epitaxial growth process; and an in-situ ion doping process to dope the third ions in the protective layer.

[0091] When the semiconductor to be formed is a P-type device, the material of the inversion layer 250 includes: silicon germanium; when the semiconductor to be formed is an N-type device, the material of the inversion layer 250 includes: carbon germanium.

[0092] The third ion is an N-type ion or a P-type ion; the N-type ion includes a phosphorus ion or an arsenic ion; the P-type ion includes a boron ion, an indium ion or a BF 2+ .

[0093] The concentration range of the third ion doped in the inversion layer 250 is 1e19 atm / cm 3 To 5e19atm / cm 3 .

[0094] The significance of selecting the doping concentration is that if the concentration is greater than 5e19atm / cm 3 If the doping concentration is too high, it is easy to cause the series resistance to be too high, which is not conducive to the electrical performance of the semiconductor structure; if the concentration is less than 1e19atm / cm 3 , the doping concentration is too low to fully block the protective layer, and it is still easy to cause the carriers in the protective layer to diffuse into the area at the bottom of the pseudo gate structure, which is not conducive to the performance of the semiconductor structure.

[0095] In this embodiment, the material of the inversion layer 250 is silicon germanium, the third ions doped are phosphorus ions, and the concentration of germanium in the silicon germanium material is 0.2, and the concentration of the phosphorus ions is 5e19atm / cm 3The thickness of the inversion layer 250 is in a range of 2 nanometers to 5 nanometers.

[0096] The significance of selecting the thickness range is that: if the thickness is less than 2 nanometers, the inversion layer 250 is too thin and cannot fully block the carriers in the subsequently formed protective layer, and the performance of the formed semiconductor structure is still poor; if the thickness is greater than 5 nanometers, the inversion layer 250 occupies a larger space, which is not conducive to improving the integration of the device.

[0097] Please refer to Fig.10 After the inversion layer 250 is formed, a protection layer 260 is formed on the surface of the inversion layer 250 , wherein the protection layer 260 is doped with second ions, and the conductivity type of the third ions is opposite to the conductivity type of the second ions.

[0098] The protection layer 260 can effectively prevent the first stress layer 240 from being heated and causing the stress to be released during the subsequent thermal process.

[0099] The formation process of the protection layer 260 includes: a selective epitaxial growth process; and an in-situ ion doping process to dope the second ions in the protection layer 260 .

[0100] When the semiconductor to be formed is a P-type device, the material of the protective layer 260 includes: silicon germanium; when the semiconductor to be formed is an N-type device, the material of the protective layer 260 includes: carbon germanium.

[0101] In this embodiment, the material of the protection layer 260 is silicon germanium.

[0102] The conductivity type of the second ions is the same as the conductivity type of the first ions.

[0103] The second ion is an N-type ion or a P-type ion.

[0104] The N-type ions include phosphorus ions or arsenic ions; the P-type ions include boron ions, indium ions or BF 2+ .

[0105] The second ion is the same as or different from the first ion.

[0106] In this embodiment, the first ions and the second ions are the same, that is, boron ions.

[0107] Since the conductivity type of the second ions is opposite to the conductivity type of the third ions, the conductivity type of the protection layer 260 is opposite to the conductivity type of the inversion layer 250 .

[0108] In this embodiment, the material of the protective layer 260 is silicon germanium, the second ions doped are boron ions, and the concentration of germanium in the silicon germanium material is 0.1-0.2, and the concentration of the boron ions is 5e19atm / cm 3 ~5e20atm / cm 3 .

[0109] By forming an inversion layer 250 between the first stress layer 240 and the protective layer 260, the inversion layer 250 is doped with a third ion, and the conductivity type of the third ion is opposite to the conductivity type of the second ion. Since the conductivity type of the inversion layer 250 is opposite to the conductivity type of the protective layer 260, the inversion layer 250 can block the ions doped in the protective layer 260, reduce the diffusion of the ions doped in the protective layer 260 into the bottom area of ​​the pseudo gate structure 210, that is, can effectively reduce the impact on the channel width, thereby improving the short channel effect, which is conducive to improving the performance of the formed semiconductor structure.

[0110] Please refer to Fig.11 A stop barrier layer 271 is formed on the surface of the protection layer 260 and the sidewall surface of the dummy gate structure 210 ; a dielectric layer 272 is formed on the surface of the stop barrier layer 271 , and the top surface of the dielectric layer 272 is higher than or flush with the top surface of the dummy gate structure 210 .

[0111] The stop barrier layer 271 is used as a stop layer for subsequent etching.

[0112] The dielectric layer 272 is used to provide support for subsequent device formation.

[0113] The material of the stop barrier layer 271 is different from the material of the dielectric layer 272 .

[0114] In this embodiment, the material of the stop barrier layer 271 is silicon nitride; the material of the dielectric layer 272 is silicon oxide.

[0115] In this embodiment, the top surface of the dummy gate structure 210 has a barrier layer (not shown in the figure), the top surface of the dielectric layer 272 is flush with the top surface of the barrier layer, and the dielectric layer 272 exposes the barrier layer on the top surface of the dummy gate structure 210 .

[0116] Please refer to Fig.12 , remove the dummy gate structure 210, form a dummy gate opening (not shown in the figure) in the dielectric layer 272; and form a gate structure 280 in the dummy gate opening.

[0117] In this embodiment, removing the dummy gate structure 210 refers to removing the dummy gate electrode layer 212 and the dummy gate dielectric layer 211 in the dummy gate structure 210 and retaining the sidewall spacer 213 , so that the sidewall spacer 213 serves as a part of the gate structure 280 .

[0118] The gate structure 280 includes: a gate dielectric layer (not shown in the figure) located at the bottom and side wall surface of the dummy gate opening, a gate electrode layer (not shown in the figure) located on the surface of the gate dielectric layer, and a side wall 213 located on the side wall surface of the gate dielectric layer and the gate electrode layer, and the gate electrode layer fills the dummy gate opening.

[0119] The material of the gate dielectric layer includes: high-K dielectric material (dielectric constant greater than 3.9), such as: hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide or aluminum oxide.

[0120] In this embodiment, the material of the gate dielectric layer is hafnium oxide.

[0121] The material of the gate electrode layer includes: metal, for example, one or more combinations of copper, tungsten, aluminum, titanium, nickel, titanium nitride and tantalum nitride.

[0122] In this embodiment, the material of the gate electrode layer is tungsten.

[0123] Please refer to Fig.13 , forming an opening 291 in the dielectric layer 272, wherein the bottom of the opening 291 exposes the top surface of the protective layer 260; performing an ion implantation process on the bottom of the opening 291, doping a fifth ion in part of the protective layer 260, the inversion layer 240 and the first stress layer 240, wherein the conductivity type of the fifth ion is the same as the conductivity type of the first ion.

[0124] The fifth ion is an N-type ion or a P-type ion.

[0125] The fifth ion is the same as or different from the first ion.

[0126] In this embodiment, the fifth ion is the same as the first ion, that is, a boron ion.

[0127] After the opening 291 is formed and before the conductive plug is subsequently formed, an ion implantation process is performed on the bottom of the opening 291, so as to dope the fifth ion in part of the protective layer 260, the inversion layer 250 and the first stress layer 240. The conductivity type of the fifth ion is the same as the conductivity type of the first ion, and doping with the fifth ion is beneficial to reducing the resistivity and improving the conductivity. At the same time, since the ion concentration of the doped part of the first stress layer 240 located at the bottom 291 of the opening is relatively high, that is, the ion doping with a relatively high concentration in a relatively small range is not easy to diffuse into the channel at the bottom of the gate structure 280. In summary, it is beneficial to further improve the performance of the formed semiconductor structure.

[0128] Please refer to Fig.14 After the ion implantation process, in the opening 291 ( Fig.13 A conductive plug 292 is formed in the housing 290 (as shown in FIG. 2 ).

[0129] The material of the conductive plug 292 includes metal, for example, one or more combinations of copper, tungsten, aluminum, titanium, nickel, titanium nitride and tantalum nitride.

[0130] In this embodiment, the conductive plug 292 is made of tungsten.

[0131] Accordingly, the embodiment of the present invention further provides a semiconductor structure formed by the above method, please continue to refer to Fig.14 , comprising: a substrate 200, wherein the surface of the substrate 200 has a gate structure 280; source and drain openings 220 ( Figure 6 ); a first stress layer 240 located in the source / drain opening 220, wherein the first stress layer 240 is doped with a first ion; a protective layer 260 located on the first stress layer 240, wherein the protective layer 260 is doped with a second ion; an inversion layer 250 located between the first stress layer 240 and the protective layer 260, wherein the inversion layer 250 is doped with a third ion, wherein the conductivity type of the third ion is opposite to the conductivity type of the second ion.

[0132] An inversion layer 250 is provided between the first stress layer 240 and the protection layer 260. Meanwhile, the protection layer 260 is doped with second ions, and the inversion layer 250 is doped with third ions, and the conductivity type of the third ions is opposite to that of the second ions. Since the conductivity type of the inversion layer 250 is opposite to that of the protection layer 260, the inversion layer 250 can block the ions doped in the protection layer 260, thereby reducing the diffusion of the ions doped in the protection layer 260 into the bottom area of ​​the gate structure 280, that is, it can effectively reduce the impact on the channel width, thereby improving the short channel effect, which is beneficial to improving the performance of the formed semiconductor structure.

[0133] The following is a detailed description with reference to the accompanying drawings.

[0134] Specifically, the groove 241 ( Figure 8 As shown in FIG. 2 , the inversion layer 250 is located on the sidewall surface and the bottom surface of the groove 241 .

[0135] In this embodiment, the protection layer 260 is located on the surface of the inversion layer 250 , and the protection layer 260 is in contact with the inversion layer 250 .

[0136] The thickness of the inversion layer 250 is in a range of 2 nanometers to 5 nanometers.

[0137] The concentration range of the third ion doped in the inversion layer 250 is 1e19 atm / cm 3 To 5e19atm / cm 3 .

[0138] The conductivity type of the first ion is the same as the conductivity type of the second ion. The first ion and the second ion are N-type ions or P-type ions. The N-type ions include phosphorus ions or arsenic ions. The P-type ions include boron ions, indium ions or BF 2+ .

[0139] The third ion is an N-type ion or a P-type ion; the N-type ion includes a phosphorus ion or an arsenic ion; the P-type ion includes a boron ion, an indium ion or a BF 2+ .

[0140] The semiconductor structure further includes: a third stress layer 230 located on the sidewall surfaces and the bottom surface of the source / drain opening 220 , and the first stress layer 240 is located on the surface of the third stress layer 230 .

[0141] The third stress layer 230 is doped with fourth ions, and the fourth ions have the same conductivity type as the first ions.

[0142] The semiconductor structure also includes: a stop barrier layer 271 located on the surface of the protective layer 260 and the side wall surface of the gate structure 280; a dielectric layer 272 located on the surface of the stop barrier layer 271, and the top surface of the dielectric layer 272 is higher than or flush with the top surface of the gate structure 280; an opening (not shown in the figure) located in the dielectric layer 272, and the bottom of the opening exposes the top surface of the protective layer 260; and a conductive plug 292 located in the opening.

[0143] In this embodiment, a portion of the protection layer 260 , the inversion layer 250 , and the first stress layer 240 are further doped with fifth ions, and the conductivity type of the fifth ions is the same as the conductivity type of the first ions.

[0144] The doped fifth ion is beneficial to reducing resistivity and improving conductivity, and at the same time, since the ion concentration of the first stress layer 240 at the bottom of the opening 291 is relatively high, that is, the ion doping with a relatively small range and a relatively high concentration is not easy to diffuse into the channel at the bottom of the gate structure 280. In summary, it is beneficial to further improve the performance of the formed semiconductor structure.

[0145] The gate structure includes: a gate dielectric layer (not shown in the figure) located on the surface of the substrate 200, a gate electrode layer (not shown in the figure) located on the surface of the gate dielectric layer, and sidewalls 213 located on the sidewall surfaces of the gate dielectric layer and the gate electrode layer.

[0146] Figures 15 to 19 1 is a schematic diagram of the structure of each step of the method for forming a semiconductor structure in another embodiment of the present invention. The difference between this embodiment and the above embodiment is that after forming the third stress layer, a first stress layer is formed on the surface of the third stress layer; after forming the first stress layer, an inversion layer is formed on the surface of the first stress layer; after forming the inversion layer, a second stress layer is formed on the surface of the inversion layer. Therefore, this embodiment continues to explain the method for forming a semiconductor structure based on the above embodiment.

[0147] Please Figure 7 Continue to refer to Fig.15 After the third stress layer 230 is formed, a first stress layer 310 is formed on the bottom and sidewall surface of the source / drain opening 220 , and the first stress layer 310 is doped with first ions.

[0148] Specifically, in this embodiment, the first stress layer 310 is formed on the surface of the third stress layer 230 .

[0149] In this embodiment, a groove 311 is defined in the first stress layer 310 .

[0150] In this embodiment, the process of forming the first stress layer 310 includes: a selective epitaxial growth process.

[0151] The material of the first stress layer 310 is the same as that of the first stress layer 240 in the above embodiment, and will not be described again.

[0152] Please refer to Fig.16 , an inversion layer 320 is formed on the surface of the first stress layer 311 , and the inversion layer 320 is doped with third ions.

[0153] Specifically, the inversion layer 320 is formed on the bottom surface and the sidewall surface of the groove 311 .

[0154] It should be noted that the volume of the groove 311 is larger than the volume of the groove 241 in the above embodiment, so that the area of ​​the inversion layer subsequently formed on the bottom surface and side wall surface of the groove 311 is larger, which is conducive to the inversion layer to fully block the ions doped in the protective layer.

[0155] The formation process and materials of the inversion layer 320 are the same as those of the inversion layer 250 in the above embodiment, and are not described in detail herein.

[0156] Please refer to Fig.17 , a second stress layer 330 is formed on the surface of the inversion layer 320 .

[0157] The second stress layer 330 is doped with first ions.

[0158] The formation process of the second stress layer 330 includes: a selective epitaxial growth process.

[0159] The material of the second stress layer 330 is the same as the formation process and material of the first stress layer 240 in the above embodiment, and will not be described in detail herein.

[0160] So far, in this embodiment, the second stress layer 330 completely fills the source-drain opening 220. In other embodiments, the second stress layer does not completely fill the source-drain opening.

[0161] Please refer to Fig.18 A protection layer 340 is formed on the surface of the second stress layer 330 , wherein the protection layer 340 is doped with second ions, and the conductivity type of the third ions is opposite to the conductivity type of the second ions.

[0162] The forming process and material of the protection layer 340 are the same as those of the protection layer 260 in the above embodiment, and are not described in detail herein.

[0163] The conductivity type of the first ions is the same as the conductivity type of the second ions.

[0164] Please refer to Fig.19 , forming a stop barrier layer 350 on the surface of the protection layer 340 and the side wall surface of the pseudo gate structure 210; forming a dielectric layer 360 on the surface of the stop barrier layer 350, and the top surface of the dielectric layer 360 is higher than or flush with the top surface of the pseudo gate structure 210; forming an opening (not shown in the figure) in the dielectric layer 360, and the bottom of the opening exposes the top surface of the protection layer 340; performing an ion implantation process on the bottom of the opening, doping a fifth ion in part of the protection layer 340, the inversion layer 320 and the first stress layer 310, and the conductivity type of the fifth ion is the same as the conductivity type of the first ion; after the ion implantation, forming a conductive plug 370 in the opening.

[0165] In this embodiment, after forming the dielectric layer 360 and before forming the opening, the method for forming the semiconductor structure further includes: removing the dummy gate structure 210, forming a dummy gate opening (not shown in the figure) in the dielectric layer 360; and forming a gate structure 380 in the dummy gate opening.

[0166] The formation process and material of the stop barrier layer 350 are the same as those of the stop barrier layer 271 in the above embodiment, and are not described in detail herein.

[0167] The formation process and materials of the dielectric layer 360 are the same as those of the dielectric layer 272 of the above embodiment, and are not described in detail herein.

[0168] The forming method and material of the conductive plug 370 are the same as those of the conductive plug 292 in the above embodiment, and will not be described in detail herein.

[0169] The forming method and material of the gate structure 380 are the same as the forming method and material of the gate structure 280 in the above embodiment, and will not be described in detail herein.

[0170] Accordingly, the embodiment of the present invention further provides a semiconductor structure formed by the above method, please continue to refer to Fig.19 , comprising: a substrate 200, wherein the surface of the substrate 200 has a gate structure 380; source and drain openings 220 ( Figure 6 ); a first stress layer 310 located in the source / drain opening 220, wherein the first stress layer 310 is doped with a first ion; a protective layer 340 located on the first stress layer 310, wherein the protective layer 340 is doped with a second ion; an inversion layer 320 located between the first stress layer 310 and the protective layer 340, wherein the inversion layer 320 is doped with a third ion, wherein the conductivity type of the third ion is opposite to the conductivity type of the second ion.

[0171] An inversion layer 320 is provided between the first stress layer 310 and the protection layer 340. Meanwhile, the inversion layer 320 is doped with a third ion, and the protection layer 340 is doped with a second ion, and the conductivity type of the third ion is opposite to that of the second ion. Since the conductivity type of the inversion layer 320 is opposite to that of the protection layer 340, the inversion layer 320 can block the doped ions of the protection layer 340, thereby reducing the diffusion of the doped ions in the protection layer 340 into the bottom area of ​​the gate structure 380, that is, it can effectively reduce the influence of the doped ions on the channel width, thereby improving the short channel effect, which is beneficial to improving the performance of the formed semiconductor structure.

[0172] The following is a detailed description with reference to the accompanying drawings.

[0173] In this embodiment, a groove 311 is defined in the first stress layer 310 , and the inversion layer 320 is located on the sidewall surface and the bottom surface of the groove 311 .

[0174] The inversion layer 320 has a larger area, and thus the inversion layer 320 can better block the doped ions in the protective layer 340, thereby better reducing the diffusion of the doped ions in the protective layer 340 into the bottom area of ​​the gate structure 380, that is, it can effectively reduce the influence of the doped ions on the channel width, and thus can improve the short channel effect, which is beneficial to improving the performance of the formed semiconductor structure.

[0175] The thickness of the inversion layer 320 is in a range of 2 nanometers to 5 nanometers.

[0176] In this embodiment, the semiconductor structure further includes: a second stress layer 330 located on the surface of the inversion layer 320 , and the second stress layer 330 is in contact with the inversion layer 320 and the protection layer 340 .

[0177] The concentration range of the third ion doped in the inversion layer 320 is 1e19 atm / cm 3 To 5e19atm / cm 3 .

[0178] The conductivity type of the first ion is the same as the conductivity type of the second ion, and the first ion and the second ion are N-type ions or P-type ions; the N-type ions include phosphorus ions or arsenic ions; the P-type ions include boron ions, indium ions or BF2+.

[0179] The third ion is an N-type ion or a P-type ion; the N-type ion includes a phosphorus ion or an arsenic ion; the P-type ion includes a boron ion, an indium ion or a BF 2+ .

[0180] The semiconductor structure further includes: a third stress layer 230 located on the sidewall surfaces and the bottom surface of the source / drain opening 220 , and the first stress layer 310 is located on the surface of the third stress layer 230 .

[0181] The third stress layer 230 is doped with fourth ions, and the fourth ions have the same conductivity type as the first ions.

[0182] Part of the protection layer 340 , the inversion layer 320 and the first stress layer 310 is doped with fifth ions, and the conductivity type of the fifth ions is the same as the conductivity type of the first ions.

[0183] The semiconductor structure also includes: a stop barrier layer 350 located on the surface of the protective layer 340 and the side wall surface of the gate structure 380; a dielectric layer 360 located on the surface of the stop barrier layer 350, and the top surface of the dielectric layer 360 is higher than or flush with the top surface of the gate structure 380; an opening located in the dielectric layer 360, and the bottom of the opening exposes the top surface of the protective layer 340; and a conductive plug 370 located in the opening.

[0184] The gate structure 380 includes: a gate dielectric layer (not shown) located on the surface of the substrate 200, a gate electrode layer (not shown) located on the surface of the gate dielectric layer, and sidewalls 213 located on the sidewall surfaces of the gate dielectric layer and the gate electrode layer.

[0185] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: A substrate, wherein a surface of the substrate has a gate structure; Source and drain openings in the substrate respectively located on both sides of the gate structure; a first stress layer located in the source / drain opening, wherein the first stress layer is doped with first ions; a protective layer located on the first stress layer, wherein the protective layer is doped with second ions; The inversion layer is located between the first stress layer and the protection layer, and the inversion layer is doped with third ions, and the conductivity type of the third ions is opposite to the conductivity type of the second ions.

2. The semiconductor structure according to claim 1, wherein: The first stress layer has a groove therein, and the inversion layer is located on the sidewall surface and the bottom surface of the groove.

3. The semiconductor structure according to claim 1, wherein: The protection layer is located on the surface of the inversion layer, and the protection layer is in contact with the inversion layer.

4. The semiconductor structure according to claim 1, wherein: Also includes: A second stress layer is located on the surface of the inversion layer, and the second stress layer is in contact with the inversion layer and the protection layer.

5. The semiconductor structure according to claim 1, wherein: The thickness of the inversion layer ranges from 2 nanometers to 5 nanometers.

6. The semiconductor structure according to claim 1, wherein: The concentration range of the third ion doped in the inversion layer is 1e19atm / cm 3 To 5e19atm / cm 3 .

7. The semiconductor structure according to claim 1, wherein: The first ion and the second ion have the same conductivity type, and the first ion and the second ion are N-type ions or P-type ions; the N-type ions include phosphorus ions or arsenic ions; the P-type ions include boron ions, indium ions or BF 2+ .

8. The semiconductor structure according to claim 1, wherein: The third ion is an N-type ion or a P-type ion; the N-type ion includes a phosphorus ion or an arsenic ion; the P-type ion includes a boron ion, an indium ion or a BF 2+ .

9. The semiconductor structure according to claim 1, wherein: Also includes: A third stress layer is located on the sidewall surfaces and the bottom surface of the source / drain opening, and the first stress layer is located on the third stress layer.

10. The semiconductor structure according to claim 9, wherein: The third stress layer is doped with fourth ions, and the fourth ions have the same conductivity type as the first ions.

11. The semiconductor structure according to claim 1, wherein: Part of the protection layer, the inversion layer and the first stress layer is also doped with fifth ions, and the conductivity type of the fifth ions is the same as the conductivity type of the first ions.

12. The semiconductor structure according to claim 1, wherein: Also includes: A stop barrier layer located on the surface of the protection layer and the surface of the sidewall of the gate structure; A dielectric layer located on the surface of the stop barrier layer, wherein the top surface of the dielectric layer is higher than or flush with the top surface of the gate structure; An opening is located in the dielectric layer, wherein the bottom of the opening exposes the top surface of the protective layer; and a conductive plug is located in the opening.

13. The semiconductor structure according to claim 1, wherein: The gate structure comprises: a gate dielectric layer located on the surface of a substrate, a gate electrode layer located on the surface of the gate dielectric layer, and sidewalls located on the sidewall surfaces of the gate dielectric layer and the gate electrode layer.

14. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, wherein a surface of the substrate has a dummy gate structure; forming source and drain openings in the substrate at both sides of the dummy gate structure respectively; forming a first stress layer in the source / drain opening, wherein the first stress layer is doped with first ions; forming a protective layer on the first stress layer, wherein the protective layer is doped with second ions; An inversion layer is formed between the first stress layer and the protection layer, and third ions are doped in the inversion layer, and the conductivity type of the third ions is opposite to the conductivity type of the second ions.

15. The method for forming a semiconductor structure according to claim 14, wherein: The first stress layer has a groove therein; the inversion layer is formed on the sidewall surface and the bottom surface of the groove.

16. The method for forming a semiconductor structure according to claim 14, wherein: The inversion layer is formed before forming the protection layer.

17. The method for forming a semiconductor structure according to claim 16, wherein: After forming the first stress layer, forming the inversion layer on the surface of the first stress layer; and forming the protection layer on the surface of the inversion layer.

18. The method for forming a semiconductor structure according to claim 16, wherein: Also includes: After forming the inversion layer and before forming the protection layer, forming a second stress layer on the surface of the inversion layer; The protection layer is formed on the surface of the second stress layer.

19. The method for forming a semiconductor structure according to claim 14, wherein: The formation process of the inversion layer includes: a selective epitaxial growth process; and an in-situ ion doping process to dope the third ion into the protective layer.

20. The method for forming a semiconductor structure according to claim 14, wherein: Also includes: After forming the source / drain openings and before forming the first stress layer, forming a third stress layer on the sidewall surfaces and bottom surfaces of the source / drain openings; After the third stress layer is formed, a first stress layer is formed in the source / drain opening, wherein the first stress layer is located on the third stress layer.

21. The method for forming a semiconductor structure according to claim 14, wherein: Also includes: Forming a stop barrier layer on the surface of the protection layer and the sidewall surface of the dummy gate structure; forming a dielectric layer on the surface of the stop barrier layer, and the top surface of the dielectric layer is higher than or flush with the top surface of the dummy gate structure; forming an opening in the dielectric layer, wherein the bottom of the opening exposes the top surface of the protective layer; A conductive plug is formed in the opening.

22. The method for forming a semiconductor structure according to claim 21, wherein: Also includes: After forming the opening and before forming the conductive plug, an ion implantation process is performed on the bottom of the opening to dope fifth ions in part of the protective layer, the inversion layer and the first stress layer, wherein the conductivity type of the fifth ions is the same as that of the first ions.

23. The method for forming a semiconductor structure according to claim 21, wherein: Also includes: removing the dummy gate structure and forming a dummy gate opening in the dielectric layer; forming a gate structure in the dummy gate opening; The gate structure comprises: a gate dielectric layer located at the bottom and side wall surface of the dummy gate opening, a gate electrode layer located on the surface of the gate dielectric layer, and sidewalls located on the side wall surfaces of the gate dielectric layer and the gate electrode layer.

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