Pixel, display panel and display device

Abstract

A pixel, a display panel, and a display device are provided. The display panel includes: sub-pixels, each including a light-emitting element and a pixel circuit including a first transistor and a second transistor; a timing control unit that generates bias data based on first characteristic information of the first transistor and generates correction data based on second characteristic information of the second transistor; and a data sensing and driving unit configured to receive the bias data and the correction data and output a bias voltage and a gray-scale voltage to the pixel circuit. The pixel circuit includes: a first transistor that outputs a driving current to the light-emitting element; a first driving circuit that controls the magnitude of the driving current based on the bias voltage; and a second driving circuit that includes the second transistor and is configured to control the pulse width of the driving current based on the gray-scale voltage.

Description

Technical Field

[0001] The present disclosure generally relates to displays, and more particularly, to a pixel circuit and a display panel having time-division pixel sensing and compensation. Background Art

[0002] When the emission wavelength of a light-emitting diode (LED) (specifically, a micro-LED that can use an inorganic material as a light-emitting material and has a micrometer size) can change according to the amount of current, it may be difficult to apply a driving method that presents gray levels based on the amount of current as in the case of organic LEDs. Summary of the Invention

[0003] According to an exemplary embodiment of the present disclosure, an inorganic or micro-scale light-emitting diode can be used as a light-emitting element in a display panel in which a pixel circuit can operate using a time-division sensing and driving method.

[0004] Embodiments provide a pixel circuit for driving a light-emitting diode. Embodiments provide a display panel including a light-emitting diode.

[0005] Additional embodiments may be partially set forth in the following description, and may be partially apparent from the description, or may be learned by practice of the presented embodiments.

[0006] A display panel according to an exemplary embodiment includes a timing control unit, a data sensing and driving unit, and a plurality of sub-pixels. Each of the plurality of sub-pixels includes a light-emitting element and a pixel circuit configured to output a driving current to the light-emitting element. The pixel circuit includes a first transistor and a second transistor. The timing control unit is configured to generate bias data based on first characteristic information of the first transistor and correction data based on second characteristic information of the second transistor. The data sensing and driving unit is configured to receive the bias data and the correction data, and output a bias voltage corresponding to the bias data and a gray-scale voltage corresponding to the correction data to the pixel circuit.

[0007] The pixel circuit may include: a first transistor configured to output a driving current to the light-emitting element, wherein the first transistor is connected to the light-emitting element; a first driving circuit configured to control the magnitude of the driving current based on the bias voltage; and a second driving circuit configured to control the pulse width of the driving current based on the gray-scale voltage, wherein the second driving circuit includes a second transistor.

[0008] A pixel according to an exemplary embodiment includes a pixel circuit connected to a light-emitting element. The pixel circuit includes: a first transistor connected between a first power line and the light-emitting element, to which a first driving voltage is applied; a fourth transistor including a gate, a first connection end, and a second connection end, the gate being connected to a scan line for transmitting a scan signal, the first connection end being connected to a first data line to which a bias voltage is applied, and the second connection end being connected to the gate of the first transistor; a fifth transistor including a gate, a first connection end, and a second connection end, the gate being connected to the scan line, the first connection end being connected to a first sensing line to which a first control voltage is applied, and the second connection end being connected to the source of the first transistor; a first capacitor connected between the gate and the source of the first transistor; a second transistor including a gate, a drain, and a source, the drain being connected to the gate of the first transistor, and the source being connected to a second sensing line to which a second control voltage is applied; a third transistor including a gate, a first connection end, and a second connection end, the gate being connected to the scan line, the first connection end being connected to a second data line to which a gray-scale voltage is applied, and the second connection end being connected to the gate of the second transistor; and a second capacitor including a first electrode and a second electrode, the first electrode being connected to a voltage line to which a reset voltage that monotonically changes during a preset period is applied, and the second electrode being connected to the gate of the second transistor.

[0009] A display panel according to an exemplary embodiment includes: a light-emitting element; a first transistor connected between a first power line and the light-emitting element, to which a first driving voltage is applied; a fourth transistor including a gate, a first connection end, and a second connection end, the gate being connected to a scan line for transmitting a scan signal, the first connection end being connected to a first data line to which a bias voltage is applied, and the second connection end being connected to the gate of the first transistor; a fifth transistor including a gate, a first connection end, and a second connection end, the gate being connected to the scan line, the first connection end being connected to a first sensing line to which a first control voltage is applied, and the second connection end being connected to the source of the first transistor; a first capacitor connected between the gate and the source of the first transistor; a second transistor including a gate, a drain, and a source, the drain being connected to the gate of the first transistor, and the source being connected to a second sensing line to which a second control voltage is applied; a third transistor including a gate, a first connection end, and a second connection end, the gate being connected to the scan line, the first connection end being connected to a second data line to which a gray-scale voltage is applied, and the second connection end being connected to the gate of the second transistor; and a second capacitor including a first electrode and a second electrode, the first electrode being connected to a voltage line to which a reset voltage that monotonically changes during a preset period is applied, and the second electrode being connected to the gate of the second transistor.

[0010] A display device according to an exemplary embodiment includes: a plurality of pixels, each including a first transistor, a second transistor connected to a gate terminal of the first transistor, and an inorganic or microscale light-emitting element connected to an output terminal of the first transistor; a time-division controller that generates bias data based on first characteristic information of the first transistor and generates correction data based on second characteristic information of the second transistor; and a sensing driver that receives the bias data and the correction data and provides a bias voltage corresponding to the bias data and a correction voltage corresponding to the correction data to at least one of the plurality of pixels.

[0011] The display device may include: a first driving circuit connected to the output terminal of the first transistor and controlling the magnitude of a driving current supplied to the light-emitting element based on the bias voltage; and a second driving circuit including the second transistor and controlling the pulse width of the driving current based on the correction voltage.

[0012] The second driving circuit may include a third transistor and a correction capacitor both connected to the gate terminal of the second transistor, wherein the correction voltage responds to the correction capacitor, wherein the third transistor includes a gate terminal, a first connection end, and a second connection end, the gate terminal is connected to a scan line, the first connection end is connected to a second data line to which the correction voltage is applied, the second connection end is connected to the gate terminal of the second transistor, wherein the correction capacitor includes a first electrode and a second electrode, the first electrode is connected to a voltage line to which a clearing voltage that monotonically changes during a preset period is applied, the second electrode is connected to the gate terminal of the second transistor; and the first driving circuit may include a fourth transistor connected to the gate terminal of the first transistor, a fifth transistor connected to the output terminal of the first transistor, and a bias capacitor connected between the gate terminal and the output terminal of the first transistor, wherein the bias voltage responds to the bias capacitor, and the gate terminal of the first transistor is connected to a first data line to which the bias voltage is applied through the fourth transistor.

[0013] Other embodiments in addition to the above embodiments may become apparent through the drawings, claims, and / or detailed description of the present disclosure. Description of the Drawings

[0014] Through the following description with reference to the drawings, the above and other embodiments of the present disclosure will become more apparent. In the drawings:

[0015] Figure 1 is a schematic block diagram of a display panel according to an embodiment;

[0016] Figure 2 is a block diagram of a timing control unit according to an embodiment;

[0017] Figure 3 is a circuit diagram of a pixel according to an embodiment;

[0018] Figure 4 is a timing diagram during a frame time period for driving Figure 3 the pixels in a display mode;

[0019] Figure 5 is a circuit diagram of a pixel and a data sensing circuit connected to the pixel according to an embodiment; and

[0020] Figure 6 is a timing diagram for driving Figure 5 the pixel and the data sensing circuit in a sensing mode. DETAILED DESCRIPTION

[0021] Now, embodiments will be described in detail with reference to the drawings. Examples of the embodiments are shown in the drawings, where the same reference numerals can always refer to the same elements. In this regard, the present embodiments can have different forms and should not be construed as limited to the descriptions set forth herein. Accordingly, the embodiments are described below with reference to the drawings to explain aspects of the present specification by way of example, and not limited thereto. As used herein, the term "and / or" includes any combination and all combinations of one or more of the related listed items. Throughout the disclosure, the expression "at least one of a, b, and c" can represent only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0022] Since the present disclosure allows various changes and many embodiments, specific embodiments will be shown in the drawings and described in detail in the written description. Through the exemplary embodiments described below with reference to the drawings, features, effects, and methods of achieving the features and effects will become apparent. However, the present disclosure is not limited to the exemplary embodiments described below and can be implemented in various forms.

[0023] Hereinafter, embodiments of the present disclosure will be described in more detail with reference to the drawings. To clearly describe the present disclosure, parts irrelevant to the description have been omitted, and in the description with reference to the drawings, the same or identical components can be given the same or identical reference numerals, and redundant descriptions thereof can be omitted.

[0024] Although terms such as "first", "second", etc. can be used to describe various elements, such elements are not necessarily limited to the above terms. The above terms are only used to distinguish one element from another. In the following embodiments, unless there is a clearly different meaning in the context, the use of a singular expression includes a plural expression. When a part is referred to as being "connected" to another part, the part can be directly connected to the other part, indirectly connected to the other part, the part can also be "electrically connected" to the other part and there are elements between them. When a part is referred to as including an element, unless otherwise described, it can also include another element in addition to the element, rather than excluding the existence of other elements.

[0025] Figure 1 A display panel 100 according to an embodiment is shown. Figure 2 An embodiment of Figure 1 a part of the timing control unit 140 is shown.

[0026] Referring to Figure 1 , the display panel 100 may include a display unit 110, a gate clear driving unit 120, a data sensing driving unit 130 (or referred to as a sensing driver), a timing control unit 140 (or referred to as a time division controller), and a voltage generation unit 150.

[0027] The display unit 110 includes pixels PX. Although only one pixel PX is shown in Figure 1 for ease of understanding, a plurality of pixels PX may be arranged in the display unit 110. The pixels PX may be arranged in a matrix form, and the matrix form includes, for example, a plurality of pixel rows extending in a first direction (i.e., the row direction) and a plurality of pixel columns extending in a second direction (i.e., the column direction).

[0028] Two or more pixels PX may constitute a unit pixel. Figure 1 The pixel PX shown in

[0029] may correspond to a sub-pixel that is part of the unit pixel.

[0030] Each pixel PX may be connected to a scan line SL[N] extending, for example, in a row direction and a voltage line VL, and may be connected to a first data line DL1 and a second data line DL2 extending, for example, in a column direction, and a first sensing line SSL1 and a second sensing line SSL2. Each pixel PX may be connected to a first power line PL1 and a second power line PL2.

[0031] When the display unit 110 includes pixels PX arranged in a matrix form, the display unit 110 may include: a plurality of scan lines including the scan line SL[N], a plurality of voltage lines including the voltage line VL, a plurality of first data lines including the first data line DL1, a plurality of second data lines including the second data line DL2, a plurality of first sensing lines including the first sensing line SSL1, a plurality of second sensing lines including the second sensing line SSL2, and a plurality of first power lines including the first power line PL1. The display unit 110 may further include a plurality of second power lines PL2 including the second power line PL2.

[0032] The scan line SL[N] and the voltage line VL may extend, for example, in a row direction and may be connected to the gate clear driving unit 120. The first data line DL1, the second data line DL2, the first sensing line SSL1, and the second sensing line SSL2 may extend, for example, in a column direction and may be connected to the data sensing driving unit 130. The first power line PL1 and the second power line PL2 may be connected to the voltage generating unit 150.

[0033] Hereinafter, the scan line SL[N], the voltage line VL, the first data line DL1 and the second data line DL2, the first sensing line SSL1 and the second sensing line SSL2, and the first power line PL1 and the second power line PL2, all of which are connected to the pixel PX, may be described in more detail.

[0034] Each pixel PX includes a light emitting element and a pixel circuit that outputs a driving current to the light emitting element. The light emitting element may be an inorganic light emitting diode (LED) manufactured using an inorganic material. The light emitting element may be a micro LED having a size on the order of, for example, 100 micrometers (μm) or less. The light emitting element may be an LED that emits light of a specific color, such as a red LED, a green LED, and a blue LED.

[0035] The pixel circuit includes a plurality of transistors, as well as a first capacitor and a second capacitor. The plurality of transistors includes a first transistor and a second transistor. The pixel circuit can store a bias voltage DATA_bias and a grayscale voltage DATA_grey in response to a scan signal, and can output a driving current to the light-emitting element. The driving current has a magnitude determined based on the bias voltage DATA_bias and a pulse width determined based on the grayscale voltage DATA_grey. The light-emitting element emits light with an expected wavelength and brightness during an expected emission duration through a driving current with a controlled magnitude and a controlled pulse width, such that grayscale can be accurately presented.

[0036] The pixel circuit includes a first transistor, a first driving circuit, and a second driving circuit including a second transistor. The first transistor is connected to the light-emitting element and outputs a driving current to the light-emitting element. The magnitude of the driving current is determined according to the magnitude of the voltage applied between the gate and the source of the first transistor.

[0037] The first driving circuit is configured to control the magnitude of the driving current based on the bias voltage DATA_bias. The first driving circuit can apply a voltage for keeping the magnitude of the driving current substantially constant based on the bias voltage DATA_bias between the gate and the source of the first transistor.

[0038] The second driving circuit includes a second transistor configured to control the pulse width of the driving current based on the grayscale voltage DATA_grey. The second driving circuit can receive the grayscale voltage DATA_grey and a clear voltage Sweep that monotonically (such as but not limited to substantially linearly) changes during a preset period, and can control the emission duration of the light-emitting element based on the grayscale voltage DATA_grey and the clear voltage Sweep. The following can be referred to Figure 3 for a more detailed description of the pixel circuit.

[0039] The gate clear driving unit 120 can generate a clear voltage Sweep and a plurality of scan signals SCAN based on a first control signal CONT1 provided by the timing control unit 140. The gate clear driving unit 120 can sequentially generate the scan signals SCAN. The sequentially generated scan signals SCAN can be supplied to the pixel PX via the scan line SL[N]. The pixel PX can receive the scan signals SCAN via the scan line SL[N].

[0040] The gate clearing driving unit 120 may generate a clearing voltage Sweep that linearly changes substantially during a preset period and provide the clearing voltage Sweep to the pixel PX via a voltage line VL. The clearing voltage Sweep may be a voltage having a substantially linearly increasing or decreasing magnitude during a preset period (such as a emission period) and having a constant magnitude during a period other than the preset period (such as a data writing period). The pixel PX may receive the clearing voltage Sweep via the voltage line VL.

[0041] In a display mode in which the display panel 100 displays an image, the data sensing driving unit 130 may generate a bias voltage DATA_bias, a grayscale voltage DATA_grey, and a first control voltage CV1 and a second control voltage CV2 based on bias data DATA2, correction data DATA3, and a control signal CONT2 provided from the timing control unit 140.

[0042] The data sensing driving unit 130 generates the bias voltage DATA_bias by digital-to-analog conversion of the bias data DATA2 based on the second control signal CONT2, amplifies the bias voltage DATA_bias, and outputs the amplified bias voltage DATA_bias to the first data line DL1. The data sensing driving unit 130 generates the grayscale voltage DATA_grey (or referred to as a correction voltage) by digital-to-analog conversion of the correction data DATA3 based on the second control signal CONT2, amplifies the grayscale voltage DATA_grey, and outputs the amplified grayscale voltage DATA_grey to the second data line DL2. In the display mode, the data sensing driving unit 130 may generate the second control voltage CV2 based on the second control signal CONT2 and output the second control voltage CV2 to the second sensing line SSL2, and may generate the first control voltage CV1 and output the first control voltage CV1 to the first sensing line SSL1. The pixel PX may receive the bias voltage DATA_bias via the first data line DL1, receive the grayscale voltage DATA_grey via the second data line DL2, and receive the first control voltage CV1 and the second control voltage CV2 via the first sensing line SSL1 and the second sensing line SSL2, respectively.

[0043] The data sensing driving unit 130 may generate a reference bias voltage, a reference grayscale voltage, and a reference source voltage for sensing characteristics of the first transistor and the second transistor in the pixel PX in a sensing mode, and generate first sensing data SD1 and second sensing data SD2 by sensing magnitudes of currents output by the first transistor and the second transistor via the first sensing line SSL1 and the second sensing line SSL2, respectively. The data sensing driving unit 130 may provide the first sensing data SD1 and the second sensing data SD2 to the timing control unit 140.

[0044] The data sensing driving unit 130 may include a sensing circuit for generating first sensing data SD1 and second sensing data SD2. The sensing circuit may include a plurality of switches, and the switches may be controlled based on a second control signal CONT2. The sensing circuit will be described in more detail below with reference to Figure 5 the sensing circuit.

[0045] The voltage generation unit 150 generates a first driving voltage PVDD and a second driving voltage PVSS for driving the display panel 100. The first driving voltage PVDD is applied to the first power line PL1, and the second driving voltage PVSS is applied to the second power line PL2. During an emission period in which the light-emitting element emits light, the voltage level of the first driving voltage PVDD may be higher than the voltage level of the second driving voltage PVSS.

[0046] The timing control unit 140 may control the display unit 110 by controlling the gate clearing driving unit 120, the data sensing driving unit 130, and the voltage generation unit 150. The timing control unit 140 may receive a control signal CONT and image data DATA1 from an external device. The timing control unit 140 may generate a first control signal CONT1 and a second control signal CONT2 by using the control signal CONT. The timing control unit 140 may generate bias data DATA2 based on first characteristic information of a first transistor. The timing control unit 140 may generate corrected data DATA3 by correcting the image data DATA1 based on second characteristic information of a second transistor.

[0047] With reference to Figure 2 , the timing control unit 140 according to an embodiment may include a compensation coefficient calculation unit 142, a compensation unit 144, and a memory 146.

[0048] The compensation coefficient calculation unit 142 may receive the first sensing data SD1 and the second sensing data SD2. The compensation coefficient calculation unit 142 may calculate a first compensation coefficient for compensating for changes in the characteristics of the first transistor of the pixel circuit based on the first sensing data SD1. The compensation coefficient calculation unit 142 may calculate a second compensation coefficient for compensating for changes in the characteristics of the second transistor of the pixel circuit based on the second sensing data SD2. The characteristics of the transistor may include the threshold voltage and / or mobility of the transistor. The first compensation coefficient may be referred to as first characteristic information of the first transistor, and the second compensation coefficient may be referred to as second characteristic information of the second transistor. The first characteristic information and the second characteristic information calculated by the compensation coefficient calculation unit 142 may be stored in the memory 146.

[0049] The compensation unit 144 may generate bias data DATA2 for compensating for changes in the characteristics of the first transistor based on a first compensation coefficient. The compensation unit 144 may provide the bias data DATA2 to the data sensing and driving unit 130.

[0050] The compensation unit 144 may receive image data DATA1. The compensation unit 144 may generate corrected data DATA3 by correcting the image data DATA1 based on a second compensation coefficient. The corrected data DATA3 is data obtained by correcting the image data DATA1 to compensate for changes in the characteristics of the second transistor. The compensation unit 144 may provide the corrected data DATA3 to the data sensing and driving unit 130.

[0051] Return reference Figure 1 Referring back, the display panel 100 may have a display period in which an image is displayed and a non-display period in which no image is displayed. The display period may include a plurality of frame time periods. Each frame time period includes a data writing period and an emission period, during which the pixel circuit stores a bias voltage and a grayscale voltage in response to a scan signal, and the light-emitting element may emit light during the emission period.

[0052] The non-display period includes a first sensing period for sensing the current output from the first transistor to compensate for changes in the characteristics of the first transistor of the pixel circuit, and a second sensing period for sensing the current output from the second transistor to compensate for changes in the characteristics of the second transistor of the pixel circuit.

[0053] A reference bias voltage and a reference source voltage are applied to the first transistor during the first sensing period, and the data sensing and driving unit 130 may sense the current output from the first transistor while changing the level of the reference bias voltage. A reference grayscale voltage and a reference source voltage are applied to the second transistor during the second sensing period, and the data sensing and driving unit 130 may sense the current output from the second transistor while changing the level of the reference grayscale voltage.

[0054] The second sensing period may be arranged immediately after the first sensing period in time. The first sensing period and the second sensing period may be arranged immediately after or immediately before the display period in time. For each preset period, there may be a first sensing period and a second sensing period.

[0055] The first transistor included in the pixel PX preferably has the same characteristics, but may have different characteristics due to process errors, degradation, etc. When a change in the characteristics of the first transistor occurs, a change in the magnitude of the driving current output from the pixel circuit of the pixel PX to the light-emitting element occurs. Therefore, when a change in the magnitude of the driving current occurs, the light-emitting element of the pixel PX emits light with different brightness levels, and the wavelength of the emitted light also varies. According to the present embodiment, the change in the magnitude of the driving current caused by the change in the characteristics of the first transistor can be compensated by the bias voltage DATA_bias applied to the pixel PX.

[0056] The second transistor included in the pixel PX preferably has the same characteristics, but may have different characteristics due to process errors, degradation, etc. When a change in the characteristics of the second transistor occurs, the pulse width of the driving current output from each pixel circuit of the pixel PX to the light-emitting element cannot be accurately controlled. When the pulse width cannot be accurately controlled, the gray level presented by each pixel PX becomes inaccurate. According to the present embodiment, the change in the pulse width of the driving current caused by the change in the characteristics of the second transistor can be compensated by the gray voltage DATA_grey applied to the pixel PX.

[0057] Figure 3 An exemplary electronic circuit for the pixel PX according to an embodiment is shown.

[0058] Referring to Figure 3 , the pixel PX includes a light-emitting element mLED and a pixel circuit that outputs a driving current Id to the light-emitting element mLED. The pixel circuit includes a first transistor T1, a first driving circuit 10, and a second driving circuit 20.

[0059] The light-emitting element mLED may be a micro-LED that uses an inorganic material as a light-emitting material and has a micron-sized dimension. As Figure 3 shown, the anode of the light-emitting element mLED may be connected to the source of the first transistor T1, and the cathode of the light-emitting element mLED may be connected to the second power line PL2 to which the second driving voltage PVSS is applied. As another alternative example, the light-emitting element mLED may be connected between the first power line PL1 to which the first driving voltage PVDD is applied and the drain of the first transistor T1.

[0060] The first transistor T1 may be as Figure 3The n-type metal oxide semiconductor field effect transistor (MOSFET) shown in FIG. The second transistor T2, the third transistor T3, the fourth transistor T4 and the fifth transistor T5 may also be n-type MOSFETs. The first transistor T1 to the fifth transistor T5 may be a thin film transistor. Each of the first transistor T1 to the fifth transistor T5 may include a semiconductor material of a metal oxide. For example, each of the first transistor T1 to the fifth transistor T5 may include an active layer formed of a metal oxide.

[0061] In the following, Figure 3 , an embodiment in which the first transistor T1 to the fifth transistor T5 of the pixel PX are n-type MOSFETs is described as shown in . However, the first transistor T1 to the fifth transistor T5 of the pixel PX may alternatively be p-type MOSFETs, and therefore, the connection relationship of the pixel circuit may be changed. That is, the spirit of the present disclosure may be similarly applied to a pixel PX including a p-type MOSFET and a display panel including the pixel PX.

[0062] The first transistor T1 includes a gate connected to the first node A, a drain connected to the first power line PL1 to which the first driving voltage PVDD is applied, and a source connected to the anode of the light emitting element mLED. The first transistor T1 outputs a driving current Id whose magnitude is controlled according to the magnitude of the voltage applied to the gate of the first transistor T1.

[0063] The first driving circuit 10 includes a fourth transistor T4, a fifth transistor T5 and a first capacitor (or bias capacitor) Cst. The first driving circuit 10 is connected to a scan line SL[N] transmitting a scan signal SCAN[N], a first data line DL1 applied with a bias voltage DATA_bias, and a first sensing line SSL1 applied with a first control voltage CV1.

[0064] The fourth transistor T4 includes a gate connected to the scan line SL[N], a first connection terminal connected to the first data line DL1, and a second connection terminal connected to the first node A and the gate of the first transistor T1. The fourth transistor T4 applies a bias voltage DATA_bias to the gate of the first transistor T1 in response to the scan signal SCAN[N].

[0065] The fifth transistor T5 includes a gate connected to the scan line SL[N], a first connection terminal connected to the first sensing line SSL1, and a second connection terminal connected to the source of the first transistor T1. The fifth transistor T5 applies the first control voltage CV1 to the source of the first transistor T1 in response to the scan signal SCAN[N].

[0066] The first capacitor Cst includes a first electrode connected to the first node A and the gate of the first transistor T1, and a second electrode connected to the source of the first transistor T1. The first capacitor Cst stores the difference between the bias voltage DATA_bias and the first control voltage CV1 respectively transmitted through the fourth transistor T4 and the fifth transistor T5 in response to the scan signal SCAN[N]. Since the first capacitor Cst is connected between the gate and the source of the first transistor T1, the first transistor T1 outputs a drive current Id having a magnitude determined based on the voltage stored in the first capacitor Cst to the light-emitting element mLED.

[0067] The bias voltage DATA_bias is a voltage corresponding to the bias data DATA2 generated based on the characteristics (such as the threshold voltage and / or mobility) of the first transistor T1 sensed by the Figure 1 data sensing and driving unit 130. That is, since the bias voltage DATA_bias is a voltage that makes the drive current Id have a preset magnitude, even if the characteristics of the first transistor T1 are irregular due to process errors, deterioration, time variation, etc., the drive current Id can have a constant magnitude.

[0068] The second driving circuit 20 includes a second transistor T2, a third transistor T3, and a second capacitor (or correction capacitor) Cswp. The second driving circuit 20 is connected to the scan line SL[N] for transmitting the scan signal SCAN[N], the second data line DL2 to which the gray-scale voltage DATA_grey is applied, the second sensing line SSL2 to which the second control voltage CV2 is applied, and the voltage line VL to which the clear voltage Sweep is applied, and the clear voltage Sweep changes substantially linearly during a preset period.

[0069] The second transistor T2 includes a gate connected to the second node B, a drain connected to the gate of the first transistor T1, and a source connected to the second sensing line SSL2. The second transistor T2 can turn off the first transistor T1 by applying the second control voltage CV2 to the gate of the first transistor T1 according to the voltage applied to the gate of the second transistor T2.

[0070] The third transistor T3 includes a gate connected to the scan line SL[N], a first connection end connected to the second data line DL2, and a second connection end connected to the gate of the second transistor T2. The third transistor T3 applies the gray-scale voltage DATA_grey to the gate of the second transistor T2 in response to the scan signal SCAN[N].

[0071] The second capacitor Cswp includes a first electrode connected to the voltage line VL and a second electrode connected to the gate of the second transistor T2. The second capacitor Cswp can store the grayscale voltage DATA_grey transmitted through the third transistor T3 in response to the scan signal SCAN[N] during the data writing period, and the voltage of the second node B can increase monotonically (such as but not limited to linearly) through the sweep voltage Sweep that varies linearly during the emission period. When the linearly rising voltage of the second node B is higher than the threshold voltage of the second transistor T2, the second transistor T2 can be turned on, and when the second control voltage CV2 is applied to the gate of the first transistor T1, the first transistor T1 can be turned off.

[0072] When the grayscale voltage DATA_grey is low, the time point at which the voltage of the second node B is higher than the threshold voltage of the second transistor T2 is delayed, and the first transistor T1 is turned off with a delay. Therefore, the emission duration during which the light-emitting element mLED emits light is extended. On the contrary, when the grayscale voltage DATA_grey is high, the voltage of the second node B quickly becomes higher than the threshold voltage of the second transistor T2, and the first transistor T1 is quickly turned off. Therefore, the emission duration during which the light-emitting element mLED emits light is shortened. By using this method to control the emission duration of the light-emitting element mLED, grayscale can be accurately presented.

[0073] Preferably, all of the threshold voltages of the second transistors T2 of the pixels PX are uniform, but due to process errors, deterioration, etc., there will be variations in the threshold voltages of the second transistors T2. According to this embodiment, the grayscale voltage DATA_grey is a voltage corresponding to the correction data DATA3, and the correction data DATA3 is generated by correcting the image data DATA1 based on the characteristics (such as threshold voltage and / or mobility) of the second transistors T2 sensed by Figure 1 the data sensing and driving unit 130. That is, since the grayscale voltage DATA_grey is a voltage that compensates for the variations in the characteristics of each second transistor T2, even if the characteristics of each second transistor T2 are irregular or change over time, the second transistor T2 can be accurately turned off at the expected time by using the sweep voltage Sweep. Therefore, grayscale can be accurately presented.

[0074] Now, the operation of the pixel PX will be described with reference to Figure 4 Describe the operation of the pixel PX.

[0075] Figure 4 Shows the signal timing during the frame time period for driving Figure 3 the pixel PX in the display mode.

[0076] Refer to Figure 4, in a display mode where pixels PX can display an image, new data can be received per frame time period, and grayscale corresponding to the received data can be presented. One frame time period 1FRAME can include a data addressing and writing period TP1 and a resetting and emitting period TP2.

[0077] The data addressing and writing period TP1 is a period during which the pixel PX stores a bias voltage DATA_bias in the first capacitor Cst and stores a grayscale voltage DATA_grey in the second capacitor Cswp in response to a scan signal SCAN[N]. The resetting and emitting period TP2 is a period during which the light-emitting element mLED emits light through a drive current Id.

[0078] The data addressing and writing period TP1 can be divided into a first period to a fifth period DP1, DP2, DP3, DP4, and DP5, and the resetting and emitting period TP2 can be divided into a sixth period DP6 and a seventh period DP7. It can be understood that the first period DP1 is a standby period, the second period DP2 is a pre-charging period, the third period DP3 is a data input period, the fourth period DP4 is a data holding period, and the fifth period DP5 is an emission preparation period. Additionally, it can be understood that the sixth period DP6 is a resetting and emission start period, and the seventh period DP7 is a resetting and emission stop period.

[0079] In the first period DP1, the first drive voltage PVDD can transition to a low level. The first drive voltage PVDD can drop to the same level as the second drive voltage PVSS. In this case, the first drive voltage PVDD can be, for example, -3V. The voltage level of the source of the first transistor T1 also substantially drops to a low level. The first drive voltage PVDD can remain at a low level (e.g., -3V) during the data addressing and writing period TP1.

[0080] The second drive voltage PVSS can be at a low level (e.g., -3V) during one frame time period 1FRAME. The first control voltage CV1 can also be at a low level (e.g., -3V) during one frame time period 1FRAME.

[0081] The second control voltage CV2 can be at a high level (e.g., 2V) in the first period DP1, and the sweep voltage Sweep can be at a high level (e.g., 6V) in the first period DP1. The scan signal SCAN[N] can be at a low level, and the third transistor T3 to the fifth transistor T5 can be cut off.

[0082] In the second period DP2, the first driving voltage PVDD, the second driving voltage PVSS, and the first control voltage CV1 may be at a low level (e.g., -3V), the second control voltage CV2 may be at a high level (e.g., 2V), and the erase voltage Sweep may be at a high level (e.g., 6V).

[0083] The scan signal SCAN[N] may transition to a high level in the second period DP2. Thus, the third transistor T3 to the fifth transistor T5 may be turned on. In this case, the bias voltage DATA_bias and the grayscale voltage DATA_grey of the pixel PX to be written in the previous row are respectively applied to the first data line DL1 and the second data line DL2. The bias voltage DATA_bias and the grayscale voltage DATA_grey of the pixel PX to be written in the previous row are respectively applied to the first node A and the second node B via the fourth transistor T4 and the third transistor T3. In this case, as Figure 4 shown, the voltage of the first node A may increase to a high level, and the voltage of the second node B may decrease to an intermediate level.

[0084] The bias voltage DATA_bias is approximately (4 + α)V, where α may be a value determined according to the characteristics of the first transistor T1. The grayscale voltage DATA_grey may be a value between approximately -7V and approximately 0V set according to the grayscale data. When the grayscale value of the grayscale data is low, the grayscale voltage DATA_grey may be at a higher voltage level, and when the grayscale value of the grayscale data is high, the grayscale voltage DATA_grey may be at a lower voltage level.

[0085] In the second period DP2, the first capacitor Cst and the second capacitor Cswp are precharged with the bias voltage DATA_bias and the grayscale voltage DATA_grey of the pixel PX to be written in the previous row, so that the time length in the third period DP3 can be reduced.

[0086] The bias voltage DATA_bias (e.g., (4 + α)V) of the pixel PX to be written in the previous row is applied to the gate of the first transistor T1, and the first control voltage CV1 with a low level (e.g., -3V) is applied to the source of the first transistor T1. Thus, the first transistor T1 is turned on. However, since both the first driving voltage PVDD and the second driving voltage PVSS are at a low level, the light-emitting element mLED does not emit light.

[0087] A second control voltage CV2 having a high level (e.g., 2V) is applied to the source of the second transistor T2, and a bias voltage DATA_bias (e.g., (4 + α)V) to be written to the pixel PX in the previous row is applied to the drain of the second transistor T2, but a gray-scale voltage DATA_grey (e.g., from about -7V to about 0V) to be written to the pixel PX in the previous row is applied to the gate of the second transistor T2. Accordingly, the second transistor T2 is not turned on.

[0088] In the third period DP3, the first driving voltage PVDD, the second driving voltage PVSS, and the first control voltage CV1 may be at a low level (e.g., -3V), the second control voltage CV2 may be at a high level (e.g., 2V), and the erase voltage Sweep may be at a high level (e.g., 6V). The scan signal SCAN[N] is at a high level, and the third transistor T3 to the fifth transistor T5 are turned on.

[0089] The bias voltage DATA_bias and the gray-scale voltage DATA_grey to be written to the current pixel PX are received via the first data line DL1 and the second data line DL2. The bias voltage DATA_bias and the gray-scale voltage DATA_grey are applied to the first node A and the second node B, i.e., the first capacitor Cst and the second capacitor Cswp, respectively.

[0090] The bias voltage DATA_bias (e.g., (4 + α)V) is applied to the gate of the first transistor T1, and the first control voltage CV1 having a low level (e.g., -3V) is applied to the source of the first transistor T1. Accordingly, the first transistor T1 is turned on. However, since both the first driving voltage PVDD and the second driving voltage PVSS are at a low level, the light-emitting element mLED does not emit light.

[0091] A second control voltage CV2 having a high level (e.g., 2V) is applied to the source of the second transistor T2, the bias voltage DATA_bias (e.g., (4 + α)V) is applied to the drain of the second transistor T2, but the gray-scale voltage DATA_grey (e.g., from about -7V to about 0V) is applied to the gate of the second transistor T2. Accordingly, the second transistor T2 is not turned on.

[0092] In the fourth period DP4, the first driving voltage PVDD, the second driving voltage PVSS, and the first control voltage CV1 may be at a low level (e.g., -3V), the second control voltage CV2 may be at a high level (e.g., 2V), and the erase voltage Sweep may be at a high level (e.g., 6V).

[0093] The scan signal SCAN[N] may transition to a low level, and the third transistor T3 to the fifth transistor T5 are turned off.

[0094] The difference between the bias voltage DATA_bias and the first control voltage CV1 with a low level is stored in the first capacitor Cst, and the difference between the grayscale voltage DATA_grey and the blanking voltage Sweep with a high level is stored in the second capacitor Cswp.

[0095] In the fifth period DP5, the first driving voltage PVDD, the second driving voltage PVSS, and the first control voltage CV1 are at a low level (e.g., -3V).

[0096] The second control voltage CV2 and the blanking voltage Sweep can transition to a low level. As Figure 4 shown, after the blanking voltage Sweep first transitions to a low level, the second control voltage CV2 can transition to a low level.

[0097] When the blanking voltage Sweep transitions from a high level (e.g., 6V) to a low level (e.g., 0V), the voltage of the second node B also decreases by 6V. For example, the voltage of the second node B can be between approximately -13V and approximately -6V. Even when the second control voltage CV2 transitions to a low level (e.g., -6V), the voltage of the gate of the second transistor T2 (i.e., the second node B) is not higher than the second control voltage CV2. Therefore, the second transistor T2 is turned off.

[0098] According to this embodiment, when the grayscale value of the grayscale data input to the pixel PX is 0, a grayscale voltage DATA_grey of 0V + Vth2 (where Vth2 is the threshold voltage) can be input to the second data line DL2 in the third period DP3. Here, Vth2 is the threshold voltage of the second transistor T2, and Figure 1The timing control unit 140 can store the threshold voltage information of the second transistor T2. The difference between the erase voltage Sweep with a high level (e.g., 6V) and the gray voltage DATA_grey of 0V+Vth2 is stored across the second capacitor Cswp. In the fifth period DP5, when the erase voltage Sweep changes from a high level (e.g., 6V) to a low level (e.g., 0V), the voltage of the second node B becomes -6V+Vth2, and when the second control voltage CV2 changes to a low level (e.g., -6V), the voltage of the source of the second transistor T2 becomes -6V. Since the voltage corresponding to the threshold voltage (Vth2) of the second transistor T2 is applied between the gate and the source of the second transistor T2, the second transistor T2 conducts and applies the second control voltage CV2 with a low level (e.g., -6V) to the gate of the first transistor T1. The first transistor T1 is turned off due to the second control voltage CV2 with a low level (e.g., -6V). Thereafter, the light-emitting element mLED does not emit light in the sixth period DP6. Since the gray value of the gray data input to the pixel PX is 0, the light-emitting element mLED should not emit light.

[0099] In the sixth period DP6, the first driving voltage PVDD changes to a high level (e.g., 5V). When a voltage difference (e.g., 8V) is generated between the first power line PL1 and the second power line PL2, a current path is formed. The first transistor T1 outputs a driving current Id corresponding to the voltage stored in the first capacitor Cst, and the light-emitting element mLED emits light with a brightness corresponding to the driving current Id. Since the bias voltage DATA_bias stored in the first capacitor Cst is a voltage for compensating the characteristics of the first transistor T1, the driving current Id can have a preset magnitude.

[0100] The erase voltage Sweep increases substantially linearly at a low level (e.g., 0V). Accordingly, the voltage of the second node B (i.e., the gate of the second transistor T2) also increases substantially linearly. The difference between the voltage of the second node B and the second control voltage CV2 with a low level (e.g., -6V) (i.e., the voltage between the gate and the source of the second transistor T2) gradually increases. When the voltage between the gate and the source of the second transistor T2 becomes higher than the threshold voltage of the second transistor T2, the sixth period DP6 ends and the seventh period DP7 starts.

[0101] In the seventh period DP7, since the voltage between the gate and the source of the second transistor T2 is higher than the threshold voltage of the second transistor T2, the second transistor T2 conducts. The conducting second transistor T2 applies the second control voltage CV2 with a low level (e.g., -6V) to the gate of the first transistor T1, and the first transistor T1 is turned off.

[0102] Determine the timing of the conduction of the second transistor T2 based on the grayscale voltage DATA_grey and the threshold voltage of the second transistor T2. Since the grayscale voltage DATA_grey is a voltage for compensating the characteristics (e.g., threshold voltage) of the second transistor T2, the timing of the conduction of the second transistor T2 can be precisely controlled, and the grayscale value of the grayscale data input to the pixel PX can be precisely presented.

[0103] Return reference Figure 1 , the voltage generation unit 150 can apply a first driving voltage PVDD with a low level (e.g., -3V) to the first power line PL1 during the data addressing and writing period TP1, and can apply a first driving voltage PVDD with a high level (e.g., 5V) to the first power line PL1 during the clear and emission period TP2.

[0104] The gate clear driving unit 120 can sequentially output the scan signal SCAN[N] during the data addressing and writing period TP1. The gate clear driving unit 120 can output the scan signal SCAN[N] to the scan line SL[N] connected to the pixel PX during the second period DP2 and the third period DP3. The gate clear driving unit 120 can output a substantially linearly increasing clear voltage Sweep to the voltage line VL during the clear and emission period TP2.

[0105] The data sensing driving unit 130 can output a second control voltage CV2 with a high level (e.g., 2V) to the second sensing line SSL2 during the data addressing and writing period TP1, and can output a second control voltage CV2 with a low level (e.g., -6V) to the second sensing line SSL2 during the clear and emission period TP2.

[0106] Figure 5 Shows a circuit for the pixel PX' according to an embodiment and a data sensing circuit 230 connected to the pixel PX'.

[0107] Reference Figure 5 , the pixel PX' is similar to Figure 3 the pixel PX shown in, so the repeated description can be omitted.

[0108] The data sensing circuit 230 can be included in the data sensing driving unit 130 and connected to the pixel PX'. The data sensing circuit 230 is connected to the pixel PX' via the first sensing line SSL1 and the second sensing line SSL2. The data sensing circuit 230 is connected to the pixel PX' via the first data line DL1 and the second data line DL2.

[0109] The data sensing circuit 230 includes a sensing circuit 233, a first control voltage output unit 234, a second control voltage output unit 235, and a switch circuit including at least some of a plurality of switches S1, S2, S3, S4, S5, and S6.

[0110] The sensing circuit 233 generates first sensed data SD1 by sensing the magnitude of a first current I1 output by the first transistor T1 when a reference bias voltage DATA_bias and a reference source voltage Vpre are applied to the first driving circuit 10 (see Figure 1 ), and generates second sensed data SD2 by sensing the magnitude of a second current I2 output by the second transistor T2 when a reference gray voltage DATA_grey and a reference source voltage Vpre are applied to the second driving circuit 20 (see Figure 1 ).

[0111] The reference bias voltage DATA_bias refers to the voltage input to the first data line DL1 during a first sensing period for sensing the characteristics of the first transistor T1, and the reference gray voltage DATA_grey refers to the voltage input to the second data line DL2 during a second sensing period for sensing the characteristics of the second transistor T2. The reference source voltage Vpre refers to the voltage applied by the sensing circuit 233 to the first sensing line SSL1 or the second sensing line SSL2. The reference source voltage Vpre can be generated by the data sensing driving unit 130.

[0112] The sensing circuit 233 includes an integrated circuit and an analog-to-digital conversion circuit (ADC) 232. The integrated circuit includes an operational amplifier 231 and a third capacitor Cfb. The sensing circuit 233 is connected to the first sensing line SSL1 via the third switch S3 and is connected to the second sensing line SSL2 via the fourth switch S4. During the first sensing period, the third switch S3 is closed and the fourth switch S4 is open. During the second sensing period, the third switch S3 is open and the fourth switch S4 is closed.

[0113] The operational amplifier 231 includes a first input terminal connected to the third switch S3 and the fourth switch S4, a second input terminal to which the reference source voltage Vpre is applied, and an output terminal connected to the analog-to-digital conversion circuit 232. The third capacitor Cfb is connected between the first input terminal and the output terminal of the operational amplifier 231. The first switch S1 can be connected in parallel with the third capacitor Cfb.

[0114] When the first switch S1 is closed, all the charges stored in the third capacitor Cfb are discharged. When the first switch S1 is opened, the current flowing into the first input terminal of the operational amplifier 231 accumulates in the third capacitor Cfb, and the voltage between the two electrodes of the third capacitor Cfb increases in proportion to the accumulated current. The voltage at the output terminal of the operational amplifier 231 decreases through the voltage between the two electrodes of the third capacitor Cfb. The analog-to-digital conversion circuit 232 can generate sensed data by sensing the voltage Vout of the output node OUT connected to the output terminal of the operational amplifier 231.

[0115] The second switch S2 can be arranged between the output terminal of the operational amplifier 231 and the output node OUT. When the second switch S2 is opened, the voltage at the output terminal of the operational amplifier 231 can be sampled in the output node OUT, and the analog-to-digital conversion circuit 232 can sense the sampled voltage Vout in the output node OUT.

[0116] The first control voltage output unit 234 is connected to the first sensing line SSL1 via the fifth switch S5. The second control voltage output unit 235 is connected to the second sensing line SSL2 via the sixth switch S6. According to the second control signal CONT2 (see Figure 1 ), the fifth switch S5 and the sixth switch S6 can both be closed in the display mode and opened in the sensing mode.

[0117] The data sensing circuit 230 may further include a reference bias voltage output unit that outputs a reference bias voltage DATA_bias to the first data line DL1, and a reference grayscale voltage output unit that outputs a reference grayscale voltage DATA_grey to the second data line DL2.

[0118] Figure 6 Shows the timing for driving Figure 5 the pixel PX' and the data sensing circuit 230 in the sensing mode.

[0119] Refer to Figure 6 , the data sensing circuit 230 can sense the characteristics of the first transistor T1 of the pixel PX' in the first sensing period STP1, and sense the characteristics of the second transistor T2 of the pixel PX' in the second sensing period STP2. The characteristics of the first transistor T1 may be threshold voltage characteristics and / or mobility characteristics, and the characteristics of the second transistor T2 may be threshold voltage characteristics.

[0120] The first sensing period STP1 can be divided into a first period to a fourth period SP1, SP2, SP3, and SP4, and the second sensing period STP2 can be divided into a fifth period to an eighth period SP5, SP6, SP7, and SP8. The first period SP1 is a standby period, the second period SP2 is a T1 bias period, the third period SP3 is a first current accumulation period, and the fourth period SP4 is a first sensing period. The fifth period SP5 is a standby period, the sixth period SP6 is a T2 bias period, the seventh period SP7 is a second current measurement period, and the eighth period SP8 is a second sensing period.

[0121] The first driving voltage PVDD can be at a high level during the first sensing period STP1 and can be at a low level during the second sensing period STP2. The second driving voltage PVSS can be at a low level during both the first sensing period STP1 and the second sensing period STP2.

[0122] The scan signal SCAN[N] is applied to the pixel PX' during the second period SP2 and the third period SP3 of the first sensing period STP1, such that the third transistor T3 to the fifth transistor T5 can be turned on. The scan signal SCAN[N] is applied to the pixel PX' during the sixth period SP6 and the seventh period SP7 of the second sensing period STP2, such that the third transistor T3 to the fifth transistor T5 can be turned on.

[0123] During the first period SP1, the first switch S1 to the third switch S3 are closed, and the fourth switch S4 is open. The reference source voltage Vpre input to the second input terminal of the operational amplifier 231 is transmitted to the output terminal of the operational amplifier 231 using the first switch S1, and the output voltage Vout of the output node OUT becomes equal to the reference source voltage Vpre using the second switch S2.

[0124] The third transistor T3 to the fifth transistor T5 are turned on due to the scan signal SCAN[N] during the second period SP2 and the third period SP3. Synchronously with the scan signal SCAN[N], a reference bias voltage DATA_bias having a high level is applied to the first data line DL1. The reference bias voltage DATA_bias is applied to the gate of the first transistor T1 via the fourth transistor T4.

[0125] The reference source voltage Vpre is applied to the source of the first transistor T1 via the fifth transistor T5. The first capacitor Cst stores the difference between the reference bias voltage DATA_bias and the reference source voltage Vpre. The difference between the reference source voltage Vpre and the second driving voltage PVSS having a low level can be set to be less than the threshold voltage of the light-emitting element mLED. Since the light-emitting element mLED is non-conductive, the first current I1 output from the first transistor T1 does not flow to the second power line PL2.

[0126] A grayscale voltage DATA_grey having a low level is applied synchronously with a scan signal SCAN[N] such that the second transistor T2 can be turned off during a second period SP2 to a fourth period SP4. As another example, since a clear voltage Sweep is held at a low level, the second transistor T2 can be turned off.

[0127] The first transistor T1 outputs a first current I1 having a magnitude determined based on the difference between a reference bias voltage DATA_bias and a reference source voltage Vpre. The first current I1 flows through a fifth transistor T5 and a third switch S3 to a first input terminal of an operational amplifier 231.

[0128] The first switch S1 is closed in the second period SP2 and is opened in the third period SP3. In the second period SP2, the first current I1 flows through the first switch S1 to the output terminal of the operational amplifier 231. When the first switch S1 is opened in the third period SP3, the first current I1 accumulates in a third capacitor Cfb. As the first current I1 accumulates in the third capacitor Cfb, the voltage between the two electrodes of the third capacitor Cfb gradually increases.

[0129] When the reference source voltage Vpre is biased to a first electrode of the third capacitor Cfb connected to the first input terminal of the operational amplifier 231, the voltage at the output terminal of the operational amplifier 231 connected to a second electrode of the third capacitor Cfb decreases due to the voltage between the two electrodes of the third capacitor Cfb decreasing from the reference source voltage Vpre. As Figure 6 shown, the voltage Vout of the output node OUT decreases with time in the third period SP3.

[0130] When the third period SP3 ends, the second switch S2 is opened, and the voltage Vout of the output node OUT no longer decreases. In the fourth period SP4, an analog-to-digital conversion circuit 232 can generate first sensed data SD1 by sensing the voltage Vout of the output node OUT.

[0131] The first sensed data SD1 is related to the threshold voltage and / or mobility of the first transistor T1. A data sensing driving unit 130 (see Figure 1 ) can generate the first sensed data SD1 while changing a reference bias voltage DATA_bias under the control of a timing control unit 140 (see Figure 1 ). The timing control unit 140 can calculate the characteristics of the first transistor T1 based on the magnitude of the reference bias voltage DATA_bias and the value of the first sensed data SD1, and store the characteristics in a memory 146 (see Figure 2 ).

[0132] In the fifth time period SP5, the first switch S1, the second switch S2, and the fourth switch S4 are closed, and the third switch S3 is open. The reference source voltage Vpre input to the second input terminal of the operational amplifier 231 is transmitted to the output terminal of the operational amplifier 231 by the first switch S1, and the output voltage Vout of the output node OUT becomes equal to the reference source voltage Vpre by the second switch S2.

[0133] The third transistor T3 to the fifth transistor T5 are turned on due to the scan signal SCAN[N] in the sixth time period SP6 and the seventh time period SP7. Synchronized with the scan signal SCAN[N], a reference gray voltage DATA_grey with a high level is applied to the second data line DL2, and a bias voltage DATA_bias with a high level is applied to the first data line DL1.

[0134] The bias voltage DATA_bias with a high level is applied to the drain of the second transistor T2 via the fourth transistor T4, and the reference gray voltage DATA_grey with a high level is applied to the gate of the second transistor T2 via the third transistor T3. The reference source voltage Vpre is applied to the source of the second transistor T2 via the fourth switch S4.

[0135] The second transistor T2 outputs a second current I2 having a magnitude determined based on the difference between the reference gray voltage DATA_grey applied to the gate of the second transistor T2 and the reference source voltage Vpre applied to the source of the second transistor T2. The second current I2 flows to the first input terminal of the operational amplifier 231 through the fourth switch S4.

[0136] The first switch S1 is closed in the sixth time period SP6 and open in the seventh time period SP7. In the sixth time period SP6, the second current I2 flows to the output terminal of the operational amplifier 231 through the first switch S1. When the first switch S1 is open in the seventh time period SP7, the second current I2 accumulates in the third capacitor Cfb. As the second current I2 accumulates in the third capacitor Cfb, the voltage between the two electrodes of the third capacitor Cfb gradually increases.

[0137] When the reference source voltage Vpre is biased to the first electrode of the third capacitor Cfb connected to the first input terminal of the operational amplifier 231, the voltage at the output terminal of the operational amplifier 231 connected to the second electrode of the third capacitor Cfb decreases from the reference source voltage Vpre due to the voltage between the two electrodes of the third capacitor Cfb. As Figure 6 shown, the voltage Vout of the output node OUT decreases with time in the seventh time period SP7.

[0138] When the seventh period SP7 ends, the second switch S2 is turned off, and the voltage Vout at the output node OUT no longer decreases. In the eighth period SP8, the analog-to-digital conversion circuit 232 can generate second sensed data SD2 by sensing the voltage Vout at the output node OUT.

[0139] The second sensed data SD2 is related to the threshold voltage and / or mobility of the second transistor T2. The data sensing driving unit 130 (see Figure 1 ) can generate the second sensed data SD2 while changing the reference gray voltage DATA_grey under the control of the timing control unit 140 (see Figure 1 ). The timing control unit 140 can calculate the characteristics of the second transistor T2 based on the magnitude of the reference gray voltage DATA_grey and the value of the second sensed data SD2, and store the characteristics in the memory 146 (see Figure 2 ).

[0140] According to one or more embodiments, a pixel circuit that operates in a time-division driving method to drive a light-emitting element such as a micro LED can be provided. The characteristics of the transistors in the pixel circuit can be sensed by a sensing circuit. When the driving circuit outputs a bias voltage and a gray voltage that compensate for changes in the characteristics of the transistors, the magnitude and pulse width of the driving current output from the pixel circuit to the light-emitting element are precisely controlled. Therefore, the light-emitting element can emit light with precise brightness and color. Accordingly, the display quality of the display panel can be improved.

[0141] In addition, when the pixel circuit has a relatively simple structure, high-density pixels can be fabricated, and a high yield can be obtained even when manufacturing a large-area panel.

[0142] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. The description of features or aspects within each embodiment should generally be considered available for other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the figures, those of ordinary skill in the relevant art will understand that various changes in form and detail can be made therein without departing from the spirit and scope of the present disclosure as defined by the claims.

Claims

1. A display panel, the display panel comprising: a plurality of sub-pixels, each including a light-emitting element and a pixel circuit configured to output a driving current to the light-emitting element, wherein the pixel circuit includes a first transistor and a second transistor; a timing control unit configured to generate bias data based on first characteristic information of the first transistor and generate correction data based on second characteristic information of the second transistor; and a data sensing driving unit configured to receive the bias data and the correction data and output a bias voltage corresponding to the bias data and a gray-scale voltage corresponding to the correction data to the pixel circuit, wherein the pixel circuit includes: the first transistor configured to output the driving current to the light-emitting element, wherein the first transistor is connected to the light-emitting element; a first driving circuit configured to control the magnitude of the driving current based on the bias voltage; and a second driving circuit configured to control the pulse width of the driving current based on the gray-scale voltage, wherein the second driving circuit includes the second transistor, wherein the first transistor and the light-emitting element are connected in series between a first power line to which a first driving voltage is applied and a second power line to which a second driving voltage is applied, the first driving circuit includes: a fourth transistor configured to apply the bias voltage to the gate of the first transistor in response to a scan signal; a fifth transistor configured to apply a first control voltage to the source of the first transistor in response to the scan signal; and a first capacitor connected between the gate and the source of the first transistor, and the second driving circuit includes: the second transistor configured to apply a second control voltage to the gate of the first transistor according to a voltage applied to the gate of the second transistor; a third transistor configured to apply the gray-scale voltage to the gate of the second transistor in response to the scan signal; and a second capacitor, one end of which receives a clearing voltage that monotonically changes during a preset period and the other end of which is connected to the gate of the second transistor.

2. The display panel according to claim 1, wherein, the change in the magnitude of the driving current, which is caused by the change of the first transistors respectively included in the plurality of sub-pixels, is compensated by the bias voltage applied to the first driving circuit, and the change in the pulse width of the driving current, which is caused by the change of the second transistors respectively included in the plurality of sub-pixels, is compensated by the gray-scale voltage applied to the second driving circuit.

3. The display panel according to claim 1, wherein, the first transistor is configured to provide the light-emitting element with the driving current having a magnitude determined according to the magnitude of the voltage applied between the gate and the source of the first transistor, The first driving circuit is configured to apply a voltage for keeping the magnitude of the driving current constant based on the bias voltage between the gate and the source of the first transistor, and the second driving circuit is configured to receive a reset voltage that monotonically changes during a preset period, and control the emission duration of the light-emitting element based on the gray-scale voltage and the reset voltage.

4. The display panel according to claim 1, wherein, the display panel is configured to display an image in each frame time period, wherein the frame time period includes: a data writing period, during which the pixel circuit stores the bias voltage in the first capacitor and stores the gray-scale voltage in the second capacitor in response to the scan signal; and an emission period, during which the light-emitting element emits light for an emission duration corresponding to the pulse width.

5. The display panel according to claim 4, the display panel further comprises: a voltage generation unit configured to supply the first driving voltage having a low level to the first power line during the data writing period and supply the first driving voltage having a high level to the first power line during the emission period; and a gate reset driving unit configured to output the scan signal and supply the reset voltage that linearly increases during the emission period to the second capacitor, wherein the data sensing driving unit is configured to supply the second control voltage having a high level to the second transistor during the data writing period and supply the second control voltage having a low level to the second transistor during the emission period.

6. The display panel according to claim 1, wherein, the data sensing driving unit includes a sensing circuit configured to: generate first sensing data by sensing the magnitude of the current output from the first transistor when a reference bias voltage and a reference source voltage are applied to the first driving circuit, and generate second sensing data by sensing the magnitude of the current output from the second transistor when a reference gray-scale voltage and the reference source voltage are applied to the second driving circuit.

7. The display panel according to claim 6, wherein, the timing control unit is configured to generate the first characteristic information and the second characteristic information based on the first sensing data and the second sensing data respectively, and includes a memory for storing the first characteristic information and the second characteristic information.

8. The display panel according to claim 6, wherein, the sensing circuit includes: a switching circuit configured to selectively apply the reference source voltage to one of the first driving circuit and the second driving circuit; an integrated circuit configured to integrate the received current; and an analog-to-digital conversion circuit configured to generate the first sensing data and the second sensing data.

9. The display panel according to claim 8, wherein, The switching circuit includes a first switch between the integrated circuit and the fifth transistor and a second switch between the integrated circuit and the second transistor, and the integrated circuit includes an operational amplifier and a third capacitor. The operational amplifier includes a first input terminal, a second input terminal, and an output terminal. The first switch and the second switch are connected to the first input terminal. The reference source voltage is applied to the second input terminal. The output terminal is connected to the analog-to-digital conversion circuit. And the third capacitor is connected between the first input terminal and the output terminal of the operational amplifier. wherein, the data sensing and driving unit is configured to: apply the reference bias voltage to the gate of the first transistor via the fourth transistor, and apply the reference source voltage to the source of the first transistor. Wherein, the first sensed data is generated by receiving the current output from the first transistor via the fifth transistor. apply the reference gray scale voltage to the gate of the second transistor via the third transistor, and apply the reference source voltage to the source of the second transistor. Wherein, the second sensed data is generated by receiving the current output from the second transistor.

10. A pixel, the pixel includes a pixel circuit connected to a light emitting element, the pixel circuit comprises: a first transistor connected between a first power line and the light emitting element, and the first power line is applied with a first driving voltage; a fourth transistor including a gate, a first connection end, and a second connection end. The gate is connected to a scan line for transmitting a scan signal. The first connection end is connected to a first data line applied with a bias voltage. And the second connection end is connected to the gate of the first transistor; a fifth transistor including a gate, a first connection end, and a second connection end. The gate is connected to the scan line. The first connection end is connected to a first sensing line applied with a first control voltage. And the second connection end is connected to the source of the first transistor; a first capacitor connected between the gate and the source of the first transistor; a second transistor including a gate, a drain, and a source. The drain is connected to the gate of the first transistor. And the source is connected to a second sensing line applied with a second control voltage; a third transistor including a gate, a first connection end, and a second connection end. The gate is connected to the scan line. The first connection end is connected to a second data line applied with a gray scale voltage. And the second connection end is connected to the gate of the second transistor; and a second capacitor including a first electrode and a second electrode. The first electrode is connected to a voltage line applied with a clearing voltage that monotonically changes during a preset period. And the second electrode is connected to the gate of the second transistor.

11. The pixel according to claim 10, the pixel is included in a display panel, wherein, The display panel is configured to display an image per frame time period, the frame time period including a data writing period and an emission period, and the display panel further includes: A gate clear driving unit configured to output the scan signal to the scan line during the data writing period and output the clear voltage linearly increasing during the emission period to the voltage line; A data sensing driving unit configured to output the second control voltage with a high level to the second sensing line during the data writing period, output the second control voltage with a low level to the second sensing line during the emission period, and output the bias voltage and the gray scale voltage to the first data line and the second data line respectively in synchronization with the scan signal; and A voltage generating unit configured to output the first driving voltage with a low level to the first power line during the data writing period and output the first driving voltage with a high level to the first power line during the emission period.

12. The pixel according to claim 11, wherein the display panel further includes a timing control unit configured to: receive image data, generate bias data based on first characteristic information of the first transistor to provide the bias data to the data sensing driving unit, generate corrected data by correcting the image data based on second characteristic information of the second transistor, and provide the corrected data to the data sensing driving unit, wherein, The data sensing driving unit is configured to receive the bias data and the corrected data, generate the bias voltage corresponding to the bias data, and generate the gray scale voltage corresponding to the corrected data.

13. The pixel according to claim 11, the display panel further includes: A first switch connected to the first sensing line; A second switch connected to the second sensing line; An operational amplifier including a first input terminal, a second input terminal, and an output terminal, the first switch and the second switch being connected to the first input terminal, and a reference source voltage being applied to the second input terminal; A third capacitor connected between the first input terminal and the output terminal of the operational amplifier; and An analog-to-digital conversion circuit connected to the output terminal of the operational amplifier.

14. The pixel according to claim 13, wherein, The gate clear driving unit is configured to output the scan signal to the scan line during a first sensing period for sensing the characteristics of the first transistor, and The data sensing driving unit is configured to turn on the first switch and turn off the second switch during the first sensing period, and output a reference bias voltage with a high level and a reference gray scale voltage with a low level to the first data line and the second data line respectively in synchronization with the scan signal.

15. The pixel according to claim 13, wherein, The gate clearing driving unit is configured to output the scan signal to the scan line during a second sensing period for sensing characteristics of the second transistor, and the data sensing driving unit is configured to turn off the first switch and turn on the second switch during the second sensing period, and output a reference bias voltage having a high level and a reference gray scale voltage having a high level to the first data line and the second data line, respectively, in synchronization with the scan signal.

16. A display device, the display device comprising: a plurality of pixels, each including a first transistor, a second transistor connected to a gate terminal of the first transistor, and an inorganic or microscale light emitting element connected to an output terminal of the first transistor; a time division controller configured to generate bias data based on first characteristic information of the first transistor and generate correction data based on second characteristic information of the second transistor; a sensing driver configured to receive the bias data and the correction data and provide a bias voltage corresponding to the bias data and a correction voltage corresponding to the correction data to at least one of the plurality of pixels; a first driving circuit connected to the output terminal of the first transistor and configured to control a magnitude of a driving current supplied to the light emitting element based on the bias voltage; and a second driving circuit including the second transistor and configured to control a pulse width of the driving current based on the correction voltage, wherein the second driving circuit includes a third transistor and a correction capacitor both connected to the gate terminal of the second transistor, wherein the correction voltage is responsive to the correction capacitor, and wherein the first driving circuit includes a fourth transistor connected to the gate terminal of the first transistor, a fifth transistor connected to the output terminal of the first transistor, and a bias capacitor connected between the gate terminal and the output terminal of the first transistor, wherein the bias voltage is responsive to the bias capacitor.

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