Display device

Abstract

A display device is provided, comprising: a scan line extending in one direction, a data line and a driving voltage line extending in another direction, a transistor electrically connected to the driving voltage line and including a first gate electrode and a first semiconductor layer, a second transistor electrically connected to the scan line and the data line and including a second gate electrode and a second semiconductor layer, a first capacitor electrically connected to the first transistor and including a first capacitor plate and a second capacitor plate, and a second capacitor including a third capacitor plate electrically connected to the first transistor and a fourth capacitor plate electrically connected to the second transistor. The second capacitor plate includes a first hole overlapping the first capacitor plate, and the fourth capacitor plate includes a second hole overlapping the third capacitor plate, wherein the second hole has a size different from the first hole.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2020-0046263, filed on April 16, 2020, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] One or more embodiments relate to a display device. Background Art

[0004] Generally, a display device may include a display element and an electronic element for controlling an electrical signal applied to the display element. The electronic element may include a transistor and a capacitor.

[0005] It will be understood that this background technology section is intended, in part, to provide a useful context for understanding the technology. However, this background technology section may also include ideas, concepts, or realizations that were not already known or understood by those skilled in the relevant art before the corresponding effective filing date of the subject matter disclosed herein. Summary of the Invention

[0006] With the development of various electronic devices having display devices, there is a demand for the development of pixel circuits suitable for high-speed driving and / or capable of providing high-quality images.

[0007] One or more embodiments may include a display device including a pixel circuit suitable for high-speed driving (e.g., high-speed driving of approximately 120 Hz or higher). Additionally or alternatively, one or more embodiments may include a display device that can display high-quality images by preventing or minimizing the generation of spots caused by brightness changes during high-speed driving.

[0008] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for purposes of limiting the embodiments presented.

[0009] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the presented embodiments.

[0010] According to one or more embodiments, a display device may include: a scan line extending in a first direction; a data line and a driving voltage line each extending in a second direction; a first transistor electrically connected to the driving voltage line and including a first gate electrode and a first semiconductor layer; a second transistor electrically connected to the data line and the scan line and including a second gate electrode and a second semiconductor layer; a first capacitor electrically connected to the first transistor and including a first capacitor plate and a second capacitor plate; and a second capacitor including a third capacitor plate electrically connected to the first transistor and a fourth capacitor plate electrically connected to the second transistor, wherein the second capacitor plate may include a first hole overlapping with the first capacitor plate, the fourth capacitor plate may include a second hole overlapping with the third capacitor plate, and a size of the second hole may be different from a size of the first hole.

[0011] The second aperture of the fourth capacitor plate may have a size greater than the first aperture of the second capacitor plate.

[0012] The third capacitor plate may include an isolation pattern.

[0013] The display device may further include a first connection line electrically connecting the third capacitor plate and the first transistor, wherein the first connection line may be electrically connected to the third capacitor plate through the second hole of the fourth capacitor plate.

[0014] The third capacitor plate may be electrically connected to one of the source and drain regions of the first semiconductor layer of the first transistor, and the fourth capacitor plate may be electrically connected to one of the source and drain regions of the second semiconductor layer of the second transistor.

[0015] The fourth capacitor plate may include an isolation pattern.

[0016] The display device may further include a second connection line electrically connecting the fourth capacitor plate and the second transistor.

[0017] The first capacitor plate may include an isolation pattern.

[0018] The display device may further include: a third transistor electrically connected to the first transistor; and a third connection line electrically connecting the first capacitor and the third transistor.

[0019] The third connection line may be electrically connected to the first capacitor plate through the first hole of the second capacitor plate.

[0020] The first capacitor plate may include a first gate electrode of the first transistor.

[0021] The display device may further include a fourth transistor electrically connected to the second capacitor and the second transistor; and a reference voltage line extending in the second direction and electrically connected to the fourth transistor.

[0022] According to one or more embodiments, a display device may include: a scan line extending in a first direction; a data line and a driving voltage line each extending in a second direction; a first transistor electrically connected to the driving voltage line and including a first gate electrode and a first semiconductor layer; a first capacitor electrically connected to the first transistor and including a first capacitor plate and a second capacitor plate; a second transistor electrically connected to the data line and the scan line and including a second gate electrode and a second semiconductor layer; and a second capacitor electrically connected to the first transistor and the second transistor and including a third capacitor plate and a fourth capacitor plate, wherein the first capacitor and the second capacitor may be spaced apart from each other, the second capacitor plate may include a first hole overlapping with the first capacitor plate, the fourth capacitor plate may include a second hole overlapping with the third capacitor plate, and a size of the second hole may be different from a size of the first hole.

[0023] The second aperture of the fourth capacitor plate may have a size greater than the first aperture of the second capacitor plate.

[0024] The third capacitor plate may be electrically connected to one of the source and drain regions of the first semiconductor layer of the first transistor, and the fourth capacitor plate may be electrically connected to one of the source and drain regions of the second semiconductor layer of the second transistor.

[0025] The display device may further include a first connection line electrically connecting the second capacitor and the first transistor, wherein the first connection line may be electrically connected to the third capacitor plate through the second hole of the fourth capacitor plate.

[0026] The third capacitor plate may include an isolation pattern.

[0027] The display device may further include a second connection line electrically connecting the fourth capacitor plate of the second capacitor and the second transistor.

[0028] The display device may further include a third transistor electrically connected to the first transistor; and a third connection line electrically connecting the first capacitor and the third transistor, wherein the third connection line may be electrically connected to the first capacitor plate through the first hole of the second capacitor plate.

[0029] The first capacitor plate may include an isolation pattern.

[0030] The first capacitor plate may include a first gate electrode of the first transistor.

[0031] The display device may further include a fourth transistor electrically connected to the second capacitor and the second transistor; and a reference voltage line extending in the second direction and electrically connected to the fourth transistor.

[0032] These and / or other aspects will become apparent and more readily appreciated from the following description of the embodiments, the drawings, and the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The above and other aspects, features and advantages of the embodiments will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0034] Figure 1 is a schematic plan view of a display device according to an embodiment;

[0035] Figure 2 is an equivalent circuit diagram of a pixel circuit electrically connected to a display element of a display device according to an embodiment;

[0036] Figure 3 is a timing diagram of example signals applied to a pixel circuit of a display device according to an embodiment;

[0037] Figure 4 yes Figure 2 A schematic plan view of the positions of transistors and capacitors of a pixel circuit;

[0038] Figures 5 to 8 is based on Figure 4 A plan view of a stacked structure of a pixel circuit manufacturing process;

[0039] Figure 9 is a schematic cross-sectional view of a display device according to an embodiment;

[0040] Figure 10 is a schematic cross-sectional view of a display device according to an embodiment; and

[0041] Figure 11 is a graph showing the difference in data transmission between the first hole and the second hole. DETAILED DESCRIPTION

[0042] Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. In this regard, the embodiments may have different forms and should not be construed as limited to the description set forth herein. Accordingly, the embodiments are described below solely with reference to the drawings to illustrate various aspects of the description.

[0043] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Throughout the disclosure, the expression "at least one of a, b, and c" refers to only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0044] The terms "and" and "or" may be used in conjunction or disjunction and may be understood to be equivalent to "and / or." In the specification and claims, for purposes of its meaning and interpretation, the phrase "at least one" is intended to include the meaning of "at least one selected from the group of..." For example, "at least one of A and B" may be understood to mean "A, B, or A and B."

[0045] Because various modifications can be applied and one or more embodiments can be implemented, the embodiments will be shown in the drawings and described in detail in the detailed description. The effects and features of the present disclosure and methods for achieving the effects and features of the present disclosure will be apparent with reference to the embodiments described in detail below in conjunction with the drawings. However, the present disclosure is not limited to the embodiments disclosed below and can be implemented in various forms.

[0046] Hereinafter, embodiments are described in detail with reference to the accompanying drawings. When describing with reference to the accompanying drawings, like reference numerals are used for like or corresponding elements, and repeated description thereof is omitted.

[0047] It will be understood that although the terms "first," "second," etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are only used to distinguish one component from another. For example, a first element referred to as a first element in one embodiment may be referred to as a second element in another embodiment without departing from the scope of the appended claims.

[0048] As used herein, the singular forms "a," "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0049] It will also be understood that the terms “comprises” and / or “comprising”, “includes” and / or “including”, “have” and / or “having” are used in this specification and they or it may specify the presence of stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of other features, integers, steps, operations, elements, components and / or any combination thereof.

[0050] It will be understood that when a layer, region, or element is referred to as being "formed on" another layer, region, or element, it can be formed directly or indirectly on the other layer, region, or element. That is, for example, there may be an intermediate layer, region, or element. For ease of explanation, the dimensions of the elements in the accompanying drawings may be exaggerated or reduced. In other words, since the dimensions and thicknesses of the elements in the accompanying drawings are arbitrarily shown for ease of explanation, the following embodiments are not limited thereto. In addition, when a layer, film, region, substrate, area, or element is referred to as being "below" another layer, film, region, substrate, area, or element, it can be directly below the other layer, film, region, substrate, area, or element, or there may be an intermediate layer, film, region, substrate, area, or element therebetween. Conversely, when a layer, film, region, substrate, area, or element is referred to as being "directly" "below" another layer, film, region, substrate, area, or element, there may be no intermediate layer, film, region, substrate, area, or element therebetween. In addition, "on" or "on" can include positioning on or below an object and does not necessarily imply a direction based on gravity.

[0051] For ease of description, the spatially relative terms "below," "under," "down," "above," "upper," or similar terms may be used herein to describe the relationship between one element or component and another element or component as shown in the accompanying drawings. It will be understood that the spatially relative terms are intended to cover different orientations of the device in use or operation in addition to the orientations depicted in the accompanying drawings. For example, where the device shown in the accompanying drawings is flipped, a device positioned "below" or "beneath" another device may be placed "above" the other device. Accordingly, the illustrative term "below" may include both a lower position and an upper position. The device may also be oriented in other directions, and therefore the spatially relative terms may be interpreted differently depending on the orientation.

[0052] In addition, the terms "overlap" or "overlapped" mean that a first object can be above or below a second object or to the side of the second object, and vice versa. In addition, the term "overlap" can include layered, stacked, facing or facing, extending over, covering or partially covering, or any other suitable term as will be appreciated and understood by those of ordinary skill in the art. The terms "face" and "facing" mean that a first element can be directly or indirectly opposite to a second element. In the case where a third element is between the first and second elements, the first and second elements can be understood to be indirectly opposite to each other, although still facing each other. When an element is described as "not overlapping" or "not overlapping" with another element, this can include the elements being spaced apart, offset from each other, or separated from each other, or any other suitable term as will be appreciated and understood by those of ordinary skill in the art.

[0053] In the following embodiments, when a component is referred to as "on a plane", it is understood that the component is viewed from the top, and when a component is referred to as "on a schematic cross-section", it is understood that the component is cut vertically and viewed from the side.

[0054] It will be understood that when a layer, region, or element is referred to as being “connected” to another layer, region, or element, it may be “directly connected” to the other layer, region, or element and / or may be “indirectly connected” to the other layer, region, or element with other layers, regions, or elements interposed therebetween. For example, it will be understood that when a layer, region, or element is referred to as being “electrically connected” to another layer, region, or element, it may be “directly electrically connected” to the other layer, region, or element and / or may be “indirectly electrically connected” to the other layer, region, or element with other layers, regions, or elements interposed therebetween.

[0055] Also, when an element is referred to as being “in contact” or “contacted” or in a similar situation with another element, the element may be “electrically in contact” or “physically in contact” with the other element; or “indirectly in contact” or “directly in contact” with the other element.

[0056] As used herein, "about" or "approximately" includes the stated value and mean within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, 20%, 10%, 5% of the stated value.

[0057] In the following embodiments, the x-axis, y-axis, and z-axis are not limited to the three axes of the rectangular coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0058] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the embodiments belong. In addition, it will be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0059] Figure 1 is a schematic plan view of a display device 1 according to the embodiment.

[0060] Reference Figure 1 The display device 1 may include a display area DA and a non-display area NDA surrounding the display area DA. The display area DA may provide an image using light emitted from pixels P. Each of the pixels P may include a display element that may emit light (e.g., red, green, and blue light).

[0061] The non-display area NDA, which may be an area where pixels P may not be arranged or disposed, may be adjacent to the display area DA and may completely surround the display area DA. In an embodiment, the display area DA may have a substantially rectangular shape having substantially longer sides in the ±y directions. Alternatively, the display area DA may have a substantially rectangular shape having substantially longer sides in the ±x directions, a substantially polygonal shape such as a square or the like, a substantially elliptical shape, or a substantially circular shape.

[0062] Figure 2 is an equivalent circuit diagram of a pixel circuit PC electrically connected to a display element of a display device according to an embodiment.

[0063] Reference Figure 2 , a display element, for example, a light emitting diode LED, may be electrically connected to a pixel circuit PC, and the pixel circuit PC may include a transistor and a capacitor.

[0064] The pixel circuit PC may include a first transistor T1 , a second transistor T2 , a third transistor T3 , a fourth transistor T4 , a fifth transistor T5 , a sixth transistor T6 , a seventh transistor T7 , and an eighth transistor T8 , a first capacitor Cst, and a second capacitor Cpr.

[0065] The first transistor T1 may be a driving transistor. The gate electrode of the first transistor T1 (hereinafter referred to as the first gate electrode) may be electrically connected to the first capacitor plate of the first capacitor Cst, the first electrode of the first transistor T1 may be electrically connected to a driving voltage line VDL that may supply a driving power supply voltage ELVDD via the fifth transistor T5, and the second electrode of the first transistor T1 may be electrically connected to a pixel electrode (e.g., an anode) of the light-emitting diode LED via the sixth transistor T6. The opposite electrode (e.g., a cathode) of the light-emitting diode LED may be electrically connected to a power line configured to supply a common power supply voltage ELVSS. One of the first electrode and the second electrode of the first transistor T1 may be a source electrode of the first transistor T1, and the other may be a drain electrode of the first transistor T1. The first transistor T1 may generate a driving current having an amplitude determined based on the voltage between the first gate electrode and the first electrode and the threshold voltage of the first transistor T1.

[0066] The first capacitor Cst may include a first capacitor plate electrically connected to the first gate electrode of the first transistor T1 and a second capacitor plate electrically connected to the driving voltage line VDL. The first capacitor Cst may store a voltage that may determine the magnitude of the driving current generated by the first transistor T1.

[0067] The second transistor T2 may be a switching transistor. A gate electrode of the second transistor T2 (hereinafter, referred to as a second gate electrode) may be electrically connected to the scan line SL, a first electrode of the second transistor T2 may be electrically connected to the data line DL, and a second electrode of the second transistor T2 may be electrically connected to the first node N1. One of the first electrode and the second electrode of the second transistor T2 may be a source electrode of the second transistor T2, and the other may be a drain electrode of the second transistor T2. The second transistor T2 may transmit a data voltage Vdata to the first node N1 in response to the scan signal GW.

[0068] A gate electrode of the third transistor T3 (hereinafter referred to as the third gate electrode) can be electrically connected to the first control line GCL. A first electrode of the third transistor T3 can be electrically connected to the first gate electrode of the first transistor T1 and / or the first capacitor plate of the first capacitor Cst, and a second electrode of the third transistor T3 can be electrically connected to the second node N2. One of the first electrode and the second electrode of the third transistor T3 can be a source electrode of the third transistor T3, and the other can be a drain electrode of the third transistor T3. The third transistor T3 can be turned on in response to the first control signal GC and can cause the first transistor T1 to be diode-connected by electrically connecting the first gate electrode G1 to the second electrode of the first transistor T1.

[0069] A gate electrode of the fourth transistor T4 (hereinafter referred to as the fourth gate electrode) can be electrically connected to the second control line EBL1. A first electrode of the fourth transistor T4 can be electrically connected to the reference voltage line VRL, and a second electrode of the fourth transistor T4 can be electrically connected to the first node N1. One of the first electrode and the second electrode of the fourth transistor T4 can be a source electrode of the fourth transistor T4, and the other can be a drain electrode of the fourth transistor T4. The fourth transistor T4 can apply the reference voltage Vref to the first node N1 in response to the second control signal EB1.

[0070] The second capacitor Cpr may include a first capacitor plate electrically connected to the first node N1 and a second capacitor plate electrically connected to the second node N2. The second capacitor Cpr may store a voltage corresponding to the threshold voltage of the first transistor T1 during the compensation period and transfer a voltage corresponding to the data voltage to the first capacitor Cst using a charge sharing method during the data write period.

[0071] A gate electrode of the fifth transistor T5 (hereinafter referred to as the fifth gate electrode) can be electrically connected to the third control line EML1. A first electrode of the fifth transistor T5 can be electrically connected to the drive voltage line VDL, and a second electrode of the fifth transistor T5 can be electrically connected to the first electrode of the first transistor T1. One of the first electrode and the second electrode of the fifth transistor T5 can be a source electrode of the fifth transistor T5, and the other can be a drain electrode of the fifth transistor T5. The fifth transistor T5 can electrically connect the drive voltage line VDL and the first electrode of the first transistor T1 to each other in response to the third control signal EM1.

[0072] A gate electrode of the sixth transistor T6 (hereinafter referred to as the sixth gate electrode) can be electrically connected to the fourth control line EML2. A first electrode of the sixth transistor T6 can be electrically connected to the second node N2, and a second electrode of the sixth transistor T6 can be electrically connected to the light-emitting diode LED. One of the first electrode and the second electrode of the sixth transistor T6 can be a source electrode of the sixth transistor T6, and the other can be a drain electrode of the sixth transistor T6. The sixth transistor T6 can electrically connect the second electrode of the first transistor T1 and the light-emitting diode LED to each other in response to the fourth control signal EM2.

[0073] A gate electrode of the seventh transistor T7 (hereinafter referred to as the seventh gate electrode) can be electrically connected to the second control line EBL1. A first electrode of the seventh transistor T7 can be electrically connected to the initialization voltage line VIL, and a second electrode of the seventh transistor T7 can be electrically connected to the light-emitting diode LED, for example, a pixel electrode (e.g., an anode) of the light-emitting diode LED. One of the first electrode and the second electrode of the seventh transistor T7 can be a source electrode of the seventh transistor T7, and the other can be a drain electrode of the seventh transistor T7. The seventh transistor T7 can apply the initialization voltage Vint to the light-emitting diode LED in response to the second control signal EB1.

[0074] A gate electrode of the eighth transistor T8 (hereinafter, referred to as the eighth gate electrode) may be electrically connected to the fifth control line EBL2. A first electrode of the eighth transistor T8 may be electrically connected to the fourth control line EML2, and a second electrode of the eighth transistor T8 may be electrically connected to the second node N2. The eighth transistor T8 may apply the fourth control signal EM2 to the second node N2 in response to the fifth control signal EB2 by electrically connecting the fourth control line EML2 to the second node N2.

[0075] Figure 3 is a timing diagram of example signals applied to a pixel circuit of a display device according to an embodiment.

[0076] Reference Figure 3 , each frame of the display device according to the embodiment may include a compensation period in which the threshold voltage can be compensated and a data writing period in which the data signal can be written, and the compensation period and the above-mentioned data writing period may each exist separately. In the case where the compensation period and the data writing period are the same, for example, when the data voltage is written to the pixel while compensating for the threshold voltage of the driving transistor (comparative example), a large amount of time may be required to fully compensate for the threshold voltage. On the other hand, in an embodiment, since there is a data writing period for writing the data voltage to each pixel after the compensation period for synchronously compensating the threshold voltage of the driving transistor of all pixels, sufficient time for compensation can be ensured, and the data writing time can be set to be short. Accordingly, the display device according to the embodiment may be more advantageous for high-speed driving.

[0077] In the initialization period TP1, since the fourth control line EML2 (see Figure 2 ) can maintain a low level voltage, so the sixth transistor T6 can be turned on. Figure 2 ) and the first control signal GC supplied via the second control line EBL1 (see Figure 2) changes from a high level voltage to a low level voltage, the third transistor T3, the fourth transistor T4 and the seventh transistor T7 may be turned on.

[0078] The initialization voltage Vint can be transmitted to the fourth node N4 via the seventh transistor T7, and the pixel electrode (anode) of the light-emitting diode LED electrically connected to the fourth node N4 can be initialized with the initialization voltage Vint. The initialization voltage Vint can be transmitted to the second node N2 via the sixth transistor T6, and then transmitted to the third node N3 via the third transistor T3. The first gate electrode of the first transistor T1 can be initialized with the initialization voltage Vint, and the first capacitor Cst can be initialized with the driving power supply voltage ELVDD and the initialization voltage Vint. The reference voltage Vref can be transmitted to the first node N1 via the fourth transistor T4. The second capacitor Cpr can be initialized with the reference voltage Vref and the initialization voltage Vint.

[0079] In the compensation period TP2, when the third control signal EM1 supplied via the third control line EML1 changes from a high level voltage to a low level voltage, the fifth transistor T5 may be turned on, the fourth control signal EM2 may change from a low level voltage to a high level voltage, and the sixth transistor T6 may be turned off.

[0080] The driving power supply voltage ELVDD may be transmitted to the first transistor T1 via the fifth transistor T5, and the first capacitor Cst may store a threshold voltage (hereinafter, Vth) of the first transistor T1. In the compensation period TP2, which may be the second period, the initialization voltage Vint may be continuously applied to the first node N1 via the fourth transistor T4, and the second capacitor Cpr may store a voltage corresponding to Vref-(ELVDD-Vth).

[0081] In the data writing period TP3 (or the third period), when the scan signal GW supplied via the scan line SL changes from a high level voltage to a low level voltage, the second transistor T2 may be turned on, and the data voltage Vdata supplied via the data line DL may be transmitted to the first node N1. When the third control signal EM1 changes from a low level voltage to a high level voltage, the fifth transistor T5 may be turned off, and when the second control signal EB1 changes from a low level voltage to a high level voltage, the fourth transistor T4 and the seventh transistor T7 may be turned off.

[0082] The data voltage Vdata can be transmitted to the first node N1 via the second transistor T2 and the second capacitor Cpr, and a voltage corresponding to the data voltage Vdata can be written to the first capacitor Cst through charge sharing between the first capacitor Cst and the second capacitor Cpr. For example, a voltage corresponding to ELVDD-Vth+CCpr / (CCst+CCpr)*(Vdata-Vref) can be transmitted to the second node N2, and a voltage corresponding to the difference between the voltage of the driving power supply voltage ELVDD and the voltage of the second node N2 can be stored in the first capacitor Cst. Here, CCst is the capacitance of the first capacitor Cst, and CCpr is the capacitance of the second capacitor Cpr.

[0083] In the on-bias period TP4 (or the fourth period) of the first transistor T1, when the scan signal GW changes from a low-level voltage to a high-level voltage, the second transistor T2 may be turned off. When the first control signal GC changes from a low-level voltage to a high-level voltage, the third transistor T3 may be turned off and connected to the control line EBL2 (see FIG. Figure 2 ) changes from a high level voltage to a low level voltage, the eighth transistor T8 may be turned on so that the fourth control signal EM2 supplied via the fourth control line EML2 may be transmitted to the second node N2.

[0084] When the fourth control signal EM2 having a high level voltage is transmitted to the second node N2 (e.g., the second electrode of the first transistor T1) via the eighth transistor T8, the voltage of the first gate electrode of the first transistor T1 can become relatively low, and the first transistor T1 can be fully turned on. In other words, before generating the drive current in the emission period TP6, the first transistor T1 can be forced to be turned on in the on-bias period TP4 of the first transistor T1, so that the hysteresis characteristic of the first transistor T1 in which the amplitude of the drive current output from the first transistor T1 to the previous frame affects the amplitude of the drive current output to the current frame can be removed. The variation of the hysteresis of the first transistor T1 of the pixel can be compensated.

[0085] In the off-bias period TP5 (or the fifth period) of the first transistor T1 , in the case where the fourth control signal EM2 changes from a high-level voltage to a low-level voltage, the sixth transistor T6 may be turned on.

[0086] The fourth control signal EM2 having a low level voltage can be transmitted to the second node N2 and the fourth node N4 via the eighth transistor T8 and the sixth transistor T6, respectively, and the second electrode of the first transistor T1 electrically connected to the second node N2 and the pixel electrode (e.g., anode) of the light emitting diode LED can be initialized with the low level voltage before the emission period TP6.

[0087] When a low-level voltage is applied to the second electrode of the first transistor T1, the voltage of the first gate electrode of the first transistor T1 becomes relatively high, and the first transistor T1 can be completely turned off. The first transistor T1 can be completely turned on in the fourth period TP4 before the emission period TP6, and then completely turned off in the fifth period TP5, and therefore, the hysteresis variation of the first transistor T1 can be further reduced.

[0088] Immediately before the emission period TP6, a low-level voltage can be applied to the pixel electrode (e.g., anode) of the light-emitting diode LED, thereby preventing the light-emitting diode LED from emitting light weakly or minutely (e.g., emitting a relatively small amount of light) during the emission period TP6 when a data voltage corresponding to full black can be applied to the pixel.

[0089] In the emission period TP6, when the fifth control signal EB2 changes from a low level voltage to a high level voltage, the eighth transistor T8 may be turned off. When the third control signal EM1 changes from a high level voltage to a low level voltage, the fifth transistor T5 may be turned on, and a driving current may flow through the first transistor T1 to the light emitting diode LED based on the voltage stored in the first capacitor Cst, which may be a storage capacitor.

[0090] Since a voltage corresponding to Vth+CCpr / (CCst+CCpr)*(Vref-Vdata) is stored in the first capacitor Cst in the third period TP3, the first transistor T1 may output a driving current that may be unrelated to the magnitude of the threshold voltage Vth. For example, the driving current may have a value corresponding to [CCpr / (CCst+CCpr)*(Vref-Vdata] 2 Proportional amplitude.

[0091] Figure 4 yes Figure 2 Schematic plan view of the positions of transistors and capacitors of the pixel circuit. Pixel circuits of the same or similar structure can be arranged or set in the vertical and horizontal directions. For example, the pixel circuits can be arranged or set in a matrix form in the ±x direction and the ±y direction, and one of the pixel circuits arranged or set in the matrix form can have a structure such as Figure 4 The structure shown in .

[0092] Figures 5 to 8 is based on Figure 4 A plan view of the stacked structure of the pixel circuit manufacturing process. Figure 5 is a plan view of a manufacturing process that can form a semiconductor layer and a gate electrode. Figure 6 is Figure 5 A plan view of capacitor plates and horizontal power lines formed or arranged on a layered structure. Figure 7 Is the connecting line and Figure 6 A plan view of lines extending in a first direction (eg, x-direction) formed or arranged on a layered structure. Figure 8 is Figure 7 A plan view of lines extending in a second direction (e.g., y-direction) formed or arranged on a layered structure.

[0093] At least one insulating layer may be provided according to Figures 5 to 8 For example, the gate insulating layer can be arranged between the layered structures of the stacked structure. Figure 5 The process of forming the first interlayer insulating layer may further include forming a first interlayer insulating layer between the first semiconductor layer A1, the second semiconductor layer A2, the third semiconductor layer A3, the fourth semiconductor layer A4, the fifth semiconductor layer A5, the sixth semiconductor layer A6, the seventh semiconductor layer A7 and the eighth semiconductor layer A8 and the first gate electrode G1, the second gate electrode G2, the third gate electrode G3, the fourth gate electrode G4, the fifth gate electrode G5, the sixth gate electrode G6, the seventh gate electrode G7 and the eighth gate electrode G8. Figure 5 Manufacturing process and Figure 6 The process of forming the second interlayer insulating layer may also include Figure 6 Manufacturing process and Figure 7 The process of forming the first planarization insulating layer may further include: Figure 7 Manufacturing process and Figure 8 The contact holes may be formed or provided in the above-mentioned insulating layers (eg, the gate insulating layer, the first interlayer insulating layer, the second interlayer insulating layer, and the planarizing insulating layer), respectively. Figures 5 to 8 The layered structures can be electrically connected to each other through corresponding contact holes.

[0094] Reference Figure 4 The pixel circuit may include a scanning signal GW (see Figure 3 ) of the scan line SL, can provide a first control signal GC (see Figure 3 ) of the first control line GCL, can provide a second control signal EB1 (see Figure 3 ) of the second control line EBL1, can provide a third control signal EM1 (see Figure 3) of the third control line EML1, can provide a fourth control signal EM2 (see Figure 3 ) of the fourth control line EML2, can provide a fifth control signal EB2 (see Figure 3 ) and can provide the initialization voltage Vint (see Figure 3 ) initialization voltage line VIL.

[0095] The scan line SL, the first control line GCL, the second control line EBL1, the third control line EML1, the fourth control line EML2, the fifth control line EBL2, and the initialization voltage line VIL may extend in a first direction (e.g., an x-direction). In an embodiment, the scan line SL, the second control line EBL1, the initialization voltage line VIL, the third control line EML1, the first control line GCL, the fifth control line EBL2, and the fourth control line EML2 may be sequentially arranged or disposed in a second direction (e.g., a y-direction).

[0096] The pixel circuit may include a data voltage Vdata (see FIG. Figure 3 ) of the data line DL, can provide a driving power supply voltage ELVDD (see Figure 3 ) of the driving voltage line VDL and can provide a reference voltage Vref (see Figure 3 ) reference voltage line VRL.

[0097] The data lines DL, driving voltage lines VDL, and reference voltage lines VRL may extend in the second direction (eg, y direction). In an embodiment, the data lines DL, driving voltage lines VDL, and reference voltage lines VRL may be sequentially arranged or disposed in the first direction (eg, x direction).

[0098] The first to eighth transistors T1 to T8 may be formed or disposed along at least one semiconductor layer, and the at least one semiconductor layer may be bent in various shapes. The at least one semiconductor layer may include a first semiconductor layer A1 corresponding to the first transistor T1, a second semiconductor layer A2 corresponding to the second transistor T2, a third semiconductor layer A3 corresponding to the third transistor T3, a fourth semiconductor layer A4 corresponding to the fourth transistor T4, a fifth semiconductor layer A5 corresponding to the fifth transistor T5, a sixth semiconductor layer A6 corresponding to the sixth transistor T6, a seventh semiconductor layer A7 corresponding to the seventh transistor T7, and an eighth semiconductor layer A8 corresponding to the eighth transistor T8.

[0099] Reference Figure 4 and Figure 5The first semiconductor layer A1 may include a first channel region overlapping with the first gate electrode G1, and first and second high-concentration impurity regions B1 and C1 on both sides of the first channel region. The second semiconductor layer A2 may include a second channel region overlapping with the second gate electrode G2, and first and second high-concentration impurity regions B2 and C2 on both sides of the second channel region. The third semiconductor layer A3 may include a third channel region overlapping with the third gate electrode G3, and first and second high-concentration impurity regions B3 and C3 on both sides of the third channel region. The fourth semiconductor layer A4 may include a fourth channel region overlapping with the fourth gate electrode G4, and first and second high-concentration impurity regions B4 and C4 on both sides of the fourth channel region. The fifth semiconductor layer A5 may include a fifth channel region overlapping with the fifth gate electrode G5, and first and second high-concentration impurity regions B5 and C5 on both sides of the fifth channel region. The sixth semiconductor layer A6 may include a sixth channel region overlapping with the sixth gate electrode G6, and first and second high-concentration impurity regions B6 and C6 on both sides of the sixth channel region. The seventh semiconductor layer A7 may include a seventh channel region overlapping with the seventh gate electrode G7, and first and second high-concentration impurity regions B7 and C7 on both sides of the seventh channel region. The eighth semiconductor layer A8 may include an eighth channel region overlapping with the eighth gate electrode G8, and first and second high-concentration impurity regions B8 and C8 on both sides of the eighth channel region.

[0100] Some or a predetermined number of the first to eighth semiconductor layers A1 to A8 may be connected to each other. Figure 5 As shown in the figure, the second semiconductor layer A2 and the fourth semiconductor layer A4 can be connected to each other and formed into one body, and the first semiconductor layer A1, the third semiconductor layer A3, the fifth semiconductor layer A5, the sixth semiconductor layer A6, the seventh semiconductor layer A7 and the eighth semiconductor layer A8 can be connected to each other and formed into one body.

[0101] Each of the first to eighth semiconductor layers A1 to A8 may include polycrystalline silicon. As described above, the first to eighth semiconductor layers A1 to A8 may include respective channel regions and corresponding high-concentration impurity regions doped with impurities on both sides of the respective channel regions. The first and second high-concentration impurity regions may include a higher impurity concentration than the channel region, and one of the first and second high-concentration impurity regions may be a source region, and the other may be a drain region. The source and drain regions may be source and drain electrodes, respectively. For example, the first and second high-concentration impurity regions B1 and C1 of the first transistor T1 may be a source region (or source electrode) and a drain region (or drain electrode), respectively. Similarly, one of the first and second high-concentration impurity regions of the second to eighth transistors T2 to T8 may be a source region (or source electrode), and the other may be a drain region (or drain electrode). The impurities may vary depending on the type of transistor and may include N-type impurities or P-type impurities.

[0102] exist Figure 5 Multiple portions or regions between adjacent semiconductor layers among the first to eighth semiconductor layers A1 to A8 shown in FIG may also be doped with impurities so as to serve as conductive lines for electrically connecting transistors.

[0103] The first capacitor Cst may overlap with the first transistor T1. Figure 4 and Figure 5 As shown in , the first capacitor Cst may include a first capacitor plate CSE1 having an isolation pattern (or an island pattern), and the first capacitor plate CSE1 may overlap with the first channel region of the first transistor T1. For example, the first capacitor plate CSE1 may include a first gate electrode G1. Alternatively, the first gate electrode G1 of the first transistor T1 may include the first capacitor plate CSE1.

[0104] like Figure 4 and Figure 6 As shown in FIG, the first capacitor Cst may include a second capacitor plate CSE2 that overlaps with the first capacitor plate CSE1. The second capacitor plate CSE2 may overlap with the first capacitor plate CSE1 and may include a first hole CH1. The first hole CH1 of the second capacitor plate CSE2 may overlap with the first capacitor plate CSE1. The second capacitor plate CSE2 may be part of a horizontal power line HDL extending in a first direction (e.g., an x-direction). For example, the horizontal power line HDL may include the second capacitor plate CSE2 of the first capacitor Cst.

[0105] exist Figure 4In a plan view, the second capacitor Cpr can be separated from the first capacitor Cst. The second capacitor Cpr and the first capacitor Cst can be arranged or disposed along a second direction (e.g., the y-direction). For example, the second capacitor Cpr can be separated from the first capacitor Cst, with the third control line EML1 and / or the fifth transistor T5 disposed therebetween. The first capacitor Cst can be disposed between the third control line EML1 and the first control line GCL, and the second capacitor Cpr can be disposed between the third control line EML1 and the second control line EBL1.

[0106] The second capacitor Cpr may include a third capacitor plate CPE1 and a fourth capacitor plate CPE2, the third capacitor plate CPE1 having a Figure 4 and Figure 5 The fourth capacitor plate CPE2 has an isolation pattern (or island pattern) as shown in FIG. Figure 4 and Figure 6 The fourth capacitor plate CPE2 may overlap the third capacitor plate CPE1 and may include a second hole CH2. The second hole CH2 may overlap the third capacitor plate CPE1. The size (or width) of the second hole CH2 may be different from the size (or width) of the first hole CH1. For example, the size (or width) of the second hole CH2 may be larger than the size (or width) of the first hole CH1.

[0107] Figure 5 The first to eighth gate electrodes G1 to G8, the first capacitor plate CSE1, and the third capacitor plate CPE1 shown in the figure may include the same or similar materials. The first to eighth gate electrodes G1 to G8, the first capacitor plate CSE1, and the third capacitor plate CPE1 may include low-resistance conductive materials such as aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu), and may include a single layer or multilayer structure including the above materials. In an embodiment, the third gate electrode G3 may be as follows: Figure 5 , but in an embodiment, the third gate electrode G3 may be a single gate electrode.

[0108] Figure 6 The second capacitor plate CSE2, the fourth capacitor plate CPE2, and the horizontal power line HDL shown in FIG may include the same or similar materials. The second capacitor plate CSE2, the fourth capacitor plate CPE2, and the horizontal power line HDL may include metals such as Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Ca, Mo, Ti, W, and Cu, and may include a single layer or a multilayer structure including the above materials.

[0109] The horizontal power supply line HDL may extend in a first direction (e.g., ±x direction). For example, the horizontal power supply lines HDL of the pixel circuits arranged or disposed in the first direction may be electrically connected to each other as one line. Each horizontal power supply line HDL may include a third hole CH3. The third hole CH3 may be used for the sixth transistor T6 and the fourth connection line CL4 (see FIG. 1 ) to be described later. Figure 7 ) between the holes for electrical connection.

[0110] Reference Figure 7 The scan line SL, the second control line EBL1, the third control line EML1, the first control line GCL, the fifth control line EBL2 and the fourth control line EML2 may be formed or arranged in Figure 6 The scan line SL, the second control line EBL1, the third control line EML1, the first control line GCL, the fifth control line EBL2, and the fourth control line EML2 may be electrically connected to the electrodes or the semiconductor layer, respectively.

[0111] The scan line SL may be electrically connected to the second gate electrode G2 through the first contact hole CT1. The second control line EBL1 may be electrically connected to the fourth gate electrode G4 through the second contact hole CT2 and may be electrically connected to the seventh gate electrode G7 through the third contact hole CT3. The initialization voltage line VIL may be electrically connected to the first high-concentration impurity region B7 of the seventh transistor T7 through the fourth contact hole CT4 (see FIG. Figure 4 ). The third control line EML1 can be electrically connected to the fifth gate electrode G5 through the fifth contact hole CT5, and the first control line GCL can be electrically connected to the third gate electrode G3 through the sixth contact hole CT6. The fifth control line EBL2 can be electrically connected to the eighth gate electrode G8 through the seventh contact hole CT7. The fourth control line EML2 can be electrically connected to the sixth gate electrode G6 through the eighth contact hole CT8, and can be electrically connected to the first high-concentration impurity region B8 of the eighth transistor T8 through the ninth contact hole CT9 (see Figure 4 ).

[0112] like Figure 7 As shown in FIG, first to second to third to fourth to fifth to sixth and seventh connection lines CL1, CL2, CL3, CL4, CL5, CL6, and CL7 may be formed together with the scan line SL or the like.

[0113] The first connection line CL1 can connect the first gate electrode G1 (see Figure 4 ) is electrically connected to the first high concentration impurity region B3 of the third transistor T3 (see Figure 4 Alternatively, the first connection line CL1 may connect the first capacitor plate CSE1 of the first capacitor Cst (see Figure 4 ) is electrically connected to the first high concentration impurity region B3 of the third transistor T3 (see Figure 4 ). One end or one end of the first connection line CL1 may be electrically connected to the first gate electrode G1 and / or the first capacitor plate CSE1 through the first hole CH1 in the second capacitor plate CSE2. In this regard, Figure 7 As shown in FIG, one end or one end portion of the first connection line CL1 can be electrically connected to the first gate electrode G1 and / or the first capacitor plate CSE1 through the tenth contact hole CT10, and the tenth contact hole CT10 can overlap with the first hole CH1. The other end or the other end portion of the first connection line CL1 can be electrically connected to the third semiconductor layer A3 of the third transistor T3, for example, the first high-concentration impurity region B3 (see FIG. Figure 4 ).

[0114] The second connection line CL2 can connect the second capacitor Cpr (see Figure 4 ) is electrically connected to the first transistor T1 (see Figure 4 ), and the third connection line CL3 can connect the second capacitor Cpr (see Figure 4 ) of the fourth capacitor plate CPE2 electrically connected to the second transistor T2 (see Figure 4 ).

[0115] One end or one end of the second connection line CL2 may be electrically connected to the third capacitor plate CPE1 through the second hole CH2 in the fourth capacitor plate CPE2. Figure 7 As shown in FIG, one end or one end portion of the second connection line CL2 may be electrically connected to the third capacitor plate CPE1 through the twelfth contact hole CT12, and the twelfth contact hole CT12 may overlap with the second hole CH2. The other end or the other end portion of the second connection line CL2 may be electrically connected to the first transistor T1 through the thirteenth contact hole CT13 (see FIG. Figure 4 ) of the first semiconductor layer A1, for example, the second high-concentration impurity region C1.

[0116] One end or one end of the third connection line CL3 may be electrically connected to the second transistor T2 through the fourteenth contact hole CT14 (see Figure 4 ) of the second semiconductor layer A2 , for example, the second high-concentration impurity region C2 , and the other end of the third connection line CL3 may be electrically connected to the fourth capacitor plate CPE2 through the fifteenth contact hole CT15 .

[0117] The fourth connection line CL4 may be electrically connected to the sixth transistor T6 (see Figure 4For example, the fourth connection line CL4 can be electrically connected to the sixth transistor T6 through the third hole CH3 in the horizontal power line HDL (see Figure 4 ) of the sixth semiconductor layer A6. In this regard, Figure 7 As can be seen in FIG, one end or one end of the fourth connection line CL4 can be electrically connected to the sixth transistor T6 through the sixteenth contact hole CT16 (see FIG. Figure 4 ) of the sixth semiconductor layer A6, for example, the first high-concentration impurity region B6.

[0118] The fifth connection line CL5 may extend in the same direction as the horizontal power line HDL and be connected to the horizontal power line HDL. The fifth connection line CL5 may be an auxiliary horizontal power line. For example, the fifth connection lines CL5 of the pixel circuits arranged or disposed in the first direction may be electrically connected to each other as a single line.

[0119] Each fifth connection line CL5 may be electrically connected to the fifth transistor T5 through the seventeenth contact hole CT17 (see Figure 4 ) of the fifth semiconductor layer A5, for example, the first high-concentration impurity region B5, and may be electrically connected to the horizontal power line HDL through the eighteenth contact hole CT18.

[0120] The sixth connection line CL6 may be electrically connected to the second transistor T2 through the eighteenth contact hole CT18 (see Figure 4 ) of the first high-concentration impurity region B2 of the second semiconductor layer A2. The seventh connection line CL7 can be electrically connected to the fourth transistor T4 (see Figure 4 ) of the first high-concentration impurity region B4 of the fourth semiconductor layer A4.

[0121] Figure 7 The layers shown in, for example, the scan line SL, the second control line EBL1, the initialization voltage line VIL, the third control line EML1, the first control line GCL, the fifth control line EBL2, the fourth control line EML2, and the first to seventh connection lines CL1 to CL7 may include the same or similar materials. The scan line SL, the second control line EBL1, the initialization voltage line VIL, the third control line EML1, the first control line GCL, the fifth control line EBL2, the fourth control line EML2, and the first to seventh connection lines CL1 to CL7 may include Mo, Al, Cu, Ti, or other suitable materials within the spirit and scope of the present disclosure, and may be formed of a multilayer or single layer including the above materials. The multilayer may have a structure (Ti / Al / Ti) in which a titanium layer, an aluminum layer, and a titanium layer may be sequentially stacked.

[0122] Reference Figure 8The data line DL, the driving voltage line VDL, the reference voltage line VRL and the connection metal layer CML may be formed or arranged on Figure 7 on the layered structure.

[0123] The data line DL may be electrically connected to the second transistor T2. For example, the data line DL may be electrically connected to the sixth connection line CL6 (see FIG. 1 ) through the twentieth contact hole CT20. Figure 7 ) and can be connected via the sixth connection line CL6 (see Figure 7 ) is electrically connected to the second transistor T2.

[0124] The driving voltage line VDL may be electrically connected to the second capacitor plate CSE2 of the first capacitor Cst and / or the horizontal power line HDL. For example, the driving voltage line VDL may be electrically connected to the fifth connection line CL5 (see FIG. 1 ) through the twenty-first contact hole CT21. Figure 7 ) and can be connected via the fifth connection line CL5 (see Figure 7 ) is electrically connected to the horizontal power line HDL and / or the second capacitor plate CSE2.

[0125] The reference voltage line VRL may be electrically connected to the fourth transistor T4. For example, the reference voltage line VRL may be electrically connected to the fourth transistor T4 via the seventh connection line CL7 (see FIG. Figure 7 ) is electrically connected to the fourth transistor T4.

[0126] The connection metal layer CML may be electrically connected to the fourth connection line CL4 through the twenty-third contact hole CT23 (see Figure 7 The connection metal layer CML may serve as a medium that may electrically connect the sixth transistor T6 to a pixel electrode (eg, an anode) of an organic light emitting diode to be described later.

[0127] The data lines DL, the driving voltage lines VDL, the reference voltage lines VRL, and the connection metal layer CML may include the same or similar materials. Within the spirit and scope of the present disclosure, the data lines DL, the driving voltage lines VDL, the reference voltage lines VRL, and the connection metal layer CML may include Mo, Al, Cu, Ti, or other suitable materials, and may be formed of a multilayer or single layer including the above materials. The multilayer may have a structure (Ti / Al / Ti) in which a titanium layer, an aluminum layer, and a titanium layer may be sequentially stacked.

[0128] Figure 9 is a schematic cross-sectional view of a display device according to an embodiment.

[0129] Reference Figure 9 , a buffer layer 111 may be formed or disposed on the substrate 100, and referring to Figure 4The first to eighth semiconductor layers described may be arranged or disposed on the buffer layer 111. In this regard, Figure 9 A first semiconductor layer A1 and a sixth semiconductor layer A6 are shown.

[0130] The buffer layer 111 can reduce or prevent foreign matter, moisture, or external air from penetrating from under the substrate 100, and can provide a flat surface on the substrate 100. The buffer layer 111 may include an inorganic insulating layer such as silicon oxide, silicon oxynitride, and silicon nitride, and may be formed of a single layer or a multilayer structure including the above materials.

[0131] The gate insulating layer 112 may be formed or disposed on the semiconductor layer, and may be formed or disposed on the semiconductor layer. Figure 5 The layered structures described, for example, the gate electrode, the first capacitor plate CSE1 and the third capacitor plate CPE1, may be arranged or disposed on the gate insulating layer 112. In this regard, Figure 9 , a first gate electrode G1, a first capacitor plate CSE1, and a third capacitor plate CPE1 are shown. The gate insulating layer 112 may include an inorganic insulating material such as silicon oxide, silicon oxynitride, and silicon nitride, and may be formed of a single layer or a multilayer structure including the above materials.

[0132] The first interlayer insulating layer 113 may be disposed on the gate electrode, the first capacitor plate CSE1, and the third capacitor plate CPE1. The first interlayer insulating layer 113 may include an inorganic insulating material such as silicon oxide, silicon oxynitride, and silicon nitride, and may be formed of a single layer or a multilayer structure including the above materials.

[0133] Reference Figure 6 The layered structures described above, such as the horizontal power supply line HDL, the second capacitor plate CSE2, and the fourth capacitor plate CPE2, may be arranged or disposed on the first interlayer insulating layer 113. A second interlayer insulating layer 116 may be arranged or disposed on the horizontal power supply line HDL, the second capacitor plate CSE2, and the fourth capacitor plate CPE2. The second interlayer insulating layer 116 may include an inorganic insulating material such as silicon oxide, silicon oxynitride, and silicon nitride, and may be formed of a single layer or a multilayer structure including the above materials.

[0134] Reference Figure 7 The layered structures described above, for example, the scan lines, the first to fifth control lines, and the first to seventh connection lines, may be arranged or disposed on the second interlayer insulating layer 116. In this regard, Figure 9 As may be shown in FIG. 1 , the first to fourth connection lines CL1 , CL2 , and CL4 may be arranged or disposed on the second interlayer insulating layer 116 .

[0135] The first connection line CL1 may be electrically connected to the first capacitor plate CSE1 through the first hole CH1. One end or one end of the second connection line CL2 may be electrically connected to the third capacitor plate CPE1 through the second hole CH2, and the other end of the second connection line CL2 may be electrically connected to the first semiconductor layer A1, for example, the second high-concentration impurity region C1.

[0136] The first planarization insulating layer 117 may be disposed on the first, second, and fourth connection lines CL1, CL2, and CL4 and may include an organic insulating material such as acrylic, benzocyclobutene (BCB), polyimide, or hexamethyldisiloxane (HMDSO).

[0137] Reference Figure 8 The described layered structures, for example, the driving voltage line VDL, the connection metal layer CML, and the like, may be arranged or disposed on the first planarization insulating layer 117. The connection metal layer CML may be electrically connected to the fourth connection line CL4, and the fourth connection line CL4 may be electrically connected to the sixth semiconductor layer A6 through the third hole CH3.

[0138] The pixel electrode 221 may be arranged or disposed on the second planarization insulating layer 119 and may be electrically connected to the connection metal layer CML through a contact hole in the second planarization insulating layer 119. The pixel electrode 221 may be electrically connected to the sixth semiconductor layer A6 of the sixth transistor via the connection metal layer CML and the fourth connection line CL4. The second planarization insulating layer 119 may include an organic insulating material such as acrylic, BCB, polyimide, or HMDSO.

[0139] The upper insulating layer 120 may be arranged or disposed on the pixel electrode 221. The upper insulating layer 120 may cover or overlap an edge of the pixel electrode 221, but may include an opening overlapping a central portion of the pixel electrode 221. The upper insulating layer 120 may include an organic insulating layer such as BCB, polyimide, or HMDSO.

[0140] The emission layer 222 may overlap with the pixel electrode 221 through the opening of the upper insulating layer 120. The emission layer 222 may include an organic material capable of emitting light of a certain or predetermined color. Although not shown, a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL) and / or an electron injection layer (EIL) may be provided or disposed below and / or above the emission layer 222.

[0141] The opposite electrode 223 can be formed of a conductive material having a relatively low work function. For example, the opposite electrode 223 may include a (semi) transparent layer, and the (semi) transparent layer includes Ag, Mg, Al, Ni, Cr, Li, Ca or an alloy thereof. Alternatively, the opposite electrode 223 may include a layer such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO) or indium oxide (In2O3) on the (semi) transparent layer. In an embodiment, the opposite electrode 223 may include Ag and Mg.

[0142] According to the reference Figure 9 In the described embodiment, although it is described that the light emitting diode may be an organic light emitting diode OLED including a stack of pixel electrodes 221, an emission layer 222, and an opposite electrode 223, in an embodiment, the light emitting diode may be an inorganic light emitting diode including an inorganic material. The inorganic light emitting diode may include a PN junction diode including an inorganic semiconductor material. When a voltage is applied to the PN junction diode in a forward direction, holes and electrons may be injected, and the energy generated by the recombination of holes and electrons may be converted into light energy so as to emit light of a certain or predetermined color. The above-mentioned inorganic light emitting diode may have a width of several microns to several hundred microns, and in an embodiment, the inorganic light emitting diode may be referred to as a micro light emitting diode (LED).

[0143] According to the reference Figures 4 to 9 In the embodiment, although it is described that the first gate electrode G1 of the first transistor T1 may include the first capacitor plate CSE1 of the first capacitor Cst, in the embodiment, the first gate electrode G1 of the first transistor T1 may be formed separately from the first capacitor plate CSE1 of the first capacitor Cst.

[0144] Figure 10 is a schematic cross-sectional view of a display device according to an embodiment.

[0145] Reference Figure 10 The first gate electrode G1 of the first transistor T1 and the first capacitor plate CSE1 of the first capacitor Cst may be arranged or disposed on different layers. For example, the first gate electrode G1 of the first transistor T1 may be arranged or disposed on the gate insulating layer 112, and the first capacitor plate CSE1 of the first capacitor Cst may be arranged or disposed on the first interlayer insulating layer 113. The first capacitor plate CSE1 of the first capacitor Cst may be electrically connected to the first gate electrode G1 of the first transistor T1 through a contact hole of the first interlayer insulating layer 113.

[0146] The first capacitor Cst may include a first capacitor plate CSE1 and a second capacitor plate CSE2, and the second capacitor Cpr may include a third capacitor plate CPE1 and a fourth capacitor plate CPE2. A first intermediate insulating layer 114 may be disposed or provided on the first capacitor plate CSE1 and the third capacitor plate CPE1, and a second intermediate insulating layer 115 may be disposed or provided on the second capacitor plate CSE2 and the fourth capacitor plate CPE2.

[0147] Each of the first and second intermediate insulating layers 114 and 115 may include an inorganic insulating material such as silicon oxide, silicon oxynitride, and silicon nitride, and may have a single-layer or multi-layer structure including the above materials.

[0148] The horizontal power line HDL may be arranged or disposed on the second intermediate insulating layer 115, and the second interlayer insulating layer 116 may be arranged or disposed on the horizontal power line HDL. The first connection line CL1, the second connection line CL2, and the fourth connection line CL4 may be arranged or disposed on the second interlayer insulating layer 116, and the driving voltage line VDL and the connection metal layer CML may be arranged or disposed on the first planarizing insulating layer 117.

[0149] The first connection line CL1 may be electrically connected to the first capacitor plate CSE1 through the first hole CH1 of the second capacitor plate CSE2 and the fourth hole CH4 of the horizontal power line HDL. The second connection line CL2 may be electrically connected to the second high-concentration impurity region C2 of the first semiconductor layer A1 via the first auxiliary contact layer ACL1 and may be electrically connected to the third capacitor plate CPE1 through the second hole CH2. Figure 10 The pixel electrode 221 can be electrically connected to the fourth connection line CL4, and the fourth connection line CL4 can be electrically connected to the sixth semiconductor layer A6 via the second auxiliary contact layer ACL2. For example, other elements and structures of the display device can be as described above with reference to Figure 9 described.

[0150] According to the above embodiment, the size (or width) of the first hole CH1 of the second capacitor plate CSE2 of the first capacitor Cst can be formed to be different from the size (or width) of the second hole CH2 of the fourth capacitor plate CPE2 of the second capacitor Cpr. For example, the size (or width) of the first hole CH1 of the second capacitor plate CSE2 of the first capacitor Cst can be formed to be smaller than the size (or width) of the second hole CH2 of the fourth capacitor plate CPE2 of the second capacitor Cpr. A pixel circuit having the above characteristics can minimize or prevent brightness variations of a display device and can minimize and prevent the generation of spots.

[0151] For example, according to the reference Figure 2In the pixel circuit described above, a voltage corresponding to the difference between the voltage of the driving power supply voltage ELVDD and the voltage of the second node N2 can be stored in the first capacitor Cst, and the voltage stored in the first capacitor Cst can be affected by the value of CCpr / (CCst+CCpr). Figure 4 In the case where a skew occurs due to process dispersion during formation of the pixel circuit shown in , for example, each electrode, line, and capacitor plate may be formed to have a width smaller than an ideal width in the process of forming the electrode, line, and capacitor plate, CCpr / (CCst+CCpr) may fluctuate due to process dispersion, thereby causing brightness variation and / or spot generation.

[0152] However, according to embodiments, the above-described problem can be prevented or minimized because the size (or width) of the first hole CH1 of the second capacitor plate CSE2 of the first capacitor Cst can be formed differently from the size (or width) of the second hole CH2 of the fourth capacitor plate CPE2 of the second capacitor Cpr. For example, by forming the size (or width) of the second hole CH2 of the second capacitor Cpr to have a relatively large capacitance greater than the size (or width) of the first hole CH1, CCpr / (CCst+CCpr) can be kept relatively constant despite the occurrence of skew, thereby minimizing the possibility of brightness variations and the generation of spots.

[0153] Figure 11 is a graph showing the difference in data transmission between the first hole CH1 and the second hole CH2. Figure 11 In the figure, the Y-axis indicates the value of the difference in data transmission compared to the case where the skew is 0 (zero), and the X-axis indicates the degree of skew. On the Y-axis, 0 indicates the case where the skew is 0 (zero), and on the X-axis, skew -0.2 (both sides) indicates that a skew of about 0.2 μm occurs in the width direction, and skew -0.4 (both sides) indicates that a skew of about 0.4 μm occurs in the width direction.

[0154] exist Figure 11 , the comparative example indicates a case where the sizes of the first hole CH1 and the second hole CH2 are the same, embodiment 1 indicates a case where the size of the second hole CH2, for example, the width, is greater than the width of the first hole CH1 by 0.2 μm, and embodiment 2 indicates a case where the size of the second hole CH2, for example, the width, is greater than the width of the first hole CH1 by 0.4 μm.

[0155] Reference Figure 11, it can be seen that, in the case of skew caused by the process, since the size of the second hole CH2 is larger than the size of the first hole CH1, the difference in data transmission gradually decreases compared to the case where the skew is 0 (zero). For example, it can be shown that since the size of the second hole CH2 is larger than the size of the first hole CH1, it becomes more similar to the case where the difference in data transmission is ideal. Gradually reducing the difference in data transmission compared to the case where the skew is 0 (zero) means that the brightness variation and / or the generation of spots caused by process dispersion can be minimized. The display device according to the embodiment can provide high-quality images with the above advantages.

[0156] The display device according to the embodiment can provide a pixel circuit suitable for high-speed driving and can effectively control brightness variation caused by process dispersion of capacitors in the pixel circuit in which the capacitors may be provided. Therefore, the display device can display high-quality images.

[0157] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the drawings, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope as defined by the appended claims.

Claims

1. A display device comprising: a scan line extending in a first direction; a data line and a driving voltage line each extending in a second direction; a first transistor electrically connected to the driving voltage line and comprising a first gate electrode and a first semiconductor layer; a second transistor electrically connected to the data line and the scan line and comprising a second gate electrode and a second semiconductor layer; a first capacitor electrically connected to the first transistor and comprising a first capacitor plate and a second capacitor plate; as well as A second capacitor comprising: a third capacitor plate electrically connected to the first transistor; and a fourth capacitor plate electrically connected to the second transistor, wherein the second capacitor plate comprising a first aperture overlapping the first capacitor plate, The fourth capacitor plate includes a second aperture overlapping the third capacitor plate, and The width of the second hole is greater than the width of the first hole.

2. The display device according to claim 1, wherein The third capacitor plate includes an isolation pattern.

3. The display device according to claim 2, further comprising a first connection line electrically connecting the third capacitor plate and the first transistor, in, The first connection line is electrically connected to the third capacitor plate through the second hole of the fourth capacitor plate.

4. The display device according to claim 1, wherein The third capacitor plate is electrically connected to one of a source region and a drain region of the first semiconductor layer of the first transistor, and The fourth capacitor plate is electrically connected to one of a source region and a drain region of the second semiconductor layer of the second transistor.

5. The display device according to claim 1, wherein The fourth capacitor plate includes an isolation pattern. 6 . The display device of claim 5 , further comprising a second connection line electrically connecting the fourth capacitor plate and the second transistor.

7. The display device according to claim 1, wherein The first capacitor plate includes an isolation pattern.

8. The display device according to claim 7, further comprising: a third transistor electrically connected to the first transistor; as well as The third connecting line electrically connects the first capacitor and the third transistor.

9. The display device according to claim 8, wherein The third connection line is electrically connected to the first capacitor plate through the first hole of the second capacitor plate.

10. The display device according to claim 1, wherein The first capacitor plate includes the first gate electrode of the first transistor.

11. The display device according to claim 1 , further comprising: a fourth transistor electrically connected to the second capacitor and the second transistor; as well as A reference voltage line extends in the second direction and is electrically connected to the fourth transistor.

12. A display device comprising: a scan line extending in a first direction; a data line and a driving voltage line each extending in a second direction; a first transistor electrically connected to the driving voltage line and comprising a first gate electrode and a first semiconductor layer; a first capacitor electrically connected to the first transistor and comprising a first capacitor plate and a second capacitor plate; a second transistor electrically connected to the data line and the scan line and comprising a second gate electrode and a second semiconductor layer; as well as a second capacitor electrically connected to the first transistor and the second transistor and comprising a third capacitor plate and a fourth capacitor plate, wherein The first capacitor and the second capacitor are spaced apart from each other, the second capacitor plate comprising a first aperture overlapping the first capacitor plate, The fourth capacitor plate includes a second aperture overlapping the third capacitor plate, and The width of the second hole is greater than the width of the first hole.

13. The display device according to claim 12, wherein: The third capacitor plate is electrically connected to one of a source region and a drain region of the first semiconductor layer of the first transistor, and The fourth capacitor plate is electrically connected to one of a source region and a drain region of the second semiconductor layer of the second transistor.

14. The display device according to claim 13, further comprising a first connection line electrically connecting the second capacitor and the first transistor. in, The first connection line is electrically connected to the third capacitor plate through the second hole of the fourth capacitor plate.

15. The display device according to claim 13, wherein The third capacitor plate includes an isolation pattern. 16 . The display device of claim 14 , further comprising a second connection line electrically connecting the fourth capacitor plate of the second capacitor and the second transistor.

17. The display device according to claim 12, further comprising: a third transistor electrically connected to the first transistor; as well as a third connecting line electrically connecting the first capacitor and the third transistor; The third connecting line is electrically connected to the first capacitor plate through the first hole of the second capacitor plate.

18. The display device according to claim 17, wherein: The first capacitor plate includes an isolation pattern.

19. The display device according to claim 12, wherein: The first capacitor plate includes the first gate electrode of the first transistor.

20. The display device according to claim 12, further comprising: a fourth transistor electrically connected to the second capacitor and the second transistor; as well as A reference voltage line extends in the second direction and is electrically connected to the fourth transistor.

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