Display panel, driving method thereof, driving circuit and display device

Abstract

The invention provides a display panel, a driving method thereof, a driving circuit and a display device.The display panel comprises a plurality of scanning lines, a plurality of data lines and pixel circuits arranged in an array mode, and each pixel circuit comprises a light-emitting unit, a light-emitting driving unit, a storage capacitor, a switching circuit, a data switch and a logic circuit. The logic circuit carries out AND operation on input line scanning signals and data signals, outputs corresponding first level signals or second level signals, and controls the switching circuit to store the data signals of the next frame to the storage capacitor or maintain the data signals of the previous frame in a sampling period. In a light emitting period, a light receiving emission signal triggers a driving tube to output a current signal to drive a light emitting unit to emit light, by selecting whether to input a data signal and a line scanning signal to a data line and a scanning line, a corresponding pixel circuit can be controlled to maintain a current picture and switch a display picture, independent control of a single pixel circuit can be realized, and the display efficiency is improved. And the display requirements of different refresh rates are met.

Description

Technical Field

[0001] The present invention belongs to the technical field of display panels, and in particular relates to a display panel and a driving method, a driving circuit and a display device thereof. Background Art

[0002] With the development of display technology and market demand, high refresh rate display devices have gradually come into people's view. Compared with traditional display devices, high refresh rate display devices have the advantages of smoother visual experience, faster response speed, and reduced visual fatigue. However, at the same time, high refresh rate also brings higher power consumption requirements.

[0003] In response to the contradiction between the pursuit of visual images and power consumption requirements, the technology of differentiated local refresh rate FFR (freeframe rate) is proposed. When displaying a static image, when it is judged that the local display content of the image remains unchanged, the refresh rate is low. When the image content changes in the next frame, the refresh rate is high.

[0004] However, current FRR technologies are all based on the timing adjustment of multiple GOA units in the gate drive circuit, which has great limitations. First, in the gate drive circuit, the GOA unit controls the picture in units of at least one line, and the local adjustment requirements of the refresh rate based on changes in the picture content are complex. For example, when different positions on the same line of the picture require different refresh rates, it cannot be achieved.

[0005] In addition, due to the design characteristics of the GOA unit, the FFR technology based on GOA timing adjustment requires that the refresh rate of the previous row in the refresh direction is higher than that of the next row, which greatly limits the application scenarios of this technology. Summary of the Invention

[0006] An object of the present invention is to provide a display panel, aiming to solve the problem that the driving architecture of a traditional display device cannot meet the requirements of different refresh rates at different locations.

[0007] A first aspect of an embodiment of the present invention provides a display panel including a plurality of scan lines, a plurality of data lines, and a pixel circuit arranged in an array, wherein the pixel circuit includes: Light-emitting unit; a light-emitting driving unit connected in series with the light-emitting unit between the anode voltage terminal and the cathode voltage terminal, the light-emitting driving unit comprising a first light-emitting switch, a driving tube, and a second light-emitting switch connected in series in sequence, the driving tube being configured to convert a data signal input during a sampling period into a current signal, the first light-emitting switch and the second light-emitting switch being configured to be triggered to conduct during a light-emitting period by the light-emitting signal to output the current signal; a storage capacitor, wherein a first terminal of the storage capacitor is connected to the anode voltage terminal or the cathode voltage terminal; a switch circuit, connected to the second end of the storage capacitor, the anode voltage end, the control end and the output end of the driver transistor, respectively; the switch circuit is triggered by a first level signal to connect the anode voltage end and the control end of the driver transistor and the second end of the storage capacitor and the output end of the driver transistor, and is triggered by a second level signal to connect the second end of the storage capacitor and the control end of the driver transistor; a data switch connected to the data line, the scan line, and the input end of the driver tube, respectively; the data switch is triggered by a row-on signal to turn on and transmit the data signal on the data line to the driver tube, and is triggered by a row-off signal to turn off; A logic circuit is respectively connected to the data line, the scan line and the switching circuit, and is used to trigger the output of the first level signal to the switching circuit when the row start signal and the data signal are received at the same time, and to trigger the output of the second level signal to the switching circuit when the row start signal and the data signal are not received at the same time.

[0008] Optionally, the first light emission switch includes a first transistor, a second end of the first transistor is connected to the input end of the driving transistor, and a control end of the first transistor is used to input the light emission signal; The second light emitting switch includes a second transistor, the first end of the second transistor is connected to the output end of the driving tube, the control end of the second transistor is connected to the control end of the first transistor, the first end of the first transistor is connected to the anode voltage end, and the second end of the second transistor is connected to the light emitting unit, or the first end of the first transistor is connected to the light emitting unit, and the second end of the second transistor is connected to the cathode voltage end.

[0009] Optionally, the switch circuit includes a third transistor, a fourth transistor and a fifth transistor; The first end of the third transistor and the first end of the storage capacitor are connected to the anode voltage end, the second end of the third transistor and the second end of the fourth transistor are connected to the control end of the driving tube, the first end of the fourth transistor and the first end of the fifth transistor are connected to the second end of the storage capacitor, and the control end of the third transistor, the control end of the fourth transistor, and the control end of the fifth transistor are connected to the output end of the logic circuit.

[0010] Optionally, the logic circuit includes a sixth transistor, a seventh transistor, an eighth transistor and a ninth transistor; The first end of the sixth transistor is used to input the first level signal, the second end of the sixth transistor is connected to the first end of the seventh transistor, the control end of the sixth transistor and the control end of the eighth transistor are connected to the scan line, the second end of the seventh transistor, the first end of the eighth transistor and the first end of the ninth transistor are connected to form the output end of the logic circuit, the control end of the seventh transistor and the control end of the ninth transistor are connected to the data line, and the second end of the eighth transistor is connected to the second end of the ninth transistor and is used to input the second level signal.

[0011] Optionally, the pixel circuit further includes: A reset switch, wherein the first end of the reset switch is used to input a reset signal, the second end of the reset switch is connected to the light-emitting unit, the control end of the reset switch is connected to the output end of the logic circuit, and the reset switch is triggered to turn on by the first level signal and triggered to turn off by the second level signal.

[0012] A second aspect of an embodiment of the present invention provides a method for driving a display panel, for driving the display panel as described above. The method for driving a display panel includes: Determining whether the image content of the next frame of the target partial image of the display panel changes; When the image content of the next frame of the target partial image remains unchanged, switching to the hold mode, and during the next frame scan drive, outputting the corresponding row start signal and not outputting the data signal to the target pixel circuit corresponding to the target partial image, and controlling the storage capacitor of the target pixel circuit to maintain the data signal of the previous frame; When the picture content of the next frame of the target partial picture changes, it switches to the working mode, and during the next frame scanning drive, outputs the corresponding data signal and the row start signal to the target pixel circuit corresponding to the target partial picture, and controls the storage capacitor of the target pixel circuit to input the data signal of the current frame.

[0013] Optionally, when the picture content of the next frame of the target partial picture remains unchanged, switching to the maintenance mode, and outputting the corresponding row start signal and not outputting the data signal to the target pixel circuit corresponding to the target partial picture during the next frame scan drive, includes: During a sampling period of the sustain mode, a row start signal is output to the scan line, and no data signal is output to the data line; During the light emission period of the sustain mode, a row start signal is not output to the scan line, and a data signal of a next frame is output to the data line or no data signal is output to the data line.

[0014] Optionally, when the picture content of the next frame of the target partial picture changes, switching to the working mode, and outputting the corresponding data signal and the row start signal to the target pixel circuit corresponding to the target partial picture during the next frame scan drive, includes: During a sampling period of the working mode, outputting a row start signal to the scan line and outputting a data signal to the data line; During the light emitting period of the operation mode, a row start signal is not output to the scan line, and a data signal of the next frame is output to the data line or no data signal is output to the data line.

[0015] A third aspect of an embodiment of the present invention provides a driving circuit for a display panel, comprising a source driving circuit, a gate driving circuit, and a timing controller, wherein the source driving circuit is respectively connected to a plurality of data lines of the display panel, and the gate driving circuit is respectively connected to a plurality of scan lines of the display panel; The timing controller is connected to the source driving circuit and the gate driving circuit respectively, and is used to output control signals to the source driving circuit and the gate driving circuit to implement the driving method of the display panel as described above.

[0016] A fourth aspect of the embodiments of the present invention provides a display device, including the display panel described above and the driving circuit of the display panel described above, wherein the driving circuit of the display panel is connected to the display panel.

[0017] Compared with the prior art, the embodiments of the present invention have the following beneficial effects: the above-mentioned display panel includes multiple scan lines, multiple data lines and pixel circuits arranged in an array, the pixel circuit includes a light-emitting unit, a light-emitting driving unit, a storage capacitor, a switching circuit, a data switch and a logic circuit, the logic circuit performs an AND operation on the input row scan signal and the data signal, and outputs a corresponding first-level signal or a second-level signal to the switching circuit, thereby controlling the switching circuit to store the data signal of the next frame in the storage capacitor during the sampling period or control the storage capacitor to maintain the data signal of the previous frame, and triggering the driving tube to output a current signal to drive the light-emitting unit to emit light during the light-emitting period by the light emission signal. By selecting whether to input the data signal and the row scan signal to the data line and the scan line, the corresponding pixel circuit can be controlled to maintain the current picture and switch the display picture, and independent control of a single pixel circuit can be achieved to meet the display requirements of different refresh rates. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A schematic diagram of a first structure of a display panel provided in the first embodiment of the present invention; Figure 2 A schematic diagram of a second structure of a display panel provided in the first embodiment of the present invention; Figure 3 A first circuit diagram of a pixel circuit provided in Embodiment 1 of the present invention; Figure 4 A schematic diagram of a first signal timing sequence of a pixel circuit provided in the first embodiment of the present invention; Figure 5 A second signal timing diagram of the pixel circuit provided in the first embodiment of the present invention; Figure 6 A third signal timing diagram of the pixel circuit provided in the first embodiment of the present invention; Figure 7 A fourth signal timing diagram of the pixel circuit provided in the first embodiment of the present invention; Figure 8 A second circuit diagram of the pixel circuit provided in the first embodiment of the present invention; Figure 9 A circuit diagram of a pixel circuit provided in Embodiment 2 of the present invention; Figure 10 A schematic flow chart of a method for driving a display panel provided in a third embodiment of the present invention; Figure 11 for Figure 10 FIG. 1 is a flow chart of step S20 of the method for driving the display panel; FIG. Figure 12 for Figure 10 FIG. 1 is a flow chart of step S30 of the method for driving the display panel; FIG. Figure 13 This is a structural diagram of a display panel driving circuit and a display device provided in the fourth and fifth embodiments of the present invention.

[0019] Among them, the reference numerals in the figures are: 100, display panel; 200, display panel drive circuit; 210, source drive circuit; 220, gate drive circuit; 230, timing controller; 10, pixel circuit; 20, light-emitting unit; 101, light-emitting drive unit; 11, first light-emitting switch; 12, second light-emitting switch; 13, switch circuit; 14, data switch; 15, logic circuit; 16, reset switch; SD, driving tube; T1, first transistor; T2, second transistor; T3, third transistor; T4, fourth transistor; T5, fifth transistor; T6, sixth transistor; T7, seventh transistor; T8, eighth transistor; T9, ninth transistor; T10, tenth transistor; T11, eleventh transistor; Cst, storage capacitor; OLED, light-emitting diode; S1, first data line; S2, second data line; S3, third data line; S4, fourth data line; G1, first scan line; G2, second scan line; G3, third scan line; G4, fourth scan line; G5, fifth scan line; G6, sixth scan line; VDD, anode voltage; VSS, cathode voltage; Da, data signal; Sc, row scan signal; Sc1, first row scan signal; Sc2, second row scan signal; Sc3, third row scan signal; Da1, first data signal; Da2, second data signal; Da3, third data signal; Vint, reset signal; EM, light emission signal; VGH, row turn-on signal; VGL, row turn-off signal; Vd, terminal voltage of light-emitting unit; t11, sampling period of the first frame; t12, light-emitting period of the first frame; t21, sampling period of the second frame; t22, light-emitting period of the second frame; t31, sampling period of the third frame; t32, light-emitting period of the third frame. DETAILED DESCRIPTION

[0020] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0021] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0022] Example 1 A first aspect of an embodiment of the present invention provides a display panel 100, such as Figure 1 and Figure 2 As shown, it includes a plurality of scan lines, a plurality of data lines and a pixel circuit 10 arranged in an array, for example Figure 1As shown, the plurality of scan lines include a first scan line G1, a second scan line G2, a third scan line G3, a fourth scan line G4, a fifth scan line G5, and a sixth scan line G6, and the plurality of data lines include a first data line S1, a second data line S2, a third data line S3, and a fourth data line S4. The pixel circuit 10 is connected to a scan line and a data line respectively. For example, Figure 2 As shown, the pixel circuit 10 in the first row and the first column is connected to the first scan line G1 and the first data line S1 and inputs the first row scan signal Sc1 and the first data signal Da1, the pixel circuit 10 in the second row and the second column is connected to the second scan line G2 and the second data line S2 and inputs the second row scan signal Sc2 and the second data signal Da2, the pixel circuit 10 in the third row and the third column is connected to the third scan line G3 and the third data line S3 and inputs the third row scan signal Sc3 and the third data signal Da3, the pixel circuit 10 is used to generate a current signal to the light-emitting unit 20 inside the pixel circuit 10 according to the received row scan signal Sc and data signal Da, and the light-emitting unit 20 lights up and emits light accordingly.

[0023] In order to independently control each pixel circuit 10 of a target partial screen or a target pixel circuit and meet different refresh rate requirements, the pixel circuit 10 includes: Light emitting unit 20; The light driving unit 101 and the light emitting unit 20 are connected in series between the anode voltage terminal and the cathode voltage terminal. The anode voltage terminal is used to input the anode voltage VDD, and the cathode voltage terminal is used to input the cathode voltage VSS. The anode voltage VDD is greater than the cathode voltage VSS.

[0024] The relative positions of the light emitting unit 20 and the light emitting driving unit 101 can be set accordingly according to the requirements. In an optional embodiment, as shown in FIG. Figure 3 As shown, the anode voltage terminal, the light emitting driving unit 101, the light emitting unit 20 and the cathode voltage terminal are connected in sequence, or, in another optional embodiment, the anode voltage terminal, the light emitting unit 20, the light emitting driving unit 101 and the cathode voltage terminal.

[0025] like Figure 3 As shown, the light-emitting drive unit includes a first light-emitting switch 11, a driving tube SD, and a second light-emitting switch 12 connected in series. The driving tube SD is used to convert the data signal Da input during the sampling period into a current signal. The first light-emitting switch 11 and the second light-emitting switch 12 are used to be triggered to turn on and output the current signal during the light-emitting period by the light-emitting signal EM. a storage capacitor Cst, wherein a first terminal of the storage capacitor Cst is connected to the anode voltage terminal, or, in another optional embodiment, a first terminal of the storage capacitor Cst is connected to the cathode voltage terminal, and the storage capacitor Cst may be correspondingly connected to a voltage terminal having a stable voltage; The switch circuit 13 is respectively connected to the second terminal of the storage capacitor Cst, the anode voltage terminal, and the control terminal and the output terminal of the driving transistor SD. The switch circuit 13 is triggered by a first level signal to connect the anode voltage terminal to the control terminal of the driving transistor SD and to connect the second terminal of the storage capacitor Cst to the output terminal of the driving transistor SD. The switch circuit 13 is triggered by a second level signal to connect the second terminal of the storage capacitor Cst to the control terminal of the driving transistor SD. The data switch 14 is connected to the data line, the scan line and the input end of the driver SD respectively. The data switch 14 is triggered by the line start signal VGH to turn on and transmit the data signal Da on the data line to the driver SD, and is triggered by the line close signal VGL to turn off. The logic circuit 15 is connected to the data line, the scan line and the switch circuit 13 respectively, and is used to trigger the output of a first level signal to the switch circuit 13 when the row start signal VGH and the data signal Da are received at the same time, and to trigger the output of a second level signal to the switch circuit 13 when the row start signal VGH and the data signal Da are not received at the same time.

[0026] In this embodiment, the driving tube SD can be a P-channel thin film transistor or an N-channel thin film transistor, and the row scanning signal Sc is composed of a row start signal VGH and a row stop signal VGL. In each frame, each pixel circuit 10 can operate in a sampling period and a light-emitting period in sequence. When the current frame row scans to the pixel circuit 10 of the corresponding row, during the sampling period, the row start signal VGH is input to the scanning line connected to the corresponding pixel circuit 10, and the data line connected to the corresponding pixel circuit 10 inputs the data signal Da or does not input the data signal Da. During the light-emitting period, the row stop signal VGL is input to the corresponding scanning line. At the same time, the pixel circuit 10 receives the light emission signal EM and generates a current signal to the light-emitting unit 20, and drives the light-emitting unit 20 to light up.

[0027] The pixel circuit 10 can switch between an operating mode and a sustaining mode according to the received data signal Da and the row scanning signal Sc. The operating mode can refresh the input data signal Da, and the sustaining mode can maintain the data signal Da of the previous frame.

[0028] In the row-by-row scanning, when scanning a plurality of pixel circuits 10 of a target partial screen, the number of target pixel circuits may include one or more.

[0029] Take the first terminal of the storage capacitor Cst connected to the anode voltage terminal as an example, Figure 4As shown, Vd represents the terminal voltage of the light-emitting unit 20. In the working mode, during the sampling period of the pixel circuit 10, such as the sampling period t11 of the first frame, when scanning to the row where the pixel circuit 10 is located, the scanning line connected to the pixel circuit 10 inputs the row start signal VGH, the data line connected to the pixel circuit 10 inputs the data signal Da, the logic circuit 15 outputs the first level signal, the switch circuit 13 connects the anode voltage terminal and the control terminal of the driving tube SD, and connects the second terminal of the storage capacitor Cst and the output terminal of the driving tube SD. At this time, no light emission signal EM is input, the first light emission switch 11 and the second light emission switch 12 are in the state of switching. The emission switch 12 is turned off, and the data signal Da is output to the storage capacitor Cst through the drive tube SD and the switch circuit 13. In the loop formed by the anode voltage terminal, the storage capacitor Cst, the switch circuit 13, the drive tube SD, and the data line, according to Kirchhoff's law, VDD-Vdata+Vcst-VDD-Vth=0, that is, Vcst=Vdata+Vth, where Vcst is the storage voltage of the storage capacitor Cst, Vth is the threshold voltage of the drive tube SD, and Vdata is the data voltage of the data signal Da. The pixel circuit 10 completes the sampling of the data signal Da.

[0030] Then, during a light-emitting period, such as the light-emitting period t12 of the first frame, when the scanning of the current row is completed and the data signal Da is not input to other rows, at this time, the scanning line connected to the pixel circuit 10 inputs the row-off signal VGL, and the data line connected to the pixel circuit 10 does not input the data signal Da. The logic circuit 15 outputs a second-level signal, and the switch circuit 13 connects the second end of the storage capacitor Cst and the control end of the driving tube SD. The stored voltage of the storage capacitor Cst is output to the driving tube SD. At this time, the light emission signal EM is input, the first light emission switch 11 and the second light emission switch 12 are turned on, and the anode voltage end, the first light emission switch 11, the driving tube SD, and the second light emission switch 12 form a current loop. The driving tube SD generates a current signal and outputs it to the light-emitting unit 20 through the second light emission switch 12. The light-emitting unit 20 displays the grayscale data of the sampling stage and emits light normally, achieving a high refresh rate.

[0031] Alternatively, during the light-emitting period, when other rows are scanned, the data line switches to input data signal Da due to the data signal Da of other rows. At this time, the scan line connected to the pixel circuit 10 inputs the row shutdown signal VGL, the logic circuit 15 still outputs the second level signal normally, the switch circuit 13 connects the second end of the storage capacitor Cst and the control end of the driving tube SD, and the storage voltage of the storage capacitor Cst is output to the driving tube SD. At this time, the light emission signal EM is input, the first light emission switch 11 and the second light emission switch 12 are turned on, the anode voltage end, the first light emission switch 11, the driving tube SD and the second light emission switch 12 form a current loop, the driving tube SD generates a current signal and outputs it to the light-emitting unit 20 through the second light emission switch 12, the light-emitting unit 20 displays the grayscale data of the sampling stage and emits light normally, achieving a high refresh rate.

[0032] When switching to the sustain mode of the next frame, in the sampling period of the pixel circuit 10, such as the sampling period t21 of the second frame, when scanning to the row where the pixel circuit 10 is located, the scan line connected to the pixel circuit 10 inputs the row start signal VGH, and the data line connected to the pixel circuit 10 does not input the data signal Da. At this time, the data line is in a low level state, the logic circuit 15 outputs a second level signal, and the switch circuit 13 connects the second end of the storage capacitor Cst and the control end of the driving tube SD. At this time, the light emission signal EM is not input, the first light emission switch 11 and the second light emission switch 12 are turned off, and the data signal Da stored in the storage capacitor Cst in the previous frame cannot be output to the storage capacitor Cst through the driving tube SD and the switch circuit 13 or be refreshed by the new data signal Da. The storage capacitor Cst will maintain the storage voltage of the previous frame.

[0033] Then, during a light-emitting period, such as light-emitting period t22 of the second frame, when scanning of the current row is completed and no data signal Da is input to other rows, the scan line connected to the pixel circuit 10 inputs the row-off signal VGL, the data line connected to the pixel circuit 10 does not input the data signal Da, the logic circuit 15 outputs a second-level signal, the switch circuit 13 connects the second end of the storage capacitor Cst and the control end of the driving transistor SD, and the storage voltage of the storage capacitor Cst, i.e., the storage voltage of the previous frame, is output to the driving transistor SD. At this time, the light emission signal EM is input, the first light emission switch 11 and the second light emission switch 12 are turned on, the anode voltage end, the first light emission switch 11, the driving transistor SD, and the second light emission switch 12 form a current loop, the driving transistor SD generates a current signal and outputs it to the light-emitting unit 20 through the second light emission switch 12, the light-emitting unit 20 displays the grayscale data of the sampling stage and emits light normally, thereby achieving a low refresh rate of the partial picture.

[0034] Alternatively, during the light-emitting period, when other rows are scanned, the data line switches to input data signal Da due to the data signal Da of the other rows. At this time, the scan line connected to the pixel circuit 10 inputs the row shutdown signal VGL, the logic circuit 15 still outputs the second level signal normally, the switch circuit 13 connects the second end of the storage capacitor Cst and the control end of the driving tube SD, and the storage voltage of the previous frame is output to the driving tube SD. At this time, the light emission signal EM is input, the first light emission switch 11 and the second light emission switch 12 are turned on, the anode voltage end, the first light emission switch 11, the driving tube SD and the second light emission switch 12 form a current loop, the driving tube SD generates a current signal and outputs it to the light-emitting unit 20 through the second light emission switch 12, the light-emitting unit 20 displays the grayscale data of the previous frame and emits light normally, and the pixel circuit 10 displays the same display information based on the same data signal Da in the previous and next frames, thereby achieving a low refresh rate of the partial picture.

[0035] When switching to the working mode of the next frame, such as the sampling period t31 of the third frame, when scanning to the row where the pixel circuit 10 is located, the scanning line connected to the pixel circuit 10 inputs the row start signal VGH, and the data line connected to the pixel circuit 10 inputs the data signal Da again, the logic circuit 15 outputs the first level signal, the switch circuit 13 connects the anode voltage terminal and the control terminal of the driving tube SD, and connects the second terminal of the storage capacitor Cst and the output terminal of the driving tube SD. At this time, the light emission signal EM is not input, the first light emission switch 11 and the second light emission switch 12 are turned off, and the refresh input data signal Da is output to the storage capacitor Cst through the driving tube SD and the switch circuit 13, and the pixel circuit 10 completes the sampling of the data signal Da.

[0036] Then, during a light-emitting period, such as the light-emitting period t32 of the third frame, the logic circuit 15 outputs a second level signal, the switch circuit 13 connects the second end of the storage capacitor Cst and the control end of the driving tube SD, and the refreshed storage voltage stored in the storage capacitor Cst is output to the driving tube SD. At this time, the light emission signal EM is input, the first light emission switch 11 and the second light emission switch 12 are turned on, the driving tube SD generates a current signal and outputs it to the light-emitting unit 20 through the second light emission switch 12, and the light-emitting unit 20 displays the grayscale data refreshed in the sampling phase and emits light normally.

[0037] The data signal Da serves as both a data voltage for display and a control signal for the logic circuit. When the pixel circuit 10 of the target local screen is required to be at a low refresh rate, it is possible to cut off the output data signal Da to the data line connected to the pixel circuit 10 when scanning to the row where the pixel circuit 10 is located, so that the pixel circuit 10 can be switched to the maintenance mode, that is, a low refresh rate is achieved.

[0038] Therefore, the pixel circuit 10 can refresh or maintain the data signal Da under the control of the dual signals of the data signal Da and the input row scanning signal Sc, so as to achieve control of the refresh rate of the target pixel circuit.

[0039] When it is necessary to realize a local low refresh rate in the column direction of the display panel 100, such as Figure 2 and Figure 5 As shown, if the pixel circuit 10 in the second column needs to be at a low refresh rate, during row-by-row scanning, the first data line S1 and the third data line S3 can normally input the first data signal Da1 and the third data signal Da3 row by row, and the second data line S2 chooses not to input the second data signal Da2 and is correspondingly pulled down to a low level. In this way, during row-by-row scanning, the pixel circuit 10 in the second column maintains the grayscale data of the previous frame and emits light, achieving a low refresh rate, while the pixel circuit 10 in the first column and the pixel circuit 10 in the third column refresh and input the grayscale data of the next frame and emit light, achieving a high refresh rate, thereby achieving a local low refresh rate in the column direction of the display panel 100.

[0040] When it is necessary to realize a local low refresh rate in the row direction of the display panel 100, such as Figure 2 and Figure 6 As shown, if the pixel circuits 10 in the second row need to be at a low refresh rate, when scanning line by line, when scanning to the pixel circuits 10 in the first row and the pixel circuits 10 in the third row, each data line can normally input the data signal Da, and each pixel circuit 10 in the first row and each pixel circuit 10 in the third row refreshes and inputs the grayscale data of the next frame and emits light, thereby achieving a high refresh rate. When scanning to the pixel circuits 10 in the second row, each data line does not input the data signal Da and is pulled low, and the pixel circuits 10 in the second row maintain the grayscale data of the previous frame and emit light, thereby achieving a low refresh rate, thereby achieving a local low refresh rate in the row direction of the display panel 100.

[0041] And when the individual pixel circuit 10 is required to be at a low refresh rate, such as Figure 2 and Figure 7 As shown, when the pixel circuits 10 in the second row and second column and the pixel circuits 10 in the third row and third column need to have a low refresh rate, when scanning the pixel circuits 10 in the first row, each data line can normally input the data signal Da, and the pixel circuits 10 in the first row refresh the input grayscale data of the next frame and emit light, thereby achieving a high refresh rate.

[0042] When scanning to each pixel circuit 10 in the second row, the first data line S1 and the third data line S3 normally input the first data signal Da1 and the third data signal Da3, and the two pixel circuits 10 in the first column of the second row and the third column of the second row refresh and input the grayscale data of the next frame and emit light, thereby achieving a high refresh rate. The second data line S2 does not input the second data signal Da2 and is pulled low, and the pixel circuit 10 in the second row and the second column maintains the grayscale data of the previous frame and emits light, thereby achieving a low refresh rate.

[0043] When scanning to each pixel circuit 10 in the third row, the first data line S1 and the second data line S2 normally input the first data signal Da1 and the second data signal Da2, and the two pixel circuits 10 in the first column of the third row and the second column of the third row refresh and input the grayscale data of the next frame and emit light, achieving a high refresh rate. The third data line S3 does not input the third data signal Da3 and is pulled low, and the pixel circuit 10 in the third row and the third column maintains the grayscale data of the previous frame and emits light, achieving a low refresh rate, thereby achieving a low refresh rate for individual pixel circuits 10.

[0044] Furthermore, since the light emitting unit 20 may store the charge of the previous frame in each frame, charge accumulation may occur during the frame scanning process, resulting in abnormal grayscale display of the light emitting unit 20 .

[0045] To this end, in an optional embodiment, as Figure 8 As shown, the pixel circuit 10 further includes: Reset switch 16, the first end of the reset switch 16 is used to input the reset signal Vint, the second end of the reset switch 16 is connected to the light-emitting unit 20, the control end of the reset switch 16 is connected to the output end of the logic circuit 15, and the reset switch 16 is triggered to turn on by the first level signal and triggered to turn off by the second level signal.

[0046] The conventional pixel circuit 10 works in the reset period, sampling period and light-emitting period in sequence to complete the reset, sampling and light-emitting operations in sequence. However, in the present application, the reset switch 16 is connected to the output end of the logic circuit 15, and it only needs to work in the sampling period and light-emitting period in sequence to complete the reset, sampling and light-emitting operations.

[0047] During the sampling period of the working mode, the logic circuit 15 outputs a first level signal, the reset switch 16 is turned on and resets the grayscale data of the previous frame received by the light-emitting unit 20. At the same time, the switch circuit 13 refreshes and stores the data signal Da of the next frame and completes the sampling. During the sampling period of the working mode, the reset and sampling operations are completed synchronously.

[0048] Then, in the light-emitting period of the working mode, the logic circuit 15 outputs a second level signal, the reset switch 16 is turned off, and no reset operation is performed.

[0049] And in the sampling period of the sustain mode, the logic circuit 15 outputs the second level signal, the reset switch 16 is turned off, and no reset operation is performed, so that the pixel circuit 10 maintains storing the grayscale data of the previous frame.

[0050] Likewise, during the light-emitting period of the sustain mode, the logic circuit 15 maintains outputting the second level signal, the reset switch 16 is turned off, and no reset operation is performed, so that the pixel circuit 10 lights up according to the current signal corresponding to the grayscale data of the previous frame.

[0051] The first light emitting switch 11 , the second light emitting switch 12 , the switch circuit 13 , the data switch 14 , the logic circuit 15 and the reset switch 16 may be composed of corresponding thin film transistors, and the specific structure is not limited.

[0052] The light emitting unit 20 is a light emitting diode (OLED).

[0053] Compared with the prior art, the embodiments of the present invention have the following advantages: the display panel 100 includes a plurality of scan lines, a plurality of data lines, and an array-arranged pixel circuit 10. The pixel circuit 10 includes a light-emitting unit 20, a light-emitting driving unit, a storage capacitor Cst, a switching circuit 13, a data switch 14, and a logic circuit 15. The logic circuit 15 performs an AND operation on the input row scan signal Sc and the data signal Da, and outputs a corresponding first-level signal or a second-level signal to the switching circuit 13, thereby controlling the switching circuit 13 to store the data signal Da of the next frame in the storage capacitor Cst during a sampling period or to control the storage capacitor Cst to maintain the data signal Da of the previous frame. During the light-emitting period, the light emission signal EM triggers the driving tube SD to output a current signal to drive the light-emitting unit 20 to emit light. By selecting whether to input the data signal Da and the row scan signal Sc to the data line and the scan line, the corresponding pixel circuit 10 can be controlled to maintain the current image or switch the display image, thereby realizing independent control of a single pixel circuit 10 to meet display requirements of different refresh rates.

[0054] Example 2 In an alternative embodiment, if Figure 9 As shown, the first light emitting switch 11 includes a first transistor T1, a second end of the first transistor T1 is connected to the input end of the driving transistor SD, and a control end of the first transistor T1 is used to input the light emitting signal EM; The second optical emission switch 12 includes a second transistor T2, a first end of the second transistor T2 is connected to the output end of the driving tube SD, a control end of the second transistor T2 is connected to the control end of the first transistor T1, a first end of the first transistor T1 is connected to the anode voltage end, and a second end of the second transistor T2 is connected to the light emitting unit 20, or a first end of the first transistor T1 is connected to the light emitting unit 20, and a second end of the second transistor T2 is connected to the cathode voltage end.

[0055] The switch circuit 13 includes a third transistor T3, a fourth transistor T4 and a fifth transistor T5; A first end of the third transistor T3 and a first end of the storage capacitor Cst are connected to the anode voltage terminal, a second end of the third transistor T3 and a second end of the fourth transistor T4 are connected to the control terminal of the driving transistor SD, a first end of the fourth transistor T4 and a first end of the fifth transistor T5 are connected to the second end of the storage capacitor Cst, and the control end of the third transistor T3, the control end of the fourth transistor T4, and the control end of the fifth transistor T5 are connected to the output terminal of the logic circuit 15.

[0056] The logic circuit 15 includes a sixth transistor T6, a seventh transistor T7, an eighth transistor T8 and a ninth transistor T9; A first end of the sixth transistor T6 is used to input a first-level signal, a second end of the sixth transistor T6 is connected to the first end of the seventh transistor T7, a control end of the sixth transistor T6 and a control end of the eighth transistor T8 are connected to the scan line, a second end of the seventh transistor T7, a first end of the eighth transistor T8, and a first end of the ninth transistor T9 are connected to form an output end of the logic circuit 15, a control end of the seventh transistor T7 and a control end of the ninth transistor T9 are connected to the data line, and a second end of the eighth transistor T8 and a second end of the ninth transistor T9 are connected and used to input a second-level signal.

[0057] The data switch 14 includes a tenth transistor T10 , a first terminal of the tenth transistor T10 is used to input a data signal Da, a second terminal of the tenth transistor T10 is connected to an input terminal of the driving transistor SD, and a control terminal of the tenth transistor T10 is used to input a row scan signal Sc.

[0058] The reset switch 16 includes an eleventh transistor T11 , a first terminal of the eleventh transistor T11 is used to input the reset signal Vint, a second terminal of the eleventh transistor T11 is connected to the light emitting unit 20 , and a control terminal of the eleventh transistor T11 is connected to the output terminal of the logic circuit 15 .

[0059] In this embodiment, based on the connection position of the light-emitting driving unit 101, the first transistor T1 and the second transistor T2 can be connected to the anode voltage terminal and the light-emitting unit 20, respectively. In the working mode, taking the driving tube SD as a P-channel thin film transistor as an example, during the sampling period of the pixel circuit 10, when scanning to the row where the pixel circuit 10 is located, the scan line connected to the pixel circuit 10 inputs the row start signal VGH, and the data line connected to the pixel circuit 10 inputs the data signal Da, the sixth transistor T6 and the seventh transistor T7 are turned on, the eighth transistor T8 and the ninth transistor T9 are turned off, and the logic circuit 15 outputs a first level signal. In an optional embodiment, the first level signal is the row off signal VGL, and the second level signal is the row start signal VGH. At the same time, the tenth transistor T10 is turned on, and the data signal The data signal Da is transmitted to the input terminal of the driving tube SD via the tenth transistor T10. The first level signal is output to the switching circuit 13. The third transistor T3 and the fifth transistor T5 are turned on, and the fourth transistor T4 is turned off. The switching circuit 13 connects the anode voltage terminal and the control terminal of the driving tube SD, and connects the second terminal of the storage capacitor Cst and the output terminal of the driving tube SD. At this time, no light emission signal EM is input, the first transistor T1 and the second transistor T2 are turned off, and the data signal Da is output to the storage capacitor Cst via the driving tube SD and the fifth transistor T5. The anode voltage terminal, the storage capacitor Cst, the fifth transistor T5, the driving tube SD, and the data line form a loop. The storage voltage Vcst of the storage capacitor Cst equals Vdata + Vth, and the pixel circuit 10 completes the sampling of the data signal Da.

[0060] At the same time, during the sampling period, the eleventh transistor T11 of the reset switch 16 receives the first level signal and is triggered to turn on, and the reset signal Vint resets the light emitting unit 20. During the sampling period of the working mode, the reset and sampling operations are completed synchronously.

[0061] Then, during the light-emitting period, when scanning of the current row is completed and no data signal Da is input to other rows, the scan line connected to the pixel circuit 10 inputs the row-off signal VGL, and the data line connected to the pixel circuit 10 does not input the data signal Da. The sixth transistor T6 and the seventh transistor T7 are turned off, and the eighth transistor T8 and the ninth transistor T9 are turned on and output a second-level signal. At this time, the tenth transistor T10 is turned off, and no data signal Da is input. The fourth transistor T4 receives the second-level signal and triggers the connection between the second end of the storage capacitor Cst and the control end of the driving transistor SD. The stored voltage of the storage capacitor Cst is output to the driving transistor SD. At this time, the light emission signal EM is input, the first transistor T1 and the second transistor T2 are turned on, and the anode voltage terminal, the first transistor T1, the driving transistor SD, and the second transistor T2 form a current loop. The driving transistor SD generates a current signal and outputs it to the light-emitting unit 20 through the second transistor T2. The light-emitting unit 20 displays the grayscale data of the sampling stage and emits light normally, achieving a high refresh rate.

[0062] At the same time, the eleventh transistor T11 of the reset switch 16 is triggered to turn off, and no reset operation is performed.

[0063] Alternatively, during the light-emitting period, when other rows are scanned, the data line switches to input data signal Da due to the data signal Da of the other rows. At this time, the scan line connected to the pixel circuit 10 inputs the row shutdown signal VGL, the sixth transistor T6 and the ninth transistor T9 are turned off, the seventh transistor T7 and the eighth transistor T8 are turned on, the logic circuit 15 still outputs the second level signal normally, the fourth transistor T4 connects the second end of the storage capacitor Cst and the control end of the driving tube SD, and the storage voltage of the storage capacitor Cst is output to the driving tube SD. At this time, the light emission signal EM is input, the first transistor T1 and the second transistor T2 are turned on, the anode voltage end, the first transistor T1, the driving tube SD and the second transistor T2 form a current loop, the driving tube SD generates a current signal and outputs it to the light-emitting unit 20 through the second transistor T2, the light-emitting unit 20 displays the grayscale data of the sampling stage and emits light normally, achieving a high refresh rate.

[0064] At the same time, the eleventh transistor T11 of the reset switch 16 is triggered to turn off, and no reset operation is performed.

[0065] When switching to the sustain mode of the next frame, during the sampling period of the pixel circuit 10, when scanning to the row where the pixel circuit 10 is located, the scan line connected to the pixel circuit 10 inputs the row start signal VGH, and the data line connected to the pixel circuit 10 does not input the data signal Da. At this time, the data line is in a low level state, the sixth transistor T6 and the ninth transistor T9 are turned on, the seventh transistor T7 and the eighth transistor T8 are turned off, the logic circuit 15 outputs a second level signal, the fourth transistor T4 is turned on and connects the second end of the storage capacitor Cst and the control end of the driving tube SD. At this time, no light emission signal EM is input, the first transistor T1 and the second transistor T2 are turned off, and the data signal Da stored in the storage capacitor Cst in the previous frame cannot be output to the storage capacitor Cst through the driving tube SD and the switching circuit 13 or be refreshed by the new data signal Da. The storage capacitor Cst will maintain the storage voltage of the previous frame.

[0066] At the same time, the eleventh transistor T11 of the reset switch 16 is triggered to turn off, and no reset operation is performed.

[0067] Then, during the light-emitting period, when scanning of the current row is completed and no data signal Da is input to other rows, the scan line connected to the pixel circuit 10 inputs the row-off signal VGL, and the data line connected to the pixel circuit 10 does not input the data signal Da. The sixth transistor T6 and the seventh transistor T7 are turned off, and the eighth transistor T8 and the ninth transistor T9 are turned on and output a second-level signal. At this time, the tenth transistor T10 is turned off, and no data signal Da is input. The fourth transistor T4 receives the second-level signal and triggers the connection between the second end of the storage capacitor Cst and the control end of the driving transistor SD. The stored voltage of the storage capacitor Cst is output to the driving transistor SD. At this time, the light emission signal EM is input, the first transistor T1 and the second transistor T2 are turned on, and the anode voltage terminal, the first transistor T1, the driving transistor SD, and the second transistor T2 form a current loop. The driving transistor SD generates a current signal and outputs it to the light-emitting unit 20 through the second transistor T2. The light-emitting unit 20 displays the grayscale data of the sampling stage and emits light normally, achieving a low refresh rate for the partial screen.

[0068] Alternatively, during the light-emitting period, when scanning to other rows, the data line switches to input the data signal Da due to the data signal Da of the other rows. At this time, the scan line connected to the pixel circuit 10 inputs the row off signal VGL, the sixth transistor T6 and the ninth transistor T9 are turned off, the seventh transistor T7 and the eighth transistor T8 are turned on, the logic circuit 15 still outputs the second level signal normally, the fourth transistor T4 is connected to the second end of the storage capacitor Cst and the control end of the driving transistor SD, and the storage voltage of the previous frame is output to the driving transistor SD. At this time, the light emission signal EM is input, the first transistor T1 and the second transistor T2 are turned on, the anode voltage end, the first transistor T1, the driving transistor SD, and the second transistor T2 form a current loop, the driving transistor SD generates a current signal and outputs it to the light-emitting unit 20 through the second transistor T2. The light-emitting unit 20 displays the grayscale data of the previous frame and emits light normally. The pixel circuit 10 displays the same display information based on the same data signal Da in the previous and next frames, thereby achieving a low refresh rate of the partial picture.

[0069] Corresponding to the above signal types and the on-off modes of each transistor, in an optional embodiment, the first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9 and the eleventh transistor T11 are P-channel thin film transistors, and the fourth transistor T4, the sixth transistor T6 and the tenth transistor T10 are N-channel thin film transistors.

[0070] Example 3 A second aspect of the embodiment of the present invention provides a driving method of a display panel 100, which is used to drive the display panel 100. Figure 10 As shown, the driving method of the display panel 100 includes: S10, determining whether the image content of the next frame of the target partial image of the display panel 100 has changed; S20, when the image content of the next frame of the target partial image remains unchanged, switching to the hold mode, and during the next frame scan drive, outputting the corresponding row start signal VGH and not outputting the data signal Da to the target pixel circuit corresponding to the target partial image, and controlling the storage capacitor Cst of the target pixel circuit to maintain the data signal Da of the previous frame; S30. When the picture content of the next frame of the target partial picture changes, switch to the working mode. During the next frame scan drive, output the corresponding data signal Da and the row start signal VGH to the target pixel circuit corresponding to the target partial picture, and control the storage capacitor Cst of the target pixel circuit to input the data signal Da of the current frame.

[0071] In this embodiment, when the target local screen displays a static screen, the characteristic values ​​of the subsequent screens can be analyzed to determine whether the target local screen has changed. When it is determined that the display content of the target local screen remains unchanged, the target local screen has a low refresh rate. At this time, it is switched to the maintenance mode. When scanning line by line, it can be selected not to output the data signal Da to the pixel circuit 10 corresponding to the target local screen, and the pixel circuit 10 of the target local screen can be switched to the maintenance mode, that is, a low refresh rate is achieved.

[0072] When it is determined that the target local picture changes in the next frame, the target local picture has a high refresh rate. At this time, it switches to the working mode. During line-by-line scanning, the output data signal Da can be selected to the pixel circuit 10 corresponding to the target local picture, and the pixel circuit 10 of the target local picture can be switched to the working mode, that is, a high refresh rate is achieved.

[0073] The pixel circuit 10 can refresh or maintain the data signal Da under the control of the dual signals of the data signal Da and the input row scanning signal Sc, so as to achieve control of the refresh rate of the target pixel circuit.

[0074] For example, when it is necessary to realize a local low refresh rate and a local high refresh rate in the column direction of the display panel 100, such as Figure 2 and Figure 5 As shown, if the pixel circuit 10 in the second column needs to be at a low refresh rate, during row-by-row scanning, the first data line S1 and the third data line S3 can normally input the first data signal Da1 and the third data signal Da3 row by row, and the second data line S2 chooses not to input the second data signal Da2 and is correspondingly pulled down to a low level. In this way, during row-by-row scanning, the pixel circuit 10 in the second column maintains the grayscale data of the previous frame and emits light, thereby achieving a low refresh rate in the column direction, while the pixel circuit 10 in the first column and the pixel circuit 10 in the third column refresh and input the grayscale data of the next frame and emit light, thereby achieving a high refresh rate in the column direction, thereby achieving different refresh rates in the column direction of the display panel 100.

[0075] When it is necessary to realize a local low refresh rate in the row direction of the display panel 100, such as Figure 2 and Figure 6 As shown, if the pixel circuits 10 in the second row need to be at a low refresh rate, when scanning row by row, when scanning to the pixel circuits 10 in the first row and the pixel circuits 10 in the third row, each data line can normally input the data signal Da, and each pixel circuit 10 in the first row and each pixel circuit 10 in the third row refreshes and inputs the grayscale data of the next frame and emits light, thereby achieving a high refresh rate in the row direction. When scanning to the pixel circuits 10 in the second row, each data line does not input the data signal Da and is pulled low, and the pixel circuits 10 in the second row maintain the grayscale data of the previous frame and emits light, thereby achieving a low refresh rate in the row direction, thereby achieving different refresh rates in the row direction of the display panel 100.

[0076] When scanning to each pixel circuit 10 in the second row, the first data line S1 and the third data line S3 normally input the first data signal Da1 and the third data signal Da3, and the two pixel circuits 10 in the first column of the second row and the third column of the second row refresh and input the grayscale data of the next frame and emit light, achieving a high refresh rate. The second data line S2 does not input the second data signal Da2 and is pulled low, and the pixel circuit 10 in the second column of the second row maintains the grayscale data of the previous frame and emits light, achieving a low refresh rate, thereby achieving a low refresh rate for individual pixel circuits 10.

[0077] When scanning to each pixel circuit 10 in the third row, the first data line S1 and the second data line S2 normally input the first data signal Da1 and the second data signal Da2, and the two pixel circuits 10 in the first column of the third row and the second column of the third row refresh and input the grayscale data of the next frame and emit light, achieving a high refresh rate. The third data line S3 does not input the third data signal Da3 and is pulled low, and the pixel circuit 10 in the third row and the third column maintains the grayscale data of the previous frame and emits light, achieving a low refresh rate, thereby achieving a low refresh rate for individual pixel circuits 10.

[0078] In an alternative embodiment, if Figure 11 As shown, S20 specifically includes: S21 . During the sampling period of the sustain mode, the row start signal VGH is output to the scan line, and the data signal Da is not output to the data line.

[0079] During the sampling period of the pixel circuit 10, when scanning to the row where the pixel circuit 10 is located, the scan line connected to the pixel circuit 10 inputs the row start signal VGH, and the data line connected to the pixel circuit 10 does not input the data signal Da. At this time, the data line is in a low level state, the logic circuit 15 of the pixel circuit 10 outputs a second level signal, and the switch circuit 13 of the pixel circuit 10 connects the second end of the storage capacitor Cst and the control end of the drive tube SD. At this time, the pixel circuit 10 does not input the light emission signal EM, and the storage capacitor Cst will maintain the storage voltage of the previous frame.

[0080] S22 . In the light emitting period of the sustain mode, the row start signal VGH is not output to the scan line, and the data signal Da of the next frame is output to the data line or the data signal Da is not output to the data line.

[0081] During the light-emitting period, when the scanning of the current row is completed and the data signal Da is not input to other rows or the input data signal Da is switched due to the data signal Da of other rows, at this time, the scanning line connected to the pixel circuit 10 inputs the row shutdown signal VGL, the logic circuit 15 of the pixel circuit 10 outputs the second level signal, and the switching circuit 13 of the pixel circuit 10 connects the second end of the storage capacitor Cst and the control end of the driving tube SD. The storage voltage of the storage capacitor Cst, that is, the storage voltage of the previous frame, is output to the driving tube SD. At this time, the light emission signal EM is input, the driving tube SD generates a current signal and outputs it to the light-emitting unit 20 through the second light emission switch 12. The light-emitting unit 20 displays the grayscale data of the sampling stage and emits light normally, thereby achieving a low refresh rate of the local picture.

[0082] In an alternative embodiment, if Figure 12 As shown, S30 includes: S31, during the sampling period of the working mode, outputting a row start signal VGH to the scan line and outputting a data signal Da to the data line; S32 . In the light-emitting period of the working mode, the row start signal VGH is not output to the scan line, and the data signal Da of the next frame is output to the data line or the data signal Da is not output to the data line.

[0083] In the working mode, during the sampling period of the pixel circuit 10, such as the sampling period of the first frame, when scanning to the row where the pixel circuit 10 is located, the scanning line connected to the pixel circuit 10 inputs the row start signal VGH, the data line connected to the pixel circuit 10 inputs the data signal Da, the logic circuit 15 of the pixel circuit 10 outputs a first level signal, the switching circuit 13 of the pixel circuit 10 connects the anode voltage terminal and the control terminal of the driving tube SD, and connects the second terminal of the storage capacitor Cst and the output terminal of the driving tube SD. At this time, the light emission signal EM is not input, the storage voltage Vcst of the storage capacitor Cst = Da + Vth, and the pixel circuit 10 completes the sampling of the data signal Da.

[0084] Then, during the light-emitting period, when the scanning of the current row is completed and no data signal Da is input to other rows, the scan line connected to the pixel circuit 10 inputs the row-off signal VGL, the data line connected to the pixel circuit 10 does not input the data signal Da, or the data line is switched to input the data signal Da due to the data signal Da of other rows, the logic circuit 15 outputs a second-level signal, the switch circuit 13 connects the second end of the storage capacitor Cst and the control end of the driving tube SD, and the stored voltage of the storage capacitor Cst is output to the driving tube SD. At this time, the light emission signal EM is input, the first light emission switch 11 and the second light emission switch 12 are turned on, and the anode voltage end, the first light emission switch 11, the driving tube SD, and the second light emission switch 12 form a current loop. The driving tube SD generates a current signal and outputs it to the light-emitting unit 20 through the second light emission switch 12. The light-emitting unit 20 displays the grayscale data of the sampling stage and emits light normally, achieving a high refresh rate.

[0085] Alternatively, during the light-emitting period, when other rows are scanned, the data line switches the input data signal Da due to the data signal Da of the other rows. At this time, the scan line connected to the pixel circuit 10 inputs the row shutdown signal VGL, and the logic circuit 15 still outputs the second level signal normally. The switching circuit 13 connects the second end of the storage capacitor Cst and the control end of the driving tube SD, and the storage voltage of the storage capacitor Cst is output to the driving tube SD. At this time, the light emission signal EM is input, the driving tube SD generates a current signal and outputs it to the light-emitting unit 20 through the second light emission switch 12. The light-emitting unit 20 displays the grayscale data of the sampling stage and emits light normally, thereby achieving a high refresh rate.

[0086] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0087] Example 4 like Figure 13 As shown, a third aspect of an embodiment of the present invention provides a driving circuit 200 for a display panel, including a source driving circuit 210, a gate driving circuit 220, and a timing controller 230. The source driving circuit 210 is respectively connected to a plurality of data lines of the display panel 100, and the gate driving circuit 220 is respectively connected to a plurality of scan lines of the display panel 100. The timing controller 230 is connected to the source driving circuit 210 and the gate driving circuit 220 respectively. The timing controller 230 is used to output control signals to the source driving circuit 210 and the gate driving circuit 220 to implement the above driving method of the display panel 100.

[0088] In this embodiment, the source driving circuit 210 is used to control the output of the data signal Da or not to output the data signal Da, and the gate driving circuit 220 is used to control the output of the row-on signal VGH and the row-off signal VGL row by row.

[0089] When the target partial screen displays a static image, the timing controller 230 analyzes the characteristic values ​​of the subsequent images to determine whether the target partial screen has changed. When it is determined that the display content of the target partial screen remains unchanged, the target partial screen has a low refresh rate. At this time, it switches to the maintenance mode. The timing controller 230 controls the source driver circuit 210 not to output the data signal Da to the target pixel circuit of the target partial screen during the sampling period, thereby controlling the target pixel circuit to maintain the data signal Da and display image of the previous frame to achieve a low refresh rate.

[0090] When it is determined that the target partial picture changes in the next frame, the target partial picture has a high refresh rate. At this time, it switches to the working mode, and the timing controller 230 controls the source driver circuit 210 to output the data signal Da to the target pixel circuit of the target partial picture during the sampling period, thereby controlling the target pixel circuit to switch to the data signal Da and display picture of the next frame to achieve a high refresh rate.

[0091] Example 5 A fourth aspect of the embodiments of the present invention provides a display device, such as Figure 13 As shown, the display device includes a display panel 100 and a display panel driving circuit 200. The specific structures of the display panel 100 and the display panel driving circuit 200 refer to the above embodiments. Since the present display device adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought by the technical solutions of the above embodiments, which will not be described in detail here. Among them, the display panel driving circuit 200 is connected to the display panel 100.

[0092] The embodiments described above are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention, and should all be included in the scope of protection of the present invention.

Claims

1. A display panel, characterized in that: A pixel circuit comprising a plurality of scan lines, a plurality of data lines and an array arrangement, wherein the pixel circuit comprises: Light-emitting unit; a light-emitting driving unit connected in series with the light-emitting unit between the anode voltage terminal and the cathode voltage terminal, the light-emitting driving unit comprising a first light-emitting switch, a driving tube, and a second light-emitting switch connected in series in sequence, the driving tube being configured to convert a data signal input during a sampling period into a current signal, the first light-emitting switch and the second light-emitting switch being configured to be triggered to conduct during a light-emitting period by the light-emitting signal to output the current signal; a storage capacitor, wherein a first terminal of the storage capacitor is connected to the anode voltage terminal or the cathode voltage terminal; a switch circuit, connected to the second end of the storage capacitor, the anode voltage end, the control end and the output end of the driver transistor, respectively; the switch circuit is triggered by a first level signal to connect the anode voltage end and the control end of the driver transistor and the second end of the storage capacitor and the output end of the driver transistor, and is triggered by a second level signal to connect the second end of the storage capacitor and the control end of the driver transistor; a data switch connected to the data line, the scan line, and the input end of the driver tube, respectively; the data switch is triggered by a row-on signal to turn on and transmit the data signal on the data line to the driver tube, and is triggered by a row-off signal to turn off; A logic circuit is respectively connected to the data line, the scan line and the switching circuit, and is used to trigger the output of the first level signal to the switching circuit when the row start signal and the data signal are received at the same time, and to trigger the output of the second level signal to the switching circuit when the row start signal and the data signal are not received at the same time.

2. The display panel according to claim 1, wherein The first light emitting switch includes a first transistor, a second end of the first transistor is connected to the input end of the driving transistor, and a control end of the first transistor is used to input the light emitting signal; The second light emitting switch includes a second transistor, the first end of the second transistor is connected to the output end of the driving tube, the control end of the second transistor is connected to the control end of the first transistor, the first end of the first transistor is connected to the anode voltage end, and the second end of the second transistor is connected to the light emitting unit, or the first end of the first transistor is connected to the light emitting unit, and the second end of the second transistor is connected to the cathode voltage end.

3. The display panel according to claim 1, wherein The switch circuit includes a third transistor, a fourth transistor and a fifth transistor; The first end of the third transistor and the first end of the storage capacitor are connected to the anode voltage end, the second end of the third transistor and the second end of the fourth transistor are connected to the control end of the driving tube, the first end of the fourth transistor and the first end of the fifth transistor are connected to the second end of the storage capacitor, and the control end of the third transistor, the control end of the fourth transistor, and the control end of the fifth transistor are connected to the output end of the logic circuit.

4. The display panel according to claim 1, wherein: The logic circuit includes a sixth transistor, a seventh transistor, an eighth transistor and a ninth transistor; The first end of the sixth transistor is used to input the first level signal, the second end of the sixth transistor is connected to the first end of the seventh transistor, the control end of the sixth transistor and the control end of the eighth transistor are connected to the scan line, the second end of the seventh transistor, the first end of the eighth transistor and the first end of the ninth transistor are connected to form the output end of the logic circuit, the control end of the seventh transistor and the control end of the ninth transistor are connected to the data line, and the second end of the eighth transistor is connected to the second end of the ninth transistor and is used to input the second level signal.

5. The display panel according to any one of claims 1 to 4, wherein: The pixel circuit further includes: A reset switch, wherein the first end of the reset switch is used to input a reset signal, the second end of the reset switch is connected to the light-emitting unit, the control end of the reset switch is connected to the output end of the logic circuit, and the reset switch is triggered to turn on by the first level signal and triggered to turn off by the second level signal.

6. A method for driving a display panel, for driving the display panel according to any one of claims 1 to 5, characterized in that: The driving method of the display panel includes: Determining whether the image content of the next frame of the target partial image of the display panel changes; When the image content of the next frame of the target partial image remains unchanged, switching to the hold mode, and during the next frame scan drive, outputting the corresponding row start signal and not outputting the data signal to the target pixel circuit corresponding to the target partial image, and controlling the storage capacitor of the target pixel circuit to maintain the data signal of the previous frame; When the picture content of the next frame of the target partial picture changes, it switches to the working mode, and during the next frame scanning drive, outputs the corresponding data signal and the row start signal to the target pixel circuit corresponding to the target partial picture, and controls the storage capacitor of the target pixel circuit to input the data signal of the current frame.

7. The method for driving a display panel according to claim 6, wherein: When the picture content of the next frame of the target partial picture remains unchanged, the circuit switches to the maintenance mode, and outputs the corresponding row start signal and does not output the data signal to the target pixel circuit corresponding to the target partial picture during the next frame scan drive, including: During a sampling period of the sustain mode, a row start signal is output to the scan line, and no data signal is output to the data line; During the light emission period of the sustain mode, a row start signal is not output to the scan line, and a data signal of a next frame is output to the data line or no data signal is output to the data line.

8. The method for driving a display panel according to claim 6, wherein: When the picture content of the next frame of the target partial picture changes, the circuit switches to the working mode, and outputs the corresponding data signal and the row start signal to the target pixel circuit corresponding to the target partial picture during the next frame scan drive, including: During a sampling period of the working mode, outputting a row start signal to the scan line and outputting a data signal to the data line; During the light emitting period of the operation mode, a row start signal is not output to the scan line, and a data signal of the next frame is output to the data line or no data signal is output to the data line.

9. A driving circuit for a display panel, characterized in that: It includes a source driving circuit, a gate driving circuit and a timing controller, wherein the source driving circuit is respectively connected to a plurality of data lines of the display panel, and the gate driving circuit is respectively connected to a plurality of scan lines of the display panel; The timing controller is connected to the source driving circuit and the gate driving circuit respectively, and is used to output control signals to the source driving circuit and the gate driving circuit to implement the driving method of the display panel according to any one of claims 6 to 8.

10. A display device, characterized in that: The device comprises the display panel according to any one of claims 1 to 5 and the driving circuit of the display panel according to claim 9, wherein the driving circuit of the display panel is connected to the display panel.

Images