Storage device, preparation method and electronic device

Abstract

An embodiment of the present application provides a storage device, a preparation method and an electronic device, including a first wafer, a second wafer and a third wafer, the third wafer including a control unit; the first wafer including a first storage cell group, the first storage cell group including a plurality of first storage cells, the first storage cells being connected to the control unit via corresponding first word lines, the first control unit including a first channel column; the second wafer including a second storage cell group, the second storage cell group including a plurality of second storage cells, the second storage cells being connected to the control unit via corresponding second word lines, and the second control unit including a second communication column.

Description

Technical Field

[0001] The present application belongs to the field of storage technology, and specifically relates to a storage device, a preparation method and an electronic device. Background Art

[0002] With the development of flash memory technology, the characteristic size of two-dimensional flash memory (2D NAND) has reached 14nm, and it is becoming increasingly difficult to further shrink it. In order to further increase storage density, we have now turned to three-dimensional flash memory (3D NAND) through structural changes.

[0003] Three-dimensional flash memory (3D NAND) can effectively circumvent the problem of feature size miniaturization of two-dimensional flash memory. Further improvement of storage density can be achieved through higher stacking height. However, as the stacking height increases, the memory cell channel will become higher and higher. Since the memory cell channel is made of polysilicon material, its resistance is relatively large. Higher stacking height will further increase the channel resistance and reduce the channel current, making data reading increasingly difficult. Summary of the invention

[0004] The present application aims to provide a storage device, a preparation method and an electronic device, which at least solve the problem in the background technology that the channel resistance increases and the communication current is small due to the high stacking height, making data reading difficult.

[0005] In order to solve the above technical problems, this application is implemented as follows:

[0006] In a first aspect, an embodiment of the present application provides a storage device, including a first wafer, a second wafer, and a third wafer.

[0007] The third wafer includes a control unit;

[0008] The first wafer includes a first storage cell group, the first storage cell group includes a plurality of first storage cells, the first storage cells are connected to the control unit through corresponding first word lines, and the first control unit includes a first channel column;

[0009] The second wafer includes a second storage cell group, the second storage cell group includes a plurality of second storage cells, the second storage cells are connected to the control unit via corresponding second word lines, and the second control unit includes a second communication column;

[0010] Wherein, when reading a target storage unit in a target wafer, the control unit controls a target channel column corresponding to the target storage unit to be turned on, and controls other channel columns except the target channel column to be turned off; the target wafer is a first wafer or a second wafer.

[0011] In a second aspect, an embodiment of the present application provides an electronic device, which includes a storage device, and the storage device is the storage device described in the first aspect above.

[0012] In a third aspect, an embodiment of the present application provides a method for preparing a storage device, which includes:

[0013] Providing a first wafer, forming a first memory cell group on the first wafer, wherein the first memory cell group includes a plurality of first memory cells, the first memory cells include first channel pillars, and the first memory cells have corresponding first word lines;

[0014] Providing a second wafer, forming a second memory cell group on the second wafer, wherein the second memory cell group includes a plurality of second memory cells, wherein the first memory cell is composed of a second channel column, and the first memory cell has a corresponding second word line;

[0015] providing a third wafer, and forming a control unit on the third wafer;

[0016] The first wafer, the second wafer and the third wafer are bonded together.

[0017] In an embodiment of the present application, based on three wafers, the channel column is split into a first channel column and a second channel column, the first channel column forms a first storage unit, the second channel column forms a second storage unit, a plurality of first storage cells constitute a first storage cell group arranged on the first wafer, a plurality of second storage cells constitute a second storage cell group arranged on the second wafer, and the third wafer is provided with a control unit, the first storage unit and the second storage unit are both connected to the control unit through corresponding word lines, so that the control unit can read the data in the two storage cells at the same time, effectively reducing the series resistance of the reading circuit and improving the reading capability.

[0018] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0020] Figure 1 A schematic diagram of the structure of a storage device provided by an embodiment of the present invention;

[0021] Figure 2a and Figure 2b A schematic structural diagram of a first channel column and a second channel column provided in an embodiment of the present invention;

[0022] Figure 3A schematic diagram of the structure of an electronic device provided by an embodiment of the present invention;

[0023] Figure 4 A schematic flow chart of a method for preparing a storage device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0024] Embodiments of the present invention will be described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0025] The features of the terms "first" and "second" in the specification and claims of this application may include one or more of the features explicitly or implicitly. In addition, "and / or" in the specification and claims represents at least one of the connected objects.

[0026] In the description of the present invention, it is necessary to understand that the orientations or positional relationships indicated by the terms "center", "row", "column", "up", "down", "periphery", etc. are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0027] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the term "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0028] An embodiment of the present invention relates to a storage device, which may be a three-dimensional flash memory storage device.

[0029] like Figure 1 , which is a schematic diagram of a storage device 10 provided in an embodiment of the present invention. The storage device 10 includes a first wafer 110 , a second wafer 120 and a third wafer 130 .

[0030] The third wafer 130 includes a control unit 131, which is a control circuit required for the three-dimensional flash memory storage device, and the control circuit may be a read control circuit. The control unit 131 can read the data stored in the storage units in the first wafer 110 and the second wafer 120 respectively.

[0031] The first wafer 110 includes a first memory cell group, the first memory cell group includes a plurality of first memory cells 111 , the first memory cells 111 are connected to the control unit 131 through corresponding first word lines, and the first memory cells 131 include first channel pillars.

[0032] The first channel column includes a first upper selection switch, a first switch group and a first lower selection switch connected in series in sequence, and the first switch group includes a plurality of first switches connected in series. The first switch may be a MOS tube switch.

[0033] like Figure 1 , Figure 2a and Figure 2b As shown, the first wafer 110 includes a first storage unit group, and the first storage unit group includes a plurality of first storage units 111, for example, including Figure 1 , Figure 2a and Figure 2b The first storage unit 111a shown in the figure is composed of a first channel column. The first channel column includes an upper selection switch BSG, N+1 MOS tube switches (where N is the stacking height of the first storage unit 111a) connected in series from top to bottom, and a lower selection switch TSG. In addition, the first storage unit 111a is connected to the control unit 131 through the corresponding first word line BL1.

[0034] The second wafer 120 includes a second storage cell group 121 . The second storage cell group includes a plurality of second storage cells 121 . The second storage cells 121 are connected to the control unit 131 through corresponding second word lines. The second storage cells 121 are composed of second communication columns.

[0035] The second channel column includes a second upper selection switch, a second switch group and a second lower selection switch connected in series in sequence, and the second switch group includes a plurality of second switches connected in series. The second switch may be a MOS tube switch.

[0036] like Figure 1 , Figure 2a and Figure 2b As shown, the second wafer 120 includes a second storage unit group, and the second storage unit group includes a plurality of second storage units 121, which may include Figure 1 , Figure 2a and Figure 2bThe second storage unit 121a shown in the figure is composed of a second channel column. The second channel column includes an upper selection switch BSG, N+1 MOS tube switches (where N is the stacking height of the second storage unit 131a) connected in series from top to bottom, and a lower selection switch TSG. In addition, the second storage unit 121a is connected to the control unit 131 through the corresponding second word line BL2.

[0037] It is understandable that the storage device 10 is composed of three major parts, namely, the first wafer 110, the second wafer 120 and the third wafer 130, which are bonded together by a wafer bonding process. Among them, the third wafer 130 forms a control unit structure necessary for the three-dimensional flash memory storage device, and the first wafer 110 and the second wafer 120 form a basic storage unit structure.

[0038] The first storage cell group and the second storage cell group are mirror-symmetric, that is, each first storage cell 111 in the first storage cell group can find its mirror-symmetric second storage cell 121 in the second storage cell group. In addition, the first storage cell 111 and the second storage cell 121 with mirror-symmetry therewith are connected to a common source. In addition, the first word line corresponding to the first storage cell 111 and the second word line corresponding to the second storage cell 121 with mirror-symmetry therewith form a common word line, and the first storage cell 111 and the second storage cell 121 with mirror-symmetry therewith are both connected to the control unit 131 through the common word line.

[0039] like Figure 1 , Figure 2a and Figure 2b As shown, the first storage cell 111a and the second storage cell 121a are mirror-symmetric. In addition, the common source ACS1 of the first storage cell 111a and the common source ACS2 of the second storage cell 121a are connected to serve as the common source ACS. The first word line BL1 corresponding to the first storage cell 111a and the second word line BL2 corresponding to the second storage cell 131a are connected and are led out through the peripheral word line to form a common word line 140 (BL). That is, the first storage cell 111a and the second storage cell 121a are both connected to the control unit 131 through the common word line, so that the control unit 131 can read the data in the first storage cell 111a and the second storage cell 121a at the same time.

[0040] It can be understood that, through the storage device 10 in this embodiment, it is equivalent to splitting the channel column with a higher stacking height into two channel columns with a lower stacking height. In the prior art, the storage device includes two wafers, one of which is used to form a control unit, and the other wafer is used to form a storage unit group, and each storage unit in the storage unit group is formed by a corresponding channel column. In this embodiment, the channel column corresponding to each storage unit is split into two channel columns, for example, a 128-layer channel stack can be split into two 64-layer channel stacks. The first channel column is made on the first wafer as the first storage unit, and the second channel column is made on the second wafer as the second storage unit. The structure is then made mirror-symmetrical by wafer bonding, and the position of the word line connected to the control unit is placed between the first channel column and the corresponding second channel column, so that when the control unit reads any storage unit, its resistance is equivalent to half of the entire channel length, which effectively reduces the series resistance on the reading circuit, increases the reading current, and improves the reading capability of the three-dimensional flash memory storage device.

[0041] In this embodiment, when reading a target storage unit in a target wafer, the control unit 131 controls the target channel column corresponding to the target storage unit to be turned on, and controls all other channel columns except the target channel column to be turned off; the target wafer is the first wafer or the second wafer.

[0042] In an example, when it is necessary to read any first storage unit 111 in the first wafer 110 , the first channel column corresponding to the first storage unit 111 may be turned on, and the other channel columns except the first channel column may be controlled to be turned off.

[0043] In this example, Figure 2a As shown, when the first storage unit 111a in the first wafer 110 needs to be read, the upper selection switch BSG and the lower selection switch TSG in the first channel column corresponding to the first storage unit 111a can be controlled to be closed, and the other upper selection switches and the lower selection switches are all disconnected, so that the first channel column corresponding to the first storage unit 111a is turned on, and the other channel columns are all disconnected. Here, a read voltage V can be applied to the selected MOS switch in the first channel column corresponding to the first storage unit 111a. read , applying a conduction voltage V to other MOS switches in the first channel column corresponding to the first storage unit 111a pass , where the read voltage V read Usually less than the on-state voltage V pass The read current is read by the control unit 131 through the first channel column corresponding to the first storage unit 111 a in the first wafer 110 .

[0044] In an example, when it is necessary to read any second storage unit 121 in the second wafer 120 , the second channel column corresponding to the second storage unit 121 may be turned on, and other channel columns except the second channel column may be controlled to be turned off.

[0045] In this example, Figure 2b As shown, when the second storage unit 121a in the second wafer 120 needs to be read, the upper selection switch BSG and the lower selection switch TSG in the second channel column corresponding to the second storage unit 121a can be controlled to be closed, and the other upper selection switches and the lower selection switches are all disconnected, so that the second channel column corresponding to the second storage unit 121a is turned on. Here, a read voltage V can be applied to the selected MOS switch in the second channel column corresponding to the second storage unit 121a. read , applying a conduction voltage V to other MOS switches in the second channel column corresponding to the second storage unit 121a pass , where the read voltage V read Usually less than the on-state voltage V pass The read current is read by the control unit 131 through the second channel column corresponding to the second storage unit 121 a in the second wafer 120 .

[0046] In this embodiment, based on three wafers, the channel column is split into a first channel column and a second channel column, the first channel column forms a first storage unit, the second channel column forms a second storage unit, a plurality of first storage cells constitute a first storage cell group arranged on the first wafer, a plurality of second storage cells constitute a second storage cell group arranged on the second wafer, and the third wafer is provided with a control unit, the first storage unit and the second storage unit are both connected to the control unit through corresponding word lines, so that the control unit can read the data in the two storage cells at the same time, effectively reducing the series resistance of the reading circuit and improving the reading capability.

[0047] like Figure 3 As shown, an embodiment of the present invention further provides an electronic device 20, which includes the storage device 10 according to any of the above embodiments.

[0048] In this embodiment, since the embodiment of the present invention is based on three wafers, the channel column is split into a first channel column and a second channel column, the first channel column forms a first storage unit, the second channel column forms a second storage unit, a plurality of first storage cells constitute a first storage cell group arranged on the first wafer, a plurality of second storage cells constitute a second storage cell group arranged on the second wafer, and the third wafer is provided with a control unit, the first storage unit and the second storage unit are both connected to the control unit through corresponding word lines, so that the control unit can read the data in the two storage cells at the same time, effectively reducing the series resistance of the reading circuit and improving the reading capability.

[0049] like Figure 4 As shown, this embodiment further provides a method for preparing a storage device, and the method for preparing a storage device may include the following steps S4100 to S4400:

[0050] Step S4100: providing a first wafer and forming a first storage unit group on the first wafer.

[0051] The first memory cell group includes a plurality of first memory cells, the first memory cells include first channel pillars, and the first memory cells have corresponding first word lines.

[0052] In this step S4100, a first memory cell group may be formed on the first wafer, the first memory cell group including a plurality of first memory cells, each of which is composed of a corresponding first channel column, and each of which has a corresponding first word line BL1.

[0053] Step S4200: providing a second wafer, and forming a second storage unit group on the second wafer.

[0054] The second memory cell group includes a plurality of second memory cells, the second memory cells include second channel pillars, and the second memory cells have corresponding second word lines.

[0055] In this step S4200, a second memory cell group may be formed on the second wafer, the second memory cell group including a plurality of second memory cells, each second memory cell being composed of a corresponding second channel column, and each second memory cell having a corresponding first word line BL2.

[0056] Here, it is necessary to set the first storage cell group and the second storage cell group to be mirror symmetric.

[0057] Step S4300: providing a third wafer and forming a control unit on the third wafer.

[0058] In this step S4300, a control unit may be formed on the third wafer, and the control unit is used to read data in the storage unit. For an introduction to the control unit, reference may be made to the storage device embodiment, and this embodiment will not be described in detail here.

[0059] Step S4400: bonding the first wafer, the second wafer, and the third wafer.

[0060] In this step S4400, the first wafer, the second wafer and the third wafer may be bonded and connected by a wafer bonding process.

[0061] In this embodiment, bonding the first wafer, the second wafer, and the third wafer in step 4400 may include the following steps S4410 to S4420:

[0062] Step S4410: bonding the second wafer and the third wafer together through a wafer bonding process, so that the first word line is connected to the second word line that is mirror-symmetrical to the first word line to form a common word line.

[0063] In this step S4410, the first wafer and the second wafer are bonded together by a wafer bonding process, and the common source electrodes of the bonded first wafer and the second wafer form a one-to-one electrical interconnection. In addition, the word lines of the first wafer and the second wafer form a one-to-one electrical interconnection to form a common word line.

[0064] Step S4420: bonding the third wafer to the first wafer and the second wafer respectively through a wafer bonding process, so that the control unit is connected to the common word line.

[0065] In this step S4420, the first wafer is bonded to the second wafer and the third wafer through a wafer bonding process, and the control unit in the third wafer is finally connected to the common word line after the first storage unit and the second storage unit are bonded, and the control circuit can read the data in the first storage unit and the second storage unit at the same time.

[0066] According to the method of this embodiment, based on three wafers, the channel column is split into a first channel column and a second channel column, the first channel column forms a first storage unit, the second channel column forms a second storage unit, a plurality of first storage cells constitute a first storage cell group arranged on the first wafer, a plurality of second storage cells constitute a second storage cell group arranged on the second wafer, and the third wafer is provided with a control unit, the first storage unit and the second storage unit are both connected to the control unit through corresponding word lines, so that the control unit can read the data in the two storage cells at the same time, effectively reducing the series resistance of the reading circuit and improving the reading capability.

[0067] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0068] Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A storage device comprising a first wafer, a second wafer and a third wafer, The third wafer includes a control unit; The first wafer includes a first storage cell group, the first storage cell group includes a plurality of first storage cells, the first storage cells are connected to the control unit through corresponding first word lines, and the first storage cells include first channel pillars; The second wafer includes a second storage cell group, the second storage cell group includes a plurality of second storage cells, the second storage cells are connected to the control unit via corresponding second word lines, and the second storage cells include second channel pillars; in, When reading a target storage unit in a target wafer, the control unit controls a target channel column corresponding to the target storage unit to be turned on, and controls other channel columns except the target channel column to be turned off; the target wafer is the first wafer or the second wafer; The first storage cell group and the second storage cell group are mirror-symmetrical, a first word line corresponding to the first storage cell and a second word line corresponding to the second storage cell which is mirror-symmetrical thereto form a common word line, and the first storage cell and the second storage cell which is mirror-symmetrical thereto are both connected to the control unit via the common word line.

2. The storage device according to claim 1, characterized in that The first channel column sequentially includes a first upper selection switch, a first switch group, and a first lower selection switch connected in series, and the first switch group includes a plurality of first switches connected in series.

3. The storage device according to claim 2, characterized in that: The second channel column sequentially includes a second upper selection switch, a second switch group, and a second lower selection switch connected in series, and the second switch group includes a plurality of second switches connected in series.

4. The storage device according to claim 1, characterized in that: The first memory cell is connected to a common source of the second memory cell which is mirror-symmetrical to the first memory cell.

5. An electronic device, characterized in that: It comprises a storage device, wherein the storage device is the storage device according to any one of claims 1 to 4.

6. A method for preparing a storage device, comprising: Providing a first wafer, forming a first memory cell group on the first wafer, wherein the first memory cell group includes a plurality of first memory cells, the first memory cells include first channel pillars, and the first memory cells have corresponding first word lines; Providing a second wafer, forming a second memory cell group on the second wafer, wherein the second memory cell group includes a plurality of second memory cells, the second memory cells include second channel pillars, and the second memory cells have corresponding second word lines; Setting the first storage unit group and the second storage unit group to be mirror-symmetric; providing a third wafer, and forming a control unit on the third wafer; Bonding the first wafer, the second wafer and the third wafer; The bonding and connecting the first wafer, the second wafer and the third wafer comprises: Bonding the first wafer and the second wafer together through a wafer bonding process, so that the first word line is connected to the second word line which is mirror-symmetrical to the first word line to form a common word line; The third wafer is bonded to the first wafer and the second wafer respectively through the wafer bonding process, so that the control unit is connected to the common word line.

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