Pixel array and image sensor including the same

Abstract

A pixel array and an image sensor are provided. The image sensor includes a substrate and a pixel array of pixels, each pixel including a pixel circuit and a pixel conversion device. The pixel circuit is formed in a pixel region corresponding to a pixel in the substrate. The pixel conversion device is arranged on the substrate to vertically overlap the pixel circuit. The pixel circuit includes a floating diffusion node, a reset switch device, and an amplifier including a load device and a plurality of switch devices, the load device being arranged in the pixel region.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2020-0050345 filed on April 24, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Devices and apparatuses consistent with the present disclosure relate to a pixel array and an image sensor including the pixel array, and more particularly, to a pixel array including a plurality of pixels each performing feedback resetting and an image sensor including the pixel array. Background Art

[0004] An image sensor is a device for capturing a 2D or 3D image of an object. Image sensors generate images of an object using a photosensitive device that responds to the intensity of light reflected from the object. Recently, with the development of complementary metal oxide semiconductor (CMOS) technology, CMOS image sensors have become widely used. Summary of the Invention

[0005] One aspect provides a pixel array capable of reducing reset noise and reducing reset time, and an image sensor including the pixel array.

[0006] According to one aspect of an example embodiment, an image sensor is provided, comprising: a plurality of pixels arranged in a matrix form and converting optical signals into electrical signals, each of the plurality of pixels comprising a photoelectric conversion device configured to convert the optical signal into an electric charge; a floating diffusion node connected to the photoelectric conversion device and storing the electric charge; an amplifier configured to inversely amplify a voltage of the floating diffusion node, output a first output signal through a first node based on the inverted amplified voltage in a reset period, and output a second output signal through a second node different from the first node based on the inverted amplified voltage in a signal output period; and a reset switch device configured to be turned on in the reset period and provide the first output signal of the amplifier to the floating diffusion node, wherein the amplifier comprises a load device configured to provide a first bias current in the reset period.

[0007] According to another aspect of an example embodiment, a pixel array of an image sensor is provided, the pixel array including a plurality of pixels, each of the plurality of pixels including: a microlens; a first photoelectric conversion device arranged below the microlens and configured to generate a first photocharge from a light signal incident thereon; and a first pixel circuit arranged in a pixel region vertically overlapping the microlens and vertically located below the first photoelectric conversion device, the first pixel circuit configured to output a first sensing signal based on an amount of the first photocharge, wherein the first pixel circuit includes a floating diffusion node storing the first photocharge; an amplifier including a plurality of switching devices, the amplifier configured to amplify a voltage of the floating diffusion node; and a resistor device configured to provide a bias current to the amplifier during a reset period.

[0008] According to another aspect of the example embodiment, an image sensor is provided, comprising: a pixel array comprising a plurality of pixels arranged in a matrix form, each of the plurality of pixels converting a light signal incident thereon into an electrical signal; and a reading circuit configured to read the plurality of pixel signals on a row basis, the plurality of pixel signals being output from the pixel array through a plurality of column lines, wherein each of the plurality of pixels comprises a photoelectric conversion device configured to convert the light signal into a photocharge; a floating diffusion node storing the photocharge; an amplifier comprising a resistor device configured to provide a first bias current during a reset period, the amplifier being configured to inversely amplify a voltage of the floating diffusion node; and a feedback device configured to provide a first output signal of the amplifier to the floating diffusion node during the reset period.

[0009] According to another aspect of the example embodiment, there is provided an image sensor comprising: a substrate; a pixel array comprising a plurality of pixels, each of the plurality of pixels comprising a pixel circuit formed in a pixel region corresponding to the pixel in the substrate; and a pixel conversion device arranged on the substrate to vertically overlap with the pixel circuit, wherein the pixel circuit comprises a floating diffusion node; a reset switch device; and an amplifier comprising a load device and a plurality of switch devices, the load device being arranged in the pixel region. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Various embodiments will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a schematic block diagram illustrating a pixel and an image sensor including the pixel according to example embodiments;

[0012] Figure 2 An example of a pixel according to an example embodiment is shown;

[0013] Figure 3A and Figure 3BThe reset period and the signal output period are shown respectively. Figure 2 Pixel operations;

[0014] Figure 4A An equivalent circuit of a pixel circuit in a reset period according to an example embodiment is shown, and Figure 4B is a graph showing the DC operating point of a pixel circuit during a reset period;

[0015] Figure 5A and Figure 5B each showing a timing diagram of a pixel array according to an example embodiment;

[0016] Figure 6A and Figure 6B each is a timing diagram illustrating a control signal and a reset control signal applied to a pixel circuit according to an example embodiment;

[0017] Figure 7A is a schematic perspective view of a pixel array according to example embodiments, and Figure 7B is included along Figure 7A A schematic vertical cross-sectional view taken along line AA′ of a pixel in the pixel array shown in FIG.

[0018] Figure 8A and Figure 8B each is a schematic plan view of a pixel according to an example embodiment;

[0019] Figure 9 shows an example of another pixel according to example embodiments;

[0020] Figure 10 shows a pixel array according to an example embodiment;

[0021] Figure 11A and Figure 11B each is a schematic plan view of a pixel according to an example embodiment;

[0022] 12A to 12C each showing a schematic vertical cross-sectional view of a pixel array according to an example embodiment;

[0023] Figure 13A is an exploded perspective view of the image sensor, and Figure 13B is a plan view of the image sensor;

[0024] Figure 14 is a block diagram of an electronic device including a plurality of camera modules to which image sensors according to example embodiments are applied; and

[0025] Figure 15 According to an example embodiment Figure 14 Detailed block diagram of multiple camera modules. DETAILED DESCRIPTION

[0026] Hereinafter, various embodiments will be described in detail with reference to the accompanying drawings.

[0027] Figure 1 is a schematic block diagram illustrating a pixel and an image sensor including the pixel according to example embodiments.

[0028] The image sensor 100 may be installed in an electronic device having a function of sensing an image or light. For example, the image sensor 100 may be installed in an electronic device such as a camera, a smartphone, a wearable device, an Internet of Things (IoT) device, a home appliance, a tablet personal computer (PC), a personal digital assistant (PDA), a portable multimedia player (PMP), a navigation system, an unmanned aerial vehicle (UAV), an advanced driver assistance system (ADAS), etc. In addition, the image sensor 100 may be installed in an electronic device included as part of a vehicle, furniture, manufacturing equipment, a door, and / or various measuring instruments.

[0029] Reference Figure 1 The image sensor 100 may include a pixel array 110, a row driver 120, a read circuit 130, a ramp signal generator 140 and a timing controller 150, and the read circuit 130 may include an analog-to-digital converter (ADC) circuit 131 and a data bus 132.

[0030] The pixel array 110 may include a plurality of pixels PX arranged in a matrix form, and include a plurality of row lines RL and a plurality of column lines CL connected to the plurality of pixels PX.

[0031] Each of the plurality of row lines RL may extend in a row direction and may be connected to pixels PX arranged in the same row. For example, each of the plurality of row lines RL may transmit a control signal output from the row driver 120 to the pixel circuit ( Figure 2 PXC) transistors, such as Figure 2 As shown in .

[0032] Each of the plurality of pixels PX according to an example embodiment may include at least one photoelectric conversion device PE (alternatively referred to as a photosensitive device) and an amplifier AMP. The photoelectric conversion device PE may sense light and may convert the sensed light into photocharges. For example, the photoelectric conversion device PE may include a photosensitive device including organic or inorganic materials, such as an inorganic photodiode, an organic photodiode, a perovskite photodiode, a phototransistor, a grating, or a pinned photodiode. In some embodiments, each of the plurality of pixels PX may include a plurality of photoelectric conversion devices PE.

[0033] The amplifier AMP can inversely amplify the floating diffusion node ( Figure 2 FD) (alternatively referred to as a floating diffusion region) and can output an amplified signal.

[0034] exist Figure 1 In an embodiment, the amplifier AMP can be operated as a feedback amplifier during the reset period, and the output signal output from the amplifier AMP can be fed back to the input of the amplifier AMP (i.e., to the floating diffusion node FD). The phase of the input signal of the amplifier AMP can be opposite to the phase of the output signal of the amplifier AMP.

[0035] Due to the reset operation in which the floating diffusion node FD is reset during the reset period, noise is generated at the floating diffusion node FD. However, because the output signal of the amplifier AMP is fed back to the floating diffusion node FD, a noise cancellation effect is achieved, which reduces the noise of the floating diffusion node FD. Therefore, the reset noise can be reduced. As such, hereinafter, the reset operation of the pixel PX will be referred to as a feedback reset (or feedback reset operation), which allows noise reduction based on the feedback operation of the amplifier AMP. Each of the multiple pixels PX can perform a feedback reset during the reset period.

[0036] A load device (alternatively referred to as a pixel load) (e.g., a resistor device that provides a bias current (referred to as a reset bias current) to the amplifier AMP when performing feedback reset) may be disposed inside the pixel PX. In other words, each of the plurality of pixels PX may include a load device that provides a reset bias current for the pixel PX. Figure 2 The structure of the pixel PX is described in detail.

[0037] During the signal output period, the amplifier AMP can output a reset signal and a sensing signal to the column line CL. The sensing signal can be generated based on the photocharge stored in the floating diffusion node FD according to the light sensing of the photoelectric conversion device PE. The multiple sensing signals generated by the multiple pixels PX may have deviations due to noise (e.g., reset noise), and the deviations are different for each pixel PX. In other words, even if the amount of light sensed by the multiple pixels PX is equal to each other, the sensing signals output from the multiple pixels PX may have different levels. In addition, the reset signal may include noise.

[0038] To minimize the noise included in the reset signal (i.e., reset noise), as described above, the amplifier AMP included in each of the plurality of pixels PX performs a feedback reset operation, thereby suppressing noise generation. Thus, the reset noise of each of the plurality of pixels PX can be minimized. Furthermore, each of the plurality of pixels PX can generate a reset signal indicating a level after the reset (e.g., the reset level of the floating diffusion node FD). The image sensor 100 can generate a pixel value indicating the amount of light sensed by the pixel PX based on the difference between the sensed signal from each pixel PX and the reset signal. For example, the image sensor 100 can generate the pixel value by removing the reset signal from the sensed signal.

[0039] A microlens for focusing light may be arranged above each of the plurality of pixels PX or above each pixel group including adjacent pixels PX. Each of the plurality of pixels PX may sense light in a specific spectral range from the light received through the microlens. For example, the pixel array 110 may include red pixels for converting light in the red spectral range into electrical signals, green pixels for converting light in the green spectral range into electrical signals, and blue pixels for converting light in the blue spectral range into electrical signals. A color filter for transmitting light in a specific spectral range may be arranged above each of the plurality of pixels PX. However, example embodiments are not limited thereto, and in some example embodiments, the pixel array 110 may include pixels that convert light in spectral ranges other than the red, green, and blue spectral ranges into electrical signals.

[0040] In some embodiments, each of the multiple pixels PX can have a multi-layer structure. A pixel PX having a multi-layer structure can include multiple stacked photoelectric conversion devices PE that convert light from different spectral ranges into electrical signals. The multiple photoelectric conversion devices PE can each generate an electrical signal corresponding to a different color. In other words, a single pixel PX can output electrical signals corresponding to multiple colors.

[0041] Each of the plurality of column lines CL may extend in a column direction and may be connected to pixels PX arranged in the same column. Each of the plurality of column lines CL may transmit reset signals and sensing signals of the pixels PX to the read circuit 130 based on each row of the pixel array 110 .

[0042] The timing controller 150 may control the timing of the row driver 120, the read circuit 130, and the ramp signal generator 140. The timing controller 150 may provide each of the row driver 120, the read circuit 130, and the ramp signal generator 140 with a timing signal indicating an operation timing.

[0043] Under the control of the timing controller 150, the row driver 120 can generate a control signal for driving the pixel array 110, and can provide the control signal to each of the plurality of pixels PX of the pixel array 110 through a plurality of row lines RL. The row driver 120 can control the plurality of pixels PX of the pixel array 110 to sense incident light simultaneously or on a row basis. In addition, the row driver 120 can select a pixel PX from the plurality of pixels PX on a row basis, and can control the selected pixel PX (e.g., a pixel PX in the same row) to output a reset signal and a sensing signal through a plurality of column lines CL.

[0044] The ramp signal generator 140 may generate a ramp signal RAMP that increases or decreases with a certain slope, and may provide the ramp signal RAMP to the ADC circuit 131 of the read circuit 130 .

[0045] The read circuit 130 can read the reset signal and the sense signal from the pixels PX in the row selected by the row driver 120 among the plurality of pixels PX. The read circuit 130 can generate and output pixel values ​​corresponding to the plurality of pixels PX on a row basis by converting the reset signal and the sense signal into digital data based on the ramp signal RAMP from the ramp signal generator 140. The reset signal and the sense signal are received from the pixel array 110 through the plurality of column lines CL.

[0046] The ADC circuit 131 may include a plurality of ADCs corresponding to a plurality of column lines CL. Each of the plurality of ADCs may compare the ramp signal RAMP with each of the reset signal and the sense signal received via the corresponding column line CL, and may generate a pixel value based on the comparison result. For example, each ADC may remove the reset signal from the sense signal and may generate a pixel value representing the amount of light sensed by the pixel PX.

[0047] The plurality of pixel values ​​generated by the ADC circuit 131 may be output as image data IDT through the data bus 132. For example, the image data IDT may be provided to an image signal processor inside or outside the image sensor 100.

[0048] As described above, in image sensor 100, reset noise can be reduced due to the feedback reset operation of amplifier AMP disposed within pixel PX. Furthermore, because the load device is disposed within pixel PX, resistance-capacitance (RC) delay can be reduced. Consequently, the time required for feedback reset (i.e., reset period) can be shortened.

[0049] Figure 2 An example of a pixel according to example embodiments is shown. Figure 2 The circuit configuration of the pixel PX is shown.

[0050] Reference Figure 2 , the pixel PX may include a photoelectric conversion device PE and a pixel circuit PXC. The pixel circuit PXC may include a floating diffusion node FD, an amplifier AMP, and a reset switching device (e.g., a reset transistor RX). In some embodiments, the pixel circuit PXC may be formed in a pixel region corresponding to the pixel PX in the substrate, and the photoelectric conversion device PE may be arranged on the substrate to vertically overlap the pixel circuit PXC.

[0051] The photoelectric conversion device PE can sense light and convert the sensed light into photocharges. In some embodiments, the photoelectric conversion device PE may include an organic photodiode, which includes a first electrode E1 and a second electrode E2. The organic photodiode may include an organic photoconductive film (OPF). However, the embodiment is not limited thereto, and in some embodiments, the photoelectric conversion device PE may be replaced with another photosensitive device described above (such as an inorganic photodiode, a pinned photodiode, etc.).

[0052] One end of the photoelectric conversion device PE (eg, the first electrode E1) may be connected to the floating diffusion node FD, and the first voltage V TOP (eg, a global voltage) may be applied to the other end thereof (eg, the second electrode E2). In some embodiments, the first voltage V TOP can be applied equally to the pixel array ( Figure 1 110) of multiple pixels PX.

[0053] In some embodiments, when the photoelectric conversion device PE is implemented by an organic photodiode and the image sensor ( Figure 1 100) operates in a global shutter mode, during the read cycle and the reset cycle, the first voltage V TOP It may have a low voltage level for internal reset of the organic photodiode.

[0054] In some embodiments, when the image sensor ( Figure 1 When the pixel array 100 operates in a rolling shutter manner, a shutter voltage may be applied on a row basis to the plurality of pixels PX of the pixel array 110. For example, the shutter voltage may be applied to the other end of the photoelectric conversion device PE (ie, the second electrode E2).

[0055] The floating diffusion node FD may store photocharges generated by the photoelectric conversion device PE. Specifically, the photocharges may be stored in a capacitor C formed by the floating diffusion node FD. FD middle.

[0056] The amplifier AMP may include a driving transistor DX, a plurality of selection transistors (eg, a first selection transistor SX1, a second selection transistor SX2, a third selection transistor SX3, and a fourth selection transistor SX4), and a load resistor R L and can be based on the first power supply voltage V PP and a second power supply voltage GND (eg, ground voltage) for operation.

[0057] The amplifier AMP may amplify an input signal (i.e., a voltage of the floating diffusion node FD) and may output an amplified voltage. The amplifier AMP may output the amplified voltage as a first output signal through a first node NO1 during a reset period, and may output the amplified voltage as a second output signal through a second node NO2 during a signal output period.

[0058] The driving transistor DX may perform inversion amplification on an input signal received through a gate terminal. The first to fourth selection transistors SX1 to SX4 may be responsive to a control signal (eg, a signal from a row driver ( Figure 1 The first control signal S1, the second control signal S2, the third control signal S3 and the fourth control signal S4 received by the controller 120 are turned on or off, thereby performing a switching operation.

[0059] In the reset period, when the first selection transistor SX1 and the third selection transistor SX3 are turned on in response to the first control signal S1 and the third control signal S3, the amplifier AMP can be operated as a common source amplifier. L The reset bias current I1 is provided to amplify the input signal to generate a first output signal.

[0060] In the signal output period, when the second selection transistor SX2 and the fourth selection transistor SX4 are turned on in response to the second control signal S2 and the fourth control signal S4, the amplifier AMP can be operated as a source follower. The amplifier AMP can be connected to the column line CL by generating a load current I L The input signal is amplified to generate a second output signal. The second output signal, which is a pixel voltage Vpx, can be provided to the reading circuit 130 via the column line CL.

[0061] The reset transistor RX is connected to the first node NO1 of the amplifier AMP and the floating diffusion node FD, and can be reset in response to the input from the row driver ( Figure 1 120) receives the reset control signal S RSTThe first output signal output from the amplifier AMP during the reset period can be fed back to the floating diffusion node FD. Since the phase of the first output signal (e.g., the amplified voltage) is opposite to the phase of the voltage of the floating diffusion node FD, noise can be reduced due to the feedback reset. In the signal output period, the amplifier AMP can be reset in response to the reset control signal S RST The device is turned off due to an invalid level (e.g., logic low).

[0062] although Figure 2 The pixel PX is shown to include one photoelectric conversion device PE and one pixel circuit PXC, but the embodiment is not limited thereto. In some embodiments, the pixel PX may include multiple photoelectric conversion devices PE and multiple pixel circuits PXC respectively connected to the multiple photoelectric conversion devices PE. In this case, the multiple photoelectric conversion devices PE can convert light signals having different colors from each other into light charges.

[0063] like Figure 2 As shown in FIG, in pixel PX, one end of the photoelectric conversion device PE can be directly connected to the floating diffusion node FD. In other words, a separate switching device can be omitted and thus not arranged between one end of the photoelectric conversion device PE and the floating diffusion node FD. Therefore, the photocharge generated by the photoelectric conversion device PE can be directly stored in the floating diffusion node FD.

[0064] In a pixel PX having such a structure, a reset signal according to a reset operation may be read out, followed by exposure, and then a sensing signal may be read out; alternatively, exposure may be performed, followed by reading of a sensing signal, and then the reset signal according to the reset operation may be read out. Therefore, it is difficult to apply a reading method based on correlated double sampling (CDS), in which a reset signal and a sensing signal including the reset signal are read out and the reset signal is subtracted from the sensing signal. This can result in image quality degradation in the image data due to reset noise. However, as described above, in the pixel PX according to various exemplary embodiments, reset noise can be eliminated (i.e., reduced) through feedback reset, thereby preventing image quality degradation.

[0065] Figure 3A and Figure 3B Shown respectively Figure 2 The operation of the pixel in the reset period and the signal output period.

[0066] Reference Figure 3AIn the reset period, the first selection transistor SX1 and the third selection transistor SX3 may be turned on in response to the active levels (e.g., logic high) of the first control signal S1 and the third control signal S3, respectively, and the second selection transistor SX2 and the fourth selection transistor SX4 may be turned off in response to the inactive levels (e.g., logic low) of the second control signal S2 and the fourth control signal S4, respectively. In addition, the reset transistor RX may be turned off in response to the reset control signal S RST The drain voltage V of the driving transistor DX outputted through the second node NO2 is turned on. D (eg, the first output signal) can be fed back to the gate terminal of the driving transistor DX. Thus, the pixel PX can be reset by feedback. Figure 4A and Figure 4B To describe the feedback reset of the pixel PX.

[0067] Figure 4A shows an equivalent circuit of a pixel circuit in a reset period according to an example embodiment, Figure 4B is a graph showing the direct current (DC) operating point of a pixel circuit during a reset period.

[0068] The driving transistor DX of the amplifier AMP can receive the voltage of the floating diffusion node FD as an input voltage through the gate terminal and can invert and amplify the input voltage. Here, the input voltage may include a noise component, for example, Vn 2 (Wherein, Vn is a noise voltage according to the amount of noise charge of the floating diffusion node FD). The inverted amplified voltage (eg, drain voltage V D ) can be output through the first node NO1, the drain voltage V D can be fed back to the gate terminal of the drive transistor DX, where the on-resistance R of the reset transistor RX is reset. RST Can be extremely small. Through the load resistor R L The reset bias current I1 provided can be equal to the sum of the current I2 flowing through the drive transistor DX and the current I3 flowing through the feedback loop. D The current I and the current I2 can be expressed by Equation 1 and Equation 2, respectively.

[0069] [Equation 1]

[0070] V D =V PP -R L ×I1

[0071] [Equation 2]

[0072]

[0073] Here, β represents a parameter determined based on the mobility and size of the driving transistor DX, and Vth represents the threshold voltage of the driving transistor DX.

[0074] Ideally, Figure 4A The feedback current I3 shown in FIG can be “0”, and the drain voltage V D and gate voltage V G Therefore, through the feedback operation of the amplifier AMP, the gate voltage V G and drain voltage V D It can be adjusted so that the reset bias current I1 is equal to the current I2, and thus, the noise component can be eliminated. In other words, by the feedback reset, the reset voltage (reset level) of the floating diffusion node FD from which the noise component is eliminated can be determined.

[0075] Reference Figure 4B , the horizontal axis represents the load resistor R L The potential difference between the two ends corresponds to the voltage V R , the vertical axis represents the current. When the voltage V R When V increases, the reset bias current I1 can increase and the current I2 can decrease. R Can be determined so that the reset bias current I1 is equal to the current I2. Here, the first power supply voltage V PP and drain voltage V D are applied to the load resistor R L Because the first power supply voltage V PP is constant, and the drain voltage V D is variable, so the drain voltage V D To determine the load resistor R L The voltage between the two ends.

[0076] The point where the reset bias current I1 is equal to the current I2 is the DC operating point, and the load resistor R L The resistance value (small signal resistance) can be determined so as to provide a voltage V corresponding to the DC operating point R For example, under the condition that the small signal operation of the pixel circuit PXC can be normally performed, the inverse of the tangent slope of the reset bias current I1 at the DC operating point may be the load resistor R L For example, when the voltage V R If the load resistor R is 3V or less and the reset bias current I1 is a few microamperes (μA) or less, the resistance can be several megohms. L The resistor may have a mega-ohm level so that the pixel circuit PXC can normally perform a feedback reset operation during a reset period.

[0077] Reference Figure 3B In the signal output period, the first selection transistor SX1 and the third selection transistor SX3 may be turned off in response to the inactive level (e.g., logic low) of the first control signal S1 and the third control signal S3, and the second selection transistor SX2 and the fourth selection transistor SX4 may be turned on in response to the active level (e.g., logic high) of the second signal S2 and the fourth signal S4. The amplifier AMP may be operated as a source follower, and the voltage amplified by the amplifier AMP (i.e., the drain voltage V D (eg, the second output signal)) can be output to the column line CL as the pixel voltage Vpx.

[0078] The signal output period may include a first period and a second period. The first period may be a reset signal output period, and the second period may be a sensing signal output period. The reset signal output period is a period after the reset period of the pixel PX, and the amplifier AMP may output a reset voltage representing a reset level in which noise is reduced by feedback reset as a pixel voltage Vpx, for example, a second output signal, through the second node NO2. The sensing signal output period is a period after the exposure period of the pixel PX, that is, a period after the photocharge generated by the photoelectric conversion device PE is stored in the floating diffusion node FD, and the amplifier AMP may generate a sensing voltage based on the photocharge stored in the floating diffusion node FD, and may output the sensing voltage as a pixel voltage Vpx, for example, a second output signal, through the second node NO2. The pixel voltage Vpx (that is, the reset voltage and the sensing voltage) may be sent to the read circuit ( Figure 1 130).

[0079] Figure 5A and Figure 5B Each shows a timing diagram of a pixel array according to example embodiments.

[0080] Figure 5A shows a pixel array according to an example embodiment ( Figure 1 110) is a timing diagram when the image sensor operates in a global shutter mode, Figure 5B A timing diagram of the pixel array 110 according to example embodiments is shown when the image sensor operates in a rolling shutter manner.

[0081] Reference Figure 1 and Figure 5A The frame period FRM may include a global reset period GR (alternatively referred to as a shutter period), an exposure period EXP, and a read period RO. During the global reset period GR, feedback reset may be performed by the plurality of pixels PX of the pixel array 110. During the exposure period EXP, the photoelectric conversion device PE may convert the optical signal into photocharges, which may be stored in the floating diffusion node ( Figure 2During the read cycle RO, the plurality of rows R1 to Rj (where j is a positive integer of 3 or greater) of the pixel array 110 may be sequentially read out to the read circuit 130 on a row basis, and the ADC circuit 131 may convert the received signals (e.g., sensing signals and reset signals) into digital data, e.g., pixel values. The read cycle for each of the plurality of rows R1 to Rj may be referred to as a row read cycle RRO.

[0082] When the photoelectric conversion device PE is implemented by an organic photodiode, the first voltage V applied to the photoelectric conversion device PE is TOP (eg, a global voltage) may have a low voltage level (eg, 0 V) ​​in the read period RO and the global reset period GR, and thus, the organic photodiode may be internally reset.

[0083] In the global reset period GR, feedback reset may be performed by the plurality of pixels PX of the pixel array 110, and in the row read period RRO, feedback reset may be performed by the pixels PX arranged in the corresponding row. Figure 6A and Figure 6B to describe.

[0084] Reference Figure 1 and Figure 5B , the frame period FRM of each row of the pixel array 110 may include a row reset period RR, an exposure period EXP, and a row read period RRO. Row reset, exposure, and row read may be performed sequentially on a row basis in the order described. The frame periods FRM may overlap with each other. For example, Figure 5B As shown in , frame 1 may temporally overlap with frame 2. However, embodiments are not limited thereto, and in some embodiments, frame 2 may begin after frame 1 ends.

[0085] The first voltage V TOP (eg, a shutter voltage) may have a high voltage level, for example, 3 V, and the shutter voltage may be applied to each row of the pixel array 110 , whereby exposure may be sequentially performed in the plurality of rows R1 to Rj.

[0086] In the row reset period RR, feedback reset can be performed by the pixels PX arranged in the corresponding row, and in the row read period RRO, feedback reset can be performed by the pixels PX arranged in the corresponding row. Figure 6A and Figure 6B to describe.

[0087] Figure 6A and Figure 6B 1 and 2 are timing diagrams each illustrating a control signal and a reset control signal applied to a pixel circuit according to example embodiments. Figure 6A According to an example embodiment Figure 5A The global reset period GR or Figure 5B The timing diagram of the row reset cycle RR in Figure 6B According to an example embodiment Figure 5A and Figure 5B Timing diagram of row read cycle RRO in .

[0088] Reference Figure 2 and Figure 6A , a portion of the global reset period GR or the row reset period RR may be a reset period RP, and feedback reset may be performed in the reset period RP. The second control signal S2 and the fourth control signal S4 may be at an inactive level (eg, logic low), and the reset control signal S RST , the first control signal S1 and the third control signal S3 may be at an active level (eg, logic high). Thus, the amplifier AMP may be based on the load resistor R L The pixel PX can perform feedback reset by operating as a common-source amplifier by supplying the reset bias current I1.

[0089] Reference Figure 2 and Figure 6B , a portion of the row read period RRO may be the reset period RP, and another portion thereof may be a signal output period, for example, a sensing signal output period SSO and a reset signal output period RSO.

[0090] The second control signal S2 and the fourth control signal S4 may be at an active level in the sensing signal output period SSO and the reset signal output period RSO, and the reset control signal S RST , the first control signal S1, and the third control signal S3 may be at an inactive level. Thus, the amplifier AMP may be operated as a source follower. The amplifier AMP may generate a second output signal (e.g., a pixel voltage Vpx) and may output the second output signal to the column line CL. The pixel voltage Vpx may be provided to the read circuit 130 via the column line CL, and the ADC circuit 131 may generate a pixel value based on the received pixel voltage Vpx.

[0091] In the sensing signal output period SSO after the exposure period, the sensing signal may be output as the pixel voltage Vpx, and the ADC circuit 131 may perform analog-to-digital conversion on the sensing signal Vsen.

[0092] Next, feedback reset can be performed in the reset period RP. The second control signal S2 and the fourth control signal S4 can be turned into an inactive level, and the reset control signal S RST , the first control signal S1 and the third control signal S3 may be turned into active levels. The amplifier AMP may be operated as a common-source amplifier, and the pixel PX may perform feedback reset.

[0093] In the reset signal output period RSO after the reset period RP, the second control signal S2 and the fourth control signal S4 can be turned into the active level again, and the reset control signal S RST , the first control signal S1 and the third control signal S3 may be transformed into inactive levels.

[0094] The amplifier AMP may output a reset signal as a second output signal, for example, a pixel voltage Vpx. The ADC circuit 131 may perform ADC conversion on the reset signal Vrst.

[0095] Figure 7A is a schematic perspective view of a pixel array according to an example embodiment, Figure 7B is included in Figure 7A Schematic vertical cross-sectional view of a pixel in the pixel array shown in . Figure 7B A vertical cross-sectional view of a pixel PX may correspond to a vertical cross-sectional view of a pixel PX along Figure 7A The line A-A' intercepts Figure 7A An example configuration of the area corresponding to the cross section of the pixel PX.

[0096] Reference Figure 7A and Figure 7B , the pixel array 110 may include a plurality of pixels PX arranged in a matrix on an XY plane. The region in which each of the plurality of pixels PX is formed on the XY plane may be referred to as a pixel region PXAR. Each of the plurality of pixels PX may include a substrate 210. In other words, the pixel array 110 may include a substrate 210. The substrate 210 may have a first surface (e.g., a main surface) 210F and a second surface (e.g., a back surface) 210B extending in a horizontal direction (X direction and Y direction). The substrate 210 may include, but is not limited to, a semiconductor substrate, e.g., a p-type silicon substrate.

[0097] Each of the plurality of pixels PX may include a photoelectric conversion unit 10 and a pixel circuit unit 20. The photoelectric conversion unit 10 may overlap the pixel circuit unit 20 vertically (eg, in the Z direction).

[0098] The photoelectric conversion unit 10 may be formed on the insulating structure 17 on the second surface 210B of the substrate 210 and may include a microlens 11, a color filter 12, and a photoelectric conversion device PE. In some embodiments, the photoelectric conversion unit 10 may further include a color filter 12, a protective layer 13, and an insulating structure 17.

[0099] The microlens 11 may be disposed above the photoelectric conversion device PE, and may condense light incident from the outside thereof to make the light incident on the photoelectric conversion device PE.

[0100] The photoelectric conversion device PE may include an upper electrode 14, a lower electrode 16, and a color selection layer 15 located therebetween. The color selection layer 15 may absorb light signals in a specific wavelength band from received light signals. The absorbed light signals may be converted into electrical signals in the color selection layer 15 by current flowing through the upper electrode 14 and the lower electrode 16.

[0101] The color selection layer 15 may include an organic conductive film that causes a photoelectric change due to a light signal in a specific wavelength band. In some embodiments, the color selection layer 15 may include an organic film in which a p-type semiconductor material and an n-type semiconductor material form a pn flat junction or a bulk heterojunction. The organic film may include a single film or a multilayer film.

[0102] Each of the upper electrode 14 and the lower electrode 16 may include a transparent conductive layer. In some embodiments, each of the upper electrode 14 and the lower electrode 16 may include indium tin oxide (ITO), indium zinc oxide (IZO), ZnO, SnO2, antimony-doped tin oxide (ATO), aluminum-doped zinc oxide (AZO), gallium-doped zinc oxide (GZO), TiO2, or fluorine-doped tin oxide (FTO).

[0103] The color filter 12 can selectively transmit light signals in a specific wavelength band and can be arranged between the microlens 11 and the photoelectric conversion device PE. For example, the color filter 12 can selectively transmit light signals in a first wavelength band, and the photoelectric conversion device PE can convert the light signals in the first wavelength band into photocharges. The light signals pass through the color filter 12 and are received by the photoelectric conversion device PE.

[0104] The protective layer 13 may be disposed between the color filter 12 and the upper electrode 14 of the photoelectric conversion device PE. In some embodiments, the protective layer 13 may be disposed between the microlens 11 and the color filter 12. The protective layer 13 may include a transparent insulating material. In some embodiments, the protective layer 13 may include a plurality of insulating films having different refractive indices.

[0105] The pixel circuit unit 20 may be formed below the photoelectric conversion unit 10 and may include a floating diffusion node FD formed on the first surface 210F of the substrate 210, a source / drain 25, and a load resistor R L The pixel circuit unit 20 may further include a gate 24, a via contact 26, and a wiring structure 29 formed below the first surface 210F of the substrate 210. The aforementioned components (i.e., the floating diffusion node FD, the source / drain 25, the load resistor R L , gate 24, via contact 26 and wiring structure 29) may constitute a pixel circuit (e.g., Figure 3A and Figure 3B of PXC).

[0106] A well region may be formed in the substrate 210. For example, in some embodiments, the well region may be a p-type well region 21, which may be formed in the substrate 210, the floating diffusion node FD, the source / drain 25, and the load resistor R L The through-electrode 22 may be formed in the p-type well region 21. In addition, the device isolation film 23 may be formed inside or outside the p-type well region 21. The through-electrode 22 may be formed to extend through the substrate 210 in the thickness direction (i.e., the Z direction) of the substrate 210. The through-electrode 22 may be connected to the lower electrode 16 of the photoelectric conversion device PE. In some embodiments, the through-electrode 22 may be formed through the device isolation film 23.

[0107] In some embodiments, p-type impurities may be implanted into the semiconductor substrate 210 to form a p-type well region 21. In addition, n-type impurities may be implanted into the p-type well region 21 to form a floating diffusion node FD, a source / drain 25, and a load resistor R. L The p-type well region 21, the floating diffusion node FD, the source / drain 25 and the load resistor R L It can be formed by a diffusion process or an ion implantation process.

[0108] Load resistor R L is a resistor formed in the p-type well region 21 and may be referred to as a well resistor. For example, the load resistor R L It can be formed by ion implantation of n-type impurities in the p-type well region 21. By adjusting the energy and dose during ion implantation, a load resistor R of megaohm level for small signal operation can be formed. L . Load resistor R L Can be formed adjacent to the side of the pixel area PXAR, as shown below with reference to Figure 8A and Figure 8B Will be described.

[0109] The wiring structure 29 may include a plurality of wirings 28 and an interlayer dielectric 27 that insulates the plurality of wirings 28 from each other. Each of the plurality of wirings 28 may include a metal, such as copper (Cu), aluminum (Al), or tungsten (W). The interlayer dielectric 27 may include an oxide film, a nitride film, or a combination thereof.

[0110] In some embodiments, the support film 30 may be bonded to the wiring structure 29. The support film 30 may serve to reinforce the strength of the substrate 210. The support film 30 may include a silicon oxide film, a silicon nitride film, or a semiconductor film.

[0111] Although reference has been Figure 7BWhile an example has been described in which the pixel PX includes one photoelectric conversion device PE, in some embodiments, the pixel PX may include two or more photoelectric conversion devices PE. For example, the photoelectric conversion unit 10 may include a photoelectric conversion device PE that absorbs light signals in a first wavelength band, and may further include another photoelectric conversion device PE that absorbs light signals in a second wavelength band different from the first wavelength band. The color filter 12 may be arranged between the photoelectric conversion device PE and the other photoelectric conversion device PE to transmit light signals in the second wavelength band.

[0112] Figure 8A and Figure 8B Each is a schematic plan view of a pixel according to an example embodiment. Specifically, Figure 8A and Figure 8B Each is a plan view of the pixel circuit unit 20 in the direction of the first surface 210F of the substrate 210, and schematically shows Figure 2 The physical layout of the pixel circuit PXC. Figure 8A and Figure 8B Each of the figures shows a pixel circuit unit 20 of one pixel PX, but a plurality of pixel circuit units 20 corresponding to a plurality of pixels PX may be arranged in a matrix form, as shown in FIG. Figure 7A As shown in .

[0113] In the pixel region PXAR of the substrate 210, a floating diffusion node FD, a source / drain 25, a gate 24, and a load resistor R may be arranged. L , and a through-hole electrode (TSV) 22 may also be arranged. Figure 2 The pixel circuit PXC matches the above components, showing the electrical connection relationship between the above components. For example, these components can be connected through via contacts ( Figure 7B 26) and multiple wiring ( Figure 7B 28) are electrically connected to each other.

[0114] The source / drain 25 and the gate 24 may constitute transistors, for example, a reset transistor RX, a drive transistor DX, and first to fourth selection transistors SX1 to SX4. The reset transistor RX, the drive transistor DX, and the first to fourth selection transistors SX1 to SX4 may be arranged in a relatively inner region of the pixel region PXAR.

[0115] Load resistor R L The load resistor R L It can be arranged adjacent to the side of the pixel area PXAR. Figure 8A In some embodiments, the load resistor R L Can be arranged to surround the pixel area PXAR. In other words, the load resistor RL The load resistor R may be arranged to surround the reset transistor RX, the drive transistor DX, and the first to fourth selection transistors SX1 to SX4. However, the embodiment is not limited thereto, and in some embodiments, the load resistor R L It can be arranged adjacent to and along at least one of the four sides of the pixel area PXAR. Figure 8B As shown in FIG, in some embodiments, the load resistor R L The load resistor R may be arranged adjacent to and along three of the four sides of the pixel region PXAR. L A load resistor R may be formed in an empty space in the pixel region PXAR, in other words, L It may be formed in the remaining space where the floating diffusion node FD, the source / drain 25, and the gate 24 are not formed, and may be formed to have a large length so that the load resistor R L Can have high resistance.

[0116] Figure 9 shows an example of another pixel according to example embodiments, Figure 10 A pixel array according to example embodiments is shown.

[0117] Reference Figure 9 The pixel PX may include a photoelectric conversion device PE and a pixel circuit PXCa. The pixel circuit PXCa may include a floating diffusion node FD, an amplifier AMPa, and a reset switching device (eg, a reset transistor RX).

[0118] Figure 9 The pixel PXa is Figure 2 Therefore, for the sake of brevity, repeated description of the same elements thereof will be omitted, and the description will be mainly about the same elements. Figure 2 The pixels PX are different.

[0119] Reference Figure 2 and Figure 9 , the first selection transistor SX1 and the second selection transistor SX2 can be arranged outside the pixel PXa. PP The second power supply voltage GND is connected to the second selection transistor SX2 and the first selection transistor SX1 , respectively, and thus, even when the first selection transistor SX1 and the second selection transistor SX2 are arranged outside the pixel PXa, the setup time may not be significantly increased.

[0120] In some embodiments, as Figure 10 As shown in FIG, the first selection transistor SX1 and the second selection transistor SX2 may be shared by a plurality of pixels PX_C connected to the same column line CL.

[0121] Figure 11A and Figure 11B Each is a schematic plan view of a pixel according to an example embodiment. Specifically, Figure 11A and Figure 11B Each shows Figure 9 Schematic physical layout of the pixel circuit PXCa.

[0122] Reference Figure 11A and Figure 11B In the pixel region PXAR of the substrate 210, a floating diffusion node FD, a source / drain 25, a gate 24, and a load resistor R may be arranged. L , and a through-hole electrode (TSV) 22 may also be arranged.

[0123] The source / drain 25 and the gate 24 may constitute transistors, for example, a reset transistor RX, a drive transistor DX, and third and fourth selection transistors SX3 and SX4. Figure 8A and Figure 8B Unlike the plan view of FIG, the first selection transistor SX1 and the second selection transistor SX2 are not arranged in the pixel region PXAR. Therefore, the size of the pixel region PXAR can be reduced. In addition, in some embodiments, as shown in FIG. Figure 11B As shown in the figure, the load resistor R L can be formed in which already Figure 8A and Figure 8B In the plan view of FIG. 1 , the first selection transistor SX1 and the second selection transistor SX2 are arranged. Therefore, the load resistor R can be increased. L area, and can increase the load resistor R L resistance.

[0124] 12A to 12C Each shows a schematic vertical cross-sectional view of a pixel array according to example embodiments.

[0125] Reference Figure 12A , the first pixel PX1, the second pixel PX2 and the third pixel PX3 are repeatedly arranged, and each of the first pixel PX1, the second pixel PX2 and the third pixel PX3 may include a photoelectric conversion unit 10 and a pixel circuit unit 20. Because the structures of the first pixel PX1, the second pixel PX2 and the third pixel PX3 are the same as those of the first pixel PX1, the second pixel PX2 and the third pixel PX3 Figure 7B The structures of the pixels PX are similar, so for the sake of brevity, their repeated description will be omitted.

[0126] The first pixel PX1 , the second pixel PX2 , and the third pixel PX3 may include color filters 12 having different colors, respectively.

[0127] For example, the first color filter 12a, the second color filter 12b, and the third color filter 12c included in the first pixel PX1, the second pixel PX2, and the third pixel PX3, respectively, may correspond to a red color filter, a green color filter, and a blue color filter, respectively. Therefore, the first pixel PX1, the second pixel PX2, and the third pixel PX3 may output sensing signals corresponding to red, green, and blue, respectively. However, the embodiment is not limited thereto, and in some embodiments, the first pixel PX1, the second pixel PX2, and the third pixel PX3 may correspond to another combination of colors. The pixel circuit unit 20 may include a pixel circuit ( Figure 2 PXC or Figure 9 PXCa), a load resistor (eg, a first load resistor R included in the first pixel PX1, the second pixel PX2, and the third pixel PX3) L 1. Second load resistor R L 2 and the third load resistor R L 3) can be formed in the corresponding pixel areas respectively. For example, the first load resistor R L 1. Second load resistor R L 2 and the third load resistor R L 3 may be formed in regions vertically overlapping the first pixel region PXAR1, the second pixel region PXAR2, and the third pixel region PXAR3 in the substrate 210, respectively.

[0128] Reference Figure 12B , the first pixel PX1 and the second pixel PX2 may be repeatedly arranged, and each of the first pixel PX1 and the second pixel PX2 may have a multilayer structure in which a plurality of photoelectric conversion units (eg, the first photoelectric conversion unit 10a and the second photoelectric conversion unit 10b) are vertically stacked.

[0129] The first photoelectric conversion unit 10a of the first pixel PX1 and the second pixel PX2 may include a first photoelectric conversion device PE1, which may include, for example, an organic photodiode. In some embodiments, the first photoelectric conversion device PE1 may convert a component in a specific color band (e.g., a green light signal) from the light signal collected by the microlens 11 into photocharges.

[0130] The second photoelectric conversion unit 10b of the first pixel PX1 and the second pixel PX2 may include a color filter 12 and a second photoelectric conversion device PE2. In some embodiments, the second photoelectric conversion device PE2 may include a photodiode PD, and the first pixel PX1 and the second pixel PX2 may each include a color filter 12 having a different color. For example, the first color filter 12a included in the first pixel PX1 may be a red filter, and the second color filter 12b included in the second pixel PX2 may be a blue filter. Therefore, the first pixel PX1 may output a sensing signal corresponding to green and red, and the second pixel PX2 may output a sensing signal corresponding to green and blue.

[0131] The pixel circuit unit 20b of each of the first pixel PX1 and the second pixel PX2 may include a first pixel circuit PXC1 and a second pixel circuit PXC2 corresponding to the first photoelectric conversion unit 10a and the second photoelectric conversion unit 10b, respectively. The first pixel circuit PXC1 may be Figure 2 The pixel circuit PXC or Figure 9 The load resistor (eg, the first load resistor R L 1 and the second load resistor R L 2) They may be formed in regions vertically overlapping with the first pixel regions PXAR1 a and PXAR2 a in the substrate 120 , respectively.

[0132] The second pixel circuit PXC2 may be the same as or different from the first pixel circuit PXC1. When the second pixel circuit PXC2 is the same as the first pixel circuit PXC1, load resistors may be formed in the second pixel regions PXAR1b and PXAR2b of the first and second pixels PX1 and PX2, respectively.

[0133] Reference Figure 12C , the pixels PX may be repeatedly arranged, and the pixels PX may have a multilayer structure in which a plurality of photoelectric conversion units (eg, a first photoelectric conversion unit 10a, a second photoelectric conversion unit 10b, and a third photoelectric conversion unit 10c) are vertically stacked.

[0134] Each of the first photoelectric conversion unit 10a, the second photoelectric conversion unit 10b, and the third photoelectric conversion unit 10c can be implemented by an organic photodiode and can convert light signals in different color bands into photocharges. Therefore, the pixel PX can output sensing signals corresponding to three colors.

[0135] The pixel circuit unit 20d may include first, second, and third pixel circuits PXC1, PXC2, and PXC3 corresponding to the first, second, and third photoelectric conversion units 10a, 10b, and 10c, respectively.

[0136] At least one of the first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3 may be Figure 2 The pixel circuit PXC or Figure 9 The pixel circuit PXCa is implemented by the pixel circuit PXCa and can be formed in corresponding pixel areas among the first pixel area PXARa, the second pixel area PXARb and the third pixel area PXARc included in the pixel area PXAR of the pixel PX. In some embodiments, the first pixel circuit PXC1, the second pixel circuit PXC2 and the third pixel circuit PXC3 can be Figure 2 The pixel circuit PXC or Figure 9 The load resistors (eg, the load resistors R included in the first pixel circuit PXC1, the second pixel circuit PXC2, and the third pixel circuit PXC3, respectively) are implemented by the pixel circuit PXCa. L a、R L b and R L c) may be formed in regions vertically overlapping the first pixel region PXARa, the second pixel region PXARb, and the third pixel region PXARc in the substrate 120, respectively.

[0137] Figure 13A and Figure 13B A stacked structure of an image sensor according to example embodiments is shown.

[0138] Figure 13A This is an exploded perspective view of the image sensor. Figure 13B is a plan view of an image sensor.

[0139] Reference Figure 13A and Figure 13B , the image sensor 100a may have a structure in which a first chip CH1 and a second chip CH2 are stacked. In the first chip CH1, a pixel array ( Figure 1 A pixel core (e.g., at least one photoelectric conversion device PE and at least one pixel circuit PXC) of each of the plurality of pixels PX in the chip 110) is formed, and in the second chip CH2, a logic circuit (e.g., a row driver 120, a reading circuit 130, a ramp signal generator 140, and a timing controller 150) may be formed.

[0140] like Figure 13BAs shown in FIG, the first chip CH1 and the second chip CH2 may include an active area AA and a logic area LA arranged in their central areas, respectively, and may also include peripheral areas PERR and PEI arranged in their outer areas, respectively. In the active area AA of the first chip CH1, the photoelectric conversion device PE and the pixel circuit PXC may be arranged in a 2D array structure. In the logic area LA of the second chip CH2, a logic circuit may be arranged.

[0141] In the peripheral regions PERR and PEI of the first chip CH1 and the second chip CH2, the through-holes TV may be arranged to extend in a third direction (Z direction). The first chip CH1 and the second chip CH2 may be electrically coupled to each other via the through-holes TV. In the peripheral region PERR of the first chip CH1, wiring extending in the first direction (X direction) or the second direction (Y direction) and vertical contacts may also be formed. In the wiring layer of the second chip CH2, a large number of wiring extending in the first direction (X direction) and the second direction (Y direction) may also be arranged, and these wirings may be connected to the logic circuit.

[0142] Although a structure has been described in which the first chip CH1 is electrically coupled to the second chip CH2 via the through-hole TV, the embodiments are not limited thereto, and in some embodiments, for example, the electrical coupling of the first chip CH1 and the second chip CH2 may be achieved through various coupling structures (such as Cu-Cu coupling, coupling of a through-hole and a Cu pad, coupling of a through-hole and an external connection terminal, or coupling through an integral through-hole).

[0143] Figure 14 is a block diagram of an electronic device including a plurality of camera modules to which image sensors according to example embodiments are applied. Figure 15 According to the embodiment Figure 14 Detailed block diagram of multiple camera modules.

[0144] Reference Figure 14 , the electronic device 1000 may include a camera module group 1100 , an application processor 1200 , a power management integrated circuit (PMIC) 1300 , and an external memory 1400 .

[0145] The camera module group 1100 may include a plurality of camera modules 1100a, 1100b, and 1100c. Figure 14 An embodiment in which three camera modules 1100a, 1100b, and 1100c are arranged is shown, but the embodiment is not limited thereto. In some embodiments, the camera module group 1100 can be modified to include only two camera modules. In addition, in some embodiments, the camera module group 1100 can be modified to include n camera modules (where n is a natural number of 4 or greater).

[0146] In the following, although reference will be made to Figure 15 The configuration of the camera module 1100 b is described in more detail, but the following description may also be equally applied to the other camera modules 1100 a and 1100 c according to the embodiments.

[0147] Reference Figure 15 , the camera module 1100 b may include a prism 1105 , an optical path bending element (OPFE) 1110 , an actuator 1130 , an image sensing device 1140 , and a storage device 1150 .

[0148] The prism 1105 may include a reflective surface 1107 of a light-reflective material, and thus may change the path of light L incident from the outside thereof.

[0149] In some embodiments, the prism 1105 can change the path of light L incident in a first direction (X direction) to a second direction (Y direction) perpendicular to the first direction (X direction). Alternatively, the prism 1105 can change the path of light L incident in the first direction (X direction) to a second direction (Y direction) perpendicular to the first direction (X direction) by rotating the reflective surface 1107 of the light-reflecting material in the A direction about the central axis 1106 or by rotating the central axis 1106 in the B direction. The OPFE 1110 can also move in a third direction (Z direction) perpendicular to the first direction (X direction) and the second direction (Y direction).

[0150] In some embodiments, as Figure 15 As shown in , although the prism 1105 may have a maximum rotation angle of 15 degrees or less in the positive (+) A direction and a maximum rotation angle of more than 15 degrees in the negative (-) A direction, embodiments of the inventive concept are not limited thereto.

[0151] In some embodiments, prism 1105 can move up to about 20 degrees in the +B or -B direction, about 10 degrees to about 20 degrees, or about 15 degrees to about 20 degrees, where the maximum angle of movement in the +B direction can be equal to the maximum angle of movement in the -B direction, or can be similar to the maximum angle of movement in the -B direction with a difference of about 1 degree between them.

[0152] In some embodiments, the prism 1105 may move the reflective surface 1107 of the light reflective material in a third direction (eg, a Z direction) parallel to the extension direction of the central axis 1106 .

[0153] The OPFE 1110 may include an optical lens including a group of m optical lenses (where m is a natural number). The m optical lenses may be moved in a second direction (Y direction) to change the optical zoom ratio of the camera module 1100b. For example, assuming that the basic optical zoom ratio of the camera module 1100b is Z, by moving the m optical lenses included in the OPFE 1110, the optical zoom ratio of the camera module 1100b may be changed to 3Z, 5Z, or 5Z or more.

[0154] The actuator 1130 can move the OPFE 1110 or the optical lens to a specific position. For example, the actuator 1130 can adjust the position of the optical lens so that the image sensor 1142 is positioned at a position corresponding to the focal length of the optical lens for accurate sensing.

[0155] The image sensing device 1140 may include an image sensor 1142, a control logic 1144, and a memory 1146. The image sensor 1142 may sense an image of a sensing object by using light L provided through an optical lens. The image sensor 1142 may be an image sensor of one of the above-described embodiments. Figure 1 In the image sensor 100, since each of the plurality of pixels included in the pixel array performs a feedback reset operation, reset noise can be reduced, and since a load device (which supplies a bias current to a feedback amplifier that operates at the time of feedback reset) is arranged inside the pixel, reset time can be reduced.

[0156] The control logic 1144 may control the overall operation of the camera module 1100b. For example, the control logic 1144 may control the operation of the camera module 1100b according to a control signal provided through the control signal line CSLb.

[0157] The memory 1146 may store information required for the operation of the camera module 1100b (such as calibration data 1147). The calibration data 1147 may include information used by the camera module 1100b to generate image data using light L provided from outside the camera module 1100b. The calibration data 1147 may include, for example, information on the rotation angle, information on the focal length, information on the optical axis, and the like, as described above. When the camera module 1100b is implemented as a multi-state camera in which the focal length changes depending on the position of the optical lens, the calibration data 1147 may include a focal length value for each position (or each state) of the optical lens and information related to autofocus.

[0158] The storage device 1150 may store image data sensed by the image sensor 1142. The storage device 1150 may be disposed outside the image sensing device 1140 and may be implemented in a form in which the storage device 1150 and a sensor chip constituting the image sensing device 1140 are stacked. In some embodiments, the storage device 1150 may be implemented by an electrically erasable programmable read-only memory (EEPROM), but the embodiment is not limited thereto.

[0159] Combined with reference Figure 14 and Figure 15 In some embodiments, each of the plurality of camera modules 1100a, 1100b, and 1100c may include an actuator 1130. Therefore, each of the plurality of camera modules 1100a, 1100b, and 1100c may include the same or different calibration data 1147 depending on the operation of the actuator 1130 included therein.

[0160] In some embodiments, among the multiple camera modules 1100a, 1100b and 1100c, one camera module (e.g., 1100b) may be a bent lens type camera module including the prism 1105 and OPFE 1110 described above, and the remaining camera modules (e.g., 1100a and 1100b) may be vertical type camera modules that do not include the prism 1105 and OPFE 1110, but the embodiments are not limited thereto.

[0161] In some embodiments, among the plurality of camera modules 1100a, 1100b, and 1100c, one camera module (e.g., 1100c) may be a vertical type depth camera that extracts depth information, for example, by using infrared (IR). In this case, the application processor 1200 may generate a 3D depth image by combining image data provided by such a depth camera with image data provided by another camera module (e.g., 1100a or 1100b).

[0162] In some embodiments, at least two camera modules (e.g., 1100a and 1100b) among the plurality of camera modules 1100a, 1100b, and 1100c may have different fields of view from each other. In this case, for example, although the optical lenses of at least two camera modules (e.g., 1100a and 1100b) among the plurality of camera modules 1100a, 1100b, and 1100c may be different from each other, the present inventive concept is not limited thereto.

[0163] In addition, in some embodiments, the plurality of camera modules 1100a, 1100b, and 1100c may have different fields of view, respectively. In this case, although the optical lenses respectively included in the plurality of camera modules 1100a, 1100b, and 1100c may also be different from each other, the embodiment is not limited thereto.

[0164] In some embodiments, the plurality of camera modules 1100a, 1100b, and 1100c may be arranged to be physically separated from one another. That is, the plurality of camera modules 1100a, 1100b, and 1100c do not divide and use the sensing area of ​​the image sensor 1142. Instead, the image sensor 1142 may be independently arranged within each of the plurality of camera modules 1100a, 1100b, and 1100c.

[0165] Return to reference Figure 14 , the application processor 1200 may include an image processing device 1210, a memory controller 1220, and an internal memory 1230. The application processor 1200 may be implemented separately from the plurality of camera modules 1100a, 1100b, and 1100c. For example, the application processor 1200 and the plurality of camera modules 1100a, 1100b, and 1100c may be implemented by separate semiconductor chips.

[0166] The image processing device 1210 may include a plurality of sub-image processors 1212 a , 1212 b , and 1212 c , an image generator 1214 , and a camera module controller 1216 .

[0167] The image processing device 1210 may include a plurality of sub-image processors 1212 a , 1212 b , and 1212 c , the number of which is the same as the number of the camera modules 1100 a , 1100 b , and 1100 c .

[0168] The plurality of image data generated by the camera modules 1100a, 1100b, and 1100c can be provided to the corresponding sub-image processors 1212a, 1212b, and 1212c, respectively, via image signal lines ISLa, ISLb, and ISLc separated from each other. For example, the image data generated by the camera module 1100a can be provided to the sub-image processor 1212a via the image signal line ISLa, the image data generated by the camera module 1100b can be provided to the sub-image processor 1212b via the image signal line ISLb, and the image data generated by the camera module 1100c can be provided to the sub-image processor 1212c via the image signal line ISLc. Although such image data transmission can be performed using, for example, a camera serial interface (CSI) based on the mobile industry processor interface (MIPI), embodiments are not limited thereto.

[0169] In some embodiments, one sub-image processor may be arranged to correspond to multiple camera modules. For example, sub-image processor 1212a and sub-image processor 1212c may be implemented as integrated into one sub-image processor, rather than as Figure 14 , the pieces of image data provided by the camera module 1100a and the camera module 1100c may be selected by a selection device (eg, a multiplexer) or the like and then provided to the integrated sub-image processor.

[0170] The image data provided to each of the sub-image processors 1212a, 1212b, and 1212c may be provided to the image generator 1214. The image generator 1214 may generate an output image by using the image data provided by each of the sub-image processors 1212a, 1212b, and 1212c according to image generation information or a mode signal.

[0171] Specifically, based on the image generation information or the mode signal, the image generator 1214 can generate an output image by combining at least some of the multiple pieces of image data generated by the camera modules 1100a, 1100b, and 1100c, each having a different field of view. Alternatively, based on the image generation information or the mode signal, the image generator 1214 can generate an output image by selecting one of the multiple pieces of image data generated by the camera modules 1100a, 1100b, and 1100c, each having a different field of view.

[0172] In some embodiments, the image generation information may include a zoom signal (or zoom factor). Additionally, in some embodiments, the mode signal may be a signal based on a mode selected by a user, for example.

[0173] When the image generation information is a zoom signal (zoom factor) and the camera modules 1100a, 1100b, and 1100c have different fields of view, the image generator 1214 may perform different operations according to the type of the zoom signal. For example, when the zoom signal is a first signal, the image data output from the camera module 1100a is merged with the image data output from the camera module 1100c, and then an output image may be generated by using the merged image signal and the image data output from the camera module 1100b and not used for merging. When the zoom signal is a second signal different from the first signal, the image generator 1214 does not perform such image data merging and may generate an output image by selecting one of the multiple image data output from the camera modules 1100a, 1100b, and 1100c, respectively. However, the embodiment is not limited thereto, and the method for processing image data may be modified and implemented in any manner as needed.

[0174] In some embodiments, the image generator 1214 may receive multiple pieces of image data having different exposure times from each other from at least one of the multiple sub-image processors 1212a, 1212b, and 1212c, and perform high dynamic range (HDR) processing on the multiple pieces of image data to generate merged image data having an increased dynamic range.

[0175] The camera module controller 1216 may provide control signals to each of the camera modules 1100a, 1100b, and 1100c. The control signals generated by the camera module controller 1216 may be provided to the corresponding camera modules 1100a, 1100b, and 1100c through separate control signal lines CSLa, CSLb, and CSLc, respectively.

[0176] One of the plurality of camera modules 1100a, 1100b, and 1100c can be designated as a master camera (e.g., 1100b) based on image generation information including a zoom signal or a mode signal, and the remaining camera modules (e.g., 1100a and 1100c) can be designated as slave cameras. Such information can be included in a control signal and provided to the corresponding camera modules 1100a, 1100b, and 1100c via separate control signal lines CSLa, CSLb, and CSLc, respectively.

[0177] The camera modules operated as the master camera and the slave camera can be changed according to the zoom factor or the operating mode signal. For example, when the field of view of camera module 1100a is wider than that of camera module 1100b and has a low zoom factor, camera module 1100b can be operated as the master camera and camera module 1100a can be operated as the slave camera. Conversely, when camera module 1100a has a high zoom factor, camera module 1100a can be operated as the master camera and camera module 1100b can be operated as the slave camera.

[0178] In some embodiments, the control signal provided from camera module controller 1216 to each of camera modules 1100a, 1100b, and 1100c may include a synchronization enable signal. For example, when camera module 1100b is the master camera and camera modules 1100a and 1100c are slave cameras, camera module controller 1216 may transmit the synchronization enable signal to camera module 1100b. Camera module 1100b, to which the synchronization enable signal is provided, may generate a synchronization signal based on the provided synchronization enable signal and may provide the generated synchronization signal to camera modules 1100a and 1100c via a synchronization signal line SSL. Camera module 1100b may be synchronized with camera modules 1100a and 1100c via the synchronization signal, thereby allowing multiple pieces of image data to be transmitted to application processor 1200.

[0179] In some embodiments, the control signal provided from the camera module controller 1216 to each of the camera modules 1100a, 1100b, and 1100c may include mode information according to the mode signal. Based on the mode information, the plurality of camera modules 1100a, 1100b, and 1100c may operate in a first operating mode and a second operating mode with respect to the sensing rate.

[0180] In the first operating mode, each of the plurality of camera modules 1100a, 1100b, and 1100c may generate an image signal at a first rate (e.g., generate an image signal having a first frame rate), encode the image signal at a second rate higher than the first rate (e.g., encode the image signal into an image signal having a second frame rate higher than the first frame rate), and transmit the encoded image signal to the application processor 1200. Here, the second rate may be 30 times or less than the first rate.

[0181] Application processor 1200 may store the received image signal (i.e., the encoded image signal) in memory 1230 included in application processor 1200 or in storage device 1400 external to application processor 1200, then read the encoded image signal from memory 1230 or storage device 1400 and decode the read image signal, and then display image data generated based on the decoded image signal. For example, a corresponding sub-image processor among the multiple sub-image processors 1212a, 1212b, and 1212c of image processing device 1210 may perform decoding and may perform image processing on the decoded image signal.

[0182] In the second operating mode, each of the plurality of camera modules 1100a, 1100b, and 1100c may generate an image signal at a third rate lower than the first rate (e.g., generate an image signal having a third frame rate lower than the first frame rate), and may transmit the image signal to the application processor 1200. The image signal provided to the application processor 1200 may be an unencoded signal. The application processor 1200 may perform image processing on the received image signal, or may store the image signal in the memory 1230 or the storage device 1400.

[0183] The PMIC 1300 may provide power (e.g., power supply voltage) to each of the plurality of camera modules 1100a, 1100b, and 1100c. For example, under the control of the application processor 1200, the PMIC 1300 may supply a first power to the camera module 1100a via a power signal line PSLa, a second power to the camera module 1100b via a power signal line PSLb, and a third power to the camera module 1100c via a power signal line PSLc.

[0184] In response to a power control signal PCON from the application processor 1200, the PMIC 1300 can generate power corresponding to each of the multiple camera modules 1100a, 1100b, and 1100c and adjust the power level. The power control signal PCON may include a power adjustment signal for each operating mode of the multiple camera modules 1100a, 1100b, and 1100c. For example, the operating mode may include a low power mode. Here, the power control signal PCON may include information about the camera module operating in the low power mode and information about the power level set in the low power mode. The multiple power levels provided to the multiple camera modules 1100a, 1100b, and 1100c can be equal to or different from each other. In addition, the power level can be dynamically changed.

[0185] While various example embodiments have been particularly shown and described with reference to the drawings, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An image sensor comprising a plurality of pixels arranged in a matrix and converting optical signals into electrical signals, each of the plurality of pixels comprising: a photoelectric conversion device configured to convert the optical signal into an electric charge; a floating diffusion node connected to the photoelectric conversion device and storing the charge; an amplifier configured to inversely amplify a voltage of the floating diffusion node, output a first output signal through a first node based on the inversely amplified voltage in a reset period, and output a second output signal through a second node different from the first node based on the inversely amplified voltage in a signal output period; as well as a reset switching device configured to be turned on during the reset period and to provide the first output signal of the amplifier to the floating diffusion node, The amplifier includes a load resistor configured to provide a first bias current during the reset period.

2. The image sensor according to claim 1, wherein The plurality of pixels are respectively arranged in a plurality of pixel areas, and The floating diffusion node, the amplifier, and the load resistor included in one pixel among the plurality of pixels are arranged in a pixel region corresponding to the one pixel among the plurality of pixel regions.

3. The image sensor according to claim 2, wherein: The image sensor further includes a substrate, and The load resistor included in the one pixel includes a well resistor provided in the substrate and arranged in a region of the substrate vertically overlapping a pixel region corresponding to the one pixel.

4. The image sensor according to claim 3, wherein: The well resistor is disposed adjacent to at least one of the four sides of the region.

5. The image sensor according to claim 3, wherein: The well resistors are arranged along sides of the region.

6. The image sensor according to claim 1, wherein The amplifier is further configured to generate the second output signal based on a second bias current during the signal output period, and The second output signal is provided to the analog-to-digital conversion circuit through a column line.

7. The image sensor according to claim 1, wherein The amplifier includes a drive transistor and a plurality of selection transistors, the reset switch device includes a reset transistor, and One end of the reset transistor and a gate terminal of the drive transistor are connected to the floating diffusion node.

8. The image sensor according to claim 7, wherein: A pixel driving voltage or a ground voltage is applied to a first terminal of the driving transistor, and the other end of the reset transistor is connected to a second terminal of the driving transistor.

9. The image sensor according to claim 1, wherein: The photoelectric conversion device includes an organic photodiode.

10. A pixel array of an image sensor, the pixel array comprising: a plurality of pixels, each of the plurality of pixels comprising: microlenses; a first photoelectric conversion device disposed below the microlens and configured to generate first photocharges from a light signal incident on the first photoelectric conversion device; and a first pixel circuit arranged in a pixel region vertically overlapping the microlens and vertically below the first photoelectric conversion device, the first pixel circuit being configured to output a first sensing signal based on the amount of the first photocharge; Wherein, the first pixel circuit includes: a floating diffusion node storing the first photocharge; an amplifier comprising a plurality of switching devices, the amplifier being configured to amplify a voltage of the floating diffusion node; a resistor arrangement configured to provide a bias current to the amplifier during a reset period, A reset switching device is configured to provide the first output signal of the amplifier to the floating diffusion node during the reset period.

11. The pixel array according to claim 10, wherein: The pixel array includes a substrate including a plurality of pixel areas respectively corresponding to the plurality of pixels, and The first pixel circuit is arranged in a pixel area corresponding to a pixel of the first pixel circuit in the substrate, and The resistor arrangement of the first pixel circuit is arranged adjacent to a side of the pixel area.

12. The pixel array according to claim 11, wherein: The resistor device is formed by doping a portion of a p-type well region in the pixel area with n-type impurities.

13. The pixel array according to claim 10, wherein: The resistor arrangement is arranged inside the substrate.

14. The pixel array according to claim 10, wherein: Each of the plurality of pixels further includes a through electrode connecting the first photoelectric conversion device to the floating diffusion node and extending in a direction perpendicular to the substrate.

15. The pixel array according to claim 10, wherein: The plurality of switch devices include: a drive transistor having a gate terminal connected to the floating diffusion node; a first switching transistor comprising a first terminal connected to one end of the resistor arrangement and a second terminal connected to the first terminal of the drive transistor; and a second switching transistor comprising a first terminal connected to the first terminal of the drive transistor and a second terminal connected to a column line, The reset switching device includes a reset transistor including a first terminal connected to the first terminal of the drive transistor and a second terminal connected to the floating diffusion node.

16. The pixel array according to claim 15, wherein: The plurality of switch devices further comprises: a third switching transistor having a first terminal connected to a ground voltage and a second terminal connected to the second terminal of the driving transistor; and A fourth switching transistor has a first terminal connected to the pixel driving voltage and a second terminal connected to the second terminal of the driving transistor.

17. An image sensor comprising: substrate; A pixel array comprising a plurality of pixels, each pixel of the plurality of pixels comprising: a pixel circuit formed in a pixel region corresponding to the pixel in the substrate; and a pixel conversion device arranged on the substrate to vertically overlap the pixel circuit, Wherein, the pixel circuit includes: floating diffusion node; an amplifier configured to amplify a voltage of the floating diffusion node and including a load resistor and a plurality of switching devices, the load resistor being arranged in the pixel region and configured to provide a bias current in a reset period; A reset switching device is configured to provide the first output signal of the amplifier to the floating diffusion node during the reset period.

18. The image sensor according to claim 17, wherein: The load resistor is arranged adjacent to at least one of four sides of the pixel region.

19. The image sensor according to claim 17, wherein: The load resistor is a well resistor formed by n-type impurities in a p-type well region.

20. The image sensor according to claim 17, wherein The plurality of switching devices are arranged at a center of the pixel area, and the load resistor is arranged between the plurality of switching devices and a side of the pixel area.

Images